Introduce files for new e1000 driver
authorMarty Connor <mdc@etherboot.org>
Sun, 18 Nov 2007 15:31:00 +0000 (10:31 -0500)
committerMarty Connor <mdc@etherboot.org>
Sun, 18 Nov 2007 15:31:00 +0000 (10:31 -0500)
src/drivers/net/e1000.c [deleted file]
src/drivers/net/e1000/e1000.h [new file with mode: 0644]
src/drivers/net/e1000/e1000_hw.c [new file with mode: 0644]
src/drivers/net/e1000/e1000_hw.h [new file with mode: 0644]
src/drivers/net/e1000/e1000_main.c [new file with mode: 0644]
src/drivers/net/e1000/e1000_osdep.h [new file with mode: 0644]
src/drivers/net/e1000_hw.h [deleted file]

diff --git a/src/drivers/net/e1000.c b/src/drivers/net/e1000.c
deleted file mode 100644 (file)
index 8f8d3db..0000000
+++ /dev/null
@@ -1,3742 +0,0 @@
-/**************************************************************************
-Etherboot -  BOOTP/TFTP Bootstrap Program
-Inter Pro 1000 for Etherboot
-Drivers are port from Intel's Linux driver e1000-4.3.15
-
-***************************************************************************/
-/*******************************************************************************
-
-  
-  Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
-  
-  This program is free software; you can redistribute it and/or modify it 
-  under the terms of the GNU General Public License as published by the Free 
-  Software Foundation; either version 2 of the License, or (at your option) 
-  any later version.
-  
-  This program is distributed in the hope that it will be useful, but WITHOUT 
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for 
-  more details.
-  
-  You should have received a copy of the GNU General Public License along with
-  this program; if not, write to the Free Software Foundation, Inc., 59 
-  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
-  
-  The full GNU General Public License is included in this distribution in the
-  file called LICENSE.
-  
-  Contact Information:
-  Linux NICS <linux.nics@intel.com>
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
-
-*******************************************************************************/
-/*
- *  Copyright (C) Archway Digital Solutions.
- *
- *  written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
- *  2/9/2002
- *
- *  Copyright (C) Linux Networx.
- *  Massive upgrade to work with the new intel gigabit NICs.
- *  <ebiederman at lnxi dot com>
- *
- *  Support for 82541ei & 82547ei chips from Intel's Linux driver 5.1.13 added by
- *  Georg Baum <gbaum@users.sf.net>, sponsored by PetaMem GmbH and linkLINE Communications, Inc.
- *
- *  01/2004: Updated to Linux driver 5.2.22 by Georg Baum <gbaum@users.sf.net>
- */
-
-/* to get some global routines like printf */
-#include "etherboot.h"
-/* to get the interface to the body of the program */
-#include "nic.h"
-/* to get the PCI support functions, if this is a PCI NIC */
-#include <gpxe/pci.h>
-#include "timer.h"
-
-typedef unsigned char *dma_addr_t;
-
-typedef enum {
-       FALSE = 0,
-       TRUE = 1
-} boolean_t;
-
-#define DEBUG 0
-
-
-/* Some pieces of code are disabled with #if 0 ... #endif.
- * They are not deleted to show where the etherboot driver differs
- * from the linux driver below the function level.
- * Some member variables of the hw struct have been eliminated
- * and the corresponding inplace checks inserted instead.
- * Pieces such as LED handling that we definitely don't need are deleted.
- *
- * Please keep the function ordering so that it is easy to produce diffs
- * against the linux driver.
- *
- * The following defines should not be needed normally,
- * but may be helpful for debugging purposes. */
-
-/* Define this if you want to program the transmission control register
- * the way the Linux driver does it. */
-#undef LINUX_DRIVER_TCTL
-
-/* Define this to behave more like the Linux driver. */
-#undef LINUX_DRIVER
-
-#include "e1000_hw.h"
-
-/* NIC specific static variables go here */
-static struct nic_operations e1000_operations;
-
-static struct e1000_hw hw;
-
-struct {
-       char tx_pool[128 + 16];
-       char rx_pool[128 + 16];
-       char packet[2096];
-} e1000_bufs __shared;
-
-static struct e1000_tx_desc *tx_base;
-static struct e1000_rx_desc *rx_base;
-
-static int tx_tail;
-static int rx_tail, rx_last;
-
-/* Function forward declarations */
-static int e1000_setup_link(struct e1000_hw *hw);
-static int e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
-static int e1000_setup_copper_link(struct e1000_hw *hw);
-static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
-static void e1000_config_collision_dist(struct e1000_hw *hw);
-static int e1000_config_mac_to_phy(struct e1000_hw *hw);
-static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
-static int e1000_check_for_link(struct e1000_hw *hw);
-static int e1000_wait_autoneg(struct e1000_hw *hw);
-static void e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed, uint16_t *duplex);
-static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
-static int e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
-static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data);
-static int e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data);
-static void e1000_phy_hw_reset(struct e1000_hw *hw);
-static int e1000_phy_reset(struct e1000_hw *hw);
-static int e1000_detect_gig_phy(struct e1000_hw *hw);
-static int e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
-static void e1000_init_rx_addrs(struct e1000_hw *hw);
-static void e1000_clear_vfta(struct e1000_hw *hw);
-
-/* Printing macros... */
-
-#define E1000_ERR(args...) printf("e1000: " args)
-
-#if DEBUG >= 3
-#define E1000_DBG(args...) printf("e1000: " args)
-#else
-#define E1000_DBG(args...)
-#endif
-
-#define MSGOUT(S, A, B)     printk(S "\n", A, B)
-#if DEBUG >= 2
-#define DEBUGFUNC(F)        DEBUGOUT(F "\n");
-#else
-#define DEBUGFUNC(F)
-#endif
-#if DEBUG >= 1
-#define DEBUGOUT(S) printf(S)
-#define DEBUGOUT1(S,A) printf(S,A)
-#define DEBUGOUT2(S,A,B) printf(S,A,B)
-#define DEBUGOUT3(S,A,B,C) printf(S,A,B,C)
-#define DEBUGOUT7(S,A,B,C,D,E,F,G) printf(S,A,B,C,D,E,F,G)
-#else
-#define DEBUGOUT(S)
-#define DEBUGOUT1(S,A)
-#define DEBUGOUT2(S,A,B)
-#define DEBUGOUT3(S,A,B,C)
-#define DEBUGOUT7(S,A,B,C,D,E,F,G)
-#endif
-
-#define E1000_WRITE_REG(a, reg, value) ( \
-    ((a)->mac_type >= e1000_82543) ? \
-        (writel((value), ((a)->hw_addr + E1000_##reg))) : \
-        (writel((value), ((a)->hw_addr + E1000_82542_##reg))))
-
-#define E1000_READ_REG(a, reg) ( \
-    ((a)->mac_type >= e1000_82543) ? \
-        readl((a)->hw_addr + E1000_##reg) : \
-        readl((a)->hw_addr + E1000_82542_##reg))
-
-#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \
-    ((a)->mac_type >= e1000_82543) ? \
-        writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2))) : \
-        writel((value), ((a)->hw_addr + E1000_82542_##reg + ((offset) << 2))))
-
-#define E1000_READ_REG_ARRAY(a, reg, offset) ( \
-    ((a)->mac_type >= e1000_82543) ? \
-        readl((a)->hw_addr + E1000_##reg + ((offset) << 2)) : \
-        readl((a)->hw_addr + E1000_82542_##reg + ((offset) << 2)))
-
-#define E1000_WRITE_FLUSH(a) {uint32_t x; x = E1000_READ_REG(a, STATUS);}
-
-
-/******************************************************************************
- * Inline functions from e1000_main.c of the linux driver
- ******************************************************************************/
-
-#if 0
-static inline uint32_t
-e1000_io_read(struct e1000_hw *hw __unused, uint32_t port)
-{
-        return inl(port);
-}
-#endif
-
-static inline void
-e1000_io_write(struct e1000_hw *hw __unused, uint32_t port, uint32_t value)
-{
-        outl(value, port);
-}
-
-static inline void e1000_pci_set_mwi(struct e1000_hw *hw)
-{
-       pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
-}
-
-static inline void e1000_pci_clear_mwi(struct e1000_hw *hw)
-{
-       pci_write_config_word(hw->pdev, PCI_COMMAND,
-                             hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
-}
-
-
-/******************************************************************************
- * Inline functions from e1000_hw.c of the linux driver
- ******************************************************************************/
-
-/******************************************************************************
-* Writes a value to one of the devices registers using port I/O (as opposed to
-* memory mapped I/O). Only 82544 and newer devices support port I/O. *
-* hw - Struct containing variables accessed by shared code
-* offset - offset to write to * value - value to write
-*****************************************************************************/
-static inline void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset,
-                                     uint32_t value){
-       e1000_io_write(hw, hw->io_base, offset);
-       e1000_io_write(hw, hw->io_base + 4, value);
-}
-
-
-/******************************************************************************
- * Functions from e1000_hw.c of the linux driver
- ******************************************************************************/
-
-/******************************************************************************
- * Set the phy type member in the hw struct.
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
-static int32_t
-e1000_set_phy_type(struct e1000_hw *hw)
-{
-       DEBUGFUNC("e1000_set_phy_type");
-
-       switch(hw->phy_id) {
-       case M88E1000_E_PHY_ID:
-       case M88E1000_I_PHY_ID:
-       case M88E1011_I_PHY_ID:
-               hw->phy_type = e1000_phy_m88;
-               break;
-       case IGP01E1000_I_PHY_ID:
-               hw->phy_type = e1000_phy_igp;
-               break;
-       default:
-               /* Should never have loaded on this device */
-               hw->phy_type = e1000_phy_undefined;
-               return -E1000_ERR_PHY_TYPE;
-       }
-
-       return E1000_SUCCESS;
-}
-
-/******************************************************************************
- * IGP phy init script - initializes the GbE PHY
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
-static void
-e1000_phy_init_script(struct e1000_hw *hw)
-{
-       DEBUGFUNC("e1000_phy_init_script");
-
-#if 0
-       /* See e1000_sw_init() of the Linux driver */
-       if(hw->phy_init_script) {
-#else
-       if((hw->mac_type == e1000_82541) ||
-          (hw->mac_type == e1000_82547) ||
-          (hw->mac_type == e1000_82541_rev_2) ||
-          (hw->mac_type == e1000_82547_rev_2)) {
-#endif
-               mdelay(20);
-
-               e1000_write_phy_reg(hw,0x0000,0x0140);
-
-               mdelay(5);
-
-               if(hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547) {
-                       e1000_write_phy_reg(hw, 0x1F95, 0x0001);
-
-                       e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
-
-                       e1000_write_phy_reg(hw, 0x1F79, 0x0018);
-
-                       e1000_write_phy_reg(hw, 0x1F30, 0x1600);
-
-                       e1000_write_phy_reg(hw, 0x1F31, 0x0014);
-
-                       e1000_write_phy_reg(hw, 0x1F32, 0x161C);
-
-                       e1000_write_phy_reg(hw, 0x1F94, 0x0003);
-
-                       e1000_write_phy_reg(hw, 0x1F96, 0x003F);
-
-                       e1000_write_phy_reg(hw, 0x2010, 0x0008);
-               } else {
-                       e1000_write_phy_reg(hw, 0x1F73, 0x0099);
-               }
-
-               e1000_write_phy_reg(hw, 0x0000, 0x3300);
-
-
-               if(hw->mac_type == e1000_82547) {
-                       uint16_t fused, fine, coarse;
-
-                       /* Move to analog registers page */
-                       e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
-
-                       if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
-                               e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
-
-                               fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
-                               coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
-
-                               if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
-                                       coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
-                                       fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
-                               } else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
-                                       fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
-
-                               fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
-                                       (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
-                                       (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
-
-                               e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
-                               e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
-                                               IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
-                       }
-               }
-       }
-}
-
-/******************************************************************************
- * Set the mac type member in the hw struct.
- * 
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
-static int
-e1000_set_mac_type(struct e1000_hw *hw)
-{
-       DEBUGFUNC("e1000_set_mac_type");
-
-       switch (hw->device_id) {
-       case E1000_DEV_ID_82542:
-               switch (hw->revision_id) {
-               case E1000_82542_2_0_REV_ID:
-                       hw->mac_type = e1000_82542_rev2_0;
-                       break;
-               case E1000_82542_2_1_REV_ID:
-                       hw->mac_type = e1000_82542_rev2_1;
-                       break;
-               default:
-                       /* Invalid 82542 revision ID */
-                       return -E1000_ERR_MAC_TYPE;
-               }
-               break;
-       case E1000_DEV_ID_82543GC_FIBER:
-       case E1000_DEV_ID_82543GC_COPPER:
-               hw->mac_type = e1000_82543;
-               break;
-       case E1000_DEV_ID_82544EI_COPPER:
-       case E1000_DEV_ID_82544EI_FIBER:
-       case E1000_DEV_ID_82544GC_COPPER:
-       case E1000_DEV_ID_82544GC_LOM:
-               hw->mac_type = e1000_82544;
-               break;
-       case E1000_DEV_ID_82540EM:
-       case E1000_DEV_ID_82540EM_LOM:
-       case E1000_DEV_ID_82540EP:
-       case E1000_DEV_ID_82540EP_LOM:
-       case E1000_DEV_ID_82540EP_LP:
-               hw->mac_type = e1000_82540;
-               break;
-       case E1000_DEV_ID_82545EM_COPPER:
-       case E1000_DEV_ID_82545EM_FIBER:
-               hw->mac_type = e1000_82545;
-               break;
-       case E1000_DEV_ID_82545GM_COPPER:
-       case E1000_DEV_ID_82545GM_FIBER:
-       case E1000_DEV_ID_82545GM_SERDES:
-               hw->mac_type = e1000_82545_rev_3;
-               break;
-       case E1000_DEV_ID_82546EB_COPPER:
-       case E1000_DEV_ID_82546EB_FIBER:
-       case E1000_DEV_ID_82546EB_QUAD_COPPER:
-               hw->mac_type = e1000_82546;
-               break;
-       case E1000_DEV_ID_82546GB_COPPER:
-       case E1000_DEV_ID_82546GB_FIBER:
-       case E1000_DEV_ID_82546GB_SERDES:
-               hw->mac_type = e1000_82546_rev_3;
-               break;
-       case E1000_DEV_ID_82541EI:
-       case E1000_DEV_ID_82541EI_MOBILE:
-               hw->mac_type = e1000_82541;
-               break;
-       case E1000_DEV_ID_82541ER:
-       case E1000_DEV_ID_82541GI:
-       case E1000_DEV_ID_82541GI_MOBILE:
-               hw->mac_type = e1000_82541_rev_2;
-               break;
-       case E1000_DEV_ID_82547EI:
-               hw->mac_type = e1000_82547;
-               break;
-       case E1000_DEV_ID_82547GI:
-               hw->mac_type = e1000_82547_rev_2;
-               break;
-       default:
-               /* Should never have loaded on this device */
-               return -E1000_ERR_MAC_TYPE;
-       }
-
-       return E1000_SUCCESS;
-}
-
-/*****************************************************************************
- * Set media type and TBI compatibility.
- *
- * hw - Struct containing variables accessed by shared code
- * **************************************************************************/
-static void
-e1000_set_media_type(struct e1000_hw *hw)
-{
-       uint32_t status;
-
-       DEBUGFUNC("e1000_set_media_type");
-       
-       if(hw->mac_type != e1000_82543) {
-               /* tbi_compatibility is only valid on 82543 */
-               hw->tbi_compatibility_en = FALSE;
-       }
-
-       switch (hw->device_id) {
-               case E1000_DEV_ID_82545GM_SERDES:
-               case E1000_DEV_ID_82546GB_SERDES:
-                       hw->media_type = e1000_media_type_internal_serdes;
-                       break;
-               default:
-                       if(hw->mac_type >= e1000_82543) {
-                               status = E1000_READ_REG(hw, STATUS);
-                               if(status & E1000_STATUS_TBIMODE) {
-                                       hw->media_type = e1000_media_type_fiber;
-                                       /* tbi_compatibility not valid on fiber */
-                                       hw->tbi_compatibility_en = FALSE;
-                               } else {
-                                       hw->media_type = e1000_media_type_copper;
-                               }
-                       } else {
-                               /* This is an 82542 (fiber only) */
-                               hw->media_type = e1000_media_type_fiber;
-                       }
-       }
-}
-
-/******************************************************************************
- * Reset the transmit and receive units; mask and clear all interrupts.
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
-static void
-e1000_reset_hw(struct e1000_hw *hw)
-{
-       uint32_t ctrl;
-       uint32_t ctrl_ext;
-       uint32_t icr;
-       uint32_t manc;
-       
-       DEBUGFUNC("e1000_reset_hw");
-       
-       /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
-       if(hw->mac_type == e1000_82542_rev2_0) {
-               DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
-               e1000_pci_clear_mwi(hw);
-       }
-
-       /* Clear interrupt mask to stop board from generating interrupts */
-       DEBUGOUT("Masking off all interrupts\n");
-       E1000_WRITE_REG(hw, IMC, 0xffffffff);
-       
-       /* Disable the Transmit and Receive units.  Then delay to allow
-        * any pending transactions to complete before we hit the MAC with
-        * the global reset.
-        */
-       E1000_WRITE_REG(hw, RCTL, 0);
-       E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
-       E1000_WRITE_FLUSH(hw);
-
-       /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
-       hw->tbi_compatibility_on = FALSE;
-
-       /* Delay to allow any outstanding PCI transactions to complete before
-        * resetting the device
-        */ 
-       mdelay(10);
-
-       ctrl = E1000_READ_REG(hw, CTRL);
-
-       /* Must reset the PHY before resetting the MAC */
-       if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
-               E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
-               mdelay(5);
-       }
-
-       /* Issue a global reset to the MAC.  This will reset the chip's
-        * transmit, receive, DMA, and link units.  It will not effect
-        * the current PCI configuration.  The global reset bit is self-
-        * clearing, and should clear within a microsecond.
-        */
-       DEBUGOUT("Issuing a global reset to MAC\n");
-
-       switch(hw->mac_type) {
-               case e1000_82544:
-               case e1000_82540:
-               case e1000_82545:
-               case e1000_82546:
-               case e1000_82541:
-               case e1000_82541_rev_2:
-                       /* These controllers can't ack the 64-bit write when issuing the
-                        * reset, so use IO-mapping as a workaround to issue the reset */
-                       E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
-                       break;
-               case e1000_82545_rev_3:
-               case e1000_82546_rev_3:
-                       /* Reset is performed on a shadow of the control register */
-                       E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
-                       break;
-               default:
-                       E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
-                       break;
-       }
-
-       /* After MAC reset, force reload of EEPROM to restore power-on settings to
-        * device.  Later controllers reload the EEPROM automatically, so just wait
-        * for reload to complete.
-        */
-       switch(hw->mac_type) {
-               case e1000_82542_rev2_0:
-               case e1000_82542_rev2_1:
-               case e1000_82543:
-               case e1000_82544:
-                       /* Wait for reset to complete */
-                       udelay(10);
-                       ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
-                       ctrl_ext |= E1000_CTRL_EXT_EE_RST;
-                       E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
-                       E1000_WRITE_FLUSH(hw);
-                       /* Wait for EEPROM reload */
-                       mdelay(2);
-                       break;
-               case e1000_82541:
-               case e1000_82541_rev_2:
-               case e1000_82547:
-               case e1000_82547_rev_2:
-                       /* Wait for EEPROM reload */
-                       mdelay(20);
-                       break;
-               default:
-                       /* Wait for EEPROM reload (it happens automatically) */
-                       mdelay(5);
-                       break;
-       }
-
-       /* Disable HW ARPs on ASF enabled adapters */
-       if(hw->mac_type >= e1000_82540) {
-               manc = E1000_READ_REG(hw, MANC);
-               manc &= ~(E1000_MANC_ARP_EN);
-               E1000_WRITE_REG(hw, MANC, manc);
-       }
-
-       if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
-               e1000_phy_init_script(hw);
-       }
-
-       /* Clear interrupt mask to stop board from generating interrupts */
-       DEBUGOUT("Masking off all interrupts\n");
-       E1000_WRITE_REG(hw, IMC, 0xffffffff);
-       
-       /* Clear any pending interrupt events. */
-       icr = E1000_READ_REG(hw, ICR);
-
-       /* If MWI was previously enabled, reenable it. */
-       if(hw->mac_type == e1000_82542_rev2_0) {
-#ifdef LINUX_DRIVER
-               if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
-#endif
-                       e1000_pci_set_mwi(hw);
-       }
-}
-
-/******************************************************************************
- * Performs basic configuration of the adapter.
- *
- * hw - Struct containing variables accessed by shared code
- * 
- * Assumes that the controller has previously been reset and is in a 
- * post-reset uninitialized state. Initializes the receive address registers,
- * multicast table, and VLAN filter table. Calls routines to setup link
- * configuration and flow control settings. Clears all on-chip counters. Leaves
- * the transmit and receive units disabled and uninitialized.
- *****************************************************************************/
-static int
-e1000_init_hw(struct e1000_hw *hw)
-{
-       uint32_t ctrl, status;
-       uint32_t i;
-       int32_t ret_val;
-       uint16_t pcix_cmd_word;
-       uint16_t pcix_stat_hi_word;
-       uint16_t cmd_mmrbc;
-       uint16_t stat_mmrbc;
-       e1000_bus_type bus_type = e1000_bus_type_unknown;
-
-       DEBUGFUNC("e1000_init_hw");
-
-       /* Set the media type and TBI compatibility */
-       e1000_set_media_type(hw);
-
-       /* Disabling VLAN filtering. */
-       DEBUGOUT("Initializing the IEEE VLAN\n");
-       E1000_WRITE_REG(hw, VET, 0);
-       
-       e1000_clear_vfta(hw);
-       
-       /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
-       if(hw->mac_type == e1000_82542_rev2_0) {
-               DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
-               e1000_pci_clear_mwi(hw);
-               E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
-               E1000_WRITE_FLUSH(hw);
-               mdelay(5);
-       }
-       
-       /* Setup the receive address. This involves initializing all of the Receive
-        * Address Registers (RARs 0 - 15).
-        */
-       e1000_init_rx_addrs(hw);
-       
-       /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
-       if(hw->mac_type == e1000_82542_rev2_0) {
-               E1000_WRITE_REG(hw, RCTL, 0);
-               E1000_WRITE_FLUSH(hw);
-               mdelay(1);
-#ifdef LINUX_DRIVER
-               if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
-#endif
-                       e1000_pci_set_mwi(hw);
-       }
-       
-       /* Zero out the Multicast HASH table */
-       DEBUGOUT("Zeroing the MTA\n");
-       for(i = 0; i < E1000_MC_TBL_SIZE; i++)
-               E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
-       
-#if 0
-       /* Set the PCI priority bit correctly in the CTRL register.  This
-        * determines if the adapter gives priority to receives, or if it
-        * gives equal priority to transmits and receives.
-        */
-       if(hw->dma_fairness) {
-               ctrl = E1000_READ_REG(hw, CTRL);
-               E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
-       }
-#endif
-
-       switch(hw->mac_type) {
-               case e1000_82545_rev_3:
-               case e1000_82546_rev_3:
-                       break;
-               default:
-                       if (hw->mac_type >= e1000_82543) {
-                               /* See e1000_get_bus_info() of the Linux driver */
-                               status = E1000_READ_REG(hw, STATUS);
-                               bus_type = (status & E1000_STATUS_PCIX_MODE) ?
-                                       e1000_bus_type_pcix : e1000_bus_type_pci;
-                       }
-
-                       /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
-                       if(bus_type == e1000_bus_type_pcix) {
-                               pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
-                               pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
-                               cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
-                                       PCIX_COMMAND_MMRBC_SHIFT;
-                               stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
-                                       PCIX_STATUS_HI_MMRBC_SHIFT;
-                               if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
-                                       stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
-                               if(cmd_mmrbc > stat_mmrbc) {
-                                       pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
-                                       pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
-                                       pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER, pcix_cmd_word);
-                               }
-                       }
-                       break;
-       }
-
-       /* Call a subroutine to configure the link and setup flow control. */
-       ret_val = e1000_setup_link(hw);
-       
-       /* Set the transmit descriptor write-back policy */
-       if(hw->mac_type > e1000_82544) {
-               ctrl = E1000_READ_REG(hw, TXDCTL);
-               ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
-               E1000_WRITE_REG(hw, TXDCTL, ctrl);
-       }
-
-#if 0
-       /* Clear all of the statistics registers (clear on read).  It is
-        * important that we do this after we have tried to establish link
-        * because the symbol error count will increment wildly if there
-        * is no link.
-        */
-       e1000_clear_hw_cntrs(hw);
-#endif
-
-       return ret_val;
-}
-
-/******************************************************************************
- * Adjust SERDES output amplitude based on EEPROM setting.
- *
- * hw - Struct containing variables accessed by shared code.
- *****************************************************************************/
-static int32_t
-e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
-{
-       uint16_t eeprom_data;
-       int32_t  ret_val;
-
-       DEBUGFUNC("e1000_adjust_serdes_amplitude");
-
-       if(hw->media_type != e1000_media_type_internal_serdes)
-               return E1000_SUCCESS;
-
-       switch(hw->mac_type) {
-               case e1000_82545_rev_3:
-               case e1000_82546_rev_3:
-                       break;
-               default:
-                       return E1000_SUCCESS;
-       }
-
-       if ((ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,
-                                       &eeprom_data))) {
-               return ret_val;
-       }
-
-       if(eeprom_data != EEPROM_RESERVED_WORD) {
-               /* Adjust SERDES output amplitude only. */
-               eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
-               if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL,
-                                                 eeprom_data)))
-                       return ret_val;
-       }
-
-       return E1000_SUCCESS;
-}
-                                                                  
-/******************************************************************************
- * Configures flow control and link settings.
- * 
- * hw - Struct containing variables accessed by shared code
- * 
- * Determines which flow control settings to use. Calls the apropriate media-
- * specific link configuration function. Configures the flow control settings.
- * Assuming the adapter has a valid link partner, a valid link should be
- * established. Assumes the hardware has previously been reset and the 
- * transmitter and receiver are not enabled.
- *****************************************************************************/
-static int
-e1000_setup_link(struct e1000_hw *hw)
-{
-       uint32_t ctrl_ext;
-       int32_t ret_val;
-       uint16_t eeprom_data;
-
-       DEBUGFUNC("e1000_setup_link");
-       
-       /* Read and store word 0x0F of the EEPROM. This word contains bits
-        * that determine the hardware's default PAUSE (flow control) mode,
-        * a bit that determines whether the HW defaults to enabling or
-        * disabling auto-negotiation, and the direction of the
-        * SW defined pins. If there is no SW over-ride of the flow
-        * control setting, then the variable hw->fc will
-        * be initialized based on a value in the EEPROM.
-        */
-       if(e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data) < 0) {
-               DEBUGOUT("EEPROM Read Error\n");
-               return -E1000_ERR_EEPROM;
-       }
-       
-       if(hw->fc == e1000_fc_default) {
-               if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
-                       hw->fc = e1000_fc_none;
-               else if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 
-                       EEPROM_WORD0F_ASM_DIR)
-                       hw->fc = e1000_fc_tx_pause;
-               else
-                       hw->fc = e1000_fc_full;
-       }
-       
-       /* We want to save off the original Flow Control configuration just
-        * in case we get disconnected and then reconnected into a different
-        * hub or switch with different Flow Control capabilities.
-        */
-       if(hw->mac_type == e1000_82542_rev2_0)
-               hw->fc &= (~e1000_fc_tx_pause);
-
-#if 0
-       /* See e1000_sw_init() of the Linux driver */
-       if((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
-#else
-       if((hw->mac_type < e1000_82543) && (hw->mac_type >= e1000_82543))
-#endif
-               hw->fc &= (~e1000_fc_rx_pause);
-       
-#if 0
-       hw->original_fc = hw->fc;
-#endif
-
-       DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
-       
-       /* Take the 4 bits from EEPROM word 0x0F that determine the initial
-        * polarity value for the SW controlled pins, and setup the
-        * Extended Device Control reg with that info.
-        * This is needed because one of the SW controlled pins is used for
-        * signal detection.  So this should be done before e1000_setup_pcs_link()
-        * or e1000_phy_setup() is called.
-        */
-       if(hw->mac_type == e1000_82543) {
-               ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 
-                       SWDPIO__EXT_SHIFT);
-               E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
-       }
-       
-       /* Call the necessary subroutine to configure the link. */
-       ret_val = (hw->media_type == e1000_media_type_copper) ?
-               e1000_setup_copper_link(hw) :
-               e1000_setup_fiber_serdes_link(hw);
-       if (ret_val < 0) {
-               return ret_val;
-       }
-       
-       /* Initialize the flow control address, type, and PAUSE timer
-        * registers to their default values.  This is done even if flow
-        * control is disabled, because it does not hurt anything to
-        * initialize these registers.
-        */
-       DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
-       
-       E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
-       E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
-       E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
-#if 0
-       E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
-#else
-       E1000_WRITE_REG(hw, FCTTV, FC_DEFAULT_TX_TIMER);
-#endif
-       
-       /* Set the flow control receive threshold registers.  Normally,
-        * these registers will be set to a default threshold that may be
-        * adjusted later by the driver's runtime code.  However, if the
-        * ability to transmit pause frames in not enabled, then these
-        * registers will be set to 0. 
-        */
-       if(!(hw->fc & e1000_fc_tx_pause)) {
-               E1000_WRITE_REG(hw, FCRTL, 0);
-               E1000_WRITE_REG(hw, FCRTH, 0);
-       } else {
-               /* We need to set up the Receive Threshold high and low water marks
-                * as well as (optionally) enabling the transmission of XON frames.
-                */
-#if 0
-               if(hw->fc_send_xon) {
-                       E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
-                       E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
-               } else {
-                       E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
-                       E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
-               }
-#else
-               E1000_WRITE_REG(hw, FCRTL, (FC_DEFAULT_LO_THRESH | E1000_FCRTL_XONE));
-               E1000_WRITE_REG(hw, FCRTH, FC_DEFAULT_HI_THRESH);
-#endif
-       }
-       return ret_val;
-}
-
-/******************************************************************************
- * Sets up link for a fiber based or serdes based adapter
- *
- * hw - Struct containing variables accessed by shared code
- *
- * Manipulates Physical Coding Sublayer functions in order to configure
- * link. Assumes the hardware has been previously reset and the transmitter
- * and receiver are not enabled.
- *****************************************************************************/
-static int
-e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
-{
-       uint32_t ctrl;
-       uint32_t status;
-       uint32_t txcw = 0;
-       uint32_t i;
-       uint32_t signal = 0;
-       int32_t ret_val;
-
-       DEBUGFUNC("e1000_setup_fiber_serdes_link");
-
-       /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be 
-        * set when the optics detect a signal. On older adapters, it will be 
-        * cleared when there is a signal.  This applies to fiber media only.
-        * If we're on serdes media, adjust the output amplitude to value set in
-        * the EEPROM.
-        */
-       ctrl = E1000_READ_REG(hw, CTRL);
-       if(hw->media_type == e1000_media_type_fiber)
-               signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
-
-       if((ret_val = e1000_adjust_serdes_amplitude(hw)))
-               return ret_val;
-
-       /* Take the link out of reset */
-       ctrl &= ~(E1000_CTRL_LRST);
-
-#if 0
-       /* Adjust VCO speed to improve BER performance */
-       if((ret_val = e1000_set_vco_speed(hw)))
-               return ret_val;
-#endif
-
-       e1000_config_collision_dist(hw);
-       
-       /* Check for a software override of the flow control settings, and setup
-        * the device accordingly.  If auto-negotiation is enabled, then software
-        * will have to set the "PAUSE" bits to the correct value in the Tranmsit
-        * Config Word Register (TXCW) and re-start auto-negotiation.  However, if
-        * auto-negotiation is disabled, then software will have to manually 
-        * configure the two flow control enable bits in the CTRL register.
-        *
-        * The possible values of the "fc" parameter are:
-        *      0:  Flow control is completely disabled
-        *      1:  Rx flow control is enabled (we can receive pause frames, but 
-        *          not send pause frames).
-        *      2:  Tx flow control is enabled (we can send pause frames but we do
-        *          not support receiving pause frames).
-        *      3:  Both Rx and TX flow control (symmetric) are enabled.
-        */
-       switch (hw->fc) {
-       case e1000_fc_none:
-               /* Flow control is completely disabled by a software over-ride. */
-               txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
-               break;
-       case e1000_fc_rx_pause:
-               /* RX Flow control is enabled and TX Flow control is disabled by a 
-                * software over-ride. Since there really isn't a way to advertise 
-                * that we are capable of RX Pause ONLY, we will advertise that we
-                * support both symmetric and asymmetric RX PAUSE. Later, we will
-                *  disable the adapter's ability to send PAUSE frames.
-                */
-               txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
-               break;
-       case e1000_fc_tx_pause:
-               /* TX Flow control is enabled, and RX Flow control is disabled, by a 
-                * software over-ride.
-                */
-               txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
-               break;
-       case e1000_fc_full:
-               /* Flow control (both RX and TX) is enabled by a software over-ride. */
-               txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
-               break;
-       default:
-               DEBUGOUT("Flow control param set incorrectly\n");
-               return -E1000_ERR_CONFIG;
-               break;
-       }
-       
-       /* Since auto-negotiation is enabled, take the link out of reset (the link
-        * will be in reset, because we previously reset the chip). This will
-        * restart auto-negotiation.  If auto-neogtiation is successful then the
-        * link-up status bit will be set and the flow control enable bits (RFCE
-        * and TFCE) will be set according to their negotiated value.
-        */
-       DEBUGOUT("Auto-negotiation enabled\n");
-       
-       E1000_WRITE_REG(hw, TXCW, txcw);
-       E1000_WRITE_REG(hw, CTRL, ctrl);
-       E1000_WRITE_FLUSH(hw);
-       
-       hw->txcw = txcw;
-       mdelay(1);
-       
-       /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
-        * indication in the Device Status Register.  Time-out if a link isn't 
-        * seen in 500 milliseconds seconds (Auto-negotiation should complete in 
-        * less than 500 milliseconds even if the other end is doing it in SW).
-        * For internal serdes, we just assume a signal is present, then poll.
-        */
-       if(hw->media_type == e1000_media_type_internal_serdes ||
-          (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
-               DEBUGOUT("Looking for Link\n");
-               for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
-                       mdelay(10);
-                       status = E1000_READ_REG(hw, STATUS);
-                       if(status & E1000_STATUS_LU) break;
-               }
-               if(i == (LINK_UP_TIMEOUT / 10)) {
-                       DEBUGOUT("Never got a valid link from auto-neg!!!\n");
-                       hw->autoneg_failed = 1;
-                       /* AutoNeg failed to achieve a link, so we'll call 
-                        * e1000_check_for_link. This routine will force the link up if
-                        * we detect a signal. This will allow us to communicate with
-                        * non-autonegotiating link partners.
-                        */
-                       if((ret_val = e1000_check_for_link(hw))) {
-                               DEBUGOUT("Error while checking for link\n");
-                               return ret_val;
-                       }
-                       hw->autoneg_failed = 0;
-               } else {
-                       hw->autoneg_failed = 0;
-                       DEBUGOUT("Valid Link Found\n");
-               }
-       } else {
-               DEBUGOUT("No Signal Detected\n");
-       }
-       return E1000_SUCCESS;
-}
-
-/******************************************************************************
-* Detects which PHY is present and the speed and duplex
-*
-* hw - Struct containing variables accessed by shared code
-******************************************************************************/
-static int
-e1000_setup_copper_link(struct e1000_hw *hw)
-{
-       uint32_t ctrl;
-       int32_t ret_val;
-       uint16_t i;
-       uint16_t phy_data;
-       
-       DEBUGFUNC("e1000_setup_copper_link");
-       
-       ctrl = E1000_READ_REG(hw, CTRL);
-       /* With 82543, we need to force speed and duplex on the MAC equal to what
-        * the PHY speed and duplex configuration is. In addition, we need to
-        * perform a hardware reset on the PHY to take it out of reset.
-        */
-       if(hw->mac_type > e1000_82543) {
-               ctrl |= E1000_CTRL_SLU;
-               ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
-               E1000_WRITE_REG(hw, CTRL, ctrl);
-       } else {
-               ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
-               E1000_WRITE_REG(hw, CTRL, ctrl);
-               e1000_phy_hw_reset(hw);
-       }
-       
-       /* Make sure we have a valid PHY */
-       if((ret_val = e1000_detect_gig_phy(hw))) {
-               DEBUGOUT("Error, did not detect valid phy.\n");
-               return ret_val;
-       }
-       DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
-
-       if(hw->mac_type <= e1000_82543 ||
-          hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
-#if 0
-          hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
-               hw->phy_reset_disable = FALSE;
-
-       if(!hw->phy_reset_disable) {
-#else
-          hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) {
-#endif
-       if (hw->phy_type == e1000_phy_igp) {
-
-               if((ret_val = e1000_phy_reset(hw))) {
-                       DEBUGOUT("Error Resetting the PHY\n");
-                       return ret_val;
-               }
-
-               /* Wait 10ms for MAC to configure PHY from eeprom settings */
-               mdelay(15);
-
-#if 0
-               /* disable lplu d3 during driver init */
-               if((ret_val = e1000_set_d3_lplu_state(hw, FALSE))) {
-                       DEBUGOUT("Error Disabling LPLU D3\n");
-                       return ret_val;
-               }
-
-               /* Configure mdi-mdix settings */
-               if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
-                                                &phy_data)))
-                       return ret_val;
-
-               if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
-                       hw->dsp_config_state = e1000_dsp_config_disabled;
-                       /* Force MDI for IGP B-0 PHY */
-                       phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX |
-                                     IGP01E1000_PSCR_FORCE_MDI_MDIX);
-                       hw->mdix = 1;
-
-               } else {
-                       hw->dsp_config_state = e1000_dsp_config_enabled;
-                       phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
-
-                       switch (hw->mdix) {
-                       case 1:
-                               phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
-                               break;
-                       case 2:
-                               phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
-                               break;
-                       case 0:
-                       default:
-                               phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
-                               break;
-                       }
-               }
-               if((ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
-                                                 phy_data)))
-                       return ret_val;
-
-               /* set auto-master slave resolution settings */
-               e1000_ms_type phy_ms_setting = hw->master_slave;
-
-               if(hw->ffe_config_state == e1000_ffe_config_active)
-                       hw->ffe_config_state = e1000_ffe_config_enabled;
-
-               if(hw->dsp_config_state == e1000_dsp_config_activated)
-                       hw->dsp_config_state = e1000_dsp_config_enabled;
-#endif
-
-               /* when autonegotiation advertisment is only 1000Mbps then we
-                * should disable SmartSpeed and enable Auto MasterSlave
-                * resolution as hardware default. */
-               if(hw->autoneg_advertised == ADVERTISE_1000_FULL) {
-                       /* Disable SmartSpeed */
-                       if((ret_val = e1000_read_phy_reg(hw,
-                                                        IGP01E1000_PHY_PORT_CONFIG,
-                                                        &phy_data)))
-                               return ret_val;
-                       phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
-                       if((ret_val = e1000_write_phy_reg(hw,
-                                                         IGP01E1000_PHY_PORT_CONFIG,
-                                                         phy_data)))
-                               return ret_val;
-                       /* Set auto Master/Slave resolution process */
-                       if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
-                                                        &phy_data)))
-                               return ret_val;
-                       phy_data &= ~CR_1000T_MS_ENABLE;
-                       if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
-                                                         phy_data)))
-                               return ret_val;
-               }
-
-               if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
-                                                &phy_data)))
-                       return ret_val;
-
-#if 0
-               /* load defaults for future use */
-               hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
-                                           ((phy_data & CR_1000T_MS_VALUE) ?
-                                            e1000_ms_force_master :
-                                            e1000_ms_force_slave) :
-                                            e1000_ms_auto;
-
-               switch (phy_ms_setting) {
-               case e1000_ms_force_master:
-                       phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
-                       break;
-               case e1000_ms_force_slave:
-                       phy_data |= CR_1000T_MS_ENABLE;
-                       phy_data &= ~(CR_1000T_MS_VALUE);
-                       break;
-               case e1000_ms_auto:
-                       phy_data &= ~CR_1000T_MS_ENABLE;
-               default:
-                       break;
-               }
-#endif
-
-               if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
-                                                 phy_data)))
-                       return ret_val;
-       } else {
-               /* Enable CRS on TX. This must be set for half-duplex operation. */
-               if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
-                                                &phy_data)))
-                       return ret_val;
-
-               phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
-
-               /* Options:
-                *   MDI/MDI-X = 0 (default)
-                *   0 - Auto for all speeds
-                *   1 - MDI mode
-                *   2 - MDI-X mode
-                *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
-                */
-#if 0
-               phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
-
-               switch (hw->mdix) {
-               case 1:
-                       phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
-                       break;
-               case 2:
-                       phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
-                       break;
-               case 3:
-                       phy_data |= M88E1000_PSCR_AUTO_X_1000T;
-                       break;
-               case 0:
-               default:
-#endif
-                       phy_data |= M88E1000_PSCR_AUTO_X_MODE;
-#if 0
-                       break;
-               }
-#endif
-
-               /* Options:
-                *   disable_polarity_correction = 0 (default)
-                *       Automatic Correction for Reversed Cable Polarity
-                *   0 - Disabled
-                *   1 - Enabled
-                */
-               phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
-               if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
-                                                 phy_data)))
-                       return ret_val;
-
-               /* Force TX_CLK in the Extended PHY Specific Control Register
-                * to 25MHz clock.
-                */
-               if((ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
-                                                &phy_data)))
-                       return ret_val;
-
-               phy_data |= M88E1000_EPSCR_TX_CLK_25;
-
-#ifdef LINUX_DRIVER
-               if (hw->phy_revision < M88E1011_I_REV_4) {
-#endif
-                       /* Configure Master and Slave downshift values */
-                       phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
-                               M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
-                       phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
-                               M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
-                       if((ret_val = e1000_write_phy_reg(hw,
-                                                         M88E1000_EXT_PHY_SPEC_CTRL,
-                                                         phy_data)))
-                               return ret_val;
-               }
-       
-               /* SW Reset the PHY so all changes take effect */
-               if((ret_val = e1000_phy_reset(hw))) {
-                       DEBUGOUT("Error Resetting the PHY\n");
-                       return ret_val;
-#ifdef LINUX_DRIVER
-               }
-#endif
-       }
-       
-       /* Options:
-        *   autoneg = 1 (default)
-        *      PHY will advertise value(s) parsed from
-        *      autoneg_advertised and fc
-        *   autoneg = 0
-        *      PHY will be set to 10H, 10F, 100H, or 100F
-        *      depending on value parsed from forced_speed_duplex.
-        */
-       
-       /* Is autoneg enabled?  This is enabled by default or by software
-        * override.  If so, call e1000_phy_setup_autoneg routine to parse the
-        * autoneg_advertised and fc options. If autoneg is NOT enabled, then
-        * the user should have provided a speed/duplex override.  If so, then
-        * call e1000_phy_force_speed_duplex to parse and set this up.
-        */
-       /* Perform some bounds checking on the hw->autoneg_advertised
-        * parameter.  If this variable is zero, then set it to the default.
-        */
-       hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
-       
-       /* If autoneg_advertised is zero, we assume it was not defaulted
-        * by the calling code so we set to advertise full capability.
-        */
-       if(hw->autoneg_advertised == 0)
-               hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
-       
-       DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
-       if((ret_val = e1000_phy_setup_autoneg(hw))) {
-               DEBUGOUT("Error Setting up Auto-Negotiation\n");
-               return ret_val;
-       }
-       DEBUGOUT("Restarting Auto-Neg\n");
-       
-       /* Restart auto-negotiation by setting the Auto Neg Enable bit and
-        * the Auto Neg Restart bit in the PHY control register.
-        */
-       if((ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data)))
-               return ret_val;
-
-       phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
-       if((ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data)))
-               return ret_val;
-
-#if 0  
-       /* Does the user want to wait for Auto-Neg to complete here, or
-        * check at a later time (for example, callback routine).
-        */
-       if(hw->wait_autoneg_complete) {
-               if((ret_val = e1000_wait_autoneg(hw))) {
-                       DEBUGOUT("Error while waiting for autoneg to complete\n");
-                       return ret_val;
-               }
-       }
-#else
-       /* If we do not wait for autonegotiation to complete I 
-        * do not see a valid link status.
-        */
-       if((ret_val = e1000_wait_autoneg(hw))) {
-               DEBUGOUT("Error while waiting for autoneg to complete\n");
-               return ret_val;
-       }
-#endif
-       } /* !hw->phy_reset_disable */
-       
-       /* Check link status. Wait up to 100 microseconds for link to become
-        * valid.
-        */
-       for(i = 0; i < 10; i++) {
-               if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
-                       return ret_val;
-               if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
-                       return ret_val;
-
-               if(phy_data & MII_SR_LINK_STATUS) {
-                       /* We have link, so we need to finish the config process:
-                        *   1) Set up the MAC to the current PHY speed/duplex
-                        *      if we are on 82543.  If we
-                        *      are on newer silicon, we only need to configure
-                        *      collision distance in the Transmit Control Register.
-                        *   2) Set up flow control on the MAC to that established with
-                        *      the link partner.
-                        */
-                       if(hw->mac_type >= e1000_82544) {
-                               e1000_config_collision_dist(hw);
-                       } else {
-                               if((ret_val = e1000_config_mac_to_phy(hw))) {
-                                       DEBUGOUT("Error configuring MAC to PHY settings\n");
-                                       return ret_val;
-                               }
-                       }
-                       if((ret_val = e1000_config_fc_after_link_up(hw))) {
-                               DEBUGOUT("Error Configuring Flow Control\n");
-                               return ret_val;
-                       }
-#if 0
-                       if(hw->phy_type == e1000_phy_igp) {
-                               if((ret_val = e1000_config_dsp_after_link_change(hw, TRUE))) {
-                                       DEBUGOUT("Error Configuring DSP after link up\n");
-                                       return ret_val;
-                               }
-                       }
-#endif
-                       DEBUGOUT("Valid link established!!!\n");
-                       return E1000_SUCCESS;
-               }
-               udelay(10);
-       }
-       
-       DEBUGOUT("Unable to establish link!!!\n");
-       return -E1000_ERR_NOLINK;
-}
-
-/******************************************************************************
-* Configures PHY autoneg and flow control advertisement settings
-*
-* hw - Struct containing variables accessed by shared code
-******************************************************************************/
-static int
-e1000_phy_setup_autoneg(struct e1000_hw *hw)
-{
-       int32_t ret_val;
-       uint16_t mii_autoneg_adv_reg;
-       uint16_t mii_1000t_ctrl_reg;
-
-       DEBUGFUNC("e1000_phy_setup_autoneg");
-       
-       /* Read the MII Auto-Neg Advertisement Register (Address 4). */
-       if((ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
-                                        &mii_autoneg_adv_reg)))
-               return ret_val;
-
-       /* Read the MII 1000Base-T Control Register (Address 9). */
-       if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg)))
-               return ret_val;
-
-       /* Need to parse both autoneg_advertised and fc and set up
-        * the appropriate PHY registers.  First we will parse for
-        * autoneg_advertised software override.  Since we can advertise
-        * a plethora of combinations, we need to check each bit
-        * individually.
-        */
-       
-       /* First we clear all the 10/100 mb speed bits in the Auto-Neg
-        * Advertisement Register (Address 4) and the 1000 mb speed bits in
-        * the  1000Base-T Control Register (Address 9).
-        */
-       mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
-       mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
-
-       DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
-
-       /* Do we want to advertise 10 Mb Half Duplex? */
-       if(hw->autoneg_advertised & ADVERTISE_10_HALF) {
-               DEBUGOUT("Advertise 10mb Half duplex\n");
-               mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
-       }
-
-       /* Do we want to advertise 10 Mb Full Duplex? */
-       if(hw->autoneg_advertised & ADVERTISE_10_FULL) {
-               DEBUGOUT("Advertise 10mb Full duplex\n");
-               mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
-       }
-
-       /* Do we want to advertise 100 Mb Half Duplex? */
-       if(hw->autoneg_advertised & ADVERTISE_100_HALF) {
-               DEBUGOUT("Advertise 100mb Half duplex\n");
-               mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
-       }
-
-       /* Do we want to advertise 100 Mb Full Duplex? */
-       if(hw->autoneg_advertised & ADVERTISE_100_FULL) {
-               DEBUGOUT("Advertise 100mb Full duplex\n");
-               mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
-       }
-
-       /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
-       if(hw->autoneg_advertised & ADVERTISE_1000_HALF) {
-               DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
-       }
-
-       /* Do we want to advertise 1000 Mb Full Duplex? */
-       if(hw->autoneg_advertised & ADVERTISE_1000_FULL) {
-               DEBUGOUT("Advertise 1000mb Full duplex\n");
-               mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
-       }
-
-       /* Check for a software override of the flow control settings, and
-        * setup the PHY advertisement registers accordingly.  If
-        * auto-negotiation is enabled, then software will have to set the
-        * "PAUSE" bits to the correct value in the Auto-Negotiation
-        * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
-        *
-        * The possible values of the "fc" parameter are:
-        *      0:  Flow control is completely disabled
-        *      1:  Rx flow control is enabled (we can receive pause frames
-        *          but not send pause frames).
-        *      2:  Tx flow control is enabled (we can send pause frames
-        *          but we do not support receiving pause frames).
-        *      3:  Both Rx and TX flow control (symmetric) are enabled.
-        *  other:  No software override.  The flow control configuration
-        *          in the EEPROM is used.
-        */
-       switch (hw->fc) {
-       case e1000_fc_none: /* 0 */
-               /* Flow control (RX & TX) is completely disabled by a
-                * software over-ride.
-                */
-               mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
-               break;
-       case e1000_fc_rx_pause: /* 1 */
-               /* RX Flow control is enabled, and TX Flow control is
-                * disabled, by a software over-ride.
-                */
-               /* Since there really isn't a way to advertise that we are
-                * capable of RX Pause ONLY, we will advertise that we
-                * support both symmetric and asymmetric RX PAUSE.  Later
-                * (in e1000_config_fc_after_link_up) we will disable the
-                *hw's ability to send PAUSE frames.
-                */
-               mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
-               break;
-       case e1000_fc_tx_pause: /* 2 */
-               /* TX Flow control is enabled, and RX Flow control is
-                * disabled, by a software over-ride.
-                */
-               mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
-               mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
-               break;
-       case e1000_fc_full: /* 3 */
-               /* Flow control (both RX and TX) is enabled by a software
-                * over-ride.
-                */
-               mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
-               break;
-       default:
-               DEBUGOUT("Flow control param set incorrectly\n");
-               return -E1000_ERR_CONFIG;
-       }
-
-       if((ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV,
-                              mii_autoneg_adv_reg)))
-               return ret_val;
-
-       DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
-
-       if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg)))
-               return ret_val;
-
-       return E1000_SUCCESS;
-}
-
-/******************************************************************************
-* Sets the collision distance in the Transmit Control register
-*
-* hw - Struct containing variables accessed by shared code
-*
-* Link should have been established previously. Reads the speed and duplex
-* information from the Device Status register.
-******************************************************************************/
-static void
-e1000_config_collision_dist(struct e1000_hw *hw)
-{
-       uint32_t tctl;
-
-       tctl = E1000_READ_REG(hw, TCTL);
-       
-       tctl &= ~E1000_TCTL_COLD;
-       tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
-       
-       E1000_WRITE_REG(hw, TCTL, tctl);
-       E1000_WRITE_FLUSH(hw);
-}
-
-/******************************************************************************
-* Sets MAC speed and duplex settings to reflect the those in the PHY
-*
-* hw - Struct containing variables accessed by shared code
-* mii_reg - data to write to the MII control register
-*
-* The contents of the PHY register containing the needed information need to
-* be passed in.
-******************************************************************************/
-static int
-e1000_config_mac_to_phy(struct e1000_hw *hw)
-{
-       uint32_t ctrl;
-       int32_t ret_val;
-       uint16_t phy_data;
-
-       DEBUGFUNC("e1000_config_mac_to_phy");
-
-       /* Read the Device Control Register and set the bits to Force Speed
-        * and Duplex.
-        */
-       ctrl = E1000_READ_REG(hw, CTRL);
-       ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
-       ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
-
-       /* Set up duplex in the Device Control and Transmit Control
-        * registers depending on negotiated values.
-        */
-       if (hw->phy_type == e1000_phy_igp) {
-               if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
-                                                &phy_data)))
-                       return ret_val;
-
-               if(phy_data & IGP01E1000_PSSR_FULL_DUPLEX) ctrl |= E1000_CTRL_FD;
-               else ctrl &= ~E1000_CTRL_FD;
-
-               e1000_config_collision_dist(hw);
-
-               /* Set up speed in the Device Control register depending on
-                * negotiated values.
-                */
-               if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
-                  IGP01E1000_PSSR_SPEED_1000MBPS)
-                       ctrl |= E1000_CTRL_SPD_1000;
-               else if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
-                       IGP01E1000_PSSR_SPEED_100MBPS)
-                       ctrl |= E1000_CTRL_SPD_100;
-       } else {
-               if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
-                                                &phy_data)))
-                       return ret_val;
-               
-               if(phy_data & M88E1000_PSSR_DPLX) ctrl |= E1000_CTRL_FD;
-               else ctrl &= ~E1000_CTRL_FD;
-
-               e1000_config_collision_dist(hw);
-
-               /* Set up speed in the Device Control register depending on
-                * negotiated values.
-                */
-               if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
-                       ctrl |= E1000_CTRL_SPD_1000;
-               else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
-                       ctrl |= E1000_CTRL_SPD_100;
-       }
-       /* Write the configured values back to the Device Control Reg. */
-       E1000_WRITE_REG(hw, CTRL, ctrl);
-       return E1000_SUCCESS;
-}
-
-/******************************************************************************
- * Forces the MAC's flow control settings.
- * 
- * hw - Struct containing variables accessed by shared code
- *
- * Sets the TFCE and RFCE bits in the device control register to reflect
- * the adapter settings. TFCE and RFCE need to be explicitly set by
- * software when a Copper PHY is used because autonegotiation is managed
- * by the PHY rather than the MAC. Software must also configure these
- * bits when link is forced on a fiber connection.
- *****************************************************************************/
-static int
-e1000_force_mac_fc(struct e1000_hw *hw)
-{
-       uint32_t ctrl;
-       
-       DEBUGFUNC("e1000_force_mac_fc");
-       
-       /* Get the current configuration of the Device Control Register */
-       ctrl = E1000_READ_REG(hw, CTRL);
-       
-       /* Because we didn't get link via the internal auto-negotiation
-        * mechanism (we either forced link or we got link via PHY
-        * auto-neg), we have to manually enable/disable transmit an
-        * receive flow control.
-        *
-        * The "Case" statement below enables/disable flow control
-        * according to the "hw->fc" parameter.
-        *
-        * The possible values of the "fc" parameter are:
-        *      0:  Flow control is completely disabled
-        *      1:  Rx flow control is enabled (we can receive pause
-        *          frames but not send pause frames).
-        *      2:  Tx flow control is enabled (we can send pause frames
-        *          frames but we do not receive pause frames).
-        *      3:  Both Rx and TX flow control (symmetric) is enabled.
-        *  other:  No other values should be possible at this point.
-        */
-       
-       switch (hw->fc) {
-       case e1000_fc_none:
-               ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
-               break;
-       case e1000_fc_rx_pause:
-               ctrl &= (~E1000_CTRL_TFCE);
-               ctrl |= E1000_CTRL_RFCE;
-               break;
-       case e1000_fc_tx_pause:
-               ctrl &= (~E1000_CTRL_RFCE);
-               ctrl |= E1000_CTRL_TFCE;
-               break;
-       case e1000_fc_full:
-               ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
-               break;
-       default:
-               DEBUGOUT("Flow control param set incorrectly\n");
-               return -E1000_ERR_CONFIG;
-       }
-       
-       /* Disable TX Flow Control for 82542 (rev 2.0) */
-       if(hw->mac_type == e1000_82542_rev2_0)
-               ctrl &= (~E1000_CTRL_TFCE);
-       
-       E1000_WRITE_REG(hw, CTRL, ctrl);
-       return E1000_SUCCESS;
-}
-
-/******************************************************************************
- * Configures flow control settings after link is established
- * 
- * hw - Struct containing variables accessed by shared code
- *
- * Should be called immediately after a valid link has been established.
- * Forces MAC flow control settings if link was forced. When in MII/GMII mode
- * and autonegotiation is enabled, the MAC flow control settings will be set
- * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
- * and RFCE bits will be automaticaly set to the negotiated flow control mode.
- *****************************************************************************/
-static int
-e1000_config_fc_after_link_up(struct e1000_hw *hw)
-{
-       int32_t ret_val;
-       uint16_t mii_status_reg;
-       uint16_t mii_nway_adv_reg;
-       uint16_t mii_nway_lp_ability_reg;
-       uint16_t speed;
-       uint16_t duplex;
-       
-       DEBUGFUNC("e1000_config_fc_after_link_up");
-       
-       /* Check for the case where we have fiber media and auto-neg failed
-        * so we had to force link.  In this case, we need to force the
-        * configuration of the MAC to match the "fc" parameter.
-        */
-       if(((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
-          ((hw->media_type == e1000_media_type_internal_serdes) && (hw->autoneg_failed))) { 
-               if((ret_val = e1000_force_mac_fc(hw))) {
-                       DEBUGOUT("Error forcing flow control settings\n");
-                       return ret_val;
-               }
-       }
-       
-       /* Check for the case where we have copper media and auto-neg is
-        * enabled.  In this case, we need to check and see if Auto-Neg
-        * has completed, and if so, how the PHY and link partner has
-        * flow control configured.
-        */
-       if(hw->media_type == e1000_media_type_copper) {
-               /* Read the MII Status Register and check to see if AutoNeg
-                * has completed.  We read this twice because this reg has
-                * some "sticky" (latched) bits.
-                */
-               if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
-                       return ret_val;
-               if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
-                       return ret_val;
-               
-               if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
-                       /* The AutoNeg process has completed, so we now need to
-                        * read both the Auto Negotiation Advertisement Register
-                        * (Address 4) and the Auto_Negotiation Base Page Ability
-                        * Register (Address 5) to determine how flow control was
-                        * negotiated.
-                        */
-                       if((ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
-                                                        &mii_nway_adv_reg)))
-                               return ret_val;
-                       if((ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
-                                                        &mii_nway_lp_ability_reg)))
-                               return ret_val;
-
-                       /* Two bits in the Auto Negotiation Advertisement Register
-                        * (Address 4) and two bits in the Auto Negotiation Base
-                        * Page Ability Register (Address 5) determine flow control
-                        * for both the PHY and the link partner.  The following
-                        * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
-                        * 1999, describes these PAUSE resolution bits and how flow
-                        * control is determined based upon these settings.
-                        * NOTE:  DC = Don't Care
-                        *
-                        *   LOCAL DEVICE  |   LINK PARTNER
-                        * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
-                        *-------|---------|-------|---------|--------------------
-                        *   0   |    0    |  DC   |   DC    | e1000_fc_none
-                        *   0   |    1    |   0   |   DC    | e1000_fc_none
-                        *   0   |    1    |   1   |    0    | e1000_fc_none
-                        *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
-                        *   1   |    0    |   0   |   DC    | e1000_fc_none
-                        *   1   |   DC    |   1   |   DC    | e1000_fc_full
-                        *   1   |    1    |   0   |    0    | e1000_fc_none
-                        *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
-                        *
-                        */
-                       /* Are both PAUSE bits set to 1?  If so, this implies
-                        * Symmetric Flow Control is enabled at both ends.  The
-                        * ASM_DIR bits are irrelevant per the spec.
-                        *
-                        * For Symmetric Flow Control:
-                        *
-                        *   LOCAL DEVICE  |   LINK PARTNER
-                        * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
-                        *-------|---------|-------|---------|--------------------
-                        *   1   |   DC    |   1   |   DC    | e1000_fc_full
-                        *
-                        */
-                       if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
-                               (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
-                               /* Now we need to check if the user selected RX ONLY
-                                * of pause frames.  In this case, we had to advertise
-                                * FULL flow control because we could not advertise RX
-                                * ONLY. Hence, we must now check to see if we need to
-                                * turn OFF  the TRANSMISSION of PAUSE frames.
-                                */
-#if 0
-                               if(hw->original_fc == e1000_fc_full) {
-                                       hw->fc = e1000_fc_full;
-#else
-                               if(hw->fc == e1000_fc_full) {
-#endif
-                                       DEBUGOUT("Flow Control = FULL.\r\n");
-                               } else {
-                                       hw->fc = e1000_fc_rx_pause;
-                                       DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
-                               }
-                       }
-                       /* For receiving PAUSE frames ONLY.
-                        *
-                        *   LOCAL DEVICE  |   LINK PARTNER
-                        * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
-                        *-------|---------|-------|---------|--------------------
-                        *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
-                        *
-                        */
-                       else if(!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
-                               (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
-                               (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
-                               (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
-                               hw->fc = e1000_fc_tx_pause;
-                               DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n");
-                       }
-                       /* For transmitting PAUSE frames ONLY.
-                        *
-                        *   LOCAL DEVICE  |   LINK PARTNER
-                        * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
-                        *-------|---------|-------|---------|--------------------
-                        *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
-                        *
-                        */
-                       else if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
-                               (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
-                               !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
-                               (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
-                               hw->fc = e1000_fc_rx_pause;
-                               DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
-                       }
-                       /* Per the IEEE spec, at this point flow control should be
-                        * disabled.  However, we want to consider that we could
-                        * be connected to a legacy switch that doesn't advertise
-                        * desired flow control, but can be forced on the link
-                        * partner.  So if we advertised no flow control, that is
-                        * what we will resolve to.  If we advertised some kind of
-                        * receive capability (Rx Pause Only or Full Flow Control)
-                        * and the link partner advertised none, we will configure
-                        * ourselves to enable Rx Flow Control only.  We can do
-                        * this safely for two reasons:  If the link partner really
-                        * didn't want flow control enabled, and we enable Rx, no
-                        * harm done since we won't be receiving any PAUSE frames
-                        * anyway.  If the intent on the link partner was to have
-                        * flow control enabled, then by us enabling RX only, we
-                        * can at least receive pause frames and process them.
-                        * This is a good idea because in most cases, since we are
-                        * predominantly a server NIC, more times than not we will
-                        * be asked to delay transmission of packets than asking
-                        * our link partner to pause transmission of frames.
-                        */
-#if 0
-                       else if(hw->original_fc == e1000_fc_none ||
-                               hw->original_fc == e1000_fc_tx_pause) {
-#else
-                       else if(hw->fc == e1000_fc_none)
-                               DEBUGOUT("Flow Control = NONE.\r\n");
-                       else if(hw->fc == e1000_fc_tx_pause) {
-#endif
-                               hw->fc = e1000_fc_none;
-                               DEBUGOUT("Flow Control = NONE.\r\n");
-                       } else {
-                               hw->fc = e1000_fc_rx_pause;
-                               DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
-                       }
-                       
-                       /* Now we need to do one last check...  If we auto-
-                        * negotiated to HALF DUPLEX, flow control should not be
-                        * enabled per IEEE 802.3 spec.
-                        */
-                       e1000_get_speed_and_duplex(hw, &speed, &duplex);
-                       
-                       if(duplex == HALF_DUPLEX)
-                               hw->fc = e1000_fc_none;
-                       
-                       /* Now we call a subroutine to actually force the MAC
-                        * controller to use the correct flow control settings.
-                        */
-                       if((ret_val = e1000_force_mac_fc(hw))) {
-                               DEBUGOUT("Error forcing flow control settings\n");
-                               return ret_val;
-                       }
-               } else {
-                       DEBUGOUT("Copper PHY and Auto Neg has not completed.\r\n");
-               }
-       }
-       return E1000_SUCCESS;
-}
-
-/******************************************************************************
- * Checks to see if the link status of the hardware has changed.
- *
- * hw - Struct containing variables accessed by shared code
- *
- * Called by any function that needs to check the link status of the adapter.
- *****************************************************************************/
-static int
-e1000_check_for_link(struct e1000_hw *hw)
-{
-       uint32_t rxcw;
-       uint32_t ctrl;
-       uint32_t status;
-       uint32_t rctl;
-       uint32_t signal = 0;
-       int32_t ret_val;
-       uint16_t phy_data;
-       uint16_t lp_capability;
-       
-       DEBUGFUNC("e1000_check_for_link");
-       
-       /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be 
-        * set when the optics detect a signal. On older adapters, it will be 
-        * cleared when there is a signal.  This applies to fiber media only.
-        */
-       if(hw->media_type == e1000_media_type_fiber)
-               signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
-
-       ctrl = E1000_READ_REG(hw, CTRL);
-       status = E1000_READ_REG(hw, STATUS);
-       rxcw = E1000_READ_REG(hw, RXCW);
-       
-       /* If we have a copper PHY then we only want to go out to the PHY
-        * registers to see if Auto-Neg has completed and/or if our link
-        * status has changed.  The get_link_status flag will be set if we
-        * receive a Link Status Change interrupt or we have Rx Sequence
-        * Errors.
-        */
-#if 0
-       if((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
-#else
-       if(hw->media_type == e1000_media_type_copper) {
-#endif
-               /* First we want to see if the MII Status Register reports
-                * link.  If so, then we want to get the current speed/duplex
-                * of the PHY.
-                * Read the register twice since the link bit is sticky.
-                */
-               if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
-                       return ret_val;
-               if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
-                       return ret_val;
-               
-               if(phy_data & MII_SR_LINK_STATUS) {
-#if 0
-                       hw->get_link_status = FALSE;
-#endif
-               } else {
-                       /* No link detected */
-                       return -E1000_ERR_NOLINK;
-               }
-
-               /* We have a M88E1000 PHY and Auto-Neg is enabled.  If we
-                * have Si on board that is 82544 or newer, Auto
-                * Speed Detection takes care of MAC speed/duplex
-                * configuration.  So we only need to configure Collision
-                * Distance in the MAC.  Otherwise, we need to force
-                * speed/duplex on the MAC to the current PHY speed/duplex
-                * settings.
-                */
-               if(hw->mac_type >= e1000_82544)
-                       e1000_config_collision_dist(hw);
-               else {
-                       if((ret_val = e1000_config_mac_to_phy(hw))) {
-                               DEBUGOUT("Error configuring MAC to PHY settings\n");
-                               return ret_val;
-                       }
-               }
-               
-               /* Configure Flow Control now that Auto-Neg has completed. First, we 
-                * need to restore the desired flow control settings because we may
-                * have had to re-autoneg with a different link partner.
-                */
-               if((ret_val = e1000_config_fc_after_link_up(hw))) {
-                       DEBUGOUT("Error configuring flow control\n");
-                       return ret_val;
-               }
-               
-               /* At this point we know that we are on copper and we have
-                * auto-negotiated link.  These are conditions for checking the link
-                * parter capability register.  We use the link partner capability to
-                * determine if TBI Compatibility needs to be turned on or off.  If
-                * the link partner advertises any speed in addition to Gigabit, then
-                * we assume that they are GMII-based, and TBI compatibility is not
-                * needed. If no other speeds are advertised, we assume the link
-                * partner is TBI-based, and we turn on TBI Compatibility.
-                */
-               if(hw->tbi_compatibility_en) {
-                       if((ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
-                                                        &lp_capability)))
-                               return ret_val;
-                       if(lp_capability & (NWAY_LPAR_10T_HD_CAPS |
-                                NWAY_LPAR_10T_FD_CAPS |
-                                NWAY_LPAR_100TX_HD_CAPS |
-                                NWAY_LPAR_100TX_FD_CAPS |
-                                NWAY_LPAR_100T4_CAPS)) {
-                               /* If our link partner advertises anything in addition to 
-                                * gigabit, we do not need to enable TBI compatibility.
-                                */
-                               if(hw->tbi_compatibility_on) {
-                                       /* If we previously were in the mode, turn it off. */
-                                       rctl = E1000_READ_REG(hw, RCTL);
-                                       rctl &= ~E1000_RCTL_SBP;
-                                       E1000_WRITE_REG(hw, RCTL, rctl);
-                                       hw->tbi_compatibility_on = FALSE;
-                               }
-                       } else {
-                               /* If TBI compatibility is was previously off, turn it on. For
-                                * compatibility with a TBI link partner, we will store bad
-                                * packets. Some frames have an additional byte on the end and
-                                * will look like CRC errors to to the hardware.
-                                */
-                               if(!hw->tbi_compatibility_on) {
-                                       hw->tbi_compatibility_on = TRUE;
-                                       rctl = E1000_READ_REG(hw, RCTL);
-                                       rctl |= E1000_RCTL_SBP;
-                                       E1000_WRITE_REG(hw, RCTL, rctl);
-                               }
-                       }
-               }
-       }
-       /* If we don't have link (auto-negotiation failed or link partner cannot
-        * auto-negotiate), the cable is plugged in (we have signal), and our
-        * link partner is not trying to auto-negotiate with us (we are receiving
-        * idles or data), we need to force link up. We also need to give
-        * auto-negotiation time to complete, in case the cable was just plugged
-        * in. The autoneg_failed flag does this.
-        */
-       else if((((hw->media_type == e1000_media_type_fiber) &&
-               ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
-               (hw->media_type == e1000_media_type_internal_serdes)) &&
-               (!(status & E1000_STATUS_LU)) &&
-               (!(rxcw & E1000_RXCW_C))) {
-               if(hw->autoneg_failed == 0) {
-                       hw->autoneg_failed = 1;
-                       return 0;
-               }
-               DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
-               
-               /* Disable auto-negotiation in the TXCW register */
-               E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
-               
-               /* Force link-up and also force full-duplex. */
-               ctrl = E1000_READ_REG(hw, CTRL);
-               ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
-               E1000_WRITE_REG(hw, CTRL, ctrl);
-               
-               /* Configure Flow Control after forcing link up. */
-               if((ret_val = e1000_config_fc_after_link_up(hw))) {
-                       DEBUGOUT("Error configuring flow control\n");
-                       return ret_val;
-               }
-       }
-       /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
-        * auto-negotiation in the TXCW register and disable forced link in the
-        * Device Control register in an attempt to auto-negotiate with our link
-        * partner.
-        */
-       else if(((hw->media_type == e1000_media_type_fiber)  ||
-                (hw->media_type == e1000_media_type_internal_serdes)) &&
-               (ctrl & E1000_CTRL_SLU) &&
-               (rxcw & E1000_RXCW_C)) {
-               DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
-               E1000_WRITE_REG(hw, TXCW, hw->txcw);
-               E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
-       }
-#if 0
-       /* If we force link for non-auto-negotiation switch, check link status
-        * based on MAC synchronization for internal serdes media type.
-        */
-       else if((hw->media_type == e1000_media_type_internal_serdes) &&
-                       !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
-               /* SYNCH bit and IV bit are sticky. */
-               udelay(10);
-               if(E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
-                       if(!(rxcw & E1000_RXCW_IV)) {
-                               hw->serdes_link_down = FALSE;
-                               DEBUGOUT("SERDES: Link is up.\n");
-                       }
-               } else {
-                       hw->serdes_link_down = TRUE;
-                       DEBUGOUT("SERDES: Link is down.\n");
-               }
-       }
-#endif
-       return E1000_SUCCESS;
-}
-
-/******************************************************************************
- * Detects the current speed and duplex settings of the hardware.
- *
- * hw - Struct containing variables accessed by shared code
- * speed - Speed of the connection
- * duplex - Duplex setting of the connection
- *****************************************************************************/
-static void 
-e1000_get_speed_and_duplex(struct e1000_hw *hw,
-                           uint16_t *speed,
-                           uint16_t *duplex)
-{
-       uint32_t status;
-       
-       DEBUGFUNC("e1000_get_speed_and_duplex");
-       
-       if(hw->mac_type >= e1000_82543) {
-               status = E1000_READ_REG(hw, STATUS);
-               if(status & E1000_STATUS_SPEED_1000) {
-                       *speed = SPEED_1000;
-                       DEBUGOUT("1000 Mbs, ");
-               } else if(status & E1000_STATUS_SPEED_100) {
-                       *speed = SPEED_100;
-                       DEBUGOUT("100 Mbs, ");
-               } else {
-                       *speed = SPEED_10;
-                       DEBUGOUT("10 Mbs, ");
-               }
-               
-               if(status & E1000_STATUS_FD) {
-                       *duplex = FULL_DUPLEX;
-                       DEBUGOUT("Full Duplex\r\n");
-               } else {
-                       *duplex = HALF_DUPLEX;
-                       DEBUGOUT(" Half Duplex\r\n");
-               }
-       } else {
-               DEBUGOUT("1000 Mbs, Full Duplex\r\n");
-               *speed = SPEED_1000;
-               *duplex = FULL_DUPLEX;
-       }
-}
-
-/******************************************************************************
-* Blocks until autoneg completes or times out (~4.5 seconds)
-*
-* hw - Struct containing variables accessed by shared code
-******************************************************************************/
-static int
-e1000_wait_autoneg(struct e1000_hw *hw)
-{
-       int32_t ret_val;
-       uint16_t i;
-       uint16_t phy_data;
-       
-       DEBUGFUNC("e1000_wait_autoneg");
-       DEBUGOUT("Waiting for Auto-Neg to complete.\n");
-       
-       /* We will wait for autoneg to complete or 4.5 seconds to expire. */
-       for(i = PHY_AUTO_NEG_TIME; i > 0; i--) {
-               /* Read the MII Status Register and wait for Auto-Neg
-                * Complete bit to be set.
-                */
-               if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
-                       return ret_val;
-               if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
-                       return ret_val;
-               if(phy_data & MII_SR_AUTONEG_COMPLETE) {
-                       DEBUGOUT("Auto-Neg complete.\n");
-                       return E1000_SUCCESS;
-               }
-               mdelay(100);
-       }
-       DEBUGOUT("Auto-Neg timedout.\n");
-       return -E1000_ERR_TIMEOUT;
-}
-
-/******************************************************************************
-* Raises the Management Data Clock
-*
-* hw - Struct containing variables accessed by shared code
-* ctrl - Device control register's current value
-******************************************************************************/
-static void
-e1000_raise_mdi_clk(struct e1000_hw *hw,
-                    uint32_t *ctrl)
-{
-       /* Raise the clock input to the Management Data Clock (by setting the MDC
-        * bit), and then delay 10 microseconds.
-        */
-       E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
-       E1000_WRITE_FLUSH(hw);
-       udelay(10);
-}
-
-/******************************************************************************
-* Lowers the Management Data Clock
-*
-* hw - Struct containing variables accessed by shared code
-* ctrl - Device control register's current value
-******************************************************************************/
-static void
-e1000_lower_mdi_clk(struct e1000_hw *hw,
-                    uint32_t *ctrl)
-{
-       /* Lower the clock input to the Management Data Clock (by clearing the MDC
-        * bit), and then delay 10 microseconds.
-        */
-       E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
-       E1000_WRITE_FLUSH(hw);
-       udelay(10);
-}
-
-/******************************************************************************
-* Shifts data bits out to the PHY
-*
-* hw - Struct containing variables accessed by shared code
-* data - Data to send out to the PHY
-* count - Number of bits to shift out
-*
-* Bits are shifted out in MSB to LSB order.
-******************************************************************************/
-static void
-e1000_shift_out_mdi_bits(struct e1000_hw *hw,
-                         uint32_t data,
-                         uint16_t count)
-{
-       uint32_t ctrl;
-       uint32_t mask;
-
-       /* We need to shift "count" number of bits out to the PHY. So, the value
-        * in the "data" parameter will be shifted out to the PHY one bit at a 
-        * time. In order to do this, "data" must be broken down into bits.
-        */
-       mask = 0x01;
-       mask <<= (count - 1);
-       
-       ctrl = E1000_READ_REG(hw, CTRL);
-       
-       /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
-       ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
-       
-       while(mask) {
-               /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
-                * then raising and lowering the Management Data Clock. A "0" is
-                * shifted out to the PHY by setting the MDIO bit to "0" and then
-                * raising and lowering the clock.
-                */
-               if(data & mask) ctrl |= E1000_CTRL_MDIO;
-               else ctrl &= ~E1000_CTRL_MDIO;
-               
-               E1000_WRITE_REG(hw, CTRL, ctrl);
-               E1000_WRITE_FLUSH(hw);
-               
-               udelay(10);
-
-               e1000_raise_mdi_clk(hw, &ctrl);
-               e1000_lower_mdi_clk(hw, &ctrl);
-
-               mask = mask >> 1;
-       }
-}
-
-/******************************************************************************
-* Shifts data bits in from the PHY
-*
-* hw - Struct containing variables accessed by shared code
-*
-* Bits are shifted in in MSB to LSB order. 
-******************************************************************************/
-static uint16_t
-e1000_shift_in_mdi_bits(struct e1000_hw *hw)
-{
-       uint32_t ctrl;
-       uint16_t data = 0;
-       uint8_t i;
-
-       /* In order to read a register from the PHY, we need to shift in a total
-        * of 18 bits from the PHY. The first two bit (turnaround) times are used
-        * to avoid contention on the MDIO pin when a read operation is performed.
-        * These two bits are ignored by us and thrown away. Bits are "shifted in"
-        * by raising the input to the Management Data Clock (setting the MDC bit),
-        * and then reading the value of the MDIO bit.
-        */ 
-       ctrl = E1000_READ_REG(hw, CTRL);
-       
-       /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
-       ctrl &= ~E1000_CTRL_MDIO_DIR;
-       ctrl &= ~E1000_CTRL_MDIO;
-       
-       E1000_WRITE_REG(hw, CTRL, ctrl);
-       E1000_WRITE_FLUSH(hw);
-       
-       /* Raise and Lower the clock before reading in the data. This accounts for
-        * the turnaround bits. The first clock occurred when we clocked out the
-        * last bit of the Register Address.
-        */
-       e1000_raise_mdi_clk(hw, &ctrl);
-       e1000_lower_mdi_clk(hw, &ctrl);
-       
-       for(data = 0, i = 0; i < 16; i++) {
-               data = data << 1;
-               e1000_raise_mdi_clk(hw, &ctrl);
-               ctrl = E1000_READ_REG(hw, CTRL);
-               /* Check to see if we shifted in a "1". */
-               if(ctrl & E1000_CTRL_MDIO) data |= 1;
-               e1000_lower_mdi_clk(hw, &ctrl);
-       }
-       
-       e1000_raise_mdi_clk(hw, &ctrl);
-       e1000_lower_mdi_clk(hw, &ctrl);
-       
-       return data;
-}
-
-/*****************************************************************************
-* Reads the value from a PHY register, if the value is on a specific non zero
-* page, sets the page first.
-*
-* hw - Struct containing variables accessed by shared code
-* reg_addr - address of the PHY register to read
-******************************************************************************/
-static int
-e1000_read_phy_reg(struct e1000_hw *hw,
-                   uint32_t reg_addr,
-                   uint16_t *phy_data)
-{
-       uint32_t ret_val;
-
-       DEBUGFUNC("e1000_read_phy_reg");
-
-       if(hw->phy_type == e1000_phy_igp &&
-          (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
-               if((ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
-                                                    (uint16_t)reg_addr)))
-                       return ret_val;
-       }
-
-       ret_val = e1000_read_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr,
-                                       phy_data);
-
-       return ret_val;
-}
-
-static int
-e1000_read_phy_reg_ex(struct e1000_hw *hw,
-                      uint32_t reg_addr,
-                      uint16_t *phy_data)
-{
-       uint32_t i;
-       uint32_t mdic = 0;
-       const uint32_t phy_addr = 1;
-
-       DEBUGFUNC("e1000_read_phy_reg_ex");
-       
-       if(reg_addr > MAX_PHY_REG_ADDRESS) {
-               DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
-               return -E1000_ERR_PARAM;
-       }
-       
-       if(hw->mac_type > e1000_82543) {
-               /* Set up Op-code, Phy Address, and register address in the MDI
-                * Control register.  The MAC will take care of interfacing with the
-                * PHY to retrieve the desired data.
-                */
-               mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
-                       (phy_addr << E1000_MDIC_PHY_SHIFT) | 
-                       (E1000_MDIC_OP_READ));
-               
-               E1000_WRITE_REG(hw, MDIC, mdic);
-
-               /* Poll the ready bit to see if the MDI read completed */
-               for(i = 0; i < 64; i++) {
-                       udelay(50);
-                       mdic = E1000_READ_REG(hw, MDIC);
-                       if(mdic & E1000_MDIC_READY) break;
-               }
-               if(!(mdic & E1000_MDIC_READY)) {
-                       DEBUGOUT("MDI Read did not complete\n");
-                       return -E1000_ERR_PHY;
-               }
-               if(mdic & E1000_MDIC_ERROR) {
-                       DEBUGOUT("MDI Error\n");
-                       return -E1000_ERR_PHY;
-               }
-               *phy_data = (uint16_t) mdic;
-       } else {
-               /* We must first send a preamble through the MDIO pin to signal the
-                * beginning of an MII instruction.  This is done by sending 32
-                * consecutive "1" bits.
-                */
-               e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
-               
-               /* Now combine the next few fields that are required for a read
-                * operation.  We use this method instead of calling the
-                * e1000_shift_out_mdi_bits routine five different times. The format of
-                * a MII read instruction consists of a shift out of 14 bits and is
-                * defined as follows:
-                *    <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
-                * followed by a shift in of 18 bits.  This first two bits shifted in
-                * are TurnAround bits used to avoid contention on the MDIO pin when a
-                * READ operation is performed.  These two bits are thrown away
-                * followed by a shift in of 16 bits which contains the desired data.
-                */
-               mdic = ((reg_addr) | (phy_addr << 5) | 
-                       (PHY_OP_READ << 10) | (PHY_SOF << 12));
-               
-               e1000_shift_out_mdi_bits(hw, mdic, 14);
-               
-               /* Now that we've shifted out the read command to the MII, we need to
-                * "shift in" the 16-bit value (18 total bits) of the requested PHY
-                * register address.
-                */
-               *phy_data = e1000_shift_in_mdi_bits(hw);
-       }
-       return E1000_SUCCESS;
-}
-
-/******************************************************************************
-* Writes a value to a PHY register
-*
-* hw - Struct containing variables accessed by shared code
-* reg_addr - address of the PHY register to write
-* data - data to write to the PHY
-******************************************************************************/
-static int 
-e1000_write_phy_reg(struct e1000_hw *hw,
-                    uint32_t reg_addr,
-                    uint16_t phy_data)
-{
-       uint32_t ret_val;
-
-       DEBUGFUNC("e1000_write_phy_reg");
-
-       if(hw->phy_type == e1000_phy_igp &&
-          (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
-               if((ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
-                                                    (uint16_t)reg_addr)))
-                       return ret_val;
-       }
-
-       ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr,
-                                        phy_data);
-
-       return ret_val;
-}
-
-static int
-e1000_write_phy_reg_ex(struct e1000_hw *hw,
-                       uint32_t reg_addr,
-                       uint16_t phy_data)
-{
-       uint32_t i;
-       uint32_t mdic = 0;
-       const uint32_t phy_addr = 1;
-       
-       DEBUGFUNC("e1000_write_phy_reg_ex");
-       
-       if(reg_addr > MAX_PHY_REG_ADDRESS) {
-               DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
-               return -E1000_ERR_PARAM;
-       }
-       
-       if(hw->mac_type > e1000_82543) {
-               /* Set up Op-code, Phy Address, register address, and data intended
-                * for the PHY register in the MDI Control register.  The MAC will take
-                * care of interfacing with the PHY to send the desired data.
-                */
-               mdic = (((uint32_t) phy_data) |
-                       (reg_addr << E1000_MDIC_REG_SHIFT) |
-                       (phy_addr << E1000_MDIC_PHY_SHIFT) | 
-                       (E1000_MDIC_OP_WRITE));
-               
-               E1000_WRITE_REG(hw, MDIC, mdic);
-               
-               /* Poll the ready bit to see if the MDI read completed */
-               for(i = 0; i < 640; i++) {
-                       udelay(5);
-                       mdic = E1000_READ_REG(hw, MDIC);
-                       if(mdic & E1000_MDIC_READY) break;
-               }
-               if(!(mdic & E1000_MDIC_READY)) {
-                       DEBUGOUT("MDI Write did not complete\n");
-                       return -E1000_ERR_PHY;
-               }
-       } else {
-               /* We'll need to use the SW defined pins to shift the write command
-                * out to the PHY. We first send a preamble to the PHY to signal the
-                * beginning of the MII instruction.  This is done by sending 32 
-                * consecutive "1" bits.
-                */
-               e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
-               
-               /* Now combine the remaining required fields that will indicate a 
-                * write operation. We use this method instead of calling the
-                * e1000_shift_out_mdi_bits routine for each field in the command. The
-                * format of a MII write instruction is as follows:
-                * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
-                */
-               mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
-                       (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
-               mdic <<= 16;
-               mdic |= (uint32_t) phy_data;
-               
-               e1000_shift_out_mdi_bits(hw, mdic, 32);
-       }
-
-       return E1000_SUCCESS;
-}
-
-/******************************************************************************
-* Returns the PHY to the power-on reset state
-*
-* hw - Struct containing variables accessed by shared code
-******************************************************************************/
-static void
-e1000_phy_hw_reset(struct e1000_hw *hw)
-{
-       uint32_t ctrl, ctrl_ext;
-
-       DEBUGFUNC("e1000_phy_hw_reset");
-       
-       DEBUGOUT("Resetting Phy...\n");
-       
-       if(hw->mac_type > e1000_82543) {
-               /* Read the device control register and assert the E1000_CTRL_PHY_RST
-                * bit. Then, take it out of reset.
-                */
-               ctrl = E1000_READ_REG(hw, CTRL);
-               E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
-               E1000_WRITE_FLUSH(hw);
-               mdelay(10);
-               E1000_WRITE_REG(hw, CTRL, ctrl);
-               E1000_WRITE_FLUSH(hw);
-       } else {
-               /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
-                * bit to put the PHY into reset. Then, take it out of reset.
-                */
-               ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
-               ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
-               ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
-               E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
-               E1000_WRITE_FLUSH(hw);
-               mdelay(10);
-               ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
-               E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
-               E1000_WRITE_FLUSH(hw);
-       }
-       udelay(150);
-}
-
-/******************************************************************************
-* Resets the PHY
-*
-* hw - Struct containing variables accessed by shared code
-*
-* Sets bit 15 of the MII Control regiser
-******************************************************************************/
-static int 
-e1000_phy_reset(struct e1000_hw *hw)
-{
-       int32_t ret_val;
-       uint16_t phy_data;
-
-       DEBUGFUNC("e1000_phy_reset");
-
-       if(hw->mac_type != e1000_82541_rev_2) {
-               if((ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data)))
-                       return ret_val;
-               
-               phy_data |= MII_CR_RESET;
-               if((ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data)))
-                       return ret_val;
-               
-               udelay(1);
-       } else e1000_phy_hw_reset(hw);
-
-       if(hw->phy_type == e1000_phy_igp)
-               e1000_phy_init_script(hw);
-
-       return E1000_SUCCESS;
-}
-
-/******************************************************************************
-* Probes the expected PHY address for known PHY IDs
-*
-* hw - Struct containing variables accessed by shared code
-******************************************************************************/
-static int
-e1000_detect_gig_phy(struct e1000_hw *hw)
-{
-       int32_t phy_init_status, ret_val;
-       uint16_t phy_id_high, phy_id_low;
-       boolean_t match = FALSE;
-
-       DEBUGFUNC("e1000_detect_gig_phy");
-       
-       /* Read the PHY ID Registers to identify which PHY is onboard. */
-       if((ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high)))
-               return ret_val;
-
-       hw->phy_id = (uint32_t) (phy_id_high << 16);
-       udelay(20);
-       if((ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low)))
-               return ret_val;
-       
-       hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
-#ifdef LINUX_DRIVER
-       hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
-#endif
-       
-       switch(hw->mac_type) {
-       case e1000_82543:
-               if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
-               break;
-       case e1000_82544:
-               if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
-               break;
-       case e1000_82540:
-       case e1000_82545:
-       case e1000_82545_rev_3:
-       case e1000_82546:
-       case e1000_82546_rev_3:
-               if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
-               break;
-       case e1000_82541:
-       case e1000_82541_rev_2:
-       case e1000_82547:
-       case e1000_82547_rev_2:
-               if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
-               break;
-       default:
-               DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
-               return -E1000_ERR_CONFIG;
-       }
-       phy_init_status = e1000_set_phy_type(hw);
-
-       if ((match) && (phy_init_status == E1000_SUCCESS)) {
-               DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
-               return E1000_SUCCESS;
-       }
-       DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
-       return -E1000_ERR_PHY;
-}
-
-/******************************************************************************
- * Sets up eeprom variables in the hw struct.  Must be called after mac_type
- * is configured.
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
-static void
-e1000_init_eeprom_params(struct e1000_hw *hw)
-{
-       struct e1000_eeprom_info *eeprom = &hw->eeprom;
-       uint32_t eecd = E1000_READ_REG(hw, EECD);
-       uint16_t eeprom_size;
-
-       DEBUGFUNC("e1000_init_eeprom_params");
-
-       switch (hw->mac_type) {
-       case e1000_82542_rev2_0:
-       case e1000_82542_rev2_1:
-       case e1000_82543:
-       case e1000_82544:
-               eeprom->type = e1000_eeprom_microwire;
-               eeprom->word_size = 64;
-               eeprom->opcode_bits = 3;
-               eeprom->address_bits = 6;
-               eeprom->delay_usec = 50;
-               break;
-       case e1000_82540:
-       case e1000_82545:
-       case e1000_82545_rev_3:
-       case e1000_82546:
-       case e1000_82546_rev_3:
-               eeprom->type = e1000_eeprom_microwire;
-               eeprom->opcode_bits = 3;
-               eeprom->delay_usec = 50;
-               if(eecd & E1000_EECD_SIZE) {
-                       eeprom->word_size = 256;
-                       eeprom->address_bits = 8;
-               } else {
-                       eeprom->word_size = 64;
-                       eeprom->address_bits = 6;
-               }
-               break;
-       case e1000_82541:
-       case e1000_82541_rev_2:
-       case e1000_82547:
-       case e1000_82547_rev_2:
-               if (eecd & E1000_EECD_TYPE) {
-                       eeprom->type = e1000_eeprom_spi;
-                       if (eecd & E1000_EECD_ADDR_BITS) {
-                               eeprom->page_size = 32;
-                               eeprom->address_bits = 16;
-                       } else {
-                               eeprom->page_size = 8;
-                               eeprom->address_bits = 8;
-                       }
-               } else {
-                       eeprom->type = e1000_eeprom_microwire;
-                       eeprom->opcode_bits = 3;
-                       eeprom->delay_usec = 50;
-                       if (eecd & E1000_EECD_ADDR_BITS) {
-                               eeprom->word_size = 256;
-                               eeprom->address_bits = 8;
-                       } else {
-                               eeprom->word_size = 64;
-                               eeprom->address_bits = 6;
-                       }
-               }
-               break;
-       default:
-               eeprom->type = e1000_eeprom_spi;
-               if (eecd & E1000_EECD_ADDR_BITS) {
-                       eeprom->page_size = 32;
-                       eeprom->address_bits = 16;
-               } else {
-                       eeprom->page_size = 8;
-                       eeprom->address_bits = 8;
-               }
-               break;
-       }
-
-       if (eeprom->type == e1000_eeprom_spi) {
-               eeprom->opcode_bits = 8;
-               eeprom->delay_usec = 1;
-               eeprom->word_size = 64;
-               if (e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size) == 0) {
-                       eeprom_size &= EEPROM_SIZE_MASK;
-
-                       switch (eeprom_size) {
-                       case EEPROM_SIZE_16KB:
-                               eeprom->word_size = 8192;
-                               break;
-                       case EEPROM_SIZE_8KB:
-                               eeprom->word_size = 4096;
-                               break;
-                       case EEPROM_SIZE_4KB:
-                               eeprom->word_size = 2048;
-                               break;
-                       case EEPROM_SIZE_2KB:
-                               eeprom->word_size = 1024;
-                               break;
-                       case EEPROM_SIZE_1KB:
-                               eeprom->word_size = 512;
-                               break;
-                       case EEPROM_SIZE_512B:
-                               eeprom->word_size = 256;
-                               break;
-                       case EEPROM_SIZE_128B:
-                       default:
-                               break;
-                       }
-               }
-       }
-}
-
-/******************************************************************************
- * Raises the EEPROM's clock input.
- *
- * hw - Struct containing variables accessed by shared code
- * eecd - EECD's current value
- *****************************************************************************/
-static void
-e1000_raise_ee_clk(struct e1000_hw *hw,
-                   uint32_t *eecd)
-{
-       /* Raise the clock input to the EEPROM (by setting the SK bit), and then
-        * wait <delay> microseconds.
-        */
-       *eecd = *eecd | E1000_EECD_SK;
-       E1000_WRITE_REG(hw, EECD, *eecd);
-       E1000_WRITE_FLUSH(hw);
-       udelay(hw->eeprom.delay_usec);
-}
-
-/******************************************************************************
- * Lowers the EEPROM's clock input.
- *
- * hw - Struct containing variables accessed by shared code 
- * eecd - EECD's current value
- *****************************************************************************/
-static void
-e1000_lower_ee_clk(struct e1000_hw *hw,
-                   uint32_t *eecd)
-{
-       /* Lower the clock input to the EEPROM (by clearing the SK bit), and then 
-        * wait 50 microseconds. 
-        */
-       *eecd = *eecd & ~E1000_EECD_SK;
-       E1000_WRITE_REG(hw, EECD, *eecd);
-       E1000_WRITE_FLUSH(hw);
-       udelay(hw->eeprom.delay_usec);
-}
-
-/******************************************************************************
- * Shift data bits out to the EEPROM.
- *
- * hw - Struct containing variables accessed by shared code
- * data - data to send to the EEPROM
- * count - number of bits to shift out
- *****************************************************************************/
-static void
-e1000_shift_out_ee_bits(struct e1000_hw *hw,
-                        uint16_t data,
-                        uint16_t count)
-{
-       struct e1000_eeprom_info *eeprom = &hw->eeprom;
-       uint32_t eecd;
-       uint32_t mask;
-       
-       /* We need to shift "count" bits out to the EEPROM. So, value in the
-        * "data" parameter will be shifted out to the EEPROM one bit at a time.
-        * In order to do this, "data" must be broken down into bits. 
-        */
-       mask = 0x01 << (count - 1);
-       eecd = E1000_READ_REG(hw, EECD);
-       if (eeprom->type == e1000_eeprom_microwire) {
-               eecd &= ~E1000_EECD_DO;
-       } else if (eeprom->type == e1000_eeprom_spi) {
-               eecd |= E1000_EECD_DO;
-       }
-       do {
-               /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
-                * and then raising and then lowering the clock (the SK bit controls
-                * the clock input to the EEPROM).  A "0" is shifted out to the EEPROM
-                * by setting "DI" to "0" and then raising and then lowering the clock.
-                */
-               eecd &= ~E1000_EECD_DI;
-               
-               if(data & mask)
-                       eecd |= E1000_EECD_DI;
-               
-               E1000_WRITE_REG(hw, EECD, eecd);
-               E1000_WRITE_FLUSH(hw);
-               
-               udelay(eeprom->delay_usec);
-               
-               e1000_raise_ee_clk(hw, &eecd);
-               e1000_lower_ee_clk(hw, &eecd);
-               
-               mask = mask >> 1;
-               
-       } while(mask);
-
-       /* We leave the "DI" bit set to "0" when we leave this routine. */
-       eecd &= ~E1000_EECD_DI;
-       E1000_WRITE_REG(hw, EECD, eecd);
-}
-
-/******************************************************************************
- * Shift data bits in from the EEPROM
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
-static uint16_t
-e1000_shift_in_ee_bits(struct e1000_hw *hw,
-                       uint16_t count)
-{
-       uint32_t eecd;
-       uint32_t i;
-       uint16_t data;
-       
-       /* In order to read a register from the EEPROM, we need to shift 'count' 
-        * bits in from the EEPROM. Bits are "shifted in" by raising the clock
-        * input to the EEPROM (setting the SK bit), and then reading the value of
-        * the "DO" bit.  During this "shifting in" process the "DI" bit should
-        * always be clear.
-        */
-       
-       eecd = E1000_READ_REG(hw, EECD);
-       
-       eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
-       data = 0;
-       
-       for(i = 0; i < count; i++) {
-               data = data << 1;
-               e1000_raise_ee_clk(hw, &eecd);
-               
-               eecd = E1000_READ_REG(hw, EECD);
-               
-               eecd &= ~(E1000_EECD_DI);
-               if(eecd & E1000_EECD_DO)
-                       data |= 1;
-               
-               e1000_lower_ee_clk(hw, &eecd);
-       }
-       
-       return data;
-}
-
-/******************************************************************************
- * Prepares EEPROM for access
- *
- * hw - Struct containing variables accessed by shared code
- *
- * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 
- * function should be called before issuing a command to the EEPROM.
- *****************************************************************************/
-static int32_t
-e1000_acquire_eeprom(struct e1000_hw *hw)
-{
-       struct e1000_eeprom_info *eeprom = &hw->eeprom;
-       uint32_t eecd, i=0;
-
-       eecd = E1000_READ_REG(hw, EECD);
-
-       /* Request EEPROM Access */
-       if(hw->mac_type > e1000_82544) {
-               eecd |= E1000_EECD_REQ;
-               E1000_WRITE_REG(hw, EECD, eecd);
-               eecd = E1000_READ_REG(hw, EECD);
-               while((!(eecd & E1000_EECD_GNT)) &&
-                     (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
-                       i++;
-                       udelay(5);
-                       eecd = E1000_READ_REG(hw, EECD);
-               }
-               if(!(eecd & E1000_EECD_GNT)) {
-                       eecd &= ~E1000_EECD_REQ;
-                       E1000_WRITE_REG(hw, EECD, eecd);
-                       DEBUGOUT("Could not acquire EEPROM grant\n");
-                       return -E1000_ERR_EEPROM;
-               }
-       }
-
-       /* Setup EEPROM for Read/Write */
-
-       if (eeprom->type == e1000_eeprom_microwire) {
-               /* Clear SK and DI */
-               eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
-               E1000_WRITE_REG(hw, EECD, eecd);
-
-               /* Set CS */
-               eecd |= E1000_EECD_CS;
-               E1000_WRITE_REG(hw, EECD, eecd);
-       } else if (eeprom->type == e1000_eeprom_spi) {
-               /* Clear SK and CS */
-               eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
-               E1000_WRITE_REG(hw, EECD, eecd);
-               udelay(1);
-       }
-
-       return E1000_SUCCESS;
-}
-
-/******************************************************************************
- * Returns EEPROM to a "standby" state
- * 
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
-static void
-e1000_standby_eeprom(struct e1000_hw *hw)
-{
-       struct e1000_eeprom_info *eeprom = &hw->eeprom;
-       uint32_t eecd;
-       
-       eecd = E1000_READ_REG(hw, EECD);
-
-       if(eeprom->type == e1000_eeprom_microwire) {
-
-               /* Deselect EEPROM */
-               eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
-               E1000_WRITE_REG(hw, EECD, eecd);
-               E1000_WRITE_FLUSH(hw);
-               udelay(eeprom->delay_usec);
-       
-               /* Clock high */
-               eecd |= E1000_EECD_SK;
-               E1000_WRITE_REG(hw, EECD, eecd);
-               E1000_WRITE_FLUSH(hw);
-               udelay(eeprom->delay_usec);
-       
-               /* Select EEPROM */
-               eecd |= E1000_EECD_CS;
-               E1000_WRITE_REG(hw, EECD, eecd);
-               E1000_WRITE_FLUSH(hw);
-               udelay(eeprom->delay_usec);
-
-               /* Clock low */
-               eecd &= ~E1000_EECD_SK;
-               E1000_WRITE_REG(hw, EECD, eecd);
-               E1000_WRITE_FLUSH(hw);
-               udelay(eeprom->delay_usec);
-       } else if(eeprom->type == e1000_eeprom_spi) {
-               /* Toggle CS to flush commands */
-               eecd |= E1000_EECD_CS;
-               E1000_WRITE_REG(hw, EECD, eecd);
-               E1000_WRITE_FLUSH(hw);
-               udelay(eeprom->delay_usec);
-               eecd &= ~E1000_EECD_CS;
-               E1000_WRITE_REG(hw, EECD, eecd);
-               E1000_WRITE_FLUSH(hw);
-               udelay(eeprom->delay_usec);
-       }
-}
-
-/******************************************************************************
- * Terminates a command by inverting the EEPROM's chip select pin
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
-static void
-e1000_release_eeprom(struct e1000_hw *hw)
-{
-       uint32_t eecd;
-
-       eecd = E1000_READ_REG(hw, EECD);
-
-       if (hw->eeprom.type == e1000_eeprom_spi) {
-               eecd |= E1000_EECD_CS;  /* Pull CS high */
-               eecd &= ~E1000_EECD_SK; /* Lower SCK */
-
-               E1000_WRITE_REG(hw, EECD, eecd);
-
-               udelay(hw->eeprom.delay_usec);
-       } else if(hw->eeprom.type == e1000_eeprom_microwire) {
-               /* cleanup eeprom */
-
-               /* CS on Microwire is active-high */
-               eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
-
-               E1000_WRITE_REG(hw, EECD, eecd);
-
-               /* Rising edge of clock */
-               eecd |= E1000_EECD_SK;
-               E1000_WRITE_REG(hw, EECD, eecd);
-               E1000_WRITE_FLUSH(hw);
-               udelay(hw->eeprom.delay_usec);
-
-               /* Falling edge of clock */
-               eecd &= ~E1000_EECD_SK;
-               E1000_WRITE_REG(hw, EECD, eecd);
-               E1000_WRITE_FLUSH(hw);
-               udelay(hw->eeprom.delay_usec);
-       }
-
-       /* Stop requesting EEPROM access */
-       if(hw->mac_type > e1000_82544) {
-               eecd &= ~E1000_EECD_REQ;
-               E1000_WRITE_REG(hw, EECD, eecd);
-       }
-}
-
-/******************************************************************************
- * Reads a 16 bit word from the EEPROM.
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
-static int32_t
-e1000_spi_eeprom_ready(struct e1000_hw *hw)
-{
-       uint16_t retry_count = 0;
-       uint8_t spi_stat_reg;
-
-       /* Read "Status Register" repeatedly until the LSB is cleared.  The
-        * EEPROM will signal that the command has been completed by clearing
-        * bit 0 of the internal status register.  If it's not cleared within
-        * 5 milliseconds, then error out.
-        */
-       retry_count = 0;
-       do {
-               e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
-               hw->eeprom.opcode_bits);
-               spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
-               if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
-                       break;
-
-               udelay(5);
-               retry_count += 5;
-
-       } while(retry_count < EEPROM_MAX_RETRY_SPI);
-
-       /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
-        * only 0-5mSec on 5V devices)
-        */
-       if(retry_count >= EEPROM_MAX_RETRY_SPI) {
-               DEBUGOUT("SPI EEPROM Status error\n");
-               return -E1000_ERR_EEPROM;
-       }
-
-       return E1000_SUCCESS;
-}
-
-/******************************************************************************
- * Reads a 16 bit word from the EEPROM.
- *
- * hw - Struct containing variables accessed by shared code
- * offset - offset of  word in the EEPROM to read
- * data - word read from the EEPROM
- * words - number of words to read
- *****************************************************************************/
-static int
-e1000_read_eeprom(struct e1000_hw *hw,
-                  uint16_t offset,
-                 uint16_t words,
-                  uint16_t *data)
-{
-       struct e1000_eeprom_info *eeprom = &hw->eeprom;
-       uint32_t i = 0;
-       
-       DEBUGFUNC("e1000_read_eeprom");
-
-       /* A check for invalid values:  offset too large, too many words, and not
-        * enough words.
-        */
-       if((offset > eeprom->word_size) || (words > eeprom->word_size - offset) ||
-          (words == 0)) {
-               DEBUGOUT("\"words\" parameter out of bounds\n");
-               return -E1000_ERR_EEPROM;
-       }
-
-       /*  Prepare the EEPROM for reading  */
-       if(e1000_acquire_eeprom(hw) != E1000_SUCCESS)
-               return -E1000_ERR_EEPROM;
-
-       if(eeprom->type == e1000_eeprom_spi) {
-               uint16_t word_in;
-               uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
-
-               if(e1000_spi_eeprom_ready(hw)) {
-                       e1000_release_eeprom(hw);
-                       return -E1000_ERR_EEPROM;
-               }
-
-               e1000_standby_eeprom(hw);
-
-               /* Some SPI eeproms use the 8th address bit embedded in the opcode */
-               if((eeprom->address_bits == 8) && (offset >= 128))
-                       read_opcode |= EEPROM_A8_OPCODE_SPI;
-
-               /* Send the READ command (opcode + addr)  */
-               e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
-               e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
-
-               /* Read the data.  The address of the eeprom internally increments with
-                * each byte (spi) being read, saving on the overhead of eeprom setup
-                * and tear-down.  The address counter will roll over if reading beyond
-                * the size of the eeprom, thus allowing the entire memory to be read
-                * starting from any offset. */
-               for (i = 0; i < words; i++) {
-                       word_in = e1000_shift_in_ee_bits(hw, 16);
-                       data[i] = (word_in >> 8) | (word_in << 8);
-               }
-       } else if(eeprom->type == e1000_eeprom_microwire) {
-               for (i = 0; i < words; i++) {
-                       /*  Send the READ command (opcode + addr)  */
-                       e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
-                                               eeprom->opcode_bits);
-                       e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
-                                               eeprom->address_bits);
-
-                       /* Read the data.  For microwire, each word requires the overhead
-                        * of eeprom setup and tear-down. */
-                       data[i] = e1000_shift_in_ee_bits(hw, 16);
-                       e1000_standby_eeprom(hw);
-               }
-       }
-
-       /* End this read operation */
-       e1000_release_eeprom(hw);
-
-       return E1000_SUCCESS;
-}
-
-/******************************************************************************
- * Verifies that the EEPROM has a valid checksum
- * 
- * hw - Struct containing variables accessed by shared code
- *
- * Reads the first 64 16 bit words of the EEPROM and sums the values read.
- * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
- * valid.
- *****************************************************************************/
-static int
-e1000_validate_eeprom_checksum(struct e1000_hw *hw)
-{
-       uint16_t checksum = 0;
-       uint16_t i, eeprom_data;
-
-       DEBUGFUNC("e1000_validate_eeprom_checksum");
-
-       for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
-               if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
-                       DEBUGOUT("EEPROM Read Error\n");
-                       return -E1000_ERR_EEPROM;
-               }
-               checksum += eeprom_data;
-       }
-       
-       if(checksum == (uint16_t) EEPROM_SUM)
-               return E1000_SUCCESS;
-       else {
-               DEBUGOUT("EEPROM Checksum Invalid\n");    
-               return -E1000_ERR_EEPROM;
-       }
-}
-
-/******************************************************************************
- * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
- * second function of dual function devices
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
-static int 
-e1000_read_mac_addr(struct e1000_hw *hw)
-{
-       uint16_t offset;
-       uint16_t eeprom_data;
-       int i;
-
-       DEBUGFUNC("e1000_read_mac_addr");
-
-       for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
-               offset = i >> 1;
-               if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
-                       DEBUGOUT("EEPROM Read Error\n");
-                       return -E1000_ERR_EEPROM;
-               }
-               hw->mac_addr[i] = eeprom_data & 0xff;
-               hw->mac_addr[i+1] = (eeprom_data >> 8) & 0xff;
-       }
-       if(((hw->mac_type == e1000_82546) || (hw->mac_type == e1000_82546_rev_3)) &&
-               (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1))
-               /* Invert the last bit if this is the second device */
-               hw->mac_addr[5] ^= 1;
-       return E1000_SUCCESS;
-}
-
-/******************************************************************************
- * Initializes receive address filters.
- *
- * hw - Struct containing variables accessed by shared code 
- *
- * Places the MAC address in receive address register 0 and clears the rest
- * of the receive addresss registers. Clears the multicast table. Assumes
- * the receiver is in reset when the routine is called.
- *****************************************************************************/
-static void
-e1000_init_rx_addrs(struct e1000_hw *hw)
-{
-       uint32_t i;
-       uint32_t addr_low;
-       uint32_t addr_high;
-       
-       DEBUGFUNC("e1000_init_rx_addrs");
-       
-       /* Setup the receive address. */
-       DEBUGOUT("Programming MAC Address into RAR[0]\n");
-       addr_low = (hw->mac_addr[0] |
-               (hw->mac_addr[1] << 8) |
-               (hw->mac_addr[2] << 16) | (hw->mac_addr[3] << 24));
-       
-       addr_high = (hw->mac_addr[4] |
-               (hw->mac_addr[5] << 8) | E1000_RAH_AV);
-       
-       E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
-       E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
-       
-       /* Zero out the other 15 receive addresses. */
-       DEBUGOUT("Clearing RAR[1-15]\n");
-       for(i = 1; i < E1000_RAR_ENTRIES; i++) {
-               E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
-               E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
-       }
-}
-
-/******************************************************************************
- * Clears the VLAN filer table
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
-static void
-e1000_clear_vfta(struct e1000_hw *hw)
-{
-       uint32_t offset;
-    
-       for(offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
-               E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
-}
-
-
-/******************************************************************************
- * Functions from e1000_main.c of the linux driver
- ******************************************************************************/
-
-/**
- * e1000_reset - Reset the adapter
- */
-
-static int
-e1000_reset(struct e1000_hw *hw)
-{
-       uint32_t pba;
-       /* Repartition Pba for greater than 9k mtu
-        * To take effect CTRL.RST is required.
-        */
-
-       if(hw->mac_type < e1000_82547) {
-               pba = E1000_PBA_48K;
-       } else {
-               pba = E1000_PBA_30K;
-       }
-       E1000_WRITE_REG(hw, PBA, pba);
-
-       /* flow control settings */
-#if 0
-       hw->fc_high_water = FC_DEFAULT_HI_THRESH;
-       hw->fc_low_water = FC_DEFAULT_LO_THRESH;
-       hw->fc_pause_time = FC_DEFAULT_TX_TIMER;
-       hw->fc_send_xon = 1;
-       hw->fc = hw->original_fc;
-#endif
-       
-       e1000_reset_hw(hw);
-       if(hw->mac_type >= e1000_82544)
-               E1000_WRITE_REG(hw, WUC, 0);
-       return e1000_init_hw(hw);
-}
-
-/**
- * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
- * @adapter: board private structure to initialize
- *
- * e1000_sw_init initializes the Adapter private data structure.
- * Fields are initialized based on PCI device information and
- * OS network device settings (MTU size).
- **/
-
-static int 
-e1000_sw_init(struct pci_device *pdev, struct e1000_hw *hw)
-{
-       int result;
-
-       /* PCI config space info */
-       pci_read_config_word(pdev, PCI_VENDOR_ID, &hw->vendor_id);
-       pci_read_config_word(pdev, PCI_DEVICE_ID, &hw->device_id);
-       pci_read_config_byte(pdev, PCI_REVISION, &hw->revision_id);
-#if 0
-       pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID,
-                             &hw->subsystem_vendor_id);
-       pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
-#endif
-
-       pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
-
-       /* identify the MAC */
-
-       result = e1000_set_mac_type(hw);
-       if (result) {
-               E1000_ERR("Unknown MAC Type\n");
-               return result;
-       }
-
-       /* initialize eeprom parameters */
-
-       e1000_init_eeprom_params(hw);
-
-#if 0
-       if((hw->mac_type == e1000_82541) ||
-          (hw->mac_type == e1000_82547) ||
-          (hw->mac_type == e1000_82541_rev_2) ||
-          (hw->mac_type == e1000_82547_rev_2))
-               hw->phy_init_script = 1;
-#endif
-
-       e1000_set_media_type(hw);
-
-#if 0
-       if(hw->mac_type < e1000_82543)
-               hw->report_tx_early = 0;
-       else
-               hw->report_tx_early = 1;
-
-       hw->wait_autoneg_complete = FALSE;
-#endif
-       hw->tbi_compatibility_en = TRUE;
-#if 0
-       hw->adaptive_ifs = TRUE;
-
-       /* Copper options */
-
-       if(hw->media_type == e1000_media_type_copper) {
-               hw->mdix = AUTO_ALL_MODES;
-               hw->disable_polarity_correction = FALSE;
-               hw->master_slave = E1000_MASTER_SLAVE;
-       }
-#endif
-       return E1000_SUCCESS;
-}
-
-
-/******************************************************************************
- * Functions not present in the linux driver
- ******************************************************************************/
-
-static void fill_rx (void)
-{
-       struct e1000_rx_desc *rd;
-       rx_last = rx_tail;
-       rd = rx_base + rx_tail;
-       rx_tail = (rx_tail + 1) % 8;
-       memset (rd, 0, 16);
-       rd->buffer_addr = virt_to_bus(&e1000_bufs.packet);
-       E1000_WRITE_REG (&hw, RDT, rx_tail);
-}
-
-static void init_descriptor (void)
-{
-       unsigned long ptr;
-       unsigned long tctl;
-
-       ptr = virt_to_phys(e1000_bufs.tx_pool);
-       if (ptr & 0xf)
-               ptr = (ptr + 0x10) & (~0xf);
-
-       tx_base = phys_to_virt(ptr);
-
-       E1000_WRITE_REG (&hw, TDBAL, virt_to_bus(tx_base));
-       E1000_WRITE_REG (&hw, TDBAH, 0);
-       E1000_WRITE_REG (&hw, TDLEN, 128);
-
-       /* Setup the HW Tx Head and Tail descriptor pointers */
-
-       E1000_WRITE_REG (&hw, TDH, 0);
-       E1000_WRITE_REG (&hw, TDT, 0);
-       tx_tail = 0;
-
-       /* Program the Transmit Control Register */
-
-#ifdef LINUX_DRIVER_TCTL
-       tctl = E1000_READ_REG(&hw, TCTL);
-
-       tctl &= ~E1000_TCTL_CT;
-       tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
-               (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
-#else
-       tctl = E1000_TCTL_PSP | E1000_TCTL_EN |
-               (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT) | 
-               (E1000_HDX_COLLISION_DISTANCE << E1000_COLD_SHIFT);
-#endif
-
-       E1000_WRITE_REG (&hw, TCTL, tctl);
-
-       e1000_config_collision_dist(&hw);
-
-
-       rx_tail = 0;
-       /* disable receive */
-       E1000_WRITE_REG (&hw, RCTL, 0);
-       ptr = virt_to_phys(e1000_bufs.rx_pool);
-       if (ptr & 0xf)
-               ptr = (ptr + 0x10) & (~0xf);
-       rx_base = phys_to_virt(ptr);
-
-       /* Setup the Base and Length of the Rx Descriptor Ring */
-
-       E1000_WRITE_REG (&hw, RDBAL, virt_to_bus(rx_base));
-       E1000_WRITE_REG (&hw, RDBAH, 0);
-
-       E1000_WRITE_REG (&hw, RDLEN, 128);
-
-       /* Setup the HW Rx Head and Tail Descriptor Pointers */
-       E1000_WRITE_REG (&hw, RDH, 0);
-       E1000_WRITE_REG (&hw, RDT, 0);
-
-       E1000_WRITE_REG (&hw, RCTL, 
-               E1000_RCTL_EN | 
-               E1000_RCTL_BAM | 
-               E1000_RCTL_SZ_2048 | 
-               E1000_RCTL_MPE);
-       fill_rx();
-}
-
-
-
-/**************************************************************************
-POLL - Wait for a frame
-***************************************************************************/
-static int
-e1000_poll (struct nic *nic, int retrieve)
-{
-       /* return true if there's an ethernet packet ready to read */
-       /* nic->packet should contain data on return */
-       /* nic->packetlen should contain length of data */
-       struct e1000_rx_desc *rd;
-       uint32_t icr;
-
-       rd = rx_base + rx_last;
-       if (!rd->status & E1000_RXD_STAT_DD)
-               return 0;
-
-       if ( ! retrieve ) return 1;
-
-       //      printf("recv: packet %! -> %! len=%d \n", packet+6, packet,rd->Length);
-       memcpy (nic->packet, e1000_bufs.packet, rd->length);
-       nic->packetlen = rd->length;
-       fill_rx ();
-
-       /* Acknowledge interrupt. */
-       icr = E1000_READ_REG(&hw, ICR);
-
-       return 1;
-}
-
-/**************************************************************************
-TRANSMIT - Transmit a frame
-***************************************************************************/
-static void
-e1000_transmit (struct nic *nic, const char *d,        /* Destination */
-                   unsigned int type,  /* Type */
-                   unsigned int size,  /* size */
-                   const char *p)      /* Packet */
-{
-       /* send the packet to destination */
-       struct eth_hdr {
-               unsigned char dst_addr[ETH_ALEN];
-               unsigned char src_addr[ETH_ALEN];
-               unsigned short type;
-       } hdr;
-       struct e1000_tx_desc *txhd;     /* header */
-       struct e1000_tx_desc *txp;      /* payload */
-       DEBUGFUNC("send");
-
-       memcpy (&hdr.dst_addr, d, ETH_ALEN);
-       memcpy (&hdr.src_addr, nic->node_addr, ETH_ALEN);
-
-       hdr.type = htons (type);
-       txhd = tx_base + tx_tail;
-       tx_tail = (tx_tail + 1) % 8;
-       txp = tx_base + tx_tail;
-       tx_tail = (tx_tail + 1) % 8;
-
-       txhd->buffer_addr = virt_to_bus (&hdr);
-       txhd->lower.data = sizeof (hdr);
-       txhd->upper.data = 0;
-
-       txp->buffer_addr = virt_to_bus(p);
-       txp->lower.data = E1000_TXD_CMD_RPS | E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS | size;
-       txp->upper.data = 0;
-
-       E1000_WRITE_REG (&hw, TDT, tx_tail);
-       while (!(txp->upper.data & E1000_TXD_STAT_DD)) {
-               udelay(10);     /* give the nic a chance to write to the register */
-       }
-       DEBUGFUNC("send end");
-}
-
-
-/**************************************************************************
-DISABLE - Turn off ethernet interface
-***************************************************************************/
-static void e1000_disable ( struct nic *nic __unused ) {
-       /* Clear the transmit ring */
-       E1000_WRITE_REG (&hw, TDH, 0);
-       E1000_WRITE_REG (&hw, TDT, 0);
-
-       /* Clear the receive ring */
-       E1000_WRITE_REG (&hw, RDH, 0);
-       E1000_WRITE_REG (&hw, RDT, 0);
-
-       /* put the card in its initial state */
-       switch(hw.mac_type) {
-               case e1000_82544:
-               case e1000_82540:
-               case e1000_82545:
-               case e1000_82546:
-               case e1000_82541:
-               case e1000_82541_rev_2:
-                       /* These controllers can't ack the 64-bit write when issuing the
-                        * reset, so use IO-mapping as a workaround to issue the reset */
-                       E1000_WRITE_REG_IO(&hw, CTRL, E1000_CTRL_RST);
-                       break;
-               case e1000_82545_rev_3:
-               case e1000_82546_rev_3:
-                       /* Reset is performed on a shadow of the control register */
-                       E1000_WRITE_REG(&hw, CTRL_DUP, E1000_CTRL_RST);
-                       break;
-               default:
-                       E1000_WRITE_REG(&hw, CTRL, E1000_CTRL_RST);
-                       break;
-       }
-
-       /* Turn off the ethernet interface */
-       E1000_WRITE_REG (&hw, RCTL, 0);
-       E1000_WRITE_REG (&hw, TCTL, 0);
-       mdelay (10);
-
-       /* Unmap my window to the device */
-       iounmap(hw.hw_addr);
-}
-
-/**************************************************************************
-IRQ - Enable, Disable, or Force interrupts
-***************************************************************************/
-static void e1000_irq(struct nic *nic __unused, irq_action_t action)
-{
-       switch ( action ) {
-       case DISABLE :
-               E1000_WRITE_REG(&hw, IMC, ~0);
-               E1000_WRITE_FLUSH(&hw);
-               break;
-       case ENABLE :
-               E1000_WRITE_REG(&hw, IMS,
-                               E1000_IMS_RXT0 | E1000_IMS_RXSEQ);
-               E1000_WRITE_FLUSH(&hw);
-               break;
-       case FORCE :
-               E1000_WRITE_REG(&hw, ICS, E1000_ICS_RXT0);
-               break;
-       }
-}
-
-#define IORESOURCE_IO  0x00000100     /* Resource type */
-#define BAR_0          0
-#define BAR_1          1
-#define BAR_5          5
-
-/**************************************************************************
-PROBE - Look for an adapter, this routine's visible to the outside
-You should omit the last argument struct pci_device * for a non-PCI NIC
-***************************************************************************/
-static int e1000_probe ( struct nic *nic, struct pci_device *p ) {
-
-       unsigned long mmio_start, mmio_len;
-       int ret_val, i;
-
-       /* Initialize hw with default values */
-       memset(&hw, 0, sizeof(hw));
-       hw.pdev = p;
-
-#if 1
-       /* Are these variables needed? */
-       hw.fc                    = e1000_fc_none;
-#if 0
-       hw.original_fc           = e1000_fc_none;
-#endif
-       hw.autoneg_failed        = 0;
-#if 0
-       hw.get_link_status       = TRUE;
-#endif
-#endif
-
-       mmio_start = pci_bar_start(p, PCI_BASE_ADDRESS_0);
-       mmio_len   = pci_bar_size(p,  PCI_BASE_ADDRESS_0);
-       hw.hw_addr = ioremap(mmio_start, mmio_len);
-
-       for(i = BAR_1; i <= BAR_5; i++) {
-               if(pci_bar_size(p, i) == 0)
-                       continue;                
-               if(pci_find_capability(p, i) & IORESOURCE_IO) {
-                       hw.io_base = pci_bar_start(p, i);
-                       break;
-                }        
-       }
-
-       adjust_pci_device(p);
-
-       pci_fill_nic ( nic, p );
-
-       /* From Matt Hortman <mbhortman@acpthinclient.com> */
-       /* MAC and Phy settings */
-
-       /* setup the private structure */
-       if (e1000_sw_init(p, &hw) < 0) {
-               iounmap(hw.hw_addr);
-               return 0;
-       }
-
-       /* make sure the EEPROM is good */
-
-       if (e1000_validate_eeprom_checksum(&hw) < 0) {
-               printf ("The EEPROM Checksum Is Not Valid\n");
-               iounmap(hw.hw_addr);
-               return 0;
-       }
-
-       /* copy the MAC address out of the EEPROM */
-
-       e1000_read_mac_addr(&hw);
-       memcpy (nic->node_addr, hw.mac_addr, ETH_ALEN);
-       
-       /* reset the hardware with the new settings */
-
-       ret_val = e1000_reset(&hw);
-       if (ret_val < 0) {
-               if ((ret_val == -E1000_ERR_NOLINK) ||
-                       (ret_val == -E1000_ERR_TIMEOUT)) {
-                       E1000_ERR("Valid Link not detected\n");
-               } else {
-                       E1000_ERR("Hardware Initialization Failed\n");
-               }
-               iounmap(hw.hw_addr);
-               return 0;
-       }
-       init_descriptor();
-
-       /* point to NIC specific routines */
-       nic->nic_op     = &e1000_operations;
-
-       return 1;
-}
-
-static struct nic_operations e1000_operations = {
-       .connect        = dummy_connect,
-       .poll           = e1000_poll,
-       .transmit       = e1000_transmit,
-       .irq            = e1000_irq,
-
-};
-
-static struct pci_device_id e1000_nics[] = {
-PCI_ROM(0x8086, 0x1000, "e1000-82542",               "Intel EtherExpressPro1000"),
-PCI_ROM(0x8086, 0x1001, "e1000-82543gc-fiber",       "Intel EtherExpressPro1000 82543GC Fiber"),
-PCI_ROM(0x8086, 0x1004, "e1000-82543gc-copper",             "Intel EtherExpressPro1000 82543GC Copper"),
-PCI_ROM(0x8086, 0x1008, "e1000-82544ei-copper",      "Intel EtherExpressPro1000 82544EI Copper"),
-PCI_ROM(0x8086, 0x1009, "e1000-82544ei-fiber",       "Intel EtherExpressPro1000 82544EI Fiber"),
-PCI_ROM(0x8086, 0x100C, "e1000-82544gc-copper",      "Intel EtherExpressPro1000 82544GC Copper"),
-PCI_ROM(0x8086, 0x100D, "e1000-82544gc-lom",         "Intel EtherExpressPro1000 82544GC LOM"),
-PCI_ROM(0x8086, 0x100E, "e1000-82540em",            "Intel EtherExpressPro1000 82540EM"),
-PCI_ROM(0x8086, 0x100F, "e1000-82545em-copper",      "Intel EtherExpressPro1000 82545EM Copper"),
-PCI_ROM(0x8086, 0x1010, "e1000-82546eb-copper",      "Intel EtherExpressPro1000 82546EB Copper"),
-PCI_ROM(0x8086, 0x1011, "e1000-82545em-fiber",       "Intel EtherExpressPro1000 82545EM Fiber"),
-PCI_ROM(0x8086, 0x1012, "e1000-82546eb-fiber",              "Intel EtherExpressPro1000 82546EB Copper"),
-PCI_ROM(0x8086, 0x1013, "e1000-82541ei",            "Intel EtherExpressPro1000 82541EI"),
-PCI_ROM(0x8086, 0x1015, "e1000-82540em-lom",        "Intel EtherExpressPro1000 82540EM LOM"),
-PCI_ROM(0x8086, 0x1016, "e1000-82540ep-lom",        "Intel EtherExpressPro1000 82540EP LOM"),
-PCI_ROM(0x8086, 0x1017, "e1000-82540ep",            "Intel EtherExpressPro1000 82540EP"),
-PCI_ROM(0x8086, 0x1018, "e1000-82541ep",            "Intel EtherExpressPro1000 82541EP"),
-PCI_ROM(0x8086, 0x1019, "e1000-82547ei",            "Intel EtherExpressPro1000 82547EI"),
-PCI_ROM(0x8086, 0x101d, "e1000-82546eb-quad-copper", "Intel EtherExpressPro1000 82546EB Quad Copper"),
-PCI_ROM(0x8086, 0x101e, "e1000-82540ep-lp",         "Intel EtherExpressPro1000 82540EP LP"),
-PCI_ROM(0x8086, 0x1026, "e1000-82545gm-copper",             "Intel EtherExpressPro1000 82545GM Copper"),
-PCI_ROM(0x8086, 0x1027, "e1000-82545gm-fiber",      "Intel EtherExpressPro1000 82545GM Fiber"),
-PCI_ROM(0x8086, 0x1028, "e1000-82545gm-serdes",             "Intel EtherExpressPro1000 82545GM SERDES"),
-PCI_ROM(0x8086, 0x1075, "e1000-82547gi",            "Intel EtherExpressPro1000 82547GI"),
-PCI_ROM(0x8086, 0x1076, "e1000-82541gi",            "Intel EtherExpressPro1000 82541GI"),
-PCI_ROM(0x8086, 0x1077, "e1000-82541gi-mobile",             "Intel EtherExpressPro1000 82541GI Mobile"),
-PCI_ROM(0x8086, 0x1078, "e1000-82541er",            "Intel EtherExpressPro1000 82541ER"),
-PCI_ROM(0x8086, 0x1079, "e1000-82546gb-copper",             "Intel EtherExpressPro1000 82546GB Copper"),
-PCI_ROM(0x8086, 0x107a, "e1000-82546gb-fiber",      "Intel EtherExpressPro1000 82546GB Fiber"),
-PCI_ROM(0x8086, 0x107b, "e1000-82546gb-serdes",             "Intel EtherExpressPro1000 82546GB SERDES"),
-};
-
-PCI_DRIVER ( e1000_driver, e1000_nics, PCI_NO_CLASS );
-
-DRIVER ( "E1000", nic_driver, pci_driver, e1000_driver,
-        e1000_probe, e1000_disable );
diff --git a/src/drivers/net/e1000/e1000.h b/src/drivers/net/e1000/e1000.h
new file mode 100644 (file)
index 0000000..4d78f7d
--- /dev/null
@@ -0,0 +1,303 @@
+/*******************************************************************************
+
+  Intel PRO/1000 Linux driver
+  Copyright(c) 1999 - 2006 Intel Corporation.
+
+  This program is free software; you can redistribute it and/or modify it
+  under the terms and conditions of the GNU General Public License,
+  version 2, as published by the Free Software Foundation.
+
+  This program is distributed in the hope it will be useful, but WITHOUT
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+  more details.
+
+  You should have received a copy of the GNU General Public License along with
+  this program; if not, write to the Free Software Foundation, Inc.,
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+
+  The full GNU General Public License is included in this distribution in
+  the file called "COPYING".
+
+  Contact Information:
+  Linux NICS <linux.nics@intel.com>
+  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+
+*******************************************************************************/
+
+/* Linux PRO/1000 Ethernet Driver main header file */
+
+#ifndef _E1000_H_
+#define _E1000_H_
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <io.h>
+#include <errno.h>
+#include <timer.h>
+#include <byteswap.h>
+#include <gpxe/pci.h>
+#include <gpxe/malloc.h>
+#include <gpxe/if_ether.h>
+#include <gpxe/ethernet.h>
+#include <gpxe/iobuf.h>
+#include <gpxe/netdevice.h>
+
+#define BAR_0          0
+#define BAR_1          1
+#define BAR_5          5
+
+struct e1000_adapter;
+
+#include "e1000_hw.h"
+
+/* Supported Rx Buffer Sizes */
+#define E1000_RXBUFFER_128   128    /* Used for packet split */
+#define E1000_RXBUFFER_256   256    /* Used for packet split */
+#define E1000_RXBUFFER_512   512
+#define E1000_RXBUFFER_1024  1024
+#define E1000_RXBUFFER_2048  2048
+#define E1000_RXBUFFER_4096  4096
+#define E1000_RXBUFFER_8192  8192
+#define E1000_RXBUFFER_16384 16384
+
+/* SmartSpeed delimiters */
+#define E1000_SMARTSPEED_DOWNSHIFT 3
+#define E1000_SMARTSPEED_MAX       15
+
+/* Packet Buffer allocations */
+#define E1000_PBA_BYTES_SHIFT 0xA
+#define E1000_TX_HEAD_ADDR_SHIFT 7
+#define E1000_PBA_TX_MASK 0xFFFF0000
+
+/* Flow Control Watermarks */
+#define E1000_FC_HIGH_DIFF 0x1638  /* High: 5688 bytes below Rx FIFO size */
+#define E1000_FC_LOW_DIFF 0x1640   /* Low:  5696 bytes below Rx FIFO size */
+
+#define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */
+
+/* How many Tx Descriptors do we need to call netif_wake_queue ? */
+#define E1000_TX_QUEUE_WAKE    16
+/* How many Rx Buffers do we bundle into one write to the hardware ? */
+#define E1000_RX_BUFFER_WRITE  16      /* Must be power of 2 */
+
+#define AUTO_ALL_MODES            0
+#define E1000_EEPROM_82544_APM    0x0004
+#define E1000_EEPROM_ICH8_APME    0x0004
+#define E1000_EEPROM_APME         0x0400
+
+#ifndef E1000_MASTER_SLAVE
+/* Switch to override PHY master/slave setting */
+#define E1000_MASTER_SLAVE     e1000_ms_hw_default
+#endif
+
+/* wrapper around a pointer to a socket buffer,
+ * so a DMA handle can be stored along with the buffer */
+struct e1000_buffer {
+       struct sk_buff *skb;
+       unsigned long time_stamp;
+       uint16_t length;
+       uint16_t next_to_watch;
+};
+
+struct e1000_tx_ring {
+       /* pointer to the descriptor ring memory */
+       void *desc;
+       /* length of descriptor ring in bytes */
+       unsigned int size;
+       /* number of descriptors in the ring */
+       unsigned int count;
+       /* next descriptor to associate a buffer with */
+       unsigned int next_to_use;
+       /* next descriptor to check for DD status bit */
+       unsigned int next_to_clean;
+       /* array of buffer information structs */
+       struct e1000_buffer *buffer_info;
+
+       uint16_t tdh;
+       uint16_t tdt;
+       boolean_t last_tx_tso;
+};
+
+struct e1000_rx_ring {
+       /* pointer to the descriptor ring memory */
+       void *desc;
+       /* length of descriptor ring in bytes */
+       unsigned int size;
+       /* number of descriptors in the ring */
+       unsigned int count;
+       /* next descriptor to associate a buffer with */
+       unsigned int next_to_use;
+       /* next descriptor to check for DD status bit */
+       unsigned int next_to_clean;
+       /* array of buffer information structs */
+       struct e1000_buffer *buffer_info;
+       /* arrays of page information for packet split */
+       struct e1000_ps_page *ps_page;
+       struct e1000_ps_page_dma *ps_page_dma;
+
+       /* cpu for rx queue */
+       int cpu;
+
+       uint16_t rdh;
+       uint16_t rdt;
+};
+
+#define E1000_DESC_UNUSED(R) \
+       ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
+       (R)->next_to_clean - (R)->next_to_use - 1)
+
+#define E1000_RX_DESC_PS(R, i)     \
+       (&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
+#define E1000_RX_DESC_EXT(R, i)            \
+       (&(((union e1000_rx_desc_extended *)((R).desc))[i]))
+#define E1000_GET_DESC(R, i, type)     (&(((struct type *)((R).desc))[i]))
+#define E1000_RX_DESC(R, i)            E1000_GET_DESC(R, i, e1000_rx_desc)
+#define E1000_TX_DESC(R, i)            E1000_GET_DESC(R, i, e1000_tx_desc)
+#define E1000_CONTEXT_DESC(R, i)       E1000_GET_DESC(R, i, e1000_context_desc)
+
+/* board specific private data structure */
+
+struct e1000_adapter {
+       struct vlan_group *vlgrp;
+       uint16_t mng_vlan_id;
+       uint32_t bd_number;
+       uint32_t rx_buffer_len;
+       uint32_t wol;
+       uint32_t smartspeed;
+       uint32_t en_mng_pt;
+       uint16_t link_speed;
+       uint16_t link_duplex;
+
+       unsigned int total_tx_bytes;
+       unsigned int total_tx_packets;
+       unsigned int total_rx_bytes;
+       unsigned int total_rx_packets;
+       /* Interrupt Throttle Rate */
+       uint32_t itr;
+       uint32_t itr_setting;
+       uint16_t tx_itr;
+       uint16_t rx_itr;
+
+       uint8_t fc_autoneg;
+
+       unsigned long led_status;
+
+       /* TX */
+       struct e1000_tx_ring *tx_ring;      /* One per active queue */
+       unsigned int restart_queue;
+       unsigned long tx_queue_len;
+       uint32_t txd_cmd;
+       uint32_t tx_int_delay;
+       uint32_t tx_abs_int_delay;
+       uint32_t gotcl;
+       uint64_t gotcl_old;
+       uint64_t tpt_old;
+       uint64_t colc_old;
+       uint32_t tx_timeout_count;
+       uint32_t tx_fifo_head;
+       uint32_t tx_head_addr;
+       uint32_t tx_fifo_size;
+       uint8_t  tx_timeout_factor;
+       boolean_t pcix_82544;
+       boolean_t detect_tx_hung;
+
+       /* RX */
+       boolean_t (*clean_rx) (struct e1000_adapter *adapter,
+                              struct e1000_rx_ring *rx_ring);
+       void (*alloc_rx_buf) (struct e1000_adapter *adapter,
+                             struct e1000_rx_ring *rx_ring,
+                               int cleaned_count);
+       struct e1000_rx_ring *rx_ring;      /* One per active queue */
+       int num_tx_queues;
+       int num_rx_queues;
+
+       uint64_t hw_csum_err;
+       uint64_t hw_csum_good;
+       uint64_t rx_hdr_split;
+       uint32_t alloc_rx_buff_failed;
+       uint32_t rx_int_delay;
+       uint32_t rx_abs_int_delay;
+       boolean_t rx_csum;
+       unsigned int rx_ps_pages;
+       uint32_t gorcl;
+       uint64_t gorcl_old;
+       uint16_t rx_ps_bsize0;
+
+
+       /* OS defined structs */
+       struct net_device *netdev;
+       struct pci_device *pdev;
+       struct net_device_stats net_stats;
+
+       /* structs defined in e1000_hw.h */
+       struct e1000_hw hw;
+       struct e1000_hw_stats stats;
+       struct e1000_phy_info phy_info;
+       struct e1000_phy_stats phy_stats;
+
+       uint32_t test_icr;
+       struct e1000_tx_ring test_tx_ring;
+       struct e1000_rx_ring test_rx_ring;
+
+       int msg_enable;
+       boolean_t have_msi;
+
+       /* to not mess up cache alignment, always add to the bottom */
+       boolean_t tso_force;
+       boolean_t smart_power_down;     /* phy smart power down */
+       boolean_t quad_port_a;
+       unsigned long flags;
+       uint32_t eeprom_wol;
+       
+#define NUM_TX_DESC    8
+#define NUM_RX_DESC    8
+
+       char *tx_desc_ring;
+       char *rx_desc_ring;
+
+       struct io_buffer *tx_iobuf[NUM_TX_DESC];
+       struct io_buffer *rx_iobuf[NUM_RX_DESC];
+
+       struct e1000_tx_desc *tx_desc[NUM_TX_DESC];
+       struct e1000_rx_desc *rx_desc[NUM_RX_DESC];
+       
+       struct e1000_tx_desc *tx_base;
+       struct e1000_rx_desc *rx_base;
+
+       uint32_t tx_head;
+       uint32_t tx_tail;
+       uint32_t tx_fill_ctr;
+       uint32_t rx_tail;
+
+       uint32_t ioaddr;
+       uint32_t irqno;
+
+};
+
+enum e1000_state_t {
+       __E1000_TESTING,
+       __E1000_RESETTING,
+       __E1000_DOWN
+};
+
+#define E1000_MNG2HOST_PORT_623 (1 << 5)
+#define E1000_MNG2HOST_PORT_664 (1 << 6)
+
+#define E1000_ERT_2048 0x100
+
+#define IORESOURCE_IO          0x00000100
+#define IORESOURCE_MEM          0x00000200
+#define IORESOURCE_PREFETCH     0x00001000
+
+#endif /* _E1000_H_ */
+
+/*
+ * Local variables:
+ *  c-basic-offset: 8
+ *  c-indent-level: 8
+ *  tab-width: 8
+ * End:
+ */
diff --git a/src/drivers/net/e1000/e1000_hw.c b/src/drivers/net/e1000/e1000_hw.c
new file mode 100644 (file)
index 0000000..0667ad6
--- /dev/null
@@ -0,0 +1,9050 @@
+/*******************************************************************************
+
+  Intel PRO/1000 Linux driver
+  Copyright(c) 1999 - 2006 Intel Corporation.
+
+  This program is free software; you can redistribute it and/or modify it
+  under the terms and conditions of the GNU General Public License,
+  version 2, as published by the Free Software Foundation.
+
+  This program is distributed in the hope it will be useful, but WITHOUT
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+  more details.
+
+  You should have received a copy of the GNU General Public License along with
+  this program; if not, write to the Free Software Foundation, Inc.,
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+
+  The full GNU General Public License is included in this distribution in
+  the file called "COPYING".
+
+  Contact Information:
+  Linux NICS <linux.nics@intel.com>
+  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+
+*******************************************************************************/
+
+/* e1000_hw.c
+ * Shared functions for accessing and configuring the MAC
+ */
+
+
+#include "e1000_hw.h"
+
+static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
+static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
+static int32_t e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data);
+static int32_t e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data);
+static int32_t e1000_get_software_semaphore(struct e1000_hw *hw);
+static void e1000_release_software_semaphore(struct e1000_hw *hw);
+
+static uint8_t e1000_arc_subsystem_valid(struct e1000_hw *hw);
+static int32_t e1000_check_downshift(struct e1000_hw *hw);
+static int32_t e1000_check_polarity(struct e1000_hw *hw, e1000_rev_polarity *polarity);
+static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
+static void e1000_clear_vfta(struct e1000_hw *hw);
+static int32_t e1000_commit_shadow_ram(struct e1000_hw *hw);
+static int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw, boolean_t link_up);
+static int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw);
+static int32_t e1000_detect_gig_phy(struct e1000_hw *hw);
+static int32_t e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank);
+static int32_t e1000_get_auto_rd_done(struct e1000_hw *hw);
+static int32_t e1000_get_cable_length(struct e1000_hw *hw, uint16_t *min_length, uint16_t *max_length);
+static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
+static int32_t e1000_get_phy_cfg_done(struct e1000_hw *hw);
+static int32_t e1000_get_software_flag(struct e1000_hw *hw);
+static int32_t e1000_ich8_cycle_init(struct e1000_hw *hw);
+static int32_t e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout);
+static int32_t e1000_id_led_init(struct e1000_hw *hw);
+static int32_t e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, uint32_t cnf_base_addr, uint32_t cnf_size);
+static int32_t e1000_init_lcd_from_nvm(struct e1000_hw *hw);
+static void e1000_init_rx_addrs(struct e1000_hw *hw);
+static void e1000_initialize_hardware_bits(struct e1000_hw *hw);
+static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw);
+static int32_t e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw);
+static int32_t e1000_mng_enable_host_if(struct e1000_hw *hw);
+static int32_t e1000_mng_host_if_write(struct e1000_hw *hw, uint8_t *buffer, uint16_t length, uint16_t offset, uint8_t *sum);
+static int32_t e1000_mng_write_cmd_header(struct e1000_hw* hw, struct e1000_host_mng_command_header* hdr);
+static int32_t e1000_mng_write_commit(struct e1000_hw *hw);
+static int32_t e1000_phy_ife_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
+static int32_t e1000_phy_igp_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
+static int32_t e1000_read_eeprom_eerd(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
+static int32_t e1000_write_eeprom_eewr(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
+static int32_t e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd);
+static int32_t e1000_phy_m88_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
+static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
+static int32_t e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t *data);
+static int32_t e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte);
+static int32_t e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte);
+static int32_t e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data);
+static int32_t e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t *data);
+static int32_t e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t data);
+static int32_t e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
+static int32_t e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
+static void e1000_release_software_flag(struct e1000_hw *hw);
+static int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active);
+static int32_t e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active);
+static int32_t e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop);
+static void e1000_set_pci_express_master_disable(struct e1000_hw *hw);
+static int32_t e1000_wait_autoneg(struct e1000_hw *hw);
+static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value);
+static int32_t e1000_set_phy_type(struct e1000_hw *hw);
+static void e1000_phy_init_script(struct e1000_hw *hw);
+static int32_t e1000_setup_copper_link(struct e1000_hw *hw);
+static int32_t e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
+static int32_t e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
+static int32_t e1000_phy_force_speed_duplex(struct e1000_hw *hw);
+static int32_t e1000_config_mac_to_phy(struct e1000_hw *hw);
+static void e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
+static void e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
+static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data,
+                                     uint16_t count);
+static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw);
+static int32_t e1000_phy_reset_dsp(struct e1000_hw *hw);
+static int32_t e1000_write_eeprom_spi(struct e1000_hw *hw, uint16_t offset,
+                                      uint16_t words, uint16_t *data);
+static int32_t e1000_write_eeprom_microwire(struct e1000_hw *hw,
+                                            uint16_t offset, uint16_t words,
+                                            uint16_t *data);
+static int32_t e1000_spi_eeprom_ready(struct e1000_hw *hw);
+static void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
+static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
+static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data,
+                                    uint16_t count);
+static int32_t e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
+                                      uint16_t phy_data);
+static int32_t e1000_read_phy_reg_ex(struct e1000_hw *hw,uint32_t reg_addr,
+                                     uint16_t *phy_data);
+static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count);
+static int32_t e1000_acquire_eeprom(struct e1000_hw *hw);
+static void e1000_release_eeprom(struct e1000_hw *hw);
+static void e1000_standby_eeprom(struct e1000_hw *hw);
+static int32_t e1000_set_vco_speed(struct e1000_hw *hw);
+static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw);
+static int32_t e1000_set_phy_mode(struct e1000_hw *hw);
+static int32_t e1000_host_if_read_cookie(struct e1000_hw *hw, uint8_t *buffer);
+static uint8_t e1000_calculate_mng_checksum(char *buffer, uint32_t length);
+static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw,
+                                               uint16_t duplex);
+static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw);
+
+/* IGP cable length table */
+static const
+uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
+    { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
+      5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
+      25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
+      40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
+      60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
+      90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
+      100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
+      110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
+
+static const
+uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =
+    { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
+      0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
+      6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
+      21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
+      40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
+      60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
+      83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
+      104, 109, 114, 118, 121, 124};
+
+/******************************************************************************
+ * Set the phy type member in the hw struct.
+ *
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+static int32_t
+e1000_set_phy_type(struct e1000_hw *hw)
+{
+    DEBUGFUNC("e1000_set_phy_type");
+
+    if (hw->mac_type == e1000_undefined)
+        return -E1000_ERR_PHY_TYPE;
+
+    switch (hw->phy_id) {
+    case M88E1000_E_PHY_ID:
+    case M88E1000_I_PHY_ID:
+    case M88E1011_I_PHY_ID:
+    case M88E1111_I_PHY_ID:
+        hw->phy_type = e1000_phy_m88;
+        break;
+    case IGP01E1000_I_PHY_ID:
+        if (hw->mac_type == e1000_82541 ||
+            hw->mac_type == e1000_82541_rev_2 ||
+            hw->mac_type == e1000_82547 ||
+            hw->mac_type == e1000_82547_rev_2) {
+            hw->phy_type = e1000_phy_igp;
+            break;
+        }
+    case IGP03E1000_E_PHY_ID:
+        hw->phy_type = e1000_phy_igp_3;
+        break;
+    case IFE_E_PHY_ID:
+    case IFE_PLUS_E_PHY_ID:
+    case IFE_C_E_PHY_ID:
+        hw->phy_type = e1000_phy_ife;
+        break;
+    case GG82563_E_PHY_ID:
+        if (hw->mac_type == e1000_80003es2lan) {
+            hw->phy_type = e1000_phy_gg82563;
+            break;
+        }
+        /* Fall Through */
+    default:
+        /* Should never have loaded on this device */
+        hw->phy_type = e1000_phy_undefined;
+        return -E1000_ERR_PHY_TYPE;
+    }
+
+    return E1000_SUCCESS;
+}
+
+/******************************************************************************
+ * IGP phy init script - initializes the GbE PHY
+ *
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+static void
+e1000_phy_init_script(struct e1000_hw *hw)
+{
+    uint32_t ret_val;
+    uint16_t phy_saved_data;
+
+    DEBUGFUNC("e1000_phy_init_script");
+
+    if (hw->phy_init_script) {
+        msleep(20);
+
+        /* Save off the current value of register 0x2F5B to be restored at
+         * the end of this routine. */
+        ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
+
+        /* Disabled the PHY transmitter */
+        e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
+
+        msleep(20);
+
+        e1000_write_phy_reg(hw,0x0000,0x0140);
+
+        msleep(5);
+
+        switch (hw->mac_type) {
+        case e1000_82541:
+        case e1000_82547:
+            e1000_write_phy_reg(hw, 0x1F95, 0x0001);
+
+            e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
+
+            e1000_write_phy_reg(hw, 0x1F79, 0x0018);
+
+            e1000_write_phy_reg(hw, 0x1F30, 0x1600);
+
+            e1000_write_phy_reg(hw, 0x1F31, 0x0014);
+
+            e1000_write_phy_reg(hw, 0x1F32, 0x161C);
+
+            e1000_write_phy_reg(hw, 0x1F94, 0x0003);
+
+            e1000_write_phy_reg(hw, 0x1F96, 0x003F);
+
+            e1000_write_phy_reg(hw, 0x2010, 0x0008);
+            break;
+
+        case e1000_82541_rev_2:
+        case e1000_82547_rev_2:
+            e1000_write_phy_reg(hw, 0x1F73, 0x0099);
+            break;
+        default:
+            break;
+        }
+
+        e1000_write_phy_reg(hw, 0x0000, 0x3300);
+
+        msleep(20);
+
+        /* Now enable the transmitter */
+        e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
+
+        if (hw->mac_type == e1000_82547) {
+            uint16_t fused, fine, coarse;
+
+            /* Move to analog registers page */
+            e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
+
+            if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
+                e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
+
+                fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
+                coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
+
+                if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
+                    coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
+                    fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
+                } else if (coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
+                    fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
+
+                fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
+                        (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
+                        (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
+
+                e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
+                e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
+                                    IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
+            }
+        }
+    }
+}
+
+/******************************************************************************
+ * Set the mac type member in the hw struct.
+ *
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+int32_t
+e1000_set_mac_type(struct e1000_hw *hw)
+{
+       DEBUGFUNC("e1000_set_mac_type");
+
+       switch (hw->device_id) {
+       case E1000_DEV_ID_82542:
+               switch (hw->revision_id) {
+               case E1000_82542_2_0_REV_ID:
+                       hw->mac_type = e1000_82542_rev2_0;
+                       break;
+               case E1000_82542_2_1_REV_ID:
+                       hw->mac_type = e1000_82542_rev2_1;
+                       break;
+               default:
+                       /* Invalid 82542 revision ID */
+                       return -E1000_ERR_MAC_TYPE;
+               }
+               break;
+       case E1000_DEV_ID_82543GC_FIBER:
+       case E1000_DEV_ID_82543GC_COPPER:
+               hw->mac_type = e1000_82543;
+               break;
+       case E1000_DEV_ID_82544EI_COPPER:
+       case E1000_DEV_ID_82544EI_FIBER:
+       case E1000_DEV_ID_82544GC_COPPER:
+       case E1000_DEV_ID_82544GC_LOM:
+               hw->mac_type = e1000_82544;
+               break;
+       case E1000_DEV_ID_82540EM:
+       case E1000_DEV_ID_82540EM_LOM:
+       case E1000_DEV_ID_82540EP:
+       case E1000_DEV_ID_82540EP_LOM:
+       case E1000_DEV_ID_82540EP_LP:
+               hw->mac_type = e1000_82540;
+               break;
+       case E1000_DEV_ID_82545EM_COPPER:
+       case E1000_DEV_ID_82545EM_FIBER:
+               hw->mac_type = e1000_82545;
+               break;
+       case E1000_DEV_ID_82545GM_COPPER:
+       case E1000_DEV_ID_82545GM_FIBER:
+       case E1000_DEV_ID_82545GM_SERDES:
+               hw->mac_type = e1000_82545_rev_3;
+               break;
+       case E1000_DEV_ID_82546EB_COPPER:
+       case E1000_DEV_ID_82546EB_FIBER:
+       case E1000_DEV_ID_82546EB_QUAD_COPPER:
+               hw->mac_type = e1000_82546;
+               break;
+       case E1000_DEV_ID_82546GB_COPPER:
+       case E1000_DEV_ID_82546GB_FIBER:
+       case E1000_DEV_ID_82546GB_SERDES:
+       case E1000_DEV_ID_82546GB_PCIE:
+       case E1000_DEV_ID_82546GB_QUAD_COPPER:
+       case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
+               hw->mac_type = e1000_82546_rev_3;
+               break;
+       case E1000_DEV_ID_82541EI:
+       case E1000_DEV_ID_82541EI_MOBILE:
+       case E1000_DEV_ID_82541ER_LOM:
+               hw->mac_type = e1000_82541;
+               break;
+       case E1000_DEV_ID_82541ER:
+       case E1000_DEV_ID_82541GI:
+       case E1000_DEV_ID_82541GI_LF:
+       case E1000_DEV_ID_82541GI_MOBILE:
+               hw->mac_type = e1000_82541_rev_2;
+               break;
+       case E1000_DEV_ID_82547EI:
+       case E1000_DEV_ID_82547EI_MOBILE:
+               hw->mac_type = e1000_82547;
+               break;
+       case E1000_DEV_ID_82547GI:
+               hw->mac_type = e1000_82547_rev_2;
+               break;
+       case E1000_DEV_ID_82571EB_COPPER:
+       case E1000_DEV_ID_82571EB_FIBER:
+       case E1000_DEV_ID_82571EB_SERDES:
+       case E1000_DEV_ID_82571EB_SERDES_DUAL:
+       case E1000_DEV_ID_82571EB_SERDES_QUAD:
+       case E1000_DEV_ID_82571EB_QUAD_COPPER:
+       case E1000_DEV_ID_82571EB_QUAD_FIBER:
+       case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
+               hw->mac_type = e1000_82571;
+               break;
+       case E1000_DEV_ID_82572EI_COPPER:
+       case E1000_DEV_ID_82572EI_FIBER:
+       case E1000_DEV_ID_82572EI_SERDES:
+       case E1000_DEV_ID_82572EI:
+               hw->mac_type = e1000_82572;
+               break;
+       case E1000_DEV_ID_82573E:
+       case E1000_DEV_ID_82573E_IAMT:
+       case E1000_DEV_ID_82573L:
+               hw->mac_type = e1000_82573;
+               break;
+       case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
+       case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
+       case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
+       case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
+               hw->mac_type = e1000_80003es2lan;
+               break;
+       case E1000_DEV_ID_ICH8_IGP_M_AMT:
+       case E1000_DEV_ID_ICH8_IGP_AMT:
+       case E1000_DEV_ID_ICH8_IGP_C:
+       case E1000_DEV_ID_ICH8_IFE:
+       case E1000_DEV_ID_ICH8_IFE_GT:
+       case E1000_DEV_ID_ICH8_IFE_G:
+       case E1000_DEV_ID_ICH8_IGP_M:
+               hw->mac_type = e1000_ich8lan;
+               break;
+       default:
+               /* Should never have loaded on this device */
+               return -E1000_ERR_MAC_TYPE;
+       }
+
+       switch (hw->mac_type) {
+       case e1000_ich8lan:
+               hw->swfwhw_semaphore_present = TRUE;
+               hw->asf_firmware_present = TRUE;
+               break;
+       case e1000_80003es2lan:
+               hw->swfw_sync_present = TRUE;
+               /* fall through */
+       case e1000_82571:
+       case e1000_82572:
+       case e1000_82573:
+               hw->eeprom_semaphore_present = TRUE;
+               /* fall through */
+       case e1000_82541:
+       case e1000_82547:
+       case e1000_82541_rev_2:
+       case e1000_82547_rev_2:
+               hw->asf_firmware_present = TRUE;
+               break;
+       default:
+               break;
+       }
+
+       /* The 82543 chip does not count tx_carrier_errors properly in
+        * FD mode
+        */
+       if (hw->mac_type == e1000_82543)
+               hw->bad_tx_carr_stats_fd = TRUE;
+
+       /* capable of receiving management packets to the host */
+       if (hw->mac_type >= e1000_82571)
+               hw->has_manc2h = TRUE;
+
+       /* In rare occasions, ESB2 systems would end up started without
+        * the RX unit being turned on.
+        */
+       if (hw->mac_type == e1000_80003es2lan)
+               hw->rx_needs_kicking = TRUE;
+
+       if (hw->mac_type > e1000_82544)
+               hw->has_smbus = TRUE;
+
+       return E1000_SUCCESS;
+}
+
+/*****************************************************************************
+ * Set media type and TBI compatibility.
+ *
+ * hw - Struct containing variables accessed by shared code
+ * **************************************************************************/
+void
+e1000_set_media_type(struct e1000_hw *hw)
+{
+    uint32_t status;
+
+    DEBUGFUNC("e1000_set_media_type");
+
+    if (hw->mac_type != e1000_82543) {
+        /* tbi_compatibility is only valid on 82543 */
+        hw->tbi_compatibility_en = FALSE;
+    }
+
+    switch (hw->device_id) {
+    case E1000_DEV_ID_82545GM_SERDES:
+    case E1000_DEV_ID_82546GB_SERDES:
+    case E1000_DEV_ID_82571EB_SERDES:
+    case E1000_DEV_ID_82571EB_SERDES_DUAL:
+    case E1000_DEV_ID_82571EB_SERDES_QUAD:
+    case E1000_DEV_ID_82572EI_SERDES:
+    case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
+        hw->media_type = e1000_media_type_internal_serdes;
+        break;
+    default:
+        switch (hw->mac_type) {
+        case e1000_82542_rev2_0:
+        case e1000_82542_rev2_1:
+            hw->media_type = e1000_media_type_fiber;
+            break;
+        case e1000_ich8lan:
+        case e1000_82573:
+            /* The STATUS_TBIMODE bit is reserved or reused for the this
+             * device.
+             */
+            hw->media_type = e1000_media_type_copper;
+            break;
+        default:
+            status = E1000_READ_REG(hw, STATUS);
+            if (status & E1000_STATUS_TBIMODE) {
+                hw->media_type = e1000_media_type_fiber;
+                /* tbi_compatibility not valid on fiber */
+                hw->tbi_compatibility_en = FALSE;
+            } else {
+                hw->media_type = e1000_media_type_copper;
+            }
+            break;
+        }
+    }
+}
+
+/******************************************************************************
+ * Reset the transmit and receive units; mask and clear all interrupts.
+ *
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+int32_t
+e1000_reset_hw(struct e1000_hw *hw)
+{
+    uint32_t ctrl;
+    uint32_t ctrl_ext;
+    uint32_t icr;
+    uint32_t manc;
+    uint32_t led_ctrl;
+    uint32_t timeout;
+    uint32_t extcnf_ctrl;
+    int32_t ret_val;
+
+    DEBUGFUNC("e1000_reset_hw");
+
+    /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
+    if (hw->mac_type == e1000_82542_rev2_0) {
+        DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
+        e1000_pci_clear_mwi(hw);
+    }
+
+    if (hw->bus_type == e1000_bus_type_pci_express) {
+        /* Prevent the PCI-E bus from sticking if there is no TLP connection
+         * on the last TLP read/write transaction when MAC is reset.
+         */
+        if (e1000_disable_pciex_master(hw) != E1000_SUCCESS) {
+            DEBUGOUT("PCI-E Master disable polling has failed.\n");
+        }
+    }
+
+    /* Clear interrupt mask to stop board from generating interrupts */
+    DEBUGOUT("Masking off all interrupts\n");
+    E1000_WRITE_REG(hw, IMC, 0xffffffff);
+
+    /* Disable the Transmit and Receive units.  Then delay to allow
+     * any pending transactions to complete before we hit the MAC with
+     * the global reset.
+     */
+    E1000_WRITE_REG(hw, RCTL, 0);
+    E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
+    E1000_WRITE_FLUSH(hw);
+
+    /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
+    hw->tbi_compatibility_on = FALSE;
+
+    /* Delay to allow any outstanding PCI transactions to complete before
+     * resetting the device
+     */
+    msleep(10);
+
+    ctrl = E1000_READ_REG(hw, CTRL);
+
+    /* Must reset the PHY before resetting the MAC */
+    if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
+        E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
+        msleep(5);
+    }
+
+    /* Must acquire the MDIO ownership before MAC reset.
+     * Ownership defaults to firmware after a reset. */
+    if (hw->mac_type == e1000_82573) {
+        timeout = 10;
+
+        extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
+        extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
+
+        do {
+            E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
+            extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
+
+            if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
+                break;
+            else
+                extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
+
+            msleep(2);
+            timeout--;
+        } while (timeout);
+    }
+
+    /* Workaround for ICH8 bit corruption issue in FIFO memory */
+    if (hw->mac_type == e1000_ich8lan) {
+        /* Set Tx and Rx buffer allocation to 8k apiece. */
+        E1000_WRITE_REG(hw, PBA, E1000_PBA_8K);
+        /* Set Packet Buffer Size to 16k. */
+        E1000_WRITE_REG(hw, PBS, E1000_PBS_16K);
+    }
+
+    /* Issue a global reset to the MAC.  This will reset the chip's
+     * transmit, receive, DMA, and link units.  It will not effect
+     * the current PCI configuration.  The global reset bit is self-
+     * clearing, and should clear within a microsecond.
+     */
+    DEBUGOUT("Issuing a global reset to MAC\n");
+
+    switch (hw->mac_type) {
+        case e1000_82544:
+        case e1000_82540:
+        case e1000_82545:
+        case e1000_82546:
+        case e1000_82541:
+        case e1000_82541_rev_2:
+            /* These controllers can't ack the 64-bit write when issuing the
+             * reset, so use IO-mapping as a workaround to issue the reset */
+            E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
+            break;
+        case e1000_82545_rev_3:
+        case e1000_82546_rev_3:
+            /* Reset is performed on a shadow of the control register */
+            E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
+            break;
+        case e1000_ich8lan:
+            if (!hw->phy_reset_disable &&
+                e1000_check_phy_reset_block(hw) == E1000_SUCCESS) {
+                /* e1000_ich8lan PHY HW reset requires MAC CORE reset
+                 * at the same time to make sure the interface between
+                 * MAC and the external PHY is reset.
+                 */
+                ctrl |= E1000_CTRL_PHY_RST;
+            }
+
+            e1000_get_software_flag(hw);
+            E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
+            msleep(5);
+            break;
+        default:
+            E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
+            break;
+    }
+
+    /* After MAC reset, force reload of EEPROM to restore power-on settings to
+     * device.  Later controllers reload the EEPROM automatically, so just wait
+     * for reload to complete.
+     */
+    switch (hw->mac_type) {
+        case e1000_82542_rev2_0:
+        case e1000_82542_rev2_1:
+        case e1000_82543:
+        case e1000_82544:
+            /* Wait for reset to complete */
+            udelay(10);
+            ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
+            ctrl_ext |= E1000_CTRL_EXT_EE_RST;
+            E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
+            E1000_WRITE_FLUSH(hw);
+            /* Wait for EEPROM reload */
+            msleep(2);
+            break;
+        case e1000_82541:
+        case e1000_82541_rev_2:
+        case e1000_82547:
+        case e1000_82547_rev_2:
+            /* Wait for EEPROM reload */
+            msleep(20);
+            break;
+        case e1000_82573:
+            if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
+                udelay(10);
+                ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
+                ctrl_ext |= E1000_CTRL_EXT_EE_RST;
+                E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
+                E1000_WRITE_FLUSH(hw);
+            }
+            /* fall through */
+        default:
+            /* Auto read done will delay 5ms or poll based on mac type */
+            ret_val = e1000_get_auto_rd_done(hw);
+            if (ret_val)
+                return ret_val;
+            break;
+    }
+
+    /* Disable HW ARPs on ASF enabled adapters */
+    if (hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) {
+        manc = E1000_READ_REG(hw, MANC);
+        manc &= ~(E1000_MANC_ARP_EN);
+        E1000_WRITE_REG(hw, MANC, manc);
+    }
+
+    if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
+        e1000_phy_init_script(hw);
+
+        /* Configure activity LED after PHY reset */
+        led_ctrl = E1000_READ_REG(hw, LEDCTL);
+        led_ctrl &= IGP_ACTIVITY_LED_MASK;
+        led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
+        E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
+    }
+
+    /* Clear interrupt mask to stop board from generating interrupts */
+    DEBUGOUT("Masking off all interrupts\n");
+    E1000_WRITE_REG(hw, IMC, 0xffffffff);
+
+    /* Clear any pending interrupt events. */
+    icr = E1000_READ_REG(hw, ICR);
+
+    /* If MWI was previously enabled, reenable it. */
+    if (hw->mac_type == e1000_82542_rev2_0) {
+        if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
+            e1000_pci_set_mwi(hw);
+    }
+
+    if (hw->mac_type == e1000_ich8lan) {
+        uint32_t kab = E1000_READ_REG(hw, KABGTXD);
+        kab |= E1000_KABGTXD_BGSQLBIAS;
+        E1000_WRITE_REG(hw, KABGTXD, kab);
+    }
+
+    return E1000_SUCCESS;
+}
+
+/******************************************************************************
+ *
+ * Initialize a number of hardware-dependent bits
+ *
+ * hw: Struct containing variables accessed by shared code
+ *
+ * This function contains hardware limitation workarounds for PCI-E adapters
+ *
+ *****************************************************************************/
+static void
+e1000_initialize_hardware_bits(struct e1000_hw *hw)
+{
+    if ((hw->mac_type >= e1000_82571) && (!hw->initialize_hw_bits_disable)) {
+        /* Settings common to all PCI-express silicon */
+        uint32_t reg_ctrl, reg_ctrl_ext;
+        uint32_t reg_tarc0, reg_tarc1;
+        uint32_t reg_tctl;
+        uint32_t reg_txdctl, reg_txdctl1;
+
+        /* link autonegotiation/sync workarounds */
+        reg_tarc0 = E1000_READ_REG(hw, TARC0);
+        reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
+
+        /* Enable not-done TX descriptor counting */
+        reg_txdctl = E1000_READ_REG(hw, TXDCTL);
+        reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
+        E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
+        reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
+        reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
+        E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
+
+        switch (hw->mac_type) {
+            case e1000_82571:
+            case e1000_82572:
+                /* Clear PHY TX compatible mode bits */
+                reg_tarc1 = E1000_READ_REG(hw, TARC1);
+                reg_tarc1 &= ~((1 << 30)|(1 << 29));
+
+                /* link autonegotiation/sync workarounds */
+                reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
+
+                /* TX ring control fixes */
+                reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
+
+                /* Multiple read bit is reversed polarity */
+                reg_tctl = E1000_READ_REG(hw, TCTL);
+                if (reg_tctl & E1000_TCTL_MULR)
+                    reg_tarc1 &= ~(1 << 28);
+                else
+                    reg_tarc1 |= (1 << 28);
+
+                E1000_WRITE_REG(hw, TARC1, reg_tarc1);
+                break;
+            case e1000_82573:
+                reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
+                reg_ctrl_ext &= ~(1 << 23);
+                reg_ctrl_ext |= (1 << 22);
+
+                /* TX byte count fix */
+                reg_ctrl = E1000_READ_REG(hw, CTRL);
+                reg_ctrl &= ~(1 << 29);
+
+                E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
+                E1000_WRITE_REG(hw, CTRL, reg_ctrl);
+                break;
+            case e1000_80003es2lan:
+                /* improve small packet performace for fiber/serdes */
+                if ((hw->media_type == e1000_media_type_fiber) ||
+                    (hw->media_type == e1000_media_type_internal_serdes)) {
+                    reg_tarc0 &= ~(1 << 20);
+                }
+
+                /* Multiple read bit is reversed polarity */
+                reg_tctl = E1000_READ_REG(hw, TCTL);
+                reg_tarc1 = E1000_READ_REG(hw, TARC1);
+                if (reg_tctl & E1000_TCTL_MULR)
+                    reg_tarc1 &= ~(1 << 28);
+                else
+                    reg_tarc1 |= (1 << 28);
+
+                E1000_WRITE_REG(hw, TARC1, reg_tarc1);
+                break;
+            case e1000_ich8lan:
+                /* Reduce concurrent DMA requests to 3 from 4 */
+                if ((hw->revision_id < 3) ||
+                    ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
+                     (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
+                    reg_tarc0 |= ((1 << 29)|(1 << 28));
+
+                reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
+                reg_ctrl_ext |= (1 << 22);
+                E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
+
+                /* workaround TX hang with TSO=on */
+                reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
+
+                /* Multiple read bit is reversed polarity */
+                reg_tctl = E1000_READ_REG(hw, TCTL);
+                reg_tarc1 = E1000_READ_REG(hw, TARC1);
+                if (reg_tctl & E1000_TCTL_MULR)
+                    reg_tarc1 &= ~(1 << 28);
+                else
+                    reg_tarc1 |= (1 << 28);
+
+                /* workaround TX hang with TSO=on */
+                reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
+
+                E1000_WRITE_REG(hw, TARC1, reg_tarc1);
+                break;
+            default:
+                break;
+        }
+
+        E1000_WRITE_REG(hw, TARC0, reg_tarc0);
+    }
+}
+
+/******************************************************************************
+ * Performs basic configuration of the adapter.
+ *
+ * hw - Struct containing variables accessed by shared code
+ *
+ * Assumes that the controller has previously been reset and is in a
+ * post-reset uninitialized state. Initializes the receive address registers,
+ * multicast table, and VLAN filter table. Calls routines to setup link
+ * configuration and flow control settings. Clears all on-chip counters. Leaves
+ * the transmit and receive units disabled and uninitialized.
+ *****************************************************************************/
+int32_t
+e1000_init_hw(struct e1000_hw *hw)
+{
+    uint32_t ctrl;
+    uint32_t i;
+    int32_t ret_val;
+    uint16_t pcix_cmd_word;
+    uint16_t pcix_stat_hi_word;
+    uint16_t cmd_mmrbc;
+    uint16_t stat_mmrbc;
+    uint32_t mta_size;
+    uint32_t reg_data;
+    uint32_t ctrl_ext;
+
+    DEBUGFUNC("e1000_init_hw");
+
+    /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
+    if ((hw->mac_type == e1000_ich8lan) &&
+        ((hw->revision_id < 3) ||
+         ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
+          (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
+            reg_data = E1000_READ_REG(hw, STATUS);
+            reg_data &= ~0x80000000;
+            E1000_WRITE_REG(hw, STATUS, reg_data);
+    }
+
+    /* Initialize Identification LED */
+    ret_val = e1000_id_led_init(hw);
+    if (ret_val) {
+        DEBUGOUT("Error Initializing Identification LED\n");
+        return ret_val;
+    }
+
+    /* Set the media type and TBI compatibility */
+    e1000_set_media_type(hw);
+
+    /* Must be called after e1000_set_media_type because media_type is used */
+    e1000_initialize_hardware_bits(hw);
+
+    /* Disabling VLAN filtering. */
+    DEBUGOUT("Initializing the IEEE VLAN\n");
+    /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
+    if (hw->mac_type != e1000_ich8lan) {
+        if (hw->mac_type < e1000_82545_rev_3)
+            E1000_WRITE_REG(hw, VET, 0);
+        e1000_clear_vfta(hw);
+    }
+
+    /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
+    if (hw->mac_type == e1000_82542_rev2_0) {
+        DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
+        e1000_pci_clear_mwi(hw);
+        E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
+        E1000_WRITE_FLUSH(hw);
+        msleep(5);
+    }
+
+    /* Setup the receive address. This involves initializing all of the Receive
+     * Address Registers (RARs 0 - 15).
+     */
+    e1000_init_rx_addrs(hw);
+
+    /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
+    if (hw->mac_type == e1000_82542_rev2_0) {
+        E1000_WRITE_REG(hw, RCTL, 0);
+        E1000_WRITE_FLUSH(hw);
+        msleep(1);
+        if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
+            e1000_pci_set_mwi(hw);
+    }
+
+    /* Zero out the Multicast HASH table */
+    DEBUGOUT("Zeroing the MTA\n");
+    mta_size = E1000_MC_TBL_SIZE;
+    if (hw->mac_type == e1000_ich8lan)
+        mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
+    for (i = 0; i < mta_size; i++) {
+        E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
+        /* use write flush to prevent Memory Write Block (MWB) from
+         * occuring when accessing our register space */
+        E1000_WRITE_FLUSH(hw);
+    }
+
+    /* Set the PCI priority bit correctly in the CTRL register.  This
+     * determines if the adapter gives priority to receives, or if it
+     * gives equal priority to transmits and receives.  Valid only on
+     * 82542 and 82543 silicon.
+     */
+    if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
+        ctrl = E1000_READ_REG(hw, CTRL);
+        E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
+    }
+
+    switch (hw->mac_type) {
+    case e1000_82545_rev_3:
+    case e1000_82546_rev_3:
+        break;
+    default:
+        /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
+        if (hw->bus_type == e1000_bus_type_pcix) {
+            e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
+            e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI,
+                &pcix_stat_hi_word);
+            cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
+                PCIX_COMMAND_MMRBC_SHIFT;
+            stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
+                PCIX_STATUS_HI_MMRBC_SHIFT;
+            if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
+                stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
+            if (cmd_mmrbc > stat_mmrbc) {
+                pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
+                pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
+                e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER,
+                    &pcix_cmd_word);
+            }
+        }
+        break;
+    }
+
+    /* More time needed for PHY to initialize */
+    if (hw->mac_type == e1000_ich8lan)
+        msleep(15);
+
+    /* Call a subroutine to configure the link and setup flow control. */
+    ret_val = e1000_setup_link(hw);
+
+    /* Set the transmit descriptor write-back policy */
+    if (hw->mac_type > e1000_82544) {
+        ctrl = E1000_READ_REG(hw, TXDCTL);
+        ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
+        E1000_WRITE_REG(hw, TXDCTL, ctrl);
+    }
+
+    if (hw->mac_type == e1000_82573) {
+        e1000_enable_tx_pkt_filtering(hw);
+    }
+
+    switch (hw->mac_type) {
+    default:
+        break;
+    case e1000_80003es2lan:
+        /* Enable retransmit on late collisions */
+        reg_data = E1000_READ_REG(hw, TCTL);
+        reg_data |= E1000_TCTL_RTLC;
+        E1000_WRITE_REG(hw, TCTL, reg_data);
+
+        /* Configure Gigabit Carry Extend Padding */
+        reg_data = E1000_READ_REG(hw, TCTL_EXT);
+        reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
+        reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
+        E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
+
+        /* Configure Transmit Inter-Packet Gap */
+        reg_data = E1000_READ_REG(hw, TIPG);
+        reg_data &= ~E1000_TIPG_IPGT_MASK;
+        reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
+        E1000_WRITE_REG(hw, TIPG, reg_data);
+
+        reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
+        reg_data &= ~0x00100000;
+        E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
+        /* Fall through */
+    case e1000_82571:
+    case e1000_82572:
+    case e1000_ich8lan:
+        ctrl = E1000_READ_REG(hw, TXDCTL1);
+        ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
+        E1000_WRITE_REG(hw, TXDCTL1, ctrl);
+        break;
+    }
+
+
+    if (hw->mac_type == e1000_82573) {
+        uint32_t gcr = E1000_READ_REG(hw, GCR);
+        gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
+        E1000_WRITE_REG(hw, GCR, gcr);
+    }
+
+    /* Clear all of the statistics registers (clear on read).  It is
+     * important that we do this after we have tried to establish link
+     * because the symbol error count will increment wildly if there
+     * is no link.
+     */
+    e1000_clear_hw_cntrs(hw);
+
+    /* ICH8 No-snoop bits are opposite polarity.
+     * Set to snoop by default after reset. */
+    if (hw->mac_type == e1000_ich8lan)
+        e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
+
+    if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
+        hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
+        ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
+        /* Relaxed ordering must be disabled to avoid a parity
+         * error crash in a PCI slot. */
+        ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
+        E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
+    }
+
+    return ret_val;
+}
+
+/******************************************************************************
+ * Adjust SERDES output amplitude based on EEPROM setting.
+ *
+ * hw - Struct containing variables accessed by shared code.
+ *****************************************************************************/
+static int32_t
+e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
+{
+    uint16_t eeprom_data;
+    int32_t  ret_val;
+
+    DEBUGFUNC("e1000_adjust_serdes_amplitude");
+
+    if (hw->media_type != e1000_media_type_internal_serdes)
+        return E1000_SUCCESS;
+
+    switch (hw->mac_type) {
+    case e1000_82545_rev_3:
+    case e1000_82546_rev_3:
+        break;
+    default:
+        return E1000_SUCCESS;
+    }
+
+    ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data);
+    if (ret_val) {
+        return ret_val;
+    }
+
+    if (eeprom_data != EEPROM_RESERVED_WORD) {
+        /* Adjust SERDES output amplitude only. */
+        eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
+        ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
+        if (ret_val)
+            return ret_val;
+    }
+
+    return E1000_SUCCESS;
+}
+
+/******************************************************************************
+ * Configures flow control and link settings.
+ *
+ * hw - Struct containing variables accessed by shared code
+ *
+ * Determines which flow control settings to use. Calls the apropriate media-
+ * specific link configuration function. Configures the flow control settings.
+ * Assuming the adapter has a valid link partner, a valid link should be
+ * established. Assumes the hardware has previously been reset and the
+ * transmitter and receiver are not enabled.
+ *****************************************************************************/
+int32_t
+e1000_setup_link(struct e1000_hw *hw)
+{
+    uint32_t ctrl_ext;
+    int32_t ret_val;
+    uint16_t eeprom_data;
+
+    DEBUGFUNC("e1000_setup_link");
+
+    /* In the case of the phy reset being blocked, we already have a link.
+     * We do not have to set it up again. */
+    if (e1000_check_phy_reset_block(hw))
+        return E1000_SUCCESS;
+
+    /* Read and store word 0x0F of the EEPROM. This word contains bits
+     * that determine the hardware's default PAUSE (flow control) mode,
+     * a bit that determines whether the HW defaults to enabling or
+     * disabling auto-negotiation, and the direction of the
+     * SW defined pins. If there is no SW over-ride of the flow
+     * control setting, then the variable hw->fc will
+     * be initialized based on a value in the EEPROM.
+     */
+    if (hw->fc == E1000_FC_DEFAULT) {
+        switch (hw->mac_type) {
+        case e1000_ich8lan:
+        case e1000_82573:
+            hw->fc = E1000_FC_FULL;
+            break;
+        default:
+            ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
+                                        1, &eeprom_data);
+            if (ret_val) {
+                DEBUGOUT("EEPROM Read Error\n");
+                return -E1000_ERR_EEPROM;
+            }
+            if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
+                hw->fc = E1000_FC_NONE;
+            else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
+                    EEPROM_WORD0F_ASM_DIR)
+                hw->fc = E1000_FC_TX_PAUSE;
+            else
+                hw->fc = E1000_FC_FULL;
+            break;
+        }
+    }
+
+    /* We want to save off the original Flow Control configuration just
+     * in case we get disconnected and then reconnected into a different
+     * hub or switch with different Flow Control capabilities.
+     */
+    if (hw->mac_type == e1000_82542_rev2_0)
+        hw->fc &= (~E1000_FC_TX_PAUSE);
+
+    if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
+        hw->fc &= (~E1000_FC_RX_PAUSE);
+
+    hw->original_fc = hw->fc;
+
+    DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
+
+    /* Take the 4 bits from EEPROM word 0x0F that determine the initial
+     * polarity value for the SW controlled pins, and setup the
+     * Extended Device Control reg with that info.
+     * This is needed because one of the SW controlled pins is used for
+     * signal detection.  So this should be done before e1000_setup_pcs_link()
+     * or e1000_phy_setup() is called.
+     */
+    if (hw->mac_type == e1000_82543) {
+        ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
+                                    1, &eeprom_data);
+        if (ret_val) {
+            DEBUGOUT("EEPROM Read Error\n");
+            return -E1000_ERR_EEPROM;
+        }
+        ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
+                    SWDPIO__EXT_SHIFT);
+        E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
+    }
+
+    /* Call the necessary subroutine to configure the link. */
+    ret_val = (hw->media_type == e1000_media_type_copper) ?
+              e1000_setup_copper_link(hw) :
+              e1000_setup_fiber_serdes_link(hw);
+
+    /* Initialize the flow control address, type, and PAUSE timer
+     * registers to their default values.  This is done even if flow
+     * control is disabled, because it does not hurt anything to
+     * initialize these registers.
+     */
+    DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
+
+    /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
+    if (hw->mac_type != e1000_ich8lan) {
+        E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
+        E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
+        E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
+    }
+
+    E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
+
+    /* Set the flow control receive threshold registers.  Normally,
+     * these registers will be set to a default threshold that may be
+     * adjusted later by the driver's runtime code.  However, if the
+     * ability to transmit pause frames in not enabled, then these
+     * registers will be set to 0.
+     */
+    if (!(hw->fc & E1000_FC_TX_PAUSE)) {
+        E1000_WRITE_REG(hw, FCRTL, 0);
+        E1000_WRITE_REG(hw, FCRTH, 0);
+    } else {
+        /* We need to set up the Receive Threshold high and low water marks
+         * as well as (optionally) enabling the transmission of XON frames.
+         */
+        if (hw->fc_send_xon) {
+            E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
+            E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
+        } else {
+            E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
+            E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
+        }
+    }
+    return ret_val;
+}
+
+/******************************************************************************
+ * Sets up link for a fiber based or serdes based adapter
+ *
+ * hw - Struct containing variables accessed by shared code
+ *
+ * Manipulates Physical Coding Sublayer functions in order to configure
+ * link. Assumes the hardware has been previously reset and the transmitter
+ * and receiver are not enabled.
+ *****************************************************************************/
+static int32_t
+e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
+{
+    uint32_t ctrl;
+    uint32_t status;
+    uint32_t txcw = 0;
+    uint32_t i;
+    uint32_t signal = 0;
+    int32_t ret_val;
+
+    DEBUGFUNC("e1000_setup_fiber_serdes_link");
+
+    /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists
+     * until explicitly turned off or a power cycle is performed.  A read to
+     * the register does not indicate its status.  Therefore, we ensure
+     * loopback mode is disabled during initialization.
+     */
+    if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572)
+        E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK);
+
+    /* On adapters with a MAC newer than 82544, SWDP 1 will be
+     * set when the optics detect a signal. On older adapters, it will be
+     * cleared when there is a signal.  This applies to fiber media only.
+     * If we're on serdes media, adjust the output amplitude to value
+     * set in the EEPROM.
+     */
+    ctrl = E1000_READ_REG(hw, CTRL);
+    if (hw->media_type == e1000_media_type_fiber)
+        signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
+
+    ret_val = e1000_adjust_serdes_amplitude(hw);
+    if (ret_val)
+        return ret_val;
+
+    /* Take the link out of reset */
+    ctrl &= ~(E1000_CTRL_LRST);
+
+    /* Adjust VCO speed to improve BER performance */
+    ret_val = e1000_set_vco_speed(hw);
+    if (ret_val)
+        return ret_val;
+
+    e1000_config_collision_dist(hw);
+
+    /* Check for a software override of the flow control settings, and setup
+     * the device accordingly.  If auto-negotiation is enabled, then software
+     * will have to set the "PAUSE" bits to the correct value in the Tranmsit
+     * Config Word Register (TXCW) and re-start auto-negotiation.  However, if
+     * auto-negotiation is disabled, then software will have to manually
+     * configure the two flow control enable bits in the CTRL register.
+     *
+     * The possible values of the "fc" parameter are:
+     *      0:  Flow control is completely disabled
+     *      1:  Rx flow control is enabled (we can receive pause frames, but
+     *          not send pause frames).
+     *      2:  Tx flow control is enabled (we can send pause frames but we do
+     *          not support receiving pause frames).
+     *      3:  Both Rx and TX flow control (symmetric) are enabled.
+     */
+    switch (hw->fc) {
+    case E1000_FC_NONE:
+        /* Flow control is completely disabled by a software over-ride. */
+        txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
+        break;
+    case E1000_FC_RX_PAUSE:
+        /* RX Flow control is enabled and TX Flow control is disabled by a
+         * software over-ride. Since there really isn't a way to advertise
+         * that we are capable of RX Pause ONLY, we will advertise that we
+         * support both symmetric and asymmetric RX PAUSE. Later, we will
+         *  disable the adapter's ability to send PAUSE frames.
+         */
+        txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
+        break;
+    case E1000_FC_TX_PAUSE:
+        /* TX Flow control is enabled, and RX Flow control is disabled, by a
+         * software over-ride.
+         */
+        txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
+        break;
+    case E1000_FC_FULL:
+        /* Flow control (both RX and TX) is enabled by a software over-ride. */
+        txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
+        break;
+    default:
+        DEBUGOUT("Flow control param set incorrectly\n");
+        return -E1000_ERR_CONFIG;
+        break;
+    }
+
+    /* Since auto-negotiation is enabled, take the link out of reset (the link
+     * will be in reset, because we previously reset the chip). This will
+     * restart auto-negotiation.  If auto-neogtiation is successful then the
+     * link-up status bit will be set and the flow control enable bits (RFCE
+     * and TFCE) will be set according to their negotiated value.
+     */
+    DEBUGOUT("Auto-negotiation enabled\n");
+
+    E1000_WRITE_REG(hw, TXCW, txcw);
+    E1000_WRITE_REG(hw, CTRL, ctrl);
+    E1000_WRITE_FLUSH(hw);
+
+    hw->txcw = txcw;
+    msleep(1);
+
+    /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
+     * indication in the Device Status Register.  Time-out if a link isn't
+     * seen in 500 milliseconds seconds (Auto-negotiation should complete in
+     * less than 500 milliseconds even if the other end is doing it in SW).
+     * For internal serdes, we just assume a signal is present, then poll.
+     */
+    if (hw->media_type == e1000_media_type_internal_serdes ||
+       (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
+        DEBUGOUT("Looking for Link\n");
+        for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
+            msleep(10);
+            status = E1000_READ_REG(hw, STATUS);
+            if (status & E1000_STATUS_LU) break;
+        }
+        if (i == (LINK_UP_TIMEOUT / 10)) {
+            DEBUGOUT("Never got a valid link from auto-neg!!!\n");
+            hw->autoneg_failed = 1;
+            /* AutoNeg failed to achieve a link, so we'll call
+             * e1000_check_for_link. This routine will force the link up if
+             * we detect a signal. This will allow us to communicate with
+             * non-autonegotiating link partners.
+             */
+            ret_val = e1000_check_for_link(hw);
+            if (ret_val) {
+                DEBUGOUT("Error while checking for link\n");
+                return ret_val;
+            }
+            hw->autoneg_failed = 0;
+        } else {
+            hw->autoneg_failed = 0;
+            DEBUGOUT("Valid Link Found\n");
+        }
+    } else {
+        DEBUGOUT("No Signal Detected\n");
+    }
+    return E1000_SUCCESS;
+}
+
+/******************************************************************************
+* Make sure we have a valid PHY and change PHY mode before link setup.
+*
+* hw - Struct containing variables accessed by shared code
+******************************************************************************/
+static int32_t
+e1000_copper_link_preconfig(struct e1000_hw *hw)
+{
+    uint32_t ctrl;
+    int32_t ret_val;
+    uint16_t phy_data;
+
+    DEBUGFUNC("e1000_copper_link_preconfig");
+
+    ctrl = E1000_READ_REG(hw, CTRL);
+    /* With 82543, we need to force speed and duplex on the MAC equal to what
+     * the PHY speed and duplex configuration is. In addition, we need to
+     * perform a hardware reset on the PHY to take it out of reset.
+     */
+    if (hw->mac_type > e1000_82543) {
+        ctrl |= E1000_CTRL_SLU;
+        ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
+        E1000_WRITE_REG(hw, CTRL, ctrl);
+    } else {
+        ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
+        E1000_WRITE_REG(hw, CTRL, ctrl);
+        ret_val = e1000_phy_hw_reset(hw);
+        if (ret_val)
+            return ret_val;
+    }
+
+    /* Make sure we have a valid PHY */
+    ret_val = e1000_detect_gig_phy(hw);
+    if (ret_val) {
+        DEBUGOUT("Error, did not detect valid phy.\n");
+        return ret_val;
+    }
+    DEBUGOUT1("Phy ID = %#08lx \n", hw->phy_id);
+
+    /* Set PHY to class A mode (if necessary) */
+    ret_val = e1000_set_phy_mode(hw);
+    if (ret_val)
+        return ret_val;
+
+    if ((hw->mac_type == e1000_82545_rev_3) ||
+       (hw->mac_type == e1000_82546_rev_3)) {
+        ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
+        phy_data |= 0x00000008;
+        ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
+    }
+
+    if (hw->mac_type <= e1000_82543 ||
+        hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
+        hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
+        hw->phy_reset_disable = FALSE;
+
+   return E1000_SUCCESS;
+}
+
+
+/********************************************************************
+* Copper link setup for e1000_phy_igp series.
+*
+* hw - Struct containing variables accessed by shared code
+*********************************************************************/
+static int32_t
+e1000_copper_link_igp_setup(struct e1000_hw *hw)
+{
+    uint32_t led_ctrl;
+    int32_t ret_val;
+    uint16_t phy_data;
+
+    DEBUGFUNC("e1000_copper_link_igp_setup");
+
+    if (hw->phy_reset_disable)
+        return E1000_SUCCESS;
+
+    ret_val = e1000_phy_reset(hw);
+    if (ret_val) {
+        DEBUGOUT("Error Resetting the PHY\n");
+        return ret_val;
+    }
+
+    /* Wait 15ms for MAC to configure PHY from eeprom settings */
+    msleep(15);
+    if (hw->mac_type != e1000_ich8lan) {
+    /* Configure activity LED after PHY reset */
+    led_ctrl = E1000_READ_REG(hw, LEDCTL);
+    led_ctrl &= IGP_ACTIVITY_LED_MASK;
+    led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
+    E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
+    }
+
+    /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
+    if (hw->phy_type == e1000_phy_igp) {
+        /* disable lplu d3 during driver init */
+        ret_val = e1000_set_d3_lplu_state(hw, FALSE);
+        if (ret_val) {
+            DEBUGOUT("Error Disabling LPLU D3\n");
+            return ret_val;
+        }
+    }
+
+    /* disable lplu d0 during driver init */
+    ret_val = e1000_set_d0_lplu_state(hw, FALSE);
+    if (ret_val) {
+        DEBUGOUT("Error Disabling LPLU D0\n");
+        return ret_val;
+    }
+    /* Configure mdi-mdix settings */
+    ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
+    if (ret_val)
+        return ret_val;
+
+    if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
+        hw->dsp_config_state = e1000_dsp_config_disabled;
+        /* Force MDI for earlier revs of the IGP PHY */
+        phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX);
+        hw->mdix = 1;
+
+    } else {
+        hw->dsp_config_state = e1000_dsp_config_enabled;
+        phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
+
+        switch (hw->mdix) {
+        case 1:
+            phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
+            break;
+        case 2:
+            phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
+            break;
+        case 0:
+        default:
+            phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
+            break;
+        }
+    }
+    ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
+    if (ret_val)
+        return ret_val;
+
+    /* set auto-master slave resolution settings */
+    if (hw->autoneg) {
+        e1000_ms_type phy_ms_setting = hw->master_slave;
+
+        if (hw->ffe_config_state == e1000_ffe_config_active)
+            hw->ffe_config_state = e1000_ffe_config_enabled;
+
+        if (hw->dsp_config_state == e1000_dsp_config_activated)
+            hw->dsp_config_state = e1000_dsp_config_enabled;
+
+        /* when autonegotiation advertisment is only 1000Mbps then we
+          * should disable SmartSpeed and enable Auto MasterSlave
+          * resolution as hardware default. */
+        if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
+            /* Disable SmartSpeed */
+            ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
+                                         &phy_data);
+            if (ret_val)
+                return ret_val;
+            phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
+            ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
+                                          phy_data);
+            if (ret_val)
+                return ret_val;
+            /* Set auto Master/Slave resolution process */
+            ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
+            if (ret_val)
+                return ret_val;
+            phy_data &= ~CR_1000T_MS_ENABLE;
+            ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
+            if (ret_val)
+                return ret_val;
+        }
+
+        ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
+        if (ret_val)
+            return ret_val;
+
+        /* load defaults for future use */
+        hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
+                                        ((phy_data & CR_1000T_MS_VALUE) ?
+                                         e1000_ms_force_master :
+                                         e1000_ms_force_slave) :
+                                         e1000_ms_auto;
+
+        switch (phy_ms_setting) {
+        case e1000_ms_force_master:
+            phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
+            break;
+        case e1000_ms_force_slave:
+            phy_data |= CR_1000T_MS_ENABLE;
+            phy_data &= ~(CR_1000T_MS_VALUE);
+            break;
+        case e1000_ms_auto:
+            phy_data &= ~CR_1000T_MS_ENABLE;
+            default:
+            break;
+        }
+        ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
+        if (ret_val)
+            return ret_val;
+    }
+
+    return E1000_SUCCESS;
+}
+
+/********************************************************************
+* Copper link setup for e1000_phy_gg82563 series.
+*
+* hw - Struct containing variables accessed by shared code
+*********************************************************************/
+static int32_t
+e1000_copper_link_ggp_setup(struct e1000_hw *hw)
+{
+    int32_t ret_val;
+    uint16_t phy_data;
+    uint32_t reg_data;
+
+    DEBUGFUNC("e1000_copper_link_ggp_setup");
+
+    if (!hw->phy_reset_disable) {
+
+        /* Enable CRS on TX for half-duplex operation. */
+        ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
+                                     &phy_data);
+        if (ret_val)
+            return ret_val;
+
+        phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
+        /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
+        phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
+
+        ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
+                                      phy_data);
+        if (ret_val)
+            return ret_val;
+
+        /* Options:
+         *   MDI/MDI-X = 0 (default)
+         *   0 - Auto for all speeds
+         *   1 - MDI mode
+         *   2 - MDI-X mode
+         *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
+         */
+        ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data);
+        if (ret_val)
+            return ret_val;
+
+        phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
+
+        switch (hw->mdix) {
+        case 1:
+            phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
+            break;
+        case 2:
+            phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
+            break;
+        case 0:
+        default:
+            phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
+            break;
+        }
+
+        /* Options:
+         *   disable_polarity_correction = 0 (default)
+         *       Automatic Correction for Reversed Cable Polarity
+         *   0 - Disabled
+         *   1 - Enabled
+         */
+        phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
+        if (hw->disable_polarity_correction == 1)
+            phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
+        ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
+
+        if (ret_val)
+            return ret_val;
+
+        /* SW Reset the PHY so all changes take effect */
+        ret_val = e1000_phy_reset(hw);
+        if (ret_val) {
+            DEBUGOUT("Error Resetting the PHY\n");
+            return ret_val;
+        }
+    } /* phy_reset_disable */
+
+    if (hw->mac_type == e1000_80003es2lan) {
+        /* Bypass RX and TX FIFO's */
+        ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
+                                       E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS |
+                                       E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
+        if (ret_val)
+            return ret_val;
+
+        ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data);
+        if (ret_val)
+            return ret_val;
+
+        phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
+        ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data);
+
+        if (ret_val)
+            return ret_val;
+
+        reg_data = E1000_READ_REG(hw, CTRL_EXT);
+        reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
+        E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
+
+        ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
+                                          &phy_data);
+        if (ret_val)
+            return ret_val;
+
+        /* Do not init these registers when the HW is in IAMT mode, since the
+         * firmware will have already initialized them.  We only initialize
+         * them if the HW is not in IAMT mode.
+         */
+        if (e1000_check_mng_mode(hw) == FALSE) {
+            /* Enable Electrical Idle on the PHY */
+            phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
+            ret_val = e1000_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
+                                          phy_data);
+            if (ret_val)
+                return ret_val;
+
+            ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
+                                         &phy_data);
+            if (ret_val)
+                return ret_val;
+
+            phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
+            ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
+                                          phy_data);
+
+            if (ret_val)
+                return ret_val;
+        }
+
+        /* Workaround: Disable padding in Kumeran interface in the MAC
+         * and in the PHY to avoid CRC errors.
+         */
+        ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
+                                     &phy_data);
+        if (ret_val)
+            return ret_val;
+        phy_data |= GG82563_ICR_DIS_PADDING;
+        ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
+                                      phy_data);
+        if (ret_val)
+            return ret_val;
+    }
+
+    return E1000_SUCCESS;
+}
+
+/********************************************************************
+* Copper link setup for e1000_phy_m88 series.
+*
+* hw - Struct containing variables accessed by shared code
+*********************************************************************/
+static int32_t
+e1000_copper_link_mgp_setup(struct e1000_hw *hw)
+{
+    int32_t ret_val;
+    uint16_t phy_data;
+
+    DEBUGFUNC("e1000_copper_link_mgp_setup");
+
+    if (hw->phy_reset_disable)
+        return E1000_SUCCESS;
+
+    /* Enable CRS on TX. This must be set for half-duplex operation. */
+    ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
+    if (ret_val)
+        return ret_val;
+
+    phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
+
+    /* Options:
+     *   MDI/MDI-X = 0 (default)
+     *   0 - Auto for all speeds
+     *   1 - MDI mode
+     *   2 - MDI-X mode
+     *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
+     */
+    phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
+
+    switch (hw->mdix) {
+    case 1:
+        phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
+        break;
+    case 2:
+        phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
+        break;
+    case 3:
+        phy_data |= M88E1000_PSCR_AUTO_X_1000T;
+        break;
+    case 0:
+    default:
+        phy_data |= M88E1000_PSCR_AUTO_X_MODE;
+        break;
+    }
+
+    /* Options:
+     *   disable_polarity_correction = 0 (default)
+     *       Automatic Correction for Reversed Cable Polarity
+     *   0 - Disabled
+     *   1 - Enabled
+     */
+    phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
+    if (hw->disable_polarity_correction == 1)
+        phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
+    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
+    if (ret_val)
+        return ret_val;
+
+    if (hw->phy_revision < M88E1011_I_REV_4) {
+        /* Force TX_CLK in the Extended PHY Specific Control Register
+         * to 25MHz clock.
+         */
+        ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
+        if (ret_val)
+            return ret_val;
+
+        phy_data |= M88E1000_EPSCR_TX_CLK_25;
+
+        if ((hw->phy_revision == E1000_REVISION_2) &&
+            (hw->phy_id == M88E1111_I_PHY_ID)) {
+            /* Vidalia Phy, set the downshift counter to 5x */
+            phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
+            phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
+            ret_val = e1000_write_phy_reg(hw,
+                                        M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
+            if (ret_val)
+                return ret_val;
+        } else {
+            /* Configure Master and Slave downshift values */
+            phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
+                              M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
+            phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
+                             M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
+            ret_val = e1000_write_phy_reg(hw,
+                                        M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
+            if (ret_val)
+               return ret_val;
+        }
+    }
+
+    /* SW Reset the PHY so all changes take effect */
+    ret_val = e1000_phy_reset(hw);
+    if (ret_val) {
+        DEBUGOUT("Error Resetting the PHY\n");
+        return ret_val;
+    }
+
+   return E1000_SUCCESS;
+}
+
+/********************************************************************
+* Setup auto-negotiation and flow control advertisements,
+* and then perform auto-negotiation.
+*
+* hw - Struct containing variables accessed by shared code
+*********************************************************************/
+static int32_t
+e1000_copper_link_autoneg(struct e1000_hw *hw)
+{
+    int32_t ret_val;
+    uint16_t phy_data;
+
+    DEBUGFUNC("e1000_copper_link_autoneg");
+
+    /* Perform some bounds checking on the hw->autoneg_advertised
+     * parameter.  If this variable is zero, then set it to the default.
+     */
+    hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
+
+    /* If autoneg_advertised is zero, we assume it was not defaulted
+     * by the calling code so we set to advertise full capability.
+     */
+    if (hw->autoneg_advertised == 0)
+        hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
+
+    /* IFE phy only supports 10/100 */
+    if (hw->phy_type == e1000_phy_ife)
+        hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
+
+    DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
+    ret_val = e1000_phy_setup_autoneg(hw);
+    if (ret_val) {
+        DEBUGOUT("Error Setting up Auto-Negotiation\n");
+        return ret_val;
+    }
+    DEBUGOUT("Restarting Auto-Neg\n");
+
+    /* Restart auto-negotiation by setting the Auto Neg Enable bit and
+     * the Auto Neg Restart bit in the PHY control register.
+     */
+    ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
+    if (ret_val)
+        return ret_val;
+
+    phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
+    ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
+    if (ret_val)
+        return ret_val;
+
+    /* Does the user want to wait for Auto-Neg to complete here, or
+     * check at a later time (for example, callback routine).
+     */
+    if (hw->wait_autoneg_complete) {
+        ret_val = e1000_wait_autoneg(hw);
+        if (ret_val) {
+            DEBUGOUT("Error while waiting for autoneg to complete\n");
+            return ret_val;
+        }
+    }
+
+    hw->get_link_status = TRUE;
+
+    return E1000_SUCCESS;
+}
+
+/******************************************************************************
+* Config the MAC and the PHY after link is up.
+*   1) Set up the MAC to the current PHY speed/duplex
+*      if we are on 82543.  If we
+*      are on newer silicon, we only need to configure
+*      collision distance in the Transmit Control Register.
+*   2) Set up flow control on the MAC to that established with
+*      the link partner.
+*   3) Config DSP to improve Gigabit link quality for some PHY revisions.
+*
+* hw - Struct containing variables accessed by shared code
+******************************************************************************/
+static int32_t
+e1000_copper_link_postconfig(struct e1000_hw *hw)
+{
+    int32_t ret_val;
+    DEBUGFUNC("e1000_copper_link_postconfig");
+
+    if (hw->mac_type >= e1000_82544) {
+        e1000_config_collision_dist(hw);
+    } else {
+        ret_val = e1000_config_mac_to_phy(hw);
+        if (ret_val) {
+            DEBUGOUT("Error configuring MAC to PHY settings\n");
+            return ret_val;
+        }
+    }
+    ret_val = e1000_config_fc_after_link_up(hw);
+    if (ret_val) {
+        DEBUGOUT("Error Configuring Flow Control\n");
+        return ret_val;
+    }
+
+    /* Config DSP to improve Giga link quality */
+    if (hw->phy_type == e1000_phy_igp) {
+        ret_val = e1000_config_dsp_after_link_change(hw, TRUE);
+        if (ret_val) {
+            DEBUGOUT("Error Configuring DSP after link up\n");
+            return ret_val;
+        }
+    }
+
+    return E1000_SUCCESS;
+}
+
+/******************************************************************************
+* Detects which PHY is present and setup the speed and duplex
+*
+* hw - Struct containing variables accessed by shared code
+******************************************************************************/
+static int32_t
+e1000_setup_copper_link(struct e1000_hw *hw)
+{
+    int32_t ret_val;
+    uint16_t i;
+    uint16_t phy_data;
+    uint16_t reg_data;
+
+    DEBUGFUNC("e1000_setup_copper_link");
+
+    switch (hw->mac_type) {
+    case e1000_80003es2lan:
+    case e1000_ich8lan:
+        /* Set the mac to wait the maximum time between each
+         * iteration and increase the max iterations when
+         * polling the phy; this fixes erroneous timeouts at 10Mbps. */
+        ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
+        if (ret_val)
+            return ret_val;
+        ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
+        if (ret_val)
+            return ret_val;
+        reg_data |= 0x3F;
+        ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
+        if (ret_val)
+            return ret_val;
+    default:
+        break;
+    }
+
+    /* Check if it is a valid PHY and set PHY mode if necessary. */
+    ret_val = e1000_copper_link_preconfig(hw);
+    if (ret_val)
+        return ret_val;
+
+    switch (hw->mac_type) {
+    case e1000_80003es2lan:
+        /* Kumeran registers are written-only */
+        reg_data = E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
+        reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
+        ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL,
+                                       reg_data);
+        if (ret_val)
+            return ret_val;
+        break;
+    default:
+        break;
+    }
+
+    if (hw->phy_type == e1000_phy_igp ||
+        hw->phy_type == e1000_phy_igp_3 ||
+        hw->phy_type == e1000_phy_igp_2) {
+        ret_val = e1000_copper_link_igp_setup(hw);
+        if (ret_val)
+            return ret_val;
+    } else if (hw->phy_type == e1000_phy_m88) {
+        ret_val = e1000_copper_link_mgp_setup(hw);
+        if (ret_val)
+            return ret_val;
+    } else if (hw->phy_type == e1000_phy_gg82563) {
+        ret_val = e1000_copper_link_ggp_setup(hw);
+        if (ret_val)
+            return ret_val;
+    }
+
+    if (hw->autoneg) {
+        /* Setup autoneg and flow control advertisement
+          * and perform autonegotiation */
+        ret_val = e1000_copper_link_autoneg(hw);
+        if (ret_val)
+            return ret_val;
+    } else {
+        /* PHY will be set to 10H, 10F, 100H,or 100F
+          * depending on value from forced_speed_duplex. */
+        DEBUGOUT("Forcing speed and duplex\n");
+        ret_val = e1000_phy_force_speed_duplex(hw);
+        if (ret_val) {
+            DEBUGOUT("Error Forcing Speed and Duplex\n");
+            return ret_val;
+        }
+    }
+
+    /* Check link status. Wait up to 100 microseconds for link to become
+     * valid.
+     */
+    for (i = 0; i < 10; i++) {
+        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
+        if (ret_val)
+            return ret_val;
+        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
+        if (ret_val)
+            return ret_val;
+
+        if (phy_data & MII_SR_LINK_STATUS) {
+            /* Config the MAC and PHY after link is up */
+            ret_val = e1000_copper_link_postconfig(hw);
+            if (ret_val)
+                return ret_val;
+
+            DEBUGOUT("Valid link established!!!\n");
+            return E1000_SUCCESS;
+        }
+        udelay(10);
+    }
+
+    DEBUGOUT("Unable to establish link!!!\n");
+    return E1000_SUCCESS;
+}
+
+/******************************************************************************
+* Configure the MAC-to-PHY interface for 10/100Mbps
+*
+* hw - Struct containing variables accessed by shared code
+******************************************************************************/
+static int32_t
+e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
+{
+    int32_t ret_val = E1000_SUCCESS;
+    uint32_t tipg;
+    uint16_t reg_data;
+
+    DEBUGFUNC("e1000_configure_kmrn_for_10_100");
+
+    reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
+    ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
+                                   reg_data);
+    if (ret_val)
+        return ret_val;
+
+    /* Configure Transmit Inter-Packet Gap */
+    tipg = E1000_READ_REG(hw, TIPG);
+    tipg &= ~E1000_TIPG_IPGT_MASK;
+    tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
+    E1000_WRITE_REG(hw, TIPG, tipg);
+
+    ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
+
+    if (ret_val)
+        return ret_val;
+
+    if (duplex == HALF_DUPLEX)
+        reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
+    else
+        reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
+
+    ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
+
+    return ret_val;
+}
+
+static int32_t
+e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
+{
+    int32_t ret_val = E1000_SUCCESS;
+    uint16_t reg_data;
+    uint32_t tipg;
+
+    DEBUGFUNC("e1000_configure_kmrn_for_1000");
+
+    reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
+    ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
+                                   reg_data);
+    if (ret_val)
+        return ret_val;
+
+    /* Configure Transmit Inter-Packet Gap */
+    tipg = E1000_READ_REG(hw, TIPG);
+    tipg &= ~E1000_TIPG_IPGT_MASK;
+    tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
+    E1000_WRITE_REG(hw, TIPG, tipg);
+
+    ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
+
+    if (ret_val)
+        return ret_val;
+
+    reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
+    ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
+
+    return ret_val;
+}
+
+/******************************************************************************
+* Configures PHY autoneg and flow control advertisement settings
+*
+* hw - Struct containing variables accessed by shared code
+******************************************************************************/
+int32_t
+e1000_phy_setup_autoneg(struct e1000_hw *hw)
+{
+    int32_t ret_val;
+    uint16_t mii_autoneg_adv_reg;
+    uint16_t mii_1000t_ctrl_reg;
+
+    DEBUGFUNC("e1000_phy_setup_autoneg");
+
+    /* Read the MII Auto-Neg Advertisement Register (Address 4). */
+    ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
+    if (ret_val)
+        return ret_val;
+
+    if (hw->phy_type != e1000_phy_ife) {
+        /* Read the MII 1000Base-T Control Register (Address 9). */
+        ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
+        if (ret_val)
+            return ret_val;
+    } else
+        mii_1000t_ctrl_reg=0;
+
+    /* Need to parse both autoneg_advertised and fc and set up
+     * the appropriate PHY registers.  First we will parse for
+     * autoneg_advertised software override.  Since we can advertise
+     * a plethora of combinations, we need to check each bit
+     * individually.
+     */
+
+    /* First we clear all the 10/100 mb speed bits in the Auto-Neg
+     * Advertisement Register (Address 4) and the 1000 mb speed bits in
+     * the  1000Base-T Control Register (Address 9).
+     */
+    mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
+    mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
+
+    DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
+
+    /* Do we want to advertise 10 Mb Half Duplex? */
+    if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
+        DEBUGOUT("Advertise 10mb Half duplex\n");
+        mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
+    }
+
+    /* Do we want to advertise 10 Mb Full Duplex? */
+    if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
+        DEBUGOUT("Advertise 10mb Full duplex\n");
+        mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
+    }
+
+    /* Do we want to advertise 100 Mb Half Duplex? */
+    if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
+        DEBUGOUT("Advertise 100mb Half duplex\n");
+        mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
+    }
+
+    /* Do we want to advertise 100 Mb Full Duplex? */
+    if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
+        DEBUGOUT("Advertise 100mb Full duplex\n");
+        mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
+    }
+
+    /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
+    if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
+        DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
+    }
+
+    /* Do we want to advertise 1000 Mb Full Duplex? */
+    if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
+        DEBUGOUT("Advertise 1000mb Full duplex\n");
+        mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
+        if (hw->phy_type == e1000_phy_ife) {
+            DEBUGOUT("e1000_phy_ife is a 10/100 PHY. Gigabit speed is not supported.\n");
+        }
+    }
+
+    /* Check for a software override of the flow control settings, and
+     * setup the PHY advertisement registers accordingly.  If
+     * auto-negotiation is enabled, then software will have to set the
+     * "PAUSE" bits to the correct value in the Auto-Negotiation
+     * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
+     *
+     * The possible values of the "fc" parameter are:
+     *      0:  Flow control is completely disabled
+     *      1:  Rx flow control is enabled (we can receive pause frames
+     *          but not send pause frames).
+     *      2:  Tx flow control is enabled (we can send pause frames
+     *          but we do not support receiving pause frames).
+     *      3:  Both Rx and TX flow control (symmetric) are enabled.
+     *  other:  No software override.  The flow control configuration
+     *          in the EEPROM is used.
+     */
+    switch (hw->fc) {
+    case E1000_FC_NONE: /* 0 */
+        /* Flow control (RX & TX) is completely disabled by a
+         * software over-ride.
+         */
+        mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
+        break;
+    case E1000_FC_RX_PAUSE: /* 1 */
+        /* RX Flow control is enabled, and TX Flow control is
+         * disabled, by a software over-ride.
+         */
+        /* Since there really isn't a way to advertise that we are
+         * capable of RX Pause ONLY, we will advertise that we
+         * support both symmetric and asymmetric RX PAUSE.  Later
+         * (in e1000_config_fc_after_link_up) we will disable the
+         *hw's ability to send PAUSE frames.
+         */
+        mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
+        break;
+    case E1000_FC_TX_PAUSE: /* 2 */
+        /* TX Flow control is enabled, and RX Flow control is
+         * disabled, by a software over-ride.
+         */
+        mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
+        mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
+        break;
+    case E1000_FC_FULL: /* 3 */
+        /* Flow control (both RX and TX) is enabled by a software
+         * over-ride.
+         */
+        mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
+        break;
+    default:
+        DEBUGOUT("Flow control param set incorrectly\n");
+        return -E1000_ERR_CONFIG;
+    }
+
+    ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
+    if (ret_val)
+        return ret_val;
+
+    DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
+
+    if (hw->phy_type != e1000_phy_ife) {
+        ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
+        if (ret_val)
+            return ret_val;
+    }
+
+    return E1000_SUCCESS;
+}
+
+/******************************************************************************
+* Force PHY speed and duplex settings to hw->forced_speed_duplex
+*
+* hw - Struct containing variables accessed by shared code
+******************************************************************************/
+static int32_t
+e1000_phy_force_speed_duplex(struct e1000_hw *hw)
+{
+    uint32_t ctrl;
+    int32_t ret_val;
+    uint16_t mii_ctrl_reg;
+    uint16_t mii_status_reg;
+    uint16_t phy_data;
+    uint16_t i;
+
+    DEBUGFUNC("e1000_phy_force_speed_duplex");
+
+    /* Turn off Flow control if we are forcing speed and duplex. */
+    hw->fc = E1000_FC_NONE;
+
+    DEBUGOUT1("hw->fc = %d\n", hw->fc);
+
+    /* Read the Device Control Register. */
+    ctrl = E1000_READ_REG(hw, CTRL);
+
+    /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
+    ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
+    ctrl &= ~(DEVICE_SPEED_MASK);
+
+    /* Clear the Auto Speed Detect Enable bit. */
+    ctrl &= ~E1000_CTRL_ASDE;
+
+    /* Read the MII Control Register. */
+    ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
+    if (ret_val)
+        return ret_val;
+
+    /* We need to disable autoneg in order to force link and duplex. */
+
+    mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
+
+    /* Are we forcing Full or Half Duplex? */
+    if (hw->forced_speed_duplex == e1000_100_full ||
+        hw->forced_speed_duplex == e1000_10_full) {
+        /* We want to force full duplex so we SET the full duplex bits in the
+         * Device and MII Control Registers.
+         */
+        ctrl |= E1000_CTRL_FD;
+        mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
+        DEBUGOUT("Full Duplex\n");
+    } else {
+        /* We want to force half duplex so we CLEAR the full duplex bits in
+         * the Device and MII Control Registers.
+         */
+        ctrl &= ~E1000_CTRL_FD;
+        mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
+        DEBUGOUT("Half Duplex\n");
+    }
+
+    /* Are we forcing 100Mbps??? */
+    if (hw->forced_speed_duplex == e1000_100_full ||
+       hw->forced_speed_duplex == e1000_100_half) {
+        /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
+        ctrl |= E1000_CTRL_SPD_100;
+        mii_ctrl_reg |= MII_CR_SPEED_100;
+        mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
+        DEBUGOUT("Forcing 100mb ");
+    } else {
+        /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
+        ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
+        mii_ctrl_reg |= MII_CR_SPEED_10;
+        mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
+        DEBUGOUT("Forcing 10mb ");
+    }
+
+    e1000_config_collision_dist(hw);
+
+    /* Write the configured values back to the Device Control Reg. */
+    E1000_WRITE_REG(hw, CTRL, ctrl);
+
+    if ((hw->phy_type == e1000_phy_m88) ||
+        (hw->phy_type == e1000_phy_gg82563)) {
+        ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
+        if (ret_val)
+            return ret_val;
+
+        /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
+         * forced whenever speed are duplex are forced.
+         */
+        phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
+        ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
+        if (ret_val)
+            return ret_val;
+
+        DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
+
+        /* Need to reset the PHY or these changes will be ignored */
+        mii_ctrl_reg |= MII_CR_RESET;
+
+    /* Disable MDI-X support for 10/100 */
+    } else if (hw->phy_type == e1000_phy_ife) {
+        ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
+        if (ret_val)
+            return ret_val;
+
+        phy_data &= ~IFE_PMC_AUTO_MDIX;
+        phy_data &= ~IFE_PMC_FORCE_MDIX;
+
+        ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data);
+        if (ret_val)
+            return ret_val;
+
+    } else {
+        /* Clear Auto-Crossover to force MDI manually.  IGP requires MDI
+         * forced whenever speed or duplex are forced.
+         */
+        ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
+        if (ret_val)
+            return ret_val;
+
+        phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
+        phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
+
+        ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
+        if (ret_val)
+            return ret_val;
+    }
+
+    /* Write back the modified PHY MII control register. */
+    ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
+    if (ret_val)
+        return ret_val;
+
+    udelay(1);
+
+    /* The wait_autoneg_complete flag may be a little misleading here.
+     * Since we are forcing speed and duplex, Auto-Neg is not enabled.
+     * But we do want to delay for a period while forcing only so we
+     * don't generate false No Link messages.  So we will wait here
+     * only if the user has set wait_autoneg_complete to 1, which is
+     * the default.
+     */
+    if (hw->wait_autoneg_complete) {
+        /* We will wait for autoneg to complete. */
+        DEBUGOUT("Waiting for forced speed/duplex link.\n");
+        mii_status_reg = 0;
+
+        /* We will wait for autoneg to complete or 4.5 seconds to expire. */
+        for (i = PHY_FORCE_TIME; i > 0; i--) {
+            /* Read the MII Status Register and wait for Auto-Neg Complete bit
+             * to be set.
+             */
+            ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
+            if (ret_val)
+                return ret_val;
+
+            ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
+            if (ret_val)
+                return ret_val;
+
+            if (mii_status_reg & MII_SR_LINK_STATUS) break;
+            msleep(100);
+        }
+        if ((i == 0) &&
+           ((hw->phy_type == e1000_phy_m88) ||
+            (hw->phy_type == e1000_phy_gg82563))) {
+            /* We didn't get link.  Reset the DSP and wait again for link. */
+            ret_val = e1000_phy_reset_dsp(hw);
+            if (ret_val) {
+                DEBUGOUT("Error Resetting PHY DSP\n");
+                return ret_val;
+            }
+        }
+        /* This loop will early-out if the link condition has been met.  */
+        for (i = PHY_FORCE_TIME; i > 0; i--) {
+            if (mii_status_reg & MII_SR_LINK_STATUS) break;
+            msleep(100);
+            /* Read the MII Status Register and wait for Auto-Neg Complete bit
+             * to be set.
+             */
+            ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
+            if (ret_val)
+                return ret_val;
+
+            ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
+            if (ret_val)
+                return ret_val;
+        }
+    }
+
+    if (hw->phy_type == e1000_phy_m88) {
+        /* Because we reset the PHY above, we need to re-force TX_CLK in the
+         * Extended PHY Specific Control Register to 25MHz clock.  This value
+         * defaults back to a 2.5MHz clock when the PHY is reset.
+         */
+        ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
+        if (ret_val)
+            return ret_val;
+
+        phy_data |= M88E1000_EPSCR_TX_CLK_25;
+        ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
+        if (ret_val)
+            return ret_val;
+
+        /* In addition, because of the s/w reset above, we need to enable CRS on
+         * TX.  This must be set for both full and half duplex operation.
+         */
+        ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
+        if (ret_val)
+            return ret_val;
+
+        phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
+        ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
+        if (ret_val)
+            return ret_val;
+
+        if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
+            (!hw->autoneg) && (hw->forced_speed_duplex == e1000_10_full ||
+             hw->forced_speed_duplex == e1000_10_half)) {
+            ret_val = e1000_polarity_reversal_workaround(hw);
+            if (ret_val)
+                return ret_val;
+        }
+    } else if (hw->phy_type == e1000_phy_gg82563) {
+        /* The TX_CLK of the Extended PHY Specific Control Register defaults
+         * to 2.5MHz on a reset.  We need to re-force it back to 25MHz, if
+         * we're not in a forced 10/duplex configuration. */
+        ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
+        if (ret_val)
+            return ret_val;
+
+        phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
+        if ((hw->forced_speed_duplex == e1000_10_full) ||
+            (hw->forced_speed_duplex == e1000_10_half))
+            phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ;
+        else
+            phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ;
+
+        /* Also due to the reset, we need to enable CRS on Tx. */
+        phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
+
+        ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
+        if (ret_val)
+            return ret_val;
+    }
+    return E1000_SUCCESS;
+}
+
+/******************************************************************************
+* Sets the collision distance in the Transmit Control register
+*
+* hw - Struct containing variables accessed by shared code
+*
+* Link should have been established previously. Reads the speed and duplex
+* information from the Device Status register.
+******************************************************************************/
+void
+e1000_config_collision_dist(struct e1000_hw *hw)
+{
+    uint32_t tctl, coll_dist;
+
+    DEBUGFUNC("e1000_config_collision_dist");
+
+    if (hw->mac_type < e1000_82543)
+        coll_dist = E1000_COLLISION_DISTANCE_82542;
+    else
+        coll_dist = E1000_COLLISION_DISTANCE;
+
+    tctl = E1000_READ_REG(hw, TCTL);
+
+    tctl &= ~E1000_TCTL_COLD;
+    tctl |= coll_dist << E1000_COLD_SHIFT;
+
+    E1000_WRITE_REG(hw, TCTL, tctl);
+    E1000_WRITE_FLUSH(hw);
+}
+
+/******************************************************************************
+* Sets MAC speed and duplex settings to reflect the those in the PHY
+*
+* hw - Struct containing variables accessed by shared code
+* mii_reg - data to write to the MII control register
+*
+* The contents of the PHY register containing the needed information need to
+* be passed in.
+******************************************************************************/
+static int32_t
+e1000_config_mac_to_phy(struct e1000_hw *hw)
+{
+    uint32_t ctrl;
+    int32_t ret_val;
+    uint16_t phy_data;
+
+    DEBUGFUNC("e1000_config_mac_to_phy");
+
+    /* 82544 or newer MAC, Auto Speed Detection takes care of
+    * MAC speed/duplex configuration.*/
+    if (hw->mac_type >= e1000_82544)
+        return E1000_SUCCESS;
+
+    /* Read the Device Control Register and set the bits to Force Speed
+     * and Duplex.
+     */
+    ctrl = E1000_READ_REG(hw, CTRL);
+    ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
+    ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
+
+    /* Set up duplex in the Device Control and Transmit Control
+     * registers depending on negotiated values.
+     */
+    ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
+    if (ret_val)
+        return ret_val;
+
+    if (phy_data & M88E1000_PSSR_DPLX)
+        ctrl |= E1000_CTRL_FD;
+    else
+        ctrl &= ~E1000_CTRL_FD;
+
+    e1000_config_collision_dist(hw);
+
+    /* Set up speed in the Device Control register depending on
+     * negotiated values.
+     */
+    if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
+        ctrl |= E1000_CTRL_SPD_1000;
+    else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
+        ctrl |= E1000_CTRL_SPD_100;
+
+    /* Write the configured values back to the Device Control Reg. */
+    E1000_WRITE_REG(hw, CTRL, ctrl);
+    return E1000_SUCCESS;
+}
+
+/******************************************************************************
+ * Forces the MAC's flow control settings.
+ *
+ * hw - Struct containing variables accessed by shared code
+ *
+ * Sets the TFCE and RFCE bits in the device control register to reflect
+ * the adapter settings. TFCE and RFCE need to be explicitly set by
+ * software when a Copper PHY is used because autonegotiation is managed
+ * by the PHY rather than the MAC. Software must also configure these
+ * bits when link is forced on a fiber connection.
+ *****************************************************************************/
+int32_t
+e1000_force_mac_fc(struct e1000_hw *hw)
+{
+    uint32_t ctrl;
+
+    DEBUGFUNC("e1000_force_mac_fc");
+
+    /* Get the current configuration of the Device Control Register */
+    ctrl = E1000_READ_REG(hw, CTRL);
+
+    /* Because we didn't get link via the internal auto-negotiation
+     * mechanism (we either forced link or we got link via PHY
+     * auto-neg), we have to manually enable/disable transmit an
+     * receive flow control.
+     *
+     * The "Case" statement below enables/disable flow control
+     * according to the "hw->fc" parameter.
+     *
+     * The possible values of the "fc" parameter are:
+     *      0:  Flow control is completely disabled
+     *      1:  Rx flow control is enabled (we can receive pause
+     *          frames but not send pause frames).
+     *      2:  Tx flow control is enabled (we can send pause frames
+     *          frames but we do not receive pause frames).
+     *      3:  Both Rx and TX flow control (symmetric) is enabled.
+     *  other:  No other values should be possible at this point.
+     */
+
+    switch (hw->fc) {
+    case E1000_FC_NONE:
+        ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
+        break;
+    case E1000_FC_RX_PAUSE:
+        ctrl &= (~E1000_CTRL_TFCE);
+        ctrl |= E1000_CTRL_RFCE;
+        break;
+    case E1000_FC_TX_PAUSE:
+        ctrl &= (~E1000_CTRL_RFCE);
+        ctrl |= E1000_CTRL_TFCE;
+        break;
+    case E1000_FC_FULL:
+        ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
+        break;
+    default:
+        DEBUGOUT("Flow control param set incorrectly\n");
+        return -E1000_ERR_CONFIG;
+    }
+
+    /* Disable TX Flow Control for 82542 (rev 2.0) */
+    if (hw->mac_type == e1000_82542_rev2_0)
+        ctrl &= (~E1000_CTRL_TFCE);
+
+    E1000_WRITE_REG(hw, CTRL, ctrl);
+    return E1000_SUCCESS;
+}
+
+/******************************************************************************
+ * Configures flow control settings after link is established
+ *
+ * hw - Struct containing variables accessed by shared code
+ *
+ * Should be called immediately after a valid link has been established.
+ * Forces MAC flow control settings if link was forced. When in MII/GMII mode
+ * and autonegotiation is enabled, the MAC flow control settings will be set
+ * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
+ * and RFCE bits will be automaticaly set to the negotiated flow control mode.
+ *****************************************************************************/
+static int32_t
+e1000_config_fc_after_link_up(struct e1000_hw *hw)
+{
+    int32_t ret_val;
+    uint16_t mii_status_reg;
+    uint16_t mii_nway_adv_reg;
+    uint16_t mii_nway_lp_ability_reg;
+    uint16_t speed;
+    uint16_t duplex;
+
+    DEBUGFUNC("e1000_config_fc_after_link_up");
+
+    /* Check for the case where we have fiber media and auto-neg failed
+     * so we had to force link.  In this case, we need to force the
+     * configuration of the MAC to match the "fc" parameter.
+     */
+    if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
+        ((hw->media_type == e1000_media_type_internal_serdes) &&
+         (hw->autoneg_failed)) ||
+        ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) {
+        ret_val = e1000_force_mac_fc(hw);
+        if (ret_val) {
+            DEBUGOUT("Error forcing flow control settings\n");
+            return ret_val;
+        }
+    }
+
+    /* Check for the case where we have copper media and auto-neg is
+     * enabled.  In this case, we need to check and see if Auto-Neg
+     * has completed, and if so, how the PHY and link partner has
+     * flow control configured.
+     */
+    if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
+        /* Read the MII Status Register and check to see if AutoNeg
+         * has completed.  We read this twice because this reg has
+         * some "sticky" (latched) bits.
+         */
+        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
+        if (ret_val)
+            return ret_val;
+        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
+        if (ret_val)
+            return ret_val;
+
+        if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
+            /* The AutoNeg process has completed, so we now need to
+             * read both the Auto Negotiation Advertisement Register
+             * (Address 4) and the Auto_Negotiation Base Page Ability
+             * Register (Address 5) to determine how flow control was
+             * negotiated.
+             */
+            ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
+                                         &mii_nway_adv_reg);
+            if (ret_val)
+                return ret_val;
+            ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
+                                         &mii_nway_lp_ability_reg);
+            if (ret_val)
+                return ret_val;
+
+            /* Two bits in the Auto Negotiation Advertisement Register
+             * (Address 4) and two bits in the Auto Negotiation Base
+             * Page Ability Register (Address 5) determine flow control
+             * for both the PHY and the link partner.  The following
+             * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
+             * 1999, describes these PAUSE resolution bits and how flow
+             * control is determined based upon these settings.
+             * NOTE:  DC = Don't Care
+             *
+             *   LOCAL DEVICE  |   LINK PARTNER
+             * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
+             *-------|---------|-------|---------|--------------------
+             *   0   |    0    |  DC   |   DC    | E1000_FC_NONE
+             *   0   |    1    |   0   |   DC    | E1000_FC_NONE
+             *   0   |    1    |   1   |    0    | E1000_FC_NONE
+             *   0   |    1    |   1   |    1    | E1000_FC_TX_PAUSE
+             *   1   |    0    |   0   |   DC    | E1000_FC_NONE
+             *   1   |   DC    |   1   |   DC    | E1000_FC_FULL
+             *   1   |    1    |   0   |    0    | E1000_FC_NONE
+             *   1   |    1    |   0   |    1    | E1000_FC_RX_PAUSE
+             *
+             */
+            /* Are both PAUSE bits set to 1?  If so, this implies
+             * Symmetric Flow Control is enabled at both ends.  The
+             * ASM_DIR bits are irrelevant per the spec.
+             *
+             * For Symmetric Flow Control:
+             *
+             *   LOCAL DEVICE  |   LINK PARTNER
+             * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
+             *-------|---------|-------|---------|--------------------
+             *   1   |   DC    |   1   |   DC    | E1000_FC_FULL
+             *
+             */
+            if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
+                (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
+                /* Now we need to check if the user selected RX ONLY
+                 * of pause frames.  In this case, we had to advertise
+                 * FULL flow control because we could not advertise RX
+                 * ONLY. Hence, we must now check to see if we need to
+                 * turn OFF  the TRANSMISSION of PAUSE frames.
+                 */
+                if (hw->original_fc == E1000_FC_FULL) {
+                    hw->fc = E1000_FC_FULL;
+                    DEBUGOUT("Flow Control = FULL.\n");
+                } else {
+                    hw->fc = E1000_FC_RX_PAUSE;
+                    DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
+                }
+            }
+            /* For receiving PAUSE frames ONLY.
+             *
+             *   LOCAL DEVICE  |   LINK PARTNER
+             * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
+             *-------|---------|-------|---------|--------------------
+             *   0   |    1    |   1   |    1    | E1000_FC_TX_PAUSE
+             *
+             */
+            else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
+                     (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
+                     (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
+                     (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
+                hw->fc = E1000_FC_TX_PAUSE;
+                DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
+            }
+            /* For transmitting PAUSE frames ONLY.
+             *
+             *   LOCAL DEVICE  |   LINK PARTNER
+             * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
+             *-------|---------|-------|---------|--------------------
+             *   1   |    1    |   0   |    1    | E1000_FC_RX_PAUSE
+             *
+             */
+            else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
+                     (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
+                     !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
+                     (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
+                hw->fc = E1000_FC_RX_PAUSE;
+                DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
+            }
+            /* Per the IEEE spec, at this point flow control should be
+             * disabled.  However, we want to consider that we could
+             * be connected to a legacy switch that doesn't advertise
+             * desired flow control, but can be forced on the link
+             * partner.  So if we advertised no flow control, that is
+             * what we will resolve to.  If we advertised some kind of
+             * receive capability (Rx Pause Only or Full Flow Control)
+             * and the link partner advertised none, we will configure
+             * ourselves to enable Rx Flow Control only.  We can do
+             * this safely for two reasons:  If the link partner really
+             * didn't want flow control enabled, and we enable Rx, no
+             * harm done since we won't be receiving any PAUSE frames
+             * anyway.  If the intent on the link partner was to have
+             * flow control enabled, then by us enabling RX only, we
+             * can at least receive pause frames and process them.
+             * This is a good idea because in most cases, since we are
+             * predominantly a server NIC, more times than not we will
+             * be asked to delay transmission of packets than asking
+             * our link partner to pause transmission of frames.
+             */
+            else if ((hw->original_fc == E1000_FC_NONE ||
+                      hw->original_fc == E1000_FC_TX_PAUSE) ||
+                      hw->fc_strict_ieee) {
+                hw->fc = E1000_FC_NONE;
+                DEBUGOUT("Flow Control = NONE.\n");
+            } else {
+                hw->fc = E1000_FC_RX_PAUSE;
+                DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
+            }
+
+            /* Now we need to do one last check...  If we auto-
+             * negotiated to HALF DUPLEX, flow control should not be
+             * enabled per IEEE 802.3 spec.
+             */
+            ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
+            if (ret_val) {
+                DEBUGOUT("Error getting link speed and duplex\n");
+                return ret_val;
+            }
+
+            if (duplex == HALF_DUPLEX)
+                hw->fc = E1000_FC_NONE;
+
+            /* Now we call a subroutine to actually force the MAC
+             * controller to use the correct flow control settings.
+             */
+            ret_val = e1000_force_mac_fc(hw);
+            if (ret_val) {
+                DEBUGOUT("Error forcing flow control settings\n");
+                return ret_val;
+            }
+        } else {
+            DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
+        }
+    }
+    return E1000_SUCCESS;
+}
+
+/******************************************************************************
+ * Checks to see if the link status of the hardware has changed.
+ *
+ * hw - Struct containing variables accessed by shared code
+ *
+ * Called by any function that needs to check the link status of the adapter.
+ *****************************************************************************/
+int32_t
+e1000_check_for_link(struct e1000_hw *hw)
+{
+    uint32_t rxcw = 0;
+    uint32_t ctrl;
+    uint32_t status;
+    uint32_t rctl;
+    uint32_t icr;
+    uint32_t signal = 0;
+    int32_t ret_val;
+    uint16_t phy_data;
+
+    DEBUGFUNC("e1000_check_for_link");
+
+    ctrl = E1000_READ_REG(hw, CTRL);
+    status = E1000_READ_REG(hw, STATUS);
+
+    /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
+     * set when the optics detect a signal. On older adapters, it will be
+     * cleared when there is a signal.  This applies to fiber media only.
+     */
+    if ((hw->media_type == e1000_media_type_fiber) ||
+        (hw->media_type == e1000_media_type_internal_serdes)) {
+        rxcw = E1000_READ_REG(hw, RXCW);
+
+        if (hw->media_type == e1000_media_type_fiber) {
+            signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
+            if (status & E1000_STATUS_LU)
+                hw->get_link_status = FALSE;
+        }
+    }
+
+    /* If we have a copper PHY then we only want to go out to the PHY
+     * registers to see if Auto-Neg has completed and/or if our link
+     * status has changed.  The get_link_status flag will be set if we
+     * receive a Link Status Change interrupt or we have Rx Sequence
+     * Errors.
+     */
+    if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
+        /* First we want to see if the MII Status Register reports
+         * link.  If so, then we want to get the current speed/duplex
+         * of the PHY.
+         * Read the register twice since the link bit is sticky.
+         */
+        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
+        if (ret_val)
+            return ret_val;
+        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
+        if (ret_val)
+            return ret_val;
+
+        if (phy_data & MII_SR_LINK_STATUS) {
+            hw->get_link_status = FALSE;
+            /* Check if there was DownShift, must be checked immediately after
+             * link-up */
+            e1000_check_downshift(hw);
+
+            /* If we are on 82544 or 82543 silicon and speed/duplex
+             * are forced to 10H or 10F, then we will implement the polarity
+             * reversal workaround.  We disable interrupts first, and upon
+             * returning, place the devices interrupt state to its previous
+             * value except for the link status change interrupt which will
+             * happen due to the execution of this workaround.
+             */
+
+            if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
+                (!hw->autoneg) &&
+                (hw->forced_speed_duplex == e1000_10_full ||
+                 hw->forced_speed_duplex == e1000_10_half)) {
+                E1000_WRITE_REG(hw, IMC, 0xffffffff);
+                ret_val = e1000_polarity_reversal_workaround(hw);
+                icr = E1000_READ_REG(hw, ICR);
+                E1000_WRITE_REG(hw, ICS, (icr & ~E1000_ICS_LSC));
+                E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK);
+            }
+
+        } else {
+            /* No link detected */
+            e1000_config_dsp_after_link_change(hw, FALSE);
+            return 0;
+        }
+
+        /* If we are forcing speed/duplex, then we simply return since
+         * we have already determined whether we have link or not.
+         */
+        if (!hw->autoneg) return -E1000_ERR_CONFIG;
+
+        /* optimize the dsp settings for the igp phy */
+        e1000_config_dsp_after_link_change(hw, TRUE);
+
+        /* We have a M88E1000 PHY and Auto-Neg is enabled.  If we
+         * have Si on board that is 82544 or newer, Auto
+         * Speed Detection takes care of MAC speed/duplex
+         * configuration.  So we only need to configure Collision
+         * Distance in the MAC.  Otherwise, we need to force
+         * speed/duplex on the MAC to the current PHY speed/duplex
+         * settings.
+         */
+        if (hw->mac_type >= e1000_82544)
+            e1000_config_collision_dist(hw);
+        else {
+            ret_val = e1000_config_mac_to_phy(hw);
+            if (ret_val) {
+                DEBUGOUT("Error configuring MAC to PHY settings\n");
+                return ret_val;
+            }
+        }
+
+        /* Configure Flow Control now that Auto-Neg has completed. First, we
+         * need to restore the desired flow control settings because we may
+         * have had to re-autoneg with a different link partner.
+         */
+        ret_val = e1000_config_fc_after_link_up(hw);
+        if (ret_val) {
+            DEBUGOUT("Error configuring flow control\n");
+            return ret_val;
+        }
+
+        /* At this point we know that we are on copper and we have
+         * auto-negotiated link.  These are conditions for checking the link
+         * partner capability register.  We use the link speed to determine if
+         * TBI compatibility needs to be turned on or off.  If the link is not
+         * at gigabit speed, then TBI compatibility is not needed.  If we are
+         * at gigabit speed, we turn on TBI compatibility.
+         */
+        if (hw->tbi_compatibility_en) {
+            uint16_t speed, duplex;
+            ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
+            if (ret_val) {
+                DEBUGOUT("Error getting link speed and duplex\n");
+                return ret_val;
+            }
+            if (speed != SPEED_1000) {
+                /* If link speed is not set to gigabit speed, we do not need
+                 * to enable TBI compatibility.
+                 */
+                if (hw->tbi_compatibility_on) {
+                    /* If we previously were in the mode, turn it off. */
+                    rctl = E1000_READ_REG(hw, RCTL);
+                    rctl &= ~E1000_RCTL_SBP;
+                    E1000_WRITE_REG(hw, RCTL, rctl);
+                    hw->tbi_compatibility_on = FALSE;
+                }
+            } else {
+                /* If TBI compatibility is was previously off, turn it on. For
+                 * compatibility with a TBI link partner, we will store bad
+                 * packets. Some frames have an additional byte on the end and
+                 * will look like CRC errors to to the hardware.
+                 */
+                if (!hw->tbi_compatibility_on) {
+                    hw->tbi_compatibility_on = TRUE;
+                    rctl = E1000_READ_REG(hw, RCTL);
+                    rctl |= E1000_RCTL_SBP;
+                    E1000_WRITE_REG(hw, RCTL, rctl);
+                }
+            }
+        }
+    }
+    /* If we don't have link (auto-negotiation failed or link partner cannot
+     * auto-negotiate), the cable is plugged in (we have signal), and our
+     * link partner is not trying to auto-negotiate with us (we are receiving
+     * idles or data), we need to force link up. We also need to give
+     * auto-negotiation time to complete, in case the cable was just plugged
+     * in. The autoneg_failed flag does this.
+     */
+    else if ((((hw->media_type == e1000_media_type_fiber) &&
+              ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
+              (hw->media_type == e1000_media_type_internal_serdes)) &&
+              (!(status & E1000_STATUS_LU)) &&
+              (!(rxcw & E1000_RXCW_C))) {
+        if (hw->autoneg_failed == 0) {
+            hw->autoneg_failed = 1;
+            return 0;
+        }
+        DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
+
+        /* Disable auto-negotiation in the TXCW register */
+        E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
+
+        /* Force link-up and also force full-duplex. */
+        ctrl = E1000_READ_REG(hw, CTRL);
+        ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
+        E1000_WRITE_REG(hw, CTRL, ctrl);
+
+        /* Configure Flow Control after forcing link up. */
+        ret_val = e1000_config_fc_after_link_up(hw);
+        if (ret_val) {
+            DEBUGOUT("Error configuring flow control\n");
+            return ret_val;
+        }
+    }
+    /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
+     * auto-negotiation in the TXCW register and disable forced link in the
+     * Device Control register in an attempt to auto-negotiate with our link
+     * partner.
+     */
+    else if (((hw->media_type == e1000_media_type_fiber) ||
+              (hw->media_type == e1000_media_type_internal_serdes)) &&
+              (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
+        DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
+        E1000_WRITE_REG(hw, TXCW, hw->txcw);
+        E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
+
+        hw->serdes_link_down = FALSE;
+    }
+    /* If we force link for non-auto-negotiation switch, check link status
+     * based on MAC synchronization for internal serdes media type.
+     */
+    else if ((hw->media_type == e1000_media_type_internal_serdes) &&
+             !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
+        /* SYNCH bit and IV bit are sticky. */
+        udelay(10);
+        if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
+            if (!(rxcw & E1000_RXCW_IV)) {
+                hw->serdes_link_down = FALSE;
+                DEBUGOUT("SERDES: Link is up.\n");
+            }
+        } else {
+            hw->serdes_link_down = TRUE;
+            DEBUGOUT("SERDES: Link is down.\n");
+        }
+    }
+    if ((hw->media_type == e1000_media_type_internal_serdes) &&
+        (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
+        hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS));
+    }
+    return E1000_SUCCESS;
+}
+
+/******************************************************************************
+ * Detects the current speed and duplex settings of the hardware.
+ *
+ * hw - Struct containing variables accessed by shared code
+ * speed - Speed of the connection
+ * duplex - Duplex setting of the connection
+ *****************************************************************************/
+int32_t
+e1000_get_speed_and_duplex(struct e1000_hw *hw,
+                           uint16_t *speed,
+                           uint16_t *duplex)
+{
+    uint32_t status;
+    int32_t ret_val;
+    uint16_t phy_data;
+
+    DEBUGFUNC("e1000_get_speed_and_duplex");
+
+    if (hw->mac_type >= e1000_82543) {
+        status = E1000_READ_REG(hw, STATUS);
+        if (status & E1000_STATUS_SPEED_1000) {
+            *speed = SPEED_1000;
+            DEBUGOUT("1000 Mbs, ");
+        } else if (status & E1000_STATUS_SPEED_100) {
+            *speed = SPEED_100;
+            DEBUGOUT("100 Mbs, ");
+        } else {
+            *speed = SPEED_10;
+            DEBUGOUT("10 Mbs, ");
+        }
+
+        if (status & E1000_STATUS_FD) {
+            *duplex = FULL_DUPLEX;
+            DEBUGOUT("Full Duplex\n");
+        } else {
+            *duplex = HALF_DUPLEX;
+            DEBUGOUT(" Half Duplex\n");
+        }
+    } else {
+        DEBUGOUT("1000 Mbs, Full Duplex\n");
+        *speed = SPEED_1000;
+        *duplex = FULL_DUPLEX;
+    }
+
+    /* IGP01 PHY may advertise full duplex operation after speed downgrade even
+     * if it is operating at half duplex.  Here we set the duplex settings to
+     * match the duplex in the link partner's capabilities.
+     */
+    if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
+        ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
+        if (ret_val)
+            return ret_val;
+
+        if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
+            *duplex = HALF_DUPLEX;
+        else {
+            ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
+            if (ret_val)
+                return ret_val;
+            if ((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
+               (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
+                *duplex = HALF_DUPLEX;
+        }
+    }
+
+    if ((hw->mac_type == e1000_80003es2lan) &&
+        (hw->media_type == e1000_media_type_copper)) {
+        if (*speed == SPEED_1000)
+            ret_val = e1000_configure_kmrn_for_1000(hw);
+        else
+            ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
+        if (ret_val)
+            return ret_val;
+    }
+
+    if ((hw->phy_type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
+        ret_val = e1000_kumeran_lock_loss_workaround(hw);
+        if (ret_val)
+            return ret_val;
+    }
+
+    return E1000_SUCCESS;
+}
+
+/******************************************************************************
+* Blocks until autoneg completes or times out (~4.5 seconds)
+*
+* hw - Struct containing variables accessed by shared code
+******************************************************************************/
+static int32_t
+e1000_wait_autoneg(struct e1000_hw *hw)
+{
+    int32_t ret_val;
+    uint16_t i;
+    uint16_t phy_data;
+
+    DEBUGFUNC("e1000_wait_autoneg");
+    DEBUGOUT("Waiting for Auto-Neg to complete.\n");
+
+    /* We will wait for autoneg to complete or 4.5 seconds to expire. */
+    for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
+        /* Read the MII Status Register and wait for Auto-Neg
+         * Complete bit to be set.
+         */
+        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
+        if (ret_val)
+            return ret_val;
+        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
+        if (ret_val)
+            return ret_val;
+        if (phy_data & MII_SR_AUTONEG_COMPLETE) {
+            return E1000_SUCCESS;
+        }
+        msleep(100);
+    }
+    return E1000_SUCCESS;
+}
+
+/******************************************************************************
+* Raises the Management Data Clock
+*
+* hw - Struct containing variables accessed by shared code
+* ctrl - Device control register's current value
+******************************************************************************/
+static void
+e1000_raise_mdi_clk(struct e1000_hw *hw,
+                    uint32_t *ctrl)
+{
+    /* Raise the clock input to the Management Data Clock (by setting the MDC
+     * bit), and then delay 10 microseconds.
+     */
+    E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
+    E1000_WRITE_FLUSH(hw);
+    udelay(10);
+}
+
+/******************************************************************************
+* Lowers the Management Data Clock
+*
+* hw - Struct containing variables accessed by shared code
+* ctrl - Device control register's current value
+******************************************************************************/
+static void
+e1000_lower_mdi_clk(struct e1000_hw *hw,
+                    uint32_t *ctrl)
+{
+    /* Lower the clock input to the Management Data Clock (by clearing the MDC
+     * bit), and then delay 10 microseconds.
+     */
+    E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
+    E1000_WRITE_FLUSH(hw);
+    udelay(10);
+}
+
+/******************************************************************************
+* Shifts data bits out to the PHY
+*
+* hw - Struct containing variables accessed by shared code
+* data - Data to send out to the PHY
+* count - Number of bits to shift out
+*
+* Bits are shifted out in MSB to LSB order.
+******************************************************************************/
+static void
+e1000_shift_out_mdi_bits(struct e1000_hw *hw,
+                         uint32_t data,
+                         uint16_t count)
+{
+    uint32_t ctrl;
+    uint32_t mask;
+
+    /* We need to shift "count" number of bits out to the PHY. So, the value
+     * in the "data" parameter will be shifted out to the PHY one bit at a
+     * time. In order to do this, "data" must be broken down into bits.
+     */
+    mask = 0x01;
+    mask <<= (count - 1);
+
+    ctrl = E1000_READ_REG(hw, CTRL);
+
+    /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
+    ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
+
+    while (mask) {
+        /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
+         * then raising and lowering the Management Data Clock. A "0" is
+         * shifted out to the PHY by setting the MDIO bit to "0" and then
+         * raising and lowering the clock.
+         */
+        if (data & mask)
+            ctrl |= E1000_CTRL_MDIO;
+        else
+            ctrl &= ~E1000_CTRL_MDIO;
+
+        E1000_WRITE_REG(hw, CTRL, ctrl);
+        E1000_WRITE_FLUSH(hw);
+
+        udelay(10);
+
+        e1000_raise_mdi_clk(hw, &ctrl);
+        e1000_lower_mdi_clk(hw, &ctrl);
+
+        mask = mask >> 1;
+    }
+}
+
+/******************************************************************************
+* Shifts data bits in from the PHY
+*
+* hw - Struct containing variables accessed by shared code
+*
+* Bits are shifted in in MSB to LSB order.
+******************************************************************************/
+static uint16_t
+e1000_shift_in_mdi_bits(struct e1000_hw *hw)
+{
+    uint32_t ctrl;
+    uint16_t data = 0;
+    uint8_t i;
+
+    /* In order to read a register from the PHY, we need to shift in a total
+     * of 18 bits from the PHY. The first two bit (turnaround) times are used
+     * to avoid contention on the MDIO pin when a read operation is performed.
+     * These two bits are ignored by us and thrown away. Bits are "shifted in"
+     * by raising the input to the Management Data Clock (setting the MDC bit),
+     * and then reading the value of the MDIO bit.
+     */
+    ctrl = E1000_READ_REG(hw, CTRL);
+
+    /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
+    ctrl &= ~E1000_CTRL_MDIO_DIR;
+    ctrl &= ~E1000_CTRL_MDIO;
+
+    E1000_WRITE_REG(hw, CTRL, ctrl);
+    E1000_WRITE_FLUSH(hw);
+
+    /* Raise and Lower the clock before reading in the data. This accounts for
+     * the turnaround bits. The first clock occurred when we clocked out the
+     * last bit of the Register Address.
+     */
+    e1000_raise_mdi_clk(hw, &ctrl);
+    e1000_lower_mdi_clk(hw, &ctrl);
+
+    for (data = 0, i = 0; i < 16; i++) {
+        data = data << 1;
+        e1000_raise_mdi_clk(hw, &ctrl);
+        ctrl = E1000_READ_REG(hw, CTRL);
+        /* Check to see if we shifted in a "1". */
+        if (ctrl & E1000_CTRL_MDIO)
+            data |= 1;
+        e1000_lower_mdi_clk(hw, &ctrl);
+    }
+
+    e1000_raise_mdi_clk(hw, &ctrl);
+    e1000_lower_mdi_clk(hw, &ctrl);
+
+    return data;
+}
+
+static int32_t
+e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
+{
+    uint32_t swfw_sync = 0;
+    uint32_t swmask = mask;
+    uint32_t fwmask = mask << 16;
+    int32_t timeout = 200;
+
+    DEBUGFUNC("e1000_swfw_sync_acquire");
+
+    if (hw->swfwhw_semaphore_present)
+        return e1000_get_software_flag(hw);
+
+    if (!hw->swfw_sync_present)
+        return e1000_get_hw_eeprom_semaphore(hw);
+
+    while (timeout) {
+            if (e1000_get_hw_eeprom_semaphore(hw))
+                return -E1000_ERR_SWFW_SYNC;
+
+            swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
+            if (!(swfw_sync & (fwmask | swmask))) {
+                break;
+            }
+
+            /* firmware currently using resource (fwmask) */
+            /* or other software thread currently using resource (swmask) */
+            e1000_put_hw_eeprom_semaphore(hw);
+            mdelay(5);
+            timeout--;
+    }
+
+    if (!timeout) {
+        DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
+        return -E1000_ERR_SWFW_SYNC;
+    }
+
+    swfw_sync |= swmask;
+    E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
+
+    e1000_put_hw_eeprom_semaphore(hw);
+    return E1000_SUCCESS;
+}
+
+static void
+e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
+{
+    uint32_t swfw_sync;
+    uint32_t swmask = mask;
+
+    DEBUGFUNC("e1000_swfw_sync_release");
+
+    if (hw->swfwhw_semaphore_present) {
+        e1000_release_software_flag(hw);
+        return;
+    }
+
+    if (!hw->swfw_sync_present) {
+        e1000_put_hw_eeprom_semaphore(hw);
+        return;
+    }
+
+    /* if (e1000_get_hw_eeprom_semaphore(hw))
+     *    return -E1000_ERR_SWFW_SYNC; */
+    while (e1000_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS);
+        /* empty */
+
+    swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
+    swfw_sync &= ~swmask;
+    E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
+
+    e1000_put_hw_eeprom_semaphore(hw);
+}
+
+/*****************************************************************************
+* Reads the value from a PHY register, if the value is on a specific non zero
+* page, sets the page first.
+* hw - Struct containing variables accessed by shared code
+* reg_addr - address of the PHY register to read
+******************************************************************************/
+int32_t
+e1000_read_phy_reg(struct e1000_hw *hw,
+                   uint32_t reg_addr,
+                   uint16_t *phy_data)
+{
+    uint32_t ret_val;
+    uint16_t swfw;
+
+    DEBUGFUNC("e1000_read_phy_reg");
+
+    if ((hw->mac_type == e1000_80003es2lan) &&
+        (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
+        swfw = E1000_SWFW_PHY1_SM;
+    } else {
+        swfw = E1000_SWFW_PHY0_SM;
+    }
+    if (e1000_swfw_sync_acquire(hw, swfw))
+        return -E1000_ERR_SWFW_SYNC;
+
+    if ((hw->phy_type == e1000_phy_igp ||
+        hw->phy_type == e1000_phy_igp_3 ||
+        hw->phy_type == e1000_phy_igp_2) &&
+       (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
+        ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
+                                         (uint16_t)reg_addr);
+        if (ret_val) {
+            e1000_swfw_sync_release(hw, swfw);
+            return ret_val;
+        }
+    } else if (hw->phy_type == e1000_phy_gg82563) {
+        if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
+            (hw->mac_type == e1000_80003es2lan)) {
+            /* Select Configuration Page */
+            if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
+                ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
+                          (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
+            } else {
+                /* Use Alternative Page Select register to access
+                 * registers 30 and 31
+                 */
+                ret_val = e1000_write_phy_reg_ex(hw,
+                                                 GG82563_PHY_PAGE_SELECT_ALT,
+                          (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
+            }
+
+            if (ret_val) {
+                e1000_swfw_sync_release(hw, swfw);
+                return ret_val;
+            }
+        }
+    }
+
+    ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
+                                    phy_data);
+
+    e1000_swfw_sync_release(hw, swfw);
+    return ret_val;
+}
+
+static int32_t
+e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
+                      uint16_t *phy_data)
+{
+    uint32_t i;
+    uint32_t mdic = 0;
+    const uint32_t phy_addr = 1;
+
+    DEBUGFUNC("e1000_read_phy_reg_ex");
+
+    if (reg_addr > MAX_PHY_REG_ADDRESS) {
+        DEBUGOUT1("PHY Address %ld is out of range\n", reg_addr);
+        return -E1000_ERR_PARAM;
+    }
+
+    if (hw->mac_type > e1000_82543) {
+        /* Set up Op-code, Phy Address, and register address in the MDI
+         * Control register.  The MAC will take care of interfacing with the
+         * PHY to retrieve the desired data.
+         */
+        mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
+                (phy_addr << E1000_MDIC_PHY_SHIFT) |
+                (E1000_MDIC_OP_READ));
+
+        E1000_WRITE_REG(hw, MDIC, mdic);
+
+        /* Poll the ready bit to see if the MDI read completed */
+        for (i = 0; i < 64; i++) {
+            udelay(50);
+            mdic = E1000_READ_REG(hw, MDIC);
+            if (mdic & E1000_MDIC_READY) break;
+        }
+        if (!(mdic & E1000_MDIC_READY)) {
+            DEBUGOUT("MDI Read did not complete\n");
+            return -E1000_ERR_PHY;
+        }
+        if (mdic & E1000_MDIC_ERROR) {
+            DEBUGOUT("MDI Error\n");
+            return -E1000_ERR_PHY;
+        }
+        *phy_data = (uint16_t) mdic;
+    } else {
+        /* We must first send a preamble through the MDIO pin to signal the
+         * beginning of an MII instruction.  This is done by sending 32
+         * consecutive "1" bits.
+         */
+        e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
+
+        /* Now combine the next few fields that are required for a read
+         * operation.  We use this method instead of calling the
+         * e1000_shift_out_mdi_bits routine five different times. The format of
+         * a MII read instruction consists of a shift out of 14 bits and is
+         * defined as follows:
+         *    <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
+         * followed by a shift in of 18 bits.  This first two bits shifted in
+         * are TurnAround bits used to avoid contention on the MDIO pin when a
+         * READ operation is performed.  These two bits are thrown away
+         * followed by a shift in of 16 bits which contains the desired data.
+         */
+        mdic = ((reg_addr) | (phy_addr << 5) |
+                (PHY_OP_READ << 10) | (PHY_SOF << 12));
+
+        e1000_shift_out_mdi_bits(hw, mdic, 14);
+
+        /* Now that we've shifted out the read command to the MII, we need to
+         * "shift in" the 16-bit value (18 total bits) of the requested PHY
+         * register address.
+         */
+        *phy_data = e1000_shift_in_mdi_bits(hw);
+    }
+    return E1000_SUCCESS;
+}
+
+/******************************************************************************
+* Writes a value to a PHY register
+*
+* hw - Struct containing variables accessed by shared code
+* reg_addr - address of the PHY register to write
+* data - data to write to the PHY
+******************************************************************************/
+int32_t
+e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
+                    uint16_t phy_data)
+{
+    uint32_t ret_val;
+    uint16_t swfw;
+
+    DEBUGFUNC("e1000_write_phy_reg");
+
+    if ((hw->mac_type == e1000_80003es2lan) &&
+        (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
+        swfw = E1000_SWFW_PHY1_SM;
+    } else {
+        swfw = E1000_SWFW_PHY0_SM;
+    }
+    if (e1000_swfw_sync_acquire(hw, swfw))
+        return -E1000_ERR_SWFW_SYNC;
+
+    if ((hw->phy_type == e1000_phy_igp ||
+        hw->phy_type == e1000_phy_igp_3 ||
+        hw->phy_type == e1000_phy_igp_2) &&
+       (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
+        ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
+                                         (uint16_t)reg_addr);
+        if (ret_val) {
+            e1000_swfw_sync_release(hw, swfw);
+            return ret_val;
+        }
+    } else if (hw->phy_type == e1000_phy_gg82563) {
+        if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
+            (hw->mac_type == e1000_80003es2lan)) {
+            /* Select Configuration Page */
+            if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
+                ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
+                          (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
+            } else {
+                /* Use Alternative Page Select register to access
+                 * registers 30 and 31
+                 */
+                ret_val = e1000_write_phy_reg_ex(hw,
+                                                 GG82563_PHY_PAGE_SELECT_ALT,
+                          (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
+            }
+
+            if (ret_val) {
+                e1000_swfw_sync_release(hw, swfw);
+                return ret_val;
+            }
+        }
+    }
+
+    ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
+                                     phy_data);
+
+    e1000_swfw_sync_release(hw, swfw);
+    return ret_val;
+}
+
+static int32_t
+e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
+                       uint16_t phy_data)
+{
+    uint32_t i;
+    uint32_t mdic = 0;
+    const uint32_t phy_addr = 1;
+
+    DEBUGFUNC("e1000_write_phy_reg_ex");
+
+    if (reg_addr > MAX_PHY_REG_ADDRESS) {
+        DEBUGOUT1("PHY Address %ld is out of range\n", reg_addr);
+        return -E1000_ERR_PARAM;
+    }
+
+    if (hw->mac_type > e1000_82543) {
+        /* Set up Op-code, Phy Address, register address, and data intended
+         * for the PHY register in the MDI Control register.  The MAC will take
+         * care of interfacing with the PHY to send the desired data.
+         */
+        mdic = (((uint32_t) phy_data) |
+                (reg_addr << E1000_MDIC_REG_SHIFT) |
+                (phy_addr << E1000_MDIC_PHY_SHIFT) |
+                (E1000_MDIC_OP_WRITE));
+
+        E1000_WRITE_REG(hw, MDIC, mdic);
+
+        /* Poll the ready bit to see if the MDI read completed */
+        for (i = 0; i < 641; i++) {
+            udelay(5);
+            mdic = E1000_READ_REG(hw, MDIC);
+            if (mdic & E1000_MDIC_READY) break;
+        }
+        if (!(mdic & E1000_MDIC_READY)) {
+            DEBUGOUT("MDI Write did not complete\n");
+            return -E1000_ERR_PHY;
+        }
+    } else {
+        /* We'll need to use the SW defined pins to shift the write command
+         * out to the PHY. We first send a preamble to the PHY to signal the
+         * beginning of the MII instruction.  This is done by sending 32
+         * consecutive "1" bits.
+         */
+        e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
+
+        /* Now combine the remaining required fields that will indicate a
+         * write operation. We use this method instead of calling the
+         * e1000_shift_out_mdi_bits routine for each field in the command. The
+         * format of a MII write instruction is as follows:
+         * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
+         */
+        mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
+                (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
+        mdic <<= 16;
+        mdic |= (uint32_t) phy_data;
+
+        e1000_shift_out_mdi_bits(hw, mdic, 32);
+    }
+
+    return E1000_SUCCESS;
+}
+
+static int32_t
+e1000_read_kmrn_reg(struct e1000_hw *hw,
+                    uint32_t reg_addr,
+                    uint16_t *data)
+{
+    uint32_t reg_val;
+    uint16_t swfw;
+    DEBUGFUNC("e1000_read_kmrn_reg");
+
+    if ((hw->mac_type == e1000_80003es2lan) &&
+        (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
+        swfw = E1000_SWFW_PHY1_SM;
+    } else {
+        swfw = E1000_SWFW_PHY0_SM;
+    }
+    if (e1000_swfw_sync_acquire(hw, swfw))
+        return -E1000_ERR_SWFW_SYNC;
+
+    /* Write register address */
+    reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
+              E1000_KUMCTRLSTA_OFFSET) |
+              E1000_KUMCTRLSTA_REN;
+    E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
+    udelay(2);
+
+    /* Read the data returned */
+    reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
+    *data = (uint16_t)reg_val;
+
+    e1000_swfw_sync_release(hw, swfw);
+    return E1000_SUCCESS;
+}
+
+static int32_t
+e1000_write_kmrn_reg(struct e1000_hw *hw,
+                     uint32_t reg_addr,
+                     uint16_t data)
+{
+    uint32_t reg_val;
+    uint16_t swfw;
+    DEBUGFUNC("e1000_write_kmrn_reg");
+
+    if ((hw->mac_type == e1000_80003es2lan) &&
+        (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
+        swfw = E1000_SWFW_PHY1_SM;
+    } else {
+        swfw = E1000_SWFW_PHY0_SM;
+    }
+    if (e1000_swfw_sync_acquire(hw, swfw))
+        return -E1000_ERR_SWFW_SYNC;
+
+    reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
+              E1000_KUMCTRLSTA_OFFSET) | data;
+    E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
+    udelay(2);
+
+    e1000_swfw_sync_release(hw, swfw);
+    return E1000_SUCCESS;
+}
+
+/******************************************************************************
+* Returns the PHY to the power-on reset state
+*
+* hw - Struct containing variables accessed by shared code
+******************************************************************************/
+int32_t
+e1000_phy_hw_reset(struct e1000_hw *hw)
+{
+    uint32_t ctrl, ctrl_ext;
+    uint32_t led_ctrl;
+    int32_t ret_val;
+    uint16_t swfw;
+
+    DEBUGFUNC("e1000_phy_hw_reset");
+
+    /* In the case of the phy reset being blocked, it's not an error, we
+     * simply return success without performing the reset. */
+    ret_val = e1000_check_phy_reset_block(hw);
+    if (ret_val)
+        return E1000_SUCCESS;
+
+    DEBUGOUT("Resetting Phy...\n");
+
+    if (hw->mac_type > e1000_82543) {
+        if ((hw->mac_type == e1000_80003es2lan) &&
+            (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
+            swfw = E1000_SWFW_PHY1_SM;
+        } else {
+            swfw = E1000_SWFW_PHY0_SM;
+        }
+        if (e1000_swfw_sync_acquire(hw, swfw)) {
+            DEBUGOUT("Unable to acquire swfw sync\n");
+            return -E1000_ERR_SWFW_SYNC;
+        }
+        /* Read the device control register and assert the E1000_CTRL_PHY_RST
+         * bit. Then, take it out of reset.
+         * For pre-e1000_82571 hardware, we delay for 10ms between the assert
+         * and deassert.  For e1000_82571 hardware and later, we instead delay
+         * for 50us between and 10ms after the deassertion.
+         */
+        ctrl = E1000_READ_REG(hw, CTRL);
+        E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
+        E1000_WRITE_FLUSH(hw);
+
+        if (hw->mac_type < e1000_82571)
+            msleep(10);
+        else
+            udelay(100);
+
+        E1000_WRITE_REG(hw, CTRL, ctrl);
+        E1000_WRITE_FLUSH(hw);
+
+        if (hw->mac_type >= e1000_82571)
+            mdelay(10);
+
+        e1000_swfw_sync_release(hw, swfw);
+    } else {
+        /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
+         * bit to put the PHY into reset. Then, take it out of reset.
+         */
+        ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
+        ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
+        ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
+        E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
+        E1000_WRITE_FLUSH(hw);
+        msleep(10);
+        ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
+        E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
+        E1000_WRITE_FLUSH(hw);
+    }
+    udelay(150);
+
+    if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
+        /* Configure activity LED after PHY reset */
+        led_ctrl = E1000_READ_REG(hw, LEDCTL);
+        led_ctrl &= IGP_ACTIVITY_LED_MASK;
+        led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
+        E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
+    }
+
+    /* Wait for FW to finish PHY configuration. */
+    ret_val = e1000_get_phy_cfg_done(hw);
+    if (ret_val != E1000_SUCCESS)
+        return ret_val;
+    e1000_release_software_semaphore(hw);
+
+    if ((hw->mac_type == e1000_ich8lan) && (hw->phy_type == e1000_phy_igp_3))
+        ret_val = e1000_init_lcd_from_nvm(hw);
+
+    return ret_val;
+}
+
+/******************************************************************************
+* Resets the PHY
+*
+* hw - Struct containing variables accessed by shared code
+*
+* Sets bit 15 of the MII Control register
+******************************************************************************/
+int32_t
+e1000_phy_reset(struct e1000_hw *hw)
+{
+    int32_t ret_val;
+    uint16_t phy_data;
+
+    DEBUGFUNC("e1000_phy_reset");
+
+    /* In the case of the phy reset being blocked, it's not an error, we
+     * simply return success without performing the reset. */
+    ret_val = e1000_check_phy_reset_block(hw);
+    if (ret_val)
+        return E1000_SUCCESS;
+
+    switch (hw->phy_type) {
+    case e1000_phy_igp:
+    case e1000_phy_igp_2:
+    case e1000_phy_igp_3:
+    case e1000_phy_ife:
+        ret_val = e1000_phy_hw_reset(hw);
+        if (ret_val)
+            return ret_val;
+        break;
+    default:
+        ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
+        if (ret_val)
+            return ret_val;
+
+        phy_data |= MII_CR_RESET;
+        ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
+        if (ret_val)
+            return ret_val;
+
+        udelay(1);
+        break;
+    }
+
+    if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
+        e1000_phy_init_script(hw);
+
+    return E1000_SUCCESS;
+}
+
+/******************************************************************************
+* Work-around for 82566 power-down: on D3 entry-
+* 1) disable gigabit link
+* 2) write VR power-down enable
+* 3) read it back
+* if successful continue, else issue LCD reset and repeat
+*
+* hw - struct containing variables accessed by shared code
+******************************************************************************/
+void
+e1000_phy_powerdown_workaround(struct e1000_hw *hw)
+{
+    int32_t reg;
+    uint16_t phy_data;
+    int32_t retry = 0;
+
+    DEBUGFUNC("e1000_phy_powerdown_workaround");
+
+    if (hw->phy_type != e1000_phy_igp_3)
+        return;
+
+    do {
+        /* Disable link */
+        reg = E1000_READ_REG(hw, PHY_CTRL);
+        E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
+                        E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
+
+        /* Write VR power-down enable - bits 9:8 should be 10b */
+        e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
+        phy_data |= (1 << 9);
+        phy_data &= ~(1 << 8);
+        e1000_write_phy_reg(hw, IGP3_VR_CTRL, phy_data);
+
+        /* Read it back and test */
+        e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
+        if (((phy_data & IGP3_VR_CTRL_MODE_MASK) == IGP3_VR_CTRL_MODE_SHUT) || retry)
+            break;
+
+        /* Issue PHY reset and repeat at most one more time */
+        reg = E1000_READ_REG(hw, CTRL);
+        E1000_WRITE_REG(hw, CTRL, reg | E1000_CTRL_PHY_RST);
+        retry++;
+    } while (retry);
+
+    return;
+
+}
+
+/******************************************************************************
+* Work-around for 82566 Kumeran PCS lock loss:
+* On link status change (i.e. PCI reset, speed change) and link is up and
+* speed is gigabit-
+* 0) if workaround is optionally disabled do nothing
+* 1) wait 1ms for Kumeran link to come up
+* 2) check Kumeran Diagnostic register PCS lock loss bit
+* 3) if not set the link is locked (all is good), otherwise...
+* 4) reset the PHY
+* 5) repeat up to 10 times
+* Note: this is only called for IGP3 copper when speed is 1gb.
+*
+* hw - struct containing variables accessed by shared code
+******************************************************************************/
+static int32_t
+e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw)
+{
+    int32_t ret_val;
+    int32_t reg;
+    int32_t cnt;
+    uint16_t phy_data;
+
+    if (hw->kmrn_lock_loss_workaround_disabled)
+        return E1000_SUCCESS;
+
+    /* Make sure link is up before proceeding.  If not just return.
+     * Attempting this while link is negotiating fouled up link
+     * stability */
+    ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
+    ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
+
+    if (phy_data & MII_SR_LINK_STATUS) {
+        for (cnt = 0; cnt < 10; cnt++) {
+            /* read once to clear */
+            ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
+            if (ret_val)
+                return ret_val;
+            /* and again to get new status */
+            ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
+            if (ret_val)
+                return ret_val;
+
+            /* check for PCS lock */
+            if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
+                return E1000_SUCCESS;
+
+            /* Issue PHY reset */
+            e1000_phy_hw_reset(hw);
+            mdelay(5);
+        }
+        /* Disable GigE link negotiation */
+        reg = E1000_READ_REG(hw, PHY_CTRL);
+        E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
+                        E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
+
+        /* unable to acquire PCS lock */
+        return E1000_ERR_PHY;
+    }
+
+    return E1000_SUCCESS;
+}
+
+/******************************************************************************
+* Probes the expected PHY address for known PHY IDs
+*
+* hw - Struct containing variables accessed by shared code
+******************************************************************************/
+static int32_t
+e1000_detect_gig_phy(struct e1000_hw *hw)
+{
+    int32_t phy_init_status, ret_val;
+    uint16_t phy_id_high, phy_id_low;
+    boolean_t match = FALSE;
+
+    DEBUGFUNC("e1000_detect_gig_phy");
+
+    if (hw->phy_id != 0)
+        return E1000_SUCCESS;
+
+    /* The 82571 firmware may still be configuring the PHY.  In this
+     * case, we cannot access the PHY until the configuration is done.  So
+     * we explicitly set the PHY values. */
+    if (hw->mac_type == e1000_82571 ||
+        hw->mac_type == e1000_82572) {
+        hw->phy_id = IGP01E1000_I_PHY_ID;
+        hw->phy_type = e1000_phy_igp_2;
+        return E1000_SUCCESS;
+    }
+
+    /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a work-
+     * around that forces PHY page 0 to be set or the reads fail.  The rest of
+     * the code in this routine uses e1000_read_phy_reg to read the PHY ID.
+     * So for ESB-2 we need to have this set so our reads won't fail.  If the
+     * attached PHY is not a e1000_phy_gg82563, the routines below will figure
+     * this out as well. */
+    if (hw->mac_type == e1000_80003es2lan)
+        hw->phy_type = e1000_phy_gg82563;
+
+    /* Read the PHY ID Registers to identify which PHY is onboard. */
+    ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
+    if (ret_val)
+        return ret_val;
+
+    hw->phy_id = (uint32_t) (phy_id_high << 16);
+    udelay(20);
+    ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
+    if (ret_val)
+        return ret_val;
+
+    hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
+    hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
+
+    switch (hw->mac_type) {
+    case e1000_82543:
+        if (hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
+        break;
+    case e1000_82544:
+        if (hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
+        break;
+    case e1000_82540:
+    case e1000_82545:
+    case e1000_82545_rev_3:
+    case e1000_82546:
+    case e1000_82546_rev_3:
+        if (hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
+        break;
+    case e1000_82541:
+    case e1000_82541_rev_2:
+    case e1000_82547:
+    case e1000_82547_rev_2:
+        if (hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
+        break;
+    case e1000_82573:
+        if (hw->phy_id == M88E1111_I_PHY_ID) match = TRUE;
+        break;
+    case e1000_80003es2lan:
+        if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE;
+        break;
+    case e1000_ich8lan:
+        if (hw->phy_id == IGP03E1000_E_PHY_ID) match = TRUE;
+        if (hw->phy_id == IFE_E_PHY_ID) match = TRUE;
+        if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = TRUE;
+        if (hw->phy_id == IFE_C_E_PHY_ID) match = TRUE;
+        break;
+    default:
+        DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
+        return -E1000_ERR_CONFIG;
+    }
+    phy_init_status = e1000_set_phy_type(hw);
+
+    if ((match) && (phy_init_status == E1000_SUCCESS)) {
+        DEBUGOUT1("PHY ID %#08lx detected\n", hw->phy_id);
+        return E1000_SUCCESS;
+    }
+    DEBUGOUT1("Invalid PHY ID %#08lx\n", hw->phy_id);
+    return -E1000_ERR_PHY;
+}
+
+/******************************************************************************
+* Resets the PHY's DSP
+*
+* hw - Struct containing variables accessed by shared code
+******************************************************************************/
+static int32_t
+e1000_phy_reset_dsp(struct e1000_hw *hw)
+{
+    int32_t ret_val;
+    DEBUGFUNC("e1000_phy_reset_dsp");
+
+    do {
+        if (hw->phy_type != e1000_phy_gg82563) {
+            ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
+            if (ret_val) break;
+        }
+        ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
+        if (ret_val) break;
+        ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
+        if (ret_val) break;
+        ret_val = E1000_SUCCESS;
+    } while (0);
+
+    return ret_val;
+}
+
+/******************************************************************************
+* Get PHY information from various PHY registers for igp PHY only.
+*
+* hw - Struct containing variables accessed by shared code
+* phy_info - PHY information structure
+******************************************************************************/
+static int32_t
+e1000_phy_igp_get_info(struct e1000_hw *hw,
+                       struct e1000_phy_info *phy_info)
+{
+    int32_t ret_val;
+    uint16_t phy_data, min_length, max_length, average;
+    e1000_rev_polarity polarity;
+
+    DEBUGFUNC("e1000_phy_igp_get_info");
+
+    /* The downshift status is checked only once, after link is established,
+     * and it stored in the hw->speed_downgraded parameter. */
+    phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
+
+    /* IGP01E1000 does not need to support it. */
+    phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
+
+    /* IGP01E1000 always correct polarity reversal */
+    phy_info->polarity_correction = e1000_polarity_reversal_enabled;
+
+    /* Check polarity status */
+    ret_val = e1000_check_polarity(hw, &polarity);
+    if (ret_val)
+        return ret_val;
+
+    phy_info->cable_polarity = polarity;
+
+    ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
+    if (ret_val)
+        return ret_val;
+
+    phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & IGP01E1000_PSSR_MDIX) >>
+                          IGP01E1000_PSSR_MDIX_SHIFT);
+
+    if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
+       IGP01E1000_PSSR_SPEED_1000MBPS) {
+        /* Local/Remote Receiver Information are only valid at 1000 Mbps */
+        ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
+        if (ret_val)
+            return ret_val;
+
+        phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
+                             SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
+                             e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
+        phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
+                              SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
+                              e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
+
+        /* Get cable length */
+        ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
+        if (ret_val)
+            return ret_val;
+
+        /* Translate to old method */
+        average = (max_length + min_length) / 2;
+
+        if (average <= e1000_igp_cable_length_50)
+            phy_info->cable_length = e1000_cable_length_50;
+        else if (average <= e1000_igp_cable_length_80)
+            phy_info->cable_length = e1000_cable_length_50_80;
+        else if (average <= e1000_igp_cable_length_110)
+            phy_info->cable_length = e1000_cable_length_80_110;
+        else if (average <= e1000_igp_cable_length_140)
+            phy_info->cable_length = e1000_cable_length_110_140;
+        else
+            phy_info->cable_length = e1000_cable_length_140;
+    }
+
+    return E1000_SUCCESS;
+}
+
+/******************************************************************************
+* Get PHY information from various PHY registers for ife PHY only.
+*
+* hw - Struct containing variables accessed by shared code
+* phy_info - PHY information structure
+******************************************************************************/
+static int32_t
+e1000_phy_ife_get_info(struct e1000_hw *hw,
+                       struct e1000_phy_info *phy_info)
+{
+    int32_t ret_val;
+    uint16_t phy_data;
+    e1000_rev_polarity polarity;
+
+    DEBUGFUNC("e1000_phy_ife_get_info");
+
+    phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
+    phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
+
+    ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
+    if (ret_val)
+        return ret_val;
+    phy_info->polarity_correction =
+                        ((phy_data & IFE_PSC_AUTO_POLARITY_DISABLE) >>
+                        IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT) ?
+                        e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
+
+    if (phy_info->polarity_correction == e1000_polarity_reversal_enabled) {
+        ret_val = e1000_check_polarity(hw, &polarity);
+        if (ret_val)
+            return ret_val;
+    } else {
+        /* Polarity is forced. */
+        polarity = ((phy_data & IFE_PSC_FORCE_POLARITY) >>
+                     IFE_PSC_FORCE_POLARITY_SHIFT) ?
+                     e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
+    }
+    phy_info->cable_polarity = polarity;
+
+    ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
+    if (ret_val)
+        return ret_val;
+
+    phy_info->mdix_mode = (e1000_auto_x_mode)
+                     ((phy_data & (IFE_PMC_AUTO_MDIX | IFE_PMC_FORCE_MDIX)) >>
+                     IFE_PMC_MDIX_MODE_SHIFT);
+
+    return E1000_SUCCESS;
+}
+
+/******************************************************************************
+* Get PHY information from various PHY registers fot m88 PHY only.
+*
+* hw - Struct containing variables accessed by shared code
+* phy_info - PHY information structure
+******************************************************************************/
+static int32_t
+e1000_phy_m88_get_info(struct e1000_hw *hw,
+                       struct e1000_phy_info *phy_info)
+{
+    int32_t ret_val;
+    uint16_t phy_data;
+    e1000_rev_polarity polarity;
+
+    DEBUGFUNC("e1000_phy_m88_get_info");
+
+    /* The downshift status is checked only once, after link is established,
+     * and it stored in the hw->speed_downgraded parameter. */
+    phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
+
+    ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
+    if (ret_val)
+        return ret_val;
+
+    phy_info->extended_10bt_distance =
+        ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
+        M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ?
+        e1000_10bt_ext_dist_enable_lower : e1000_10bt_ext_dist_enable_normal;
+
+    phy_info->polarity_correction =
+        ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
+        M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ?
+        e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
+
+    /* Check polarity status */
+    ret_val = e1000_check_polarity(hw, &polarity);
+    if (ret_val)
+        return ret_val;
+    phy_info->cable_polarity = polarity;
+
+    ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
+    if (ret_val)
+        return ret_val;
+
+    phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & M88E1000_PSSR_MDIX) >>
+                          M88E1000_PSSR_MDIX_SHIFT);
+
+    if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
+        /* Cable Length Estimation and Local/Remote Receiver Information
+         * are only valid at 1000 Mbps.
+         */
+        if (hw->phy_type != e1000_phy_gg82563) {
+            phy_info->cable_length = (e1000_cable_length)((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
+                                      M88E1000_PSSR_CABLE_LENGTH_SHIFT);
+        } else {
+            ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
+                                         &phy_data);
+            if (ret_val)
+                return ret_val;
+
+            phy_info->cable_length = (e1000_cable_length)(phy_data & GG82563_DSPD_CABLE_LENGTH);
+        }
+