compilation warnings cleanup
[people/xl0/gpxe.git] / src / drivers / net / r8169.c
1 /**************************************************************************
2 *    r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit
3 *    Written 2003 by Timothy Legge <tlegge@rogers.com>
4 *
5 *    This program is free software; you can redistribute it and/or modify
6 *    it under the terms of the GNU General Public License as published by
7 *    the Free Software Foundation; either version 2 of the License, or
8 *    (at your option) any later version.
9 *
10 *    This program is distributed in the hope that it will be useful,
11 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
12 *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13 *    GNU General Public License for more details.
14 *
15 *    You should have received a copy of the GNU General Public License
16 *    along with this program; if not, write to the Free Software
17 *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 *
19 *    Portions of this code based on:
20 *       r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver 
21 *               for Linux kernel 2.4.x.
22 *
23 *    Written 2002 ShuChen <shuchen@realtek.com.tw>
24 *         See Linux Driver for full information
25 *       
26 *    Linux Driver Versions: 
27 *       1.27a, 10.02.2002
28 *       RTL8169_VERSION "2.2"   <2004/08/09>
29
30 *    Thanks to:
31 *       Jean Chen of RealTek Semiconductor Corp. for
32 *       providing the evaluation NIC used to develop 
33 *       this driver.  RealTek's support for Etherboot 
34 *       is appreciated.
35 *       
36 *    REVISION HISTORY:
37 *    ================
38 *
39 *    v1.0       11-26-2003      timlegge        Initial port of Linux driver
40 *    v1.5       01-17-2004      timlegge        Initial driver output cleanup
41 *    v1.6       03-27-2004      timlegge        Additional Cleanup
42 *    v1.7       11-22-2005      timlegge        Update to RealTek Driver Version 2.2
43 *    
44 *    Indent Options: indent -kr -i8
45 ***************************************************************************/
46
47 #include "etherboot.h"
48 #include "nic.h"
49 #include <gpxe/pci.h>
50 #include <gpxe/ethernet.h>
51 #include "timer.h"
52
53 #define drv_version "v1.6"
54 #define drv_date "03-27-2004"
55
56 #define HZ 1000
57
58 static u32 ioaddr;
59
60 /* Condensed operations for readability. */
61 #define virt_to_le32desc(addr)  cpu_to_le32(virt_to_bus(addr))
62 #define le32desc_to_virt(addr)  bus_to_virt(le32_to_cpu(addr))
63
64 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
65
66 #undef RTL8169_DEBUG
67 #undef RTL8169_JUMBO_FRAME_SUPPORT
68 #undef RTL8169_HW_FLOW_CONTROL_SUPPORT
69
70
71 #undef RTL8169_IOCTL_SUPPORT
72 #undef RTL8169_DYNAMIC_CONTROL
73 #define RTL8169_USE_IO
74
75
76 #ifdef RTL8169_DEBUG
77 #define assert(expr) \
78                if(!(expr)) { printk( "Assertion failed! %s,%s,%s,line=%d\n", #expr,__FILE__,__FUNCTION__,__LINE__); }
79 #define DBG_PRINTF( fmt, args...)   printk("r8169: " fmt, ## args);
80 #else
81 #define assert(expr) do {} while (0)
82 #define DBG_PRINTF( fmt, args...)   ;
83 #endif                          // end of #ifdef RTL8169_DEBUG
84
85 /* media options 
86         _10_Half = 0x01,
87         _10_Full = 0x02,
88         _100_Half = 0x04,
89         _100_Full = 0x08,
90         _1000_Full = 0x10,
91 */
92 static int media = -1;
93
94 #if 0
95 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
96 static int max_interrupt_work = 20;
97 #endif
98
99 #if 0
100 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
101    The RTL chips use a 64 element hash table based on the Ethernet CRC.  */
102 static int multicast_filter_limit = 32;
103 #endif
104
105 /* MAC address length*/
106 #define MAC_ADDR_LEN    6
107
108 /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/
109 #define MAX_ETH_FRAME_SIZE      1536
110
111 #define TX_FIFO_THRESH 256      /* In bytes */
112
113 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer.  */
114 #define RX_DMA_BURST    7       /* Maximum PCI burst, '6' is 1024 */
115 #define TX_DMA_BURST    7       /* Maximum PCI burst, '6' is 1024 */
116 #define ETTh                0x3F        /* 0x3F means NO threshold */
117
118 #define EarlyTxThld     0x3F    /* 0x3F means NO early transmit */
119 #define RxPacketMaxSize 0x0800  /* Maximum size supported is 16K-1 */
120 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
121
122 #define NUM_TX_DESC     1       /* Number of Tx descriptor registers */
123 #define NUM_RX_DESC     4       /* Number of Rx descriptor registers */
124 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
125
126 #define RTL_MIN_IO_SIZE 0x80
127 #define TX_TIMEOUT  (6*HZ)
128
129 #define RTL8169_TIMER_EXPIRE_TIME 100   //100
130
131 #define ETH_HDR_LEN         14
132 #define DEFAULT_MTU         1500
133 #define DEFAULT_RX_BUF_LEN  1536
134
135
136 #ifdef RTL8169_JUMBO_FRAME_SUPPORT
137 #define MAX_JUMBO_FRAME_MTU    ( 10000 )
138 #define MAX_RX_SKBDATA_SIZE    ( MAX_JUMBO_FRAME_MTU + ETH_HDR_LEN )
139 #else
140 #define MAX_RX_SKBDATA_SIZE 1600
141 #endif                          //end #ifdef RTL8169_JUMBO_FRAME_SUPPORT
142
143 #ifdef RTL8169_USE_IO
144 #define RTL_W8(reg, val8)   outb ((val8), ioaddr + (reg))
145 #define RTL_W16(reg, val16) outw ((val16), ioaddr + (reg))
146 #define RTL_W32(reg, val32) outl ((val32), ioaddr + (reg))
147 #define RTL_R8(reg)         inb (ioaddr + (reg))
148 #define RTL_R16(reg)        inw (ioaddr + (reg))
149 #define RTL_R32(reg)        ((unsigned long) inl (ioaddr + (reg)))
150 #else
151 /* write/read MMIO register */
152 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
153 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
154 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
155 #define RTL_R8(reg)             readb (ioaddr + (reg))
156 #define RTL_R16(reg)            readw (ioaddr + (reg))
157 #define RTL_R32(reg)            ((unsigned long) readl (ioaddr + (reg)))
158 #endif
159
160 #define MCFG_METHOD_1           0x01
161 #define MCFG_METHOD_2           0x02
162 #define MCFG_METHOD_3           0x03
163 #define MCFG_METHOD_4           0x04
164
165 #define PCFG_METHOD_1           0x01    //PHY Reg 0x03 bit0-3 == 0x0000
166 #define PCFG_METHOD_2           0x02    //PHY Reg 0x03 bit0-3 == 0x0001
167 #define PCFG_METHOD_3           0x03    //PHY Reg 0x03 bit0-3 == 0x0002
168
169 static struct {
170         const char *name;
171         u8 mcfg;                /* depend on RTL8169 docs */
172         u32 RxConfigMask;       /* should clear the bits supported by this chip */
173 } rtl_chip_info[] = {
174         {
175         "RTL-8169", MCFG_METHOD_1, 0xff7e1880,}, {
176         "RTL8169s/8110s", MCFG_METHOD_2, 0xff7e1880}, {
177 "RTL8169s/8110s", MCFG_METHOD_3, 0xff7e1880},};
178
179 enum RTL8169_registers {
180         MAC0 = 0x0,             /* Ethernet hardware address. */
181         MAR0 = 0x8,             /* Multicast filter. */
182         TxDescStartAddr = 0x20,
183         TxHDescStartAddr = 0x28,
184         FLASH = 0x30,
185         ERSR = 0x36,
186         ChipCmd = 0x37,
187         TxPoll = 0x38,
188         IntrMask = 0x3C,
189         IntrStatus = 0x3E,
190         TxConfig = 0x40,
191         RxConfig = 0x44,
192         RxMissed = 0x4C,
193         Cfg9346 = 0x50,
194         Config0 = 0x51,
195         Config1 = 0x52,
196         Config2 = 0x53,
197         Config3 = 0x54,
198         Config4 = 0x55,
199         Config5 = 0x56,
200         MultiIntr = 0x5C,
201         PHYAR = 0x60,
202         TBICSR = 0x64,
203         TBI_ANAR = 0x68,
204         TBI_LPAR = 0x6A,
205         PHYstatus = 0x6C,
206         RxMaxSize = 0xDA,
207         CPlusCmd = 0xE0,
208         RxDescStartAddr = 0xE4,
209         ETThReg = 0xEC,
210         FuncEvent = 0xF0,
211         FuncEventMask = 0xF4,
212         FuncPresetState = 0xF8,
213         FuncForceEvent = 0xFC,
214 };
215
216 enum RTL8169_register_content {
217         /*InterruptStatusBits */
218         SYSErr = 0x8000,
219         PCSTimeout = 0x4000,
220         SWInt = 0x0100,
221         TxDescUnavail = 0x80,
222         RxFIFOOver = 0x40,
223         LinkChg = 0x20,
224         RxOverflow = 0x10,
225         TxErr = 0x08,
226         TxOK = 0x04,
227         RxErr = 0x02,
228         RxOK = 0x01,
229
230         /*RxStatusDesc */
231         RxRES = 0x00200000,
232         RxCRC = 0x00080000,
233         RxRUNT = 0x00100000,
234         RxRWT = 0x00400000,
235
236         /*ChipCmdBits */
237         CmdReset = 0x10,
238         CmdRxEnb = 0x08,
239         CmdTxEnb = 0x04,
240         RxBufEmpty = 0x01,
241
242         /*Cfg9346Bits */
243         Cfg9346_Lock = 0x00,
244         Cfg9346_Unlock = 0xC0,
245
246         /*rx_mode_bits */
247         AcceptErr = 0x20,
248         AcceptRunt = 0x10,
249         AcceptBroadcast = 0x08,
250         AcceptMulticast = 0x04,
251         AcceptMyPhys = 0x02,
252         AcceptAllPhys = 0x01,
253
254         /*RxConfigBits */
255         RxCfgFIFOShift = 13,
256         RxCfgDMAShift = 8,
257
258         /*TxConfigBits */
259         TxInterFrameGapShift = 24,
260         TxDMAShift = 8,         /* DMA burst value (0-7) is shift this many bits */
261
262         /*rtl8169_PHYstatus */
263         TBI_Enable = 0x80,
264         TxFlowCtrl = 0x40,
265         RxFlowCtrl = 0x20,
266         _1000bpsF = 0x10,
267         _100bps = 0x08,
268         _10bps = 0x04,
269         LinkStatus = 0x02,
270         FullDup = 0x01,
271
272         /*GIGABIT_PHY_registers */
273         PHY_CTRL_REG = 0,
274         PHY_STAT_REG = 1,
275         PHY_AUTO_NEGO_REG = 4,
276         PHY_1000_CTRL_REG = 9,
277
278         /*GIGABIT_PHY_REG_BIT */
279         PHY_Restart_Auto_Nego = 0x0200,
280         PHY_Enable_Auto_Nego = 0x1000,
281
282         /* PHY_STAT_REG = 1; */
283         PHY_Auto_Neco_Comp = 0x0020,
284
285         /* PHY_AUTO_NEGO_REG = 4; */
286         PHY_Cap_10_Half = 0x0020,
287         PHY_Cap_10_Full = 0x0040,
288         PHY_Cap_100_Half = 0x0080,
289         PHY_Cap_100_Full = 0x0100,
290
291         /* PHY_1000_CTRL_REG = 9; */
292         PHY_Cap_1000_Full = 0x0200,
293         PHY_Cap_1000_Half = 0x0100,
294
295         PHY_Cap_PAUSE = 0x0400,
296         PHY_Cap_ASYM_PAUSE = 0x0800,
297
298         PHY_Cap_Null = 0x0,
299
300         /*_MediaType*/
301         _10_Half = 0x01,
302         _10_Full = 0x02,
303         _100_Half = 0x04,
304         _100_Full = 0x08,
305         _1000_Full = 0x10,
306
307         /*_TBICSRBit*/
308         TBILinkOK = 0x02000000,
309 };
310
311 enum _DescStatusBit {
312         OWNbit = 0x80000000,
313         EORbit = 0x40000000,
314         FSbit = 0x20000000,
315         LSbit = 0x10000000,
316 };
317
318 struct TxDesc {
319         u32 status;
320         u32 vlan_tag;
321         u32 buf_addr;
322         u32 buf_Haddr;
323 };
324
325 struct RxDesc {
326         u32 status;
327         u32 vlan_tag;
328         u32 buf_addr;
329         u32 buf_Haddr;
330 };
331
332 /* The descriptors for this card are required to be aligned on 256
333  * byte boundaries.  As the align attribute does not do more than 16
334  * bytes of alignment it requires some extra steps.  Add 256 to the
335  * size of the array and the init_ring adjusts the alignment.
336  *
337  * UPDATE: This is no longer true; we can request arbitrary alignment.
338  */
339
340 /* Define the TX and RX Descriptors and Buffers */
341 #define __align_256 __attribute__ (( aligned ( 256 ) ))
342 struct {
343         struct TxDesc tx_ring[NUM_TX_DESC] __align_256;
344         unsigned char txb[NUM_TX_DESC * RX_BUF_SIZE];
345         struct RxDesc rx_ring[NUM_RX_DESC] __align_256;
346         unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE];
347 } r8169_bufs __shared;
348 #define tx_ring r8169_bufs.tx_ring
349 #define rx_ring r8169_bufs.rx_ring
350 #define txb r8169_bufs.txb
351 #define rxb r8169_bufs.rxb
352
353 static struct rtl8169_private {
354         void *mmio_addr;        /* memory map physical address */
355         int chipset;
356         int pcfg;
357         int mcfg;
358         unsigned long cur_rx;   /* Index into the Rx descriptor buffer of next Rx pkt. */
359         unsigned long cur_tx;   /* Index into the Tx descriptor buffer of next Rx pkt. */
360         struct TxDesc *TxDescArray;     /* Index of 256-alignment Tx Descriptor buffer */
361         struct RxDesc *RxDescArray;     /* Index of 256-alignment Rx Descriptor buffer */
362         unsigned char *RxBufferRing[NUM_RX_DESC];       /* Index of Rx Buffer array */
363         unsigned char *Tx_skbuff[NUM_TX_DESC];
364 } tpx;
365
366 static struct rtl8169_private *tpc;
367
368 static const u16 rtl8169_intr_mask =
369     LinkChg | RxOverflow | RxFIFOOver | TxErr | TxOK | RxErr | RxOK;
370 static const unsigned int rtl8169_rx_config =
371     (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift) |
372     0x0000000E;
373
374 static void rtl8169_hw_PHY_config(struct nic *nic __unused);
375 //static void rtl8169_hw_PHY_reset(struct net_device *dev);
376
377 #define RTL8169_WRITE_GMII_REG_BIT( ioaddr, reg, bitnum, bitval )\
378 { \
379        int val; \
380        if( bitval == 1 ){ val = ( RTL8169_READ_GMII_REG( ioaddr, reg ) | (bitval<<bitnum) ) & 0xffff ; } \
381        else{ val = ( RTL8169_READ_GMII_REG( ioaddr, reg ) & (~(0x0001<<bitnum)) ) & 0xffff ; } \
382        RTL8169_WRITE_GMII_REG( ioaddr, reg, val ); \
383  }
384
385 //=================================================================
386 //      PHYAR
387 //      bit             Symbol
388 //      31              Flag
389 //      30-21   reserved
390 //      20-16   5-bit GMII/MII register address
391 //      15-0    16-bit GMII/MII register data
392 //=================================================================
393 void RTL8169_WRITE_GMII_REG(unsigned long ioaddr, int RegAddr, int value)
394 {
395         int i;
396
397         RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
398         udelay(1000);
399
400         for (i = 2000; i > 0; i--) {
401                 // Check if the RTL8169 has completed writing to the specified MII register
402                 if (!(RTL_R32(PHYAR) & 0x80000000)) {
403                         break;
404                 } else {
405                         udelay(100);
406                 }               // end of if( ! (RTL_R32(PHYAR)&0x80000000) )
407         }                       // end of for() loop
408 }
409
410 //=================================================================
411 int RTL8169_READ_GMII_REG(unsigned long ioaddr, int RegAddr)
412 {
413         int i, value = -1;
414
415         RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
416         udelay(1000);
417
418         for (i = 2000; i > 0; i--) {
419                 // Check if the RTL8169 has completed retrieving data from the specified MII register
420                 if (RTL_R32(PHYAR) & 0x80000000) {
421                         value = (int) (RTL_R32(PHYAR) & 0xFFFF);
422                         break;
423                 } else {
424                         udelay(100);
425                 }               // end of if( RTL_R32(PHYAR) & 0x80000000 )
426         }                       // end of for() loop
427         return value;
428 }
429
430
431 #if 0
432 static void mdio_write(int RegAddr, int value)
433 {
434         int i;
435
436         RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
437         udelay(1000);
438
439         for (i = 2000; i > 0; i--) {
440                 /* Check if the RTL8169 has completed writing to the specified MII register */
441                 if (!(RTL_R32(PHYAR) & 0x80000000)) {
442                         break;
443                 } else {
444                         udelay(100);
445                 }
446         }
447 }
448
449 static int mdio_read(int RegAddr)
450 {
451         int i, value = -1;
452
453         RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
454         udelay(1000);
455
456         for (i = 2000; i > 0; i--) {
457                 /* Check if the RTL8169 has completed retrieving data from the specified MII register */
458                 if (RTL_R32(PHYAR) & 0x80000000) {
459                         value = (int) (RTL_R32(PHYAR) & 0xFFFF);
460                         break;
461                 } else {
462                         udelay(100);
463                 }
464         }
465         return value;
466 }
467 #endif
468
469 #define IORESOURCE_MEM 0x00000200
470
471 static int rtl8169_init_board(struct pci_device *pdev)
472 {
473         int i;
474 //      unsigned long mmio_end, mmio_flags
475         unsigned long mmio_start, mmio_len;
476
477         adjust_pci_device(pdev);
478
479         mmio_start = pci_bar_start(pdev, PCI_BASE_ADDRESS_1);
480 //       mmio_end = pci_resource_end (pdev, 1);
481 //       mmio_flags = pci_resource_flags (pdev, PCI_BASE_ADDRESS_1);
482         mmio_len = pci_bar_size(pdev, PCI_BASE_ADDRESS_1);
483
484         // make sure PCI base addr 1 is MMIO
485 //     if (!(mmio_flags & IORESOURCE_MEM)) {
486 //             printf ("region #1 not an MMIO resource, aborting\n");
487 //             return 0;
488 //     }
489
490         // check for weird/broken PCI region reporting
491         if (mmio_len < RTL_MIN_IO_SIZE) {
492                 printf("Invalid PCI region size(s), aborting\n");
493                 return 0;
494         }
495 #ifdef RTL8169_USE_IO
496         ioaddr = pci_bar_start(pdev, PCI_BASE_ADDRESS_0);
497 #else
498         // ioremap MMIO region
499         ioaddr = (unsigned long) ioremap(mmio_start, mmio_len);
500         if (ioaddr == 0) {
501                 printk("cannot remap MMIO, aborting\n");
502                 return 0;
503         }
504 #endif
505
506         tpc->mmio_addr = &ioaddr;
507         /* Soft reset the chip. */
508         RTL_W8(ChipCmd, CmdReset);
509
510         /* Check that the chip has finished the reset. */
511         for (i = 1000; i > 0; i--)
512                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
513                         break;
514                 else
515                         udelay(10);
516         // identify config method
517         {
518                 unsigned long val32 = (RTL_R32(TxConfig) & 0x7c800000);
519                 if (val32 == (0x1 << 28)) {
520                         tpc->mcfg = MCFG_METHOD_4;
521                 } else if (val32 == (0x1 << 26)) {
522                         tpc->mcfg = MCFG_METHOD_3;
523                 } else if (val32 == (0x1 << 23)) {
524                         tpc->mcfg = MCFG_METHOD_2;
525                 } else if (val32 == 0x00000000) {
526                         tpc->mcfg = MCFG_METHOD_1;
527                 } else {
528                         tpc->mcfg = MCFG_METHOD_1;
529                 }
530         }
531         {
532                 unsigned char val8 =
533                     (unsigned char) (RTL8169_READ_GMII_REG(ioaddr, 3) &
534                                      0x000f);
535                 if (val8 == 0x00) {
536                         tpc->pcfg = PCFG_METHOD_1;
537                 } else if (val8 == 0x01) {
538                         tpc->pcfg = PCFG_METHOD_2;
539                 } else if (val8 == 0x02) {
540                         tpc->pcfg = PCFG_METHOD_3;
541                 } else {
542                         tpc->pcfg = PCFG_METHOD_3;
543                 }
544         }
545
546         /* identify chip attached to board */
547
548         for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--)
549                 if (tpc->mcfg == rtl_chip_info[i].mcfg) {
550                         tpc->chipset = i;
551                         goto match;
552                 }
553         /* if unknown chip, assume array element #0, original RTL-8169 in this case */
554         DBG ( "PCI device: unknown chip version, assuming RTL-8169\n" );
555         DBG ( "PCI device: TxConfig = %#lX\n", ( unsigned long ) RTL_R32 ( TxConfig ) );
556
557         tpc->chipset = 0;
558         return 1;
559
560       match:
561         return 0;
562
563 }
564
565 /**************************************************************************
566 IRQ - Wait for a frame
567 ***************************************************************************/
568 static void r8169_irq(struct nic *nic __unused, irq_action_t action)
569 {
570         int intr_status = 0;
571         int interested = RxOverflow | RxFIFOOver | RxErr | RxOK;
572
573         switch (action) {
574         case DISABLE:
575         case ENABLE:
576                 intr_status = RTL_R16(IntrStatus);
577                 /* h/w no longer present (hotplug?) or major error, 
578                    bail */
579                 if (intr_status == 0xFFFF)
580                         break;
581                 
582                 intr_status = intr_status & ~interested;
583                 if (action == ENABLE)
584                         intr_status = intr_status | interested;
585                 RTL_W16(IntrMask, intr_status);
586                 break;
587         case FORCE:
588                 RTL_W8(TxPoll, (RTL_R8(TxPoll) | 0x01));
589                 break;
590         }
591 }
592
593 /**************************************************************************
594 POLL - Wait for a frame
595 ***************************************************************************/
596 static int r8169_poll(struct nic *nic, int retreive)
597 {
598         /* return true if there's an ethernet packet ready to read */
599         /* nic->packet should contain data on return */
600         /* nic->packetlen should contain length of data */
601         int cur_rx;
602         unsigned int intr_status = 0;
603         cur_rx = tpc->cur_rx;
604         if ((tpc->RxDescArray[cur_rx].status & OWNbit) == 0) {
605                 /* There is a packet ready */
606                 if (!retreive)
607                         return 1;
608                 intr_status = RTL_R16(IntrStatus);
609                 /* h/w no longer present (hotplug?) or major error,
610                    bail */
611                 if (intr_status == 0xFFFF)
612                         return 0;
613                 RTL_W16(IntrStatus, intr_status &
614                         ~(RxFIFOOver | RxOverflow | RxOK));
615
616                 if (!(tpc->RxDescArray[cur_rx].status & RxRES)) {
617                         nic->packetlen = (int) (tpc->RxDescArray[cur_rx].
618                                                 status & 0x00001FFF) - 4;
619                         memcpy(nic->packet, tpc->RxBufferRing[cur_rx],
620                                nic->packetlen);
621                         if (cur_rx == NUM_RX_DESC - 1)
622                                 tpc->RxDescArray[cur_rx].status =
623                                     (OWNbit | EORbit) + RX_BUF_SIZE;
624                         else
625                                 tpc->RxDescArray[cur_rx].status =
626                                     OWNbit + RX_BUF_SIZE;
627                         tpc->RxDescArray[cur_rx].buf_addr =
628                             virt_to_bus(tpc->RxBufferRing[cur_rx]);
629                 } else
630                         printf("Error Rx");
631                 /* FIXME: shouldn't I reset the status on an error */
632                 cur_rx = (cur_rx + 1) % NUM_RX_DESC;
633                 tpc->cur_rx = cur_rx;
634                 RTL_W16(IntrStatus, intr_status &
635                         (RxFIFOOver | RxOverflow | RxOK));
636
637                 return 1;
638
639         }
640         tpc->cur_rx = cur_rx;
641         /* FIXME: There is no reason to do this as cur_rx did not change */
642
643         return (0);             /* initially as this is called to flush the input */
644
645 }
646
647 /**************************************************************************
648 TRANSMIT - Transmit a frame
649 ***************************************************************************/
650 static void r8169_transmit(struct nic *nic, const char *d,      /* Destination */
651                            unsigned int t,      /* Type */
652                            unsigned int s,      /* size */
653                            const char *p)
654 {                               /* Packet */
655         /* send the packet to destination */
656
657         u16 nstype;
658         u32 to;
659         u8 *ptxb;
660         int entry = tpc->cur_tx % NUM_TX_DESC;
661
662         /* point to the current txb incase multiple tx_rings are used */
663         ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE];
664         memcpy(ptxb, d, ETH_ALEN);
665         memcpy(ptxb + ETH_ALEN, nic->node_addr, ETH_ALEN);
666         nstype = htons((u16) t);
667         memcpy(ptxb + 2 * ETH_ALEN, (u8 *) & nstype, 2);
668         memcpy(ptxb + ETH_HLEN, p, s);
669         s += ETH_HLEN;
670         s &= 0x0FFF;
671         while (s < ETH_ZLEN)
672                 ptxb[s++] = '\0';
673
674         tpc->TxDescArray[entry].buf_addr = virt_to_bus(ptxb);
675         if (entry != (NUM_TX_DESC - 1))
676                 tpc->TxDescArray[entry].status =
677                     (OWNbit | FSbit | LSbit) | ((s > ETH_ZLEN) ? s :
678                                                 ETH_ZLEN);
679         else
680                 tpc->TxDescArray[entry].status =
681                     (OWNbit | EORbit | FSbit | LSbit) | ((s > ETH_ZLEN) ? s
682                                                          : ETH_ZLEN);
683         RTL_W8(TxPoll, 0x40);   /* set polling bit */
684
685         tpc->cur_tx++;
686         to = currticks() + TX_TIMEOUT;
687         while ((tpc->TxDescArray[entry].status & OWNbit) && (currticks() < to));        /* wait */
688
689         if (currticks() >= to) {
690                 printf("TX Time Out");
691         }
692 }
693
694 static void rtl8169_set_rx_mode(struct nic *nic __unused)
695 {
696         u32 mc_filter[2];       /* Multicast hash filter */
697         int rx_mode;
698         u32 tmp = 0;
699
700         /* IFF_ALLMULTI */
701         /* Too many to filter perfectly -- accept all multicasts. */
702         rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
703         mc_filter[1] = mc_filter[0] = 0xffffffff;
704
705         tmp =
706             rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) &
707                                            rtl_chip_info[tpc->chipset].
708                                            RxConfigMask);
709
710         RTL_W32(RxConfig, tmp);
711         RTL_W32(MAR0 + 0, mc_filter[0]);
712         RTL_W32(MAR0 + 4, mc_filter[1]);
713 }
714 static void rtl8169_hw_start(struct nic *nic)
715 {
716         u32 i;
717
718         /* Soft reset the chip. */
719         RTL_W8(ChipCmd, CmdReset);
720
721         /* Check that the chip has finished the reset. */
722         for (i = 1000; i > 0; i--) {
723                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
724                         break;
725                 else
726                         udelay(10);
727         }
728
729         RTL_W8(Cfg9346, Cfg9346_Unlock);
730         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
731         RTL_W8(ETThReg, ETTh);
732
733         /* For gigabit rtl8169 */
734         RTL_W16(RxMaxSize, RxPacketMaxSize);
735
736         /* Set Rx Config register */
737         i = rtl8169_rx_config | (RTL_R32(RxConfig) &
738                                  rtl_chip_info[tpc->chipset].RxConfigMask);
739         RTL_W32(RxConfig, i);
740
741         /* Set DMA burst size and Interframe Gap Time */
742         RTL_W32(TxConfig,
743                 (TX_DMA_BURST << TxDMAShift) | (InterFrameGap <<
744                                                 TxInterFrameGapShift));
745
746
747         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd));
748
749         if (tpc->mcfg == MCFG_METHOD_2 || tpc->mcfg == MCFG_METHOD_3) {
750                 RTL_W16(CPlusCmd,
751                         (RTL_R16(CPlusCmd) | (1 << 14) | (1 << 3)));
752                 DBG_PRINTF
753                     ("Set MAC Reg C+CR Offset 0xE0: bit-3 and bit-14\n");
754         } else {
755                 RTL_W16(CPlusCmd, (RTL_R16(CPlusCmd) | (1 << 3)));
756                 DBG_PRINTF("Set MAC Reg C+CR Offset 0xE0: bit-3.\n");
757         }
758
759         {
760                 //RTL_W16(0xE2, 0x1517);
761                 //RTL_W16(0xE2, 0x152a);
762                 //RTL_W16(0xE2, 0x282a);
763                 RTL_W16(0xE2, 0x0000);
764         }
765
766
767
768         tpc->cur_rx = 0;
769
770         RTL_W32(TxDescStartAddr, virt_to_le32desc(tpc->TxDescArray));
771         RTL_W32(RxDescStartAddr, virt_to_le32desc(tpc->RxDescArray));
772         RTL_W8(Cfg9346, Cfg9346_Lock);
773         udelay(10);
774
775         RTL_W32(RxMissed, 0);
776
777         rtl8169_set_rx_mode(nic);
778
779         /* no early-rx interrupts */
780         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
781
782         RTL_W16(IntrMask, rtl8169_intr_mask);
783
784 }
785
786 static void rtl8169_init_ring(struct nic *nic __unused)
787 {
788         int i;
789
790         tpc->cur_rx = 0;
791         tpc->cur_tx = 0;
792         memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc));
793         memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc));
794
795         for (i = 0; i < NUM_TX_DESC; i++) {
796                 tpc->Tx_skbuff[i] = &txb[i];
797         }
798
799         for (i = 0; i < NUM_RX_DESC; i++) {
800                 if (i == (NUM_RX_DESC - 1))
801                         tpc->RxDescArray[i].status =
802                             (OWNbit | EORbit) | RX_BUF_SIZE;
803                 else
804                         tpc->RxDescArray[i].status = OWNbit | RX_BUF_SIZE;
805
806                 tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE];
807                 tpc->RxDescArray[i].buf_addr =
808                     virt_to_bus(tpc->RxBufferRing[i]);
809         }
810 }
811
812 /**************************************************************************
813 RESET - Finish setting up the ethernet interface
814 ***************************************************************************/
815 static void r8169_reset(struct nic *nic)
816 {
817         int i;
818
819         tpc->TxDescArray = tx_ring;
820         tpc->RxDescArray = rx_ring;
821
822         rtl8169_init_ring(nic);
823         rtl8169_hw_start(nic);
824         /* Construct a perfect filter frame with the mac address as first match
825          * and broadcast for all others */
826         for (i = 0; i < 192; i++)
827                 txb[i] = 0xFF;
828
829         txb[0] = nic->node_addr[0];
830         txb[1] = nic->node_addr[1];
831         txb[2] = nic->node_addr[2];
832         txb[3] = nic->node_addr[3];
833         txb[4] = nic->node_addr[4];
834         txb[5] = nic->node_addr[5];
835 }
836
837 /**************************************************************************
838 DISABLE - Turn off ethernet interface
839 ***************************************************************************/
840 static void r8169_disable ( struct nic *nic __unused ) {
841         int i;
842         /* Stop the chip's Tx and Rx DMA processes. */
843         RTL_W8(ChipCmd, 0x00);
844
845         /* Disable interrupts by clearing the interrupt mask. */
846         RTL_W16(IntrMask, 0x0000);
847
848         RTL_W32(RxMissed, 0);
849
850         tpc->TxDescArray = NULL;
851         tpc->RxDescArray = NULL;
852         for (i = 0; i < NUM_RX_DESC; i++) {
853                 tpc->RxBufferRing[i] = NULL;
854         }
855 }
856
857 static struct nic_operations r8169_operations = {
858         .connect        = dummy_connect,
859         .poll           = r8169_poll,
860         .transmit       = r8169_transmit,
861         .irq            = r8169_irq,
862
863 };
864
865 static struct pci_device_id r8169_nics[] = {
866         PCI_ROM(0x10ec, 0x8169, "r8169", "RealTek RTL8169 Gigabit Ethernet"),
867         PCI_ROM(0x16ec, 0x0116, "usr-r8169", "US Robotics RTL8169 Gigabit Ethernet"),
868         PCI_ROM(0x1186, 0x4300, "dlink-r8169", "D-Link RTL8169 Gigabit Ethernet"),
869 };
870
871 PCI_DRIVER ( r8169_driver, r8169_nics, PCI_NO_CLASS );
872
873 /**************************************************************************
874 PROBE - Look for an adapter, this routine's visible to the outside
875 ***************************************************************************/
876
877 #define board_found 1
878 #define valid_link 0
879 static int r8169_probe ( struct nic *nic, struct pci_device *pci ) {
880
881         static int board_idx = -1;
882         static int printed_version = 0;
883         int i, rc;
884         int option = -1, Cap10_100 = 0, Cap1000 = 0;
885
886         printf ( "r8169.c: Found %s, Vendor=%hX Device=%hX\n",
887                pci->name, pci->vendor, pci->device );
888
889         board_idx++;
890
891         printed_version = 1;
892
893         /* point to private storage */
894         tpc = &tpx;
895
896         rc = rtl8169_init_board(pci);   /* Return code is meaningless */
897
898         /* Get MAC address.  FIXME: read EEPROM */
899         for (i = 0; i < MAC_ADDR_LEN; i++)
900                 nic->node_addr[i] = RTL_R8(MAC0 + i);
901
902         DBG ( "%s: Identified chip type is '%s'.\n", pci->name,
903                  rtl_chip_info[tpc->chipset].name );
904
905         /* Print out some hardware info */
906         DBG ( "%s: %s at IOAddr %#hX, ", pci->name, eth_ntoa ( nic->node_addr ),
907                ioaddr );
908
909         /* Config PHY */
910         rtl8169_hw_PHY_config(nic);
911
912         DBG_PRINTF("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
913         RTL_W8(0x82, 0x01);
914
915         if (tpc->mcfg < MCFG_METHOD_3) {
916                 DBG_PRINTF("Set PCI Latency=0x40\n");
917                 pci_write_config_byte(pci, PCI_LATENCY_TIMER, 0x40);
918         }
919
920         if (tpc->mcfg == MCFG_METHOD_2) {
921                 DBG_PRINTF("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
922                 RTL_W8(0x82, 0x01);
923                 DBG_PRINTF("Set PHY Reg 0x0bh = 0x00h\n");
924                 RTL8169_WRITE_GMII_REG(ioaddr, 0x0b, 0x0000);   //w 0x0b 15 0 0
925         }
926
927         /* if TBI is not endbled */
928         if (!(RTL_R8(PHYstatus) & TBI_Enable)) {
929                 int val = RTL8169_READ_GMII_REG(ioaddr, PHY_AUTO_NEGO_REG);
930
931 #ifdef RTL8169_HW_FLOW_CONTROL_SUPPORT
932                 val |= PHY_Cap_PAUSE | PHY_Cap_ASYM_PAUSE;
933 #endif                          //end #define RTL8169_HW_FLOW_CONTROL_SUPPORT
934
935                 option = media;
936                 /* Force RTL8169 in 10/100/1000 Full/Half mode. */
937                 if (option > 0) {
938                         printf(" Force-mode Enabled.\n");
939                         Cap10_100 = 0, Cap1000 = 0;
940                         switch (option) {
941                         case _10_Half:
942                                 Cap10_100 = PHY_Cap_10_Half;
943                                 Cap1000 = PHY_Cap_Null;
944                                 break;
945                         case _10_Full:
946                                 Cap10_100 = PHY_Cap_10_Full;
947                                 Cap1000 = PHY_Cap_Null;
948                                 break;
949                         case _100_Half:
950                                 Cap10_100 = PHY_Cap_100_Half;
951                                 Cap1000 = PHY_Cap_Null;
952                                 break;
953                         case _100_Full:
954                                 Cap10_100 = PHY_Cap_100_Full;
955                                 Cap1000 = PHY_Cap_Null;
956                                 break;
957                         case _1000_Full:
958                                 Cap10_100 = PHY_Cap_Null;
959                                 Cap1000 = PHY_Cap_1000_Full;
960                                 break;
961                         default:
962                                 break;
963                         }
964                         RTL8169_WRITE_GMII_REG(ioaddr, PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0xC1F));   //leave PHY_AUTO_NEGO_REG bit4:0 unchanged
965                         RTL8169_WRITE_GMII_REG(ioaddr, PHY_1000_CTRL_REG,
966                                                Cap1000);
967                 } else {
968                         DBG ( "%s: Auto-negotiation Enabled.\n",  pci->name );
969
970                         // enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged
971                         RTL8169_WRITE_GMII_REG(ioaddr, PHY_AUTO_NEGO_REG,
972                                                PHY_Cap_10_Half |
973                                                PHY_Cap_10_Full |
974                                                PHY_Cap_100_Half |
975                                                PHY_Cap_100_Full | (val &
976                                                                    0xC1F));
977
978                         // enable 1000 Full Mode
979 //                     RTL8169_WRITE_GMII_REG( ioaddr, PHY_1000_CTRL_REG, PHY_Cap_1000_Full );
980                         RTL8169_WRITE_GMII_REG(ioaddr, PHY_1000_CTRL_REG, PHY_Cap_1000_Full | PHY_Cap_1000_Half);       //rtl8168
981
982                 }               // end of if( option > 0 )
983
984                 // Enable auto-negotiation and restart auto-nigotiation
985                 RTL8169_WRITE_GMII_REG(ioaddr, PHY_CTRL_REG,
986                                        PHY_Enable_Auto_Nego |
987                                        PHY_Restart_Auto_Nego);
988                 udelay(100);
989
990                 // wait for auto-negotiation process
991                 for (i = 10000; i > 0; i--) {
992                         //check if auto-negotiation complete
993                         if (RTL8169_READ_GMII_REG(ioaddr, PHY_STAT_REG) &
994                             PHY_Auto_Neco_Comp) {
995                                 udelay(100);
996                                 option = RTL_R8(PHYstatus);
997                                 if (option & _1000bpsF) {
998                                         printf
999                                             ("1000Mbps Full-duplex operation.\n");
1000                                 } else {
1001                                         printf
1002                                             ("%sMbps %s-duplex operation.\n",
1003                                              (option & _100bps) ? "100" :
1004                                              "10",
1005                                              (option & FullDup) ? "Full" :
1006                                              "Half");
1007                                 }
1008                                 break;
1009                         } else {
1010                                 udelay(100);
1011                         }       // end of if( RTL8169_READ_GMII_REG(ioaddr, 1) & 0x20 )
1012                 }               // end for-loop to wait for auto-negotiation process
1013
1014
1015         } else {
1016                 udelay(100);
1017                 printf
1018                     ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n",
1019                      pci->name,
1020                      (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed");
1021
1022         }
1023
1024         r8169_reset(nic);
1025         /* point to NIC specific routines */
1026         nic->nic_op     = &r8169_operations;
1027         pci_fill_nic ( nic, pci );
1028         nic->irqno = pci->irq;
1029         nic->ioaddr = ioaddr;
1030         return 1;
1031
1032 }
1033
1034 //======================================================================================================
1035 /*
1036 static void rtl8169_hw_PHY_reset(struct nic *nic __unused)
1037 {
1038         int val, phy_reset_expiretime = 50;
1039         struct rtl8169_private *priv = dev->priv;
1040         unsigned long ioaddr = priv->ioaddr;
1041
1042         DBG_PRINTF("%s: Reset RTL8169s PHY\n", dev->name);
1043
1044         val = ( RTL8169_READ_GMII_REG( ioaddr, 0 ) | 0x8000 ) & 0xffff;
1045         RTL8169_WRITE_GMII_REG( ioaddr, 0, val );
1046
1047         do //waiting for phy reset
1048         {
1049                 if( RTL8169_READ_GMII_REG( ioaddr, 0 ) & 0x8000 ){
1050                         phy_reset_expiretime --;
1051                         udelay(100);
1052                 }
1053                 else{
1054                         break;
1055                 }
1056         }while( phy_reset_expiretime >= 0 );
1057
1058         assert( phy_reset_expiretime > 0 );
1059 }
1060
1061 */
1062
1063 //======================================================================================================
1064 static void rtl8169_hw_PHY_config(struct nic *nic __unused)
1065 {
1066
1067         DBG_PRINTF("priv->mcfg=%d, priv->pcfg=%d\n", tpc->mcfg, tpc->pcfg);
1068
1069         if (tpc->mcfg == MCFG_METHOD_4) {
1070 /*
1071                 RTL8169_WRITE_GMII_REG( (unsigned long)ioaddr, 0x1F, 0x0001 );
1072                 RTL8169_WRITE_GMII_REG( (unsigned long)ioaddr, 0x1b, 0x841e );
1073                 RTL8169_WRITE_GMII_REG( (unsigned long)ioaddr, 0x0e, 0x7bfb );
1074                 RTL8169_WRITE_GMII_REG( (unsigned long)ioaddr, 0x09, 0x273a );
1075 */
1076
1077                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x1F,
1078                                        0x0002);
1079                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x01,
1080                                        0x90D0);
1081                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x1F,
1082                                        0x0000);
1083         } else if ((tpc->mcfg == MCFG_METHOD_2)
1084                    || (tpc->mcfg == MCFG_METHOD_3)) {
1085                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x1F,
1086                                        0x0001);
1087                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x15,
1088                                        0x1000);
1089                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x18,
1090                                        0x65C7);
1091                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1092                                        0x0000);
1093                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x03,
1094                                        0x00A1);
1095                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x02,
1096                                        0x0008);
1097                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x01,
1098                                        0x1020);
1099                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x00,
1100                                        0x1000);
1101                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1102                                        0x0800);
1103                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1104                                        0x0000);
1105                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1106                                        0x7000);
1107                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x03,
1108                                        0xFF41);
1109                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x02,
1110                                        0xDE60);
1111                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x01,
1112                                        0x0140);
1113                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x00,
1114                                        0x0077);
1115                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1116                                        0x7800);
1117                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1118                                        0x7000);
1119                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1120                                        0xA000);
1121                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x03,
1122                                        0xDF01);
1123                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x02,
1124                                        0xDF20);
1125                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x01,
1126                                        0xFF95);
1127                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x00,
1128                                        0xFA00);
1129                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1130                                        0xA800);
1131                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1132                                        0xA000);
1133                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1134                                        0xB000);
1135                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x03,
1136                                        0xFF41);
1137                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x02,
1138                                        0xDE20);
1139                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x01,
1140                                        0x0140);
1141                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x00,
1142                                        0x00BB);
1143                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1144                                        0xB800);
1145                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1146                                        0xB000);
1147                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1148                                        0xF000);
1149                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x03,
1150                                        0xDF01);
1151                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x02,
1152                                        0xDF20);
1153                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x01,
1154                                        0xFF95);
1155                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x00,
1156                                        0xBF00);
1157                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1158                                        0xF800);
1159                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1160                                        0xF000);
1161                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1162                                        0x0000);
1163                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x1F,
1164                                        0x0000);
1165                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x0B,
1166                                        0x0000);
1167         } else {
1168                 DBG_PRINTF("tpc->mcfg=%d. Discard hw PHY config.\n",
1169                           tpc->mcfg);
1170         }
1171 }
1172
1173 DRIVER ( "r8169/PCI", nic_driver, pci_driver, r8169_driver,
1174          r8169_probe, r8169_disable );