5 #include <gpxe/blockdev.h>
6 #include <gpxe/uaccess.h>
14 struct async_operation;
17 * An ATA Logical Block Address
19 * ATA controllers have three byte-wide registers for specifying the
20 * block address: LBA Low, LBA Mid and LBA High. This allows for a
21 * 24-bit address. Some devices support the "48-bit address feature
22 * set" (LBA48), in which case each of these byte-wide registers is
23 * actually a two-entry FIFO, and the "previous" byte pushed into the
24 * FIFO is used as the corresponding high-order byte. So, to set up
25 * the 48-bit address 0x123456abcdef, you would issue
27 * 0x56 -> LBA Low register
28 * 0xef -> LBA Low register
29 * 0x34 -> LBA Mid register
30 * 0xcd -> LBA Mid register
31 * 0x12 -> LBA High register
32 * 0xab -> LBA High register
34 * This structure encapsulates this information by providing a single
35 * 64-bit integer in native byte order, unioned with bytes named so
36 * that the sequence becomes
38 * low_prev -> LBA Low register
39 * low_cur -> LBA Low register
40 * mid_prev -> LBA Mid register
41 * mid_cur -> LBA Mid register
42 * high_prev -> LBA High register
43 * high_cur -> LBA High register
45 * Just to complicate matters further, in non-LBA48 mode it is
46 * possible to have a 28-bit address, in which case bits 27:24 must be
47 * written into the low four bits of the Device register.
50 /** LBA as a 64-bit integer in native-endian order */
54 #if __BYTE_ORDER == __LITTLE_ENDIAN
62 #elif __BYTE_ORDER == __BIG_ENDIAN
71 #error "I need a byte order"
76 /** An ATA 2-byte FIFO register */
78 /** Value in native-endian order */
82 #if __BYTE_ORDER == __LITTLE_ENDIAN
85 #elif __BYTE_ORDER == __BIG_ENDIAN
89 #error "I need a byte order"
94 /** ATA command block */
96 /** Logical block address */
100 /** Error/feature register */
101 union ata_fifo err_feat;
102 /** Device register */
104 /** Command/status register */
106 /** LBA48 addressing flag */
110 /** Obsolete bits in the ATA device register */
111 #define ATA_DEV_OBSOLETE 0xa0
113 /** LBA flag in the ATA device register */
114 #define ATA_DEV_LBA 0x40
116 /** Slave ("device 1") flag in the ATA device register */
117 #define ATA_DEV_SLAVE 0x10
119 /** Master ("device 0") flag in the ATA device register */
120 #define ATA_DEV_MASTER 0x00
122 /** Mask of non-LBA portion of device register */
123 #define ATA_DEV_MASK 0xf0
125 /** "Read sectors" command */
126 #define ATA_CMD_READ 0x20
128 /** "Read sectors (ext)" command */
129 #define ATA_CMD_READ_EXT 0x24
131 /** "Write sectors" command */
132 #define ATA_CMD_WRITE 0x30
134 /** "Write sectors (ext)" command */
135 #define ATA_CMD_WRITE_EXT 0x34
137 /** "Identify" command */
138 #define ATA_CMD_IDENTIFY 0xec
140 /** An ATA command */
142 /** ATA command block */
144 /** Data-out buffer (may be NULL)
146 * If non-NULL, this buffer must be ata_command::cb::count
150 /** Data-in buffer (may be NULL)
152 * If non-NULL, this buffer must be ata_command::cb::count
159 * Structure returned by ATA IDENTIFY command
161 * This is a huge structure with many fields that we don't care about,
162 * so we implement only a few fields.
164 struct ata_identity {
165 uint16_t ignore_a[60]; /* words 0-59 */
166 uint32_t lba_sectors; /* words 60-61 */
167 uint16_t ignore_b[21]; /* words 62-82 */
168 uint16_t supports_lba48; /* word 83 */
169 uint16_t ignore_c[16]; /* words 84-99 */
170 uint64_t lba48_sectors; /* words 100-103 */
171 uint16_t ignore_d[152]; /* words 104-255 */
174 /** Supports LBA48 flag */
175 #define ATA_SUPPORTS_LBA48 ( 1 << 10 )
177 /** ATA sector size */
178 #define ATA_SECTOR_SIZE 512
182 /** Block device interface */
183 struct block_device blockdev;
186 * Must be ATA_DEV_MASTER or ATA_DEV_SLAVE.
189 /** LBA48 extended addressing */
195 * @v command ATA command
196 * @ret aop Asynchronous operation
198 struct async_operation * ( * command ) ( struct ata_device *ata,
199 struct ata_command *command );
202 extern int init_atadev ( struct ata_device *ata );
204 #endif /* _GPXE_ATA_H */