compilation warnings cleanup
[people/xl0/gpxe.git] / src / drivers / net / tlan.c
1 /**************************************************************************
2 *
3 *    tlan.c -- Etherboot device driver for the Texas Instruments ThunderLAN
4 *    Written 2003-2003 by Timothy Legge <tlegge@rogers.com>
5 *
6 *    This program is free software; you can redistribute it and/or modify
7 *    it under the terms of the GNU General Public License as published by
8 *    the Free Software Foundation; either version 2 of the License, or
9 *    (at your option) any later version.
10 *
11 *    This program is distributed in the hope that it will be useful,
12 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
13 *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14 *    GNU General Public License for more details.
15 *
16 *    You should have received a copy of the GNU General Public License
17 *    along with this program; if not, write to the Free Software
18 *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 *
20 *    Portions of this code based on:
21 *       lan.c: Linux ThunderLan Driver:
22 *
23 *       by James Banks
24 *
25 *       (C) 1997-1998 Caldera, Inc.
26 *       (C) 1998 James Banks
27 *       (C) 1999-2001 Torben Mathiasen
28 *       (C) 2002 Samuel Chessman
29 *
30 *    REVISION HISTORY:
31 *    ================
32 *    v1.0       07-08-2003      timlegge        Initial not quite working version
33 *    v1.1       07-27-2003      timlegge        Sync 5.0 and 5.1 versions
34 *    v1.2       08-19-2003      timlegge        Implement Multicast Support
35 *    v1.3       08-23-2003      timlegge        Fix the transmit Function
36 *    v1.4       01-17-2004      timlegge        Initial driver output cleanup    
37 *    
38 *    Indent Options: indent -kr -i8
39 ***************************************************************************/
40
41 /* to get some global routines like printf */
42 #include "etherboot.h"
43 /* to get the interface to the body of the program */
44 #include "nic.h"
45 /* to get the PCI support functions, if this is a PCI NIC */
46 #include <gpxe/pci.h>
47 #include "timer.h"
48 #include "tlan.h"
49
50 #define drv_version "v1.4"
51 #define drv_date "01-17-2004"
52
53 /* NIC specific static variables go here */
54 #define HZ 100
55 #define TX_TIME_OUT       (6*HZ)
56
57 /* Condensed operations for readability. */
58 #define virt_to_le32desc(addr)  cpu_to_le32(virt_to_bus(addr))
59 #define le32desc_to_virt(addr)  bus_to_virt(le32_to_cpu(addr))
60
61 //#define EDEBUG
62 #ifdef EDEBUG
63 #define dprintf(x) printf x
64 #else
65 #define dprintf(x)
66 #endif
67
68 static void TLan_ResetLists(struct nic *nic __unused);
69 static void TLan_ResetAdapter(struct nic *nic __unused);
70 static void TLan_FinishReset(struct nic *nic __unused);
71
72 static void TLan_EeSendStart(u16);
73 static int TLan_EeSendByte(u16, u8, int);
74 static void TLan_EeReceiveByte(u16, u8 *, int);
75 static int TLan_EeReadByte(u16 io_base, u8, u8 *);
76
77 static void TLan_PhyDetect(struct nic *nic);
78 static void TLan_PhyPowerDown(struct nic *nic);
79 static void TLan_PhyPowerUp(struct nic *nic);
80
81
82 static void TLan_SetMac(struct nic *nic __unused, int areg, char *mac);
83
84 static void TLan_PhyReset(struct nic *nic);
85 static void TLan_PhyStartLink(struct nic *nic);
86 static void TLan_PhyFinishAutoNeg(struct nic *nic);
87
88 #ifdef MONITOR
89 static void TLan_PhyMonitor(struct nic *nic);
90 #endif
91
92
93 static void refill_rx(struct nic *nic __unused);
94
95 static int TLan_MiiReadReg(struct nic *nic __unused, u16, u16, u16 *);
96 static void TLan_MiiSendData(u16, u32, unsigned);
97 static void TLan_MiiSync(u16);
98 static void TLan_MiiWriteReg(struct nic *nic __unused, u16, u16, u16);
99
100
101 static const char *media[] = {
102         "10BaseT-HD ", "10BaseT-FD ", "100baseTx-HD ",
103         "100baseTx-FD", "100baseT4", 0
104 };
105
106 /* This much match tlan_pci_tbl[]!  */
107 enum tlan_nics {
108         NETEL10 = 0, NETEL100 = 1, NETFLEX3I = 2, THUNDER = 3, NETFLEX3B =
109             4, NETEL100PI = 5,
110         NETEL100D = 6, NETEL100I = 7, OC2183 = 8, OC2325 = 9, OC2326 =
111             10, NETELLIGENT_10_100_WS_5100 = 11,
112         NETELLIGENT_10_T2 = 12
113 };
114
115 struct pci_id_info {
116         const char *name;
117         int nic_id;
118         struct match_info {
119                 u32 pci, pci_mask, subsystem, subsystem_mask;
120                 u32 revision, revision_mask;    /* Only 8 bits. */
121         } id;
122         u32 flags;
123         u16 addrOfs;            /* Address Offset */
124 };
125
126 static const struct pci_id_info tlan_pci_tbl[] = {
127         {"Compaq Netelligent 10 T PCI UTP", NETEL10,
128          {0xae340e11, 0xffffffff, 0, 0, 0, 0},
129          TLAN_ADAPTER_ACTIVITY_LED, 0x83},
130         {"Compaq Netelligent 10/100 TX PCI UTP", NETEL100,
131          {0xae320e11, 0xffffffff, 0, 0, 0, 0},
132          TLAN_ADAPTER_ACTIVITY_LED, 0x83},
133         {"Compaq Integrated NetFlex-3/P", NETFLEX3I,
134          {0xae350e11, 0xffffffff, 0, 0, 0, 0},
135          TLAN_ADAPTER_NONE, 0x83},
136         {"Compaq NetFlex-3/P", THUNDER,
137          {0xf1300e11, 0xffffffff, 0, 0, 0, 0},
138          TLAN_ADAPTER_UNMANAGED_PHY | TLAN_ADAPTER_BIT_RATE_PHY, 0x83},
139         {"Compaq NetFlex-3/P", NETFLEX3B,
140          {0xf1500e11, 0xffffffff, 0, 0, 0, 0},
141          TLAN_ADAPTER_NONE, 0x83},
142         {"Compaq Netelligent Integrated 10/100 TX UTP", NETEL100PI,
143          {0xae430e11, 0xffffffff, 0, 0, 0, 0},
144          TLAN_ADAPTER_ACTIVITY_LED, 0x83},
145         {"Compaq Netelligent Dual 10/100 TX PCI UTP", NETEL100D,
146          {0xae400e11, 0xffffffff, 0, 0, 0, 0},
147          TLAN_ADAPTER_NONE, 0x83},
148         {"Compaq Netelligent 10/100 TX Embedded UTP", NETEL100I,
149          {0xb0110e11, 0xffffffff, 0, 0, 0, 0},
150          TLAN_ADAPTER_NONE, 0x83},
151         {"Olicom OC-2183/2185", OC2183,
152          {0x0013108d, 0xffffffff, 0, 0, 0, 0},
153          TLAN_ADAPTER_USE_INTERN_10, 0x83},
154         {"Olicom OC-2325", OC2325,
155          {0x0012108d, 0xffffffff, 0, 0, 0, 0},
156          TLAN_ADAPTER_UNMANAGED_PHY, 0xF8},
157         {"Olicom OC-2326", OC2326,
158          {0x0014108d, 0xffffffff, 0, 0, 0, 0},
159          TLAN_ADAPTER_USE_INTERN_10, 0xF8},
160         {"Compaq Netelligent 10/100 TX UTP", NETELLIGENT_10_100_WS_5100,
161          {0xb0300e11, 0xffffffff, 0, 0, 0, 0},
162          TLAN_ADAPTER_ACTIVITY_LED, 0x83},
163         {"Compaq Netelligent 10 T/2 PCI UTP/Coax", NETELLIGENT_10_T2,
164          {0xb0120e11, 0xffffffff, 0, 0, 0, 0},
165          TLAN_ADAPTER_NONE, 0x83},
166         {"Compaq NetFlex-3/E", 0,       /* EISA card */
167          {0, 0, 0, 0, 0, 0},
168          TLAN_ADAPTER_ACTIVITY_LED | TLAN_ADAPTER_UNMANAGED_PHY |
169          TLAN_ADAPTER_BIT_RATE_PHY, 0x83},
170         {"Compaq NetFlex-3/E", 0,       /* EISA card */
171          {0, 0, 0, 0, 0, 0},
172          TLAN_ADAPTER_ACTIVITY_LED, 0x83},
173         {0, 0,
174          {0, 0, 0, 0, 0, 0},
175          0, 0},
176 };
177
178 struct TLanList {
179         u32 forward;
180         u16 cStat;
181         u16 frameSize;
182         struct {
183                 u32 count;
184                 u32 address;
185         } buffer[TLAN_BUFFERS_PER_LIST];
186 };
187
188 struct {
189         struct TLanList tx_ring[TLAN_NUM_TX_LISTS];
190         unsigned char txb[TLAN_MAX_FRAME_SIZE * TLAN_NUM_TX_LISTS];
191         struct TLanList rx_ring[TLAN_NUM_RX_LISTS];
192         unsigned char rxb[TLAN_MAX_FRAME_SIZE * TLAN_NUM_RX_LISTS];
193 } tlan_buffers __shared;
194 #define tx_ring tlan_buffers.tx_ring
195 #define txb tlan_buffers.txb
196 #define rx_ring tlan_buffers.rx_ring
197 #define rxb tlan_buffers.rxb
198
199 typedef u8 TLanBuffer[TLAN_MAX_FRAME_SIZE];
200
201 static int chip_idx;
202
203 /*****************************************************************
204 * TLAN Private Information Structure
205 *
206 ****************************************************************/
207 static struct tlan_private {
208         unsigned short vendor_id;       /* PCI Vendor code */
209         unsigned short dev_id;  /* PCI Device code */
210         const char *nic_name;
211         unsigned int cur_rx, dirty_rx;  /* Producer/consumer ring indicies */
212         unsigned rx_buf_sz;     /* Based on mtu + Slack */
213         struct TLanList *txList;
214         u32 txHead;
215         u32 txInProgress;
216         u32 txTail;
217         int eoc;
218         u32 phyOnline;
219         u32 aui;
220         u32 duplex;
221         u32 phy[2];
222         u32 phyNum;
223         u32 speed;
224         u8 tlanRev;
225         u8 tlanFullDuplex;
226         u8 link;
227         u8 neg_be_verbose;
228 } TLanPrivateInfo;
229
230 static struct tlan_private *priv;
231
232 static u32 BASE;
233
234 /***************************************************************
235 *       TLan_ResetLists
236 *
237 *       Returns:
238 *               Nothing
239 *       Parms:
240 *               dev     The device structure with the list
241 *                       stuctures to be reset.
242 *
243 *       This routine sets the variables associated with managing
244 *       the TLAN lists to their initial values.
245 *
246 **************************************************************/
247
248 static void TLan_ResetLists(struct nic *nic __unused)
249 {
250
251         int i;
252         struct TLanList *list;
253         priv->txHead = 0;
254         priv->txTail = 0;
255
256         for (i = 0; i < TLAN_NUM_TX_LISTS; i++) {
257                 list = &tx_ring[i];
258                 list->cStat = TLAN_CSTAT_UNUSED;
259                 list->buffer[0].address = virt_to_bus(txb + 
260                                 (i * TLAN_MAX_FRAME_SIZE)); 
261                 list->buffer[2].count = 0;
262                 list->buffer[2].address = 0;
263                 list->buffer[9].address = 0;
264         }
265
266         priv->cur_rx = 0;
267         priv->rx_buf_sz = (TLAN_MAX_FRAME_SIZE);
268 //      priv->rx_head_desc = &rx_ring[0];
269
270         /* Initialize all the Rx descriptors */
271         for (i = 0; i < TLAN_NUM_RX_LISTS; i++) {
272                 rx_ring[i].forward = virt_to_le32desc(&rx_ring[i + 1]);
273                 rx_ring[i].cStat = TLAN_CSTAT_READY;
274                 rx_ring[i].frameSize = TLAN_MAX_FRAME_SIZE;
275                 rx_ring[i].buffer[0].count =
276                     TLAN_MAX_FRAME_SIZE | TLAN_LAST_BUFFER;
277                 rx_ring[i].buffer[0].address =
278                     virt_to_le32desc(&rxb[i * TLAN_MAX_FRAME_SIZE]);
279                 rx_ring[i].buffer[1].count = 0;
280                 rx_ring[i].buffer[1].address = 0;
281         }
282
283         /* Mark the last entry as wrapping the ring */
284         rx_ring[i - 1].forward = virt_to_le32desc(&rx_ring[0]);
285         priv->dirty_rx = (unsigned int) (i - TLAN_NUM_RX_LISTS);
286
287 } /* TLan_ResetLists */
288
289 /***************************************************************
290 *       TLan_Reset
291 *
292 *       Returns:
293 *               0
294 *       Parms:
295 *               dev     Pointer to device structure of adapter
296 *                       to be reset.
297 *
298 *       This function resets the adapter and it's physical
299 *       device.  See Chap. 3, pp. 9-10 of the "ThunderLAN
300 *       Programmer's Guide" for details.  The routine tries to
301 *       implement what is detailed there, though adjustments
302 *       have been made.
303 *
304 **************************************************************/
305
306 void TLan_ResetAdapter(struct nic *nic __unused)
307 {
308         int i;
309         u32 addr;
310         u32 data;
311         u8 data8;
312
313         priv->tlanFullDuplex = FALSE;
314         priv->phyOnline = 0;
315 /*  1.  Assert reset bit. */
316
317         data = inl(BASE + TLAN_HOST_CMD);
318         data |= TLAN_HC_AD_RST;
319         outl(data, BASE + TLAN_HOST_CMD);
320
321         udelay(1000);
322
323 /*  2.  Turn off interrupts. ( Probably isn't necessary ) */
324
325         data = inl(BASE + TLAN_HOST_CMD);
326         data |= TLAN_HC_INT_OFF;
327         outl(data, BASE + TLAN_HOST_CMD);
328 /*  3.  Clear AREGs and HASHs. */
329
330         for (i = TLAN_AREG_0; i <= TLAN_HASH_2; i += 4) {
331                 TLan_DioWrite32(BASE, (u16) i, 0);
332         }
333
334 /*  4.  Setup NetConfig register. */
335
336         data =
337             TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN | TLAN_NET_CFG_PHY_EN;
338         TLan_DioWrite16(BASE, TLAN_NET_CONFIG, (u16) data);
339
340 /*  5.  Load Ld_Tmr and Ld_Thr in HOST_CMD. */
341
342         outl(TLAN_HC_LD_TMR | 0x3f, BASE + TLAN_HOST_CMD);
343         outl(TLAN_HC_LD_THR | 0x0, BASE + TLAN_HOST_CMD);
344
345 /*  6.  Unreset the MII by setting NMRST (in NetSio) to 1. */
346
347         outw(TLAN_NET_SIO, BASE + TLAN_DIO_ADR);
348         addr = BASE + TLAN_DIO_DATA + TLAN_NET_SIO;
349         TLan_SetBit(TLAN_NET_SIO_NMRST, addr);
350
351 /*  7.  Setup the remaining registers. */
352
353         if (priv->tlanRev >= 0x30) {
354                 data8 = TLAN_ID_TX_EOC | TLAN_ID_RX_EOC;
355                 TLan_DioWrite8(BASE, TLAN_INT_DIS, data8);
356         }
357         TLan_PhyDetect(nic);
358         data = TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN;
359
360         if (tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_BIT_RATE_PHY) {
361                 data |= TLAN_NET_CFG_BIT;
362                 if (priv->aui == 1) {
363                         TLan_DioWrite8(BASE, TLAN_ACOMMIT, 0x0a);
364                 } else if (priv->duplex == TLAN_DUPLEX_FULL) {
365                         TLan_DioWrite8(BASE, TLAN_ACOMMIT, 0x00);
366                         priv->tlanFullDuplex = TRUE;
367                 } else {
368                         TLan_DioWrite8(BASE, TLAN_ACOMMIT, 0x08);
369                 }
370         }
371
372         if (priv->phyNum == 0) {
373                 data |= TLAN_NET_CFG_PHY_EN;
374         }
375         TLan_DioWrite16(BASE, TLAN_NET_CONFIG, (u16) data);
376
377         if (tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_UNMANAGED_PHY) {
378                 TLan_FinishReset(nic);
379         } else {
380                 TLan_PhyPowerDown(nic);
381         }
382
383 }       /* TLan_ResetAdapter */
384
385 void TLan_FinishReset(struct nic *nic)
386 {
387
388         u8 data;
389         u32 phy;
390         u8 sio;
391         u16 status;
392         u16 partner;
393         u16 tlphy_ctl;
394         u16 tlphy_par;
395         u16 tlphy_id1, tlphy_id2;
396         int i;
397
398         phy = priv->phy[priv->phyNum];
399
400         data = TLAN_NET_CMD_NRESET | TLAN_NET_CMD_NWRAP;
401         if (priv->tlanFullDuplex) {
402                 data |= TLAN_NET_CMD_DUPLEX;
403         }
404         TLan_DioWrite8(BASE, TLAN_NET_CMD, data);
405         data = TLAN_NET_MASK_MASK4 | TLAN_NET_MASK_MASK5;
406         if (priv->phyNum == 0) {
407                 data |= TLAN_NET_MASK_MASK7;
408         }
409         TLan_DioWrite8(BASE, TLAN_NET_MASK, data);
410         TLan_DioWrite16(BASE, TLAN_MAX_RX, ((1536) + 7) & ~7);
411         TLan_MiiReadReg(nic, phy, MII_GEN_ID_HI, &tlphy_id1);
412         TLan_MiiReadReg(nic, phy, MII_GEN_ID_LO, &tlphy_id2);
413
414         if ((tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_UNMANAGED_PHY)
415             || (priv->aui)) {
416                 status = MII_GS_LINK;
417                 dprintf(("TLAN:  %s: Link forced.\n", priv->nic_name));
418         } else {
419                 TLan_MiiReadReg(nic, phy, MII_GEN_STS, &status);
420                 udelay(1000);
421                 TLan_MiiReadReg(nic, phy, MII_GEN_STS, &status);
422                 if ((status & MII_GS_LINK) &&   /* We only support link info on Nat.Sem. PHY's */
423                     (tlphy_id1 == NAT_SEM_ID1)
424                     && (tlphy_id2 == NAT_SEM_ID2)) {
425                         TLan_MiiReadReg(nic, phy, MII_AN_LPA, &partner);
426                         TLan_MiiReadReg(nic, phy, TLAN_TLPHY_PAR,
427                                         &tlphy_par);
428
429                         dprintf(("TLAN: %s: Link active with ",
430                                priv->nic_name));
431                         if (!(tlphy_par & TLAN_PHY_AN_EN_STAT)) {
432                                 dprintf(("forced 10%sMbps %s-Duplex\n",
433                                        tlphy_par & TLAN_PHY_SPEED_100 ? ""
434                                        : "0",
435                                        tlphy_par & TLAN_PHY_DUPLEX_FULL ?
436                                        "Full" : "Half"));
437                         } else {
438                                 dprintf
439                                     (("AutoNegotiation enabled, at 10%sMbps %s-Duplex\n",
440                                      tlphy_par & TLAN_PHY_SPEED_100 ? "" :
441                                      "0",
442                                      tlphy_par & TLAN_PHY_DUPLEX_FULL ?
443                                      "Full" : "Half"));
444                                 dprintf(("TLAN: Partner capability: "));
445                                 for (i = 5; i <= 10; i++)
446                                         if (partner & (1 << i)) {
447                                                 dprintf(("%s", media[i - 5]));
448                                         }
449                                 dprintf(("\n"));
450                         }
451
452                         TLan_DioWrite8(BASE, TLAN_LED_REG, TLAN_LED_LINK);
453 #ifdef MONITOR
454                         /* We have link beat..for now anyway */
455                         priv->link = 1;
456                         /*Enabling link beat monitoring */
457                         /* TLan_SetTimer( nic, (10*HZ), TLAN_TIMER_LINK_BEAT ); */
458                         mdelay(10000);
459                         TLan_PhyMonitor(nic);
460 #endif
461                 } else if (status & MII_GS_LINK) {
462                         dprintf(("TLAN: %s: Link active\n", priv->nic_name));
463                         TLan_DioWrite8(BASE, TLAN_LED_REG, TLAN_LED_LINK);
464                 }
465         }
466
467         if (priv->phyNum == 0) {
468                 TLan_MiiReadReg(nic, phy, TLAN_TLPHY_CTL, &tlphy_ctl);
469                 tlphy_ctl |= TLAN_TC_INTEN;
470                 TLan_MiiWriteReg(nic, phy, TLAN_TLPHY_CTL, tlphy_ctl);
471                 sio = TLan_DioRead8(BASE, TLAN_NET_SIO);
472                 sio |= TLAN_NET_SIO_MINTEN;
473                 TLan_DioWrite8(BASE, TLAN_NET_SIO, sio);
474         }
475
476         if (status & MII_GS_LINK) {
477                 TLan_SetMac(nic, 0, nic->node_addr);
478                 priv->phyOnline = 1;
479                 outb((TLAN_HC_INT_ON >> 8), BASE + TLAN_HOST_CMD + 1);
480                 outl(virt_to_bus(&rx_ring), BASE + TLAN_CH_PARM);
481                 outl(TLAN_HC_GO | TLAN_HC_RT, BASE + TLAN_HOST_CMD);
482         } else {
483                 dprintf
484                     (("TLAN: %s: Link inactive, will retry in 10 secs...\n",
485                      priv->nic_name));
486                 /* TLan_SetTimer( nic, (10*HZ), TLAN_TIMER_FINISH_RESET ); */
487                 mdelay(10000);
488                 TLan_FinishReset(nic);
489                 return;
490
491         }
492
493 }       /* TLan_FinishReset */
494
495 /**************************************************************************
496 POLL - Wait for a frame
497 ***************************************************************************/
498 static int tlan_poll(struct nic *nic, int retrieve)
499 {
500         /* return true if there's an ethernet packet ready to read */
501         /* nic->packet should contain data on return */
502         /* nic->packetlen should contain length of data */
503         u32 framesize;
504         u32 host_cmd = 0;
505         u32 ack = 1;
506         int eoc = 0;
507         int entry = priv->cur_rx % TLAN_NUM_RX_LISTS;
508         u16 tmpCStat = le32_to_cpu(rx_ring[entry].cStat);
509         u16 host_int = inw(BASE + TLAN_HOST_INT);
510
511         if ((tmpCStat & TLAN_CSTAT_FRM_CMP) && !retrieve)
512           return 1;
513
514         outw(host_int, BASE + TLAN_HOST_INT);
515
516         if (!(tmpCStat & TLAN_CSTAT_FRM_CMP))
517                 return 0;
518
519         /* printf("PI-1: 0x%hX\n", host_int); */
520         if (tmpCStat & TLAN_CSTAT_EOC)
521                 eoc = 1;
522
523         framesize = rx_ring[entry].frameSize;
524
525         nic->packetlen = framesize;
526
527         dprintf((".%d.", framesize)); 
528      
529         memcpy(nic->packet, rxb +
530                (priv->cur_rx * TLAN_MAX_FRAME_SIZE), nic->packetlen);
531
532         rx_ring[entry].cStat = 0;
533
534         dprintf(("%d", entry));  
535
536         entry = (entry + 1) % TLAN_NUM_RX_LISTS;
537         priv->cur_rx = entry;
538         if (eoc) {
539                 if ((rx_ring[entry].cStat & TLAN_CSTAT_READY) ==
540                     TLAN_CSTAT_READY) {
541                         ack |= TLAN_HC_GO | TLAN_HC_RT;
542                         host_cmd = TLAN_HC_ACK | ack | 0x001C0000;
543                         outl(host_cmd, BASE + TLAN_HOST_CMD);
544                 }
545         } else {
546                 host_cmd = TLAN_HC_ACK | ack | (0x000C0000);
547                 outl(host_cmd, BASE + TLAN_HOST_CMD);
548                 
549                 dprintf(("AC: 0x%hX\n", inw(BASE + TLAN_CH_PARM))); 
550                 dprintf(("PI-2: 0x%hX\n", inw(BASE + TLAN_HOST_INT)));
551         }
552         refill_rx(nic);
553         return (1);             /* initially as this is called to flush the input */
554 }
555
556 static void refill_rx(struct nic *nic __unused)
557 {
558         int entry = 0;
559
560         for (;
561              (priv->cur_rx - priv->dirty_rx +
562               TLAN_NUM_RX_LISTS) % TLAN_NUM_RX_LISTS > 0;
563              priv->dirty_rx = (priv->dirty_rx + 1) % TLAN_NUM_RX_LISTS) {
564                 entry = priv->dirty_rx % TLAN_NUM_TX_LISTS;
565                 rx_ring[entry].frameSize = TLAN_MAX_FRAME_SIZE;
566                 rx_ring[entry].cStat = TLAN_CSTAT_READY;
567         }
568
569 }
570
571 /**************************************************************************
572 TRANSMIT - Transmit a frame
573 ***************************************************************************/
574 static void tlan_transmit(struct nic *nic, const char *d,       /* Destination */
575                           unsigned int t,       /* Type */
576                           unsigned int s,       /* size */
577                           const char *p)
578 {                               /* Packet */
579         u16 nstype;
580         u32 to;
581         struct TLanList *tail_list;
582         struct TLanList *head_list;
583         u8 *tail_buffer;
584         u32 ack = 0;
585         u32 host_cmd;
586         int eoc = 0;
587         u16 tmpCStat;
588 #ifdef EBDEBUG
589         u16 host_int = inw(BASE + TLAN_HOST_INT);
590 #endif
591         int entry = 0;
592
593         dprintf(("INT0-0x%hX\n", host_int));
594
595         if (!priv->phyOnline) {
596                 printf("TRANSMIT:  %s PHY is not ready\n", priv->nic_name);
597                 return;
598         }
599
600         tail_list = priv->txList + priv->txTail;
601
602         if (tail_list->cStat != TLAN_CSTAT_UNUSED) {
603                 printf("TRANSMIT: %s is busy (Head=%d Tail=%d)\n",
604                        priv->nic_name, priv->txList, priv->txTail);
605                 tx_ring[entry].cStat = TLAN_CSTAT_UNUSED;
606 //              priv->txBusyCount++;
607                 return;
608         }
609
610         tail_list->forward = 0;
611
612         tail_buffer = txb + (priv->txTail * TLAN_MAX_FRAME_SIZE);
613
614         /* send the packet to destination */
615         memcpy(tail_buffer, d, ETH_ALEN);
616         memcpy(tail_buffer + ETH_ALEN, nic->node_addr, ETH_ALEN);
617         nstype = htons((u16) t);
618         memcpy(tail_buffer + 2 * ETH_ALEN, (u8 *) & nstype, 2);
619         memcpy(tail_buffer + ETH_HLEN, p, s);
620
621         s += ETH_HLEN;
622         s &= 0x0FFF;
623         while (s < ETH_ZLEN)
624                 tail_buffer[s++] = '\0';
625
626         /*=====================================================*/
627         /* Receive
628          * 0000 0000 0001 1100
629          * 0000 0000 0000 1100
630          * 0000 0000 0000 0011 = 0x0003
631          *
632          * 0000 0000 0000 0000 0000 0000 0000 0011
633          * 0000 0000 0000 1100 0000 0000 0000 0000 = 0x000C0000
634          *
635          * Transmit
636          * 0000 0000 0001 1100
637          * 0000 0000 0000 0100
638          * 0000 0000 0000 0001 = 0x0001
639          *
640          * 0000 0000 0000 0000 0000 0000 0000 0001
641          * 0000 0000 0000 0100 0000 0000 0000 0000 = 0x00040000
642          * */
643
644         /* Setup the transmit descriptor */
645         tail_list->frameSize = (u16) s;
646         tail_list->buffer[0].count = TLAN_LAST_BUFFER | (u32) s;
647         tail_list->buffer[1].count = 0;
648         tail_list->buffer[1].address = 0;
649
650         tail_list->cStat = TLAN_CSTAT_READY;
651
652         dprintf(("INT1-0x%hX\n", inw(BASE + TLAN_HOST_INT)));
653
654         if (!priv->txInProgress) {
655                 priv->txInProgress = 1;
656                 outl(virt_to_le32desc(tail_list), BASE + TLAN_CH_PARM);
657                 outl(TLAN_HC_GO, BASE + TLAN_HOST_CMD);
658         } else {
659                 if (priv->txTail == 0) {
660                         dprintf(("Out buffer\n"));
661                         (priv->txList + (TLAN_NUM_TX_LISTS - 1))->forward =
662                             virt_to_le32desc(tail_list);
663                 } else {
664                         dprintf(("Fix this \n"));
665                         (priv->txList + (priv->txTail - 1))->forward =
666                             virt_to_le32desc(tail_list);
667                 }
668         }
669         
670         CIRC_INC(priv->txTail, TLAN_NUM_TX_LISTS);
671
672         dprintf(("INT2-0x%hX\n", inw(BASE + TLAN_HOST_INT)));
673
674         to = currticks() + TX_TIME_OUT;
675         while ((tail_list->cStat == TLAN_CSTAT_READY) && currticks() < to);
676
677         head_list = priv->txList + priv->txHead;
678         while (((tmpCStat = head_list->cStat) & TLAN_CSTAT_FRM_CMP) 
679                         && (ack < 255)) {
680                 ack++;
681                 if(tmpCStat & TLAN_CSTAT_EOC)
682                         eoc =1;
683                 head_list->cStat = TLAN_CSTAT_UNUSED;
684                 CIRC_INC(priv->txHead, TLAN_NUM_TX_LISTS);
685                 head_list = priv->txList + priv->txHead;
686                 
687         }
688         if(!ack)
689                 printf("Incomplete TX Frame\n");
690
691         if(eoc) {
692                 head_list = priv->txList + priv->txHead;
693                 if ((head_list->cStat & TLAN_CSTAT_READY) == TLAN_CSTAT_READY) {
694                         outl(virt_to_le32desc(head_list), BASE + TLAN_CH_PARM);
695                         ack |= TLAN_HC_GO;
696                 } else {
697                         priv->txInProgress = 0;
698                 }
699         }
700         if(ack) {
701                 host_cmd = TLAN_HC_ACK | ack;
702                 outl(host_cmd, BASE + TLAN_HOST_CMD);
703         }
704         
705         if(priv->tlanRev < 0x30 ) {
706                 ack = 1;
707                 head_list = priv->txList + priv->txHead;
708                 if ((head_list->cStat & TLAN_CSTAT_READY) == TLAN_CSTAT_READY) {
709                         outl(virt_to_le32desc(head_list), BASE + TLAN_CH_PARM);
710                         ack |= TLAN_HC_GO;
711                 } else {
712                         priv->txInProgress = 0;
713                 }
714                 host_cmd = TLAN_HC_ACK | ack | 0x00140000;
715                 outl(host_cmd, BASE + TLAN_HOST_CMD);
716                 
717         }
718                         
719         if (currticks() >= to) {
720                 printf("TX Time Out");
721         }
722 }
723
724 /**************************************************************************
725 DISABLE - Turn off ethernet interface
726 ***************************************************************************/
727 static void tlan_disable ( struct nic *nic __unused ) {
728         /* put the card in its initial state */
729         /* This function serves 3 purposes.
730          * This disables DMA and interrupts so we don't receive
731          *  unexpected packets or interrupts from the card after
732          *  etherboot has finished.
733          * This frees resources so etherboot may use
734          *  this driver on another interface
735          * This allows etherboot to reinitialize the interface
736          *  if something is something goes wrong.
737          *
738          */
739         outl(TLAN_HC_AD_RST, BASE + TLAN_HOST_CMD);
740 }
741
742 /**************************************************************************
743 IRQ - Enable, Disable, or Force interrupts
744 ***************************************************************************/
745 static void tlan_irq(struct nic *nic __unused, irq_action_t action __unused)
746 {
747   switch ( action ) {
748   case DISABLE :
749     break;
750   case ENABLE :
751     break;
752   case FORCE :
753     break;
754   }
755 }
756
757 static struct nic_operations tlan_operations = {
758         .connect        = dummy_connect,
759         .poll           = tlan_poll,
760         .transmit       = tlan_transmit,
761         .irq            = tlan_irq,
762
763 };
764
765 static void TLan_SetMulticastList(struct nic *nic) {
766         int i;
767         u8 tmp;
768
769         /* !IFF_PROMISC */
770         tmp = TLan_DioRead8(BASE, TLAN_NET_CMD);
771         TLan_DioWrite8(BASE, TLAN_NET_CMD, tmp & ~TLAN_NET_CMD_CAF);
772
773         /* IFF_ALLMULTI */
774         for(i = 0; i< 3; i++)
775                 TLan_SetMac(nic, i + 1, NULL);
776         TLan_DioWrite32(BASE, TLAN_HASH_1, 0xFFFFFFFF);
777         TLan_DioWrite32(BASE, TLAN_HASH_2, 0xFFFFFFFF);
778
779         
780 }
781 /**************************************************************************
782 PROBE - Look for an adapter, this routine's visible to the outside
783 ***************************************************************************/
784
785 #define board_found 1
786 #define valid_link 0
787 static int tlan_probe ( struct nic *nic, struct pci_device *pci ) {
788
789         u16 data = 0;
790         int err;
791         int i;
792
793         if (pci->ioaddr == 0)
794                 return 0;
795
796         nic->irqno  = 0;
797         pci_fill_nic ( nic, pci );
798         nic->ioaddr = pci->ioaddr;
799
800         BASE = pci->ioaddr;
801
802         /* Set nic as PCI bus master */
803         adjust_pci_device(pci);
804         
805         /* Point to private storage */
806         priv = &TLanPrivateInfo;
807
808         /* Figure out which chip we're dealing with */
809         i = 0;
810         chip_idx = -1;
811         while (tlan_pci_tbl[i].name) {
812                 if ((((u32) pci->device << 16) | pci->vendor) ==
813                     (tlan_pci_tbl[i].id.pci & 0xffffffff)) {
814                         chip_idx = i;
815                         break;
816                 }
817                 i++;
818         }
819
820         priv->vendor_id = pci->vendor;
821         priv->dev_id = pci->device;
822         priv->nic_name = pci->name;
823         priv->eoc = 0;
824
825         err = 0;
826         for (i = 0; i < 6; i++)
827                 err |= TLan_EeReadByte(BASE,
828                                        (u8) tlan_pci_tbl[chip_idx].
829                                        addrOfs + i,
830                                        (u8 *) & nic->node_addr[i]);
831         if (err) {
832                 printf("TLAN: %s: Error reading MAC from eeprom: %d\n",
833                        pci->name, err);
834         } else 
835                 /* Print out some hardware info */
836                 printf("%s: %! at ioaddr %hX, ", 
837                         pci->name, nic->node_addr, pci->ioaddr);
838
839         priv->tlanRev = TLan_DioRead8(BASE, TLAN_DEF_REVISION);
840         printf("revision: 0x%hX\n", priv->tlanRev);
841
842         TLan_ResetLists(nic);
843         TLan_ResetAdapter(nic);
844
845         data = inl(BASE + TLAN_HOST_CMD);
846         data |= TLAN_HC_INT_OFF;
847         outw(data, BASE + TLAN_HOST_CMD);
848
849         TLan_SetMulticastList(nic);
850         udelay(100); 
851         priv->txList = tx_ring;
852
853 /*      if (board_found && valid_link)
854         {*/
855         /* point to NIC specific routines */
856         nic->nic_op     = &tlan_operations;
857         return 1;
858 }
859
860
861 /*****************************************************************************
862 ******************************************************************************
863
864         ThunderLAN Driver Eeprom routines
865
866         The Compaq Netelligent 10 and 10/100 cards use a Microchip 24C02A
867         EEPROM.  These functions are based on information in Microchip's
868         data sheet.  I don't know how well this functions will work with
869         other EEPROMs.
870
871 ******************************************************************************
872 *****************************************************************************/
873
874
875 /***************************************************************
876 *       TLan_EeSendStart
877 *
878 *       Returns:
879 *               Nothing
880 *       Parms:
881 *               io_base         The IO port base address for the
882 *                               TLAN device with the EEPROM to
883 *                               use.
884 *
885 *       This function sends a start cycle to an EEPROM attached
886 *       to a TLAN chip.
887 *
888 **************************************************************/
889
890 void TLan_EeSendStart(u16 io_base)
891 {
892         u16 sio;
893
894         outw(TLAN_NET_SIO, io_base + TLAN_DIO_ADR);
895         sio = io_base + TLAN_DIO_DATA + TLAN_NET_SIO;
896
897         TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
898         TLan_SetBit(TLAN_NET_SIO_EDATA, sio);
899         TLan_SetBit(TLAN_NET_SIO_ETXEN, sio);
900         TLan_ClearBit(TLAN_NET_SIO_EDATA, sio);
901         TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
902
903 }       /* TLan_EeSendStart */
904
905 /***************************************************************
906 *       TLan_EeSendByte
907 *
908 *       Returns:
909 *               If the correct ack was received, 0, otherwise 1
910 *       Parms:  io_base         The IO port base address for the
911 *                               TLAN device with the EEPROM to
912 *                               use.
913 *               data            The 8 bits of information to
914 *                               send to the EEPROM.
915 *               stop            If TLAN_EEPROM_STOP is passed, a
916 *                               stop cycle is sent after the
917 *                               byte is sent after the ack is
918 *                               read.
919 *
920 *       This function sends a byte on the serial EEPROM line,
921 *       driving the clock to send each bit. The function then
922 *       reverses transmission direction and reads an acknowledge
923 *       bit.
924 *
925 **************************************************************/
926
927 int TLan_EeSendByte(u16 io_base, u8 data, int stop)
928 {
929         int err;
930         u8 place;
931         u16 sio;
932
933         outw(TLAN_NET_SIO, io_base + TLAN_DIO_ADR);
934         sio = io_base + TLAN_DIO_DATA + TLAN_NET_SIO;
935
936         /* Assume clock is low, tx is enabled; */
937         for (place = 0x80; place != 0; place >>= 1) {
938                 if (place & data)
939                         TLan_SetBit(TLAN_NET_SIO_EDATA, sio);
940                 else
941                         TLan_ClearBit(TLAN_NET_SIO_EDATA, sio);
942                 TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
943                 TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
944         }
945         TLan_ClearBit(TLAN_NET_SIO_ETXEN, sio);
946         TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
947         err = TLan_GetBit(TLAN_NET_SIO_EDATA, sio);
948         TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
949         TLan_SetBit(TLAN_NET_SIO_ETXEN, sio);
950
951         if ((!err) && stop) {
952                 TLan_ClearBit(TLAN_NET_SIO_EDATA, sio); /* STOP, raise data while clock is high */
953                 TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
954                 TLan_SetBit(TLAN_NET_SIO_EDATA, sio);
955         }
956
957         return (err);
958
959 }       /* TLan_EeSendByte */
960
961 /***************************************************************
962 *       TLan_EeReceiveByte
963 *
964 *       Returns:
965 *               Nothing
966 *       Parms:
967 *               io_base         The IO port base address for the
968 *                               TLAN device with the EEPROM to
969 *                               use.
970 *               data            An address to a char to hold the
971 *                               data sent from the EEPROM.
972 *               stop            If TLAN_EEPROM_STOP is passed, a
973 *                               stop cycle is sent after the
974 *                               byte is received, and no ack is
975 *                               sent.
976 *
977 *       This function receives 8 bits of data from the EEPROM
978 *       over the serial link.  It then sends and ack bit, or no
979 *       ack and a stop bit.  This function is used to retrieve
980 *       data after the address of a byte in the EEPROM has been
981 *       sent.
982 *
983 **************************************************************/
984
985 void TLan_EeReceiveByte(u16 io_base, u8 * data, int stop)
986 {
987         u8 place;
988         u16 sio;
989
990         outw(TLAN_NET_SIO, io_base + TLAN_DIO_ADR);
991         sio = io_base + TLAN_DIO_DATA + TLAN_NET_SIO;
992         *data = 0;
993
994         /* Assume clock is low, tx is enabled; */
995         TLan_ClearBit(TLAN_NET_SIO_ETXEN, sio);
996         for (place = 0x80; place; place >>= 1) {
997                 TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
998                 if (TLan_GetBit(TLAN_NET_SIO_EDATA, sio))
999                         *data |= place;
1000                 TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
1001         }
1002
1003         TLan_SetBit(TLAN_NET_SIO_ETXEN, sio);
1004         if (!stop) {
1005                 TLan_ClearBit(TLAN_NET_SIO_EDATA, sio); /* Ack = 0 */
1006                 TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
1007                 TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
1008         } else {
1009                 TLan_SetBit(TLAN_NET_SIO_EDATA, sio);   /* No ack = 1 (?) */
1010                 TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
1011                 TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
1012                 TLan_ClearBit(TLAN_NET_SIO_EDATA, sio); /* STOP, raise data while clock is high */
1013                 TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
1014                 TLan_SetBit(TLAN_NET_SIO_EDATA, sio);
1015         }
1016
1017 }       /* TLan_EeReceiveByte */
1018
1019 /***************************************************************
1020 *       TLan_EeReadByte
1021 *
1022 *       Returns:
1023 *               No error = 0, else, the stage at which the error
1024 *               occurred.
1025 *       Parms:
1026 *               io_base         The IO port base address for the
1027 *                               TLAN device with the EEPROM to
1028 *                               use.
1029 *               ee_addr         The address of the byte in the
1030 *                               EEPROM whose contents are to be
1031 *                               retrieved.
1032 *               data            An address to a char to hold the
1033 *                               data obtained from the EEPROM.
1034 *
1035 *       This function reads a byte of information from an byte
1036 *       cell in the EEPROM.
1037 *
1038 **************************************************************/
1039
1040 int TLan_EeReadByte(u16 io_base, u8 ee_addr, u8 * data)
1041 {
1042         int err;
1043         int ret = 0;
1044
1045
1046         TLan_EeSendStart(io_base);
1047         err = TLan_EeSendByte(io_base, 0xA0, TLAN_EEPROM_ACK);
1048         if (err) {
1049                 ret = 1;
1050                 goto fail;
1051         }
1052         err = TLan_EeSendByte(io_base, ee_addr, TLAN_EEPROM_ACK);
1053         if (err) {
1054                 ret = 2;
1055                 goto fail;
1056         }
1057         TLan_EeSendStart(io_base);
1058         err = TLan_EeSendByte(io_base, 0xA1, TLAN_EEPROM_ACK);
1059         if (err) {
1060                 ret = 3;
1061                 goto fail;
1062         }
1063         TLan_EeReceiveByte(io_base, data, TLAN_EEPROM_STOP);
1064       fail:
1065
1066         return ret;
1067
1068 }       /* TLan_EeReadByte */
1069
1070
1071 /*****************************************************************************
1072 ******************************************************************************
1073
1074 ThunderLAN Driver MII Routines
1075
1076 These routines are based on the information in Chap. 2 of the
1077 "ThunderLAN Programmer's Guide", pp. 15-24.
1078
1079 ******************************************************************************
1080 *****************************************************************************/
1081
1082
1083 /***************************************************************
1084 *       TLan_MiiReadReg
1085 *
1086 *       Returns:
1087 *               0       if ack received ok
1088 *               1       otherwise.
1089 *
1090 *       Parms:
1091 *               dev             The device structure containing
1092 *                               The io address and interrupt count
1093 *                               for this device.
1094 *               phy             The address of the PHY to be queried.
1095 *               reg             The register whose contents are to be
1096 *                               retreived.
1097 *               val             A pointer to a variable to store the
1098 *                               retrieved value.
1099 *
1100 *       This function uses the TLAN's MII bus to retreive the contents
1101 *       of a given register on a PHY.  It sends the appropriate info
1102 *       and then reads the 16-bit register value from the MII bus via
1103 *       the TLAN SIO register.
1104 *
1105 **************************************************************/
1106
1107 int TLan_MiiReadReg(struct nic *nic __unused, u16 phy, u16 reg, u16 * val)
1108 {
1109         u8 nack;
1110         u16 sio, tmp;
1111         u32 i;
1112         int err;
1113         int minten;
1114
1115         err = FALSE;
1116         outw(TLAN_NET_SIO, BASE + TLAN_DIO_ADR);
1117         sio = BASE + TLAN_DIO_DATA + TLAN_NET_SIO;
1118
1119         TLan_MiiSync(BASE);
1120
1121         minten = TLan_GetBit(TLAN_NET_SIO_MINTEN, sio);
1122         if (minten)
1123                 TLan_ClearBit(TLAN_NET_SIO_MINTEN, sio);
1124
1125         TLan_MiiSendData(BASE, 0x1, 2); /* Start ( 01b ) */
1126         TLan_MiiSendData(BASE, 0x2, 2); /* Read  ( 10b ) */
1127         TLan_MiiSendData(BASE, phy, 5); /* Device #      */
1128         TLan_MiiSendData(BASE, reg, 5); /* Register #    */
1129
1130
1131         TLan_ClearBit(TLAN_NET_SIO_MTXEN, sio); /* Change direction */
1132
1133         TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);  /* Clock Idle bit */
1134         TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1135         TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);  /* Wait 300ns */
1136
1137         nack = TLan_GetBit(TLAN_NET_SIO_MDATA, sio);    /* Check for ACK */
1138         TLan_SetBit(TLAN_NET_SIO_MCLK, sio);    /* Finish ACK */
1139         if (nack) {             /* No ACK, so fake it */
1140                 for (i = 0; i < 16; i++) {
1141                         TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
1142                         TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1143                 }
1144                 tmp = 0xffff;
1145                 err = TRUE;
1146         } else {                /* ACK, so read data */
1147                 for (tmp = 0, i = 0x8000; i; i >>= 1) {
1148                         TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
1149                         if (TLan_GetBit(TLAN_NET_SIO_MDATA, sio))
1150                                 tmp |= i;
1151                         TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1152                 }
1153         }
1154
1155
1156         TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);  /* Idle cycle */
1157         TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1158
1159         if (minten)
1160                 TLan_SetBit(TLAN_NET_SIO_MINTEN, sio);
1161
1162         *val = tmp;
1163
1164         return err;
1165
1166 }                               /* TLan_MiiReadReg */
1167
1168 /***************************************************************
1169 *       TLan_MiiSendData
1170 *
1171 *       Returns:
1172 *               Nothing
1173 *       Parms:
1174 *               base_port       The base IO port of the adapter in
1175 *                               question.
1176 *               dev             The address of the PHY to be queried.
1177 *               data            The value to be placed on the MII bus.
1178 *               num_bits        The number of bits in data that are to
1179 *                               be placed on the MII bus.
1180 *
1181 *       This function sends on sequence of bits on the MII
1182 *       configuration bus.
1183 *
1184 **************************************************************/
1185
1186 void TLan_MiiSendData(u16 base_port, u32 data, unsigned num_bits)
1187 {
1188         u16 sio;
1189         u32 i;
1190
1191         if (num_bits == 0)
1192                 return;
1193
1194         outw(TLAN_NET_SIO, base_port + TLAN_DIO_ADR);
1195         sio = base_port + TLAN_DIO_DATA + TLAN_NET_SIO;
1196         TLan_SetBit(TLAN_NET_SIO_MTXEN, sio);
1197
1198         for (i = (0x1 << (num_bits - 1)); i; i >>= 1) {
1199                 TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
1200                 (void) TLan_GetBit(TLAN_NET_SIO_MCLK, sio);
1201                 if (data & i)
1202                         TLan_SetBit(TLAN_NET_SIO_MDATA, sio);
1203                 else
1204                         TLan_ClearBit(TLAN_NET_SIO_MDATA, sio);
1205                 TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1206                 (void) TLan_GetBit(TLAN_NET_SIO_MCLK, sio);
1207         }
1208
1209 }                               /* TLan_MiiSendData */
1210
1211 /***************************************************************
1212 *       TLan_MiiSync
1213 *
1214 *       Returns:
1215 *               Nothing
1216 *       Parms:
1217 *               base_port       The base IO port of the adapter in
1218 *                               question.
1219 *
1220 *       This functions syncs all PHYs in terms of the MII configuration
1221 *       bus.
1222 *
1223 **************************************************************/
1224
1225 void TLan_MiiSync(u16 base_port)
1226 {
1227         int i;
1228         u16 sio;
1229
1230         outw(TLAN_NET_SIO, base_port + TLAN_DIO_ADR);
1231         sio = base_port + TLAN_DIO_DATA + TLAN_NET_SIO;
1232
1233         TLan_ClearBit(TLAN_NET_SIO_MTXEN, sio);
1234         for (i = 0; i < 32; i++) {
1235                 TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
1236                 TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1237         }
1238
1239 }                               /* TLan_MiiSync */
1240
1241 /***************************************************************
1242 *       TLan_MiiWriteReg
1243 *
1244 *       Returns:
1245 *               Nothing
1246 *       Parms:
1247 *               dev             The device structure for the device
1248 *                               to write to.
1249 *               phy             The address of the PHY to be written to.
1250 *               reg             The register whose contents are to be
1251 *                               written.
1252 *               val             The value to be written to the register.
1253 *
1254 *       This function uses the TLAN's MII bus to write the contents of a
1255 *       given register on a PHY.  It sends the appropriate info and then
1256 *       writes the 16-bit register value from the MII configuration bus
1257 *       via the TLAN SIO register.
1258 *
1259 **************************************************************/
1260
1261 void TLan_MiiWriteReg(struct nic *nic __unused, u16 phy, u16 reg, u16 val)
1262 {
1263         u16 sio;
1264         int minten;
1265
1266         outw(TLAN_NET_SIO, BASE + TLAN_DIO_ADR);
1267         sio = BASE + TLAN_DIO_DATA + TLAN_NET_SIO;
1268
1269         TLan_MiiSync(BASE);
1270
1271         minten = TLan_GetBit(TLAN_NET_SIO_MINTEN, sio);
1272         if (minten)
1273                 TLan_ClearBit(TLAN_NET_SIO_MINTEN, sio);
1274
1275         TLan_MiiSendData(BASE, 0x1, 2); /* Start ( 01b ) */
1276         TLan_MiiSendData(BASE, 0x1, 2); /* Write ( 01b ) */
1277         TLan_MiiSendData(BASE, phy, 5); /* Device #      */
1278         TLan_MiiSendData(BASE, reg, 5); /* Register #    */
1279
1280         TLan_MiiSendData(BASE, 0x2, 2); /* Send ACK */
1281         TLan_MiiSendData(BASE, val, 16);        /* Send Data */
1282
1283         TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);  /* Idle cycle */
1284         TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1285
1286         if (minten)
1287                 TLan_SetBit(TLAN_NET_SIO_MINTEN, sio);
1288
1289
1290 }                               /* TLan_MiiWriteReg */
1291
1292 /***************************************************************
1293 *       TLan_SetMac
1294 *
1295 *       Returns:
1296 *               Nothing
1297 *       Parms:
1298 *               dev     Pointer to device structure of adapter
1299 *                       on which to change the AREG.
1300 *               areg    The AREG to set the address in (0 - 3).
1301 *               mac     A pointer to an array of chars.  Each
1302 *                       element stores one byte of the address.
1303 *                       IE, it isn't in ascii.
1304 *
1305 *       This function transfers a MAC address to one of the
1306 *       TLAN AREGs (address registers).  The TLAN chip locks
1307 *       the register on writing to offset 0 and unlocks the
1308 *       register after writing to offset 5.  If NULL is passed
1309 *       in mac, then the AREG is filled with 0's.
1310 *
1311 **************************************************************/
1312
1313 void TLan_SetMac(struct nic *nic __unused, int areg, char *mac)
1314 {
1315         int i;
1316
1317         areg *= 6;
1318
1319         if (mac != NULL) {
1320                 for (i = 0; i < 6; i++)
1321                         TLan_DioWrite8(BASE, TLAN_AREG_0 + areg + i,
1322                                        mac[i]);
1323         } else {
1324                 for (i = 0; i < 6; i++)
1325                         TLan_DioWrite8(BASE, TLAN_AREG_0 + areg + i, 0);
1326         }
1327
1328 }                               /* TLan_SetMac */
1329
1330 /*********************************************************************
1331 *       TLan_PhyDetect
1332 *
1333 *       Returns:
1334 *               Nothing
1335 *       Parms:
1336 *               dev     A pointer to the device structure of the adapter
1337 *                       for which the PHY needs determined.
1338 *
1339 *       So far I've found that adapters which have external PHYs
1340 *       may also use the internal PHY for part of the functionality.
1341 *       (eg, AUI/Thinnet).  This function finds out if this TLAN
1342 *       chip has an internal PHY, and then finds the first external
1343 *       PHY (starting from address 0) if it exists).
1344 *
1345 ********************************************************************/
1346
1347 void TLan_PhyDetect(struct nic *nic)
1348 {
1349         u16 control;
1350         u16 hi;
1351         u16 lo;
1352         u32 phy;
1353
1354         if (tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_UNMANAGED_PHY) {
1355                 priv->phyNum = 0xFFFF;
1356                 return;
1357         }
1358
1359         TLan_MiiReadReg(nic, TLAN_PHY_MAX_ADDR, MII_GEN_ID_HI, &hi);
1360
1361         if (hi != 0xFFFF) {
1362                 priv->phy[0] = TLAN_PHY_MAX_ADDR;
1363         } else {
1364                 priv->phy[0] = TLAN_PHY_NONE;
1365         }
1366
1367         priv->phy[1] = TLAN_PHY_NONE;
1368         for (phy = 0; phy <= TLAN_PHY_MAX_ADDR; phy++) {
1369                 TLan_MiiReadReg(nic, phy, MII_GEN_CTL, &control);
1370                 TLan_MiiReadReg(nic, phy, MII_GEN_ID_HI, &hi);
1371                 TLan_MiiReadReg(nic, phy, MII_GEN_ID_LO, &lo);
1372                 if ((control != 0xFFFF) || (hi != 0xFFFF)
1373                     || (lo != 0xFFFF)) {
1374                         printf("PHY found at %hX %hX %hX %hX\n", phy,
1375                                control, hi, lo);
1376                         if ((priv->phy[1] == TLAN_PHY_NONE)
1377                             && (phy != TLAN_PHY_MAX_ADDR)) {
1378                                 priv->phy[1] = phy;
1379                         }
1380                 }
1381         }
1382
1383         if (priv->phy[1] != TLAN_PHY_NONE) {
1384                 priv->phyNum = 1;
1385         } else if (priv->phy[0] != TLAN_PHY_NONE) {
1386                 priv->phyNum = 0;
1387         } else {
1388                 printf
1389                     ("TLAN:  Cannot initialize device, no PHY was found!\n");
1390         }
1391
1392 }                               /* TLan_PhyDetect */
1393
1394 void TLan_PhyPowerDown(struct nic *nic)
1395 {
1396
1397         u16 value;
1398         dprintf(("%s: Powering down PHY(s).\n", priv->nic_name));
1399         value = MII_GC_PDOWN | MII_GC_LOOPBK | MII_GC_ISOLATE;
1400         TLan_MiiSync(BASE);
1401         TLan_MiiWriteReg(nic, priv->phy[priv->phyNum], MII_GEN_CTL, value);
1402         if ((priv->phyNum == 0) && (priv->phy[1] != TLAN_PHY_NONE)
1403             &&
1404             (!(tlan_pci_tbl[chip_idx].
1405                flags & TLAN_ADAPTER_USE_INTERN_10))) {
1406                 TLan_MiiSync(BASE);
1407                 TLan_MiiWriteReg(nic, priv->phy[1], MII_GEN_CTL, value);
1408         }
1409
1410         /* Wait for 50 ms and powerup
1411          * This is abitrary.  It is intended to make sure the
1412          * tranceiver settles.
1413          */
1414         /* TLan_SetTimer( dev, (HZ/20), TLAN_TIMER_PHY_PUP ); */
1415         mdelay(50);
1416         TLan_PhyPowerUp(nic);
1417
1418 }                               /* TLan_PhyPowerDown */
1419
1420
1421 void TLan_PhyPowerUp(struct nic *nic)
1422 {
1423         u16 value;
1424
1425         dprintf(("%s: Powering up PHY.\n", priv->nic_name));
1426         TLan_MiiSync(BASE);
1427         value = MII_GC_LOOPBK;
1428         TLan_MiiWriteReg(nic, priv->phy[priv->phyNum], MII_GEN_CTL, value);
1429         TLan_MiiSync(BASE);
1430         /* Wait for 500 ms and reset the
1431          * tranceiver.  The TLAN docs say both 50 ms and
1432          * 500 ms, so do the longer, just in case.
1433          */
1434         mdelay(500);
1435         TLan_PhyReset(nic);
1436         /* TLan_SetTimer( dev, (HZ/20), TLAN_TIMER_PHY_RESET ); */
1437
1438 }                               /* TLan_PhyPowerUp */
1439
1440 void TLan_PhyReset(struct nic *nic)
1441 {
1442         u16 phy;
1443         u16 value;
1444
1445         phy = priv->phy[priv->phyNum];
1446
1447         dprintf(("%s: Reseting PHY.\n", priv->nic_name));
1448         TLan_MiiSync(BASE);
1449         value = MII_GC_LOOPBK | MII_GC_RESET;
1450         TLan_MiiWriteReg(nic, phy, MII_GEN_CTL, value);
1451         TLan_MiiReadReg(nic, phy, MII_GEN_CTL, &value);
1452         while (value & MII_GC_RESET) {
1453                 TLan_MiiReadReg(nic, phy, MII_GEN_CTL, &value);
1454         }
1455
1456         /* Wait for 500 ms and initialize.
1457          * I don't remember why I wait this long.
1458          * I've changed this to 50ms, as it seems long enough.
1459          */
1460         /* TLan_SetTimer( dev, (HZ/20), TLAN_TIMER_PHY_START_LINK ); */
1461         mdelay(50);
1462         TLan_PhyStartLink(nic);
1463
1464 }                               /* TLan_PhyReset */
1465
1466
1467 void TLan_PhyStartLink(struct nic *nic)
1468 {
1469
1470         u16 ability;
1471         u16 control;
1472         u16 data;
1473         u16 phy;
1474         u16 status;
1475         u16 tctl;
1476
1477         phy = priv->phy[priv->phyNum];
1478         dprintf(("%s: Trying to activate link.\n", priv->nic_name));
1479         TLan_MiiReadReg(nic, phy, MII_GEN_STS, &status);
1480         TLan_MiiReadReg(nic, phy, MII_GEN_STS, &ability);
1481
1482         if ((status & MII_GS_AUTONEG) && (!priv->aui)) {
1483                 ability = status >> 11;
1484                 if (priv->speed == TLAN_SPEED_10 &&
1485                     priv->duplex == TLAN_DUPLEX_HALF) {
1486                         TLan_MiiWriteReg(nic, phy, MII_GEN_CTL, 0x0000);
1487                 } else if (priv->speed == TLAN_SPEED_10 &&
1488                            priv->duplex == TLAN_DUPLEX_FULL) {
1489                         priv->tlanFullDuplex = TRUE;
1490                         TLan_MiiWriteReg(nic, phy, MII_GEN_CTL, 0x0100);
1491                 } else if (priv->speed == TLAN_SPEED_100 &&
1492                            priv->duplex == TLAN_DUPLEX_HALF) {
1493                         TLan_MiiWriteReg(nic, phy, MII_GEN_CTL, 0x2000);
1494                 } else if (priv->speed == TLAN_SPEED_100 &&
1495                            priv->duplex == TLAN_DUPLEX_FULL) {
1496                         priv->tlanFullDuplex = TRUE;
1497                         TLan_MiiWriteReg(nic, phy, MII_GEN_CTL, 0x2100);
1498                 } else {
1499
1500                         /* Set Auto-Neg advertisement */
1501                         TLan_MiiWriteReg(nic, phy, MII_AN_ADV,
1502                                          (ability << 5) | 1);
1503                         /* Enablee Auto-Neg */
1504                         TLan_MiiWriteReg(nic, phy, MII_GEN_CTL, 0x1000);
1505                         /* Restart Auto-Neg */
1506                         TLan_MiiWriteReg(nic, phy, MII_GEN_CTL, 0x1200);
1507                         /* Wait for 4 sec for autonegotiation
1508                          * to complete.  The max spec time is less than this
1509                          * but the card need additional time to start AN.
1510                          * .5 sec should be plenty extra.
1511                          */
1512                         dprintf(("TLAN: %s: Starting autonegotiation.\n",
1513                                priv->nic_name));
1514                         mdelay(4000);
1515                         TLan_PhyFinishAutoNeg(nic);
1516                         /* TLan_SetTimer( dev, (2*HZ), TLAN_TIMER_PHY_FINISH_AN ); */
1517                         return;
1518                 }
1519
1520         }
1521
1522         if ((priv->aui) && (priv->phyNum != 0)) {
1523                 priv->phyNum = 0;
1524                 data =
1525                     TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN |
1526                     TLAN_NET_CFG_PHY_EN;
1527                 TLan_DioWrite16(BASE, TLAN_NET_CONFIG, data);
1528                 mdelay(50);
1529                 /* TLan_SetTimer( dev, (40*HZ/1000), TLAN_TIMER_PHY_PDOWN ); */
1530                 TLan_PhyPowerDown(nic);
1531                 return;
1532         } else if (priv->phyNum == 0) {
1533                 control = 0;
1534                 TLan_MiiReadReg(nic, phy, TLAN_TLPHY_CTL, &tctl);
1535                 if (priv->aui) {
1536                         tctl |= TLAN_TC_AUISEL;
1537                 } else {
1538                         tctl &= ~TLAN_TC_AUISEL;
1539                         if (priv->duplex == TLAN_DUPLEX_FULL) {
1540                                 control |= MII_GC_DUPLEX;
1541                                 priv->tlanFullDuplex = TRUE;
1542                         }
1543                         if (priv->speed == TLAN_SPEED_100) {
1544                                 control |= MII_GC_SPEEDSEL;
1545                         }
1546                 }
1547                 TLan_MiiWriteReg(nic, phy, MII_GEN_CTL, control);
1548                 TLan_MiiWriteReg(nic, phy, TLAN_TLPHY_CTL, tctl);
1549         }
1550
1551         /* Wait for 2 sec to give the tranceiver time
1552          * to establish link.
1553          */
1554         /* TLan_SetTimer( dev, (4*HZ), TLAN_TIMER_FINISH_RESET ); */
1555         mdelay(2000);
1556         TLan_FinishReset(nic);
1557
1558 }                               /* TLan_PhyStartLink */
1559
1560 void TLan_PhyFinishAutoNeg(struct nic *nic)
1561 {
1562
1563         u16 an_adv;
1564         u16 an_lpa;
1565         u16 data;
1566         u16 mode;
1567         u16 phy;
1568         u16 status;
1569
1570         phy = priv->phy[priv->phyNum];
1571
1572         TLan_MiiReadReg(nic, phy, MII_GEN_STS, &status);
1573         udelay(1000);
1574         TLan_MiiReadReg(nic, phy, MII_GEN_STS, &status);
1575
1576         if (!(status & MII_GS_AUTOCMPLT)) {
1577                 /* Wait for 8 sec to give the process
1578                  * more time.  Perhaps we should fail after a while.
1579                  */
1580                 if (!priv->neg_be_verbose++) {
1581                         printf
1582                             ("TLAN:  Giving autonegotiation more time.\n");
1583                         printf
1584                             ("TLAN:  Please check that your adapter has\n");
1585                         printf
1586                             ("TLAN:  been properly connected to a HUB or Switch.\n");
1587                         printf
1588                             ("TLAN:  Trying to establish link in the background...\n");
1589                 }
1590                 mdelay(8000);
1591                 TLan_PhyFinishAutoNeg(nic);
1592                 /* TLan_SetTimer( dev, (8*HZ), TLAN_TIMER_PHY_FINISH_AN ); */
1593                 return;
1594         }
1595
1596         dprintf(("TLAN: %s: Autonegotiation complete.\n", priv->nic_name));
1597         TLan_MiiReadReg(nic, phy, MII_AN_ADV, &an_adv);
1598         TLan_MiiReadReg(nic, phy, MII_AN_LPA, &an_lpa);
1599         mode = an_adv & an_lpa & 0x03E0;
1600         if (mode & 0x0100) {
1601                 printf("Full Duplex\n");
1602                 priv->tlanFullDuplex = TRUE;
1603         } else if (!(mode & 0x0080) && (mode & 0x0040)) {
1604                 priv->tlanFullDuplex = TRUE;
1605                 printf("Full Duplex\n");
1606         }
1607
1608         if ((!(mode & 0x0180))
1609             && (tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_USE_INTERN_10)
1610             && (priv->phyNum != 0)) {
1611                 priv->phyNum = 0;
1612                 data =
1613                     TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN |
1614                     TLAN_NET_CFG_PHY_EN;
1615                 TLan_DioWrite16(BASE, TLAN_NET_CONFIG, data);
1616                 /* TLan_SetTimer( nic, (400*HZ/1000), TLAN_TIMER_PHY_PDOWN ); */
1617                 mdelay(400);
1618                 TLan_PhyPowerDown(nic);
1619                 return;
1620         }
1621
1622         if (priv->phyNum == 0) {
1623                 if ((priv->duplex == TLAN_DUPLEX_FULL)
1624                     || (an_adv & an_lpa & 0x0040)) {
1625                         TLan_MiiWriteReg(nic, phy, MII_GEN_CTL,
1626                                          MII_GC_AUTOENB | MII_GC_DUPLEX);
1627                         dprintf
1628                             (("TLAN:  Starting internal PHY with FULL-DUPLEX\n"));
1629                 } else {
1630                         TLan_MiiWriteReg(nic, phy, MII_GEN_CTL,
1631                                          MII_GC_AUTOENB);
1632                         dprintf
1633                             (("TLAN:  Starting internal PHY with HALF-DUPLEX\n"));
1634                 }
1635         }
1636
1637         /* Wait for 100 ms.  No reason in partiticular.
1638          */
1639         /* TLan_SetTimer( dev, (HZ/10), TLAN_TIMER_FINISH_RESET ); */
1640         mdelay(100);
1641         TLan_FinishReset(nic);
1642
1643 }                               /* TLan_PhyFinishAutoNeg */
1644
1645 #ifdef MONITOR
1646
1647 /*********************************************************************
1648 *
1649 *      TLan_phyMonitor
1650 *
1651 *      Returns:
1652 *              None
1653 *
1654 *      Params:
1655 *              dev             The device structure of this device.
1656 *
1657 *
1658 *      This function monitors PHY condition by reading the status
1659 *      register via the MII bus. This can be used to give info
1660 *      about link changes (up/down), and possible switch to alternate
1661 *      media.
1662 *
1663 ********************************************************************/
1664
1665 void TLan_PhyMonitor(struct net_device *dev)
1666 {
1667         TLanPrivateInfo *priv = dev->priv;
1668         u16 phy;
1669         u16 phy_status;
1670
1671         phy = priv->phy[priv->phyNum];
1672
1673         /* Get PHY status register */
1674         TLan_MiiReadReg(nic, phy, MII_GEN_STS, &phy_status);
1675
1676         /* Check if link has been lost */
1677         if (!(phy_status & MII_GS_LINK)) {
1678                 if (priv->link) {
1679                         priv->link = 0;
1680                         printf("TLAN: %s has lost link\n", priv->nic_name);
1681                         priv->flags &= ~IFF_RUNNING;
1682                         mdelay(2000);
1683                         TLan_PhyMonitor(nic);
1684                         /* TLan_SetTimer( dev, (2*HZ), TLAN_TIMER_LINK_BEAT ); */
1685                         return;
1686                 }
1687         }
1688
1689         /* Link restablished? */
1690         if ((phy_status & MII_GS_LINK) && !priv->link) {
1691                 priv->link = 1;
1692                 printf("TLAN: %s has reestablished link\n",
1693                        priv->nic_name);
1694                 priv->flags |= IFF_RUNNING;
1695         }
1696
1697         /* Setup a new monitor */
1698         /* TLan_SetTimer( dev, (2*HZ), TLAN_TIMER_LINK_BEAT ); */
1699         mdelay(2000);
1700         TLan_PhyMonitor(nic);
1701 }
1702
1703 #endif                          /* MONITOR */
1704
1705 static struct pci_device_id tlan_nics[] = {
1706         PCI_ROM(0x0e11, 0xae34, "netel10", "Compaq Netelligent 10 T PCI UTP"),
1707         PCI_ROM(0x0e11, 0xae32, "netel100","Compaq Netelligent 10/100 TX PCI UTP"),
1708         PCI_ROM(0x0e11, 0xae35, "netflex3i", "Compaq Integrated NetFlex-3/P"),
1709         PCI_ROM(0x0e11, 0xf130, "thunder", "Compaq NetFlex-3/P"),
1710         PCI_ROM(0x0e11, 0xf150, "netflex3b", "Compaq NetFlex-3/P"),
1711         PCI_ROM(0x0e11, 0xae43, "netel100pi", "Compaq Netelligent Integrated 10/100 TX UTP"),
1712         PCI_ROM(0x0e11, 0xae40, "netel100d", "Compaq Netelligent Dual 10/100 TX PCI UTP"),
1713         PCI_ROM(0x0e11, 0xb011, "netel100i", "Compaq Netelligent 10/100 TX Embedded UTP"),
1714         PCI_ROM(0x108d, 0x0013, "oc2183", "Olicom OC-2183/2185"),
1715         PCI_ROM(0x108d, 0x0012, "oc2325", "Olicom OC-2325"),
1716         PCI_ROM(0x108d, 0x0014, "oc2326", "Olicom OC-2326"),
1717         PCI_ROM(0x0e11, 0xb030, "netelligent_10_100_ws_5100", "Compaq Netelligent 10/100 TX UTP"),
1718         PCI_ROM(0x0e11, 0xb012, "netelligent_10_t2", "Compaq Netelligent 10 T/2 PCI UTP/Coax"),
1719 };
1720
1721 PCI_DRIVER ( tlan_driver, tlan_nics, PCI_NO_CLASS );
1722
1723 DRIVER ( "TLAN/PCI", nic_driver, pci_driver, tlan_driver,
1724          tlan_probe, tlan_disable );