compilation warnings cleanup
[people/xl0/gpxe.git] / src / drivers / net / tg3.c
1 /* $Id$
2  * tg3.c: Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001, 2002 Jeff Garzik (jgarzik@mandrakesoft.com)
6  * Copyright (C) 2003 Eric Biederman (ebiederman@lnxi.com)  [etherboot port]
7  */
8
9 /* 11-13-2003   timlegge        Fix Issue with NetGear GA302T 
10  * 11-18-2003   ebiederm        Generalize NetGear Fix to what the code was supposed to be.
11  * 01-06-2005   Alf (Frederic Olivie) Add Dell bcm 5751 (0x1677) support
12  * 04-15-2005   Martin Vogt Add Fujitsu Siemens Computer (FSC) 0x1734 bcm 5751 0x105d support
13  */
14
15 #include "etherboot.h"
16 #include "nic.h"
17 #include <gpxe/pci.h>
18 #include <gpxe/ethernet.h>
19 #include "timer.h"
20 #include "string.h"
21 #include "tg3.h"
22
23 #define SUPPORT_COPPER_PHY  1
24 #define SUPPORT_FIBER_PHY   1
25 #define SUPPORT_LINK_REPORT 1
26 #define SUPPORT_PARTNO_STR  1
27 #define SUPPORT_PHY_STR     1
28
29 static struct tg3 tg3;
30
31 /* Dummy defines for error handling */
32 #define EBUSY  1
33 #define ENODEV 2
34 #define EINVAL 3
35 #define ENOMEM 4
36
37
38 /* These numbers seem to be hard coded in the NIC firmware somehow.
39  * You can't change the ring sizes, but you can change where you place
40  * them in the NIC onboard memory.
41  */
42 #define TG3_RX_RING_SIZE                512
43 #define TG3_DEF_RX_RING_PENDING         20      /* RX_RING_PENDING seems to be o.k. at 20 and 200 */
44 #define TG3_RX_RCB_RING_SIZE    1024
45
46 /*      (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ? \
47          512 : 1024) */
48 #define TG3_TX_RING_SIZE                512
49 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
50
51 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_RING_SIZE)
52 #define TG3_RX_RCB_RING_BYTES   (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_RCB_RING_SIZE)
53
54 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * TG3_TX_RING_SIZE)
55 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
56 #define PREV_TX(N)              (((N) - 1) & (TG3_TX_RING_SIZE - 1))
57
58 #define RX_PKT_BUF_SZ           (1536 + 2 + 64)
59
60 struct eth_frame {
61         uint8_t  dst_addr[ETH_ALEN];
62         uint8_t  src_addr[ETH_ALEN];
63         uint16_t type;
64         uint8_t  data [ETH_FRAME_LEN - ETH_HLEN];
65 };
66
67 struct bss {
68         struct tg3_rx_buffer_desc rx_std[TG3_RX_RING_SIZE];
69         struct tg3_rx_buffer_desc rx_rcb[TG3_RX_RCB_RING_SIZE];
70         struct tg3_tx_buffer_desc tx_ring[TG3_TX_RING_SIZE];
71         struct tg3_hw_status      hw_status;
72         struct tg3_hw_stats       hw_stats;
73         unsigned char             rx_bufs[TG3_DEF_RX_RING_PENDING][RX_PKT_BUF_SZ];
74         struct eth_frame          tx_frame[2];
75 } tg3_bss __shared;
76
77 /**
78  * pci_save_state - save the PCI configuration space of a device before suspending
79  * @dev: - PCI device that we're dealing with
80  * @buffer: - buffer to hold config space context
81  *
82  * @buffer must be large enough to hold the entire PCI 2.2 config space 
83  * (>= 64 bytes).
84  */
85 static int pci_save_state(struct pci_device *dev, uint32_t *buffer)
86 {
87         int i;
88         for (i = 0; i < 16; i++)
89                 pci_read_config_dword(dev, i * 4,&buffer[i]);
90         return 0;
91 }
92
93 /** 
94  * pci_restore_state - Restore the saved state of a PCI device
95  * @dev: - PCI device that we're dealing with
96  * @buffer: - saved PCI config space
97  *
98  */
99 static int pci_restore_state(struct pci_device *dev, uint32_t *buffer)
100 {
101         int i;
102
103         for (i = 0; i < 16; i++)
104                 pci_write_config_dword(dev,i * 4, buffer[i]);
105         return 0;
106 }
107
108 static void tg3_write_indirect_reg32(uint32_t off, uint32_t val)
109 {
110         pci_write_config_dword(tg3.pdev, TG3PCI_REG_BASE_ADDR, off);
111         pci_write_config_dword(tg3.pdev, TG3PCI_REG_DATA, val);
112 }
113
114 #define tw32(reg,val)           tg3_write_indirect_reg32((reg),(val))
115 #define tw32_mailbox(reg, val)  writel(((val) & 0xffffffff), tg3.regs + (reg))
116 #define tw16(reg,val)           writew(((val) & 0xffff), tg3.regs + (reg))
117 #define tw8(reg,val)            writeb(((val) & 0xff), tg3.regs + (reg))
118 #define tr32(reg)               readl(tg3.regs + (reg))
119 #define tr16(reg)               readw(tg3.regs + (reg))
120 #define tr8(reg)                readb(tg3.regs + (reg))
121
122 static void tw32_carefully(uint32_t reg, uint32_t val)
123 {
124         tw32(reg, val);
125         tr32(reg);
126         udelay(100);
127 }
128
129 static void tw32_mailbox2(uint32_t reg, uint32_t val)
130 {
131         tw32_mailbox(reg, val);
132         tr32(reg);
133 }
134
135 static void tg3_write_mem(uint32_t off, uint32_t val)
136 {
137         pci_write_config_dword(tg3.pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
138         pci_write_config_dword(tg3.pdev, TG3PCI_MEM_WIN_DATA, val);
139
140         /* Always leave this as zero. */
141         pci_write_config_dword(tg3.pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
142 }
143
144 static void tg3_read_mem(uint32_t off, uint32_t *val)
145 {
146         pci_write_config_dword(tg3.pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
147         pci_read_config_dword(tg3.pdev, TG3PCI_MEM_WIN_DATA, val);
148
149         /* Always leave this as zero. */
150         pci_write_config_dword(tg3.pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
151 }
152
153 static void tg3_disable_ints(struct tg3 *tp)
154 {
155         tw32(TG3PCI_MISC_HOST_CTRL,
156              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
157         tw32_mailbox2(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
158 }
159
160 static void tg3_switch_clocks(struct tg3 *tp)
161 {
162         uint32_t orig_clock_ctrl, clock_ctrl;
163
164         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
165
166         orig_clock_ctrl = clock_ctrl;
167         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN | CLOCK_CTRL_CLKRUN_OENABLE | 0x1f);
168         tp->pci_clock_ctrl = clock_ctrl;
169         
170         if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) &&
171             (!((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
172                && (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) &&
173                 (orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE)!=0) {
174                 tw32_carefully(TG3PCI_CLOCK_CTRL, 
175                         clock_ctrl | (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK));
176                 tw32_carefully(TG3PCI_CLOCK_CTRL, 
177                         clock_ctrl | (CLOCK_CTRL_ALTCLK));
178         }
179         tw32_carefully(TG3PCI_CLOCK_CTRL, clock_ctrl);
180 }
181
182 #define PHY_BUSY_LOOPS  5000
183
184 static int tg3_readphy(struct tg3 *tp, int reg, uint32_t *val)
185 {
186         uint32_t frame_val;
187         int loops, ret;
188
189         tw32_carefully(MAC_MI_MODE, tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL);
190
191         *val = 0xffffffff;
192
193         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
194                       MI_COM_PHY_ADDR_MASK);
195         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
196                       MI_COM_REG_ADDR_MASK);
197         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
198         
199         tw32_carefully(MAC_MI_COM, frame_val);
200
201         loops = PHY_BUSY_LOOPS;
202         while (loops-- > 0) {
203                 udelay(10);
204                 frame_val = tr32(MAC_MI_COM);
205
206                 if ((frame_val & MI_COM_BUSY) == 0) {
207                         udelay(5);
208                         frame_val = tr32(MAC_MI_COM);
209                         break;
210                 }
211         }
212
213         ret = -EBUSY;
214         if (loops > 0) {
215                 *val = frame_val & MI_COM_DATA_MASK;
216                 ret = 0;
217         }
218
219         tw32_carefully(MAC_MI_MODE, tp->mi_mode);
220
221         return ret;
222 }
223
224 static int tg3_writephy(struct tg3 *tp, int reg, uint32_t val)
225 {
226         uint32_t frame_val;
227         int loops, ret;
228
229         tw32_carefully(MAC_MI_MODE, tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL);
230
231         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
232                       MI_COM_PHY_ADDR_MASK);
233         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
234                       MI_COM_REG_ADDR_MASK);
235         frame_val |= (val & MI_COM_DATA_MASK);
236         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
237         
238         tw32_carefully(MAC_MI_COM, frame_val);
239
240         loops = PHY_BUSY_LOOPS;
241         while (loops-- > 0) {
242                 udelay(10);
243                 frame_val = tr32(MAC_MI_COM);
244                 if ((frame_val & MI_COM_BUSY) == 0) {
245                         udelay(5);
246                         frame_val = tr32(MAC_MI_COM);
247                         break;
248                 }
249         }
250
251         ret = -EBUSY;
252         if (loops > 0)
253                 ret = 0;
254
255         tw32_carefully(MAC_MI_MODE, tp->mi_mode);
256
257         return ret;
258 }
259
260 static int tg3_writedsp(struct tg3 *tp, uint16_t addr, uint16_t val)
261 {
262         int err;
263         err  = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, addr);
264         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
265         return err;
266 }
267
268
269 static void tg3_phy_set_wirespeed(struct tg3 *tp)
270 {
271         uint32_t val;
272
273         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
274                 return;
275
276         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007);
277         tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
278         tg3_writephy(tp, MII_TG3_AUX_CTRL, (val | (1 << 15) | (1 << 4)));
279 }
280
281 static int tg3_bmcr_reset(struct tg3 *tp)
282 {
283         uint32_t phy_control;
284         int limit, err;
285
286         /* OK, reset it, and poll the BMCR_RESET bit until it
287          * clears or we time out.
288          */
289         phy_control = BMCR_RESET;
290         err = tg3_writephy(tp, MII_BMCR, phy_control);
291         if (err != 0)
292                 return -EBUSY;
293
294         limit = 5000;
295         while (limit--) {
296                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
297                 if (err != 0)
298                         return -EBUSY;
299
300                 if ((phy_control & BMCR_RESET) == 0) {
301                         udelay(40);
302                         break;
303                 }
304                 udelay(10);
305         }
306         if (limit <= 0)
307                 return -EBUSY;
308
309         return 0;
310 }
311
312 static int tg3_wait_macro_done(struct tg3 *tp)
313 {
314         int limit = 100;
315
316         while (limit--) {
317                 uint32_t tmp32;
318
319                 tg3_readphy(tp, 0x16, &tmp32);
320                 if ((tmp32 & 0x1000) == 0)
321                         break;
322         }
323         if (limit <= 0)
324                 return -EBUSY;
325
326         return 0;
327 }
328
329 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
330 {
331         static const uint32_t test_pat[4][6] = {
332         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
333         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
334         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
335         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
336         };
337         int chan;
338
339         for (chan = 0; chan < 4; chan++) {
340                 int i;
341
342                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
343                         (chan * 0x2000) | 0x0200);
344                 tg3_writephy(tp, 0x16, 0x0002);
345
346                 for (i = 0; i < 6; i++)
347                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
348                                 test_pat[chan][i]);
349
350                 tg3_writephy(tp, 0x16, 0x0202);
351                 if (tg3_wait_macro_done(tp)) {
352                         *resetp = 1;
353                         return -EBUSY;
354                 }
355
356                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
357                              (chan * 0x2000) | 0x0200);
358                 tg3_writephy(tp, 0x16, 0x0082);
359                 if (tg3_wait_macro_done(tp)) {
360                         *resetp = 1;
361                         return -EBUSY;
362                 }
363
364                 tg3_writephy(tp, 0x16, 0x0802);
365                 if (tg3_wait_macro_done(tp)) {
366                         *resetp = 1;
367                         return -EBUSY;
368                 }
369
370                 for (i = 0; i < 6; i += 2) {
371                         uint32_t low, high;
372
373                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low);
374                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high);
375                         if (tg3_wait_macro_done(tp)) {
376                                 *resetp = 1;
377                                 return -EBUSY;
378                         }
379                         low &= 0x7fff;
380                         high &= 0x000f;
381                         if (low != test_pat[chan][i] ||
382                             high != test_pat[chan][i+1]) {
383                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
384                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
385                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
386
387                                 return -EBUSY;
388                         }
389                 }
390         }
391
392         return 0;
393 }
394
395 static int tg3_phy_reset_chanpat(struct tg3 *tp)
396 {
397         int chan;
398
399         for (chan = 0; chan < 4; chan++) {
400                 int i;
401
402                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
403                              (chan * 0x2000) | 0x0200);
404                 tg3_writephy(tp, 0x16, 0x0002);
405                 for (i = 0; i < 6; i++)
406                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
407                 tg3_writephy(tp, 0x16, 0x0202);
408                 if (tg3_wait_macro_done(tp))
409                         return -EBUSY;
410         }
411
412         return 0;
413 }
414
415 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
416 {
417         uint32_t reg32, phy9_orig;
418         int retries, do_phy_reset, err;
419
420         retries = 10;
421         do_phy_reset = 1;
422         do {
423                 if (do_phy_reset) {
424                         err = tg3_bmcr_reset(tp);
425                         if (err)
426                                 return err;
427                         do_phy_reset = 0;
428                 }
429                 
430                 /* Disable transmitter and interrupt.  */
431                 tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32);
432                 reg32 |= 0x3000;
433                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
434
435                 /* Set full-duplex, 1000 mbps.  */
436                 tg3_writephy(tp, MII_BMCR,
437                         BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
438
439                 /* Set to master mode.  */
440                 tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig);
441                 tg3_writephy(tp, MII_TG3_CTRL,
442                         (MII_TG3_CTRL_AS_MASTER |
443                                 MII_TG3_CTRL_ENABLE_AS_MASTER));
444
445                 /* Enable SM_DSP_CLOCK and 6dB.  */
446                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
447
448                 /* Block the PHY control access.  */
449                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
450                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
451
452                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
453                 if (!err)
454                         break;
455         } while (--retries);
456
457         err = tg3_phy_reset_chanpat(tp);
458         if (err)
459                 return err;
460
461         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
462         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
463
464         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
465         tg3_writephy(tp, 0x16, 0x0000);
466
467         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
468
469         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
470
471         tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32);
472         reg32 &= ~0x3000;
473         tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
474
475         return err;
476 }
477
478 /* This will reset the tigon3 PHY if there is no valid
479  * link.
480  */
481 static int tg3_phy_reset(struct tg3 *tp)
482 {
483         uint32_t phy_status;
484         int err;
485
486         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
487         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
488         if (err != 0)
489                 return -EBUSY;
490
491         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) ||
492                 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
493                 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
494                 err = tg3_phy_reset_5703_4_5(tp);
495                 if (err)
496                         return err;
497                 goto out;
498         }
499         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
500           // Taken from Broadcom's source code
501           tg3_writephy(tp, 0x18, 0x0c00);
502           tg3_writephy(tp, 0x17, 0x000a);
503           tg3_writephy(tp, 0x15, 0x310b);
504           tg3_writephy(tp, 0x17, 0x201f);
505           tg3_writephy(tp, 0x15, 0x9506);
506           tg3_writephy(tp, 0x17, 0x401f);
507           tg3_writephy(tp, 0x15, 0x14e2);
508           tg3_writephy(tp, 0x18, 0x0400);
509         }
510         err = tg3_bmcr_reset(tp);
511         if (err)
512                 return err;
513  out:
514         tg3_phy_set_wirespeed(tp);
515         return 0;
516 }
517
518 static void tg3_set_power_state_0(struct tg3 *tp)
519 {
520         uint16_t power_control;
521         int pm = tp->pm_cap;
522
523         /* Make sure register accesses (indirect or otherwise)
524          * will function correctly.
525          */
526         pci_write_config_dword(tp->pdev,  TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
527
528         pci_read_config_word(tp->pdev, pm + PCI_PM_CTRL, &power_control);
529
530         power_control |= PCI_PM_CTRL_PME_STATUS;
531         power_control &= ~(PCI_PM_CTRL_STATE_MASK);
532         power_control |= 0;
533         pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
534
535         tw32_carefully(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
536
537         return;
538 }
539
540
541 #if SUPPORT_LINK_REPORT
542 static void tg3_link_report(struct tg3 *tp)
543 {
544         if (!tp->carrier_ok) {
545                 printf("Link is down.\n");
546         } else {
547                 printf("Link is up at %d Mbps, %s duplex. %s %s %s\n",
548                         (tp->link_config.active_speed == SPEED_1000 ?
549                                1000 :
550                         (tp->link_config.active_speed == SPEED_100 ?
551                                 100 : 10)),
552                         (tp->link_config.active_duplex == DUPLEX_FULL ?  
553                                 "full" : "half"),
554                         (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "TX" : "",
555                         (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "RX" : "",
556                         (tp->tg3_flags & (TG3_FLAG_TX_PAUSE |TG3_FLAG_RX_PAUSE)) ? "flow control" : "");
557         }
558 }
559 #else
560 #define tg3_link_report(tp)
561 #endif
562
563 static void tg3_setup_flow_control(struct tg3 *tp, uint32_t local_adv, uint32_t remote_adv)
564 {
565         uint32_t new_tg3_flags = 0;
566
567         if (local_adv & ADVERTISE_PAUSE_CAP) {
568                 if (local_adv & ADVERTISE_PAUSE_ASYM) {
569                         if (remote_adv & LPA_PAUSE_CAP)
570                                 new_tg3_flags |=
571                                         (TG3_FLAG_RX_PAUSE |
572                                          TG3_FLAG_TX_PAUSE);
573                         else if (remote_adv & LPA_PAUSE_ASYM)
574                                 new_tg3_flags |=
575                                         (TG3_FLAG_RX_PAUSE);
576                 } else {
577                         if (remote_adv & LPA_PAUSE_CAP)
578                                 new_tg3_flags |=
579                                         (TG3_FLAG_RX_PAUSE |
580                                          TG3_FLAG_TX_PAUSE);
581                 }
582         } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
583                 if ((remote_adv & LPA_PAUSE_CAP) &&
584                     (remote_adv & LPA_PAUSE_ASYM))
585                         new_tg3_flags |= TG3_FLAG_TX_PAUSE;
586         }
587
588         tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
589         tp->tg3_flags |= new_tg3_flags;
590
591         if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
592                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
593         else
594                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
595
596         if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
597                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
598         else
599                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
600 }
601
602 #if SUPPORT_COPPER_PHY
603 static void tg3_aux_stat_to_speed_duplex(
604         struct tg3 *tp __unused, uint32_t val, uint8_t *speed, uint8_t *duplex)
605 {
606         static const uint8_t map[] = {
607                 [0] = (SPEED_INVALID << 2) | DUPLEX_INVALID,
608                 [MII_TG3_AUX_STAT_10HALF >> 8]   = (SPEED_10 << 2) | DUPLEX_HALF,
609                 [MII_TG3_AUX_STAT_10FULL >> 8]   = (SPEED_10 << 2) | DUPLEX_FULL,
610                 [MII_TG3_AUX_STAT_100HALF >> 8]  = (SPEED_100 << 2) | DUPLEX_HALF,
611                 [MII_TG3_AUX_STAT_100_4 >> 8] = (SPEED_INVALID << 2) | DUPLEX_INVALID,
612                 [MII_TG3_AUX_STAT_100FULL >> 8]  = (SPEED_100 << 2) | DUPLEX_FULL,
613                 [MII_TG3_AUX_STAT_1000HALF >> 8] = (SPEED_1000 << 2) | DUPLEX_HALF,
614                 [MII_TG3_AUX_STAT_1000FULL >> 8] = (SPEED_1000 << 2) | DUPLEX_FULL,
615         };
616         uint8_t result;
617         result = map[(val & MII_TG3_AUX_STAT_SPDMASK) >> 8];
618         *speed = result >> 2;
619         *duplex = result & 3;
620 }
621
622 static int tg3_phy_copper_begin(struct tg3 *tp)
623 {
624         uint32_t new_adv;
625
626         tp->link_config.advertising =
627                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
628                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
629                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
630                         ADVERTISED_Autoneg | ADVERTISED_MII);
631         
632         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY) {
633                 tp->link_config.advertising &=
634                         ~(ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
635         }
636         
637         new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
638         if (tp->link_config.advertising & ADVERTISED_10baseT_Half) {
639                 new_adv |= ADVERTISE_10HALF;
640         }
641         if (tp->link_config.advertising & ADVERTISED_10baseT_Full) {
642                 new_adv |= ADVERTISE_10FULL;
643         }
644         if (tp->link_config.advertising & ADVERTISED_100baseT_Half) {
645                 new_adv |= ADVERTISE_100HALF;
646         }
647         if (tp->link_config.advertising & ADVERTISED_100baseT_Full) {
648                 new_adv |= ADVERTISE_100FULL;
649         }
650         tg3_writephy(tp, MII_ADVERTISE, new_adv);
651         
652         if (tp->link_config.advertising &
653                 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
654                 new_adv = 0;
655                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half) {
656                         new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
657                 }
658                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full) {
659                         new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
660                 }
661                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
662                         (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
663                                 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)) {
664                         new_adv |= (MII_TG3_CTRL_AS_MASTER |
665                                 MII_TG3_CTRL_ENABLE_AS_MASTER);
666                 }
667                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
668         } else {
669                 tg3_writephy(tp, MII_TG3_CTRL, 0);
670         }
671
672         tg3_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
673
674         return 0;
675 }
676
677 static int tg3_init_5401phy_dsp(struct tg3 *tp)
678 {
679         int err;
680
681         /* Turn off tap power management. */
682         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c20);
683         
684         err |= tg3_writedsp(tp, 0x0012, 0x1804);
685         err |= tg3_writedsp(tp, 0x0013, 0x1204);
686         err |= tg3_writedsp(tp, 0x8006, 0x0132);
687         err |= tg3_writedsp(tp, 0x8006, 0x0232);
688         err |= tg3_writedsp(tp, 0x201f, 0x0a20);
689
690         udelay(40);
691
692         return err;
693 }
694
695 static int tg3_setup_copper_phy(struct tg3 *tp)
696 {
697         int current_link_up;
698         uint32_t bmsr, dummy;
699         int i, err;
700
701         tw32_carefully(MAC_STATUS,
702                 (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED
703                  | MAC_STATUS_LNKSTATE_CHANGED));
704
705         tp->mi_mode = MAC_MI_MODE_BASE;
706         tw32_carefully(MAC_MI_MODE, tp->mi_mode);
707
708         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
709
710         /* Some third-party PHYs need to be reset on link going
711          * down.
712          */
713         if (    (       (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) ||
714                         (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
715                         (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)) &&
716                 (tp->carrier_ok)) {
717                 tg3_readphy(tp, MII_BMSR, &bmsr);
718                 tg3_readphy(tp, MII_BMSR, &bmsr);
719                 if (!(bmsr & BMSR_LSTATUS))
720                         tg3_phy_reset(tp);
721         }
722
723         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
724                 tg3_readphy(tp, MII_BMSR, &bmsr);
725                 tg3_readphy(tp, MII_BMSR, &bmsr);
726
727                 if (!(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
728                         bmsr = 0;
729
730                 if (!(bmsr & BMSR_LSTATUS)) {
731                         err = tg3_init_5401phy_dsp(tp);
732                         if (err)
733                                 return err;
734
735                         tg3_readphy(tp, MII_BMSR, &bmsr);
736                         for (i = 0; i < 1000; i++) {
737                                 udelay(10);
738                                 tg3_readphy(tp, MII_BMSR, &bmsr);
739                                 if (bmsr & BMSR_LSTATUS) {
740                                         udelay(40);
741                                         break;
742                                 }
743                         }
744
745                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
746                             !(bmsr & BMSR_LSTATUS) &&
747                             tp->link_config.active_speed == SPEED_1000) {
748                                 err = tg3_phy_reset(tp);
749                                 if (!err)
750                                         err = tg3_init_5401phy_dsp(tp);
751                                 if (err)
752                                         return err;
753                         }
754                 }
755         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
756                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
757                 /* 5701 {A0,B0} CRC bug workaround */
758                 tg3_writephy(tp, 0x15, 0x0a75);
759                 tg3_writephy(tp, 0x1c, 0x8c68);
760                 tg3_writephy(tp, 0x1c, 0x8d68);
761                 tg3_writephy(tp, 0x1c, 0x8c68);
762         }
763
764         /* Clear pending interrupts... */
765         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
766         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
767
768         tg3_writephy(tp, MII_TG3_IMASK, ~0);
769
770         if (tp->led_mode == led_mode_three_link)
771                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
772                              MII_TG3_EXT_CTRL_LNK3_LED_MODE);
773         else
774                 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
775
776         current_link_up = 0;
777
778         tg3_readphy(tp, MII_BMSR, &bmsr);
779         tg3_readphy(tp, MII_BMSR, &bmsr);
780
781         if (bmsr & BMSR_LSTATUS) {
782                 uint32_t aux_stat, bmcr;
783
784                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
785                 for (i = 0; i < 2000; i++) {
786                         udelay(10);
787                         tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
788                         if (aux_stat)
789                                 break;
790                 }
791
792                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
793                         &tp->link_config.active_speed,
794                         &tp->link_config.active_duplex);
795                 tg3_readphy(tp, MII_BMCR, &bmcr);
796                 tg3_readphy(tp, MII_BMCR, &bmcr);
797                 if (bmcr & BMCR_ANENABLE) {
798                         uint32_t gig_ctrl;
799                         
800                         current_link_up = 1;
801                         
802                         /* Force autoneg restart if we are exiting
803                          * low power mode.
804                          */
805                         tg3_readphy(tp, MII_TG3_CTRL, &gig_ctrl);
806                         if (!(gig_ctrl & (MII_TG3_CTRL_ADV_1000_HALF |
807                                       MII_TG3_CTRL_ADV_1000_FULL))) {
808                                 current_link_up = 0;
809                         }
810                 } else {
811                         current_link_up = 0;
812                 }
813         }
814
815         if (current_link_up == 1 &&
816                 (tp->link_config.active_duplex == DUPLEX_FULL)) {
817                 uint32_t local_adv, remote_adv;
818
819                 tg3_readphy(tp, MII_ADVERTISE, &local_adv);
820                 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
821
822                 tg3_readphy(tp, MII_LPA, &remote_adv);
823                 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
824
825                 /* If we are not advertising full pause capability,
826                  * something is wrong.  Bring the link down and reconfigure.
827                  */
828                 if (local_adv != ADVERTISE_PAUSE_CAP) {
829                         current_link_up = 0;
830                 } else {
831                         tg3_setup_flow_control(tp, local_adv, remote_adv);
832                 }
833         }
834
835         if (current_link_up == 0) {
836                 uint32_t tmp;
837
838                 tg3_phy_copper_begin(tp);
839
840                 tg3_readphy(tp, MII_BMSR, &tmp);
841                 tg3_readphy(tp, MII_BMSR, &tmp);
842                 if (tmp & BMSR_LSTATUS)
843                         current_link_up = 1;
844         }
845
846         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
847         if (current_link_up == 1) {
848                 if (tp->link_config.active_speed == SPEED_100 ||
849                     tp->link_config.active_speed == SPEED_10)
850                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
851                 else
852                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
853         } else
854                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
855
856         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
857         if (tp->link_config.active_duplex == DUPLEX_HALF)
858                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
859
860         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
861         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
862                 if ((tp->led_mode == led_mode_link10) ||
863                     (current_link_up == 1 &&
864                      tp->link_config.active_speed == SPEED_10))
865                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
866         } else {
867                 if (current_link_up == 1)
868                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
869                 tw32(MAC_LED_CTRL, LED_CTRL_PHY_MODE_1);
870         }
871
872         /* ??? Without this setting Netgear GA302T PHY does not
873          * ??? send/receive packets...
874          * With this other PHYs cannot bring up the link
875          */
876         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
877                 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
878                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
879                 tw32_carefully(MAC_MI_MODE, tp->mi_mode);
880         }
881
882         tw32_carefully(MAC_MODE, tp->mac_mode);
883
884         /* Link change polled. */
885         tw32_carefully(MAC_EVENT, 0);
886
887         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
888             current_link_up == 1 &&
889             tp->link_config.active_speed == SPEED_1000 &&
890             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
891              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
892                 udelay(120);
893                 tw32_carefully(MAC_STATUS,
894                         (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED));
895                 tg3_write_mem(
896                               NIC_SRAM_FIRMWARE_MBOX,
897                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
898         }
899
900         if (current_link_up != tp->carrier_ok) {
901                 tp->carrier_ok = current_link_up;
902                 tg3_link_report(tp);
903         }
904
905         return 0;
906 }
907 #else
908 #define tg3_setup_copper_phy(TP) (-EINVAL)
909 #endif /* SUPPORT_COPPER_PHY */
910
911 #if SUPPORT_FIBER_PHY
912 struct tg3_fiber_aneginfo {
913         int state;
914 #define ANEG_STATE_UNKNOWN              0
915 #define ANEG_STATE_AN_ENABLE            1
916 #define ANEG_STATE_RESTART_INIT         2
917 #define ANEG_STATE_RESTART              3
918 #define ANEG_STATE_DISABLE_LINK_OK      4
919 #define ANEG_STATE_ABILITY_DETECT_INIT  5
920 #define ANEG_STATE_ABILITY_DETECT       6
921 #define ANEG_STATE_ACK_DETECT_INIT      7
922 #define ANEG_STATE_ACK_DETECT           8
923 #define ANEG_STATE_COMPLETE_ACK_INIT    9
924 #define ANEG_STATE_COMPLETE_ACK         10
925 #define ANEG_STATE_IDLE_DETECT_INIT     11
926 #define ANEG_STATE_IDLE_DETECT          12
927 #define ANEG_STATE_LINK_OK              13
928 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
929 #define ANEG_STATE_NEXT_PAGE_WAIT       15
930
931         uint32_t flags;
932 #define MR_AN_ENABLE            0x00000001
933 #define MR_RESTART_AN           0x00000002
934 #define MR_AN_COMPLETE          0x00000004
935 #define MR_PAGE_RX              0x00000008
936 #define MR_NP_LOADED            0x00000010
937 #define MR_TOGGLE_TX            0x00000020
938 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
939 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
940 #define MR_LP_ADV_SYM_PAUSE     0x00000100
941 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
942 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
943 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
944 #define MR_LP_ADV_NEXT_PAGE     0x00001000
945 #define MR_TOGGLE_RX            0x00002000
946 #define MR_NP_RX                0x00004000
947
948 #define MR_LINK_OK              0x80000000
949
950         unsigned long link_time, cur_time;
951
952         uint32_t ability_match_cfg;
953         int ability_match_count;
954
955         char ability_match, idle_match, ack_match;
956
957         uint32_t txconfig, rxconfig;
958 #define ANEG_CFG_NP             0x00000080
959 #define ANEG_CFG_ACK            0x00000040
960 #define ANEG_CFG_RF2            0x00000020
961 #define ANEG_CFG_RF1            0x00000010
962 #define ANEG_CFG_PS2            0x00000001
963 #define ANEG_CFG_PS1            0x00008000
964 #define ANEG_CFG_HD             0x00004000
965 #define ANEG_CFG_FD             0x00002000
966 #define ANEG_CFG_INVAL          0x00001f06
967
968 };
969 #define ANEG_OK         0
970 #define ANEG_DONE       1
971 #define ANEG_TIMER_ENAB 2
972 #define ANEG_FAILED     -1
973
974 #define ANEG_STATE_SETTLE_TIME  10000
975
976 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
977                                    struct tg3_fiber_aneginfo *ap)
978 {
979         unsigned long delta;
980         uint32_t rx_cfg_reg;
981         int ret;
982
983         if (ap->state == ANEG_STATE_UNKNOWN) {
984                 ap->rxconfig = 0;
985                 ap->link_time = 0;
986                 ap->cur_time = 0;
987                 ap->ability_match_cfg = 0;
988                 ap->ability_match_count = 0;
989                 ap->ability_match = 0;
990                 ap->idle_match = 0;
991                 ap->ack_match = 0;
992         }
993         ap->cur_time++;
994
995         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
996                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
997
998                 if (rx_cfg_reg != ap->ability_match_cfg) {
999                         ap->ability_match_cfg = rx_cfg_reg;
1000                         ap->ability_match = 0;
1001                         ap->ability_match_count = 0;
1002                 } else {
1003                         if (++ap->ability_match_count > 1) {
1004                                 ap->ability_match = 1;
1005                                 ap->ability_match_cfg = rx_cfg_reg;
1006                         }
1007                 }
1008                 if (rx_cfg_reg & ANEG_CFG_ACK)
1009                         ap->ack_match = 1;
1010                 else
1011                         ap->ack_match = 0;
1012
1013                 ap->idle_match = 0;
1014         } else {
1015                 ap->idle_match = 1;
1016                 ap->ability_match_cfg = 0;
1017                 ap->ability_match_count = 0;
1018                 ap->ability_match = 0;
1019                 ap->ack_match = 0;
1020
1021                 rx_cfg_reg = 0;
1022         }
1023
1024         ap->rxconfig = rx_cfg_reg;
1025         ret = ANEG_OK;
1026
1027         switch(ap->state) {
1028         case ANEG_STATE_UNKNOWN:
1029                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
1030                         ap->state = ANEG_STATE_AN_ENABLE;
1031
1032                 /* fallthru */
1033         case ANEG_STATE_AN_ENABLE:
1034                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
1035                 if (ap->flags & MR_AN_ENABLE) {
1036                         ap->link_time = 0;
1037                         ap->cur_time = 0;
1038                         ap->ability_match_cfg = 0;
1039                         ap->ability_match_count = 0;
1040                         ap->ability_match = 0;
1041                         ap->idle_match = 0;
1042                         ap->ack_match = 0;
1043
1044                         ap->state = ANEG_STATE_RESTART_INIT;
1045                 } else {
1046                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
1047                 }
1048                 break;
1049
1050         case ANEG_STATE_RESTART_INIT:
1051                 ap->link_time = ap->cur_time;
1052                 ap->flags &= ~(MR_NP_LOADED);
1053                 ap->txconfig = 0;
1054                 tw32(MAC_TX_AUTO_NEG, 0);
1055                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1056                 tw32_carefully(MAC_MODE, tp->mac_mode);
1057
1058                 ret = ANEG_TIMER_ENAB;
1059                 ap->state = ANEG_STATE_RESTART;
1060
1061                 /* fallthru */
1062         case ANEG_STATE_RESTART:
1063                 delta = ap->cur_time - ap->link_time;
1064                 if (delta > ANEG_STATE_SETTLE_TIME) {
1065                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
1066                 } else {
1067                         ret = ANEG_TIMER_ENAB;
1068                 }
1069                 break;
1070
1071         case ANEG_STATE_DISABLE_LINK_OK:
1072                 ret = ANEG_DONE;
1073                 break;
1074
1075         case ANEG_STATE_ABILITY_DETECT_INIT:
1076                 ap->flags &= ~(MR_TOGGLE_TX);
1077                 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
1078                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
1079                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1080                 tw32_carefully(MAC_MODE, tp->mac_mode);
1081
1082                 ap->state = ANEG_STATE_ABILITY_DETECT;
1083                 break;
1084
1085         case ANEG_STATE_ABILITY_DETECT:
1086                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
1087                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
1088                 }
1089                 break;
1090
1091         case ANEG_STATE_ACK_DETECT_INIT:
1092                 ap->txconfig |= ANEG_CFG_ACK;
1093                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
1094                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1095                 tw32_carefully(MAC_MODE, tp->mac_mode);
1096
1097                 ap->state = ANEG_STATE_ACK_DETECT;
1098
1099                 /* fallthru */
1100         case ANEG_STATE_ACK_DETECT:
1101                 if (ap->ack_match != 0) {
1102                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
1103                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
1104                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
1105                         } else {
1106                                 ap->state = ANEG_STATE_AN_ENABLE;
1107                         }
1108                 } else if (ap->ability_match != 0 &&
1109                            ap->rxconfig == 0) {
1110                         ap->state = ANEG_STATE_AN_ENABLE;
1111                 }
1112                 break;
1113
1114         case ANEG_STATE_COMPLETE_ACK_INIT:
1115                 if (ap->rxconfig & ANEG_CFG_INVAL) {
1116                         ret = ANEG_FAILED;
1117                         break;
1118                 }
1119                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
1120                                MR_LP_ADV_HALF_DUPLEX |
1121                                MR_LP_ADV_SYM_PAUSE |
1122                                MR_LP_ADV_ASYM_PAUSE |
1123                                MR_LP_ADV_REMOTE_FAULT1 |
1124                                MR_LP_ADV_REMOTE_FAULT2 |
1125                                MR_LP_ADV_NEXT_PAGE |
1126                                MR_TOGGLE_RX |
1127                                MR_NP_RX);
1128                 if (ap->rxconfig & ANEG_CFG_FD)
1129                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
1130                 if (ap->rxconfig & ANEG_CFG_HD)
1131                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
1132                 if (ap->rxconfig & ANEG_CFG_PS1)
1133                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
1134                 if (ap->rxconfig & ANEG_CFG_PS2)
1135                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
1136                 if (ap->rxconfig & ANEG_CFG_RF1)
1137                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
1138                 if (ap->rxconfig & ANEG_CFG_RF2)
1139                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
1140                 if (ap->rxconfig & ANEG_CFG_NP)
1141                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
1142
1143                 ap->link_time = ap->cur_time;
1144
1145                 ap->flags ^= (MR_TOGGLE_TX);
1146                 if (ap->rxconfig & 0x0008)
1147                         ap->flags |= MR_TOGGLE_RX;
1148                 if (ap->rxconfig & ANEG_CFG_NP)
1149                         ap->flags |= MR_NP_RX;
1150                 ap->flags |= MR_PAGE_RX;
1151
1152                 ap->state = ANEG_STATE_COMPLETE_ACK;
1153                 ret = ANEG_TIMER_ENAB;
1154                 break;
1155
1156         case ANEG_STATE_COMPLETE_ACK:
1157                 if (ap->ability_match != 0 &&
1158                     ap->rxconfig == 0) {
1159                         ap->state = ANEG_STATE_AN_ENABLE;
1160                         break;
1161                 }
1162                 delta = ap->cur_time - ap->link_time;
1163                 if (delta > ANEG_STATE_SETTLE_TIME) {
1164                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
1165                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
1166                         } else {
1167                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
1168                                     !(ap->flags & MR_NP_RX)) {
1169                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
1170                                 } else {
1171                                         ret = ANEG_FAILED;
1172                                 }
1173                         }
1174                 }
1175                 break;
1176
1177         case ANEG_STATE_IDLE_DETECT_INIT:
1178                 ap->link_time = ap->cur_time;
1179                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
1180                 tw32_carefully(MAC_MODE, tp->mac_mode);
1181
1182                 ap->state = ANEG_STATE_IDLE_DETECT;
1183                 ret = ANEG_TIMER_ENAB;
1184                 break;
1185
1186         case ANEG_STATE_IDLE_DETECT:
1187                 if (ap->ability_match != 0 &&
1188                     ap->rxconfig == 0) {
1189                         ap->state = ANEG_STATE_AN_ENABLE;
1190                         break;
1191                 }
1192                 delta = ap->cur_time - ap->link_time;
1193                 if (delta > ANEG_STATE_SETTLE_TIME) {
1194                         /* XXX another gem from the Broadcom driver :( */
1195                         ap->state = ANEG_STATE_LINK_OK;
1196                 }
1197                 break;
1198
1199         case ANEG_STATE_LINK_OK:
1200                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
1201                 ret = ANEG_DONE;
1202                 break;
1203
1204         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
1205                 /* ??? unimplemented */
1206                 break;
1207
1208         case ANEG_STATE_NEXT_PAGE_WAIT:
1209                 /* ??? unimplemented */
1210                 break;
1211
1212         default:
1213                 ret = ANEG_FAILED;
1214                 break;
1215         };
1216
1217         return ret;
1218 }
1219
1220 static int tg3_setup_fiber_phy(struct tg3 *tp)
1221 {
1222         uint32_t orig_pause_cfg;
1223         uint16_t orig_active_speed;
1224         uint8_t orig_active_duplex;
1225         int current_link_up;
1226         int i;
1227
1228         orig_pause_cfg =
1229                 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
1230                                   TG3_FLAG_TX_PAUSE));
1231         orig_active_speed = tp->link_config.active_speed;
1232         orig_active_duplex = tp->link_config.active_duplex;
1233
1234         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
1235         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
1236         tw32_carefully(MAC_MODE, tp->mac_mode);
1237
1238         /* Reset when initting first time or we have a link. */
1239         if (!(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) ||
1240             (tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED)) {
1241                 /* Set PLL lock range. */
1242                 tg3_writephy(tp, 0x16, 0x8007);
1243
1244                 /* SW reset */
1245                 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
1246
1247                 /* Wait for reset to complete. */
1248                 mdelay(5);
1249
1250                 /* Config mode; select PMA/Ch 1 regs. */
1251                 tg3_writephy(tp, 0x10, 0x8411);
1252
1253                 /* Enable auto-lock and comdet, select txclk for tx. */
1254                 tg3_writephy(tp, 0x11, 0x0a10);
1255
1256                 tg3_writephy(tp, 0x18, 0x00a0);
1257                 tg3_writephy(tp, 0x16, 0x41ff);
1258
1259                 /* Assert and deassert POR. */
1260                 tg3_writephy(tp, 0x13, 0x0400);
1261                 udelay(40);
1262                 tg3_writephy(tp, 0x13, 0x0000);
1263
1264                 tg3_writephy(tp, 0x11, 0x0a50);
1265                 udelay(40);
1266                 tg3_writephy(tp, 0x11, 0x0a10);
1267
1268                 /* Wait for signal to stabilize */
1269                 mdelay(150);
1270
1271                 /* Deselect the channel register so we can read the PHYID
1272                  * later.
1273                  */
1274                 tg3_writephy(tp, 0x10, 0x8011);
1275         }
1276
1277         /* Disable link change interrupt.  */
1278         tw32_carefully(MAC_EVENT, 0);
1279
1280         current_link_up = 0;
1281         if (tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED) {
1282                 if (!(tp->tg3_flags & TG3_FLAG_GOT_SERDES_FLOWCTL)) {
1283                         struct tg3_fiber_aneginfo aninfo;
1284                         int status = ANEG_FAILED;
1285                         unsigned int tick;
1286                         uint32_t tmp;
1287
1288                         memset(&aninfo, 0, sizeof(aninfo));
1289                         aninfo.flags |= (MR_AN_ENABLE);
1290
1291                         tw32(MAC_TX_AUTO_NEG, 0);
1292
1293                         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
1294                         tw32_carefully(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
1295
1296                         tw32_carefully(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
1297
1298                         aninfo.state = ANEG_STATE_UNKNOWN;
1299                         aninfo.cur_time = 0;
1300                         tick = 0;
1301                         while (++tick < 195000) {
1302                                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
1303                                 if (status == ANEG_DONE ||
1304                                     status == ANEG_FAILED)
1305                                         break;
1306
1307                                 udelay(1);
1308                         }
1309
1310                         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
1311                         tw32_carefully(MAC_MODE, tp->mac_mode);
1312
1313                         if (status == ANEG_DONE &&
1314                             (aninfo.flags &
1315                              (MR_AN_COMPLETE | MR_LINK_OK |
1316                               MR_LP_ADV_FULL_DUPLEX))) {
1317                                 uint32_t local_adv, remote_adv;
1318
1319                                 local_adv = ADVERTISE_PAUSE_CAP;
1320                                 remote_adv = 0;
1321                                 if (aninfo.flags & MR_LP_ADV_SYM_PAUSE)
1322                                         remote_adv |= LPA_PAUSE_CAP;
1323                                 if (aninfo.flags & MR_LP_ADV_ASYM_PAUSE)
1324                                         remote_adv |= LPA_PAUSE_ASYM;
1325
1326                                 tg3_setup_flow_control(tp, local_adv, remote_adv);
1327
1328                                 tp->tg3_flags |=
1329                                         TG3_FLAG_GOT_SERDES_FLOWCTL;
1330                                 current_link_up = 1;
1331                         }
1332                         for (i = 0; i < 60; i++) {
1333                                 udelay(20);
1334                                 tw32_carefully(MAC_STATUS,
1335                                         (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED));
1336                                 if ((tr32(MAC_STATUS) &
1337                                      (MAC_STATUS_SYNC_CHANGED |
1338                                       MAC_STATUS_CFG_CHANGED)) == 0)
1339                                         break;
1340                         }
1341                         if (current_link_up == 0 &&
1342                             (tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED)) {
1343                                 current_link_up = 1;
1344                         }
1345                 } else {
1346                         /* Forcing 1000FD link up. */
1347                         current_link_up = 1;
1348                 }
1349         }
1350
1351         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1352         tw32_carefully(MAC_MODE, tp->mac_mode);
1353
1354         tp->hw_status->status =
1355                 (SD_STATUS_UPDATED |
1356                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
1357
1358         for (i = 0; i < 100; i++) {
1359                 udelay(20);
1360                 tw32_carefully(MAC_STATUS,
1361                         (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED));
1362                 if ((tr32(MAC_STATUS) &
1363                      (MAC_STATUS_SYNC_CHANGED |
1364                       MAC_STATUS_CFG_CHANGED)) == 0)
1365                         break;
1366         }
1367
1368         if ((tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED) == 0)
1369                 current_link_up = 0;
1370
1371         if (current_link_up == 1) {
1372                 tp->link_config.active_speed = SPEED_1000;
1373                 tp->link_config.active_duplex = DUPLEX_FULL;
1374         } else {
1375                 tp->link_config.active_speed = SPEED_INVALID;
1376                 tp->link_config.active_duplex = DUPLEX_INVALID;
1377         }
1378
1379         if (current_link_up != tp->carrier_ok) {
1380                 tp->carrier_ok = current_link_up;
1381                 tg3_link_report(tp);
1382         } else {
1383                 uint32_t now_pause_cfg =
1384                         tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
1385                                          TG3_FLAG_TX_PAUSE);
1386                 if (orig_pause_cfg != now_pause_cfg ||
1387                     orig_active_speed != tp->link_config.active_speed ||
1388                     orig_active_duplex != tp->link_config.active_duplex)
1389                         tg3_link_report(tp);
1390         }
1391
1392         if ((tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED) == 0) {
1393                 tw32_carefully(MAC_MODE, tp->mac_mode | MAC_MODE_LINK_POLARITY);
1394                 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
1395                         tw32_carefully(MAC_MODE, tp->mac_mode);
1396                 }
1397         }
1398
1399         return 0;
1400 }
1401 #else
1402 #define tg3_setup_fiber_phy(TP) (-EINVAL)
1403 #endif /* SUPPORT_FIBER_PHY */
1404
1405 static int tg3_setup_phy(struct tg3 *tp)
1406 {
1407         int err;
1408
1409         if (tp->phy_id == PHY_ID_SERDES) {
1410                 err = tg3_setup_fiber_phy(tp);
1411         } else {
1412                 err = tg3_setup_copper_phy(tp);
1413         }
1414
1415         if (tp->link_config.active_speed == SPEED_1000 &&
1416             tp->link_config.active_duplex == DUPLEX_HALF)
1417                 tw32(MAC_TX_LENGTHS,
1418                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1419                       (6 << TX_LENGTHS_IPG_SHIFT) |
1420                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1421         else
1422                 tw32(MAC_TX_LENGTHS,
1423                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1424                       (6 << TX_LENGTHS_IPG_SHIFT) |
1425                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1426
1427         return err;
1428 }
1429
1430
1431 #define MAX_WAIT_CNT 1000
1432
1433 /* To stop a block, clear the enable bit and poll till it
1434  * clears.  
1435  */
1436 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, uint32_t enable_bit)
1437 {
1438         unsigned int i;
1439         uint32_t val;
1440
1441         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1442                 switch(ofs) {
1443                 case RCVLSC_MODE:
1444                 case DMAC_MODE:
1445                 case MBFREE_MODE:
1446                 case BUFMGR_MODE:
1447                 case MEMARB_MODE:
1448                         /* We can't enable/disable these bits of the
1449                          * 5705, just say success.
1450                          */
1451                         return 0;
1452                 default:
1453                         break;
1454                 }
1455         }
1456         val = tr32(ofs);
1457         val &= ~enable_bit;
1458         tw32(ofs, val);
1459         tr32(ofs);
1460
1461         for (i = 0; i < MAX_WAIT_CNT; i++) {
1462                 udelay(100);
1463                 val = tr32(ofs);
1464                 if ((val & enable_bit) == 0)
1465                         break;
1466         }
1467
1468         if (i == MAX_WAIT_CNT) {
1469                 printf( "tg3_stop_block timed out, ofs=%#lx enable_bit=%3lx\n",
1470                        ofs, enable_bit );
1471                 return -ENODEV;
1472         }
1473
1474         return 0;
1475 }
1476
1477 static int tg3_abort_hw(struct tg3 *tp)
1478 {
1479         int i, err;
1480
1481         tg3_disable_ints(tp);
1482
1483         tp->rx_mode &= ~RX_MODE_ENABLE;
1484         tw32_carefully(MAC_RX_MODE, tp->rx_mode);
1485
1486         err  = tg3_stop_block(tp, RCVBDI_MODE,   RCVBDI_MODE_ENABLE);
1487         err |= tg3_stop_block(tp, RCVLPC_MODE,   RCVLPC_MODE_ENABLE);
1488         err |= tg3_stop_block(tp, RCVLSC_MODE,   RCVLSC_MODE_ENABLE);
1489         err |= tg3_stop_block(tp, RCVDBDI_MODE,  RCVDBDI_MODE_ENABLE);
1490         err |= tg3_stop_block(tp, RCVDCC_MODE,   RCVDCC_MODE_ENABLE);
1491         err |= tg3_stop_block(tp, RCVCC_MODE,    RCVCC_MODE_ENABLE);
1492
1493         err |= tg3_stop_block(tp, SNDBDS_MODE,   SNDBDS_MODE_ENABLE);
1494         err |= tg3_stop_block(tp, SNDBDI_MODE,   SNDBDI_MODE_ENABLE);
1495         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1496         err |= tg3_stop_block(tp, RDMAC_MODE,    RDMAC_MODE_ENABLE);
1497         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
1498         err |= tg3_stop_block(tp, SNDBDC_MODE,   SNDBDC_MODE_ENABLE);
1499         if (err)
1500                 goto out;
1501
1502         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
1503         tw32_carefully(MAC_MODE, tp->mac_mode);
1504
1505         tp->tx_mode &= ~TX_MODE_ENABLE;
1506         tw32_carefully(MAC_TX_MODE, tp->tx_mode);
1507
1508         for (i = 0; i < MAX_WAIT_CNT; i++) {
1509                 udelay(100);
1510                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
1511                         break;
1512         }
1513         if (i >= MAX_WAIT_CNT) {
1514                 printf("tg3_abort_hw timed out TX_MODE_ENABLE will not clear MAC_TX_MODE=%x\n",
1515                         tr32(MAC_TX_MODE));
1516                 return -ENODEV;
1517         }
1518
1519         err  = tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE);
1520         err |= tg3_stop_block(tp, WDMAC_MODE,  WDMAC_MODE_ENABLE);
1521         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE);
1522
1523         tw32(FTQ_RESET, 0xffffffff);
1524         tw32(FTQ_RESET, 0x00000000);
1525
1526         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE);
1527         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE);
1528         if (err)
1529                 goto out;
1530
1531         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
1532
1533 out:
1534         return err;
1535 }
1536
1537 static void tg3_chip_reset(struct tg3 *tp)
1538 {
1539         uint32_t val;
1540
1541         if (!(tp->tg3_flags2 & TG3_FLG2_SUN_5704)) {
1542                 /* Force NVRAM to settle.
1543                  * This deals with a chip bug which can result in EEPROM
1544                  * corruption.
1545                  */
1546                 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
1547                         int i;
1548         
1549                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
1550                         for (i = 0; i < 100000; i++) {
1551                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
1552                                         break;
1553                                 udelay(10);
1554                         }
1555                 }
1556         }
1557         /* In Etherboot we don't need to worry about the 5701
1558          * REG_WRITE_BUG because we do all register writes indirectly.
1559          */
1560
1561         // Alf: here patched
1562         /* do the reset */
1563         val = GRC_MISC_CFG_CORECLK_RESET;
1564         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
1565             || (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1566                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
1567         }
1568
1569         // Alf : Please VALIDATE THIS.
1570         // It is necessary in my case (5751) to prevent a reboot, but
1571         // I have no idea about a side effect on any other version.
1572         // It appears to be what's done in tigon3.c from Broadcom
1573         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
1574           tw32(GRC_MISC_CFG, 0x20000000) ;
1575           val |= 0x20000000 ;
1576         }
1577
1578         tw32(GRC_MISC_CFG, val);
1579
1580         /* Flush PCI posted writes.  The normal MMIO registers
1581          * are inaccessible at this time so this is the only
1582          * way to make this reliably.  I tried to use indirect
1583          * register read/write but this upset some 5701 variants.
1584          */
1585         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
1586
1587         udelay(120);
1588
1589         /* Re-enable indirect register accesses. */
1590         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
1591                                tp->misc_host_ctrl);
1592
1593         /* Set MAX PCI retry to zero. */
1594         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
1595         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
1596             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
1597                 val |= PCISTATE_RETRY_SAME_DMA;
1598         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
1599
1600         pci_restore_state(tp->pdev, tp->pci_cfg_state);
1601
1602         /* Make sure PCI-X relaxed ordering bit is clear. */
1603         pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
1604         val &= ~PCIX_CAPS_RELAXED_ORDERING;
1605         pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
1606
1607         tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
1608
1609         if (((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0) &&
1610                 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
1611                 tp->pci_clock_ctrl |=
1612                         (CLOCK_CTRL_FORCE_CLKRUN | CLOCK_CTRL_CLKRUN_OENABLE);
1613                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
1614         }
1615
1616         tw32(TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
1617 }
1618
1619 static void tg3_stop_fw(struct tg3 *tp)
1620 {
1621         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
1622                 uint32_t val;
1623                 int i;
1624
1625                 tg3_write_mem(NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1626                 val = tr32(GRC_RX_CPU_EVENT);
1627                 val |= (1 << 14);
1628                 tw32(GRC_RX_CPU_EVENT, val);
1629
1630                 /* Wait for RX cpu to ACK the event.  */
1631                 for (i = 0; i < 100; i++) {
1632                         if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
1633                                 break;
1634                         udelay(1);
1635                 }
1636         }
1637 }
1638
1639 static int tg3_restart_fw(struct tg3 *tp, uint32_t state)
1640 {
1641         uint32_t val;
1642         int i;
1643         
1644         tg3_write_mem(NIC_SRAM_FIRMWARE_MBOX, 
1645                 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1646         /* Wait for firmware initialization to complete. */
1647         for (i = 0; i < 100000; i++) {
1648                 tg3_read_mem(NIC_SRAM_FIRMWARE_MBOX, &val);
1649                 if (val == (uint32_t) ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1650                         break;
1651                 udelay(10);
1652         }
1653         if (i >= 100000 &&
1654                     !(tp->tg3_flags2 & TG3_FLG2_SUN_5704)) {
1655                 printf ( "Firmware will not restart magic=%#lx\n",
1656                         val );
1657                 return -ENODEV;
1658         }
1659         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1660           state = DRV_STATE_SUSPEND;
1661         }
1662
1663         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
1664             (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)) {
1665           // Enable PCIE bug fix
1666           tg3_read_mem(0x7c00, &val);
1667           tg3_write_mem(0x7c00, val | 0x02000000);
1668         }
1669         tg3_write_mem(NIC_SRAM_FW_DRV_STATE_MBOX, state);
1670         return 0;
1671 }
1672
1673 static int tg3_halt(struct tg3 *tp)
1674 {
1675         tg3_stop_fw(tp);
1676         tg3_abort_hw(tp);
1677         tg3_chip_reset(tp);
1678         return tg3_restart_fw(tp, DRV_STATE_UNLOAD);
1679 }
1680
1681 static void __tg3_set_mac_addr(struct tg3 *tp)
1682 {
1683         uint32_t addr_high, addr_low;
1684         int i;
1685
1686         addr_high = ((tp->nic->node_addr[0] << 8) |
1687                      tp->nic->node_addr[1]);
1688         addr_low = ((tp->nic->node_addr[2] << 24) |
1689                     (tp->nic->node_addr[3] << 16) |
1690                     (tp->nic->node_addr[4] <<  8) |
1691                     (tp->nic->node_addr[5] <<  0));
1692         for (i = 0; i < 4; i++) {
1693                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
1694                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
1695         }
1696
1697         if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
1698                 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
1699                 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705)) {
1700                 for(i = 0; i < 12; i++) {
1701                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
1702                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
1703                 }
1704         }
1705         addr_high = (tp->nic->node_addr[0] +
1706                      tp->nic->node_addr[1] +
1707                      tp->nic->node_addr[2] +
1708                      tp->nic->node_addr[3] +
1709                      tp->nic->node_addr[4] +
1710                      tp->nic->node_addr[5]) &
1711                 TX_BACKOFF_SEED_MASK;
1712         tw32(MAC_TX_BACKOFF_SEED, addr_high);
1713 }
1714
1715 static void tg3_set_bdinfo(struct tg3 *tp, uint32_t bdinfo_addr,
1716                            dma_addr_t mapping, uint32_t maxlen_flags,
1717                            uint32_t nic_addr)
1718 {
1719         tg3_write_mem((bdinfo_addr +
1720                        TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
1721                       ((uint64_t) mapping >> 32));
1722         tg3_write_mem((bdinfo_addr +
1723                        TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
1724                       ((uint64_t) mapping & 0xffffffff));
1725         tg3_write_mem((bdinfo_addr +
1726                        TG3_BDINFO_MAXLEN_FLAGS),
1727                        maxlen_flags);
1728         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
1729                 tg3_write_mem((bdinfo_addr + TG3_BDINFO_NIC_ADDR), nic_addr);
1730         }
1731 }
1732
1733
1734 static void tg3_init_rings(struct tg3 *tp)
1735 {
1736         unsigned i;
1737
1738         /* Zero out the tg3 variables */
1739         memset(&tg3_bss, 0, sizeof(tg3_bss));
1740         tp->rx_std    = &tg3_bss.rx_std[0];
1741         tp->rx_rcb    = &tg3_bss.rx_rcb[0];
1742         tp->tx_ring   = &tg3_bss.tx_ring[0];
1743         tp->hw_status = &tg3_bss.hw_status;
1744         tp->hw_stats  = &tg3_bss.hw_stats;
1745         tp->mac_mode  = 0;
1746
1747
1748         /* Initialize tx/rx rings for packet processing.
1749          *
1750          * The chip has been shut down and the driver detached from
1751          * the networking, so no interrupts or new tx packets will
1752          * end up in the driver.
1753          */
1754
1755         /* Initialize invariants of the rings, we only set this
1756          * stuff once.  This works because the card does not
1757          * write into the rx buffer posting rings.
1758          */
1759         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
1760                 struct tg3_rx_buffer_desc *rxd;
1761
1762                 rxd = &tp->rx_std[i];
1763                 rxd->idx_len = (RX_PKT_BUF_SZ - 2 - 64) << RXD_LEN_SHIFT;
1764                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
1765                 rxd->opaque = (RXD_OPAQUE_RING_STD | (i << RXD_OPAQUE_INDEX_SHIFT));
1766
1767                 /* Note where the receive buffer for the ring is placed */
1768                 rxd->addr_hi = 0;
1769                 rxd->addr_lo = virt_to_bus(
1770                         &tg3_bss.rx_bufs[i%TG3_DEF_RX_RING_PENDING][2]);
1771         }
1772 }
1773
1774 #define TG3_WRITE_SETTINGS(TABLE) \
1775 do { \
1776         const uint32_t *_table, *_end; \
1777         _table = TABLE; \
1778         _end = _table + sizeof(TABLE)/sizeof(TABLE[0]);  \
1779         for(; _table < _end; _table += 2) { \
1780                 tw32(_table[0], _table[1]); \
1781         } \
1782 } while(0)
1783
1784
1785 /* initialize/reset the tg3 */
1786 static int tg3_setup_hw(struct tg3 *tp)
1787 {
1788         uint32_t val, rdmac_mode;
1789         int i, err, limit;
1790
1791         /* Simply don't support setups with extremly buggy firmware in etherboot */
1792         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
1793                 printf("Error 5701_A0 firmware bug detected\n");
1794                 return -EINVAL;
1795         }
1796
1797         tg3_disable_ints(tp);
1798
1799         /* Originally this was all in tg3_init_hw */
1800
1801         /* Force the chip into D0. */
1802         tg3_set_power_state_0(tp);
1803
1804         tg3_switch_clocks(tp);
1805
1806         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
1807
1808         // This should go somewhere else
1809 #define T3_PCIE_CAPABILITY_ID_REG           0xD0
1810 #define T3_PCIE_CAPABILITY_ID               0x10
1811 #define T3_PCIE_CAPABILITY_REG              0xD2
1812
1813         /* Originally this was all in tg3_reset_hw */
1814
1815         tg3_stop_fw(tp);
1816
1817         /* No need to call tg3_abort_hw here, it is called before tg3_setup_hw. */
1818
1819         tg3_chip_reset(tp);
1820
1821         tw32(GRC_MODE, tp->grc_mode);  /* Redundant? */
1822
1823         err = tg3_restart_fw(tp, DRV_STATE_START);
1824         if (err)
1825                 return err;
1826
1827         if (tp->phy_id == PHY_ID_SERDES) {
1828                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
1829         }
1830         tw32_carefully(MAC_MODE, tp->mac_mode);
1831
1832
1833         /* This works around an issue with Athlon chipsets on
1834          * B3 tigon3 silicon.  This bit has no effect on any
1835          * other revision.
1836          * Alf: Except 5750 ! (which reboots)
1837          */
1838
1839         if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
1840           tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
1841         tw32_carefully(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
1842
1843         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
1844             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
1845                 val = tr32(TG3PCI_PCISTATE);
1846                 val |= PCISTATE_RETRY_SAME_DMA;
1847                 tw32(TG3PCI_PCISTATE, val);
1848         }
1849
1850         /* Descriptor ring init may make accesses to the
1851          * NIC SRAM area to setup the TX descriptors, so we
1852          * can only do this after the hardware has been
1853          * successfully reset.
1854          */
1855         tg3_init_rings(tp);
1856
1857         /* Clear statistics/status block in chip */
1858         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
1859                 for (i = NIC_SRAM_STATS_BLK;
1860                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
1861                      i += sizeof(uint32_t)) {
1862                         tg3_write_mem(i, 0);
1863                         udelay(40);
1864                 }
1865         }
1866
1867         /* This value is determined during the probe time DMA
1868          * engine test, tg3_setup_dma.
1869          */
1870         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
1871
1872         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
1873                           GRC_MODE_4X_NIC_SEND_RINGS |
1874                           GRC_MODE_NO_TX_PHDR_CSUM |
1875                           GRC_MODE_NO_RX_PHDR_CSUM);
1876         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
1877         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1878         tp->grc_mode |= GRC_MODE_NO_RX_PHDR_CSUM;
1879
1880         tw32(GRC_MODE,
1881                 tp->grc_mode | 
1882                 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
1883
1884         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
1885         tw32(GRC_MISC_CFG,
1886              (65 << GRC_MISC_CFG_PRESCALAR_SHIFT));
1887
1888         /* Initialize MBUF/DESC pool. */
1889         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
1890                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
1891                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
1892                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
1893                 else
1894                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
1895                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
1896                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
1897         }
1898         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE)) {
1899                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
1900                      tp->bufmgr_config.mbuf_read_dma_low_water);
1901                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
1902                      tp->bufmgr_config.mbuf_mac_rx_low_water);
1903                 tw32(BUFMGR_MB_HIGH_WATER,
1904                      tp->bufmgr_config.mbuf_high_water);
1905         } else {
1906                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
1907                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
1908                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
1909                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
1910                 tw32(BUFMGR_MB_HIGH_WATER,
1911                      tp->bufmgr_config.mbuf_high_water_jumbo);
1912         }
1913         tw32(BUFMGR_DMA_LOW_WATER,
1914              tp->bufmgr_config.dma_low_water);
1915         tw32(BUFMGR_DMA_HIGH_WATER,
1916              tp->bufmgr_config.dma_high_water);
1917
1918         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
1919         for (i = 0; i < 2000; i++) {
1920                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
1921                         break;
1922                 udelay(10);
1923         }
1924         if (i >= 2000) {
1925                 printf("tg3_setup_hw cannot enable BUFMGR\n");
1926                 return -ENODEV;
1927         }
1928
1929         tw32(FTQ_RESET, 0xffffffff);
1930         tw32(FTQ_RESET, 0x00000000);
1931         for (i = 0; i < 2000; i++) {
1932                 if (tr32(FTQ_RESET) == 0x00000000)
1933                         break;
1934                 udelay(10);
1935         }
1936         if (i >= 2000) {
1937                 printf("tg3_setup_hw cannot reset FTQ\n");
1938                 return -ENODEV;
1939         }
1940
1941         /* Initialize TG3_BDINFO's at:
1942          *  RCVDBDI_STD_BD:     standard eth size rx ring
1943          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
1944          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
1945          *
1946          * like so:
1947          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
1948          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
1949          *                              ring attribute flags
1950          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
1951          *
1952          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
1953          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
1954          *
1955          * ??? No space allocated for mini receive ring? :(
1956          *
1957          * The size of each ring is fixed in the firmware, but the location is
1958          * configurable.
1959          */
1960         {
1961                 static const uint32_t table_all[] = {
1962                         /* Setup replenish thresholds. */
1963                         RCVBDI_STD_THRESH, TG3_DEF_RX_RING_PENDING / 8,
1964
1965                         /* Etherboot lives below 4GB */
1966                         RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, 0,
1967                         RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR, NIC_SRAM_RX_BUFFER_DESC,
1968                 };
1969                 static const uint32_t table_not_5705[] = {
1970                         /* Buffer maximum length */
1971                         RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT,
1972                         
1973                         /* Disable the mini frame rx ring */
1974                         RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,      BDINFO_FLAGS_DISABLED,
1975                         
1976                         /* Disable the jumbo frame rx ring */
1977                         RCVBDI_JUMBO_THRESH, 0,
1978                         RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, BDINFO_FLAGS_DISABLED,
1979                         
1980                         
1981                 };
1982                 TG3_WRITE_SETTINGS(table_all);
1983                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, 
1984                         virt_to_bus(tp->rx_std));
1985                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1986                         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
1987                                 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
1988                 } else {
1989                         TG3_WRITE_SETTINGS(table_not_5705);
1990                 }
1991         }
1992
1993         
1994         /* There is only one send ring on 5705, no need to explicitly
1995          * disable the others.
1996          */
1997         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
1998                 /* Clear out send RCB ring in SRAM. */
1999                 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
2000                         tg3_write_mem(i + TG3_BDINFO_MAXLEN_FLAGS, BDINFO_FLAGS_DISABLED);
2001         }
2002
2003         tp->tx_prod = 0;
2004         tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
2005         tw32_mailbox2(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
2006
2007         tg3_set_bdinfo(tp,
2008                 NIC_SRAM_SEND_RCB,
2009                 virt_to_bus(tp->tx_ring),
2010                 (TG3_TX_RING_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT),
2011                 NIC_SRAM_TX_BUFFER_DESC);
2012
2013         /* There is only one receive return ring on 5705, no need to explicitly
2014          * disable the others.
2015          */
2016         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
2017                 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK; i += TG3_BDINFO_SIZE) {
2018                         tg3_write_mem(i + TG3_BDINFO_MAXLEN_FLAGS,
2019                                 BDINFO_FLAGS_DISABLED);
2020                 }
2021         }
2022
2023         tp->rx_rcb_ptr = 0;
2024         tw32_mailbox2(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
2025
2026         tg3_set_bdinfo(tp,
2027                 NIC_SRAM_RCV_RET_RCB,
2028                 virt_to_bus(tp->rx_rcb),
2029                 (TG3_RX_RCB_RING_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT),
2030                 0);
2031
2032         tp->rx_std_ptr = TG3_DEF_RX_RING_PENDING;
2033         tw32_mailbox2(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
2034                      tp->rx_std_ptr);
2035
2036         tw32_mailbox2(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW, 0);
2037
2038         /* Initialize MAC address and backoff seed. */
2039         __tg3_set_mac_addr(tp);
2040
2041         /* Calculate RDMAC_MODE setting early, we need it to determine
2042          * the RCVLPC_STATE_ENABLE mask.
2043          */
2044         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
2045                 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
2046                 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
2047                 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
2048                 RDMAC_MODE_LNGREAD_ENAB);
2049         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
2050                 rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
2051         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2052                 if (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
2053                         if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
2054                                 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
2055                                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
2056                         }
2057                 }
2058         }
2059
2060         /* Setup host coalescing engine. */
2061         tw32(HOSTCC_MODE, 0);
2062         for (i = 0; i < 2000; i++) {
2063                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
2064                         break;
2065                 udelay(10);
2066         }
2067
2068         tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
2069                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
2070         tw32_carefully(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
2071
2072         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
2073         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
2074                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
2075                                        GRC_LCLCTRL_GPIO_OUTPUT1);
2076         tw32_carefully(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
2077
2078         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
2079         tr32(MAILBOX_INTERRUPT_0);
2080
2081         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
2082                 tw32_carefully(DMAC_MODE, DMAC_MODE_ENABLE);
2083         }
2084
2085         val = ( WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
2086                 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
2087                 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
2088                 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
2089                 WDMAC_MODE_LNGREAD_ENAB);
2090         if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) &&
2091                 ((tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) != 0) &&
2092                 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
2093                 val |= WDMAC_MODE_RX_ACCEL;
2094         }
2095         tw32_carefully(WDMAC_MODE, val);
2096
2097         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
2098                 val = tr32(TG3PCI_X_CAPS);
2099                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
2100                         val &= PCIX_CAPS_BURST_MASK;
2101                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
2102                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2103                         val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
2104                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
2105                         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
2106                                 val |= (tp->split_mode_max_reqs <<
2107                                         PCIX_CAPS_SPLIT_SHIFT);
2108                 }
2109                 tw32(TG3PCI_X_CAPS, val);
2110         }
2111
2112         tw32_carefully(RDMAC_MODE, rdmac_mode);
2113         {
2114                 static const uint32_t table_all[] = {
2115                         /* MTU + ethernet header + FCS + optional VLAN tag */
2116                         MAC_RX_MTU_SIZE, ETH_MAX_MTU + ETH_HLEN + 8,
2117                         
2118                         /* The slot time is changed by tg3_setup_phy if we
2119                          * run at gigabit with half duplex.
2120                          */
2121                         MAC_TX_LENGTHS, 
2122                         (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2123                         (6 << TX_LENGTHS_IPG_SHIFT) |
2124                         (32 << TX_LENGTHS_SLOT_TIME_SHIFT),
2125                         
2126                         /* Receive rules. */
2127                         MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS,
2128                         RCVLPC_CONFIG, 0x0181,
2129                         
2130                         /* Receive/send statistics. */
2131                         RCVLPC_STATS_ENABLE, 0xffffff,
2132                         RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE,
2133                         SNDDATAI_STATSENAB, 0xffffff,
2134                         SNDDATAI_STATSCTRL, (SNDDATAI_SCTRL_ENABLE |SNDDATAI_SCTRL_FASTUPD),
2135                         
2136                         /* Host coalescing engine */
2137                         HOSTCC_RXCOL_TICKS, 0,
2138                         HOSTCC_TXCOL_TICKS, LOW_TXCOL_TICKS,
2139                         HOSTCC_RXMAX_FRAMES, 1,
2140                         HOSTCC_TXMAX_FRAMES, LOW_RXMAX_FRAMES,
2141                         HOSTCC_RXCOAL_MAXF_INT, 1,
2142                         HOSTCC_TXCOAL_MAXF_INT, 0,
2143                         
2144                         /* Status/statistics block address. */
2145                         /* Etherboot lives below 4GB, so HIGH == 0 */
2146                         HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, 0,
2147
2148                         /* No need to enable 32byte coalesce mode. */
2149                         HOSTCC_MODE, HOSTCC_MODE_ENABLE | 0,
2150                         
2151                         RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE,
2152                         RCVLPC_MODE, RCVLPC_MODE_ENABLE,
2153                         
2154                         RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE,
2155
2156                         SNDDATAC_MODE, SNDDATAC_MODE_ENABLE,
2157                         SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE,
2158                         RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB,
2159                         RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ,
2160                         SNDDATAI_MODE, SNDDATAI_MODE_ENABLE,
2161                         SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE,
2162                         SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE,
2163                         
2164                         /* Accept all multicast frames. */
2165                         MAC_HASH_REG_0, 0xffffffff,
2166                         MAC_HASH_REG_1, 0xffffffff,
2167                         MAC_HASH_REG_2, 0xffffffff,
2168                         MAC_HASH_REG_3, 0xffffffff,
2169                 };
2170                 static const uint32_t table_not_5705[] = {
2171                         /* Host coalescing engine */
2172                         HOSTCC_RXCOAL_TICK_INT, 0,
2173                         HOSTCC_TXCOAL_TICK_INT, 0,
2174
2175                         /* Status/statistics block address. */
2176                         /* Etherboot lives below 4GB, so HIGH == 0 */
2177                         HOSTCC_STAT_COAL_TICKS, DEFAULT_STAT_COAL_TICKS,
2178                         HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, 0,
2179                         HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK,
2180                         HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK,
2181
2182                         RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE,
2183
2184                         MBFREE_MODE, MBFREE_MODE_ENABLE,
2185                 };
2186                 TG3_WRITE_SETTINGS(table_all);
2187                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
2188                         virt_to_bus(tp->hw_stats));
2189                 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
2190                         virt_to_bus(tp->hw_status));
2191                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
2192                         TG3_WRITE_SETTINGS(table_not_5705);
2193                 }
2194         }
2195
2196         tp->tx_mode = TX_MODE_ENABLE;
2197         tw32_carefully(MAC_TX_MODE, tp->tx_mode);
2198
2199         tp->rx_mode = RX_MODE_ENABLE;
2200         tw32_carefully(MAC_RX_MODE, tp->rx_mode);
2201
2202         tp->mi_mode = MAC_MI_MODE_BASE;
2203         tw32_carefully(MAC_MI_MODE, tp->mi_mode);
2204
2205         tw32(MAC_LED_CTRL, 0);
2206         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2207         if (tp->phy_id == PHY_ID_SERDES) {
2208                 tw32_carefully(MAC_RX_MODE, RX_MODE_RESET);
2209         }
2210         tp->rx_mode |= RX_MODE_KEEP_VLAN_TAG; /* drop tagged vlan packets */
2211         tw32_carefully(MAC_RX_MODE, tp->rx_mode);
2212
2213         if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
2214                 tw32(MAC_SERDES_CFG, 0x616000);
2215
2216         /* Prevent chip from dropping frames when flow control
2217          * is enabled.
2218          */
2219         tw32(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
2220         tr32(MAC_LOW_WMARK_MAX_RX_FRAME);
2221
2222         err = tg3_setup_phy(tp);
2223
2224         /* Ignore CRC stats */
2225
2226         /* Initialize receive rules. */
2227         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
2228         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
2229         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
2230         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
2231
2232         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
2233             || (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750))
2234                 limit = 8;
2235         else
2236                 limit = 16;
2237         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
2238                 limit -= 4;
2239         switch (limit) {
2240         case 16:        tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
2241         case 15:        tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
2242         case 14:        tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
2243         case 13:        tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
2244         case 12:        tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
2245         case 11:        tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
2246         case 10:        tw32(MAC_RCV_RULE_9,  0);  tw32(MAC_RCV_VALUE_9,  0);
2247         case 9:         tw32(MAC_RCV_RULE_8,  0);  tw32(MAC_RCV_VALUE_8,  0);
2248         case 8:         tw32(MAC_RCV_RULE_7,  0);  tw32(MAC_RCV_VALUE_7,  0);
2249         case 7:         tw32(MAC_RCV_RULE_6,  0);  tw32(MAC_RCV_VALUE_6,  0);
2250         case 6:         tw32(MAC_RCV_RULE_5,  0);  tw32(MAC_RCV_VALUE_5,  0);
2251         case 5:         tw32(MAC_RCV_RULE_4,  0);  tw32(MAC_RCV_VALUE_4,  0);
2252         case 4:         /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
2253         case 3:         /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
2254         case 2:
2255         case 1:
2256         default:
2257                 break;
2258         };
2259
2260         return err;
2261 }
2262
2263
2264
2265 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
2266 static void tg3_nvram_init(struct tg3 *tp)
2267 {
2268         tw32(GRC_EEPROM_ADDR,
2269              (EEPROM_ADDR_FSM_RESET |
2270               (EEPROM_DEFAULT_CLOCK_PERIOD <<
2271                EEPROM_ADDR_CLKPERD_SHIFT)));
2272
2273         mdelay(1);
2274
2275         /* Enable seeprom accesses. */
2276         tw32_carefully(GRC_LOCAL_CTRL,
2277                 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
2278
2279         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2280             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2281                 uint32_t nvcfg1 = tr32(NVRAM_CFG1);
2282
2283                 tp->tg3_flags |= TG3_FLAG_NVRAM;
2284                 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
2285                         if (nvcfg1 & NVRAM_CFG1_BUFFERED_MODE)
2286                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
2287                 } else {
2288                         nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
2289                         tw32(NVRAM_CFG1, nvcfg1);
2290                 }
2291
2292         } else {
2293                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
2294         }
2295 }
2296
2297
2298 static int tg3_nvram_read_using_eeprom(
2299         struct tg3 *tp __unused, uint32_t offset, uint32_t *val)
2300 {
2301         uint32_t tmp;
2302         int i;
2303
2304         if (offset > EEPROM_ADDR_ADDR_MASK ||
2305                 (offset % 4) != 0) {
2306                 return -EINVAL;
2307         }
2308
2309         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2310                                         EEPROM_ADDR_DEVID_MASK |
2311                                         EEPROM_ADDR_READ);
2312         tw32(GRC_EEPROM_ADDR,
2313              tmp |
2314              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2315              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2316               EEPROM_ADDR_ADDR_MASK) |
2317              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2318
2319         for (i = 0; i < 10000; i++) {
2320                 tmp = tr32(GRC_EEPROM_ADDR);
2321
2322                 if (tmp & EEPROM_ADDR_COMPLETE)
2323                         break;
2324                 udelay(100);
2325         }
2326         if (!(tmp & EEPROM_ADDR_COMPLETE)) {
2327                 return -EBUSY;
2328         }
2329
2330         *val = tr32(GRC_EEPROM_DATA);
2331         return 0;
2332 }
2333
2334 static int tg3_nvram_read(struct tg3 *tp, uint32_t offset, uint32_t *val)
2335 {
2336         int i, saw_done_clear;
2337
2338         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2339                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2340
2341         if (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED)
2342                 offset = ((offset / NVRAM_BUFFERED_PAGE_SIZE) <<
2343                           NVRAM_BUFFERED_PAGE_POS) +
2344                         (offset % NVRAM_BUFFERED_PAGE_SIZE);
2345
2346         if (offset > NVRAM_ADDR_MSK)
2347                 return -EINVAL;
2348
2349         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2350         for (i = 0; i < 1000; i++) {
2351                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2352                         break;
2353                 udelay(20);
2354         }
2355
2356         tw32(NVRAM_ADDR, offset);
2357         tw32(NVRAM_CMD,
2358              NVRAM_CMD_RD | NVRAM_CMD_GO |
2359              NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2360
2361         /* Wait for done bit to clear then set again. */
2362         saw_done_clear = 0;
2363         for (i = 0; i < 1000; i++) {
2364                 udelay(10);
2365                 if (!saw_done_clear &&
2366                     !(tr32(NVRAM_CMD) & NVRAM_CMD_DONE))
2367                         saw_done_clear = 1;
2368                 else if (saw_done_clear &&
2369                          (tr32(NVRAM_CMD) & NVRAM_CMD_DONE))
2370                         break;
2371         }
2372         if (i >= 1000) {
2373                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2374                 return -EBUSY;
2375         }
2376
2377         *val = bswap_32(tr32(NVRAM_RDDATA));
2378         tw32(NVRAM_SWARB, 0x20);
2379
2380         return 0;
2381 }
2382
2383 struct subsys_tbl_ent {
2384         uint16_t subsys_vendor, subsys_devid;
2385         uint32_t phy_id;
2386 };
2387
2388 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
2389         /* Broadcom boards. */
2390         { 0x14e4, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
2391         { 0x14e4, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
2392         { 0x14e4, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
2393         { 0x14e4, 0x0003, PHY_ID_SERDES  }, /* BCM95700A9 */
2394         { 0x14e4, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
2395         { 0x14e4, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
2396         { 0x14e4, 0x0007, PHY_ID_SERDES  }, /* BCM95701A7 */
2397         { 0x14e4, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
2398         { 0x14e4, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
2399         { 0x14e4, 0x0009, PHY_ID_BCM5701 }, /* BCM95703Ax1 */
2400         { 0x14e4, 0x8009, PHY_ID_BCM5701 }, /* BCM95703Ax2 */
2401
2402         /* 3com boards. */
2403         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
2404         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
2405         /* { PCI_VENDOR_ID_3COM, 0x1002, PHY_ID_XXX },     3C996CT */
2406         /* { PCI_VENDOR_ID_3COM, 0x1003, PHY_ID_XXX },     3C997T */
2407         { PCI_VENDOR_ID_3COM, 0x1004, PHY_ID_SERDES  }, /* 3C996SX */
2408         /* { PCI_VENDOR_ID_3COM, 0x1005, PHY_ID_XXX },     3C997SZ */
2409         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
2410         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
2411
2412         /* DELL boards. */
2413         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
2414         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
2415         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
2416         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
2417         { PCI_VENDOR_ID_DELL, 0x0179, PHY_ID_BCM5751 }, /* EtherXpress */
2418         
2419         /* Fujitsu Siemens Computer */
2420         { PCI_VENDOR_ID_FSC, 0x105d, PHY_ID_BCM5751 }, /* Futro C200 */ 
2421
2422         /* Compaq boards. */
2423         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
2424         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
2425         { PCI_VENDOR_ID_COMPAQ, 0x007d, PHY_ID_SERDES  }, /* CHANGELING */
2426         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
2427         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }  /* NC7780_2 */
2428 };
2429
2430 static int tg3_phy_probe(struct tg3 *tp)
2431 {
2432         uint32_t eeprom_phy_id, hw_phy_id_1, hw_phy_id_2;
2433         uint32_t hw_phy_id, hw_phy_id_masked;
2434         enum phy_led_mode eeprom_led_mode;
2435         uint32_t val;
2436         unsigned i;
2437         int eeprom_signature_found, err;
2438
2439         tp->phy_id = PHY_ID_INVALID;
2440
2441         for (i = 0; i < sizeof(subsys_id_to_phy_id)/sizeof(subsys_id_to_phy_id[0]); i++) {
2442                 if ((subsys_id_to_phy_id[i].subsys_vendor == tp->subsystem_vendor) &&
2443                         (subsys_id_to_phy_id[i].subsys_devid == tp->subsystem_device)) {
2444                         tp->phy_id = subsys_id_to_phy_id[i].phy_id;
2445                         break;
2446                 }
2447         }
2448
2449         eeprom_phy_id = PHY_ID_INVALID;
2450         eeprom_led_mode = led_mode_auto;
2451         eeprom_signature_found = 0;
2452         tg3_read_mem(NIC_SRAM_DATA_SIG, &val);
2453         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
2454                 uint32_t nic_cfg;
2455
2456                 tg3_read_mem(NIC_SRAM_DATA_CFG, &nic_cfg);
2457                 tp->nic_sram_data_cfg = nic_cfg;
2458
2459                 eeprom_signature_found = 1;
2460
2461                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
2462                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER) {
2463                         eeprom_phy_id = PHY_ID_SERDES;
2464                 } else {
2465                         uint32_t nic_phy_id;
2466
2467                         tg3_read_mem(NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
2468                         if (nic_phy_id != 0) {
2469                                 uint32_t id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
2470                                 uint32_t id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
2471
2472                                 eeprom_phy_id  = (id1 >> 16) << 10;
2473                                 eeprom_phy_id |= (id2 & 0xfc00) << 16;
2474                                 eeprom_phy_id |= (id2 & 0x03ff) <<  0;
2475                         }
2476                 }
2477
2478                 switch (nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK) {
2479                 case NIC_SRAM_DATA_CFG_LED_TRIPLE_SPD:
2480                         eeprom_led_mode = led_mode_three_link;
2481                         break;
2482
2483                 case NIC_SRAM_DATA_CFG_LED_LINK_SPD:
2484                         eeprom_led_mode = led_mode_link10;
2485                         break;
2486
2487                 default:
2488                         eeprom_led_mode = led_mode_auto;
2489                         break;
2490                 };
2491                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) ||
2492                         (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
2493                         (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) &&
2494                         (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP)) {
2495                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
2496                 }
2497
2498                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE)
2499                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
2500                 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
2501                         tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
2502         }
2503
2504         /* Now read the physical PHY_ID from the chip and verify
2505          * that it is sane.  If it doesn't look good, we fall back
2506          * to either the hard-coded table based PHY_ID and failing
2507          * that the value found in the eeprom area.
2508          */
2509         err  = tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
2510         err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
2511
2512         hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
2513         hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
2514         hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
2515
2516         hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
2517
2518         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
2519                 tp->phy_id = hw_phy_id;
2520         } else {
2521                 /* phy_id currently holds the value found in the
2522                  * subsys_id_to_phy_id[] table or PHY_ID_INVALID
2523                  * if a match was not found there.
2524                  */
2525                 if (tp->phy_id == PHY_ID_INVALID) {
2526                         if (!eeprom_signature_found ||
2527                             !KNOWN_PHY_ID(eeprom_phy_id & PHY_ID_MASK))
2528                                 return -ENODEV;
2529                         tp->phy_id = eeprom_phy_id;
2530                 }
2531         }
2532
2533         err = tg3_phy_reset(tp);
2534         if (err)
2535                 return err;
2536
2537         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2538             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
2539                 uint32_t mii_tg3_ctrl;
2540                 
2541                 /* These chips, when reset, only advertise 10Mb
2542                  * capabilities.  Fix that.
2543                  */
2544                 err  = tg3_writephy(tp, MII_ADVERTISE,
2545                                     (ADVERTISE_CSMA |
2546                                      ADVERTISE_PAUSE_CAP |
2547                                      ADVERTISE_10HALF |
2548                                      ADVERTISE_10FULL |
2549                                      ADVERTISE_100HALF |
2550                                      ADVERTISE_100FULL));
2551                 mii_tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
2552                                 MII_TG3_CTRL_ADV_1000_FULL |
2553                                 MII_TG3_CTRL_AS_MASTER |
2554                                 MII_TG3_CTRL_ENABLE_AS_MASTER);
2555                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2556                         mii_tg3_ctrl = 0;
2557
2558                 err |= tg3_writephy(tp, MII_TG3_CTRL, mii_tg3_ctrl);
2559                 err |= tg3_writephy(tp, MII_BMCR,
2560                                     (BMCR_ANRESTART | BMCR_ANENABLE));
2561         }
2562
2563         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
2564                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2565                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2566                 tg3_writedsp(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
2567         }
2568
2569         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2570                 tg3_writephy(tp, 0x1c, 0x8d68);
2571                 tg3_writephy(tp, 0x1c, 0x8d68);
2572         }
2573
2574         /* Enable Ethernet@WireSpeed */
2575         tg3_phy_set_wirespeed(tp);
2576
2577         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
2578                 err = tg3_init_5401phy_dsp(tp);
2579         }
2580
2581         /* Determine the PHY led mode. 
2582          * Be careful if this gets set wrong it can result in an inability to 
2583          * establish a link.
2584          */
2585         if (tp->phy_id == PHY_ID_SERDES) {
2586                 tp->led_mode = led_mode_three_link;
2587         }
2588         else if (tp->subsystem_vendor == PCI_VENDOR_ID_DELL) {
2589                 tp->led_mode = led_mode_link10;
2590         } else {
2591                 tp->led_mode = led_mode_three_link;
2592                 if (eeprom_signature_found &&
2593                     eeprom_led_mode != led_mode_auto)
2594                         tp->led_mode = eeprom_led_mode;
2595         }
2596
2597         if (tp->phy_id == PHY_ID_SERDES)
2598                 tp->link_config.advertising =
2599                         (ADVERTISED_1000baseT_Half |
2600                          ADVERTISED_1000baseT_Full |
2601                          ADVERTISED_Autoneg |
2602                          ADVERTISED_FIBRE);
2603         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2604                 tp->link_config.advertising &=
2605                         ~(ADVERTISED_1000baseT_Half |
2606                           ADVERTISED_1000baseT_Full);
2607
2608         return err;
2609 }
2610
2611 #if SUPPORT_PARTNO_STR
2612 static void tg3_read_partno(struct tg3 *tp)
2613 {
2614         unsigned char vpd_data[256];
2615         int i;
2616
2617         for (i = 0; i < 256; i += 4) {
2618                 uint32_t tmp;
2619
2620                 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
2621                         goto out_not_found;
2622
2623                 vpd_data[i + 0] = ((tmp >>  0) & 0xff);
2624                 vpd_data[i + 1] = ((tmp >>  8) & 0xff);
2625                 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
2626                 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
2627         }
2628
2629         /* Now parse and find the part number. */
2630         for (i = 0; i < 256; ) {
2631                 unsigned char val = vpd_data[i];
2632                 int block_end;
2633
2634                 if (val == 0x82 || val == 0x91) {
2635                         i = (i + 3 +
2636                              (vpd_data[i + 1] +
2637                               (vpd_data[i + 2] << 8)));
2638                         continue;
2639                 }
2640
2641                 if (val != 0x90)
2642                         goto out_not_found;
2643
2644                 block_end = (i + 3 +
2645                              (vpd_data[i + 1] +
2646                               (vpd_data[i + 2] << 8)));
2647                 i += 3;
2648                 while (i < block_end) {
2649                         if (vpd_data[i + 0] == 'P' &&
2650                             vpd_data[i + 1] == 'N') {
2651                                 int partno_len = vpd_data[i + 2];
2652
2653                                 if (partno_len > 24)
2654                                         goto out_not_found;
2655
2656                                 memcpy(tp->board_part_number,
2657                                        &vpd_data[i + 3],
2658                                        partno_len);
2659
2660                                 /* Success. */
2661                                 return;
2662                         }
2663                 }
2664
2665                 /* Part number not found. */
2666                 goto out_not_found;
2667         }
2668
2669 out_not_found:
2670         memcpy(tp->board_part_number, "none", sizeof("none"));
2671 }
2672 #else
2673 #define tg3_read_partno(TP) ((TP)->board_part_number[0] = '\0')
2674 #endif
2675
2676 static int tg3_get_invariants(struct tg3 *tp)
2677 {
2678         uint32_t misc_ctrl_reg;
2679         uint32_t pci_state_reg, grc_misc_cfg;
2680         uint16_t pci_cmd;
2681         uint8_t  pci_latency;
2682         uint32_t val ;
2683         int err;
2684
2685         /* Read the subsystem vendor and device ids */
2686         pci_read_config_word(tp->pdev, PCI_SUBSYSTEM_VENDOR_ID, &tp->subsystem_vendor);
2687         pci_read_config_word(tp->pdev, PCI_SUBSYSTEM_ID, &tp->subsystem_device);
2688
2689         /* The sun_5704 code needs infrastructure etherboot does have
2690          * ignore it for now.
2691          */
2692
2693         /* If we have an AMD 762 or Intel ICH/ICH0 chipset, write
2694          * reordering to the mailbox registers done by the host
2695          * controller can cause major troubles.  We read back from
2696          * every mailbox register write to force the writes to be
2697          * posted to the chip in order.
2698          *
2699          * TG3_FLAG_MBOX_WRITE_REORDER has been forced on.
2700          */
2701
2702         /* Force memory write invalidate off.  If we leave it on,
2703          * then on 5700_BX chips we have to enable a workaround.
2704          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundry
2705          * to match the cacheline size.  The Broadcom driver have this
2706          * workaround but turns MWI off all the times so never uses
2707          * it.  This seems to suggest that the workaround is insufficient.
2708          */
2709         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
2710         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
2711         /* Also, force SERR#/PERR# in PCI command. */
2712         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
2713         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
2714
2715         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
2716          * has the register indirect write enable bit set before
2717          * we try to access any of the MMIO registers.  It is also
2718          * critical that the PCI-X hw workaround situation is decided
2719          * before that as well.
2720          */
2721         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, &misc_ctrl_reg);
2722
2723         tp->pci_chip_rev_id = (misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT);
2724
2725         /* Initialize misc host control in PCI block. */
2726         tp->misc_host_ctrl |= (misc_ctrl_reg &
2727                                MISC_HOST_CTRL_CHIPREV);
2728         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
2729                                tp->misc_host_ctrl);
2730
2731         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, &pci_latency);
2732         if (pci_latency < 64) {
2733                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, 64);
2734         }
2735
2736         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &pci_state_reg);
2737
2738         /* If this is a 5700 BX chipset, and we are in PCI-X
2739          * mode, enable register write workaround.
2740          *
2741          * The workaround is to use indirect register accesses
2742          * for all chip writes not to mailbox registers.
2743          *
2744          * In etherboot to simplify things we just always use this work around.
2745          */
2746         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
2747                 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
2748         }
2749         /* Back to back register writes can cause problems on the 5701,
2750          * the workaround is to read back all reg writes except those to
2751          * mailbox regs.
2752          * In etherboot we always use indirect register accesses so
2753          * we don't see this.
2754          */
2755
2756         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
2757                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
2758         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
2759                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
2760
2761         /* Chip-specific fixup from Broadcom driver */
2762         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
2763             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
2764                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
2765                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
2766         }
2767
2768         /* determine if it is PCIE system */
2769         // Alf : I have no idea what this is about...
2770         // But it's definitely usefull
2771         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
2772           val = tr32(TG3PCI_MSI_CAP_ID) ;
2773           if (((val >> 8) & 0xff) == T3_PCIE_CAPABILITY_ID_REG) {
2774             val = tr32(T3_PCIE_CAPABILITY_ID_REG) ;
2775             if ((val & 0xff) == T3_PCIE_CAPABILITY_ID) {
2776               tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS ;
2777             }
2778           }
2779         }
2780
2781         /* Force the chip into D0. */
2782         tg3_set_power_state_0(tp);
2783
2784         /* Etherboot does not ask the tg3 to do checksums */
2785         /* Etherboot does not ask the tg3 to do jumbo frames */
2786         /* Ehterboot does not ask the tg3 to use WakeOnLan. */
2787
2788         /* A few boards don't want Ethernet@WireSpeed phy feature */
2789         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
2790             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
2791                 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2792                         (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
2793                         (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1))) {
2794                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
2795         }
2796
2797         /* Avoid tagged irq status etherboot does not use irqs */
2798
2799         /* Only 5701 and later support tagged irq status mode.
2800          * Also, 5788 chips cannot use tagged irq status.
2801          *
2802          * However, since etherboot does not use irqs avoid tagged irqs
2803          * status  because the interrupt condition is more difficult to
2804          * fully clear in that mode.
2805          */
2806         
2807         /* Since some 5700_AX && 5700_BX have problems with 32BYTE
2808          * coalesce_mode, and the rest work fine anything set.
2809          * Don't enable HOST_CC_MODE_32BYTE in etherboot.
2810          */
2811
2812         /* Initialize MAC MI mode, polling disabled. */
2813         tw32_carefully(MAC_MI_MODE, tp->mi_mode);
2814
2815         /* Initialize data/descriptor byte/word swapping. */
2816         tw32(GRC_MODE, tp->grc_mode);
2817
2818         tg3_switch_clocks(tp);
2819
2820         /* Clear this out for sanity. */
2821         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
2822
2823         /* Etherboot does not need to check if the PCIX_TARGET_HWBUG
2824          * is needed.  It always uses it.
2825          */
2826         
2827         udelay(50);
2828         tg3_nvram_init(tp);
2829
2830         /* The TX descriptors will reside in main memory.
2831          */
2832
2833         /* See which board we are using.
2834          */
2835         grc_misc_cfg = tr32(GRC_MISC_CFG);
2836         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
2837
2838         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
2839             grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5704CIOBE) {
2840                 tp->tg3_flags |= TG3_FLAG_SPLIT_MODE;
2841                 tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ;
2842         }
2843
2844         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
2845             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
2846              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
2847                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
2848
2849 #define PCI_DEVICE_ID_TIGON3_5901       0x170d
2850 #define PCI_DEVICE_ID_TIGON3_5901_2     0x170e
2851
2852         /* these are limited to 10/100 only */
2853         if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) &&
2854                     ((grc_misc_cfg == 0x8000) || (grc_misc_cfg == 0x4000))) ||
2855                 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2856                         (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM) &&
2857                         ((tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901) ||
2858                                 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2)))) {
2859                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
2860         }
2861
2862         err = tg3_phy_probe(tp);
2863         if (err) {
2864                 printf("phy probe failed, err %d\n", err);
2865         }
2866
2867         tg3_read_partno(tp);
2868
2869
2870         /* 5700 BX chips need to have their TX producer index mailboxes
2871          * written twice to workaround a bug.
2872          * In etherboot we do this unconditionally to simplify things.
2873          */
2874
2875         /* 5700 chips can get confused if TX buffers straddle the
2876          * 4GB address boundary in some cases.
2877          * 
2878          * In etherboot we can ignore the problem as etherboot lives below 4GB.
2879          */
2880
2881         /* In etherboot wake-on-lan is unconditionally disabled */
2882         return err;
2883 }
2884
2885 static int  tg3_get_device_address(struct tg3 *tp)
2886 {
2887         struct nic *nic = tp->nic;
2888         uint32_t hi, lo, mac_offset;
2889
2890         if (PCI_FUNC(tp->pdev->devfn) == 0)
2891                 mac_offset = 0x7c;
2892         else
2893                 mac_offset = 0xcc;
2894
2895         /* First try to get it from MAC address mailbox. */
2896         tg3_read_mem(NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
2897         if ((hi >> 16) == 0x484b) {
2898                 nic->node_addr[0] = (hi >>  8) & 0xff;
2899                 nic->node_addr[1] = (hi >>  0) & 0xff;
2900
2901                 tg3_read_mem(NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
2902                 nic->node_addr[2] = (lo >> 24) & 0xff;
2903                 nic->node_addr[3] = (lo >> 16) & 0xff;
2904                 nic->node_addr[4] = (lo >>  8) & 0xff;
2905                 nic->node_addr[5] = (lo >>  0) & 0xff;
2906         }
2907         /* Next, try NVRAM. */
2908         else if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
2909                  !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
2910                 nic->node_addr[0] = ((hi >> 16) & 0xff);
2911                 nic->node_addr[1] = ((hi >> 24) & 0xff);
2912                 nic->node_addr[2] = ((lo >>  0) & 0xff);
2913                 nic->node_addr[3] = ((lo >>  8) & 0xff);
2914                 nic->node_addr[4] = ((lo >> 16) & 0xff);
2915                 nic->node_addr[5] = ((lo >> 24) & 0xff);
2916         }
2917         /* Finally just fetch it out of the MAC control regs. */
2918         else {
2919                 hi = tr32(MAC_ADDR_0_HIGH);
2920                 lo = tr32(MAC_ADDR_0_LOW);
2921
2922                 nic->node_addr[5] = lo & 0xff;
2923                 nic->node_addr[4] = (lo >> 8) & 0xff;
2924                 nic->node_addr[3] = (lo >> 16) & 0xff;
2925                 nic->node_addr[2] = (lo >> 24) & 0xff;
2926                 nic->node_addr[1] = hi & 0xff;
2927                 nic->node_addr[0] = (hi >> 8) & 0xff;
2928         }
2929
2930         return 0;
2931 }
2932
2933
2934 static int tg3_setup_dma(struct tg3 *tp)
2935 {
2936         tw32(TG3PCI_CLOCK_CTRL, 0);
2937
2938         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) == 0) {
2939                 tp->dma_rwctrl =
2940                         (0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
2941                         (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT) |
2942                         (0x7 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
2943                         (0x7 << DMA_RWCTRL_READ_WATER_SHIFT) |
2944                         (0x0f << DMA_RWCTRL_MIN_DMA_SHIFT);
2945                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2946                         tp->dma_rwctrl &= ~(DMA_RWCTRL_MIN_DMA << DMA_RWCTRL_MIN_DMA_SHIFT);
2947                 }
2948         } else {
2949                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
2950                         tp->dma_rwctrl =
2951                                 (0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
2952                                 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT) |
2953                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
2954                                 (0x7 << DMA_RWCTRL_READ_WATER_SHIFT) |
2955                                 (0x00 << DMA_RWCTRL_MIN_DMA_SHIFT);
2956                 else
2957                         tp->dma_rwctrl =
2958                                 (0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
2959                                 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT) |
2960                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
2961                                 (0x3 << DMA_RWCTRL_READ_WATER_SHIFT) |
2962                                 (0x0f << DMA_RWCTRL_MIN_DMA_SHIFT);
2963
2964                 /* Wheee, some more chip bugs... */
2965                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) ||
2966                         (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)) {
2967                         uint32_t ccval = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
2968
2969                         if ((ccval == 0x6) || (ccval == 0x7)) {
2970                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
2971                         }
2972                 }
2973         }
2974
2975         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) ||
2976                 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)) {
2977                 tp->dma_rwctrl &= ~(DMA_RWCTRL_MIN_DMA << DMA_RWCTRL_MIN_DMA_SHIFT);
2978         }
2979
2980         /*
2981           Alf : Tried that, but it does not work. Should be this way though :-(
2982         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
2983           tp->dma_rwctrl |= 0x001f0000;
2984         }
2985         */
2986         tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
2987
2988         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
2989
2990         return 0;
2991 }
2992
2993 static void tg3_init_link_config(struct tg3 *tp)
2994 {
2995         tp->link_config.advertising =
2996                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2997                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
2998                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
2999                  ADVERTISED_Autoneg | ADVERTISED_MII);
3000         tp->carrier_ok = 0;
3001         tp->link_config.active_speed = SPEED_INVALID;
3002         tp->link_config.active_duplex = DUPLEX_INVALID;
3003 }
3004
3005
3006 #if SUPPORT_PHY_STR
3007 static const char * tg3_phy_string(struct tg3 *tp)
3008 {
3009         switch (tp->phy_id & PHY_ID_MASK) {
3010         case PHY_ID_BCM5400:    return "5400";
3011         case PHY_ID_BCM5401:    return "5401";
3012         case PHY_ID_BCM5411:    return "5411";
3013         case PHY_ID_BCM5701:    return "5701";
3014         case PHY_ID_BCM5703:    return "5703";
3015         case PHY_ID_BCM5704:    return "5704";
3016         case PHY_ID_BCM5705:    return "5705";
3017         case PHY_ID_BCM5750:    return "5750";
3018         case PHY_ID_BCM5751:    return "5751"; 
3019         case PHY_ID_BCM8002:    return "8002/serdes";
3020         case PHY_ID_SERDES:     return "serdes";
3021         default:                return "unknown";
3022         };
3023 }
3024 #else
3025 #define tg3_phy_string(TP) "?"
3026 #endif
3027
3028
3029 static void tg3_poll_link(struct tg3 *tp)
3030 {
3031         uint32_t mac_stat;
3032
3033         mac_stat = tr32(MAC_STATUS);
3034         if (tp->phy_id == PHY_ID_SERDES) {
3035                 if (tp->carrier_ok?
3036                         (mac_stat & MAC_STATUS_LNKSTATE_CHANGED):
3037                         (mac_stat & MAC_STATUS_PCS_SYNCED)) {
3038                         tw32_carefully(MAC_MODE, tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK);
3039                         tw32_carefully(MAC_MODE, tp->mac_mode);
3040
3041                         tg3_setup_phy(tp);
3042                 }
3043         }
3044         else {
3045                 if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED) {
3046                         tg3_setup_phy(tp);
3047                 }
3048         }
3049 }
3050
3051 /**************************************************************************
3052 POLL - Wait for a frame
3053 ***************************************************************************/
3054 static void tg3_ack_irqs(struct tg3 *tp)
3055 {
3056         if (tp->hw_status->status & SD_STATUS_UPDATED) {
3057                 /*
3058                  * writing any value to intr-mbox-0 clears PCI INTA# and
3059                  * chip-internal interrupt pending events.
3060                  * writing non-zero to intr-mbox-0 additional tells the
3061                  * NIC to stop sending us irqs, engaging "in-intr-handler"
3062                  * event coalescing.
3063                  */
3064                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 
3065                         0x00000001);
3066                 /*
3067                  * Flush PCI write.  This also guarantees that our
3068                  * status block has been flushed to host memory.
3069                  */
3070                 tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
3071                 tp->hw_status->status &= ~SD_STATUS_UPDATED;
3072         }
3073 }
3074
3075 static int tg3_poll(struct nic *nic, int retrieve)
3076 {
3077         /* return true if there's an ethernet packet ready to read */
3078         /* nic->packet should contain data on return */
3079         /* nic->packetlen should contain length of data */
3080
3081         struct tg3 *tp = &tg3;
3082         int result;
3083
3084         result = 0;
3085
3086         if ( (tp->hw_status->idx[0].rx_producer != tp->rx_rcb_ptr) && !retrieve ) 
3087           return 1;
3088
3089         tg3_ack_irqs(tp);
3090
3091         if (tp->hw_status->idx[0].rx_producer != tp->rx_rcb_ptr) {
3092                 struct tg3_rx_buffer_desc *desc;
3093                 unsigned int len;
3094                 desc = &tp->rx_rcb[tp->rx_rcb_ptr];
3095                 if ((desc->opaque & RXD_OPAQUE_RING_MASK) == RXD_OPAQUE_RING_STD) {
3096                         len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3097                         
3098                         nic->packetlen = len;
3099                         memcpy(nic->packet, bus_to_virt(desc->addr_lo), len);
3100                         result = 1;
3101                 }
3102                 tp->rx_rcb_ptr = (tp->rx_rcb_ptr + 1) % TG3_RX_RCB_RING_SIZE;
3103                 
3104                 /* ACK the status ring */
3105                 tw32_mailbox2(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, tp->rx_rcb_ptr);
3106
3107                 /* Refill RX ring. */
3108                 if (result) {
3109                         tp->rx_std_ptr = (tp->rx_std_ptr + 1) % TG3_RX_RING_SIZE;
3110                         tw32_mailbox2(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW, tp->rx_std_ptr);
3111                 }
3112         }
3113         tg3_poll_link(tp);
3114         return result;
3115 }
3116
3117 /**************************************************************************
3118 TRANSMIT - Transmit a frame
3119 ***************************************************************************/
3120 #if 0
3121 static void tg3_set_txd(struct tg3 *tp, int entry,
3122         dma_addr_t mapping, int len, uint32_t flags,
3123         uint32_t mss_and_is_end)
3124 {
3125         struct tg3_tx_buffer_desc *txd =  &tp->tx_ring[entry];
3126         int is_end = (mss_and_is_end & 0x1);
3127         if (is_end) {
3128                 flags |= TXD_FLAG_END;
3129         }
3130
3131         txd->addr_hi   = 0;
3132         txd->addr_lo   = mapping & 0xffffffff;
3133         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3134         txd->vlan_tag  = 0 << TXD_VLAN_TAG_SHIFT;
3135 }
3136 #endif
3137
3138 static void tg3_transmit(struct nic *nic, const char *dst_addr,
3139         unsigned int type, unsigned int size, const char *packet)
3140 {
3141         static int frame_idx;
3142         struct eth_frame *frame;
3143         
3144         /* send the packet to destination */
3145         struct tg3_tx_buffer_desc *txd;
3146         struct tg3 *tp;
3147         uint32_t entry;
3148         int i;
3149
3150         /* Wait until there is a free packet frame */
3151         tp = &tg3;
3152         i = 0;
3153         entry = tp->tx_prod;
3154         while((tp->hw_status->idx[0].tx_consumer != entry) &&
3155                 (tp->hw_status->idx[0].tx_consumer != PREV_TX(entry))) {
3156                 mdelay(10);     /* give the nick a chance */
3157                 if (++i > 500) { /* timeout 5s for transmit */
3158                         printf("transmit timed out\n");
3159                         tg3_halt(tp);
3160                         tg3_setup_hw(tp);
3161                         return;
3162                 }
3163         }
3164         if (i != 0) {
3165                 printf("#");
3166         }
3167         
3168         /* Copy the packet to the our local buffer */
3169         frame = &tg3_bss.tx_frame[frame_idx];
3170         memcpy(frame[frame_idx].dst_addr, dst_addr, ETH_ALEN);
3171         memcpy(frame[frame_idx].src_addr, nic->node_addr, ETH_ALEN);
3172         frame[frame_idx].type = htons(type);
3173         memset(frame[frame_idx].data, 0, sizeof(frame[frame_idx].data));
3174         memcpy(frame[frame_idx].data, packet, size);
3175
3176         /* Setup the ring buffer entry to transmit */
3177         txd            = &tp->tx_ring[entry];
3178         txd->addr_hi   = 0; /* Etherboot runs under 4GB */
3179         txd->addr_lo   = virt_to_bus(&frame[frame_idx]);
3180         txd->len_flags = ((size + ETH_HLEN) << TXD_LEN_SHIFT) | TXD_FLAG_END;
3181         txd->vlan_tag  = 0 << TXD_VLAN_TAG_SHIFT;
3182
3183         /* Advance to the next entry */
3184         entry = NEXT_TX(entry);
3185         frame_idx ^= 1;
3186
3187         /* Packets are ready, update Tx producer idx local and on card */
3188         tw32_mailbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3189         tw32_mailbox2((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3190         tp->tx_prod = entry;
3191 }
3192
3193 /**************************************************************************
3194 DISABLE - Turn off ethernet interface
3195 ***************************************************************************/
3196 static void tg3_disable ( struct nic *nic __unused ) {
3197         struct tg3 *tp = &tg3;
3198         /* put the card in its initial state */
3199         /* This function serves 3 purposes.
3200          * This disables DMA and interrupts so we don't receive
3201          *  unexpected packets or interrupts from the card after
3202          *  etherboot has finished. 
3203          * This frees resources so etherboot may use
3204          *  this driver on another interface
3205          * This allows etherboot to reinitialize the interface
3206          *  if something is something goes wrong.
3207          */
3208         tg3_halt(tp);
3209         tp->tg3_flags &= ~(TG3_FLAG_INIT_COMPLETE|TG3_FLAG_GOT_SERDES_FLOWCTL);
3210         tp->carrier_ok = 0;
3211         iounmap((void *)tp->regs);
3212 }
3213
3214 /**************************************************************************
3215 IRQ - Enable, Disable, or Force interrupts
3216 ***************************************************************************/
3217 static void tg3_irq(struct nic *nic __unused, irq_action_t action __unused)
3218 {
3219   switch ( action ) {
3220   case DISABLE :
3221     break;
3222   case ENABLE :
3223     break;
3224   case FORCE :
3225     break;
3226   }
3227 }
3228
3229 static struct nic_operations tg3_operations = {
3230         .connect        = dummy_connect,
3231         .poll           = tg3_poll,
3232         .transmit       = tg3_transmit,
3233         .irq            = tg3_irq,
3234
3235 };
3236
3237 /**************************************************************************
3238 PROBE - Look for an adapter, this routine's visible to the outside
3239 You should omit the last argument struct pci_device * for a non-PCI NIC
3240 ***************************************************************************/
3241 static int tg3_probe ( struct nic *nic, struct pci_device *pdev ) {
3242
3243         struct tg3 *tp = &tg3;
3244         unsigned long tg3reg_base, tg3reg_len;
3245         int i, err, pm_cap;
3246
3247         memset(tp, 0, sizeof(*tp));
3248
3249         adjust_pci_device(pdev);
3250
3251         pci_fill_nic ( nic, pdev );
3252         nic->irqno  = 0;
3253
3254         /* Find power-management capability. */
3255         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3256         if (pm_cap == 0) {
3257                 printf("Cannot find PowerManagement capability, aborting.\n");
3258                 return 0;
3259         }
3260         tg3reg_base = pci_bar_start(pdev, PCI_BASE_ADDRESS_0);
3261         if (tg3reg_base == -1UL) {
3262                 printf("Unuseable bar\n");
3263                 return 0;
3264         }
3265         tg3reg_len  = pci_bar_size(pdev,  PCI_BASE_ADDRESS_0);
3266
3267         tp->pdev       = pdev;
3268         tp->nic        = nic;
3269         tp->pm_cap     = pm_cap;
3270         tp->rx_mode    = 0;
3271         tp->tx_mode    = 0;
3272         tp->mi_mode    = MAC_MI_MODE_BASE;
3273         tp->tg3_flags  = 0 & ~TG3_FLAG_INIT_COMPLETE; 
3274         
3275         /* The word/byte swap controls here control register access byte
3276          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
3277          * setting below.
3278          */
3279         tp->misc_host_ctrl =
3280                 MISC_HOST_CTRL_MASK_PCI_INT |
3281                 MISC_HOST_CTRL_WORD_SWAP |
3282                 MISC_HOST_CTRL_INDIR_ACCESS |
3283                 MISC_HOST_CTRL_PCISTATE_RW;
3284
3285         /* The NONFRM (non-frame) byte/word swap controls take effect
3286          * on descriptor entries, anything which isn't packet data.
3287          *
3288          * The StrongARM chips on the board (one for tx, one for rx)
3289          * are running in big-endian mode.
3290          */
3291         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
3292                         GRC_MODE_WSWAP_NONFRM_DATA);
3293 #if __BYTE_ORDER == __BIG_ENDIAN
3294         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
3295 #endif
3296         tp->regs = (unsigned long) ioremap(tg3reg_base, tg3reg_len);
3297         if (tp->regs == 0UL) {
3298                 printf("Cannot map device registers, aborting\n");
3299                 return 0;
3300         }
3301
3302         tg3_init_link_config(tp);
3303
3304         err = tg3_get_invariants(tp);
3305         if (err) {
3306                 printf("Problem fetching invariants of chip, aborting.\n");
3307                 goto err_out_iounmap;
3308         }
3309
3310         err = tg3_get_device_address(tp);
3311         if (err) {
3312                 printf("Could not obtain valid ethernet address, aborting.\n");
3313                 goto err_out_iounmap;
3314         }
3315
3316         DBG ( "Ethernet addr: %s\n", eth_ntoa ( nic->node_addr ) );
3317
3318         tg3_setup_dma(tp);
3319
3320         /* Now that we have fully setup the chip, save away a snapshot
3321          * of the PCI config space.  We need to restore this after
3322          * GRC_MISC_CFG core clock resets and some resume events.
3323          */
3324         pci_save_state(tp->pdev, tp->pci_cfg_state);
3325
3326         printf("Tigon3 [partno(%s) rev %hx PHY(%s)] (PCI%s:%s:%s)\n",
3327                 tp->board_part_number,
3328                 tp->pci_chip_rev_id,
3329                 tg3_phy_string(tp),
3330                 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "X" : ""),
3331                 ((tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED) ?
3332                         ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "133MHz" : "66MHz") :
3333                         ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "100MHz" : "33MHz")),
3334                 ((tp->tg3_flags & TG3_FLAG_PCI_32BIT) ? "32-bit" : "64-bit"));
3335
3336
3337         err = tg3_setup_hw(tp); 
3338         if (err) {
3339                 goto err_out_disable;
3340         } 
3341         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
3342
3343         /* Wait for a reasonable time for the link to come up */
3344         tg3_poll_link(tp);
3345         for(i = 0; !tp->carrier_ok && (i < VALID_LINK_TIMEOUT*100); i++) {
3346                 mdelay(1);
3347                 tg3_poll_link(tp);
3348         }
3349         if (!tp->carrier_ok){
3350                 printf("Valid link not established\n");
3351                 goto err_out_disable;
3352         }
3353
3354         nic->nic_op     = &tg3_operations;
3355         return 1;
3356
3357  err_out_iounmap:
3358         iounmap((void *)tp->regs);
3359         return 0;
3360  err_out_disable:
3361         tg3_disable(nic);
3362         return 0;
3363 }
3364
3365
3366 static struct pci_device_id tg3_nics[] = {
3367 PCI_ROM(0x14e4, 0x1644, "tg3-5700",        "Broadcom Tigon 3 5700"),
3368 PCI_ROM(0x14e4, 0x1645, "tg3-5701",        "Broadcom Tigon 3 5701"),
3369 PCI_ROM(0x14e4, 0x1646, "tg3-5702",        "Broadcom Tigon 3 5702"),
3370 PCI_ROM(0x14e4, 0x1647, "tg3-5703",        "Broadcom Tigon 3 5703"),
3371 PCI_ROM(0x14e4, 0x1648, "tg3-5704",        "Broadcom Tigon 3 5704"),
3372 PCI_ROM(0x14e4, 0x164d, "tg3-5702FE",      "Broadcom Tigon 3 5702FE"),
3373 PCI_ROM(0x14e4, 0x1653, "tg3-5705",        "Broadcom Tigon 3 5705"),
3374 PCI_ROM(0x14e4, 0x1654, "tg3-5705_2",      "Broadcom Tigon 3 5705_2"),
3375 PCI_ROM(0x14e4, 0x165d, "tg3-5705M",       "Broadcom Tigon 3 5705M"),
3376 PCI_ROM(0x14e4, 0x165e, "tg3-5705M_2",     "Broadcom Tigon 3 5705M_2"),
3377 PCI_ROM(0x14e4, 0x1677, "tg3-5751",        "Broadcom Tigon 3 5751"),
3378 PCI_ROM(0x14e4, 0x1696, "tg3-5782",        "Broadcom Tigon 3 5782"),
3379 PCI_ROM(0x14e4, 0x169c, "tg3-5788",        "Broadcom Tigon 3 5788"),
3380 PCI_ROM(0x14e4, 0x16a6, "tg3-5702X",       "Broadcom Tigon 3 5702X"),
3381 PCI_ROM(0x14e4, 0x16a7, "tg3-5703X",       "Broadcom Tigon 3 5703X"),
3382 PCI_ROM(0x14e4, 0x16a8, "tg3-5704S",       "Broadcom Tigon 3 5704S"),
3383 PCI_ROM(0x14e4, 0x16c6, "tg3-5702A3",      "Broadcom Tigon 3 5702A3"),
3384 PCI_ROM(0x14e4, 0x16c7, "tg3-5703A3",      "Broadcom Tigon 3 5703A3"),
3385 PCI_ROM(0x14e4, 0x170d, "tg3-5901",        "Broadcom Tigon 3 5901"),
3386 PCI_ROM(0x14e4, 0x170e, "tg3-5901_2",      "Broadcom Tigon 3 5901_2"),
3387 PCI_ROM(0x1148, 0x4400, "tg3-9DXX",        "Syskonnect 9DXX"),
3388 PCI_ROM(0x1148, 0x4500, "tg3-9MXX",        "Syskonnect 9MXX"),
3389 PCI_ROM(0x173b, 0x03e8, "tg3-ac1000",      "Altima AC1000"),
3390 PCI_ROM(0x173b, 0x03e9, "tg3-ac1001",      "Altima AC1001"),
3391 PCI_ROM(0x173b, 0x03ea, "tg3-ac9100",      "Altima AC9100"),
3392 PCI_ROM(0x173b, 0x03eb, "tg3-ac1003",      "Altima AC1003"),
3393 };
3394
3395 PCI_DRIVER ( tg3_driver, tg3_nics, PCI_NO_CLASS );
3396
3397 DRIVER ( "TG3", nic_driver, pci_driver, tg3_driver,
3398          tg3_probe, tg3_disable );