Move current e1000 driver files to e1000-old/ directory to avoid collisions
[people/xl0/gpxe.git] / src / drivers / net / e1000-old / e1000.c
1 /**************************************************************************
2 Etherboot -  BOOTP/TFTP Bootstrap Program
3 Inter Pro 1000 for Etherboot
4 Drivers are port from Intel's Linux driver e1000-4.3.15
5
6 ***************************************************************************/
7 /*******************************************************************************
8
9   
10   Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
11   
12   This program is free software; you can redistribute it and/or modify it 
13   under the terms of the GNU General Public License as published by the Free 
14   Software Foundation; either version 2 of the License, or (at your option) 
15   any later version.
16   
17   This program is distributed in the hope that it will be useful, but WITHOUT 
18   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
19   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for 
20   more details.
21   
22   You should have received a copy of the GNU General Public License along with
23   this program; if not, write to the Free Software Foundation, Inc., 59 
24   Temple Place - Suite 330, Boston, MA  02111-1307, USA.
25   
26   The full GNU General Public License is included in this distribution in the
27   file called LICENSE.
28   
29   Contact Information:
30   Linux NICS <linux.nics@intel.com>
31   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
32
33 *******************************************************************************/
34 /*
35  *  Copyright (C) Archway Digital Solutions.
36  *
37  *  written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
38  *  2/9/2002
39  *
40  *  Copyright (C) Linux Networx.
41  *  Massive upgrade to work with the new intel gigabit NICs.
42  *  <ebiederman at lnxi dot com>
43  *
44  *  Support for 82541ei & 82547ei chips from Intel's Linux driver 5.1.13 added by
45  *  Georg Baum <gbaum@users.sf.net>, sponsored by PetaMem GmbH and linkLINE Communications, Inc.
46  *
47  *  01/2004: Updated to Linux driver 5.2.22 by Georg Baum <gbaum@users.sf.net>
48  */
49
50 /* to get some global routines like printf */
51 #include "etherboot.h"
52 /* to get the interface to the body of the program */
53 #include "nic.h"
54 /* to get the PCI support functions, if this is a PCI NIC */
55 #include <gpxe/pci.h>
56 #include "timer.h"
57
58 typedef unsigned char *dma_addr_t;
59
60 typedef enum {
61         FALSE = 0,
62         TRUE = 1
63 } boolean_t;
64
65 #define DEBUG 0
66
67
68 /* Some pieces of code are disabled with #if 0 ... #endif.
69  * They are not deleted to show where the etherboot driver differs
70  * from the linux driver below the function level.
71  * Some member variables of the hw struct have been eliminated
72  * and the corresponding inplace checks inserted instead.
73  * Pieces such as LED handling that we definitely don't need are deleted.
74  *
75  * Please keep the function ordering so that it is easy to produce diffs
76  * against the linux driver.
77  *
78  * The following defines should not be needed normally,
79  * but may be helpful for debugging purposes. */
80
81 /* Define this if you want to program the transmission control register
82  * the way the Linux driver does it. */
83 #undef LINUX_DRIVER_TCTL
84
85 /* Define this to behave more like the Linux driver. */
86 #undef LINUX_DRIVER
87
88 #include "e1000_hw.h"
89
90 /* NIC specific static variables go here */
91 static struct nic_operations e1000_operations;
92
93 static struct e1000_hw hw;
94
95 struct {
96         char tx_pool[128 + 16];
97         char rx_pool[128 + 16];
98         char packet[2096];
99 } e1000_bufs __shared;
100
101 static struct e1000_tx_desc *tx_base;
102 static struct e1000_rx_desc *rx_base;
103
104 static int tx_tail;
105 static int rx_tail, rx_last;
106
107 /* Function forward declarations */
108 static int e1000_setup_link(struct e1000_hw *hw);
109 static int e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
110 static int e1000_setup_copper_link(struct e1000_hw *hw);
111 static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
112 static void e1000_config_collision_dist(struct e1000_hw *hw);
113 static int e1000_config_mac_to_phy(struct e1000_hw *hw);
114 static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
115 static int e1000_check_for_link(struct e1000_hw *hw);
116 static int e1000_wait_autoneg(struct e1000_hw *hw);
117 static void e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed, uint16_t *duplex);
118 static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
119 static int e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
120 static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data);
121 static int e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data);
122 static void e1000_phy_hw_reset(struct e1000_hw *hw);
123 static int e1000_phy_reset(struct e1000_hw *hw);
124 static int e1000_detect_gig_phy(struct e1000_hw *hw);
125 static int e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
126 static void e1000_init_rx_addrs(struct e1000_hw *hw);
127 static void e1000_clear_vfta(struct e1000_hw *hw);
128
129 /* Printing macros... */
130
131 #define E1000_ERR(args...) printf("e1000: " args)
132
133 #if DEBUG >= 3
134 #define E1000_DBG(args...) printf("e1000: " args)
135 #else
136 #define E1000_DBG(args...)
137 #endif
138
139 #define MSGOUT(S, A, B)     printk(S "\n", A, B)
140 #if DEBUG >= 2
141 #define DEBUGFUNC(F)        DEBUGOUT(F "\n");
142 #else
143 #define DEBUGFUNC(F)
144 #endif
145 #if DEBUG >= 1
146 #define DEBUGOUT(S) printf(S)
147 #define DEBUGOUT1(S,A) printf(S,A)
148 #define DEBUGOUT2(S,A,B) printf(S,A,B)
149 #define DEBUGOUT3(S,A,B,C) printf(S,A,B,C)
150 #define DEBUGOUT7(S,A,B,C,D,E,F,G) printf(S,A,B,C,D,E,F,G)
151 #else
152 #define DEBUGOUT(S)
153 #define DEBUGOUT1(S,A)
154 #define DEBUGOUT2(S,A,B)
155 #define DEBUGOUT3(S,A,B,C)
156 #define DEBUGOUT7(S,A,B,C,D,E,F,G)
157 #endif
158
159 #define E1000_WRITE_REG(a, reg, value) ( \
160     ((a)->mac_type >= e1000_82543) ? \
161         (writel((value), ((a)->hw_addr + E1000_##reg))) : \
162         (writel((value), ((a)->hw_addr + E1000_82542_##reg))))
163
164 #define E1000_READ_REG(a, reg) ( \
165     ((a)->mac_type >= e1000_82543) ? \
166         readl((a)->hw_addr + E1000_##reg) : \
167         readl((a)->hw_addr + E1000_82542_##reg))
168
169 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \
170     ((a)->mac_type >= e1000_82543) ? \
171         writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2))) : \
172         writel((value), ((a)->hw_addr + E1000_82542_##reg + ((offset) << 2))))
173
174 #define E1000_READ_REG_ARRAY(a, reg, offset) ( \
175     ((a)->mac_type >= e1000_82543) ? \
176         readl((a)->hw_addr + E1000_##reg + ((offset) << 2)) : \
177         readl((a)->hw_addr + E1000_82542_##reg + ((offset) << 2)))
178
179 #define E1000_WRITE_FLUSH(a) {uint32_t x; x = E1000_READ_REG(a, STATUS);}
180
181
182 /******************************************************************************
183  * Inline functions from e1000_main.c of the linux driver
184  ******************************************************************************/
185
186 #if 0
187 static inline uint32_t
188 e1000_io_read(struct e1000_hw *hw __unused, uint32_t port)
189 {
190         return inl(port);
191 }
192 #endif
193
194 static inline void
195 e1000_io_write(struct e1000_hw *hw __unused, uint32_t port, uint32_t value)
196 {
197         outl(value, port);
198 }
199
200 static inline void e1000_pci_set_mwi(struct e1000_hw *hw)
201 {
202         pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
203 }
204
205 static inline void e1000_pci_clear_mwi(struct e1000_hw *hw)
206 {
207         pci_write_config_word(hw->pdev, PCI_COMMAND,
208                               hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
209 }
210
211
212 /******************************************************************************
213  * Inline functions from e1000_hw.c of the linux driver
214  ******************************************************************************/
215
216 /******************************************************************************
217 * Writes a value to one of the devices registers using port I/O (as opposed to
218 * memory mapped I/O). Only 82544 and newer devices support port I/O. *
219 * hw - Struct containing variables accessed by shared code
220 * offset - offset to write to * value - value to write
221 *****************************************************************************/
222 static inline void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset,
223                                       uint32_t value){
224         e1000_io_write(hw, hw->io_base, offset);
225         e1000_io_write(hw, hw->io_base + 4, value);
226 }
227
228
229 /******************************************************************************
230  * Functions from e1000_hw.c of the linux driver
231  ******************************************************************************/
232
233 /******************************************************************************
234  * Set the phy type member in the hw struct.
235  *
236  * hw - Struct containing variables accessed by shared code
237  *****************************************************************************/
238 static int32_t
239 e1000_set_phy_type(struct e1000_hw *hw)
240 {
241         DEBUGFUNC("e1000_set_phy_type");
242
243         switch(hw->phy_id) {
244         case M88E1000_E_PHY_ID:
245         case M88E1000_I_PHY_ID:
246         case M88E1011_I_PHY_ID:
247                 hw->phy_type = e1000_phy_m88;
248                 break;
249         case IGP01E1000_I_PHY_ID:
250                 hw->phy_type = e1000_phy_igp;
251                 break;
252         default:
253                 /* Should never have loaded on this device */
254                 hw->phy_type = e1000_phy_undefined;
255                 return -E1000_ERR_PHY_TYPE;
256         }
257
258         return E1000_SUCCESS;
259 }
260
261 /******************************************************************************
262  * IGP phy init script - initializes the GbE PHY
263  *
264  * hw - Struct containing variables accessed by shared code
265  *****************************************************************************/
266 static void
267 e1000_phy_init_script(struct e1000_hw *hw)
268 {
269         DEBUGFUNC("e1000_phy_init_script");
270
271 #if 0
272         /* See e1000_sw_init() of the Linux driver */
273         if(hw->phy_init_script) {
274 #else
275         if((hw->mac_type == e1000_82541) ||
276            (hw->mac_type == e1000_82547) ||
277            (hw->mac_type == e1000_82541_rev_2) ||
278            (hw->mac_type == e1000_82547_rev_2)) {
279 #endif
280                 mdelay(20);
281
282                 e1000_write_phy_reg(hw,0x0000,0x0140);
283
284                 mdelay(5);
285
286                 if(hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547) {
287                         e1000_write_phy_reg(hw, 0x1F95, 0x0001);
288
289                         e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
290
291                         e1000_write_phy_reg(hw, 0x1F79, 0x0018);
292
293                         e1000_write_phy_reg(hw, 0x1F30, 0x1600);
294
295                         e1000_write_phy_reg(hw, 0x1F31, 0x0014);
296
297                         e1000_write_phy_reg(hw, 0x1F32, 0x161C);
298
299                         e1000_write_phy_reg(hw, 0x1F94, 0x0003);
300
301                         e1000_write_phy_reg(hw, 0x1F96, 0x003F);
302
303                         e1000_write_phy_reg(hw, 0x2010, 0x0008);
304                 } else {
305                         e1000_write_phy_reg(hw, 0x1F73, 0x0099);
306                 }
307
308                 e1000_write_phy_reg(hw, 0x0000, 0x3300);
309
310
311                 if(hw->mac_type == e1000_82547) {
312                         uint16_t fused, fine, coarse;
313
314                         /* Move to analog registers page */
315                         e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
316
317                         if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
318                                 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
319
320                                 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
321                                 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
322
323                                 if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
324                                         coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
325                                         fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
326                                 } else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
327                                         fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
328
329                                 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
330                                         (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
331                                         (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
332
333                                 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
334                                 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
335                                                 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
336                         }
337                 }
338         }
339 }
340
341 /******************************************************************************
342  * Set the mac type member in the hw struct.
343  * 
344  * hw - Struct containing variables accessed by shared code
345  *****************************************************************************/
346 static int
347 e1000_set_mac_type(struct e1000_hw *hw)
348 {
349         DEBUGFUNC("e1000_set_mac_type");
350
351         switch (hw->device_id) {
352         case E1000_DEV_ID_82542:
353                 switch (hw->revision_id) {
354                 case E1000_82542_2_0_REV_ID:
355                         hw->mac_type = e1000_82542_rev2_0;
356                         break;
357                 case E1000_82542_2_1_REV_ID:
358                         hw->mac_type = e1000_82542_rev2_1;
359                         break;
360                 default:
361                         /* Invalid 82542 revision ID */
362                         return -E1000_ERR_MAC_TYPE;
363                 }
364                 break;
365         case E1000_DEV_ID_82543GC_FIBER:
366         case E1000_DEV_ID_82543GC_COPPER:
367                 hw->mac_type = e1000_82543;
368                 break;
369         case E1000_DEV_ID_82544EI_COPPER:
370         case E1000_DEV_ID_82544EI_FIBER:
371         case E1000_DEV_ID_82544GC_COPPER:
372         case E1000_DEV_ID_82544GC_LOM:
373                 hw->mac_type = e1000_82544;
374                 break;
375         case E1000_DEV_ID_82540EM:
376         case E1000_DEV_ID_82540EM_LOM:
377         case E1000_DEV_ID_82540EP:
378         case E1000_DEV_ID_82540EP_LOM:
379         case E1000_DEV_ID_82540EP_LP:
380                 hw->mac_type = e1000_82540;
381                 break;
382         case E1000_DEV_ID_82545EM_COPPER:
383         case E1000_DEV_ID_82545EM_FIBER:
384                 hw->mac_type = e1000_82545;
385                 break;
386         case E1000_DEV_ID_82545GM_COPPER:
387         case E1000_DEV_ID_82545GM_FIBER:
388         case E1000_DEV_ID_82545GM_SERDES:
389                 hw->mac_type = e1000_82545_rev_3;
390                 break;
391         case E1000_DEV_ID_82546EB_COPPER:
392         case E1000_DEV_ID_82546EB_FIBER:
393         case E1000_DEV_ID_82546EB_QUAD_COPPER:
394                 hw->mac_type = e1000_82546;
395                 break;
396         case E1000_DEV_ID_82546GB_COPPER:
397         case E1000_DEV_ID_82546GB_FIBER:
398         case E1000_DEV_ID_82546GB_SERDES:
399                 hw->mac_type = e1000_82546_rev_3;
400                 break;
401         case E1000_DEV_ID_82541EI:
402         case E1000_DEV_ID_82541EI_MOBILE:
403                 hw->mac_type = e1000_82541;
404                 break;
405         case E1000_DEV_ID_82541ER:
406         case E1000_DEV_ID_82541GI:
407         case E1000_DEV_ID_82541GI_MOBILE:
408                 hw->mac_type = e1000_82541_rev_2;
409                 break;
410         case E1000_DEV_ID_82547EI:
411                 hw->mac_type = e1000_82547;
412                 break;
413         case E1000_DEV_ID_82547GI:
414                 hw->mac_type = e1000_82547_rev_2;
415                 break;
416         default:
417                 /* Should never have loaded on this device */
418                 return -E1000_ERR_MAC_TYPE;
419         }
420
421         return E1000_SUCCESS;
422 }
423
424 /*****************************************************************************
425  * Set media type and TBI compatibility.
426  *
427  * hw - Struct containing variables accessed by shared code
428  * **************************************************************************/
429 static void
430 e1000_set_media_type(struct e1000_hw *hw)
431 {
432         uint32_t status;
433
434         DEBUGFUNC("e1000_set_media_type");
435         
436         if(hw->mac_type != e1000_82543) {
437                 /* tbi_compatibility is only valid on 82543 */
438                 hw->tbi_compatibility_en = FALSE;
439         }
440
441         switch (hw->device_id) {
442                 case E1000_DEV_ID_82545GM_SERDES:
443                 case E1000_DEV_ID_82546GB_SERDES:
444                         hw->media_type = e1000_media_type_internal_serdes;
445                         break;
446                 default:
447                         if(hw->mac_type >= e1000_82543) {
448                                 status = E1000_READ_REG(hw, STATUS);
449                                 if(status & E1000_STATUS_TBIMODE) {
450                                         hw->media_type = e1000_media_type_fiber;
451                                         /* tbi_compatibility not valid on fiber */
452                                         hw->tbi_compatibility_en = FALSE;
453                                 } else {
454                                         hw->media_type = e1000_media_type_copper;
455                                 }
456                         } else {
457                                 /* This is an 82542 (fiber only) */
458                                 hw->media_type = e1000_media_type_fiber;
459                         }
460         }
461 }
462
463 /******************************************************************************
464  * Reset the transmit and receive units; mask and clear all interrupts.
465  *
466  * hw - Struct containing variables accessed by shared code
467  *****************************************************************************/
468 static void
469 e1000_reset_hw(struct e1000_hw *hw)
470 {
471         uint32_t ctrl;
472         uint32_t ctrl_ext;
473         uint32_t icr;
474         uint32_t manc;
475         
476         DEBUGFUNC("e1000_reset_hw");
477         
478         /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
479         if(hw->mac_type == e1000_82542_rev2_0) {
480                 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
481                 e1000_pci_clear_mwi(hw);
482         }
483
484         /* Clear interrupt mask to stop board from generating interrupts */
485         DEBUGOUT("Masking off all interrupts\n");
486         E1000_WRITE_REG(hw, IMC, 0xffffffff);
487         
488         /* Disable the Transmit and Receive units.  Then delay to allow
489          * any pending transactions to complete before we hit the MAC with
490          * the global reset.
491          */
492         E1000_WRITE_REG(hw, RCTL, 0);
493         E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
494         E1000_WRITE_FLUSH(hw);
495
496         /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
497         hw->tbi_compatibility_on = FALSE;
498
499         /* Delay to allow any outstanding PCI transactions to complete before
500          * resetting the device
501          */ 
502         mdelay(10);
503
504         ctrl = E1000_READ_REG(hw, CTRL);
505
506         /* Must reset the PHY before resetting the MAC */
507         if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
508                 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
509                 mdelay(5);
510         }
511
512         /* Issue a global reset to the MAC.  This will reset the chip's
513          * transmit, receive, DMA, and link units.  It will not effect
514          * the current PCI configuration.  The global reset bit is self-
515          * clearing, and should clear within a microsecond.
516          */
517         DEBUGOUT("Issuing a global reset to MAC\n");
518
519         switch(hw->mac_type) {
520                 case e1000_82544:
521                 case e1000_82540:
522                 case e1000_82545:
523                 case e1000_82546:
524                 case e1000_82541:
525                 case e1000_82541_rev_2:
526                         /* These controllers can't ack the 64-bit write when issuing the
527                          * reset, so use IO-mapping as a workaround to issue the reset */
528                         E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
529                         break;
530                 case e1000_82545_rev_3:
531                 case e1000_82546_rev_3:
532                         /* Reset is performed on a shadow of the control register */
533                         E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
534                         break;
535                 default:
536                         E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
537                         break;
538         }
539
540         /* After MAC reset, force reload of EEPROM to restore power-on settings to
541          * device.  Later controllers reload the EEPROM automatically, so just wait
542          * for reload to complete.
543          */
544         switch(hw->mac_type) {
545                 case e1000_82542_rev2_0:
546                 case e1000_82542_rev2_1:
547                 case e1000_82543:
548                 case e1000_82544:
549                         /* Wait for reset to complete */
550                         udelay(10);
551                         ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
552                         ctrl_ext |= E1000_CTRL_EXT_EE_RST;
553                         E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
554                         E1000_WRITE_FLUSH(hw);
555                         /* Wait for EEPROM reload */
556                         mdelay(2);
557                         break;
558                 case e1000_82541:
559                 case e1000_82541_rev_2:
560                 case e1000_82547:
561                 case e1000_82547_rev_2:
562                         /* Wait for EEPROM reload */
563                         mdelay(20);
564                         break;
565                 default:
566                         /* Wait for EEPROM reload (it happens automatically) */
567                         mdelay(5);
568                         break;
569         }
570
571         /* Disable HW ARPs on ASF enabled adapters */
572         if(hw->mac_type >= e1000_82540) {
573                 manc = E1000_READ_REG(hw, MANC);
574                 manc &= ~(E1000_MANC_ARP_EN);
575                 E1000_WRITE_REG(hw, MANC, manc);
576         }
577
578         if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
579                 e1000_phy_init_script(hw);
580         }
581
582         /* Clear interrupt mask to stop board from generating interrupts */
583         DEBUGOUT("Masking off all interrupts\n");
584         E1000_WRITE_REG(hw, IMC, 0xffffffff);
585         
586         /* Clear any pending interrupt events. */
587         icr = E1000_READ_REG(hw, ICR);
588
589         /* If MWI was previously enabled, reenable it. */
590         if(hw->mac_type == e1000_82542_rev2_0) {
591 #ifdef LINUX_DRIVER
592                 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
593 #endif
594                         e1000_pci_set_mwi(hw);
595         }
596 }
597
598 /******************************************************************************
599  * Performs basic configuration of the adapter.
600  *
601  * hw - Struct containing variables accessed by shared code
602  * 
603  * Assumes that the controller has previously been reset and is in a 
604  * post-reset uninitialized state. Initializes the receive address registers,
605  * multicast table, and VLAN filter table. Calls routines to setup link
606  * configuration and flow control settings. Clears all on-chip counters. Leaves
607  * the transmit and receive units disabled and uninitialized.
608  *****************************************************************************/
609 static int
610 e1000_init_hw(struct e1000_hw *hw)
611 {
612         uint32_t ctrl, status;
613         uint32_t i;
614         int32_t ret_val;
615         uint16_t pcix_cmd_word;
616         uint16_t pcix_stat_hi_word;
617         uint16_t cmd_mmrbc;
618         uint16_t stat_mmrbc;
619         e1000_bus_type bus_type = e1000_bus_type_unknown;
620
621         DEBUGFUNC("e1000_init_hw");
622
623         /* Set the media type and TBI compatibility */
624         e1000_set_media_type(hw);
625
626         /* Disabling VLAN filtering. */
627         DEBUGOUT("Initializing the IEEE VLAN\n");
628         E1000_WRITE_REG(hw, VET, 0);
629         
630         e1000_clear_vfta(hw);
631         
632         /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
633         if(hw->mac_type == e1000_82542_rev2_0) {
634                 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
635                 e1000_pci_clear_mwi(hw);
636                 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
637                 E1000_WRITE_FLUSH(hw);
638                 mdelay(5);
639         }
640         
641         /* Setup the receive address. This involves initializing all of the Receive
642          * Address Registers (RARs 0 - 15).
643          */
644         e1000_init_rx_addrs(hw);
645         
646         /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
647         if(hw->mac_type == e1000_82542_rev2_0) {
648                 E1000_WRITE_REG(hw, RCTL, 0);
649                 E1000_WRITE_FLUSH(hw);
650                 mdelay(1);
651 #ifdef LINUX_DRIVER
652                 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
653 #endif
654                         e1000_pci_set_mwi(hw);
655         }
656         
657         /* Zero out the Multicast HASH table */
658         DEBUGOUT("Zeroing the MTA\n");
659         for(i = 0; i < E1000_MC_TBL_SIZE; i++)
660                 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
661         
662 #if 0
663         /* Set the PCI priority bit correctly in the CTRL register.  This
664          * determines if the adapter gives priority to receives, or if it
665          * gives equal priority to transmits and receives.
666          */
667         if(hw->dma_fairness) {
668                 ctrl = E1000_READ_REG(hw, CTRL);
669                 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
670         }
671 #endif
672
673         switch(hw->mac_type) {
674                 case e1000_82545_rev_3:
675                 case e1000_82546_rev_3:
676                         break;
677                 default:
678                         if (hw->mac_type >= e1000_82543) {
679                                 /* See e1000_get_bus_info() of the Linux driver */
680                                 status = E1000_READ_REG(hw, STATUS);
681                                 bus_type = (status & E1000_STATUS_PCIX_MODE) ?
682                                         e1000_bus_type_pcix : e1000_bus_type_pci;
683                         }
684
685                         /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
686                         if(bus_type == e1000_bus_type_pcix) {
687                                 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
688                                 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
689                                 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
690                                         PCIX_COMMAND_MMRBC_SHIFT;
691                                 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
692                                         PCIX_STATUS_HI_MMRBC_SHIFT;
693                                 if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
694                                         stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
695                                 if(cmd_mmrbc > stat_mmrbc) {
696                                         pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
697                                         pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
698                                         pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER, pcix_cmd_word);
699                                 }
700                         }
701                         break;
702         }
703
704         /* Call a subroutine to configure the link and setup flow control. */
705         ret_val = e1000_setup_link(hw);
706         
707         /* Set the transmit descriptor write-back policy */
708         if(hw->mac_type > e1000_82544) {
709                 ctrl = E1000_READ_REG(hw, TXDCTL);
710                 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
711                 E1000_WRITE_REG(hw, TXDCTL, ctrl);
712         }
713
714 #if 0
715         /* Clear all of the statistics registers (clear on read).  It is
716          * important that we do this after we have tried to establish link
717          * because the symbol error count will increment wildly if there
718          * is no link.
719          */
720         e1000_clear_hw_cntrs(hw);
721 #endif
722
723         return ret_val;
724 }
725
726 /******************************************************************************
727  * Adjust SERDES output amplitude based on EEPROM setting.
728  *
729  * hw - Struct containing variables accessed by shared code.
730  *****************************************************************************/
731 static int32_t
732 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
733 {
734         uint16_t eeprom_data;
735         int32_t  ret_val;
736
737         DEBUGFUNC("e1000_adjust_serdes_amplitude");
738
739         if(hw->media_type != e1000_media_type_internal_serdes)
740                 return E1000_SUCCESS;
741
742         switch(hw->mac_type) {
743                 case e1000_82545_rev_3:
744                 case e1000_82546_rev_3:
745                         break;
746                 default:
747                         return E1000_SUCCESS;
748         }
749
750         if ((ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,
751                                         &eeprom_data))) {
752                 return ret_val;
753         }
754
755         if(eeprom_data != EEPROM_RESERVED_WORD) {
756                 /* Adjust SERDES output amplitude only. */
757                 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
758                 if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL,
759                                                   eeprom_data)))
760                         return ret_val;
761         }
762
763         return E1000_SUCCESS;
764 }
765                                                                    
766 /******************************************************************************
767  * Configures flow control and link settings.
768  * 
769  * hw - Struct containing variables accessed by shared code
770  * 
771  * Determines which flow control settings to use. Calls the apropriate media-
772  * specific link configuration function. Configures the flow control settings.
773  * Assuming the adapter has a valid link partner, a valid link should be
774  * established. Assumes the hardware has previously been reset and the 
775  * transmitter and receiver are not enabled.
776  *****************************************************************************/
777 static int
778 e1000_setup_link(struct e1000_hw *hw)
779 {
780         uint32_t ctrl_ext;
781         int32_t ret_val;
782         uint16_t eeprom_data;
783
784         DEBUGFUNC("e1000_setup_link");
785         
786         /* Read and store word 0x0F of the EEPROM. This word contains bits
787          * that determine the hardware's default PAUSE (flow control) mode,
788          * a bit that determines whether the HW defaults to enabling or
789          * disabling auto-negotiation, and the direction of the
790          * SW defined pins. If there is no SW over-ride of the flow
791          * control setting, then the variable hw->fc will
792          * be initialized based on a value in the EEPROM.
793          */
794         if(e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data) < 0) {
795                 DEBUGOUT("EEPROM Read Error\n");
796                 return -E1000_ERR_EEPROM;
797         }
798         
799         if(hw->fc == e1000_fc_default) {
800                 if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
801                         hw->fc = e1000_fc_none;
802                 else if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 
803                         EEPROM_WORD0F_ASM_DIR)
804                         hw->fc = e1000_fc_tx_pause;
805                 else
806                         hw->fc = e1000_fc_full;
807         }
808         
809         /* We want to save off the original Flow Control configuration just
810          * in case we get disconnected and then reconnected into a different
811          * hub or switch with different Flow Control capabilities.
812          */
813         if(hw->mac_type == e1000_82542_rev2_0)
814                 hw->fc &= (~e1000_fc_tx_pause);
815
816 #if 0
817         /* See e1000_sw_init() of the Linux driver */
818         if((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
819 #else
820         if((hw->mac_type < e1000_82543) && (hw->mac_type >= e1000_82543))
821 #endif
822                 hw->fc &= (~e1000_fc_rx_pause);
823         
824 #if 0
825         hw->original_fc = hw->fc;
826 #endif
827
828         DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
829         
830         /* Take the 4 bits from EEPROM word 0x0F that determine the initial
831          * polarity value for the SW controlled pins, and setup the
832          * Extended Device Control reg with that info.
833          * This is needed because one of the SW controlled pins is used for
834          * signal detection.  So this should be done before e1000_setup_pcs_link()
835          * or e1000_phy_setup() is called.
836          */
837         if(hw->mac_type == e1000_82543) {
838                 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 
839                         SWDPIO__EXT_SHIFT);
840                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
841         }
842         
843         /* Call the necessary subroutine to configure the link. */
844         ret_val = (hw->media_type == e1000_media_type_copper) ?
845                 e1000_setup_copper_link(hw) :
846                 e1000_setup_fiber_serdes_link(hw);
847         if (ret_val < 0) {
848                 return ret_val;
849         }
850         
851         /* Initialize the flow control address, type, and PAUSE timer
852          * registers to their default values.  This is done even if flow
853          * control is disabled, because it does not hurt anything to
854          * initialize these registers.
855          */
856         DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
857         
858         E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
859         E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
860         E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
861 #if 0
862         E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
863 #else
864         E1000_WRITE_REG(hw, FCTTV, FC_DEFAULT_TX_TIMER);
865 #endif
866         
867         /* Set the flow control receive threshold registers.  Normally,
868          * these registers will be set to a default threshold that may be
869          * adjusted later by the driver's runtime code.  However, if the
870          * ability to transmit pause frames in not enabled, then these
871          * registers will be set to 0. 
872          */
873         if(!(hw->fc & e1000_fc_tx_pause)) {
874                 E1000_WRITE_REG(hw, FCRTL, 0);
875                 E1000_WRITE_REG(hw, FCRTH, 0);
876         } else {
877                 /* We need to set up the Receive Threshold high and low water marks
878                  * as well as (optionally) enabling the transmission of XON frames.
879                  */
880 #if 0
881                 if(hw->fc_send_xon) {
882                         E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
883                         E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
884                 } else {
885                         E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
886                         E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
887                 }
888 #else
889                 E1000_WRITE_REG(hw, FCRTL, (FC_DEFAULT_LO_THRESH | E1000_FCRTL_XONE));
890                 E1000_WRITE_REG(hw, FCRTH, FC_DEFAULT_HI_THRESH);
891 #endif
892         }
893         return ret_val;
894 }
895
896 /******************************************************************************
897  * Sets up link for a fiber based or serdes based adapter
898  *
899  * hw - Struct containing variables accessed by shared code
900  *
901  * Manipulates Physical Coding Sublayer functions in order to configure
902  * link. Assumes the hardware has been previously reset and the transmitter
903  * and receiver are not enabled.
904  *****************************************************************************/
905 static int
906 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
907 {
908         uint32_t ctrl;
909         uint32_t status;
910         uint32_t txcw = 0;
911         uint32_t i;
912         uint32_t signal = 0;
913         int32_t ret_val;
914
915         DEBUGFUNC("e1000_setup_fiber_serdes_link");
916
917         /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be 
918          * set when the optics detect a signal. On older adapters, it will be 
919          * cleared when there is a signal.  This applies to fiber media only.
920          * If we're on serdes media, adjust the output amplitude to value set in
921          * the EEPROM.
922          */
923         ctrl = E1000_READ_REG(hw, CTRL);
924         if(hw->media_type == e1000_media_type_fiber)
925                 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
926
927         if((ret_val = e1000_adjust_serdes_amplitude(hw)))
928                 return ret_val;
929
930         /* Take the link out of reset */
931         ctrl &= ~(E1000_CTRL_LRST);
932
933 #if 0
934         /* Adjust VCO speed to improve BER performance */
935         if((ret_val = e1000_set_vco_speed(hw)))
936                 return ret_val;
937 #endif
938
939         e1000_config_collision_dist(hw);
940         
941         /* Check for a software override of the flow control settings, and setup
942          * the device accordingly.  If auto-negotiation is enabled, then software
943          * will have to set the "PAUSE" bits to the correct value in the Tranmsit
944          * Config Word Register (TXCW) and re-start auto-negotiation.  However, if
945          * auto-negotiation is disabled, then software will have to manually 
946          * configure the two flow control enable bits in the CTRL register.
947          *
948          * The possible values of the "fc" parameter are:
949          *      0:  Flow control is completely disabled
950          *      1:  Rx flow control is enabled (we can receive pause frames, but 
951          *          not send pause frames).
952          *      2:  Tx flow control is enabled (we can send pause frames but we do
953          *          not support receiving pause frames).
954          *      3:  Both Rx and TX flow control (symmetric) are enabled.
955          */
956         switch (hw->fc) {
957         case e1000_fc_none:
958                 /* Flow control is completely disabled by a software over-ride. */
959                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
960                 break;
961         case e1000_fc_rx_pause:
962                 /* RX Flow control is enabled and TX Flow control is disabled by a 
963                  * software over-ride. Since there really isn't a way to advertise 
964                  * that we are capable of RX Pause ONLY, we will advertise that we
965                  * support both symmetric and asymmetric RX PAUSE. Later, we will
966                  *  disable the adapter's ability to send PAUSE frames.
967                  */
968                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
969                 break;
970         case e1000_fc_tx_pause:
971                 /* TX Flow control is enabled, and RX Flow control is disabled, by a 
972                  * software over-ride.
973                  */
974                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
975                 break;
976         case e1000_fc_full:
977                 /* Flow control (both RX and TX) is enabled by a software over-ride. */
978                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
979                 break;
980         default:
981                 DEBUGOUT("Flow control param set incorrectly\n");
982                 return -E1000_ERR_CONFIG;
983                 break;
984         }
985         
986         /* Since auto-negotiation is enabled, take the link out of reset (the link
987          * will be in reset, because we previously reset the chip). This will
988          * restart auto-negotiation.  If auto-neogtiation is successful then the
989          * link-up status bit will be set and the flow control enable bits (RFCE
990          * and TFCE) will be set according to their negotiated value.
991          */
992         DEBUGOUT("Auto-negotiation enabled\n");
993         
994         E1000_WRITE_REG(hw, TXCW, txcw);
995         E1000_WRITE_REG(hw, CTRL, ctrl);
996         E1000_WRITE_FLUSH(hw);
997         
998         hw->txcw = txcw;
999         mdelay(1);
1000         
1001         /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
1002          * indication in the Device Status Register.  Time-out if a link isn't 
1003          * seen in 500 milliseconds seconds (Auto-negotiation should complete in 
1004          * less than 500 milliseconds even if the other end is doing it in SW).
1005          * For internal serdes, we just assume a signal is present, then poll.
1006          */
1007         if(hw->media_type == e1000_media_type_internal_serdes ||
1008            (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
1009                 DEBUGOUT("Looking for Link\n");
1010                 for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
1011                         mdelay(10);
1012                         status = E1000_READ_REG(hw, STATUS);
1013                         if(status & E1000_STATUS_LU) break;
1014                 }
1015                 if(i == (LINK_UP_TIMEOUT / 10)) {
1016                         DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1017                         hw->autoneg_failed = 1;
1018                         /* AutoNeg failed to achieve a link, so we'll call 
1019                          * e1000_check_for_link. This routine will force the link up if
1020                          * we detect a signal. This will allow us to communicate with
1021                          * non-autonegotiating link partners.
1022                          */
1023                         if((ret_val = e1000_check_for_link(hw))) {
1024                                 DEBUGOUT("Error while checking for link\n");
1025                                 return ret_val;
1026                         }
1027                         hw->autoneg_failed = 0;
1028                 } else {
1029                         hw->autoneg_failed = 0;
1030                         DEBUGOUT("Valid Link Found\n");
1031                 }
1032         } else {
1033                 DEBUGOUT("No Signal Detected\n");
1034         }
1035         return E1000_SUCCESS;
1036 }
1037
1038 /******************************************************************************
1039 * Detects which PHY is present and the speed and duplex
1040 *
1041 * hw - Struct containing variables accessed by shared code
1042 ******************************************************************************/
1043 static int
1044 e1000_setup_copper_link(struct e1000_hw *hw)
1045 {
1046         uint32_t ctrl;
1047         int32_t ret_val;
1048         uint16_t i;
1049         uint16_t phy_data;
1050         
1051         DEBUGFUNC("e1000_setup_copper_link");
1052         
1053         ctrl = E1000_READ_REG(hw, CTRL);
1054         /* With 82543, we need to force speed and duplex on the MAC equal to what
1055          * the PHY speed and duplex configuration is. In addition, we need to
1056          * perform a hardware reset on the PHY to take it out of reset.
1057          */
1058         if(hw->mac_type > e1000_82543) {
1059                 ctrl |= E1000_CTRL_SLU;
1060                 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1061                 E1000_WRITE_REG(hw, CTRL, ctrl);
1062         } else {
1063                 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1064                 E1000_WRITE_REG(hw, CTRL, ctrl);
1065                 e1000_phy_hw_reset(hw);
1066         }
1067         
1068         /* Make sure we have a valid PHY */
1069         if((ret_val = e1000_detect_gig_phy(hw))) {
1070                 DEBUGOUT("Error, did not detect valid phy.\n");
1071                 return ret_val;
1072         }
1073         DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
1074
1075         if(hw->mac_type <= e1000_82543 ||
1076            hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1077 #if 0
1078            hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
1079                 hw->phy_reset_disable = FALSE;
1080
1081         if(!hw->phy_reset_disable) {
1082 #else
1083            hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) {
1084 #endif
1085         if (hw->phy_type == e1000_phy_igp) {
1086
1087                 if((ret_val = e1000_phy_reset(hw))) {
1088                         DEBUGOUT("Error Resetting the PHY\n");
1089                         return ret_val;
1090                 }
1091
1092                 /* Wait 10ms for MAC to configure PHY from eeprom settings */
1093                 mdelay(15);
1094
1095 #if 0
1096                 /* disable lplu d3 during driver init */
1097                 if((ret_val = e1000_set_d3_lplu_state(hw, FALSE))) {
1098                         DEBUGOUT("Error Disabling LPLU D3\n");
1099                         return ret_val;
1100                 }
1101
1102                 /* Configure mdi-mdix settings */
1103                 if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
1104                                                  &phy_data)))
1105                         return ret_val;
1106
1107                 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1108                         hw->dsp_config_state = e1000_dsp_config_disabled;
1109                         /* Force MDI for IGP B-0 PHY */
1110                         phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX |
1111                                       IGP01E1000_PSCR_FORCE_MDI_MDIX);
1112                         hw->mdix = 1;
1113
1114                 } else {
1115                         hw->dsp_config_state = e1000_dsp_config_enabled;
1116                         phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1117
1118                         switch (hw->mdix) {
1119                         case 1:
1120                                 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1121                                 break;
1122                         case 2:
1123                                 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1124                                 break;
1125                         case 0:
1126                         default:
1127                                 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1128                                 break;
1129                         }
1130                 }
1131                 if((ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
1132                                                   phy_data)))
1133                         return ret_val;
1134
1135                 /* set auto-master slave resolution settings */
1136                 e1000_ms_type phy_ms_setting = hw->master_slave;
1137
1138                 if(hw->ffe_config_state == e1000_ffe_config_active)
1139                         hw->ffe_config_state = e1000_ffe_config_enabled;
1140
1141                 if(hw->dsp_config_state == e1000_dsp_config_activated)
1142                         hw->dsp_config_state = e1000_dsp_config_enabled;
1143 #endif
1144
1145                 /* when autonegotiation advertisment is only 1000Mbps then we
1146                  * should disable SmartSpeed and enable Auto MasterSlave
1147                  * resolution as hardware default. */
1148                 if(hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1149                         /* Disable SmartSpeed */
1150                         if((ret_val = e1000_read_phy_reg(hw,
1151                                                          IGP01E1000_PHY_PORT_CONFIG,
1152                                                          &phy_data)))
1153                                 return ret_val;
1154                         phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1155                         if((ret_val = e1000_write_phy_reg(hw,
1156                                                           IGP01E1000_PHY_PORT_CONFIG,
1157                                                           phy_data)))
1158                                 return ret_val;
1159                         /* Set auto Master/Slave resolution process */
1160                         if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
1161                                                          &phy_data)))
1162                                 return ret_val;
1163                         phy_data &= ~CR_1000T_MS_ENABLE;
1164                         if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
1165                                                           phy_data)))
1166                                 return ret_val;
1167                 }
1168
1169                 if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
1170                                                  &phy_data)))
1171                         return ret_val;
1172
1173 #if 0
1174                 /* load defaults for future use */
1175                 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1176                                             ((phy_data & CR_1000T_MS_VALUE) ?
1177                                              e1000_ms_force_master :
1178                                              e1000_ms_force_slave) :
1179                                              e1000_ms_auto;
1180
1181                 switch (phy_ms_setting) {
1182                 case e1000_ms_force_master:
1183                         phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1184                         break;
1185                 case e1000_ms_force_slave:
1186                         phy_data |= CR_1000T_MS_ENABLE;
1187                         phy_data &= ~(CR_1000T_MS_VALUE);
1188                         break;
1189                 case e1000_ms_auto:
1190                         phy_data &= ~CR_1000T_MS_ENABLE;
1191                 default:
1192                         break;
1193                 }
1194 #endif
1195
1196                 if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
1197                                                   phy_data)))
1198                         return ret_val;
1199         } else {
1200                 /* Enable CRS on TX. This must be set for half-duplex operation. */
1201                 if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1202                                                  &phy_data)))
1203                         return ret_val;
1204
1205                 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1206
1207                 /* Options:
1208                  *   MDI/MDI-X = 0 (default)
1209                  *   0 - Auto for all speeds
1210                  *   1 - MDI mode
1211                  *   2 - MDI-X mode
1212                  *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1213                  */
1214 #if 0
1215                 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1216
1217                 switch (hw->mdix) {
1218                 case 1:
1219                         phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1220                         break;
1221                 case 2:
1222                         phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1223                         break;
1224                 case 3:
1225                         phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1226                         break;
1227                 case 0:
1228                 default:
1229 #endif
1230                         phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1231 #if 0
1232                         break;
1233                 }
1234 #endif
1235
1236                 /* Options:
1237                  *   disable_polarity_correction = 0 (default)
1238                  *       Automatic Correction for Reversed Cable Polarity
1239                  *   0 - Disabled
1240                  *   1 - Enabled
1241                  */
1242                 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1243                 if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1244                                                   phy_data)))
1245                         return ret_val;
1246
1247                 /* Force TX_CLK in the Extended PHY Specific Control Register
1248                  * to 25MHz clock.
1249                  */
1250                 if((ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1251                                                  &phy_data)))
1252                         return ret_val;
1253
1254                 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1255
1256 #ifdef LINUX_DRIVER
1257                 if (hw->phy_revision < M88E1011_I_REV_4) {
1258 #endif
1259                         /* Configure Master and Slave downshift values */
1260                         phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1261                                 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1262                         phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1263                                 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1264                         if((ret_val = e1000_write_phy_reg(hw,
1265                                                           M88E1000_EXT_PHY_SPEC_CTRL,
1266                                                           phy_data)))
1267                                 return ret_val;
1268                 }
1269         
1270                 /* SW Reset the PHY so all changes take effect */
1271                 if((ret_val = e1000_phy_reset(hw))) {
1272                         DEBUGOUT("Error Resetting the PHY\n");
1273                         return ret_val;
1274 #ifdef LINUX_DRIVER
1275                 }
1276 #endif
1277         }
1278         
1279         /* Options:
1280          *   autoneg = 1 (default)
1281          *      PHY will advertise value(s) parsed from
1282          *      autoneg_advertised and fc
1283          *   autoneg = 0
1284          *      PHY will be set to 10H, 10F, 100H, or 100F
1285          *      depending on value parsed from forced_speed_duplex.
1286          */
1287         
1288         /* Is autoneg enabled?  This is enabled by default or by software
1289          * override.  If so, call e1000_phy_setup_autoneg routine to parse the
1290          * autoneg_advertised and fc options. If autoneg is NOT enabled, then
1291          * the user should have provided a speed/duplex override.  If so, then
1292          * call e1000_phy_force_speed_duplex to parse and set this up.
1293          */
1294         /* Perform some bounds checking on the hw->autoneg_advertised
1295          * parameter.  If this variable is zero, then set it to the default.
1296          */
1297         hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1298         
1299         /* If autoneg_advertised is zero, we assume it was not defaulted
1300          * by the calling code so we set to advertise full capability.
1301          */
1302         if(hw->autoneg_advertised == 0)
1303                 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1304         
1305         DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1306         if((ret_val = e1000_phy_setup_autoneg(hw))) {
1307                 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1308                 return ret_val;
1309         }
1310         DEBUGOUT("Restarting Auto-Neg\n");
1311         
1312         /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1313          * the Auto Neg Restart bit in the PHY control register.
1314          */
1315         if((ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data)))
1316                 return ret_val;
1317
1318         phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1319         if((ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data)))
1320                 return ret_val;
1321
1322 #if 0   
1323         /* Does the user want to wait for Auto-Neg to complete here, or
1324          * check at a later time (for example, callback routine).
1325          */
1326         if(hw->wait_autoneg_complete) {
1327                 if((ret_val = e1000_wait_autoneg(hw))) {
1328                         DEBUGOUT("Error while waiting for autoneg to complete\n");
1329                         return ret_val;
1330                 }
1331         }
1332 #else
1333         /* If we do not wait for autonegotiation to complete I 
1334          * do not see a valid link status.
1335          */
1336         if((ret_val = e1000_wait_autoneg(hw))) {
1337                 DEBUGOUT("Error while waiting for autoneg to complete\n");
1338                 return ret_val;
1339         }
1340 #endif
1341         } /* !hw->phy_reset_disable */
1342         
1343         /* Check link status. Wait up to 100 microseconds for link to become
1344          * valid.
1345          */
1346         for(i = 0; i < 10; i++) {
1347                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
1348                         return ret_val;
1349                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
1350                         return ret_val;
1351
1352                 if(phy_data & MII_SR_LINK_STATUS) {
1353                         /* We have link, so we need to finish the config process:
1354                          *   1) Set up the MAC to the current PHY speed/duplex
1355                          *      if we are on 82543.  If we
1356                          *      are on newer silicon, we only need to configure
1357                          *      collision distance in the Transmit Control Register.
1358                          *   2) Set up flow control on the MAC to that established with
1359                          *      the link partner.
1360                          */
1361                         if(hw->mac_type >= e1000_82544) {
1362                                 e1000_config_collision_dist(hw);
1363                         } else {
1364                                 if((ret_val = e1000_config_mac_to_phy(hw))) {
1365                                         DEBUGOUT("Error configuring MAC to PHY settings\n");
1366                                         return ret_val;
1367                                 }
1368                         }
1369                         if((ret_val = e1000_config_fc_after_link_up(hw))) {
1370                                 DEBUGOUT("Error Configuring Flow Control\n");
1371                                 return ret_val;
1372                         }
1373 #if 0
1374                         if(hw->phy_type == e1000_phy_igp) {
1375                                 if((ret_val = e1000_config_dsp_after_link_change(hw, TRUE))) {
1376                                         DEBUGOUT("Error Configuring DSP after link up\n");
1377                                         return ret_val;
1378                                 }
1379                         }
1380 #endif
1381                         DEBUGOUT("Valid link established!!!\n");
1382                         return E1000_SUCCESS;
1383                 }
1384                 udelay(10);
1385         }
1386         
1387         DEBUGOUT("Unable to establish link!!!\n");
1388         return -E1000_ERR_NOLINK;
1389 }
1390
1391 /******************************************************************************
1392 * Configures PHY autoneg and flow control advertisement settings
1393 *
1394 * hw - Struct containing variables accessed by shared code
1395 ******************************************************************************/
1396 static int
1397 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1398 {
1399         int32_t ret_val;
1400         uint16_t mii_autoneg_adv_reg;
1401         uint16_t mii_1000t_ctrl_reg;
1402
1403         DEBUGFUNC("e1000_phy_setup_autoneg");
1404         
1405         /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1406         if((ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
1407                                          &mii_autoneg_adv_reg)))
1408                 return ret_val;
1409
1410         /* Read the MII 1000Base-T Control Register (Address 9). */
1411         if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg)))
1412                 return ret_val;
1413
1414         /* Need to parse both autoneg_advertised and fc and set up
1415          * the appropriate PHY registers.  First we will parse for
1416          * autoneg_advertised software override.  Since we can advertise
1417          * a plethora of combinations, we need to check each bit
1418          * individually.
1419          */
1420         
1421         /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1422          * Advertisement Register (Address 4) and the 1000 mb speed bits in
1423          * the  1000Base-T Control Register (Address 9).
1424          */
1425         mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
1426         mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1427
1428         DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
1429
1430         /* Do we want to advertise 10 Mb Half Duplex? */
1431         if(hw->autoneg_advertised & ADVERTISE_10_HALF) {
1432                 DEBUGOUT("Advertise 10mb Half duplex\n");
1433                 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1434         }
1435
1436         /* Do we want to advertise 10 Mb Full Duplex? */
1437         if(hw->autoneg_advertised & ADVERTISE_10_FULL) {
1438                 DEBUGOUT("Advertise 10mb Full duplex\n");
1439                 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1440         }
1441
1442         /* Do we want to advertise 100 Mb Half Duplex? */
1443         if(hw->autoneg_advertised & ADVERTISE_100_HALF) {
1444                 DEBUGOUT("Advertise 100mb Half duplex\n");
1445                 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1446         }
1447
1448         /* Do we want to advertise 100 Mb Full Duplex? */
1449         if(hw->autoneg_advertised & ADVERTISE_100_FULL) {
1450                 DEBUGOUT("Advertise 100mb Full duplex\n");
1451                 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1452         }
1453
1454         /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1455         if(hw->autoneg_advertised & ADVERTISE_1000_HALF) {
1456                 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
1457         }
1458
1459         /* Do we want to advertise 1000 Mb Full Duplex? */
1460         if(hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1461                 DEBUGOUT("Advertise 1000mb Full duplex\n");
1462                 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1463         }
1464
1465         /* Check for a software override of the flow control settings, and
1466          * setup the PHY advertisement registers accordingly.  If
1467          * auto-negotiation is enabled, then software will have to set the
1468          * "PAUSE" bits to the correct value in the Auto-Negotiation
1469          * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
1470          *
1471          * The possible values of the "fc" parameter are:
1472          *      0:  Flow control is completely disabled
1473          *      1:  Rx flow control is enabled (we can receive pause frames
1474          *          but not send pause frames).
1475          *      2:  Tx flow control is enabled (we can send pause frames
1476          *          but we do not support receiving pause frames).
1477          *      3:  Both Rx and TX flow control (symmetric) are enabled.
1478          *  other:  No software override.  The flow control configuration
1479          *          in the EEPROM is used.
1480          */
1481         switch (hw->fc) {
1482         case e1000_fc_none: /* 0 */
1483                 /* Flow control (RX & TX) is completely disabled by a
1484                  * software over-ride.
1485                  */
1486                 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1487                 break;
1488         case e1000_fc_rx_pause: /* 1 */
1489                 /* RX Flow control is enabled, and TX Flow control is
1490                  * disabled, by a software over-ride.
1491                  */
1492                 /* Since there really isn't a way to advertise that we are
1493                  * capable of RX Pause ONLY, we will advertise that we
1494                  * support both symmetric and asymmetric RX PAUSE.  Later
1495                  * (in e1000_config_fc_after_link_up) we will disable the
1496                  *hw's ability to send PAUSE frames.
1497                  */
1498                 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1499                 break;
1500         case e1000_fc_tx_pause: /* 2 */
1501                 /* TX Flow control is enabled, and RX Flow control is
1502                  * disabled, by a software over-ride.
1503                  */
1504                 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1505                 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1506                 break;
1507         case e1000_fc_full: /* 3 */
1508                 /* Flow control (both RX and TX) is enabled by a software
1509                  * over-ride.
1510                  */
1511                 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1512                 break;
1513         default:
1514                 DEBUGOUT("Flow control param set incorrectly\n");
1515                 return -E1000_ERR_CONFIG;
1516         }
1517
1518         if((ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV,
1519                                mii_autoneg_adv_reg)))
1520                 return ret_val;
1521
1522         DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1523
1524         if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg)))
1525                 return ret_val;
1526
1527         return E1000_SUCCESS;
1528 }
1529
1530 /******************************************************************************
1531 * Sets the collision distance in the Transmit Control register
1532 *
1533 * hw - Struct containing variables accessed by shared code
1534 *
1535 * Link should have been established previously. Reads the speed and duplex
1536 * information from the Device Status register.
1537 ******************************************************************************/
1538 static void
1539 e1000_config_collision_dist(struct e1000_hw *hw)
1540 {
1541         uint32_t tctl;
1542
1543         tctl = E1000_READ_REG(hw, TCTL);
1544         
1545         tctl &= ~E1000_TCTL_COLD;
1546         tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
1547         
1548         E1000_WRITE_REG(hw, TCTL, tctl);
1549         E1000_WRITE_FLUSH(hw);
1550 }
1551
1552 /******************************************************************************
1553 * Sets MAC speed and duplex settings to reflect the those in the PHY
1554 *
1555 * hw - Struct containing variables accessed by shared code
1556 * mii_reg - data to write to the MII control register
1557 *
1558 * The contents of the PHY register containing the needed information need to
1559 * be passed in.
1560 ******************************************************************************/
1561 static int
1562 e1000_config_mac_to_phy(struct e1000_hw *hw)
1563 {
1564         uint32_t ctrl;
1565         int32_t ret_val;
1566         uint16_t phy_data;
1567
1568         DEBUGFUNC("e1000_config_mac_to_phy");
1569
1570         /* Read the Device Control Register and set the bits to Force Speed
1571          * and Duplex.
1572          */
1573         ctrl = E1000_READ_REG(hw, CTRL);
1574         ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1575         ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
1576
1577         /* Set up duplex in the Device Control and Transmit Control
1578          * registers depending on negotiated values.
1579          */
1580         if (hw->phy_type == e1000_phy_igp) {
1581                 if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
1582                                                  &phy_data)))
1583                         return ret_val;
1584
1585                 if(phy_data & IGP01E1000_PSSR_FULL_DUPLEX) ctrl |= E1000_CTRL_FD;
1586                 else ctrl &= ~E1000_CTRL_FD;
1587
1588                 e1000_config_collision_dist(hw);
1589
1590                 /* Set up speed in the Device Control register depending on
1591                  * negotiated values.
1592                  */
1593                 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
1594                    IGP01E1000_PSSR_SPEED_1000MBPS)
1595                         ctrl |= E1000_CTRL_SPD_1000;
1596                 else if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
1597                         IGP01E1000_PSSR_SPEED_100MBPS)
1598                         ctrl |= E1000_CTRL_SPD_100;
1599         } else {
1600                 if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
1601                                                  &phy_data)))
1602                         return ret_val;
1603                 
1604                 if(phy_data & M88E1000_PSSR_DPLX) ctrl |= E1000_CTRL_FD;
1605                 else ctrl &= ~E1000_CTRL_FD;
1606
1607                 e1000_config_collision_dist(hw);
1608
1609                 /* Set up speed in the Device Control register depending on
1610                  * negotiated values.
1611                  */
1612                 if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1613                         ctrl |= E1000_CTRL_SPD_1000;
1614                 else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
1615                         ctrl |= E1000_CTRL_SPD_100;
1616         }
1617         /* Write the configured values back to the Device Control Reg. */
1618         E1000_WRITE_REG(hw, CTRL, ctrl);
1619         return E1000_SUCCESS;
1620 }
1621
1622 /******************************************************************************
1623  * Forces the MAC's flow control settings.
1624  * 
1625  * hw - Struct containing variables accessed by shared code
1626  *
1627  * Sets the TFCE and RFCE bits in the device control register to reflect
1628  * the adapter settings. TFCE and RFCE need to be explicitly set by
1629  * software when a Copper PHY is used because autonegotiation is managed
1630  * by the PHY rather than the MAC. Software must also configure these
1631  * bits when link is forced on a fiber connection.
1632  *****************************************************************************/
1633 static int
1634 e1000_force_mac_fc(struct e1000_hw *hw)
1635 {
1636         uint32_t ctrl;
1637         
1638         DEBUGFUNC("e1000_force_mac_fc");
1639         
1640         /* Get the current configuration of the Device Control Register */
1641         ctrl = E1000_READ_REG(hw, CTRL);
1642         
1643         /* Because we didn't get link via the internal auto-negotiation
1644          * mechanism (we either forced link or we got link via PHY
1645          * auto-neg), we have to manually enable/disable transmit an
1646          * receive flow control.
1647          *
1648          * The "Case" statement below enables/disable flow control
1649          * according to the "hw->fc" parameter.
1650          *
1651          * The possible values of the "fc" parameter are:
1652          *      0:  Flow control is completely disabled
1653          *      1:  Rx flow control is enabled (we can receive pause
1654          *          frames but not send pause frames).
1655          *      2:  Tx flow control is enabled (we can send pause frames
1656          *          frames but we do not receive pause frames).
1657          *      3:  Both Rx and TX flow control (symmetric) is enabled.
1658          *  other:  No other values should be possible at this point.
1659          */
1660         
1661         switch (hw->fc) {
1662         case e1000_fc_none:
1663                 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1664                 break;
1665         case e1000_fc_rx_pause:
1666                 ctrl &= (~E1000_CTRL_TFCE);
1667                 ctrl |= E1000_CTRL_RFCE;
1668                 break;
1669         case e1000_fc_tx_pause:
1670                 ctrl &= (~E1000_CTRL_RFCE);
1671                 ctrl |= E1000_CTRL_TFCE;
1672                 break;
1673         case e1000_fc_full:
1674                 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1675                 break;
1676         default:
1677                 DEBUGOUT("Flow control param set incorrectly\n");
1678                 return -E1000_ERR_CONFIG;
1679         }
1680         
1681         /* Disable TX Flow Control for 82542 (rev 2.0) */
1682         if(hw->mac_type == e1000_82542_rev2_0)
1683                 ctrl &= (~E1000_CTRL_TFCE);
1684         
1685         E1000_WRITE_REG(hw, CTRL, ctrl);
1686         return E1000_SUCCESS;
1687 }
1688
1689 /******************************************************************************
1690  * Configures flow control settings after link is established
1691  * 
1692  * hw - Struct containing variables accessed by shared code
1693  *
1694  * Should be called immediately after a valid link has been established.
1695  * Forces MAC flow control settings if link was forced. When in MII/GMII mode
1696  * and autonegotiation is enabled, the MAC flow control settings will be set
1697  * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
1698  * and RFCE bits will be automaticaly set to the negotiated flow control mode.
1699  *****************************************************************************/
1700 static int
1701 e1000_config_fc_after_link_up(struct e1000_hw *hw)
1702 {
1703         int32_t ret_val;
1704         uint16_t mii_status_reg;
1705         uint16_t mii_nway_adv_reg;
1706         uint16_t mii_nway_lp_ability_reg;
1707         uint16_t speed;
1708         uint16_t duplex;
1709         
1710         DEBUGFUNC("e1000_config_fc_after_link_up");
1711         
1712         /* Check for the case where we have fiber media and auto-neg failed
1713          * so we had to force link.  In this case, we need to force the
1714          * configuration of the MAC to match the "fc" parameter.
1715          */
1716         if(((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
1717            ((hw->media_type == e1000_media_type_internal_serdes) && (hw->autoneg_failed))) { 
1718                 if((ret_val = e1000_force_mac_fc(hw))) {
1719                         DEBUGOUT("Error forcing flow control settings\n");
1720                         return ret_val;
1721                 }
1722         }
1723         
1724         /* Check for the case where we have copper media and auto-neg is
1725          * enabled.  In this case, we need to check and see if Auto-Neg
1726          * has completed, and if so, how the PHY and link partner has
1727          * flow control configured.
1728          */
1729         if(hw->media_type == e1000_media_type_copper) {
1730                 /* Read the MII Status Register and check to see if AutoNeg
1731                  * has completed.  We read this twice because this reg has
1732                  * some "sticky" (latched) bits.
1733                  */
1734                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
1735                         return ret_val;
1736                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
1737                         return ret_val;
1738                 
1739                 if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
1740                         /* The AutoNeg process has completed, so we now need to
1741                          * read both the Auto Negotiation Advertisement Register
1742                          * (Address 4) and the Auto_Negotiation Base Page Ability
1743                          * Register (Address 5) to determine how flow control was
1744                          * negotiated.
1745                          */
1746                         if((ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
1747                                                          &mii_nway_adv_reg)))
1748                                 return ret_val;
1749                         if((ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
1750                                                          &mii_nway_lp_ability_reg)))
1751                                 return ret_val;
1752
1753                         /* Two bits in the Auto Negotiation Advertisement Register
1754                          * (Address 4) and two bits in the Auto Negotiation Base
1755                          * Page Ability Register (Address 5) determine flow control
1756                          * for both the PHY and the link partner.  The following
1757                          * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1758                          * 1999, describes these PAUSE resolution bits and how flow
1759                          * control is determined based upon these settings.
1760                          * NOTE:  DC = Don't Care
1761                          *
1762                          *   LOCAL DEVICE  |   LINK PARTNER
1763                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1764                          *-------|---------|-------|---------|--------------------
1765                          *   0   |    0    |  DC   |   DC    | e1000_fc_none
1766                          *   0   |    1    |   0   |   DC    | e1000_fc_none
1767                          *   0   |    1    |   1   |    0    | e1000_fc_none
1768                          *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
1769                          *   1   |    0    |   0   |   DC    | e1000_fc_none
1770                          *   1   |   DC    |   1   |   DC    | e1000_fc_full
1771                          *   1   |    1    |   0   |    0    | e1000_fc_none
1772                          *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
1773                          *
1774                          */
1775                         /* Are both PAUSE bits set to 1?  If so, this implies
1776                          * Symmetric Flow Control is enabled at both ends.  The
1777                          * ASM_DIR bits are irrelevant per the spec.
1778                          *
1779                          * For Symmetric Flow Control:
1780                          *
1781                          *   LOCAL DEVICE  |   LINK PARTNER
1782                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1783                          *-------|---------|-------|---------|--------------------
1784                          *   1   |   DC    |   1   |   DC    | e1000_fc_full
1785                          *
1786                          */
1787                         if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1788                                 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1789                                 /* Now we need to check if the user selected RX ONLY
1790                                  * of pause frames.  In this case, we had to advertise
1791                                  * FULL flow control because we could not advertise RX
1792                                  * ONLY. Hence, we must now check to see if we need to
1793                                  * turn OFF  the TRANSMISSION of PAUSE frames.
1794                                  */
1795 #if 0
1796                                 if(hw->original_fc == e1000_fc_full) {
1797                                         hw->fc = e1000_fc_full;
1798 #else
1799                                 if(hw->fc == e1000_fc_full) {
1800 #endif
1801                                         DEBUGOUT("Flow Control = FULL.\r\n");
1802                                 } else {
1803                                         hw->fc = e1000_fc_rx_pause;
1804                                         DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1805                                 }
1806                         }
1807                         /* For receiving PAUSE frames ONLY.
1808                          *
1809                          *   LOCAL DEVICE  |   LINK PARTNER
1810                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1811                          *-------|---------|-------|---------|--------------------
1812                          *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
1813                          *
1814                          */
1815                         else if(!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1816                                 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1817                                 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1818                                 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1819                                 hw->fc = e1000_fc_tx_pause;
1820                                 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n");
1821                         }
1822                         /* For transmitting PAUSE frames ONLY.
1823                          *
1824                          *   LOCAL DEVICE  |   LINK PARTNER
1825                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1826                          *-------|---------|-------|---------|--------------------
1827                          *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
1828                          *
1829                          */
1830                         else if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1831                                 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1832                                 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1833                                 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1834                                 hw->fc = e1000_fc_rx_pause;
1835                                 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1836                         }
1837                         /* Per the IEEE spec, at this point flow control should be
1838                          * disabled.  However, we want to consider that we could
1839                          * be connected to a legacy switch that doesn't advertise
1840                          * desired flow control, but can be forced on the link
1841                          * partner.  So if we advertised no flow control, that is
1842                          * what we will resolve to.  If we advertised some kind of
1843                          * receive capability (Rx Pause Only or Full Flow Control)
1844                          * and the link partner advertised none, we will configure
1845                          * ourselves to enable Rx Flow Control only.  We can do
1846                          * this safely for two reasons:  If the link partner really
1847                          * didn't want flow control enabled, and we enable Rx, no
1848                          * harm done since we won't be receiving any PAUSE frames
1849                          * anyway.  If the intent on the link partner was to have
1850                          * flow control enabled, then by us enabling RX only, we
1851                          * can at least receive pause frames and process them.
1852                          * This is a good idea because in most cases, since we are
1853                          * predominantly a server NIC, more times than not we will
1854                          * be asked to delay transmission of packets than asking
1855                          * our link partner to pause transmission of frames.
1856                          */
1857 #if 0
1858                         else if(hw->original_fc == e1000_fc_none ||
1859                                 hw->original_fc == e1000_fc_tx_pause) {
1860 #else
1861                         else if(hw->fc == e1000_fc_none)
1862                                 DEBUGOUT("Flow Control = NONE.\r\n");
1863                         else if(hw->fc == e1000_fc_tx_pause) {
1864 #endif
1865                                 hw->fc = e1000_fc_none;
1866                                 DEBUGOUT("Flow Control = NONE.\r\n");
1867                         } else {
1868                                 hw->fc = e1000_fc_rx_pause;
1869                                 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1870                         }
1871                         
1872                         /* Now we need to do one last check...  If we auto-
1873                          * negotiated to HALF DUPLEX, flow control should not be
1874                          * enabled per IEEE 802.3 spec.
1875                          */
1876                         e1000_get_speed_and_duplex(hw, &speed, &duplex);
1877                         
1878                         if(duplex == HALF_DUPLEX)
1879                                 hw->fc = e1000_fc_none;
1880                         
1881                         /* Now we call a subroutine to actually force the MAC
1882                          * controller to use the correct flow control settings.
1883                          */
1884                         if((ret_val = e1000_force_mac_fc(hw))) {
1885                                 DEBUGOUT("Error forcing flow control settings\n");
1886                                 return ret_val;
1887                         }
1888                 } else {
1889                         DEBUGOUT("Copper PHY and Auto Neg has not completed.\r\n");
1890                 }
1891         }
1892         return E1000_SUCCESS;
1893 }
1894
1895 /******************************************************************************
1896  * Checks to see if the link status of the hardware has changed.
1897  *
1898  * hw - Struct containing variables accessed by shared code
1899  *
1900  * Called by any function that needs to check the link status of the adapter.
1901  *****************************************************************************/
1902 static int
1903 e1000_check_for_link(struct e1000_hw *hw)
1904 {
1905         uint32_t rxcw;
1906         uint32_t ctrl;
1907         uint32_t status;
1908         uint32_t rctl;
1909         uint32_t signal = 0;
1910         int32_t ret_val;
1911         uint16_t phy_data;
1912         uint16_t lp_capability;
1913         
1914         DEBUGFUNC("e1000_check_for_link");
1915         
1916         /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be 
1917          * set when the optics detect a signal. On older adapters, it will be 
1918          * cleared when there is a signal.  This applies to fiber media only.
1919          */
1920         if(hw->media_type == e1000_media_type_fiber)
1921                 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
1922
1923         ctrl = E1000_READ_REG(hw, CTRL);
1924         status = E1000_READ_REG(hw, STATUS);
1925         rxcw = E1000_READ_REG(hw, RXCW);
1926         
1927         /* If we have a copper PHY then we only want to go out to the PHY
1928          * registers to see if Auto-Neg has completed and/or if our link
1929          * status has changed.  The get_link_status flag will be set if we
1930          * receive a Link Status Change interrupt or we have Rx Sequence
1931          * Errors.
1932          */
1933 #if 0
1934         if((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
1935 #else
1936         if(hw->media_type == e1000_media_type_copper) {
1937 #endif
1938                 /* First we want to see if the MII Status Register reports
1939                  * link.  If so, then we want to get the current speed/duplex
1940                  * of the PHY.
1941                  * Read the register twice since the link bit is sticky.
1942                  */
1943                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
1944                         return ret_val;
1945                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
1946                         return ret_val;
1947                 
1948                 if(phy_data & MII_SR_LINK_STATUS) {
1949 #if 0
1950                         hw->get_link_status = FALSE;
1951 #endif
1952                 } else {
1953                         /* No link detected */
1954                         return -E1000_ERR_NOLINK;
1955                 }
1956
1957                 /* We have a M88E1000 PHY and Auto-Neg is enabled.  If we
1958                  * have Si on board that is 82544 or newer, Auto
1959                  * Speed Detection takes care of MAC speed/duplex
1960                  * configuration.  So we only need to configure Collision
1961                  * Distance in the MAC.  Otherwise, we need to force
1962                  * speed/duplex on the MAC to the current PHY speed/duplex
1963                  * settings.
1964                  */
1965                 if(hw->mac_type >= e1000_82544)
1966                         e1000_config_collision_dist(hw);
1967                 else {
1968                         if((ret_val = e1000_config_mac_to_phy(hw))) {
1969                                 DEBUGOUT("Error configuring MAC to PHY settings\n");
1970                                 return ret_val;
1971                         }
1972                 }
1973                 
1974                 /* Configure Flow Control now that Auto-Neg has completed. First, we 
1975                  * need to restore the desired flow control settings because we may
1976                  * have had to re-autoneg with a different link partner.
1977                  */
1978                 if((ret_val = e1000_config_fc_after_link_up(hw))) {
1979                         DEBUGOUT("Error configuring flow control\n");
1980                         return ret_val;
1981                 }
1982                 
1983                 /* At this point we know that we are on copper and we have
1984                  * auto-negotiated link.  These are conditions for checking the link
1985                  * parter capability register.  We use the link partner capability to
1986                  * determine if TBI Compatibility needs to be turned on or off.  If
1987                  * the link partner advertises any speed in addition to Gigabit, then
1988                  * we assume that they are GMII-based, and TBI compatibility is not
1989                  * needed. If no other speeds are advertised, we assume the link
1990                  * partner is TBI-based, and we turn on TBI Compatibility.
1991                  */
1992                 if(hw->tbi_compatibility_en) {
1993                         if((ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
1994                                                          &lp_capability)))
1995                                 return ret_val;
1996                         if(lp_capability & (NWAY_LPAR_10T_HD_CAPS |
1997                                 NWAY_LPAR_10T_FD_CAPS |
1998                                 NWAY_LPAR_100TX_HD_CAPS |
1999                                 NWAY_LPAR_100TX_FD_CAPS |
2000                                 NWAY_LPAR_100T4_CAPS)) {
2001                                 /* If our link partner advertises anything in addition to 
2002                                  * gigabit, we do not need to enable TBI compatibility.
2003                                  */
2004                                 if(hw->tbi_compatibility_on) {
2005                                         /* If we previously were in the mode, turn it off. */
2006                                         rctl = E1000_READ_REG(hw, RCTL);
2007                                         rctl &= ~E1000_RCTL_SBP;
2008                                         E1000_WRITE_REG(hw, RCTL, rctl);
2009                                         hw->tbi_compatibility_on = FALSE;
2010                                 }
2011                         } else {
2012                                 /* If TBI compatibility is was previously off, turn it on. For
2013                                  * compatibility with a TBI link partner, we will store bad
2014                                  * packets. Some frames have an additional byte on the end and
2015                                  * will look like CRC errors to to the hardware.
2016                                  */
2017                                 if(!hw->tbi_compatibility_on) {
2018                                         hw->tbi_compatibility_on = TRUE;
2019                                         rctl = E1000_READ_REG(hw, RCTL);
2020                                         rctl |= E1000_RCTL_SBP;
2021                                         E1000_WRITE_REG(hw, RCTL, rctl);
2022                                 }
2023                         }
2024                 }
2025         }
2026         /* If we don't have link (auto-negotiation failed or link partner cannot
2027          * auto-negotiate), the cable is plugged in (we have signal), and our
2028          * link partner is not trying to auto-negotiate with us (we are receiving
2029          * idles or data), we need to force link up. We also need to give
2030          * auto-negotiation time to complete, in case the cable was just plugged
2031          * in. The autoneg_failed flag does this.
2032          */
2033         else if((((hw->media_type == e1000_media_type_fiber) &&
2034                 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
2035                 (hw->media_type == e1000_media_type_internal_serdes)) &&
2036                 (!(status & E1000_STATUS_LU)) &&
2037                 (!(rxcw & E1000_RXCW_C))) {
2038                 if(hw->autoneg_failed == 0) {
2039                         hw->autoneg_failed = 1;
2040                         return 0;
2041                 }
2042                 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
2043                 
2044                 /* Disable auto-negotiation in the TXCW register */
2045                 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
2046                 
2047                 /* Force link-up and also force full-duplex. */
2048                 ctrl = E1000_READ_REG(hw, CTRL);
2049                 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
2050                 E1000_WRITE_REG(hw, CTRL, ctrl);
2051                 
2052                 /* Configure Flow Control after forcing link up. */
2053                 if((ret_val = e1000_config_fc_after_link_up(hw))) {
2054                         DEBUGOUT("Error configuring flow control\n");
2055                         return ret_val;
2056                 }
2057         }
2058         /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
2059          * auto-negotiation in the TXCW register and disable forced link in the
2060          * Device Control register in an attempt to auto-negotiate with our link
2061          * partner.
2062          */
2063         else if(((hw->media_type == e1000_media_type_fiber)  ||
2064                  (hw->media_type == e1000_media_type_internal_serdes)) &&
2065                 (ctrl & E1000_CTRL_SLU) &&
2066                 (rxcw & E1000_RXCW_C)) {
2067                 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
2068                 E1000_WRITE_REG(hw, TXCW, hw->txcw);
2069                 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
2070         }
2071 #if 0
2072         /* If we force link for non-auto-negotiation switch, check link status
2073          * based on MAC synchronization for internal serdes media type.
2074          */
2075         else if((hw->media_type == e1000_media_type_internal_serdes) &&
2076                         !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
2077                 /* SYNCH bit and IV bit are sticky. */
2078                 udelay(10);
2079                 if(E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
2080                         if(!(rxcw & E1000_RXCW_IV)) {
2081                                 hw->serdes_link_down = FALSE;
2082                                 DEBUGOUT("SERDES: Link is up.\n");
2083                         }
2084                 } else {
2085                         hw->serdes_link_down = TRUE;
2086                         DEBUGOUT("SERDES: Link is down.\n");
2087                 }
2088         }
2089 #endif
2090         return E1000_SUCCESS;
2091 }
2092
2093 /******************************************************************************
2094  * Detects the current speed and duplex settings of the hardware.
2095  *
2096  * hw - Struct containing variables accessed by shared code
2097  * speed - Speed of the connection
2098  * duplex - Duplex setting of the connection
2099  *****************************************************************************/
2100 static void 
2101 e1000_get_speed_and_duplex(struct e1000_hw *hw,
2102                            uint16_t *speed,
2103                            uint16_t *duplex)
2104 {
2105         uint32_t status;
2106         
2107         DEBUGFUNC("e1000_get_speed_and_duplex");
2108         
2109         if(hw->mac_type >= e1000_82543) {
2110                 status = E1000_READ_REG(hw, STATUS);
2111                 if(status & E1000_STATUS_SPEED_1000) {
2112                         *speed = SPEED_1000;
2113                         DEBUGOUT("1000 Mbs, ");
2114                 } else if(status & E1000_STATUS_SPEED_100) {
2115                         *speed = SPEED_100;
2116                         DEBUGOUT("100 Mbs, ");
2117                 } else {
2118                         *speed = SPEED_10;
2119                         DEBUGOUT("10 Mbs, ");
2120                 }
2121                 
2122                 if(status & E1000_STATUS_FD) {
2123                         *duplex = FULL_DUPLEX;
2124                         DEBUGOUT("Full Duplex\r\n");
2125                 } else {
2126                         *duplex = HALF_DUPLEX;
2127                         DEBUGOUT(" Half Duplex\r\n");
2128                 }
2129         } else {
2130                 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
2131                 *speed = SPEED_1000;
2132                 *duplex = FULL_DUPLEX;
2133         }
2134 }
2135
2136 /******************************************************************************
2137 * Blocks until autoneg completes or times out (~4.5 seconds)
2138 *
2139 * hw - Struct containing variables accessed by shared code
2140 ******************************************************************************/
2141 static int
2142 e1000_wait_autoneg(struct e1000_hw *hw)
2143 {
2144         int32_t ret_val;
2145         uint16_t i;
2146         uint16_t phy_data;
2147         
2148         DEBUGFUNC("e1000_wait_autoneg");
2149         DEBUGOUT("Waiting for Auto-Neg to complete.\n");
2150         
2151         /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2152         for(i = PHY_AUTO_NEG_TIME; i > 0; i--) {
2153                 /* Read the MII Status Register and wait for Auto-Neg
2154                  * Complete bit to be set.
2155                  */
2156                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2157                         return ret_val;
2158                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2159                         return ret_val;
2160                 if(phy_data & MII_SR_AUTONEG_COMPLETE) {
2161                         DEBUGOUT("Auto-Neg complete.\n");
2162                         return E1000_SUCCESS;
2163                 }
2164                 mdelay(100);
2165         }
2166         DEBUGOUT("Auto-Neg timedout.\n");
2167         return -E1000_ERR_TIMEOUT;
2168 }
2169
2170 /******************************************************************************
2171 * Raises the Management Data Clock
2172 *
2173 * hw - Struct containing variables accessed by shared code
2174 * ctrl - Device control register's current value
2175 ******************************************************************************/
2176 static void
2177 e1000_raise_mdi_clk(struct e1000_hw *hw,
2178                     uint32_t *ctrl)
2179 {
2180         /* Raise the clock input to the Management Data Clock (by setting the MDC
2181          * bit), and then delay 10 microseconds.
2182          */
2183         E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
2184         E1000_WRITE_FLUSH(hw);
2185         udelay(10);
2186 }
2187
2188 /******************************************************************************
2189 * Lowers the Management Data Clock
2190 *
2191 * hw - Struct containing variables accessed by shared code
2192 * ctrl - Device control register's current value
2193 ******************************************************************************/
2194 static void
2195 e1000_lower_mdi_clk(struct e1000_hw *hw,
2196                     uint32_t *ctrl)
2197 {
2198         /* Lower the clock input to the Management Data Clock (by clearing the MDC
2199          * bit), and then delay 10 microseconds.
2200          */
2201         E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
2202         E1000_WRITE_FLUSH(hw);
2203         udelay(10);
2204 }
2205
2206 /******************************************************************************
2207 * Shifts data bits out to the PHY
2208 *
2209 * hw - Struct containing variables accessed by shared code
2210 * data - Data to send out to the PHY
2211 * count - Number of bits to shift out
2212 *
2213 * Bits are shifted out in MSB to LSB order.
2214 ******************************************************************************/
2215 static void
2216 e1000_shift_out_mdi_bits(struct e1000_hw *hw,
2217                          uint32_t data,
2218                          uint16_t count)
2219 {
2220         uint32_t ctrl;
2221         uint32_t mask;
2222
2223         /* We need to shift "count" number of bits out to the PHY. So, the value
2224          * in the "data" parameter will be shifted out to the PHY one bit at a 
2225          * time. In order to do this, "data" must be broken down into bits.
2226          */
2227         mask = 0x01;
2228         mask <<= (count - 1);
2229         
2230         ctrl = E1000_READ_REG(hw, CTRL);
2231         
2232         /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
2233         ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
2234         
2235         while(mask) {
2236                 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
2237                  * then raising and lowering the Management Data Clock. A "0" is
2238                  * shifted out to the PHY by setting the MDIO bit to "0" and then
2239                  * raising and lowering the clock.
2240                  */
2241                 if(data & mask) ctrl |= E1000_CTRL_MDIO;
2242                 else ctrl &= ~E1000_CTRL_MDIO;
2243                 
2244                 E1000_WRITE_REG(hw, CTRL, ctrl);
2245                 E1000_WRITE_FLUSH(hw);
2246                 
2247                 udelay(10);
2248
2249                 e1000_raise_mdi_clk(hw, &ctrl);
2250                 e1000_lower_mdi_clk(hw, &ctrl);
2251
2252                 mask = mask >> 1;
2253         }
2254 }
2255
2256 /******************************************************************************
2257 * Shifts data bits in from the PHY
2258 *
2259 * hw - Struct containing variables accessed by shared code
2260 *
2261 * Bits are shifted in in MSB to LSB order. 
2262 ******************************************************************************/
2263 static uint16_t
2264 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
2265 {
2266         uint32_t ctrl;
2267         uint16_t data = 0;
2268         uint8_t i;
2269
2270         /* In order to read a register from the PHY, we need to shift in a total
2271          * of 18 bits from the PHY. The first two bit (turnaround) times are used
2272          * to avoid contention on the MDIO pin when a read operation is performed.
2273          * These two bits are ignored by us and thrown away. Bits are "shifted in"
2274          * by raising the input to the Management Data Clock (setting the MDC bit),
2275          * and then reading the value of the MDIO bit.
2276          */ 
2277         ctrl = E1000_READ_REG(hw, CTRL);
2278         
2279         /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
2280         ctrl &= ~E1000_CTRL_MDIO_DIR;
2281         ctrl &= ~E1000_CTRL_MDIO;
2282         
2283         E1000_WRITE_REG(hw, CTRL, ctrl);
2284         E1000_WRITE_FLUSH(hw);
2285         
2286         /* Raise and Lower the clock before reading in the data. This accounts for
2287          * the turnaround bits. The first clock occurred when we clocked out the
2288          * last bit of the Register Address.
2289          */
2290         e1000_raise_mdi_clk(hw, &ctrl);
2291         e1000_lower_mdi_clk(hw, &ctrl);
2292         
2293         for(data = 0, i = 0; i < 16; i++) {
2294                 data = data << 1;
2295                 e1000_raise_mdi_clk(hw, &ctrl);
2296                 ctrl = E1000_READ_REG(hw, CTRL);
2297                 /* Check to see if we shifted in a "1". */
2298                 if(ctrl & E1000_CTRL_MDIO) data |= 1;
2299                 e1000_lower_mdi_clk(hw, &ctrl);
2300         }
2301         
2302         e1000_raise_mdi_clk(hw, &ctrl);
2303         e1000_lower_mdi_clk(hw, &ctrl);
2304         
2305         return data;
2306 }
2307
2308 /*****************************************************************************
2309 * Reads the value from a PHY register, if the value is on a specific non zero
2310 * page, sets the page first.
2311 *
2312 * hw - Struct containing variables accessed by shared code
2313 * reg_addr - address of the PHY register to read
2314 ******************************************************************************/
2315 static int
2316 e1000_read_phy_reg(struct e1000_hw *hw,
2317                    uint32_t reg_addr,
2318                    uint16_t *phy_data)
2319 {
2320         uint32_t ret_val;
2321
2322         DEBUGFUNC("e1000_read_phy_reg");
2323
2324         if(hw->phy_type == e1000_phy_igp &&
2325            (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2326                 if((ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2327                                                      (uint16_t)reg_addr)))
2328                         return ret_val;
2329         }
2330
2331         ret_val = e1000_read_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr,
2332                                         phy_data);
2333
2334         return ret_val;
2335 }
2336
2337 static int
2338 e1000_read_phy_reg_ex(struct e1000_hw *hw,
2339                       uint32_t reg_addr,
2340                       uint16_t *phy_data)
2341 {
2342         uint32_t i;
2343         uint32_t mdic = 0;
2344         const uint32_t phy_addr = 1;
2345
2346         DEBUGFUNC("e1000_read_phy_reg_ex");
2347         
2348         if(reg_addr > MAX_PHY_REG_ADDRESS) {
2349                 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2350                 return -E1000_ERR_PARAM;
2351         }
2352         
2353         if(hw->mac_type > e1000_82543) {
2354                 /* Set up Op-code, Phy Address, and register address in the MDI
2355                  * Control register.  The MAC will take care of interfacing with the
2356                  * PHY to retrieve the desired data.
2357                  */
2358                 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
2359                         (phy_addr << E1000_MDIC_PHY_SHIFT) | 
2360                         (E1000_MDIC_OP_READ));
2361                 
2362                 E1000_WRITE_REG(hw, MDIC, mdic);
2363
2364                 /* Poll the ready bit to see if the MDI read completed */
2365                 for(i = 0; i < 64; i++) {
2366                         udelay(50);
2367                         mdic = E1000_READ_REG(hw, MDIC);
2368                         if(mdic & E1000_MDIC_READY) break;
2369                 }
2370                 if(!(mdic & E1000_MDIC_READY)) {
2371                         DEBUGOUT("MDI Read did not complete\n");
2372                         return -E1000_ERR_PHY;
2373                 }
2374                 if(mdic & E1000_MDIC_ERROR) {
2375                         DEBUGOUT("MDI Error\n");
2376                         return -E1000_ERR_PHY;
2377                 }
2378                 *phy_data = (uint16_t) mdic;
2379         } else {
2380                 /* We must first send a preamble through the MDIO pin to signal the
2381                  * beginning of an MII instruction.  This is done by sending 32
2382                  * consecutive "1" bits.
2383                  */
2384                 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2385                 
2386                 /* Now combine the next few fields that are required for a read
2387                  * operation.  We use this method instead of calling the
2388                  * e1000_shift_out_mdi_bits routine five different times. The format of
2389                  * a MII read instruction consists of a shift out of 14 bits and is
2390                  * defined as follows:
2391                  *    <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
2392                  * followed by a shift in of 18 bits.  This first two bits shifted in
2393                  * are TurnAround bits used to avoid contention on the MDIO pin when a
2394                  * READ operation is performed.  These two bits are thrown away
2395                  * followed by a shift in of 16 bits which contains the desired data.
2396                  */
2397                 mdic = ((reg_addr) | (phy_addr << 5) | 
2398                         (PHY_OP_READ << 10) | (PHY_SOF << 12));
2399                 
2400                 e1000_shift_out_mdi_bits(hw, mdic, 14);
2401                 
2402                 /* Now that we've shifted out the read command to the MII, we need to
2403                  * "shift in" the 16-bit value (18 total bits) of the requested PHY
2404                  * register address.
2405                  */
2406                 *phy_data = e1000_shift_in_mdi_bits(hw);
2407         }
2408         return E1000_SUCCESS;
2409 }
2410
2411 /******************************************************************************
2412 * Writes a value to a PHY register
2413 *
2414 * hw - Struct containing variables accessed by shared code
2415 * reg_addr - address of the PHY register to write
2416 * data - data to write to the PHY
2417 ******************************************************************************/
2418 static int 
2419 e1000_write_phy_reg(struct e1000_hw *hw,
2420                     uint32_t reg_addr,
2421                     uint16_t phy_data)
2422 {
2423         uint32_t ret_val;
2424
2425         DEBUGFUNC("e1000_write_phy_reg");
2426
2427         if(hw->phy_type == e1000_phy_igp &&
2428            (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2429                 if((ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2430                                                      (uint16_t)reg_addr)))
2431                         return ret_val;
2432         }
2433
2434         ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr,
2435                                          phy_data);
2436
2437         return ret_val;
2438 }
2439
2440 static int
2441 e1000_write_phy_reg_ex(struct e1000_hw *hw,
2442                        uint32_t reg_addr,
2443                        uint16_t phy_data)
2444 {
2445         uint32_t i;
2446         uint32_t mdic = 0;
2447         const uint32_t phy_addr = 1;
2448         
2449         DEBUGFUNC("e1000_write_phy_reg_ex");
2450         
2451         if(reg_addr > MAX_PHY_REG_ADDRESS) {
2452                 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2453                 return -E1000_ERR_PARAM;
2454         }
2455         
2456         if(hw->mac_type > e1000_82543) {
2457                 /* Set up Op-code, Phy Address, register address, and data intended
2458                  * for the PHY register in the MDI Control register.  The MAC will take
2459                  * care of interfacing with the PHY to send the desired data.
2460                  */
2461                 mdic = (((uint32_t) phy_data) |
2462                         (reg_addr << E1000_MDIC_REG_SHIFT) |
2463                         (phy_addr << E1000_MDIC_PHY_SHIFT) | 
2464                         (E1000_MDIC_OP_WRITE));
2465                 
2466                 E1000_WRITE_REG(hw, MDIC, mdic);
2467                 
2468                 /* Poll the ready bit to see if the MDI read completed */
2469                 for(i = 0; i < 640; i++) {
2470                         udelay(5);
2471                         mdic = E1000_READ_REG(hw, MDIC);
2472                         if(mdic & E1000_MDIC_READY) break;
2473                 }
2474                 if(!(mdic & E1000_MDIC_READY)) {
2475                         DEBUGOUT("MDI Write did not complete\n");
2476                         return -E1000_ERR_PHY;
2477                 }
2478         } else {
2479                 /* We'll need to use the SW defined pins to shift the write command
2480                  * out to the PHY. We first send a preamble to the PHY to signal the
2481                  * beginning of the MII instruction.  This is done by sending 32 
2482                  * consecutive "1" bits.
2483                  */
2484                 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2485                 
2486                 /* Now combine the remaining required fields that will indicate a 
2487                  * write operation. We use this method instead of calling the
2488                  * e1000_shift_out_mdi_bits routine for each field in the command. The
2489                  * format of a MII write instruction is as follows:
2490                  * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
2491                  */
2492                 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
2493                         (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
2494                 mdic <<= 16;
2495                 mdic |= (uint32_t) phy_data;
2496                 
2497                 e1000_shift_out_mdi_bits(hw, mdic, 32);
2498         }
2499
2500         return E1000_SUCCESS;
2501 }
2502
2503 /******************************************************************************
2504 * Returns the PHY to the power-on reset state
2505 *
2506 * hw - Struct containing variables accessed by shared code
2507 ******************************************************************************/
2508 static void
2509 e1000_phy_hw_reset(struct e1000_hw *hw)
2510 {
2511         uint32_t ctrl, ctrl_ext;
2512
2513         DEBUGFUNC("e1000_phy_hw_reset");
2514         
2515         DEBUGOUT("Resetting Phy...\n");
2516         
2517         if(hw->mac_type > e1000_82543) {
2518                 /* Read the device control register and assert the E1000_CTRL_PHY_RST
2519                  * bit. Then, take it out of reset.
2520                  */
2521                 ctrl = E1000_READ_REG(hw, CTRL);
2522                 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
2523                 E1000_WRITE_FLUSH(hw);
2524                 mdelay(10);
2525                 E1000_WRITE_REG(hw, CTRL, ctrl);
2526                 E1000_WRITE_FLUSH(hw);
2527         } else {
2528                 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
2529                  * bit to put the PHY into reset. Then, take it out of reset.
2530                  */
2531                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
2532                 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
2533                 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
2534                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2535                 E1000_WRITE_FLUSH(hw);
2536                 mdelay(10);
2537                 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
2538                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2539                 E1000_WRITE_FLUSH(hw);
2540         }
2541         udelay(150);
2542 }
2543
2544 /******************************************************************************
2545 * Resets the PHY
2546 *
2547 * hw - Struct containing variables accessed by shared code
2548 *
2549 * Sets bit 15 of the MII Control regiser
2550 ******************************************************************************/
2551 static int 
2552 e1000_phy_reset(struct e1000_hw *hw)
2553 {
2554         int32_t ret_val;
2555         uint16_t phy_data;
2556
2557         DEBUGFUNC("e1000_phy_reset");
2558
2559         if(hw->mac_type != e1000_82541_rev_2) {
2560                 if((ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data)))
2561                         return ret_val;
2562                 
2563                 phy_data |= MII_CR_RESET;
2564                 if((ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data)))
2565                         return ret_val;
2566                 
2567                 udelay(1);
2568         } else e1000_phy_hw_reset(hw);
2569
2570         if(hw->phy_type == e1000_phy_igp)
2571                 e1000_phy_init_script(hw);
2572
2573         return E1000_SUCCESS;
2574 }
2575
2576 /******************************************************************************
2577 * Probes the expected PHY address for known PHY IDs
2578 *
2579 * hw - Struct containing variables accessed by shared code
2580 ******************************************************************************/
2581 static int
2582 e1000_detect_gig_phy(struct e1000_hw *hw)
2583 {
2584         int32_t phy_init_status, ret_val;
2585         uint16_t phy_id_high, phy_id_low;
2586         boolean_t match = FALSE;
2587
2588         DEBUGFUNC("e1000_detect_gig_phy");
2589         
2590         /* Read the PHY ID Registers to identify which PHY is onboard. */
2591         if((ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high)))
2592                 return ret_val;
2593
2594         hw->phy_id = (uint32_t) (phy_id_high << 16);
2595         udelay(20);
2596         if((ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low)))
2597                 return ret_val;
2598         
2599         hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
2600 #ifdef LINUX_DRIVER
2601         hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
2602 #endif
2603         
2604         switch(hw->mac_type) {
2605         case e1000_82543:
2606                 if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
2607                 break;
2608         case e1000_82544:
2609                 if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
2610                 break;
2611         case e1000_82540:
2612         case e1000_82545:
2613         case e1000_82545_rev_3:
2614         case e1000_82546:
2615         case e1000_82546_rev_3:
2616                 if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
2617                 break;
2618         case e1000_82541:
2619         case e1000_82541_rev_2:
2620         case e1000_82547:
2621         case e1000_82547_rev_2:
2622                 if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
2623                 break;
2624         default:
2625                 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
2626                 return -E1000_ERR_CONFIG;
2627         }
2628         phy_init_status = e1000_set_phy_type(hw);
2629
2630         if ((match) && (phy_init_status == E1000_SUCCESS)) {
2631                 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
2632                 return E1000_SUCCESS;
2633         }
2634         DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
2635         return -E1000_ERR_PHY;
2636 }
2637
2638 /******************************************************************************
2639  * Sets up eeprom variables in the hw struct.  Must be called after mac_type
2640  * is configured.
2641  *
2642  * hw - Struct containing variables accessed by shared code
2643  *****************************************************************************/
2644 static void
2645 e1000_init_eeprom_params(struct e1000_hw *hw)
2646 {
2647         struct e1000_eeprom_info *eeprom = &hw->eeprom;
2648         uint32_t eecd = E1000_READ_REG(hw, EECD);
2649         uint16_t eeprom_size;
2650
2651         DEBUGFUNC("e1000_init_eeprom_params");
2652
2653         switch (hw->mac_type) {
2654         case e1000_82542_rev2_0:
2655         case e1000_82542_rev2_1:
2656         case e1000_82543:
2657         case e1000_82544:
2658                 eeprom->type = e1000_eeprom_microwire;
2659                 eeprom->word_size = 64;
2660                 eeprom->opcode_bits = 3;
2661                 eeprom->address_bits = 6;
2662                 eeprom->delay_usec = 50;
2663                 break;
2664         case e1000_82540:
2665         case e1000_82545:
2666         case e1000_82545_rev_3:
2667         case e1000_82546:
2668         case e1000_82546_rev_3:
2669                 eeprom->type = e1000_eeprom_microwire;
2670                 eeprom->opcode_bits = 3;
2671                 eeprom->delay_usec = 50;
2672                 if(eecd & E1000_EECD_SIZE) {
2673                         eeprom->word_size = 256;
2674                         eeprom->address_bits = 8;
2675                 } else {
2676                         eeprom->word_size = 64;
2677                         eeprom->address_bits = 6;
2678                 }
2679                 break;
2680         case e1000_82541:
2681         case e1000_82541_rev_2:
2682         case e1000_82547:
2683         case e1000_82547_rev_2:
2684                 if (eecd & E1000_EECD_TYPE) {
2685                         eeprom->type = e1000_eeprom_spi;
2686                         if (eecd & E1000_EECD_ADDR_BITS) {
2687                                 eeprom->page_size = 32;
2688                                 eeprom->address_bits = 16;
2689                         } else {
2690                                 eeprom->page_size = 8;
2691                                 eeprom->address_bits = 8;
2692                         }
2693                 } else {
2694                         eeprom->type = e1000_eeprom_microwire;
2695                         eeprom->opcode_bits = 3;
2696                         eeprom->delay_usec = 50;
2697                         if (eecd & E1000_EECD_ADDR_BITS) {
2698                                 eeprom->word_size = 256;
2699                                 eeprom->address_bits = 8;
2700                         } else {
2701                                 eeprom->word_size = 64;
2702                                 eeprom->address_bits = 6;
2703                         }
2704                 }
2705                 break;
2706         default:
2707                 eeprom->type = e1000_eeprom_spi;
2708                 if (eecd & E1000_EECD_ADDR_BITS) {
2709                         eeprom->page_size = 32;
2710                         eeprom->address_bits = 16;
2711                 } else {
2712                         eeprom->page_size = 8;
2713                         eeprom->address_bits = 8;
2714                 }
2715                 break;
2716         }
2717
2718         if (eeprom->type == e1000_eeprom_spi) {
2719                 eeprom->opcode_bits = 8;
2720                 eeprom->delay_usec = 1;
2721                 eeprom->word_size = 64;
2722                 if (e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size) == 0) {
2723                         eeprom_size &= EEPROM_SIZE_MASK;
2724
2725                         switch (eeprom_size) {
2726                         case EEPROM_SIZE_16KB:
2727                                 eeprom->word_size = 8192;
2728                                 break;
2729                         case EEPROM_SIZE_8KB:
2730                                 eeprom->word_size = 4096;
2731                                 break;
2732                         case EEPROM_SIZE_4KB:
2733                                 eeprom->word_size = 2048;
2734                                 break;
2735                         case EEPROM_SIZE_2KB:
2736                                 eeprom->word_size = 1024;
2737                                 break;
2738                         case EEPROM_SIZE_1KB:
2739                                 eeprom->word_size = 512;
2740                                 break;
2741                         case EEPROM_SIZE_512B:
2742                                 eeprom->word_size = 256;
2743                                 break;
2744                         case EEPROM_SIZE_128B:
2745                         default:
2746                                 break;
2747                         }
2748                 }
2749         }
2750 }
2751
2752 /******************************************************************************
2753  * Raises the EEPROM's clock input.
2754  *
2755  * hw - Struct containing variables accessed by shared code
2756  * eecd - EECD's current value
2757  *****************************************************************************/
2758 static void
2759 e1000_raise_ee_clk(struct e1000_hw *hw,
2760                    uint32_t *eecd)
2761 {
2762         /* Raise the clock input to the EEPROM (by setting the SK bit), and then
2763          * wait <delay> microseconds.
2764          */
2765         *eecd = *eecd | E1000_EECD_SK;
2766         E1000_WRITE_REG(hw, EECD, *eecd);
2767         E1000_WRITE_FLUSH(hw);
2768         udelay(hw->eeprom.delay_usec);
2769 }
2770
2771 /******************************************************************************
2772  * Lowers the EEPROM's clock input.
2773  *
2774  * hw - Struct containing variables accessed by shared code 
2775  * eecd - EECD's current value
2776  *****************************************************************************/
2777 static void
2778 e1000_lower_ee_clk(struct e1000_hw *hw,
2779                    uint32_t *eecd)
2780 {
2781         /* Lower the clock input to the EEPROM (by clearing the SK bit), and then 
2782          * wait 50 microseconds. 
2783          */
2784         *eecd = *eecd & ~E1000_EECD_SK;
2785         E1000_WRITE_REG(hw, EECD, *eecd);
2786         E1000_WRITE_FLUSH(hw);
2787         udelay(hw->eeprom.delay_usec);
2788 }
2789
2790 /******************************************************************************
2791  * Shift data bits out to the EEPROM.
2792  *
2793  * hw - Struct containing variables accessed by shared code
2794  * data - data to send to the EEPROM
2795  * count - number of bits to shift out
2796  *****************************************************************************/
2797 static void
2798 e1000_shift_out_ee_bits(struct e1000_hw *hw,
2799                         uint16_t data,
2800                         uint16_t count)
2801 {
2802         struct e1000_eeprom_info *eeprom = &hw->eeprom;
2803         uint32_t eecd;
2804         uint32_t mask;
2805         
2806         /* We need to shift "count" bits out to the EEPROM. So, value in the
2807          * "data" parameter will be shifted out to the EEPROM one bit at a time.
2808          * In order to do this, "data" must be broken down into bits. 
2809          */
2810         mask = 0x01 << (count - 1);
2811         eecd = E1000_READ_REG(hw, EECD);
2812         if (eeprom->type == e1000_eeprom_microwire) {
2813                 eecd &= ~E1000_EECD_DO;
2814         } else if (eeprom->type == e1000_eeprom_spi) {
2815                 eecd |= E1000_EECD_DO;
2816         }
2817         do {
2818                 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
2819                  * and then raising and then lowering the clock (the SK bit controls
2820                  * the clock input to the EEPROM).  A "0" is shifted out to the EEPROM
2821                  * by setting "DI" to "0" and then raising and then lowering the clock.
2822                  */
2823                 eecd &= ~E1000_EECD_DI;
2824                 
2825                 if(data & mask)
2826                         eecd |= E1000_EECD_DI;
2827                 
2828                 E1000_WRITE_REG(hw, EECD, eecd);
2829                 E1000_WRITE_FLUSH(hw);
2830                 
2831                 udelay(eeprom->delay_usec);
2832                 
2833                 e1000_raise_ee_clk(hw, &eecd);
2834                 e1000_lower_ee_clk(hw, &eecd);
2835                 
2836                 mask = mask >> 1;
2837                 
2838         } while(mask);
2839
2840         /* We leave the "DI" bit set to "0" when we leave this routine. */
2841         eecd &= ~E1000_EECD_DI;
2842         E1000_WRITE_REG(hw, EECD, eecd);
2843 }
2844
2845 /******************************************************************************
2846  * Shift data bits in from the EEPROM
2847  *
2848  * hw - Struct containing variables accessed by shared code
2849  *****************************************************************************/
2850 static uint16_t
2851 e1000_shift_in_ee_bits(struct e1000_hw *hw,
2852                        uint16_t count)
2853 {
2854         uint32_t eecd;
2855         uint32_t i;
2856         uint16_t data;
2857         
2858         /* In order to read a register from the EEPROM, we need to shift 'count' 
2859          * bits in from the EEPROM. Bits are "shifted in" by raising the clock
2860          * input to the EEPROM (setting the SK bit), and then reading the value of
2861          * the "DO" bit.  During this "shifting in" process the "DI" bit should
2862          * always be clear.
2863          */
2864         
2865         eecd = E1000_READ_REG(hw, EECD);
2866         
2867         eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
2868         data = 0;
2869         
2870         for(i = 0; i < count; i++) {
2871                 data = data << 1;
2872                 e1000_raise_ee_clk(hw, &eecd);
2873                 
2874                 eecd = E1000_READ_REG(hw, EECD);
2875                 
2876                 eecd &= ~(E1000_EECD_DI);
2877                 if(eecd & E1000_EECD_DO)
2878                         data |= 1;
2879                 
2880                 e1000_lower_ee_clk(hw, &eecd);
2881         }
2882         
2883         return data;
2884 }
2885
2886 /******************************************************************************
2887  * Prepares EEPROM for access
2888  *
2889  * hw - Struct containing variables accessed by shared code
2890  *
2891  * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 
2892  * function should be called before issuing a command to the EEPROM.
2893  *****************************************************************************/
2894 static int32_t
2895 e1000_acquire_eeprom(struct e1000_hw *hw)
2896 {
2897         struct e1000_eeprom_info *eeprom = &hw->eeprom;
2898         uint32_t eecd, i=0;
2899
2900         eecd = E1000_READ_REG(hw, EECD);
2901
2902         /* Request EEPROM Access */
2903         if(hw->mac_type > e1000_82544) {
2904                 eecd |= E1000_EECD_REQ;
2905                 E1000_WRITE_REG(hw, EECD, eecd);
2906                 eecd = E1000_READ_REG(hw, EECD);
2907                 while((!(eecd & E1000_EECD_GNT)) &&
2908                       (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
2909                         i++;
2910                         udelay(5);
2911                         eecd = E1000_READ_REG(hw, EECD);
2912                 }
2913                 if(!(eecd & E1000_EECD_GNT)) {
2914                         eecd &= ~E1000_EECD_REQ;
2915                         E1000_WRITE_REG(hw, EECD, eecd);
2916                         DEBUGOUT("Could not acquire EEPROM grant\n");
2917                         return -E1000_ERR_EEPROM;
2918                 }
2919         }
2920
2921         /* Setup EEPROM for Read/Write */
2922
2923         if (eeprom->type == e1000_eeprom_microwire) {
2924                 /* Clear SK and DI */
2925                 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
2926                 E1000_WRITE_REG(hw, EECD, eecd);
2927
2928                 /* Set CS */
2929                 eecd |= E1000_EECD_CS;
2930                 E1000_WRITE_REG(hw, EECD, eecd);
2931         } else if (eeprom->type == e1000_eeprom_spi) {
2932                 /* Clear SK and CS */
2933                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
2934                 E1000_WRITE_REG(hw, EECD, eecd);
2935                 udelay(1);
2936         }
2937
2938         return E1000_SUCCESS;
2939 }
2940
2941 /******************************************************************************
2942  * Returns EEPROM to a "standby" state
2943  * 
2944  * hw - Struct containing variables accessed by shared code
2945  *****************************************************************************/
2946 static void
2947 e1000_standby_eeprom(struct e1000_hw *hw)
2948 {
2949         struct e1000_eeprom_info *eeprom = &hw->eeprom;
2950         uint32_t eecd;
2951         
2952         eecd = E1000_READ_REG(hw, EECD);
2953
2954         if(eeprom->type == e1000_eeprom_microwire) {
2955
2956                 /* Deselect EEPROM */
2957                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
2958                 E1000_WRITE_REG(hw, EECD, eecd);
2959                 E1000_WRITE_FLUSH(hw);
2960                 udelay(eeprom->delay_usec);
2961         
2962                 /* Clock high */
2963                 eecd |= E1000_EECD_SK;
2964                 E1000_WRITE_REG(hw, EECD, eecd);
2965                 E1000_WRITE_FLUSH(hw);
2966                 udelay(eeprom->delay_usec);
2967         
2968                 /* Select EEPROM */
2969                 eecd |= E1000_EECD_CS;
2970                 E1000_WRITE_REG(hw, EECD, eecd);
2971                 E1000_WRITE_FLUSH(hw);
2972                 udelay(eeprom->delay_usec);
2973
2974                 /* Clock low */
2975                 eecd &= ~E1000_EECD_SK;
2976                 E1000_WRITE_REG(hw, EECD, eecd);
2977                 E1000_WRITE_FLUSH(hw);
2978                 udelay(eeprom->delay_usec);
2979         } else if(eeprom->type == e1000_eeprom_spi) {
2980                 /* Toggle CS to flush commands */
2981                 eecd |= E1000_EECD_CS;
2982                 E1000_WRITE_REG(hw, EECD, eecd);
2983                 E1000_WRITE_FLUSH(hw);
2984                 udelay(eeprom->delay_usec);
2985                 eecd &= ~E1000_EECD_CS;
2986                 E1000_WRITE_REG(hw, EECD, eecd);
2987                 E1000_WRITE_FLUSH(hw);
2988                 udelay(eeprom->delay_usec);
2989         }
2990 }
2991
2992 /******************************************************************************
2993  * Terminates a command by inverting the EEPROM's chip select pin
2994  *
2995  * hw - Struct containing variables accessed by shared code
2996  *****************************************************************************/
2997 static void
2998 e1000_release_eeprom(struct e1000_hw *hw)
2999 {
3000         uint32_t eecd;
3001
3002         eecd = E1000_READ_REG(hw, EECD);
3003
3004         if (hw->eeprom.type == e1000_eeprom_spi) {
3005                 eecd |= E1000_EECD_CS;  /* Pull CS high */
3006                 eecd &= ~E1000_EECD_SK; /* Lower SCK */
3007
3008                 E1000_WRITE_REG(hw, EECD, eecd);
3009
3010                 udelay(hw->eeprom.delay_usec);
3011         } else if(hw->eeprom.type == e1000_eeprom_microwire) {
3012                 /* cleanup eeprom */
3013
3014                 /* CS on Microwire is active-high */
3015                 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
3016
3017                 E1000_WRITE_REG(hw, EECD, eecd);
3018
3019                 /* Rising edge of clock */
3020                 eecd |= E1000_EECD_SK;
3021                 E1000_WRITE_REG(hw, EECD, eecd);
3022                 E1000_WRITE_FLUSH(hw);
3023                 udelay(hw->eeprom.delay_usec);
3024
3025                 /* Falling edge of clock */
3026                 eecd &= ~E1000_EECD_SK;
3027                 E1000_WRITE_REG(hw, EECD, eecd);
3028                 E1000_WRITE_FLUSH(hw);
3029                 udelay(hw->eeprom.delay_usec);
3030         }
3031
3032         /* Stop requesting EEPROM access */
3033         if(hw->mac_type > e1000_82544) {
3034                 eecd &= ~E1000_EECD_REQ;
3035                 E1000_WRITE_REG(hw, EECD, eecd);
3036         }
3037 }
3038
3039 /******************************************************************************
3040  * Reads a 16 bit word from the EEPROM.
3041  *
3042  * hw - Struct containing variables accessed by shared code
3043  *****************************************************************************/
3044 static int32_t
3045 e1000_spi_eeprom_ready(struct e1000_hw *hw)
3046 {
3047         uint16_t retry_count = 0;
3048         uint8_t spi_stat_reg;
3049
3050         /* Read "Status Register" repeatedly until the LSB is cleared.  The
3051          * EEPROM will signal that the command has been completed by clearing
3052          * bit 0 of the internal status register.  If it's not cleared within
3053          * 5 milliseconds, then error out.
3054          */
3055         retry_count = 0;
3056         do {
3057                 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
3058                 hw->eeprom.opcode_bits);
3059                 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
3060                 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
3061                         break;
3062
3063                 udelay(5);
3064                 retry_count += 5;
3065
3066         } while(retry_count < EEPROM_MAX_RETRY_SPI);
3067
3068         /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
3069          * only 0-5mSec on 5V devices)
3070          */
3071         if(retry_count >= EEPROM_MAX_RETRY_SPI) {
3072                 DEBUGOUT("SPI EEPROM Status error\n");
3073                 return -E1000_ERR_EEPROM;
3074         }
3075
3076         return E1000_SUCCESS;
3077 }
3078
3079 /******************************************************************************
3080  * Reads a 16 bit word from the EEPROM.
3081  *
3082  * hw - Struct containing variables accessed by shared code
3083  * offset - offset of  word in the EEPROM to read
3084  * data - word read from the EEPROM
3085  * words - number of words to read
3086  *****************************************************************************/
3087 static int
3088 e1000_read_eeprom(struct e1000_hw *hw,
3089                   uint16_t offset,
3090                   uint16_t words,
3091                   uint16_t *data)
3092 {
3093         struct e1000_eeprom_info *eeprom = &hw->eeprom;
3094         uint32_t i = 0;
3095         
3096         DEBUGFUNC("e1000_read_eeprom");
3097
3098         /* A check for invalid values:  offset too large, too many words, and not
3099          * enough words.
3100          */
3101         if((offset > eeprom->word_size) || (words > eeprom->word_size - offset) ||
3102            (words == 0)) {
3103                 DEBUGOUT("\"words\" parameter out of bounds\n");
3104                 return -E1000_ERR_EEPROM;
3105         }
3106
3107         /*  Prepare the EEPROM for reading  */
3108         if(e1000_acquire_eeprom(hw) != E1000_SUCCESS)
3109                 return -E1000_ERR_EEPROM;
3110
3111         if(eeprom->type == e1000_eeprom_spi) {
3112                 uint16_t word_in;
3113                 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
3114
3115                 if(e1000_spi_eeprom_ready(hw)) {
3116                         e1000_release_eeprom(hw);
3117                         return -E1000_ERR_EEPROM;
3118                 }
3119
3120                 e1000_standby_eeprom(hw);
3121
3122                 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
3123                 if((eeprom->address_bits == 8) && (offset >= 128))
3124                         read_opcode |= EEPROM_A8_OPCODE_SPI;
3125
3126                 /* Send the READ command (opcode + addr)  */
3127                 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
3128                 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
3129
3130                 /* Read the data.  The address of the eeprom internally increments with
3131                  * each byte (spi) being read, saving on the overhead of eeprom setup
3132                  * and tear-down.  The address counter will roll over if reading beyond
3133                  * the size of the eeprom, thus allowing the entire memory to be read
3134                  * starting from any offset. */
3135                 for (i = 0; i < words; i++) {
3136                         word_in = e1000_shift_in_ee_bits(hw, 16);
3137                         data[i] = (word_in >> 8) | (word_in << 8);
3138                 }
3139         } else if(eeprom->type == e1000_eeprom_microwire) {
3140                 for (i = 0; i < words; i++) {
3141                         /*  Send the READ command (opcode + addr)  */
3142                         e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
3143                                                 eeprom->opcode_bits);
3144                         e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
3145                                                 eeprom->address_bits);
3146
3147                         /* Read the data.  For microwire, each word requires the overhead
3148                          * of eeprom setup and tear-down. */
3149                         data[i] = e1000_shift_in_ee_bits(hw, 16);
3150                         e1000_standby_eeprom(hw);
3151                 }
3152         }
3153
3154         /* End this read operation */
3155         e1000_release_eeprom(hw);
3156
3157         return E1000_SUCCESS;
3158 }
3159
3160 /******************************************************************************
3161  * Verifies that the EEPROM has a valid checksum
3162  * 
3163  * hw - Struct containing variables accessed by shared code
3164  *
3165  * Reads the first 64 16 bit words of the EEPROM and sums the values read.
3166  * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
3167  * valid.
3168  *****************************************************************************/
3169 static int
3170 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
3171 {
3172         uint16_t checksum = 0;
3173         uint16_t i, eeprom_data;
3174
3175         DEBUGFUNC("e1000_validate_eeprom_checksum");
3176
3177         for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
3178                 if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3179                         DEBUGOUT("EEPROM Read Error\n");
3180                         return -E1000_ERR_EEPROM;
3181                 }
3182                 checksum += eeprom_data;
3183         }
3184         
3185         if(checksum == (uint16_t) EEPROM_SUM)
3186                 return E1000_SUCCESS;
3187         else {
3188                 DEBUGOUT("EEPROM Checksum Invalid\n");    
3189                 return -E1000_ERR_EEPROM;
3190         }
3191 }
3192
3193 /******************************************************************************
3194  * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
3195  * second function of dual function devices
3196  *
3197  * hw - Struct containing variables accessed by shared code
3198  *****************************************************************************/
3199 static int 
3200 e1000_read_mac_addr(struct e1000_hw *hw)
3201 {
3202         uint16_t offset;
3203         uint16_t eeprom_data;
3204         int i;
3205
3206         DEBUGFUNC("e1000_read_mac_addr");
3207
3208         for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
3209                 offset = i >> 1;
3210                 if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
3211                         DEBUGOUT("EEPROM Read Error\n");
3212                         return -E1000_ERR_EEPROM;
3213                 }
3214                 hw->mac_addr[i] = eeprom_data & 0xff;
3215                 hw->mac_addr[i+1] = (eeprom_data >> 8) & 0xff;
3216         }
3217         if(((hw->mac_type == e1000_82546) || (hw->mac_type == e1000_82546_rev_3)) &&
3218                 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1))
3219                 /* Invert the last bit if this is the second device */
3220                 hw->mac_addr[5] ^= 1;
3221         return E1000_SUCCESS;
3222 }
3223
3224 /******************************************************************************
3225  * Initializes receive address filters.
3226  *
3227  * hw - Struct containing variables accessed by shared code 
3228  *
3229  * Places the MAC address in receive address register 0 and clears the rest
3230  * of the receive addresss registers. Clears the multicast table. Assumes
3231  * the receiver is in reset when the routine is called.
3232  *****************************************************************************/
3233 static void
3234 e1000_init_rx_addrs(struct e1000_hw *hw)
3235 {
3236         uint32_t i;
3237         uint32_t addr_low;
3238         uint32_t addr_high;
3239         
3240         DEBUGFUNC("e1000_init_rx_addrs");
3241         
3242         /* Setup the receive address. */
3243         DEBUGOUT("Programming MAC Address into RAR[0]\n");
3244         addr_low = (hw->mac_addr[0] |
3245                 (hw->mac_addr[1] << 8) |
3246                 (hw->mac_addr[2] << 16) | (hw->mac_addr[3] << 24));
3247         
3248         addr_high = (hw->mac_addr[4] |
3249                 (hw->mac_addr[5] << 8) | E1000_RAH_AV);
3250         
3251         E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
3252         E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
3253         
3254         /* Zero out the other 15 receive addresses. */
3255         DEBUGOUT("Clearing RAR[1-15]\n");
3256         for(i = 1; i < E1000_RAR_ENTRIES; i++) {
3257                 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
3258                 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
3259         }
3260 }
3261
3262 /******************************************************************************
3263  * Clears the VLAN filer table
3264  *
3265  * hw - Struct containing variables accessed by shared code
3266  *****************************************************************************/
3267 static void
3268 e1000_clear_vfta(struct e1000_hw *hw)
3269 {
3270         uint32_t offset;
3271     
3272         for(offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
3273                 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
3274 }
3275
3276
3277 /******************************************************************************
3278  * Functions from e1000_main.c of the linux driver
3279  ******************************************************************************/
3280
3281 /**
3282  * e1000_reset - Reset the adapter
3283  */
3284
3285 static int
3286 e1000_reset(struct e1000_hw *hw)
3287 {
3288         uint32_t pba;
3289         /* Repartition Pba for greater than 9k mtu
3290          * To take effect CTRL.RST is required.
3291          */
3292
3293         if(hw->mac_type < e1000_82547) {
3294                 pba = E1000_PBA_48K;
3295         } else {
3296                 pba = E1000_PBA_30K;
3297         }
3298         E1000_WRITE_REG(hw, PBA, pba);
3299
3300         /* flow control settings */
3301 #if 0
3302         hw->fc_high_water = FC_DEFAULT_HI_THRESH;
3303         hw->fc_low_water = FC_DEFAULT_LO_THRESH;
3304         hw->fc_pause_time = FC_DEFAULT_TX_TIMER;
3305         hw->fc_send_xon = 1;
3306         hw->fc = hw->original_fc;
3307 #endif
3308         
3309         e1000_reset_hw(hw);
3310         if(hw->mac_type >= e1000_82544)
3311                 E1000_WRITE_REG(hw, WUC, 0);
3312         return e1000_init_hw(hw);
3313 }
3314
3315 /**
3316  * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
3317  * @adapter: board private structure to initialize
3318  *
3319  * e1000_sw_init initializes the Adapter private data structure.
3320  * Fields are initialized based on PCI device information and
3321  * OS network device settings (MTU size).
3322  **/
3323
3324 static int 
3325 e1000_sw_init(struct pci_device *pdev,&n