Warnings purge of drivers (continued)
[people/xl0/gpxe.git] / src / drivers / net / tlan.c
1 /**************************************************************************
2 *
3 *    tlan.c -- Etherboot device driver for the Texas Instruments ThunderLAN
4 *    Written 2003-2003 by Timothy Legge <tlegge@rogers.com>
5 *
6 *    This program is free software; you can redistribute it and/or modify
7 *    it under the terms of the GNU General Public License as published by
8 *    the Free Software Foundation; either version 2 of the License, or
9 *    (at your option) any later version.
10 *
11 *    This program is distributed in the hope that it will be useful,
12 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
13 *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14 *    GNU General Public License for more details.
15 *
16 *    You should have received a copy of the GNU General Public License
17 *    along with this program; if not, write to the Free Software
18 *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 *
20 *    Portions of this code based on:
21 *       lan.c: Linux ThunderLan Driver:
22 *
23 *       by James Banks
24 *
25 *       (C) 1997-1998 Caldera, Inc.
26 *       (C) 1998 James Banks
27 *       (C) 1999-2001 Torben Mathiasen
28 *       (C) 2002 Samuel Chessman
29 *
30 *    REVISION HISTORY:
31 *    ================
32 *    v1.0       07-08-2003      timlegge        Initial not quite working version
33 *    v1.1       07-27-2003      timlegge        Sync 5.0 and 5.1 versions
34 *    v1.2       08-19-2003      timlegge        Implement Multicast Support
35 *    v1.3       08-23-2003      timlegge        Fix the transmit Function
36 *    v1.4       01-17-2004      timlegge        Initial driver output cleanup    
37 *    
38 *    Indent Options: indent -kr -i8
39 ***************************************************************************/
40
41 #include "etherboot.h"
42 #include "nic.h"
43 #include <gpxe/pci.h>
44 #include <gpxe/ethernet.h>
45 #include "timer.h"
46 #include "tlan.h"
47
48 #define drv_version "v1.4"
49 #define drv_date "01-17-2004"
50
51 /* NIC specific static variables go here */
52 #define HZ 100
53 #define TX_TIME_OUT       (6*HZ)
54
55 /* Condensed operations for readability. */
56 #define virt_to_le32desc(addr)  cpu_to_le32(virt_to_bus(addr))
57 #define le32desc_to_virt(addr)  bus_to_virt(le32_to_cpu(addr))
58
59 static void TLan_ResetLists(struct nic *nic __unused);
60 static void TLan_ResetAdapter(struct nic *nic __unused);
61 static void TLan_FinishReset(struct nic *nic __unused);
62
63 static void TLan_EeSendStart(u16);
64 static int TLan_EeSendByte(u16, u8, int);
65 static void TLan_EeReceiveByte(u16, u8 *, int);
66 static int TLan_EeReadByte(u16 io_base, u8, u8 *);
67
68 static void TLan_PhyDetect(struct nic *nic);
69 static void TLan_PhyPowerDown(struct nic *nic);
70 static void TLan_PhyPowerUp(struct nic *nic);
71
72
73 static void TLan_SetMac(struct nic *nic __unused, int areg, unsigned char *mac);
74
75 static void TLan_PhyReset(struct nic *nic);
76 static void TLan_PhyStartLink(struct nic *nic);
77 static void TLan_PhyFinishAutoNeg(struct nic *nic);
78
79 #ifdef MONITOR
80 static void TLan_PhyMonitor(struct nic *nic);
81 #endif
82
83
84 static void refill_rx(struct nic *nic __unused);
85
86 static int TLan_MiiReadReg(struct nic *nic __unused, u16, u16, u16 *);
87 static void TLan_MiiSendData(u16, u32, unsigned);
88 static void TLan_MiiSync(u16);
89 static void TLan_MiiWriteReg(struct nic *nic __unused, u16, u16, u16);
90
91
92 static const char *media[] = {
93         "10BaseT-HD ", "10BaseT-FD ", "100baseTx-HD ",
94         "100baseTx-FD", "100baseT4", 0
95 };
96
97 /* This much match tlan_pci_tbl[]!  */
98 enum tlan_nics {
99         NETEL10 = 0, NETEL100 = 1, NETFLEX3I = 2, THUNDER = 3, NETFLEX3B =
100             4, NETEL100PI = 5,
101         NETEL100D = 6, NETEL100I = 7, OC2183 = 8, OC2325 = 9, OC2326 =
102             10, NETELLIGENT_10_100_WS_5100 = 11,
103         NETELLIGENT_10_T2 = 12
104 };
105
106 struct pci_id_info {
107         const char *name;
108         int nic_id;
109         struct match_info {
110                 u32 pci, pci_mask, subsystem, subsystem_mask;
111                 u32 revision, revision_mask;    /* Only 8 bits. */
112         } id;
113         u32 flags;
114         u16 addrOfs;            /* Address Offset */
115 };
116
117 static const struct pci_id_info tlan_pci_tbl[] = {
118         {"Compaq Netelligent 10 T PCI UTP", NETEL10,
119          {0xae340e11, 0xffffffff, 0, 0, 0, 0},
120          TLAN_ADAPTER_ACTIVITY_LED, 0x83},
121         {"Compaq Netelligent 10/100 TX PCI UTP", NETEL100,
122          {0xae320e11, 0xffffffff, 0, 0, 0, 0},
123          TLAN_ADAPTER_ACTIVITY_LED, 0x83},
124         {"Compaq Integrated NetFlex-3/P", NETFLEX3I,
125          {0xae350e11, 0xffffffff, 0, 0, 0, 0},
126          TLAN_ADAPTER_NONE, 0x83},
127         {"Compaq NetFlex-3/P", THUNDER,
128          {0xf1300e11, 0xffffffff, 0, 0, 0, 0},
129          TLAN_ADAPTER_UNMANAGED_PHY | TLAN_ADAPTER_BIT_RATE_PHY, 0x83},
130         {"Compaq NetFlex-3/P", NETFLEX3B,
131          {0xf1500e11, 0xffffffff, 0, 0, 0, 0},
132          TLAN_ADAPTER_NONE, 0x83},
133         {"Compaq Netelligent Integrated 10/100 TX UTP", NETEL100PI,
134          {0xae430e11, 0xffffffff, 0, 0, 0, 0},
135          TLAN_ADAPTER_ACTIVITY_LED, 0x83},
136         {"Compaq Netelligent Dual 10/100 TX PCI UTP", NETEL100D,
137          {0xae400e11, 0xffffffff, 0, 0, 0, 0},
138          TLAN_ADAPTER_NONE, 0x83},
139         {"Compaq Netelligent 10/100 TX Embedded UTP", NETEL100I,
140          {0xb0110e11, 0xffffffff, 0, 0, 0, 0},
141          TLAN_ADAPTER_NONE, 0x83},
142         {"Olicom OC-2183/2185", OC2183,
143          {0x0013108d, 0xffffffff, 0, 0, 0, 0},
144          TLAN_ADAPTER_USE_INTERN_10, 0x83},
145         {"Olicom OC-2325", OC2325,
146          {0x0012108d, 0xffffffff, 0, 0, 0, 0},
147          TLAN_ADAPTER_UNMANAGED_PHY, 0xF8},
148         {"Olicom OC-2326", OC2326,
149          {0x0014108d, 0xffffffff, 0, 0, 0, 0},
150          TLAN_ADAPTER_USE_INTERN_10, 0xF8},
151         {"Compaq Netelligent 10/100 TX UTP", NETELLIGENT_10_100_WS_5100,
152          {0xb0300e11, 0xffffffff, 0, 0, 0, 0},
153          TLAN_ADAPTER_ACTIVITY_LED, 0x83},
154         {"Compaq Netelligent 10 T/2 PCI UTP/Coax", NETELLIGENT_10_T2,
155          {0xb0120e11, 0xffffffff, 0, 0, 0, 0},
156          TLAN_ADAPTER_NONE, 0x83},
157         {"Compaq NetFlex-3/E", 0,       /* EISA card */
158          {0, 0, 0, 0, 0, 0},
159          TLAN_ADAPTER_ACTIVITY_LED | TLAN_ADAPTER_UNMANAGED_PHY |
160          TLAN_ADAPTER_BIT_RATE_PHY, 0x83},
161         {"Compaq NetFlex-3/E", 0,       /* EISA card */
162          {0, 0, 0, 0, 0, 0},
163          TLAN_ADAPTER_ACTIVITY_LED, 0x83},
164         {0, 0,
165          {0, 0, 0, 0, 0, 0},
166          0, 0},
167 };
168
169 struct TLanList {
170         u32 forward;
171         u16 cStat;
172         u16 frameSize;
173         struct {
174                 u32 count;
175                 u32 address;
176         } buffer[TLAN_BUFFERS_PER_LIST];
177 };
178
179 struct {
180         struct TLanList tx_ring[TLAN_NUM_TX_LISTS];
181         unsigned char txb[TLAN_MAX_FRAME_SIZE * TLAN_NUM_TX_LISTS];
182         struct TLanList rx_ring[TLAN_NUM_RX_LISTS];
183         unsigned char rxb[TLAN_MAX_FRAME_SIZE * TLAN_NUM_RX_LISTS];
184 } tlan_buffers __shared;
185 #define tx_ring tlan_buffers.tx_ring
186 #define txb tlan_buffers.txb
187 #define rx_ring tlan_buffers.rx_ring
188 #define rxb tlan_buffers.rxb
189
190 typedef u8 TLanBuffer[TLAN_MAX_FRAME_SIZE];
191
192 static int chip_idx;
193
194 /*****************************************************************
195 * TLAN Private Information Structure
196 *
197 ****************************************************************/
198 static struct tlan_private {
199         unsigned short vendor_id;       /* PCI Vendor code */
200         unsigned short dev_id;  /* PCI Device code */
201         const char *nic_name;
202         unsigned int cur_rx, dirty_rx;  /* Producer/consumer ring indicies */
203         unsigned rx_buf_sz;     /* Based on mtu + Slack */
204         struct TLanList *txList;
205         u32 txHead;
206         u32 txInProgress;
207         u32 txTail;
208         int eoc;
209         u32 phyOnline;
210         u32 aui;
211         u32 duplex;
212         u32 phy[2];
213         u32 phyNum;
214         u32 speed;
215         u8 tlanRev;
216         u8 tlanFullDuplex;
217         u8 link;
218         u8 neg_be_verbose;
219 } TLanPrivateInfo;
220
221 static struct tlan_private *priv;
222
223 static u32 BASE;
224
225 /***************************************************************
226 *       TLan_ResetLists
227 *
228 *       Returns:
229 *               Nothing
230 *       Parms:
231 *               dev     The device structure with the list
232 *                       stuctures to be reset.
233 *
234 *       This routine sets the variables associated with managing
235 *       the TLAN lists to their initial values.
236 *
237 **************************************************************/
238
239 static void TLan_ResetLists(struct nic *nic __unused)
240 {
241
242         int i;
243         struct TLanList *list;
244         priv->txHead = 0;
245         priv->txTail = 0;
246
247         for (i = 0; i < TLAN_NUM_TX_LISTS; i++) {
248                 list = &tx_ring[i];
249                 list->cStat = TLAN_CSTAT_UNUSED;
250                 list->buffer[0].address = virt_to_bus(txb + 
251                                 (i * TLAN_MAX_FRAME_SIZE)); 
252                 list->buffer[2].count = 0;
253                 list->buffer[2].address = 0;
254                 list->buffer[9].address = 0;
255         }
256
257         priv->cur_rx = 0;
258         priv->rx_buf_sz = (TLAN_MAX_FRAME_SIZE);
259 //      priv->rx_head_desc = &rx_ring[0];
260
261         /* Initialize all the Rx descriptors */
262         for (i = 0; i < TLAN_NUM_RX_LISTS; i++) {
263                 rx_ring[i].forward = virt_to_le32desc(&rx_ring[i + 1]);
264                 rx_ring[i].cStat = TLAN_CSTAT_READY;
265                 rx_ring[i].frameSize = TLAN_MAX_FRAME_SIZE;
266                 rx_ring[i].buffer[0].count =
267                     TLAN_MAX_FRAME_SIZE | TLAN_LAST_BUFFER;
268                 rx_ring[i].buffer[0].address =
269                     virt_to_le32desc(&rxb[i * TLAN_MAX_FRAME_SIZE]);
270                 rx_ring[i].buffer[1].count = 0;
271                 rx_ring[i].buffer[1].address = 0;
272         }
273
274         /* Mark the last entry as wrapping the ring */
275         rx_ring[i - 1].forward = virt_to_le32desc(&rx_ring[0]);
276         priv->dirty_rx = (unsigned int) (i - TLAN_NUM_RX_LISTS);
277
278 } /* TLan_ResetLists */
279
280 /***************************************************************
281 *       TLan_Reset
282 *
283 *       Returns:
284 *               0
285 *       Parms:
286 *               dev     Pointer to device structure of adapter
287 *                       to be reset.
288 *
289 *       This function resets the adapter and it's physical
290 *       device.  See Chap. 3, pp. 9-10 of the "ThunderLAN
291 *       Programmer's Guide" for details.  The routine tries to
292 *       implement what is detailed there, though adjustments
293 *       have been made.
294 *
295 **************************************************************/
296
297 void TLan_ResetAdapter(struct nic *nic __unused)
298 {
299         int i;
300         u32 addr;
301         u32 data;
302         u8 data8;
303
304         priv->tlanFullDuplex = FALSE;
305         priv->phyOnline = 0;
306 /*  1.  Assert reset bit. */
307
308         data = inl(BASE + TLAN_HOST_CMD);
309         data |= TLAN_HC_AD_RST;
310         outl(data, BASE + TLAN_HOST_CMD);
311
312         udelay(1000);
313
314 /*  2.  Turn off interrupts. ( Probably isn't necessary ) */
315
316         data = inl(BASE + TLAN_HOST_CMD);
317         data |= TLAN_HC_INT_OFF;
318         outl(data, BASE + TLAN_HOST_CMD);
319 /*  3.  Clear AREGs and HASHs. */
320
321         for (i = TLAN_AREG_0; i <= TLAN_HASH_2; i += 4) {
322                 TLan_DioWrite32(BASE, (u16) i, 0);
323         }
324
325 /*  4.  Setup NetConfig register. */
326
327         data =
328             TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN | TLAN_NET_CFG_PHY_EN;
329         TLan_DioWrite16(BASE, TLAN_NET_CONFIG, (u16) data);
330
331 /*  5.  Load Ld_Tmr and Ld_Thr in HOST_CMD. */
332
333         outl(TLAN_HC_LD_TMR | 0x3f, BASE + TLAN_HOST_CMD);
334         outl(TLAN_HC_LD_THR | 0x0, BASE + TLAN_HOST_CMD);
335
336 /*  6.  Unreset the MII by setting NMRST (in NetSio) to 1. */
337
338         outw(TLAN_NET_SIO, BASE + TLAN_DIO_ADR);
339         addr = BASE + TLAN_DIO_DATA + TLAN_NET_SIO;
340         TLan_SetBit(TLAN_NET_SIO_NMRST, addr);
341
342 /*  7.  Setup the remaining registers. */
343
344         if (priv->tlanRev >= 0x30) {
345                 data8 = TLAN_ID_TX_EOC | TLAN_ID_RX_EOC;
346                 TLan_DioWrite8(BASE, TLAN_INT_DIS, data8);
347         }
348         TLan_PhyDetect(nic);
349         data = TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN;
350
351         if (tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_BIT_RATE_PHY) {
352                 data |= TLAN_NET_CFG_BIT;
353                 if (priv->aui == 1) {
354                         TLan_DioWrite8(BASE, TLAN_ACOMMIT, 0x0a);
355                 } else if (priv->duplex == TLAN_DUPLEX_FULL) {
356                         TLan_DioWrite8(BASE, TLAN_ACOMMIT, 0x00);
357                         priv->tlanFullDuplex = TRUE;
358                 } else {
359                         TLan_DioWrite8(BASE, TLAN_ACOMMIT, 0x08);
360                 }
361         }
362
363         if (priv->phyNum == 0) {
364                 data |= TLAN_NET_CFG_PHY_EN;
365         }
366         TLan_DioWrite16(BASE, TLAN_NET_CONFIG, (u16) data);
367
368         if (tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_UNMANAGED_PHY) {
369                 TLan_FinishReset(nic);
370         } else {
371                 TLan_PhyPowerDown(nic);
372         }
373
374 }       /* TLan_ResetAdapter */
375
376 void TLan_FinishReset(struct nic *nic)
377 {
378
379         u8 data;
380         u32 phy;
381         u8 sio;
382         u16 status;
383         u16 partner;
384         u16 tlphy_ctl;
385         u16 tlphy_par;
386         u16 tlphy_id1, tlphy_id2;
387         int i;
388
389         phy = priv->phy[priv->phyNum];
390
391         data = TLAN_NET_CMD_NRESET | TLAN_NET_CMD_NWRAP;
392         if (priv->tlanFullDuplex) {
393                 data |= TLAN_NET_CMD_DUPLEX;
394         }
395         TLan_DioWrite8(BASE, TLAN_NET_CMD, data);
396         data = TLAN_NET_MASK_MASK4 | TLAN_NET_MASK_MASK5;
397         if (priv->phyNum == 0) {
398                 data |= TLAN_NET_MASK_MASK7;
399         }
400         TLan_DioWrite8(BASE, TLAN_NET_MASK, data);
401         TLan_DioWrite16(BASE, TLAN_MAX_RX, ((1536) + 7) & ~7);
402         TLan_MiiReadReg(nic, phy, MII_GEN_ID_HI, &tlphy_id1);
403         TLan_MiiReadReg(nic, phy, MII_GEN_ID_LO, &tlphy_id2);
404
405         if ((tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_UNMANAGED_PHY)
406             || (priv->aui)) {
407                 status = MII_GS_LINK;
408                 DBG ( "TLAN:  %s: Link forced.\n", priv->nic_name );
409         } else {
410                 TLan_MiiReadReg(nic, phy, MII_GEN_STS, &status);
411                 udelay(1000);
412                 TLan_MiiReadReg(nic, phy, MII_GEN_STS, &status);
413                 if ((status & MII_GS_LINK) &&   /* We only support link info on Nat.Sem. PHY's */
414                     (tlphy_id1 == NAT_SEM_ID1)
415                     && (tlphy_id2 == NAT_SEM_ID2)) {
416                         TLan_MiiReadReg(nic, phy, MII_AN_LPA, &partner);
417                         TLan_MiiReadReg(nic, phy, TLAN_TLPHY_PAR,
418                                         &tlphy_par);
419
420                         DBG ( "TLAN: %s: Link active with ",
421                                priv->nic_name );
422                         if (!(tlphy_par & TLAN_PHY_AN_EN_STAT)) {
423                                 DBG ( "forced 10%sMbps %s-Duplex\n",
424                                        tlphy_par & TLAN_PHY_SPEED_100 ? ""
425                                        : "0",
426                                        tlphy_par & TLAN_PHY_DUPLEX_FULL ?
427                                        "Full" : "Half" );
428                         } else {
429                                 DBG 
430                                     ( "AutoNegotiation enabled, at 10%sMbps %s-Duplex\n",
431                                      tlphy_par & TLAN_PHY_SPEED_100 ? "" :
432                                      "0",
433                                      tlphy_par & TLAN_PHY_DUPLEX_FULL ?
434                                      "Full" : "Half" );
435                                 DBG ( "TLAN: Partner capability: " );
436                                 for (i = 5; i <= 10; i++)
437                                         if (partner & (1 << i)) {
438                                                 DBG ( "%s", media[i - 5] );
439                                         }
440                                 DBG ( "\n" );
441                         }
442
443                         TLan_DioWrite8(BASE, TLAN_LED_REG, TLAN_LED_LINK);
444 #ifdef MONITOR
445                         /* We have link beat..for now anyway */
446                         priv->link = 1;
447                         /*Enabling link beat monitoring */
448                         /* TLan_SetTimer( nic, (10*HZ), TLAN_TIMER_LINK_BEAT ); */
449                         mdelay(10000);
450                         TLan_PhyMonitor(nic);
451 #endif
452                 } else if (status & MII_GS_LINK) {
453                         DBG ( "TLAN: %s: Link active\n", priv->nic_name );
454                         TLan_DioWrite8(BASE, TLAN_LED_REG, TLAN_LED_LINK);
455                 }
456         }
457
458         if (priv->phyNum == 0) {
459                 TLan_MiiReadReg(nic, phy, TLAN_TLPHY_CTL, &tlphy_ctl);
460                 tlphy_ctl |= TLAN_TC_INTEN;
461                 TLan_MiiWriteReg(nic, phy, TLAN_TLPHY_CTL, tlphy_ctl);
462                 sio = TLan_DioRead8(BASE, TLAN_NET_SIO);
463                 sio |= TLAN_NET_SIO_MINTEN;
464                 TLan_DioWrite8(BASE, TLAN_NET_SIO, sio);
465         }
466
467         if (status & MII_GS_LINK) {
468                 TLan_SetMac(nic, 0, nic->node_addr);
469                 priv->phyOnline = 1;
470                 outb((TLAN_HC_INT_ON >> 8), BASE + TLAN_HOST_CMD + 1);
471                 outl(virt_to_bus(&rx_ring), BASE + TLAN_CH_PARM);
472                 outl(TLAN_HC_GO | TLAN_HC_RT, BASE + TLAN_HOST_CMD);
473         } else {
474                 DBG 
475                     ( "TLAN: %s: Link inactive, will retry in 10 secs...\n",
476                      priv->nic_name );
477                 /* TLan_SetTimer( nic, (10*HZ), TLAN_TIMER_FINISH_RESET ); */
478                 mdelay(10000);
479                 TLan_FinishReset(nic);
480                 return;
481
482         }
483
484 }       /* TLan_FinishReset */
485
486 /**************************************************************************
487 POLL - Wait for a frame
488 ***************************************************************************/
489 static int tlan_poll(struct nic *nic, int retrieve)
490 {
491         /* return true if there's an ethernet packet ready to read */
492         /* nic->packet should contain data on return */
493         /* nic->packetlen should contain length of data */
494         u32 framesize;
495         u32 host_cmd = 0;
496         u32 ack = 1;
497         int eoc = 0;
498         int entry = priv->cur_rx % TLAN_NUM_RX_LISTS;
499         u16 tmpCStat = le32_to_cpu(rx_ring[entry].cStat);
500         u16 host_int = inw(BASE + TLAN_HOST_INT);
501
502         if ((tmpCStat & TLAN_CSTAT_FRM_CMP) && !retrieve)
503           return 1;
504
505         outw(host_int, BASE + TLAN_HOST_INT);
506
507         if (!(tmpCStat & TLAN_CSTAT_FRM_CMP))
508                 return 0;
509
510         /* printf("PI-1: 0x%hX\n", host_int); */
511         if (tmpCStat & TLAN_CSTAT_EOC)
512                 eoc = 1;
513
514         framesize = rx_ring[entry].frameSize;
515
516         nic->packetlen = framesize;
517
518         DBG ( ".%d.", (unsigned int) framesize ); 
519      
520         memcpy(nic->packet, rxb +
521                (priv->cur_rx * TLAN_MAX_FRAME_SIZE), nic->packetlen);
522
523         rx_ring[entry].cStat = 0;
524
525         DBG ( "%d", entry );  
526
527         entry = (entry + 1) % TLAN_NUM_RX_LISTS;
528         priv->cur_rx = entry;
529         if (eoc) {
530                 if ((rx_ring[entry].cStat & TLAN_CSTAT_READY) ==
531                     TLAN_CSTAT_READY) {
532                         ack |= TLAN_HC_GO | TLAN_HC_RT;
533                         host_cmd = TLAN_HC_ACK | ack | 0x001C0000;
534                         outl(host_cmd, BASE + TLAN_HOST_CMD);
535                 }
536         } else {
537                 host_cmd = TLAN_HC_ACK | ack | (0x000C0000);
538                 outl(host_cmd, BASE + TLAN_HOST_CMD);
539                 
540                 DBG ( "AC: 0x%hX\n", inw(BASE + TLAN_CH_PARM) ); 
541                 DBG ( "PI-2: 0x%hX\n", inw(BASE + TLAN_HOST_INT) );
542         }
543         refill_rx(nic);
544         return (1);             /* initially as this is called to flush the input */
545 }
546
547 static void refill_rx(struct nic *nic __unused)
548 {
549         int entry = 0;
550
551         for (;
552              (priv->cur_rx - priv->dirty_rx +
553               TLAN_NUM_RX_LISTS) % TLAN_NUM_RX_LISTS > 0;
554              priv->dirty_rx = (priv->dirty_rx + 1) % TLAN_NUM_RX_LISTS) {
555                 entry = priv->dirty_rx % TLAN_NUM_TX_LISTS;
556                 rx_ring[entry].frameSize = TLAN_MAX_FRAME_SIZE;
557                 rx_ring[entry].cStat = TLAN_CSTAT_READY;
558         }
559
560 }
561
562 /**************************************************************************
563 TRANSMIT - Transmit a frame
564 ***************************************************************************/
565 static void tlan_transmit(struct nic *nic, const char *d,       /* Destination */
566                           unsigned int t,       /* Type */
567                           unsigned int s,       /* size */
568                           const char *p)
569 {                               /* Packet */
570         u16 nstype;
571         u32 to;
572         struct TLanList *tail_list;
573         struct TLanList *head_list;
574         u8 *tail_buffer;
575         u32 ack = 0;
576         u32 host_cmd;
577         int eoc = 0;
578         u16 tmpCStat;
579         u16 host_int = inw(BASE + TLAN_HOST_INT);
580
581         int entry = 0;
582
583         DBG ( "INT0-0x%hX\n", host_int );
584
585         if (!priv->phyOnline) {
586                 printf("TRANSMIT:  %s PHY is not ready\n", priv->nic_name);
587                 return;
588         }
589
590         tail_list = priv->txList + priv->txTail;
591
592         if (tail_list->cStat != TLAN_CSTAT_UNUSED) {
593                 printf("TRANSMIT: %s is busy (Head=%p Tail=%x)\n",
594                        priv->nic_name, priv->txList, (unsigned int) priv->txTail);
595                 tx_ring[entry].cStat = TLAN_CSTAT_UNUSED;
596 //              priv->txBusyCount++;
597                 return;
598         }
599
600         tail_list->forward = 0;
601
602         tail_buffer = txb + (priv->txTail * TLAN_MAX_FRAME_SIZE);
603
604         /* send the packet to destination */
605         memcpy(tail_buffer, d, ETH_ALEN);
606         memcpy(tail_buffer + ETH_ALEN, nic->node_addr, ETH_ALEN);
607         nstype = htons((u16) t);
608         memcpy(tail_buffer + 2 * ETH_ALEN, (u8 *) & nstype, 2);
609         memcpy(tail_buffer + ETH_HLEN, p, s);
610
611         s += ETH_HLEN;
612         s &= 0x0FFF;
613         while (s < ETH_ZLEN)
614                 tail_buffer[s++] = '\0';
615
616         /*=====================================================*/
617         /* Receive
618          * 0000 0000 0001 1100
619          * 0000 0000 0000 1100
620          * 0000 0000 0000 0011 = 0x0003
621          *
622          * 0000 0000 0000 0000 0000 0000 0000 0011
623          * 0000 0000 0000 1100 0000 0000 0000 0000 = 0x000C0000
624          *
625          * Transmit
626          * 0000 0000 0001 1100
627          * 0000 0000 0000 0100
628          * 0000 0000 0000 0001 = 0x0001
629          *
630          * 0000 0000 0000 0000 0000 0000 0000 0001
631          * 0000 0000 0000 0100 0000 0000 0000 0000 = 0x00040000
632          * */
633
634         /* Setup the transmit descriptor */
635         tail_list->frameSize = (u16) s;
636         tail_list->buffer[0].count = TLAN_LAST_BUFFER | (u32) s;
637         tail_list->buffer[1].count = 0;
638         tail_list->buffer[1].address = 0;
639
640         tail_list->cStat = TLAN_CSTAT_READY;
641
642         DBG ( "INT1-0x%hX\n", inw(BASE + TLAN_HOST_INT) );
643
644         if (!priv->txInProgress) {
645                 priv->txInProgress = 1;
646                 outl(virt_to_le32desc(tail_list), BASE + TLAN_CH_PARM);
647                 outl(TLAN_HC_GO, BASE + TLAN_HOST_CMD);
648         } else {
649                 if (priv->txTail == 0) {
650                         DBG ( "Out buffer\n" );
651                         (priv->txList + (TLAN_NUM_TX_LISTS - 1))->forward =
652                             virt_to_le32desc(tail_list);
653                 } else {
654                         DBG ( "Fix this \n" );
655                         (priv->txList + (priv->txTail - 1))->forward =
656                             virt_to_le32desc(tail_list);
657                 }
658         }
659         
660         CIRC_INC(priv->txTail, TLAN_NUM_TX_LISTS);
661
662         DBG ( "INT2-0x%hX\n", inw(BASE + TLAN_HOST_INT) );
663
664         to = currticks() + TX_TIME_OUT;
665         while ((tail_list->cStat == TLAN_CSTAT_READY) && currticks() < to);
666
667         head_list = priv->txList + priv->txHead;
668         while (((tmpCStat = head_list->cStat) & TLAN_CSTAT_FRM_CMP) 
669                         && (ack < 255)) {
670                 ack++;
671                 if(tmpCStat & TLAN_CSTAT_EOC)
672                         eoc =1;
673                 head_list->cStat = TLAN_CSTAT_UNUSED;
674                 CIRC_INC(priv->txHead, TLAN_NUM_TX_LISTS);
675                 head_list = priv->txList + priv->txHead;
676                 
677         }
678         if(!ack)
679                 printf("Incomplete TX Frame\n");
680
681         if(eoc) {
682                 head_list = priv->txList + priv->txHead;
683                 if ((head_list->cStat & TLAN_CSTAT_READY) == TLAN_CSTAT_READY) {
684                         outl(virt_to_le32desc(head_list), BASE + TLAN_CH_PARM);
685                         ack |= TLAN_HC_GO;
686                 } else {
687                         priv->txInProgress = 0;
688                 }
689         }
690         if(ack) {
691                 host_cmd = TLAN_HC_ACK | ack;
692                 outl(host_cmd, BASE + TLAN_HOST_CMD);
693         }
694         
695         if(priv->tlanRev < 0x30 ) {
696                 ack = 1;
697                 head_list = priv->txList + priv->txHead;
698                 if ((head_list->cStat & TLAN_CSTAT_READY) == TLAN_CSTAT_READY) {
699                         outl(virt_to_le32desc(head_list), BASE + TLAN_CH_PARM);
700                         ack |= TLAN_HC_GO;
701                 } else {
702                         priv->txInProgress = 0;
703                 }
704                 host_cmd = TLAN_HC_ACK | ack | 0x00140000;
705                 outl(host_cmd, BASE + TLAN_HOST_CMD);
706                 
707         }
708                         
709         if (currticks() >= to) {
710                 printf("TX Time Out");
711         }
712 }
713
714 /**************************************************************************
715 DISABLE - Turn off ethernet interface
716 ***************************************************************************/
717 static void tlan_disable ( struct nic *nic __unused ) {
718         /* put the card in its initial state */
719         /* This function serves 3 purposes.
720          * This disables DMA and interrupts so we don't receive
721          *  unexpected packets or interrupts from the card after
722          *  etherboot has finished.
723          * This frees resources so etherboot may use
724          *  this driver on another interface
725          * This allows etherboot to reinitialize the interface
726          *  if something is something goes wrong.
727          *
728          */
729         outl(TLAN_HC_AD_RST, BASE + TLAN_HOST_CMD);
730 }
731
732 /**************************************************************************
733 IRQ - Enable, Disable, or Force interrupts
734 ***************************************************************************/
735 static void tlan_irq(struct nic *nic __unused, irq_action_t action __unused)
736 {
737   switch ( action ) {
738   case DISABLE :
739     break;
740   case ENABLE :
741     break;
742   case FORCE :
743     break;
744   }
745 }
746
747 static struct nic_operations tlan_operations = {
748         .connect        = dummy_connect,
749         .poll           = tlan_poll,
750         .transmit       = tlan_transmit,
751         .irq            = tlan_irq,
752
753 };
754
755 static void TLan_SetMulticastList(struct nic *nic) {
756         int i;
757         u8 tmp;
758
759         /* !IFF_PROMISC */
760         tmp = TLan_DioRead8(BASE, TLAN_NET_CMD);
761         TLan_DioWrite8(BASE, TLAN_NET_CMD, tmp & ~TLAN_NET_CMD_CAF);
762
763         /* IFF_ALLMULTI */
764         for(i = 0; i< 3; i++)
765                 TLan_SetMac(nic, i + 1, NULL);
766         TLan_DioWrite32(BASE, TLAN_HASH_1, 0xFFFFFFFF);
767         TLan_DioWrite32(BASE, TLAN_HASH_2, 0xFFFFFFFF);
768
769         
770 }
771 /**************************************************************************
772 PROBE - Look for an adapter, this routine's visible to the outside
773 ***************************************************************************/
774
775 #define board_found 1
776 #define valid_link 0
777 static int tlan_probe ( struct nic *nic, struct pci_device *pci ) {
778
779         u16 data = 0;
780         int err;
781         int i;
782
783         if (pci->ioaddr == 0)
784                 return 0;
785
786         nic->irqno  = 0;
787         pci_fill_nic ( nic, pci );
788         nic->ioaddr = pci->ioaddr;
789
790         BASE = pci->ioaddr;
791
792         /* Set nic as PCI bus master */
793         adjust_pci_device(pci);
794         
795         /* Point to private storage */
796         priv = &TLanPrivateInfo;
797
798         /* Figure out which chip we're dealing with */
799         i = 0;
800         chip_idx = -1;
801         while (tlan_pci_tbl[i].name) {
802                 if ((((u32) pci->device << 16) | pci->vendor) ==
803                     (tlan_pci_tbl[i].id.pci & 0xffffffff)) {
804                         chip_idx = i;
805                         break;
806                 }
807                 i++;
808         }
809
810         priv->vendor_id = pci->vendor;
811         priv->dev_id = pci->device;
812         priv->nic_name = pci->driver_name;
813         priv->eoc = 0;
814
815         err = 0;
816         for (i = 0; i < 6; i++)
817                 err |= TLan_EeReadByte(BASE,
818                                        (u8) tlan_pci_tbl[chip_idx].
819                                        addrOfs + i,
820                                        (u8 *) & nic->node_addr[i]);
821         if (err) {
822             printf ( "TLAN: %s: Error reading MAC from eeprom: %d\n",
823                     pci->driver_name, err);
824         } else {
825             DBG ( "%s: %s at ioaddr %#lX, ", 
826                   pci->driver_name, eth_ntoa ( nic->node_addr ), pci->ioaddr );
827         }
828
829         priv->tlanRev = TLan_DioRead8(BASE, TLAN_DEF_REVISION);
830         printf("revision: 0x%hX\n", priv->tlanRev);
831
832         TLan_ResetLists(nic);
833         TLan_ResetAdapter(nic);
834
835         data = inl(BASE + TLAN_HOST_CMD);
836         data |= TLAN_HC_INT_OFF;
837         outw(data, BASE + TLAN_HOST_CMD);
838
839         TLan_SetMulticastList(nic);
840         udelay(100); 
841         priv->txList = tx_ring;
842
843 /*      if (board_found && valid_link)
844         {*/
845         /* point to NIC specific routines */
846         nic->nic_op     = &tlan_operations;
847         return 1;
848 }
849
850
851 /*****************************************************************************
852 ******************************************************************************
853
854         ThunderLAN Driver Eeprom routines
855
856         The Compaq Netelligent 10 and 10/100 cards use a Microchip 24C02A
857         EEPROM.  These functions are based on information in Microchip's
858         data sheet.  I don't know how well this functions will work with
859         other EEPROMs.
860
861 ******************************************************************************
862 *****************************************************************************/
863
864
865 /***************************************************************
866 *       TLan_EeSendStart
867 *
868 *       Returns:
869 *               Nothing
870 *       Parms:
871 *               io_base         The IO port base address for the
872 *                               TLAN device with the EEPROM to
873 *                               use.
874 *
875 *       This function sends a start cycle to an EEPROM attached
876 *       to a TLAN chip.
877 *
878 **************************************************************/
879
880 void TLan_EeSendStart(u16 io_base)
881 {
882         u16 sio;
883
884         outw(TLAN_NET_SIO, io_base + TLAN_DIO_ADR);
885         sio = io_base + TLAN_DIO_DATA + TLAN_NET_SIO;
886
887         TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
888         TLan_SetBit(TLAN_NET_SIO_EDATA, sio);
889         TLan_SetBit(TLAN_NET_SIO_ETXEN, sio);
890         TLan_ClearBit(TLAN_NET_SIO_EDATA, sio);
891         TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
892
893 }       /* TLan_EeSendStart */
894
895 /***************************************************************
896 *       TLan_EeSendByte
897 *
898 *       Returns:
899 *               If the correct ack was received, 0, otherwise 1
900 *       Parms:  io_base         The IO port base address for the
901 *                               TLAN device with the EEPROM to
902 *                               use.
903 *               data            The 8 bits of information to
904 *                               send to the EEPROM.
905 *               stop            If TLAN_EEPROM_STOP is passed, a
906 *                               stop cycle is sent after the
907 *                               byte is sent after the ack is
908 *                               read.
909 *
910 *       This function sends a byte on the serial EEPROM line,
911 *       driving the clock to send each bit. The function then
912 *       reverses transmission direction and reads an acknowledge
913 *       bit.
914 *
915 **************************************************************/
916
917 int TLan_EeSendByte(u16 io_base, u8 data, int stop)
918 {
919         int err;
920         u8 place;
921         u16 sio;
922
923         outw(TLAN_NET_SIO, io_base + TLAN_DIO_ADR);
924         sio = io_base + TLAN_DIO_DATA + TLAN_NET_SIO;
925
926         /* Assume clock is low, tx is enabled; */
927         for (place = 0x80; place != 0; place >>= 1) {
928                 if (place & data)
929                         TLan_SetBit(TLAN_NET_SIO_EDATA, sio);
930                 else
931                         TLan_ClearBit(TLAN_NET_SIO_EDATA, sio);
932                 TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
933                 TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
934         }
935         TLan_ClearBit(TLAN_NET_SIO_ETXEN, sio);
936         TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
937         err = TLan_GetBit(TLAN_NET_SIO_EDATA, sio);
938         TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
939         TLan_SetBit(TLAN_NET_SIO_ETXEN, sio);
940
941         if ((!err) && stop) {
942                 TLan_ClearBit(TLAN_NET_SIO_EDATA, sio); /* STOP, raise data while clock is high */
943                 TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
944                 TLan_SetBit(TLAN_NET_SIO_EDATA, sio);
945         }
946
947         return (err);
948
949 }       /* TLan_EeSendByte */
950
951 /***************************************************************
952 *       TLan_EeReceiveByte
953 *
954 *       Returns:
955 *               Nothing
956 *       Parms:
957 *               io_base         The IO port base address for the
958 *                               TLAN device with the EEPROM to
959 *                               use.
960 *               data            An address to a char to hold the
961 *                               data sent from the EEPROM.
962 *               stop            If TLAN_EEPROM_STOP is passed, a
963 *                               stop cycle is sent after the
964 *                               byte is received, and no ack is
965 *                               sent.
966 *
967 *       This function receives 8 bits of data from the EEPROM
968 *       over the serial link.  It then sends and ack bit, or no
969 *       ack and a stop bit.  This function is used to retrieve
970 *       data after the address of a byte in the EEPROM has been
971 *       sent.
972 *
973 **************************************************************/
974
975 void TLan_EeReceiveByte(u16 io_base, u8 * data, int stop)
976 {
977         u8 place;
978         u16 sio;
979
980         outw(TLAN_NET_SIO, io_base + TLAN_DIO_ADR);
981         sio = io_base + TLAN_DIO_DATA + TLAN_NET_SIO;
982         *data = 0;
983
984         /* Assume clock is low, tx is enabled; */
985         TLan_ClearBit(TLAN_NET_SIO_ETXEN, sio);
986         for (place = 0x80; place; place >>= 1) {
987                 TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
988                 if (TLan_GetBit(TLAN_NET_SIO_EDATA, sio))
989                         *data |= place;
990                 TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
991         }
992
993         TLan_SetBit(TLAN_NET_SIO_ETXEN, sio);
994         if (!stop) {
995                 TLan_ClearBit(TLAN_NET_SIO_EDATA, sio); /* Ack = 0 */
996                 TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
997                 TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
998         } else {
999                 TLan_SetBit(TLAN_NET_SIO_EDATA, sio);   /* No ack = 1 (?) */
1000                 TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
1001                 TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
1002                 TLan_ClearBit(TLAN_NET_SIO_EDATA, sio); /* STOP, raise data while clock is high */
1003                 TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
1004                 TLan_SetBit(TLAN_NET_SIO_EDATA, sio);
1005         }
1006
1007 }       /* TLan_EeReceiveByte */
1008
1009 /***************************************************************
1010 *       TLan_EeReadByte
1011 *
1012 *       Returns:
1013 *               No error = 0, else, the stage at which the error
1014 *               occurred.
1015 *       Parms:
1016 *               io_base         The IO port base address for the
1017 *                               TLAN device with the EEPROM to
1018 *                               use.
1019 *               ee_addr         The address of the byte in the
1020 *                               EEPROM whose contents are to be
1021 *                               retrieved.
1022 *               data            An address to a char to hold the
1023 *                               data obtained from the EEPROM.
1024 *
1025 *       This function reads a byte of information from an byte
1026 *       cell in the EEPROM.
1027 *
1028 **************************************************************/
1029
1030 int TLan_EeReadByte(u16 io_base, u8 ee_addr, u8 * data)
1031 {
1032         int err;
1033         int ret = 0;
1034
1035
1036         TLan_EeSendStart(io_base);
1037         err = TLan_EeSendByte(io_base, 0xA0, TLAN_EEPROM_ACK);
1038         if (err) {
1039                 ret = 1;
1040                 goto fail;
1041         }
1042         err = TLan_EeSendByte(io_base, ee_addr, TLAN_EEPROM_ACK);
1043         if (err) {
1044                 ret = 2;
1045                 goto fail;
1046         }
1047         TLan_EeSendStart(io_base);
1048         err = TLan_EeSendByte(io_base, 0xA1, TLAN_EEPROM_ACK);
1049         if (err) {
1050                 ret = 3;
1051                 goto fail;
1052         }
1053         TLan_EeReceiveByte(io_base, data, TLAN_EEPROM_STOP);
1054       fail:
1055
1056         return ret;
1057
1058 }       /* TLan_EeReadByte */
1059
1060
1061 /*****************************************************************************
1062 ******************************************************************************
1063
1064 ThunderLAN Driver MII Routines
1065
1066 These routines are based on the information in Chap. 2 of the
1067 "ThunderLAN Programmer's Guide", pp. 15-24.
1068
1069 ******************************************************************************
1070 *****************************************************************************/
1071
1072
1073 /***************************************************************
1074 *       TLan_MiiReadReg
1075 *
1076 *       Returns:
1077 *               0       if ack received ok
1078 *               1       otherwise.
1079 *
1080 *       Parms:
1081 *               dev             The device structure containing
1082 *                               The io address and interrupt count
1083 *                               for this device.
1084 *               phy             The address of the PHY to be queried.
1085 *               reg             The register whose contents are to be
1086 *                               retreived.
1087 *               val             A pointer to a variable to store the
1088 *                               retrieved value.
1089 *
1090 *       This function uses the TLAN's MII bus to retreive the contents
1091 *       of a given register on a PHY.  It sends the appropriate info
1092 *       and then reads the 16-bit register value from the MII bus via
1093 *       the TLAN SIO register.
1094 *
1095 **************************************************************/
1096
1097 int TLan_MiiReadReg(struct nic *nic __unused, u16 phy, u16 reg, u16 * val)
1098 {
1099         u8 nack;
1100         u16 sio, tmp;
1101         u32 i;
1102         int err;
1103         int minten;
1104
1105         err = FALSE;
1106         outw(TLAN_NET_SIO, BASE + TLAN_DIO_ADR);
1107         sio = BASE + TLAN_DIO_DATA + TLAN_NET_SIO;
1108
1109         TLan_MiiSync(BASE);
1110
1111         minten = TLan_GetBit(TLAN_NET_SIO_MINTEN, sio);
1112         if (minten)
1113                 TLan_ClearBit(TLAN_NET_SIO_MINTEN, sio);
1114
1115         TLan_MiiSendData(BASE, 0x1, 2); /* Start ( 01b ) */
1116         TLan_MiiSendData(BASE, 0x2, 2); /* Read  ( 10b ) */
1117         TLan_MiiSendData(BASE, phy, 5); /* Device #      */
1118         TLan_MiiSendData(BASE, reg, 5); /* Register #    */
1119
1120
1121         TLan_ClearBit(TLAN_NET_SIO_MTXEN, sio); /* Change direction */
1122
1123         TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);  /* Clock Idle bit */
1124         TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1125         TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);  /* Wait 300ns */
1126
1127         nack = TLan_GetBit(TLAN_NET_SIO_MDATA, sio);    /* Check for ACK */
1128         TLan_SetBit(TLAN_NET_SIO_MCLK, sio);    /* Finish ACK */
1129         if (nack) {             /* No ACK, so fake it */
1130                 for (i = 0; i < 16; i++) {
1131                         TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
1132                         TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1133                 }
1134                 tmp = 0xffff;
1135                 err = TRUE;
1136         } else {                /* ACK, so read data */
1137                 for (tmp = 0, i = 0x8000; i; i >>= 1) {
1138                         TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
1139                         if (TLan_GetBit(TLAN_NET_SIO_MDATA, sio))
1140                                 tmp |= i;
1141                         TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1142                 }
1143         }
1144
1145
1146         TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);  /* Idle cycle */
1147         TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1148
1149         if (minten)
1150                 TLan_SetBit(TLAN_NET_SIO_MINTEN, sio);
1151
1152         *val = tmp;
1153
1154         return err;
1155
1156 }                               /* TLan_MiiReadReg */
1157
1158 /***************************************************************
1159 *       TLan_MiiSendData
1160 *
1161 *       Returns:
1162 *               Nothing
1163 *       Parms:
1164 *               base_port       The base IO port of the adapter in
1165 *                               question.
1166 *               dev             The address of the PHY to be queried.
1167 *               data            The value to be placed on the MII bus.
1168 *               num_bits        The number of bits in data that are to
1169 *                               be placed on the MII bus.
1170 *
1171 *       This function sends on sequence of bits on the MII
1172 *       configuration bus.
1173 *
1174 **************************************************************/
1175
1176 void TLan_MiiSendData(u16 base_port, u32 data, unsigned num_bits)
1177 {
1178         u16 sio;
1179         u32 i;
1180
1181         if (num_bits == 0)
1182                 return;
1183
1184         outw(TLAN_NET_SIO, base_port + TLAN_DIO_ADR);
1185         sio = base_port + TLAN_DIO_DATA + TLAN_NET_SIO;
1186         TLan_SetBit(TLAN_NET_SIO_MTXEN, sio);
1187
1188         for (i = (0x1 << (num_bits - 1)); i; i >>= 1) {
1189                 TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
1190                 (void) TLan_GetBit(TLAN_NET_SIO_MCLK, sio);
1191                 if (data & i)
1192                         TLan_SetBit(TLAN_NET_SIO_MDATA, sio);
1193                 else
1194                         TLan_ClearBit(TLAN_NET_SIO_MDATA, sio);
1195                 TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1196                 (void) TLan_GetBit(TLAN_NET_SIO_MCLK, sio);
1197         }
1198
1199 }                               /* TLan_MiiSendData */
1200
1201 /***************************************************************
1202 *       TLan_MiiSync
1203 *
1204 *       Returns:
1205 *               Nothing
1206 *       Parms:
1207 *               base_port       The base IO port of the adapter in
1208 *                               question.
1209 *
1210 *       This functions syncs all PHYs in terms of the MII configuration
1211 *       bus.
1212 *
1213 **************************************************************/
1214
1215 void TLan_MiiSync(u16 base_port)
1216 {
1217         int i;
1218         u16 sio;
1219
1220         outw(TLAN_NET_SIO, base_port + TLAN_DIO_ADR);
1221         sio = base_port + TLAN_DIO_DATA + TLAN_NET_SIO;
1222
1223         TLan_ClearBit(TLAN_NET_SIO_MTXEN, sio);
1224         for (i = 0; i < 32; i++) {
1225                 TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
1226                 TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1227         }
1228
1229 }                               /* TLan_MiiSync */
1230
1231 /***************************************************************
1232 *       TLan_MiiWriteReg
1233 *
1234 *       Returns:
1235 *               Nothing
1236 *       Parms:
1237 *               dev             The device structure for the device
1238 *                               to write to.
1239 *               phy             The address of the PHY to be written to.
1240 *               reg             The register whose contents are to be
1241 *                               written.
1242 *               val             The value to be written to the register.
1243 *
1244 *       This function uses the TLAN's MII bus to write the contents of a
1245 *       given register on a PHY.  It sends the appropriate info and then
1246 *       writes the 16-bit register value from the MII configuration bus
1247 *       via the TLAN SIO register.
1248 *
1249 **************************************************************/
1250
1251 void TLan_MiiWriteReg(struct nic *nic __unused, u16 phy, u16 reg, u16 val)
1252 {
1253         u16 sio;
1254         int minten;
1255
1256         outw(TLAN_NET_SIO, BASE + TLAN_DIO_ADR);
1257         sio = BASE + TLAN_DIO_DATA + TLAN_NET_SIO;
1258
1259         TLan_MiiSync(BASE);
1260
1261         minten = TLan_GetBit(TLAN_NET_SIO_MINTEN, sio);
1262         if (minten)
1263                 TLan_ClearBit(TLAN_NET_SIO_MINTEN, sio);
1264
1265         TLan_MiiSendData(BASE, 0x1, 2); /* Start ( 01b ) */
1266         TLan_MiiSendData(BASE, 0x1, 2); /* Write ( 01b ) */
1267         TLan_MiiSendData(BASE, phy, 5); /* Device #      */
1268         TLan_MiiSendData(BASE, reg, 5); /* Register #    */
1269
1270         TLan_MiiSendData(BASE, 0x2, 2); /* Send ACK */
1271         TLan_MiiSendData(BASE, val, 16);        /* Send Data */
1272
1273         TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);  /* Idle cycle */
1274         TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1275
1276         if (minten)
1277                 TLan_SetBit(TLAN_NET_SIO_MINTEN, sio);
1278
1279
1280 }                               /* TLan_MiiWriteReg */
1281
1282 /***************************************************************
1283 *       TLan_SetMac
1284 *
1285 *       Returns:
1286 *               Nothing
1287 *       Parms:
1288 *               dev     Pointer to device structure of adapter
1289 *                       on which to change the AREG.
1290 *               areg    The AREG to set the address in (0 - 3).
1291 *               mac     A pointer to an array of chars.  Each
1292 *                       element stores one byte of the address.
1293 *                       IE, it isn't in ascii.
1294 *
1295 *       This function transfers a MAC address to one of the
1296 *       TLAN AREGs (address registers).  The TLAN chip locks
1297 *       the register on writing to offset 0 and unlocks the
1298 *       register after writing to offset 5.  If NULL is passed
1299 *       in mac, then the AREG is filled with 0's.
1300 *
1301 **************************************************************/
1302
1303 void TLan_SetMac(struct nic *nic __unused, int areg, unsigned char *mac)
1304 {
1305         int i;
1306
1307         areg *= 6;
1308
1309         if (mac != NULL) {
1310                 for (i = 0; i < 6; i++)
1311                         TLan_DioWrite8(BASE, TLAN_AREG_0 + areg + i,
1312                                        mac[i]);
1313         } else {
1314                 for (i = 0; i < 6; i++)
1315                         TLan_DioWrite8(BASE, TLAN_AREG_0 + areg + i, 0);
1316         }
1317
1318 }                               /* TLan_SetMac */
1319
1320 /*********************************************************************
1321 *       TLan_PhyDetect
1322 *
1323 *       Returns:
1324 *               Nothing
1325 *       Parms:
1326 *               dev     A pointer to the device structure of the adapter
1327 *                       for which the PHY needs determined.
1328 *
1329 *       So far I've found that adapters which have external PHYs
1330 *       may also use the internal PHY for part of the functionality.
1331 *       (eg, AUI/Thinnet).  This function finds out if this TLAN
1332 *       chip has an internal PHY, and then finds the first external
1333 *       PHY (starting from address 0) if it exists).
1334 *
1335 ********************************************************************/
1336
1337 void TLan_PhyDetect(struct nic *nic)
1338 {
1339         u16 control;
1340         u16 hi;
1341         u16 lo;
1342         u32 phy;
1343
1344         if (tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_UNMANAGED_PHY) {
1345                 priv->phyNum = 0xFFFF;
1346                 return;
1347         }
1348
1349         TLan_MiiReadReg(nic, TLAN_PHY_MAX_ADDR, MII_GEN_ID_HI, &hi);
1350
1351         if (hi != 0xFFFF) {
1352                 priv->phy[0] = TLAN_PHY_MAX_ADDR;
1353         } else {
1354                 priv->phy[0] = TLAN_PHY_NONE;
1355         }
1356
1357         priv->phy[1] = TLAN_PHY_NONE;
1358         for (phy = 0; phy <= TLAN_PHY_MAX_ADDR; phy++) {
1359                 TLan_MiiReadReg(nic, phy, MII_GEN_CTL, &control);
1360                 TLan_MiiReadReg(nic, phy, MII_GEN_ID_HI, &hi);
1361                 TLan_MiiReadReg(nic, phy, MII_GEN_ID_LO, &lo);
1362                 if ((control != 0xFFFF) || (hi != 0xFFFF)
1363                     || (lo != 0xFFFF)) {
1364                         printf("PHY found at %hX %hX %hX %hX\n", 
1365                                (unsigned int) phy, control, hi, lo);
1366                         if ((priv->phy[1] == TLAN_PHY_NONE)
1367                             && (phy != TLAN_PHY_MAX_ADDR)) {
1368                                 priv->phy[1] = phy;
1369                         }
1370                 }
1371         }
1372
1373         if (priv->phy[1] != TLAN_PHY_NONE) {
1374                 priv->phyNum = 1;
1375         } else if (priv->phy[0] != TLAN_PHY_NONE) {
1376                 priv->phyNum = 0;
1377         } else {
1378                 printf
1379                     ("TLAN:  Cannot initialize device, no PHY was found!\n");
1380         }
1381
1382 }                               /* TLan_PhyDetect */
1383
1384 void TLan_PhyPowerDown(struct nic *nic)
1385 {
1386
1387         u16 value;
1388         DBG ( "%s: Powering down PHY(s).\n", priv->nic_name );
1389         value = MII_GC_PDOWN | MII_GC_LOOPBK | MII_GC_ISOLATE;
1390         TLan_MiiSync(BASE);
1391         TLan_MiiWriteReg(nic, priv->phy[priv->phyNum], MII_GEN_CTL, value);
1392         if ((priv->phyNum == 0) && (priv->phy[1] != TLAN_PHY_NONE)
1393             &&
1394             (!(tlan_pci_tbl[chip_idx].
1395                flags & TLAN_ADAPTER_USE_INTERN_10))) {
1396                 TLan_MiiSync(BASE);
1397                 TLan_MiiWriteReg(nic, priv->phy[1], MII_GEN_CTL, value);
1398         }
1399
1400         /* Wait for 50 ms and powerup
1401          * This is abitrary.  It is intended to make sure the
1402          * tranceiver settles.
1403          */
1404         /* TLan_SetTimer( dev, (HZ/20), TLAN_TIMER_PHY_PUP ); */
1405         mdelay(50);
1406         TLan_PhyPowerUp(nic);
1407
1408 }                               /* TLan_PhyPowerDown */
1409
1410
1411 void TLan_PhyPowerUp(struct nic *nic)
1412 {
1413         u16 value;
1414
1415         DBG ( "%s: Powering up PHY.\n", priv->nic_name );
1416         TLan_MiiSync(BASE);
1417         value = MII_GC_LOOPBK;
1418         TLan_MiiWriteReg(nic, priv->phy[priv->phyNum], MII_GEN_CTL, value);
1419         TLan_MiiSync(BASE);
1420         /* Wait for 500 ms and reset the
1421          * tranceiver.  The TLAN docs say both 50 ms and
1422          * 500 ms, so do the longer, just in case.
1423          */
1424         mdelay(500);
1425         TLan_PhyReset(nic);
1426         /* TLan_SetTimer( dev, (HZ/20), TLAN_TIMER_PHY_RESET ); */
1427
1428 }                               /* TLan_PhyPowerUp */
1429
1430 void TLan_PhyReset(struct nic *nic)
1431 {
1432         u16 phy;
1433         u16 value;
1434
1435         phy = priv->phy[priv->phyNum];
1436
1437         DBG ( "%s: Reseting PHY.\n", priv->nic_name );
1438         TLan_MiiSync(BASE);
1439         value = MII_GC_LOOPBK | MII_GC_RESET;
1440         TLan_MiiWriteReg(nic, phy, MII_GEN_CTL, value);
1441         TLan_MiiReadReg(nic, phy, MII_GEN_CTL, &value);
1442         while (value & MII_GC_RESET) {
1443                 TLan_MiiReadReg(nic, phy, MII_GEN_CTL, &value);
1444         }
1445
1446         /* Wait for 500 ms and initialize.
1447          * I don't remember why I wait this long.
1448          * I've changed this to 50ms, as it seems long enough.
1449          */
1450         /* TLan_SetTimer( dev, (HZ/20), TLAN_TIMER_PHY_START_LINK ); */
1451         mdelay(50);
1452         TLan_PhyStartLink(nic);
1453
1454 }                               /* TLan_PhyReset */
1455
1456
1457 void TLan_PhyStartLink(struct nic *nic)
1458 {
1459
1460         u16 ability;
1461         u16 control;
1462         u16 data;
1463         u16 phy;
1464         u16 status;
1465         u16 tctl;
1466
1467         phy = priv->phy[priv->phyNum];
1468         DBG ( "%s: Trying to activate link.\n", priv->nic_name );
1469         TLan_MiiReadReg(nic, phy, MII_GEN_STS, &status);
1470         TLan_MiiReadReg(nic, phy, MII_GEN_STS, &ability);
1471
1472         if ((status & MII_GS_AUTONEG) && (!priv->aui)) {
1473                 ability = status >> 11;
1474                 if (priv->speed == TLAN_SPEED_10 &&
1475                     priv->duplex == TLAN_DUPLEX_HALF) {
1476                         TLan_MiiWriteReg(nic, phy, MII_GEN_CTL, 0x0000);
1477                 } else if (priv->speed == TLAN_SPEED_10 &&
1478                            priv->duplex == TLAN_DUPLEX_FULL) {
1479                         priv->tlanFullDuplex = TRUE;
1480                         TLan_MiiWriteReg(nic, phy, MII_GEN_CTL, 0x0100);
1481                 } else if (priv->speed == TLAN_SPEED_100 &&
1482                            priv->duplex == TLAN_DUPLEX_HALF) {
1483                         TLan_MiiWriteReg(nic, phy, MII_GEN_CTL, 0x2000);
1484                 } else if (priv->speed == TLAN_SPEED_100 &&
1485                            priv->duplex == TLAN_DUPLEX_FULL) {
1486                         priv->tlanFullDuplex = TRUE;
1487                         TLan_MiiWriteReg(nic, phy, MII_GEN_CTL, 0x2100);
1488                 } else {
1489
1490                         /* Set Auto-Neg advertisement */
1491                         TLan_MiiWriteReg(nic, phy, MII_AN_ADV,
1492                                          (ability << 5) | 1);
1493                         /* Enablee Auto-Neg */
1494                         TLan_MiiWriteReg(nic, phy, MII_GEN_CTL, 0x1000);
1495                         /* Restart Auto-Neg */
1496                         TLan_MiiWriteReg(nic, phy, MII_GEN_CTL, 0x1200);
1497                         /* Wait for 4 sec for autonegotiation
1498                          * to complete.  The max spec time is less than this
1499                          * but the card need additional time to start AN.
1500                          * .5 sec should be plenty extra.
1501                          */
1502                         DBG ( "TLAN: %s: Starting autonegotiation.\n",
1503                                priv->nic_name );
1504                         mdelay(4000);
1505                         TLan_PhyFinishAutoNeg(nic);
1506                         /* TLan_SetTimer( dev, (2*HZ), TLAN_TIMER_PHY_FINISH_AN ); */
1507                         return;
1508                 }
1509
1510         }
1511
1512         if ((priv->aui) && (priv->phyNum != 0)) {
1513                 priv->phyNum = 0;
1514                 data =
1515                     TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN |
1516                     TLAN_NET_CFG_PHY_EN;
1517                 TLan_DioWrite16(BASE, TLAN_NET_CONFIG, data);
1518                 mdelay(50);
1519                 /* TLan_SetTimer( dev, (40*HZ/1000), TLAN_TIMER_PHY_PDOWN ); */
1520                 TLan_PhyPowerDown(nic);
1521                 return;
1522         } else if (priv->phyNum == 0) {
1523                 control = 0;
1524                 TLan_MiiReadReg(nic, phy, TLAN_TLPHY_CTL, &tctl);
1525                 if (priv->aui) {
1526                         tctl |= TLAN_TC_AUISEL;
1527                 } else {
1528                         tctl &= ~TLAN_TC_AUISEL;
1529                         if (priv->duplex == TLAN_DUPLEX_FULL) {
1530                                 control |= MII_GC_DUPLEX;
1531                                 priv->tlanFullDuplex = TRUE;
1532                         }
1533                         if (priv->speed == TLAN_SPEED_100) {
1534                                 control |= MII_GC_SPEEDSEL;
1535                         }
1536                 }
1537                 TLan_MiiWriteReg(nic, phy, MII_GEN_CTL, control);
1538                 TLan_MiiWriteReg(nic, phy, TLAN_TLPHY_CTL, tctl);
1539         }
1540
1541         /* Wait for 2 sec to give the tranceiver time
1542          * to establish link.
1543          */
1544         /* TLan_SetTimer( dev, (4*HZ), TLAN_TIMER_FINISH_RESET ); */
1545         mdelay(2000);
1546         TLan_FinishReset(nic);
1547
1548 }                               /* TLan_PhyStartLink */
1549
1550 void TLan_PhyFinishAutoNeg(struct nic *nic)
1551 {
1552
1553         u16 an_adv;
1554         u16 an_lpa;
1555         u16 data;
1556         u16 mode;
1557         u16 phy;
1558         u16 status;
1559
1560         phy = priv->phy[priv->phyNum];
1561
1562         TLan_MiiReadReg(nic, phy, MII_GEN_STS, &status);
1563         udelay(1000);
1564         TLan_MiiReadReg(nic, phy, MII_GEN_STS, &status);
1565
1566         if (!(status & MII_GS_AUTOCMPLT)) {
1567                 /* Wait for 8 sec to give the process
1568                  * more time.  Perhaps we should fail after a while.
1569                  */
1570                 if (!priv->neg_be_verbose++) {
1571                         printf
1572                             ("TLAN:  Giving autonegotiation more time.\n");
1573                         printf
1574                             ("TLAN:  Please check that your adapter has\n");
1575                         printf
1576                             ("TLAN:  been properly connected to a HUB or Switch.\n");
1577                         printf
1578                             ("TLAN:  Trying to establish link in the background...\n");
1579                 }
1580                 mdelay(8000);
1581                 TLan_PhyFinishAutoNeg(nic);
1582                 /* TLan_SetTimer( dev, (8*HZ), TLAN_TIMER_PHY_FINISH_AN ); */
1583                 return;
1584         }
1585
1586         DBG ( "TLAN: %s: Autonegotiation complete.\n", priv->nic_name );
1587         TLan_MiiReadReg(nic, phy, MII_AN_ADV, &an_adv);
1588         TLan_MiiReadReg(nic, phy, MII_AN_LPA, &an_lpa);
1589         mode = an_adv & an_lpa & 0x03E0;
1590         if (mode & 0x0100) {
1591                 printf("Full Duplex\n");
1592                 priv->tlanFullDuplex = TRUE;
1593         } else if (!(mode & 0x0080) && (mode & 0x0040)) {
1594                 priv->tlanFullDuplex = TRUE;
1595                 printf("Full Duplex\n");
1596         }
1597
1598         if ((!(mode & 0x0180))
1599             && (tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_USE_INTERN_10)
1600             && (priv->phyNum != 0)) {
1601                 priv->phyNum = 0;
1602                 data =
1603                     TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN |
1604                     TLAN_NET_CFG_PHY_EN;
1605                 TLan_DioWrite16(BASE, TLAN_NET_CONFIG, data);
1606                 /* TLan_SetTimer( nic, (400*HZ/1000), TLAN_TIMER_PHY_PDOWN ); */
1607                 mdelay(400);
1608                 TLan_PhyPowerDown(nic);
1609                 return;
1610         }
1611
1612         if (priv->phyNum == 0) {
1613                 if ((priv->duplex == TLAN_DUPLEX_FULL)
1614                     || (an_adv & an_lpa & 0x0040)) {
1615                         TLan_MiiWriteReg(nic, phy, MII_GEN_CTL,
1616                                          MII_GC_AUTOENB | MII_GC_DUPLEX);
1617                         DBG 
1618                             ( "TLAN:  Starting internal PHY with FULL-DUPLEX\n" );
1619                 } else {
1620                         TLan_MiiWriteReg(nic, phy, MII_GEN_CTL,
1621                                          MII_GC_AUTOENB);
1622                         DBG 
1623                             ( "TLAN:  Starting internal PHY with HALF-DUPLEX\n" );
1624                 }
1625         }
1626
1627         /* Wait for 100 ms.  No reason in partiticular.
1628          */
1629         /* TLan_SetTimer( dev, (HZ/10), TLAN_TIMER_FINISH_RESET ); */
1630         mdelay(100);
1631         TLan_FinishReset(nic);
1632
1633 }                               /* TLan_PhyFinishAutoNeg */
1634
1635 #ifdef MONITOR
1636
1637 /*********************************************************************
1638 *
1639 *      TLan_phyMonitor
1640 *
1641 *      Returns:
1642 *              None
1643 *
1644 *      Params:
1645 *              dev             The device structure of this device.
1646 *
1647 *
1648 *      This function monitors PHY condition by reading the status
1649 *      register via the MII bus. This can be used to give info
1650 *      about link changes (up/down), and possible switch to alternate
1651 *      media.
1652 *
1653 ********************************************************************/
1654
1655 void TLan_PhyMonitor(struct net_device *dev)
1656 {
1657         TLanPrivateInfo *priv = dev->priv;
1658         u16 phy;
1659         u16 phy_status;
1660
1661         phy = priv->phy[priv->phyNum];
1662
1663         /* Get PHY status register */
1664         TLan_MiiReadReg(nic, phy, MII_GEN_STS, &phy_status);
1665
1666         /* Check if link has been lost */
1667         if (!(phy_status & MII_GS_LINK)) {
1668                 if (priv->link) {
1669                         priv->link = 0;
1670                         printf("TLAN: %s has lost link\n", priv->nic_name);
1671                         priv->flags &= ~IFF_RUNNING;
1672                         mdelay(2000);
1673                         TLan_PhyMonitor(nic);
1674                         /* TLan_SetTimer( dev, (2*HZ), TLAN_TIMER_LINK_BEAT ); */
1675                         return;
1676                 }
1677         }
1678
1679         /* Link restablished? */
1680         if ((phy_status & MII_GS_LINK) && !priv->link) {
1681                 priv->link = 1;
1682                 printf("TLAN: %s has reestablished link\n",
1683                        priv->nic_name);
1684                 priv->flags |= IFF_RUNNING;
1685         }
1686
1687         /* Setup a new monitor */
1688         /* TLan_SetTimer( dev, (2*HZ), TLAN_TIMER_LINK_BEAT ); */
1689         mdelay(2000);
1690         TLan_PhyMonitor(nic);
1691 }
1692
1693 #endif                          /* MONITOR */
1694
1695 static struct pci_device_id tlan_nics[] = {
1696         PCI_ROM(0x0e11, 0xae34, "netel10", "Compaq Netelligent 10 T PCI UTP"),
1697         PCI_ROM(0x0e11, 0xae32, "netel100","Compaq Netelligent 10/100 TX PCI UTP"),
1698         PCI_ROM(0x0e11, 0xae35, "netflex3i", "Compaq Integrated NetFlex-3/P"),
1699         PCI_ROM(0x0e11, 0xf130, "thunder", "Compaq NetFlex-3/P"),
1700         PCI_ROM(0x0e11, 0xf150, "netflex3b", "Compaq NetFlex-3/P"),
1701         PCI_ROM(0x0e11, 0xae43, "netel100pi", "Compaq Netelligent Integrated 10/100 TX UTP"),
1702         PCI_ROM(0x0e11, 0xae40, "netel100d", "Compaq Netelligent Dual 10/100 TX PCI UTP"),
1703         PCI_ROM(0x0e11, 0xb011, "netel100i", "Compaq Netelligent 10/100 TX Embedded UTP"),
1704         PCI_ROM(0x108d, 0x0013, "oc2183", "Olicom OC-2183/2185"),
1705         PCI_ROM(0x108d, 0x0012, "oc2325", "Olicom OC-2325"),
1706         PCI_ROM(0x108d, 0x0014, "oc2326", "Olicom OC-2326"),
1707         PCI_ROM(0x0e11, 0xb030, "netelligent_10_100_ws_5100", "Compaq Netelligent 10/100 TX UTP"),
1708         PCI_ROM(0x0e11, 0xb012, "netelligent_10_t2", "Compaq Netelligent 10 T/2 PCI UTP/Coax"),
1709 };
1710
1711 PCI_DRIVER ( tlan_driver, tlan_nics, PCI_NO_CLASS );
1712
1713 DRIVER ( "TLAN/PCI", nic_driver, pci_driver, tlan_driver,
1714          tlan_probe, tlan_disable );