Ensured that all drivers call xxx_fill_nic().
[people/xl0/gpxe.git] / src / drivers / net / e1000.c
1 /**************************************************************************
2 Etherboot -  BOOTP/TFTP Bootstrap Program
3 Inter Pro 1000 for Etherboot
4 Drivers are port from Intel's Linux driver e1000-4.3.15
5
6 ***************************************************************************/
7 /*******************************************************************************
8
9   
10   Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
11   
12   This program is free software; you can redistribute it and/or modify it 
13   under the terms of the GNU General Public License as published by the Free 
14   Software Foundation; either version 2 of the License, or (at your option) 
15   any later version.
16   
17   This program is distributed in the hope that it will be useful, but WITHOUT 
18   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
19   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for 
20   more details.
21   
22   You should have received a copy of the GNU General Public License along with
23   this program; if not, write to the Free Software Foundation, Inc., 59 
24   Temple Place - Suite 330, Boston, MA  02111-1307, USA.
25   
26   The full GNU General Public License is included in this distribution in the
27   file called LICENSE.
28   
29   Contact Information:
30   Linux NICS <linux.nics@intel.com>
31   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
32
33 *******************************************************************************/
34 /*
35  *  Copyright (C) Archway Digital Solutions.
36  *
37  *  written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
38  *  2/9/2002
39  *
40  *  Copyright (C) Linux Networx.
41  *  Massive upgrade to work with the new intel gigabit NICs.
42  *  <ebiederman at lnxi dot com>
43  *
44  *  Support for 82541ei & 82547ei chips from Intel's Linux driver 5.1.13 added by
45  *  Georg Baum <gbaum@users.sf.net>, sponsored by PetaMem GmbH and linkLINE Communications, Inc.
46  *
47  *  01/2004: Updated to Linux driver 5.2.22 by Georg Baum <gbaum@users.sf.net>
48  */
49
50 /* to get some global routines like printf */
51 #include "etherboot.h"
52 /* to get the interface to the body of the program */
53 #include "nic.h"
54 /* to get the PCI support functions, if this is a PCI NIC */
55 #include "pci.h"
56 #include "timer.h"
57
58 typedef unsigned char *dma_addr_t;
59
60 typedef enum {
61         FALSE = 0,
62         TRUE = 1
63 } boolean_t;
64
65 #define DEBUG 0
66
67
68 /* Some pieces of code are disabled with #if 0 ... #endif.
69  * They are not deleted to show where the etherboot driver differs
70  * from the linux driver below the function level.
71  * Some member variables of the hw struct have been eliminated
72  * and the corresponding inplace checks inserted instead.
73  * Pieces such as LED handling that we definitely don't need are deleted.
74  *
75  * The following defines should not be needed normally,
76  * but may be helpful for debugging purposes. */
77
78 /* Define this if you want to program the transmission control register
79  * the way the Linux driver does it. */
80 #undef LINUX_DRIVER_TCTL
81
82 /* Define this to behave more like the Linux driver. */
83 #undef LINUX_DRIVER
84
85 #include "e1000_hw.h"
86
87 /* NIC specific static variables go here */
88 static struct nic_operations e1000_operations;
89 static struct pci_driver e1000_driver;
90
91 static struct e1000_hw hw;
92 static char tx_pool[128 + 16];
93 static char rx_pool[128 + 16];
94 static char packet[2096];
95
96 static struct e1000_tx_desc *tx_base;
97 static struct e1000_rx_desc *rx_base;
98
99 static int tx_tail;
100 static int rx_tail, rx_last;
101
102 /* Function forward declarations */
103 static int e1000_setup_link(struct e1000_hw *hw);
104 static int e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
105 static int e1000_setup_copper_link(struct e1000_hw *hw);
106 static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
107 static void e1000_config_collision_dist(struct e1000_hw *hw);
108 static int e1000_config_mac_to_phy(struct e1000_hw *hw);
109 static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
110 static int e1000_check_for_link(struct e1000_hw *hw);
111 static int e1000_wait_autoneg(struct e1000_hw *hw);
112 static void e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed, uint16_t *duplex);
113 static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
114 static int e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
115 static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data);
116 static int e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data);
117 static void e1000_phy_hw_reset(struct e1000_hw *hw);
118 static int e1000_phy_reset(struct e1000_hw *hw);
119 static int e1000_detect_gig_phy(struct e1000_hw *hw);
120 static void e1000_irq(struct nic *nic, irq_action_t action);
121
122 /* Printing macros... */
123
124 #define E1000_ERR(args...) printf("e1000: " args)
125
126 #if DEBUG >= 3
127 #define E1000_DBG(args...) printf("e1000: " args)
128 #else
129 #define E1000_DBG(args...)
130 #endif
131
132 #define MSGOUT(S, A, B)     printk(S "\n", A, B)
133 #if DEBUG >= 2
134 #define DEBUGFUNC(F)        DEBUGOUT(F "\n");
135 #else
136 #define DEBUGFUNC(F)
137 #endif
138 #if DEBUG >= 1
139 #define DEBUGOUT(S) printf(S)
140 #define DEBUGOUT1(S,A) printf(S,A)
141 #define DEBUGOUT2(S,A,B) printf(S,A,B)
142 #define DEBUGOUT3(S,A,B,C) printf(S,A,B,C)
143 #define DEBUGOUT7(S,A,B,C,D,E,F,G) printf(S,A,B,C,D,E,F,G)
144 #else
145 #define DEBUGOUT(S)
146 #define DEBUGOUT1(S,A)
147 #define DEBUGOUT2(S,A,B)
148 #define DEBUGOUT3(S,A,B,C)
149 #define DEBUGOUT7(S,A,B,C,D,E,F,G)
150 #endif
151
152 #define E1000_WRITE_REG(a, reg, value) ( \
153     ((a)->mac_type >= e1000_82543) ? \
154         (writel((value), ((a)->hw_addr + E1000_##reg))) : \
155         (writel((value), ((a)->hw_addr + E1000_82542_##reg))))
156
157 #define E1000_READ_REG(a, reg) ( \
158     ((a)->mac_type >= e1000_82543) ? \
159         readl((a)->hw_addr + E1000_##reg) : \
160         readl((a)->hw_addr + E1000_82542_##reg))
161
162 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \
163     ((a)->mac_type >= e1000_82543) ? \
164         writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2))) : \
165         writel((value), ((a)->hw_addr + E1000_82542_##reg + ((offset) << 2))))
166
167 #define E1000_READ_REG_ARRAY(a, reg, offset) ( \
168     ((a)->mac_type >= e1000_82543) ? \
169         readl((a)->hw_addr + E1000_##reg + ((offset) << 2)) : \
170         readl((a)->hw_addr + E1000_82542_##reg + ((offset) << 2)))
171
172 #define E1000_WRITE_FLUSH(a) {uint32_t x; x = E1000_READ_REG(a, STATUS);}
173
174 uint32_t
175 e1000_io_read(struct e1000_hw *hw __unused, uint32_t port)
176 {
177         return inl(port);
178 }
179
180 void
181 e1000_io_write(struct e1000_hw *hw __unused, uint32_t port, uint32_t value)
182 {
183         outl(value, port);
184 }
185
186 static inline void e1000_pci_set_mwi(struct e1000_hw *hw)
187 {
188         pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
189 }
190
191 static inline void e1000_pci_clear_mwi(struct e1000_hw *hw)
192 {
193         pci_write_config_word(hw->pdev, PCI_COMMAND,
194                               hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
195 }
196
197 /******************************************************************************
198  * Raises the EEPROM's clock input.
199  *
200  * hw - Struct containing variables accessed by shared code
201  * eecd - EECD's current value
202  *****************************************************************************/
203 static void
204 e1000_raise_ee_clk(struct e1000_hw *hw,
205                    uint32_t *eecd)
206 {
207         /* Raise the clock input to the EEPROM (by setting the SK bit), and then
208          * wait <delay> microseconds.
209          */
210         *eecd = *eecd | E1000_EECD_SK;
211         E1000_WRITE_REG(hw, EECD, *eecd);
212         E1000_WRITE_FLUSH(hw);
213         udelay(hw->eeprom.delay_usec);
214 }
215
216 /******************************************************************************
217  * Lowers the EEPROM's clock input.
218  *
219  * hw - Struct containing variables accessed by shared code 
220  * eecd - EECD's current value
221  *****************************************************************************/
222 static void
223 e1000_lower_ee_clk(struct e1000_hw *hw,
224                    uint32_t *eecd)
225 {
226         /* Lower the clock input to the EEPROM (by clearing the SK bit), and then 
227          * wait 50 microseconds. 
228          */
229         *eecd = *eecd & ~E1000_EECD_SK;
230         E1000_WRITE_REG(hw, EECD, *eecd);
231         E1000_WRITE_FLUSH(hw);
232         udelay(hw->eeprom.delay_usec);
233 }
234
235 /******************************************************************************
236  * Shift data bits out to the EEPROM.
237  *
238  * hw - Struct containing variables accessed by shared code
239  * data - data to send to the EEPROM
240  * count - number of bits to shift out
241  *****************************************************************************/
242 static void
243 e1000_shift_out_ee_bits(struct e1000_hw *hw,
244                         uint16_t data,
245                         uint16_t count)
246 {
247         struct e1000_eeprom_info *eeprom = &hw->eeprom;
248         uint32_t eecd;
249         uint32_t mask;
250         
251         /* We need to shift "count" bits out to the EEPROM. So, value in the
252          * "data" parameter will be shifted out to the EEPROM one bit at a time.
253          * In order to do this, "data" must be broken down into bits. 
254          */
255         mask = 0x01 << (count - 1);
256         eecd = E1000_READ_REG(hw, EECD);
257         if (eeprom->type == e1000_eeprom_microwire) {
258                 eecd &= ~E1000_EECD_DO;
259         } else if (eeprom->type == e1000_eeprom_spi) {
260                 eecd |= E1000_EECD_DO;
261         }
262         do {
263                 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
264                  * and then raising and then lowering the clock (the SK bit controls
265                  * the clock input to the EEPROM).  A "0" is shifted out to the EEPROM
266                  * by setting "DI" to "0" and then raising and then lowering the clock.
267                  */
268                 eecd &= ~E1000_EECD_DI;
269                 
270                 if(data & mask)
271                         eecd |= E1000_EECD_DI;
272                 
273                 E1000_WRITE_REG(hw, EECD, eecd);
274                 E1000_WRITE_FLUSH(hw);
275                 
276                 udelay(eeprom->delay_usec);
277                 
278                 e1000_raise_ee_clk(hw, &eecd);
279                 e1000_lower_ee_clk(hw, &eecd);
280                 
281                 mask = mask >> 1;
282                 
283         } while(mask);
284
285         /* We leave the "DI" bit set to "0" when we leave this routine. */
286         eecd &= ~E1000_EECD_DI;
287         E1000_WRITE_REG(hw, EECD, eecd);
288 }
289
290 /******************************************************************************
291  * Shift data bits in from the EEPROM
292  *
293  * hw - Struct containing variables accessed by shared code
294  *****************************************************************************/
295 static uint16_t
296 e1000_shift_in_ee_bits(struct e1000_hw *hw,
297                        uint16_t count)
298 {
299         uint32_t eecd;
300         uint32_t i;
301         uint16_t data;
302         
303         /* In order to read a register from the EEPROM, we need to shift 'count' 
304          * bits in from the EEPROM. Bits are "shifted in" by raising the clock
305          * input to the EEPROM (setting the SK bit), and then reading the value of
306          * the "DO" bit.  During this "shifting in" process the "DI" bit should
307          * always be clear.
308          */
309         
310         eecd = E1000_READ_REG(hw, EECD);
311         
312         eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
313         data = 0;
314         
315         for(i = 0; i < count; i++) {
316                 data = data << 1;
317                 e1000_raise_ee_clk(hw, &eecd);
318                 
319                 eecd = E1000_READ_REG(hw, EECD);
320                 
321                 eecd &= ~(E1000_EECD_DI);
322                 if(eecd & E1000_EECD_DO)
323                         data |= 1;
324                 
325                 e1000_lower_ee_clk(hw, &eecd);
326         }
327         
328         return data;
329 }
330
331 /******************************************************************************
332  * Prepares EEPROM for access
333  *
334  * hw - Struct containing variables accessed by shared code
335  *
336  * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 
337  * function should be called before issuing a command to the EEPROM.
338  *****************************************************************************/
339 static int32_t
340 e1000_acquire_eeprom(struct e1000_hw *hw)
341 {
342         struct e1000_eeprom_info *eeprom = &hw->eeprom;
343         uint32_t eecd, i=0;
344
345         eecd = E1000_READ_REG(hw, EECD);
346
347         /* Request EEPROM Access */
348         if(hw->mac_type > e1000_82544) {
349                 eecd |= E1000_EECD_REQ;
350                 E1000_WRITE_REG(hw, EECD, eecd);
351                 eecd = E1000_READ_REG(hw, EECD);
352                 while((!(eecd & E1000_EECD_GNT)) &&
353                       (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
354                         i++;
355                         udelay(5);
356                         eecd = E1000_READ_REG(hw, EECD);
357                 }
358                 if(!(eecd & E1000_EECD_GNT)) {
359                         eecd &= ~E1000_EECD_REQ;
360                         E1000_WRITE_REG(hw, EECD, eecd);
361                         DEBUGOUT("Could not acquire EEPROM grant\n");
362                         return -E1000_ERR_EEPROM;
363                 }
364         }
365
366         /* Setup EEPROM for Read/Write */
367
368         if (eeprom->type == e1000_eeprom_microwire) {
369                 /* Clear SK and DI */
370                 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
371                 E1000_WRITE_REG(hw, EECD, eecd);
372
373                 /* Set CS */
374                 eecd |= E1000_EECD_CS;
375                 E1000_WRITE_REG(hw, EECD, eecd);
376         } else if (eeprom->type == e1000_eeprom_spi) {
377                 /* Clear SK and CS */
378                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
379                 E1000_WRITE_REG(hw, EECD, eecd);
380                 udelay(1);
381         }
382
383         return E1000_SUCCESS;
384 }
385
386 /******************************************************************************
387  * Returns EEPROM to a "standby" state
388  * 
389  * hw - Struct containing variables accessed by shared code
390  *****************************************************************************/
391 static void
392 e1000_standby_eeprom(struct e1000_hw *hw)
393 {
394         struct e1000_eeprom_info *eeprom = &hw->eeprom;
395         uint32_t eecd;
396         
397         eecd = E1000_READ_REG(hw, EECD);
398
399         if(eeprom->type == e1000_eeprom_microwire) {
400
401                 /* Deselect EEPROM */
402                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
403                 E1000_WRITE_REG(hw, EECD, eecd);
404                 E1000_WRITE_FLUSH(hw);
405                 udelay(eeprom->delay_usec);
406         
407                 /* Clock high */
408                 eecd |= E1000_EECD_SK;
409                 E1000_WRITE_REG(hw, EECD, eecd);
410                 E1000_WRITE_FLUSH(hw);
411                 udelay(eeprom->delay_usec);
412         
413                 /* Select EEPROM */
414                 eecd |= E1000_EECD_CS;
415                 E1000_WRITE_REG(hw, EECD, eecd);
416                 E1000_WRITE_FLUSH(hw);
417                 udelay(eeprom->delay_usec);
418
419                 /* Clock low */
420                 eecd &= ~E1000_EECD_SK;
421                 E1000_WRITE_REG(hw, EECD, eecd);
422                 E1000_WRITE_FLUSH(hw);
423                 udelay(eeprom->delay_usec);
424         } else if(eeprom->type == e1000_eeprom_spi) {
425                 /* Toggle CS to flush commands */
426                 eecd |= E1000_EECD_CS;
427                 E1000_WRITE_REG(hw, EECD, eecd);
428                 E1000_WRITE_FLUSH(hw);
429                 udelay(eeprom->delay_usec);
430                 eecd &= ~E1000_EECD_CS;
431                 E1000_WRITE_REG(hw, EECD, eecd);
432                 E1000_WRITE_FLUSH(hw);
433                 udelay(eeprom->delay_usec);
434         }
435 }
436
437 /******************************************************************************
438  * Terminates a command by inverting the EEPROM's chip select pin
439  *
440  * hw - Struct containing variables accessed by shared code
441  *****************************************************************************/
442 static void
443 e1000_release_eeprom(struct e1000_hw *hw)
444 {
445         uint32_t eecd;
446
447         eecd = E1000_READ_REG(hw, EECD);
448
449         if (hw->eeprom.type == e1000_eeprom_spi) {
450                 eecd |= E1000_EECD_CS;  /* Pull CS high */
451                 eecd &= ~E1000_EECD_SK; /* Lower SCK */
452
453                 E1000_WRITE_REG(hw, EECD, eecd);
454
455                 udelay(hw->eeprom.delay_usec);
456         } else if(hw->eeprom.type == e1000_eeprom_microwire) {
457                 /* cleanup eeprom */
458
459                 /* CS on Microwire is active-high */
460                 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
461
462                 E1000_WRITE_REG(hw, EECD, eecd);
463
464                 /* Rising edge of clock */
465                 eecd |= E1000_EECD_SK;
466                 E1000_WRITE_REG(hw, EECD, eecd);
467                 E1000_WRITE_FLUSH(hw);
468                 udelay(hw->eeprom.delay_usec);
469
470                 /* Falling edge of clock */
471                 eecd &= ~E1000_EECD_SK;
472                 E1000_WRITE_REG(hw, EECD, eecd);
473                 E1000_WRITE_FLUSH(hw);
474                 udelay(hw->eeprom.delay_usec);
475         }
476
477         /* Stop requesting EEPROM access */
478         if(hw->mac_type > e1000_82544) {
479                 eecd &= ~E1000_EECD_REQ;
480                 E1000_WRITE_REG(hw, EECD, eecd);
481         }
482 }
483
484 /******************************************************************************
485  * Reads a 16 bit word from the EEPROM.
486  *
487  * hw - Struct containing variables accessed by shared code
488  *****************************************************************************/
489 static int32_t
490 e1000_spi_eeprom_ready(struct e1000_hw *hw)
491 {
492         uint16_t retry_count = 0;
493         uint8_t spi_stat_reg;
494
495         /* Read "Status Register" repeatedly until the LSB is cleared.  The
496          * EEPROM will signal that the command has been completed by clearing
497          * bit 0 of the internal status register.  If it's not cleared within
498          * 5 milliseconds, then error out.
499          */
500         retry_count = 0;
501         do {
502                 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
503                 hw->eeprom.opcode_bits);
504                 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
505                 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
506                         break;
507
508                 udelay(5);
509                 retry_count += 5;
510
511         } while(retry_count < EEPROM_MAX_RETRY_SPI);
512
513         /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
514          * only 0-5mSec on 5V devices)
515          */
516         if(retry_count >= EEPROM_MAX_RETRY_SPI) {
517                 DEBUGOUT("SPI EEPROM Status error\n");
518                 return -E1000_ERR_EEPROM;
519         }
520
521         return E1000_SUCCESS;
522 }
523
524 /******************************************************************************
525  * Reads a 16 bit word from the EEPROM.
526  *
527  * hw - Struct containing variables accessed by shared code
528  * offset - offset of  word in the EEPROM to read
529  * data - word read from the EEPROM
530  * words - number of words to read
531  *****************************************************************************/
532 static int
533 e1000_read_eeprom(struct e1000_hw *hw,
534                   uint16_t offset,
535                   uint16_t words,
536                   uint16_t *data)
537 {
538         struct e1000_eeprom_info *eeprom = &hw->eeprom;
539         uint32_t i = 0;
540         
541         DEBUGFUNC("e1000_read_eeprom");
542
543         /* A check for invalid values:  offset too large, too many words, and not
544          * enough words.
545          */
546         if((offset > eeprom->word_size) || (words > eeprom->word_size - offset) ||
547            (words == 0)) {
548                 DEBUGOUT("\"words\" parameter out of bounds\n");
549                 return -E1000_ERR_EEPROM;
550         }
551
552         /*  Prepare the EEPROM for reading  */
553         if(e1000_acquire_eeprom(hw) != E1000_SUCCESS)
554                 return -E1000_ERR_EEPROM;
555
556         if(eeprom->type == e1000_eeprom_spi) {
557                 uint16_t word_in;
558                 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
559
560                 if(e1000_spi_eeprom_ready(hw)) {
561                         e1000_release_eeprom(hw);
562                         return -E1000_ERR_EEPROM;
563                 }
564
565                 e1000_standby_eeprom(hw);
566
567                 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
568                 if((eeprom->address_bits == 8) && (offset >= 128))
569                         read_opcode |= EEPROM_A8_OPCODE_SPI;
570
571                 /* Send the READ command (opcode + addr)  */
572                 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
573                 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
574
575                 /* Read the data.  The address of the eeprom internally increments with
576                  * each byte (spi) being read, saving on the overhead of eeprom setup
577                  * and tear-down.  The address counter will roll over if reading beyond
578                  * the size of the eeprom, thus allowing the entire memory to be read
579                  * starting from any offset. */
580                 for (i = 0; i < words; i++) {
581                         word_in = e1000_shift_in_ee_bits(hw, 16);
582                         data[i] = (word_in >> 8) | (word_in << 8);
583                 }
584         } else if(eeprom->type == e1000_eeprom_microwire) {
585                 for (i = 0; i < words; i++) {
586                         /*  Send the READ command (opcode + addr)  */
587                         e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
588                                                 eeprom->opcode_bits);
589                         e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
590                                                 eeprom->address_bits);
591
592                         /* Read the data.  For microwire, each word requires the overhead
593                          * of eeprom setup and tear-down. */
594                         data[i] = e1000_shift_in_ee_bits(hw, 16);
595                         e1000_standby_eeprom(hw);
596                 }
597         }
598
599         /* End this read operation */
600         e1000_release_eeprom(hw);
601
602         return E1000_SUCCESS;
603 }
604
605 /******************************************************************************
606  * Verifies that the EEPROM has a valid checksum
607  * 
608  * hw - Struct containing variables accessed by shared code
609  *
610  * Reads the first 64 16 bit words of the EEPROM and sums the values read.
611  * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
612  * valid.
613  *****************************************************************************/
614 static int
615 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
616 {
617         uint16_t checksum = 0;
618         uint16_t i, eeprom_data;
619
620         DEBUGFUNC("e1000_validate_eeprom_checksum");
621
622         for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
623                 if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
624                         DEBUGOUT("EEPROM Read Error\n");
625                         return -E1000_ERR_EEPROM;
626                 }
627                 checksum += eeprom_data;
628         }
629         
630         if(checksum == (uint16_t) EEPROM_SUM)
631                 return E1000_SUCCESS;
632         else {
633                 DEBUGOUT("EEPROM Checksum Invalid\n");    
634                 return -E1000_ERR_EEPROM;
635         }
636 }
637
638 /******************************************************************************
639  * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
640  * second function of dual function devices
641  *
642  * hw - Struct containing variables accessed by shared code
643  *****************************************************************************/
644 static int 
645 e1000_read_mac_addr(struct e1000_hw *hw)
646 {
647         uint16_t offset;
648         uint16_t eeprom_data;
649         int i;
650
651         DEBUGFUNC("e1000_read_mac_addr");
652
653         for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
654                 offset = i >> 1;
655                 if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
656                         DEBUGOUT("EEPROM Read Error\n");
657                         return -E1000_ERR_EEPROM;
658                 }
659                 hw->mac_addr[i] = eeprom_data & 0xff;
660                 hw->mac_addr[i+1] = (eeprom_data >> 8) & 0xff;
661         }
662         if(((hw->mac_type == e1000_82546) || (hw->mac_type == e1000_82546_rev_3)) &&
663                 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1))
664                 /* Invert the last bit if this is the second device */
665                 hw->mac_addr[5] ^= 1;
666         return E1000_SUCCESS;
667 }
668
669 /******************************************************************************
670  * Initializes receive address filters.
671  *
672  * hw - Struct containing variables accessed by shared code 
673  *
674  * Places the MAC address in receive address register 0 and clears the rest
675  * of the receive addresss registers. Clears the multicast table. Assumes
676  * the receiver is in reset when the routine is called.
677  *****************************************************************************/
678 static void
679 e1000_init_rx_addrs(struct e1000_hw *hw)
680 {
681         uint32_t i;
682         uint32_t addr_low;
683         uint32_t addr_high;
684         
685         DEBUGFUNC("e1000_init_rx_addrs");
686         
687         /* Setup the receive address. */
688         DEBUGOUT("Programming MAC Address into RAR[0]\n");
689         addr_low = (hw->mac_addr[0] |
690                 (hw->mac_addr[1] << 8) |
691                 (hw->mac_addr[2] << 16) | (hw->mac_addr[3] << 24));
692         
693         addr_high = (hw->mac_addr[4] |
694                 (hw->mac_addr[5] << 8) | E1000_RAH_AV);
695         
696         E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
697         E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
698         
699         /* Zero out the other 15 receive addresses. */
700         DEBUGOUT("Clearing RAR[1-15]\n");
701         for(i = 1; i < E1000_RAR_ENTRIES; i++) {
702                 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
703                 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
704         }
705 }
706
707 /******************************************************************************
708  * Clears the VLAN filer table
709  *
710  * hw - Struct containing variables accessed by shared code
711  *****************************************************************************/
712 static void
713 e1000_clear_vfta(struct e1000_hw *hw)
714 {
715         uint32_t offset;
716     
717         for(offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
718                 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
719 }
720
721 /******************************************************************************
722 * Writes a value to one of the devices registers using port I/O (as opposed to
723 * memory mapped I/O). Only 82544 and newer devices support port I/O. *
724 * hw - Struct containing variables accessed by shared code
725 * offset - offset to write to * value - value to write
726 *****************************************************************************/
727 void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value){
728         uint32_t io_addr = hw->io_base;
729         uint32_t io_data = hw->io_base + 4;
730         e1000_io_write(hw, io_addr, offset);
731         e1000_io_write(hw, io_data, value);
732 }
733
734 /******************************************************************************
735  * Set the phy type member in the hw struct.
736  *
737  * hw - Struct containing variables accessed by shared code
738  *****************************************************************************/
739 static int32_t
740 e1000_set_phy_type(struct e1000_hw *hw)
741 {
742         DEBUGFUNC("e1000_set_phy_type");
743
744         switch(hw->phy_id) {
745         case M88E1000_E_PHY_ID:
746         case M88E1000_I_PHY_ID:
747         case M88E1011_I_PHY_ID:
748                 hw->phy_type = e1000_phy_m88;
749                 break;
750         case IGP01E1000_I_PHY_ID:
751                 hw->phy_type = e1000_phy_igp;
752                 break;
753         default:
754                 /* Should never have loaded on this device */
755                 hw->phy_type = e1000_phy_undefined;
756                 return -E1000_ERR_PHY_TYPE;
757         }
758
759         return E1000_SUCCESS;
760 }
761
762 /******************************************************************************
763  * IGP phy init script - initializes the GbE PHY
764  *
765  * hw - Struct containing variables accessed by shared code
766  *****************************************************************************/
767 static void
768 e1000_phy_init_script(struct e1000_hw *hw)
769 {
770         DEBUGFUNC("e1000_phy_init_script");
771
772 #if 0
773         /* See e1000_sw_init() of the Linux driver */
774         if(hw->phy_init_script) {
775 #else
776         if((hw->mac_type == e1000_82541) ||
777            (hw->mac_type == e1000_82547) ||
778            (hw->mac_type == e1000_82541_rev_2) ||
779            (hw->mac_type == e1000_82547_rev_2)) {
780 #endif
781                 mdelay(20);
782
783                 e1000_write_phy_reg(hw,0x0000,0x0140);
784
785                 mdelay(5);
786
787                 if(hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547) {
788                         e1000_write_phy_reg(hw, 0x1F95, 0x0001);
789
790                         e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
791
792                         e1000_write_phy_reg(hw, 0x1F79, 0x0018);
793
794                         e1000_write_phy_reg(hw, 0x1F30, 0x1600);
795
796                         e1000_write_phy_reg(hw, 0x1F31, 0x0014);
797
798                         e1000_write_phy_reg(hw, 0x1F32, 0x161C);
799
800                         e1000_write_phy_reg(hw, 0x1F94, 0x0003);
801
802                         e1000_write_phy_reg(hw, 0x1F96, 0x003F);
803
804                         e1000_write_phy_reg(hw, 0x2010, 0x0008);
805                 } else {
806                         e1000_write_phy_reg(hw, 0x1F73, 0x0099);
807                 }
808
809                 e1000_write_phy_reg(hw, 0x0000, 0x3300);
810
811
812                 if(hw->mac_type == e1000_82547) {
813                         uint16_t fused, fine, coarse;
814
815                         /* Move to analog registers page */
816                         e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
817
818                         if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
819                                 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
820
821                                 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
822                                 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
823
824                                 if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
825                                         coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
826                                         fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
827                                 } else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
828                                         fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
829
830                                 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
831                                         (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
832                                         (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
833
834                                 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
835                                 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
836                                                 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
837                         }
838                 }
839         }
840 }
841
842 /******************************************************************************
843  * Set the mac type member in the hw struct.
844  * 
845  * hw - Struct containing variables accessed by shared code
846  *****************************************************************************/
847 static int
848 e1000_set_mac_type(struct e1000_hw *hw)
849 {
850         DEBUGFUNC("e1000_set_mac_type");
851
852         switch (hw->device_id) {
853         case E1000_DEV_ID_82542:
854                 switch (hw->revision_id) {
855                 case E1000_82542_2_0_REV_ID:
856                         hw->mac_type = e1000_82542_rev2_0;
857                         break;
858                 case E1000_82542_2_1_REV_ID:
859                         hw->mac_type = e1000_82542_rev2_1;
860                         break;
861                 default:
862                         /* Invalid 82542 revision ID */
863                         return -E1000_ERR_MAC_TYPE;
864                 }
865                 break;
866         case E1000_DEV_ID_82543GC_FIBER:
867         case E1000_DEV_ID_82543GC_COPPER:
868                 hw->mac_type = e1000_82543;
869                 break;
870         case E1000_DEV_ID_82544EI_COPPER:
871         case E1000_DEV_ID_82544EI_FIBER:
872         case E1000_DEV_ID_82544GC_COPPER:
873         case E1000_DEV_ID_82544GC_LOM:
874                 hw->mac_type = e1000_82544;
875                 break;
876         case E1000_DEV_ID_82540EM:
877         case E1000_DEV_ID_82540EM_LOM:
878         case E1000_DEV_ID_82540EP:
879         case E1000_DEV_ID_82540EP_LOM:
880         case E1000_DEV_ID_82540EP_LP:
881                 hw->mac_type = e1000_82540;
882                 break;
883         case E1000_DEV_ID_82545EM_COPPER:
884         case E1000_DEV_ID_82545EM_FIBER:
885                 hw->mac_type = e1000_82545;
886                 break;
887         case E1000_DEV_ID_82545GM_COPPER:
888         case E1000_DEV_ID_82545GM_FIBER:
889         case E1000_DEV_ID_82545GM_SERDES:
890                 hw->mac_type = e1000_82545_rev_3;
891                 break;
892         case E1000_DEV_ID_82546EB_COPPER:
893         case E1000_DEV_ID_82546EB_FIBER:
894         case E1000_DEV_ID_82546EB_QUAD_COPPER:
895                 hw->mac_type = e1000_82546;
896                 break;
897         case E1000_DEV_ID_82546GB_COPPER:
898         case E1000_DEV_ID_82546GB_FIBER:
899         case E1000_DEV_ID_82546GB_SERDES:
900                 hw->mac_type = e1000_82546_rev_3;
901                 break;
902         case E1000_DEV_ID_82541EI:
903         case E1000_DEV_ID_82541EI_MOBILE:
904                 hw->mac_type = e1000_82541;
905                 break;
906         case E1000_DEV_ID_82541ER:
907         case E1000_DEV_ID_82541GI:
908         case E1000_DEV_ID_82541GI_MOBILE:
909                 hw->mac_type = e1000_82541_rev_2;
910                 break;
911         case E1000_DEV_ID_82547EI:
912                 hw->mac_type = e1000_82547;
913                 break;
914         case E1000_DEV_ID_82547GI:
915                 hw->mac_type = e1000_82547_rev_2;
916                 break;
917         default:
918                 /* Should never have loaded on this device */
919                 return -E1000_ERR_MAC_TYPE;
920         }
921
922         return E1000_SUCCESS;
923 }
924
925 /*****************************************************************************
926  * Set media type and TBI compatibility.
927  *
928  * hw - Struct containing variables accessed by shared code
929  * **************************************************************************/
930 static void
931 e1000_set_media_type(struct e1000_hw *hw)
932 {
933         uint32_t status;
934
935         DEBUGFUNC("e1000_set_media_type");
936         
937         if(hw->mac_type != e1000_82543) {
938                 /* tbi_compatibility is only valid on 82543 */
939                 hw->tbi_compatibility_en = FALSE;
940         }
941
942         switch (hw->device_id) {
943                 case E1000_DEV_ID_82545GM_SERDES:
944                 case E1000_DEV_ID_82546GB_SERDES:
945                         hw->media_type = e1000_media_type_internal_serdes;
946                         break;
947                 default:
948                         if(hw->mac_type >= e1000_82543) {
949                                 status = E1000_READ_REG(hw, STATUS);
950                                 if(status & E1000_STATUS_TBIMODE) {
951                                         hw->media_type = e1000_media_type_fiber;
952                                         /* tbi_compatibility not valid on fiber */
953                                         hw->tbi_compatibility_en = FALSE;
954                                 } else {
955                                         hw->media_type = e1000_media_type_copper;
956                                 }
957                         } else {
958                                 /* This is an 82542 (fiber only) */
959                                 hw->media_type = e1000_media_type_fiber;
960                         }
961         }
962 }
963
964 /******************************************************************************
965  * Reset the transmit and receive units; mask and clear all interrupts.
966  *
967  * hw - Struct containing variables accessed by shared code
968  *****************************************************************************/
969 static void
970 e1000_reset_hw(struct e1000_hw *hw)
971 {
972         uint32_t ctrl;
973         uint32_t ctrl_ext;
974         uint32_t icr;
975         uint32_t manc;
976         
977         DEBUGFUNC("e1000_reset_hw");
978         
979         /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
980         if(hw->mac_type == e1000_82542_rev2_0) {
981                 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
982                 e1000_pci_clear_mwi(hw);
983         }
984
985         /* Clear interrupt mask to stop board from generating interrupts */
986         DEBUGOUT("Masking off all interrupts\n");
987         E1000_WRITE_REG(hw, IMC, 0xffffffff);
988         
989         /* Disable the Transmit and Receive units.  Then delay to allow
990          * any pending transactions to complete before we hit the MAC with
991          * the global reset.
992          */
993         E1000_WRITE_REG(hw, RCTL, 0);
994         E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
995         E1000_WRITE_FLUSH(hw);
996
997         /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
998         hw->tbi_compatibility_on = FALSE;
999
1000         /* Delay to allow any outstanding PCI transactions to complete before
1001          * resetting the device
1002          */ 
1003         mdelay(10);
1004
1005         ctrl = E1000_READ_REG(hw, CTRL);
1006
1007         /* Must reset the PHY before resetting the MAC */
1008         if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1009                 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
1010                 mdelay(5);
1011         }
1012
1013         /* Issue a global reset to the MAC.  This will reset the chip's
1014          * transmit, receive, DMA, and link units.  It will not effect
1015          * the current PCI configuration.  The global reset bit is self-
1016          * clearing, and should clear within a microsecond.
1017          */
1018         DEBUGOUT("Issuing a global reset to MAC\n");
1019
1020         switch(hw->mac_type) {
1021                 case e1000_82544:
1022                 case e1000_82540:
1023                 case e1000_82545:
1024                 case e1000_82546:
1025                 case e1000_82541:
1026                 case e1000_82541_rev_2:
1027                         /* These controllers can't ack the 64-bit write when issuing the
1028                          * reset, so use IO-mapping as a workaround to issue the reset */
1029                         E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
1030                         break;
1031                 case e1000_82545_rev_3:
1032                 case e1000_82546_rev_3:
1033                         /* Reset is performed on a shadow of the control register */
1034                         E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
1035                         break;
1036                 default:
1037                         E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
1038                         break;
1039         }
1040
1041         /* After MAC reset, force reload of EEPROM to restore power-on settings to
1042          * device.  Later controllers reload the EEPROM automatically, so just wait
1043          * for reload to complete.
1044          */
1045         switch(hw->mac_type) {
1046                 case e1000_82542_rev2_0:
1047                 case e1000_82542_rev2_1:
1048                 case e1000_82543:
1049                 case e1000_82544:
1050                         /* Wait for reset to complete */
1051                         udelay(10);
1052                         ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1053                         ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1054                         E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1055                         E1000_WRITE_FLUSH(hw);
1056                         /* Wait for EEPROM reload */
1057                         mdelay(2);
1058                         break;
1059                 case e1000_82541:
1060                 case e1000_82541_rev_2:
1061                 case e1000_82547:
1062                 case e1000_82547_rev_2:
1063                         /* Wait for EEPROM reload */
1064                         mdelay(20);
1065                         break;
1066                 default:
1067                         /* Wait for EEPROM reload (it happens automatically) */
1068                         mdelay(5);
1069                         break;
1070         }
1071
1072         /* Disable HW ARPs on ASF enabled adapters */
1073         if(hw->mac_type >= e1000_82540) {
1074                 manc = E1000_READ_REG(hw, MANC);
1075                 manc &= ~(E1000_MANC_ARP_EN);
1076                 E1000_WRITE_REG(hw, MANC, manc);
1077         }
1078
1079         if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1080                 e1000_phy_init_script(hw);
1081         }
1082
1083         /* Clear interrupt mask to stop board from generating interrupts */
1084         DEBUGOUT("Masking off all interrupts\n");
1085         E1000_WRITE_REG(hw, IMC, 0xffffffff);
1086         
1087         /* Clear any pending interrupt events. */
1088         icr = E1000_READ_REG(hw, ICR);
1089
1090         /* If MWI was previously enabled, reenable it. */
1091         if(hw->mac_type == e1000_82542_rev2_0) {
1092 #ifdef LINUX_DRIVER
1093                 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1094 #endif
1095                         e1000_pci_set_mwi(hw);
1096         }
1097 }
1098
1099 /******************************************************************************
1100  * Performs basic configuration of the adapter.
1101  *
1102  * hw - Struct containing variables accessed by shared code
1103  * 
1104  * Assumes that the controller has previously been reset and is in a 
1105  * post-reset uninitialized state. Initializes the receive address registers,
1106  * multicast table, and VLAN filter table. Calls routines to setup link
1107  * configuration and flow control settings. Clears all on-chip counters. Leaves
1108  * the transmit and receive units disabled and uninitialized.
1109  *****************************************************************************/
1110 static int
1111 e1000_init_hw(struct e1000_hw *hw)
1112 {
1113         uint32_t ctrl, status;
1114         uint32_t i;
1115         int32_t ret_val;
1116         uint16_t pcix_cmd_word;
1117         uint16_t pcix_stat_hi_word;
1118         uint16_t cmd_mmrbc;
1119         uint16_t stat_mmrbc;
1120         e1000_bus_type bus_type = e1000_bus_type_unknown;
1121
1122         DEBUGFUNC("e1000_init_hw");
1123
1124         /* Set the media type and TBI compatibility */
1125         e1000_set_media_type(hw);
1126
1127         /* Disabling VLAN filtering. */
1128         DEBUGOUT("Initializing the IEEE VLAN\n");
1129         E1000_WRITE_REG(hw, VET, 0);
1130         
1131         e1000_clear_vfta(hw);
1132         
1133         /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
1134         if(hw->mac_type == e1000_82542_rev2_0) {
1135                 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1136                 e1000_pci_clear_mwi(hw);
1137                 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
1138                 E1000_WRITE_FLUSH(hw);
1139                 mdelay(5);
1140         }
1141         
1142         /* Setup the receive address. This involves initializing all of the Receive
1143          * Address Registers (RARs 0 - 15).
1144          */
1145         e1000_init_rx_addrs(hw);
1146         
1147         /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
1148         if(hw->mac_type == e1000_82542_rev2_0) {
1149                 E1000_WRITE_REG(hw, RCTL, 0);
1150                 E1000_WRITE_FLUSH(hw);
1151                 mdelay(1);
1152 #ifdef LINUX_DRIVER
1153                 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1154 #endif
1155                         e1000_pci_set_mwi(hw);
1156         }
1157         
1158         /* Zero out the Multicast HASH table */
1159         DEBUGOUT("Zeroing the MTA\n");
1160         for(i = 0; i < E1000_MC_TBL_SIZE; i++)
1161                 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
1162         
1163 #if 0
1164         /* Set the PCI priority bit correctly in the CTRL register.  This
1165          * determines if the adapter gives priority to receives, or if it
1166          * gives equal priority to transmits and receives.
1167          */
1168         if(hw->dma_fairness) {
1169                 ctrl = E1000_READ_REG(hw, CTRL);
1170                 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
1171         }
1172 #endif
1173
1174         switch(hw->mac_type) {
1175                 case e1000_82545_rev_3:
1176                 case e1000_82546_rev_3:
1177                         break;
1178                 default:
1179                         if (hw->mac_type >= e1000_82543) {
1180                                 /* See e1000_get_bus_info() of the Linux driver */
1181                                 status = E1000_READ_REG(hw, STATUS);
1182                                 bus_type = (status & E1000_STATUS_PCIX_MODE) ?
1183                                         e1000_bus_type_pcix : e1000_bus_type_pci;
1184                         }
1185
1186                         /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
1187                         if(bus_type == e1000_bus_type_pcix) {
1188                                 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
1189                                 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
1190                                 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
1191                                         PCIX_COMMAND_MMRBC_SHIFT;
1192                                 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
1193                                         PCIX_STATUS_HI_MMRBC_SHIFT;
1194                                 if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
1195                                         stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
1196                                 if(cmd_mmrbc > stat_mmrbc) {
1197                                         pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
1198                                         pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
1199                                         pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER, pcix_cmd_word);
1200                                 }
1201                         }
1202                         break;
1203         }
1204
1205         /* Call a subroutine to configure the link and setup flow control. */
1206         ret_val = e1000_setup_link(hw);
1207         
1208         /* Set the transmit descriptor write-back policy */
1209         if(hw->mac_type > e1000_82544) {
1210                 ctrl = E1000_READ_REG(hw, TXDCTL);
1211                 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
1212                 E1000_WRITE_REG(hw, TXDCTL, ctrl);
1213         }
1214
1215 #if 0
1216         /* Clear all of the statistics registers (clear on read).  It is
1217          * important that we do this after we have tried to establish link
1218          * because the symbol error count will increment wildly if there
1219          * is no link.
1220          */
1221         e1000_clear_hw_cntrs(hw);
1222 #endif
1223
1224         return ret_val;
1225 }
1226
1227 /******************************************************************************
1228  * Adjust SERDES output amplitude based on EEPROM setting.
1229  *
1230  * hw - Struct containing variables accessed by shared code.
1231  *****************************************************************************/
1232 static int32_t
1233 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
1234 {
1235         uint16_t eeprom_data;
1236         int32_t  ret_val;
1237
1238         DEBUGFUNC("e1000_adjust_serdes_amplitude");
1239
1240         if(hw->media_type != e1000_media_type_internal_serdes)
1241                 return E1000_SUCCESS;
1242
1243         switch(hw->mac_type) {
1244                 case e1000_82545_rev_3:
1245                 case e1000_82546_rev_3:
1246                         break;
1247                 default:
1248                         return E1000_SUCCESS;
1249         }
1250
1251         if ((ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,
1252                                         &eeprom_data))) {
1253                 return ret_val;
1254         }
1255
1256         if(eeprom_data != EEPROM_RESERVED_WORD) {
1257                 /* Adjust SERDES output amplitude only. */
1258                 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
1259                 if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL,
1260                                                   eeprom_data)))
1261                         return ret_val;
1262         }
1263
1264         return E1000_SUCCESS;
1265 }
1266                                                                    
1267 /******************************************************************************
1268  * Configures flow control and link settings.
1269  * 
1270  * hw - Struct containing variables accessed by shared code
1271  * 
1272  * Determines which flow control settings to use. Calls the apropriate media-
1273  * specific link configuration function. Configures the flow control settings.
1274  * Assuming the adapter has a valid link partner, a valid link should be
1275  * established. Assumes the hardware has previously been reset and the 
1276  * transmitter and receiver are not enabled.
1277  *****************************************************************************/
1278 static int
1279 e1000_setup_link(struct e1000_hw *hw)
1280 {
1281         uint32_t ctrl_ext;
1282         int32_t ret_val;
1283         uint16_t eeprom_data;
1284
1285         DEBUGFUNC("e1000_setup_link");
1286         
1287         /* Read and store word 0x0F of the EEPROM. This word contains bits
1288          * that determine the hardware's default PAUSE (flow control) mode,
1289          * a bit that determines whether the HW defaults to enabling or
1290          * disabling auto-negotiation, and the direction of the
1291          * SW defined pins. If there is no SW over-ride of the flow
1292          * control setting, then the variable hw->fc will
1293          * be initialized based on a value in the EEPROM.
1294          */
1295         if(e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data) < 0) {
1296                 DEBUGOUT("EEPROM Read Error\n");
1297                 return -E1000_ERR_EEPROM;
1298         }
1299         
1300         if(hw->fc == e1000_fc_default) {
1301                 if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
1302                         hw->fc = e1000_fc_none;
1303                 else if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 
1304                         EEPROM_WORD0F_ASM_DIR)
1305                         hw->fc = e1000_fc_tx_pause;
1306                 else
1307                         hw->fc = e1000_fc_full;
1308         }
1309         
1310         /* We want to save off the original Flow Control configuration just
1311          * in case we get disconnected and then reconnected into a different
1312          * hub or switch with different Flow Control capabilities.
1313          */
1314         if(hw->mac_type == e1000_82542_rev2_0)
1315                 hw->fc &= (~e1000_fc_tx_pause);
1316
1317 #if 0
1318         /* See e1000_sw_init() of the Linux driver */
1319         if((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
1320 #else
1321         if((hw->mac_type < e1000_82543) && (hw->mac_type >= e1000_82543))
1322 #endif
1323                 hw->fc &= (~e1000_fc_rx_pause);
1324         
1325 #if 0
1326         hw->original_fc = hw->fc;
1327 #endif
1328
1329         DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
1330         
1331         /* Take the 4 bits from EEPROM word 0x0F that determine the initial
1332          * polarity value for the SW controlled pins, and setup the
1333          * Extended Device Control reg with that info.
1334          * This is needed because one of the SW controlled pins is used for
1335          * signal detection.  So this should be done before e1000_setup_pcs_link()
1336          * or e1000_phy_setup() is called.
1337          */
1338         if(hw->mac_type == e1000_82543) {
1339                 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 
1340                         SWDPIO__EXT_SHIFT);
1341                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1342         }
1343         
1344         /* Call the necessary subroutine to configure the link. */
1345         ret_val = (hw->media_type == e1000_media_type_copper) ?
1346                 e1000_setup_copper_link(hw) :
1347                 e1000_setup_fiber_serdes_link(hw);
1348         if (ret_val < 0) {
1349                 return ret_val;
1350         }
1351         
1352         /* Initialize the flow control address, type, and PAUSE timer
1353          * registers to their default values.  This is done even if flow
1354          * control is disabled, because it does not hurt anything to
1355          * initialize these registers.
1356          */
1357         DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
1358         
1359         E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1360         E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1361         E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1362 #if 0
1363         E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
1364 #else
1365         E1000_WRITE_REG(hw, FCTTV, FC_DEFAULT_TX_TIMER);
1366 #endif
1367         
1368         /* Set the flow control receive threshold registers.  Normally,
1369          * these registers will be set to a default threshold that may be
1370          * adjusted later by the driver's runtime code.  However, if the
1371          * ability to transmit pause frames in not enabled, then these
1372          * registers will be set to 0. 
1373          */
1374         if(!(hw->fc & e1000_fc_tx_pause)) {
1375                 E1000_WRITE_REG(hw, FCRTL, 0);
1376                 E1000_WRITE_REG(hw, FCRTH, 0);
1377         } else {
1378                 /* We need to set up the Receive Threshold high and low water marks
1379                  * as well as (optionally) enabling the transmission of XON frames.
1380                  */
1381 #if 0
1382                 if(hw->fc_send_xon) {
1383                         E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
1384                         E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1385                 } else {
1386                         E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
1387                         E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1388                 }
1389 #else
1390                 E1000_WRITE_REG(hw, FCRTL, (FC_DEFAULT_LO_THRESH | E1000_FCRTL_XONE));
1391                 E1000_WRITE_REG(hw, FCRTH, FC_DEFAULT_HI_THRESH);
1392 #endif
1393         }
1394         return ret_val;
1395 }
1396
1397 /******************************************************************************
1398  * Sets up link for a fiber based or serdes based adapter
1399  *
1400  * hw - Struct containing variables accessed by shared code
1401  *
1402  * Manipulates Physical Coding Sublayer functions in order to configure
1403  * link. Assumes the hardware has been previously reset and the transmitter
1404  * and receiver are not enabled.
1405  *****************************************************************************/
1406 static int
1407 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1408 {
1409         uint32_t ctrl;
1410         uint32_t status;
1411         uint32_t txcw = 0;
1412         uint32_t i;
1413         uint32_t signal = 0;
1414         int32_t ret_val;
1415
1416         DEBUGFUNC("e1000_setup_fiber_serdes_link");
1417
1418         /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be 
1419          * set when the optics detect a signal. On older adapters, it will be 
1420          * cleared when there is a signal.  This applies to fiber media only.
1421          * If we're on serdes media, adjust the output amplitude to value set in
1422          * the EEPROM.
1423          */
1424         ctrl = E1000_READ_REG(hw, CTRL);
1425         if(hw->media_type == e1000_media_type_fiber)
1426                 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
1427
1428         if((ret_val = e1000_adjust_serdes_amplitude(hw)))
1429                 return ret_val;
1430
1431         /* Take the link out of reset */
1432         ctrl &= ~(E1000_CTRL_LRST);
1433
1434 #if 0
1435         /* Adjust VCO speed to improve BER performance */
1436         if((ret_val = e1000_set_vco_speed(hw)))
1437                 return ret_val;
1438 #endif
1439
1440         e1000_config_collision_dist(hw);
1441         
1442         /* Check for a software override of the flow control settings, and setup
1443          * the device accordingly.  If auto-negotiation is enabled, then software
1444          * will have to set the "PAUSE" bits to the correct value in the Tranmsit
1445          * Config Word Register (TXCW) and re-start auto-negotiation.  However, if
1446          * auto-negotiation is disabled, then software will have to manually 
1447          * configure the two flow control enable bits in the CTRL register.
1448          *
1449          * The possible values of the "fc" parameter are:
1450          *      0:  Flow control is completely disabled
1451          *      1:  Rx flow control is enabled (we can receive pause frames, but 
1452          *          not send pause frames).
1453          *      2:  Tx flow control is enabled (we can send pause frames but we do
1454          *          not support receiving pause frames).
1455          *      3:  Both Rx and TX flow control (symmetric) are enabled.
1456          */
1457         switch (hw->fc) {
1458         case e1000_fc_none:
1459                 /* Flow control is completely disabled by a software over-ride. */
1460                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1461                 break;
1462         case e1000_fc_rx_pause:
1463                 /* RX Flow control is enabled and TX Flow control is disabled by a 
1464                  * software over-ride. Since there really isn't a way to advertise 
1465                  * that we are capable of RX Pause ONLY, we will advertise that we
1466                  * support both symmetric and asymmetric RX PAUSE. Later, we will
1467                  *  disable the adapter's ability to send PAUSE frames.
1468                  */
1469                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1470                 break;
1471         case e1000_fc_tx_pause:
1472                 /* TX Flow control is enabled, and RX Flow control is disabled, by a 
1473                  * software over-ride.
1474                  */
1475                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1476                 break;
1477         case e1000_fc_full:
1478                 /* Flow control (both RX and TX) is enabled by a software over-ride. */
1479                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1480                 break;
1481         default:
1482                 DEBUGOUT("Flow control param set incorrectly\n");
1483                 return -E1000_ERR_CONFIG;
1484                 break;
1485         }
1486         
1487         /* Since auto-negotiation is enabled, take the link out of reset (the link
1488          * will be in reset, because we previously reset the chip). This will
1489          * restart auto-negotiation.  If auto-neogtiation is successful then the
1490          * link-up status bit will be set and the flow control enable bits (RFCE
1491          * and TFCE) will be set according to their negotiated value.
1492          */
1493         DEBUGOUT("Auto-negotiation enabled\n");
1494         
1495         E1000_WRITE_REG(hw, TXCW, txcw);
1496         E1000_WRITE_REG(hw, CTRL, ctrl);
1497         E1000_WRITE_FLUSH(hw);
1498         
1499         hw->txcw = txcw;
1500         mdelay(1);
1501         
1502         /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
1503          * indication in the Device Status Register.  Time-out if a link isn't 
1504          * seen in 500 milliseconds seconds (Auto-negotiation should complete in 
1505          * less than 500 milliseconds even if the other end is doing it in SW).
1506          * For internal serdes, we just assume a signal is present, then poll.
1507          */
1508         if(hw->media_type == e1000_media_type_internal_serdes ||
1509            (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
1510                 DEBUGOUT("Looking for Link\n");
1511                 for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
1512                         mdelay(10);
1513                         status = E1000_READ_REG(hw, STATUS);
1514                         if(status & E1000_STATUS_LU) break;
1515                 }
1516                 if(i == (LINK_UP_TIMEOUT / 10)) {
1517                         DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1518                         hw->autoneg_failed = 1;
1519                         /* AutoNeg failed to achieve a link, so we'll call 
1520                          * e1000_check_for_link. This routine will force the link up if
1521                          * we detect a signal. This will allow us to communicate with
1522                          * non-autonegotiating link partners.
1523                          */
1524                         if((ret_val = e1000_check_for_link(hw))) {
1525                                 DEBUGOUT("Error while checking for link\n");
1526                                 return ret_val;
1527                         }
1528                         hw->autoneg_failed = 0;
1529                 } else {
1530                         hw->autoneg_failed = 0;
1531                         DEBUGOUT("Valid Link Found\n");
1532                 }
1533         } else {
1534                 DEBUGOUT("No Signal Detected\n");
1535         }
1536         return E1000_SUCCESS;
1537 }
1538
1539 /******************************************************************************
1540 * Detects which PHY is present and the speed and duplex
1541 *
1542 * hw - Struct containing variables accessed by shared code
1543 ******************************************************************************/
1544 static int
1545 e1000_setup_copper_link(struct e1000_hw *hw)
1546 {
1547         uint32_t ctrl;
1548         int32_t ret_val;
1549         uint16_t i;
1550         uint16_t phy_data;
1551         
1552         DEBUGFUNC("e1000_setup_copper_link");
1553         
1554         ctrl = E1000_READ_REG(hw, CTRL);
1555         /* With 82543, we need to force speed and duplex on the MAC equal to what
1556          * the PHY speed and duplex configuration is. In addition, we need to
1557          * perform a hardware reset on the PHY to take it out of reset.
1558          */
1559         if(hw->mac_type > e1000_82543) {
1560                 ctrl |= E1000_CTRL_SLU;
1561                 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1562                 E1000_WRITE_REG(hw, CTRL, ctrl);
1563         } else {
1564                 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1565                 E1000_WRITE_REG(hw, CTRL, ctrl);
1566                 e1000_phy_hw_reset(hw);
1567         }
1568         
1569         /* Make sure we have a valid PHY */
1570         if((ret_val = e1000_detect_gig_phy(hw))) {
1571                 DEBUGOUT("Error, did not detect valid phy.\n");
1572                 return ret_val;
1573         }
1574         DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
1575
1576         if(hw->mac_type <= e1000_82543 ||
1577            hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1578 #if 0
1579            hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
1580                 hw->phy_reset_disable = FALSE;
1581
1582         if(!hw->phy_reset_disable) {
1583 #else
1584            hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) {
1585 #endif
1586         if (hw->phy_type == e1000_phy_igp) {
1587
1588                 if((ret_val = e1000_phy_reset(hw))) {
1589                         DEBUGOUT("Error Resetting the PHY\n");
1590                         return ret_val;
1591                 }
1592
1593                 /* Wait 10ms for MAC to configure PHY from eeprom settings */
1594                 mdelay(15);
1595
1596 #if 0
1597                 /* disable lplu d3 during driver init */
1598                 if((ret_val = e1000_set_d3_lplu_state(hw, FALSE))) {
1599                         DEBUGOUT("Error Disabling LPLU D3\n");
1600                         return ret_val;
1601                 }
1602
1603                 /* Configure mdi-mdix settings */
1604                 if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
1605                                                  &phy_data)))
1606                         return ret_val;
1607
1608                 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1609                         hw->dsp_config_state = e1000_dsp_config_disabled;
1610                         /* Force MDI for IGP B-0 PHY */
1611                         phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX |
1612                                       IGP01E1000_PSCR_FORCE_MDI_MDIX);
1613                         hw->mdix = 1;
1614
1615                 } else {
1616                         hw->dsp_config_state = e1000_dsp_config_enabled;
1617                         phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1618
1619                         switch (hw->mdix) {
1620                         case 1:
1621                                 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1622                                 break;
1623                         case 2:
1624                                 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1625                                 break;
1626                         case 0:
1627                         default:
1628                                 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1629                                 break;
1630                         }
1631                 }
1632                 if((ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
1633                                                   phy_data)))
1634                         return ret_val;
1635
1636                 /* set auto-master slave resolution settings */
1637                 e1000_ms_type phy_ms_setting = hw->master_slave;
1638
1639                 if(hw->ffe_config_state == e1000_ffe_config_active)
1640                         hw->ffe_config_state = e1000_ffe_config_enabled;
1641
1642                 if(hw->dsp_config_state == e1000_dsp_config_activated)
1643                         hw->dsp_config_state = e1000_dsp_config_enabled;
1644 #endif
1645
1646                 /* when autonegotiation advertisment is only 1000Mbps then we
1647                  * should disable SmartSpeed and enable Auto MasterSlave
1648                  * resolution as hardware default. */
1649                 if(hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1650                         /* Disable SmartSpeed */
1651                         if((ret_val = e1000_read_phy_reg(hw,
1652                                                          IGP01E1000_PHY_PORT_CONFIG,
1653                                                          &phy_data)))
1654                                 return ret_val;
1655                         phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1656                         if((ret_val = e1000_write_phy_reg(hw,
1657                                                           IGP01E1000_PHY_PORT_CONFIG,
1658                                                           phy_data)))
1659                                 return ret_val;
1660                         /* Set auto Master/Slave resolution process */
1661                         if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
1662                                                          &phy_data)))
1663                                 return ret_val;
1664                         phy_data &= ~CR_1000T_MS_ENABLE;
1665                         if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
1666                                                           phy_data)))
1667                                 return ret_val;
1668                 }
1669
1670                 if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
1671                                                  &phy_data)))
1672                         return ret_val;
1673
1674 #if 0
1675                 /* load defaults for future use */
1676                 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1677                                             ((phy_data & CR_1000T_MS_VALUE) ?
1678                                              e1000_ms_force_master :
1679                                              e1000_ms_force_slave) :
1680                                              e1000_ms_auto;
1681
1682                 switch (phy_ms_setting) {
1683                 case e1000_ms_force_master:
1684                         phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1685                         break;
1686                 case e1000_ms_force_slave:
1687                         phy_data |= CR_1000T_MS_ENABLE;
1688                         phy_data &= ~(CR_1000T_MS_VALUE);
1689                         break;
1690                 case e1000_ms_auto:
1691                         phy_data &= ~CR_1000T_MS_ENABLE;
1692                 default:
1693                         break;
1694                 }
1695 #endif
1696
1697                 if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
1698                                                   phy_data)))
1699                         return ret_val;
1700         } else {
1701                 /* Enable CRS on TX. This must be set for half-duplex operation. */
1702                 if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1703                                                  &phy_data)))
1704                         return ret_val;
1705
1706                 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1707
1708                 /* Options:
1709                  *   MDI/MDI-X = 0 (default)
1710                  *   0 - Auto for all speeds
1711                  *   1 - MDI mode
1712                  *   2 - MDI-X mode
1713                  *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1714                  */
1715 #if 0
1716                 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1717
1718                 switch (hw->mdix) {
1719                 case 1:
1720                         phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1721                         break;
1722                 case 2:
1723                         phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1724                         break;
1725                 case 3:
1726                         phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1727                         break;
1728                 case 0:
1729                 default:
1730 #endif
1731                         phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1732 #if 0
1733                         break;
1734                 }
1735 #endif
1736
1737                 /* Options:
1738                  *   disable_polarity_correction = 0 (default)
1739                  *       Automatic Correction for Reversed Cable Polarity
1740                  *   0 - Disabled
1741                  *   1 - Enabled
1742                  */
1743                 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1744                 if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1745                                                   phy_data)))
1746                         return ret_val;
1747
1748                 /* Force TX_CLK in the Extended PHY Specific Control Register
1749                  * to 25MHz clock.
1750                  */
1751                 if((ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1752                                                  &phy_data)))
1753                         return ret_val;
1754
1755                 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1756
1757 #ifdef LINUX_DRIVER
1758                 if (hw->phy_revision < M88E1011_I_REV_4) {
1759 #endif
1760                         /* Configure Master and Slave downshift values */
1761                         phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1762                                 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1763                         phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1764                                 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1765                         if((ret_val = e1000_write_phy_reg(hw,
1766                                                           M88E1000_EXT_PHY_SPEC_CTRL,
1767                                                           phy_data)))
1768                                 return ret_val;
1769                 }
1770         
1771                 /* SW Reset the PHY so all changes take effect */
1772                 if((ret_val = e1000_phy_reset(hw))) {
1773                         DEBUGOUT("Error Resetting the PHY\n");
1774                         return ret_val;
1775 #ifdef LINUX_DRIVER
1776                 }
1777 #endif
1778         }
1779         
1780         /* Options:
1781          *   autoneg = 1 (default)
1782          *      PHY will advertise value(s) parsed from
1783          *      autoneg_advertised and fc
1784          *   autoneg = 0
1785          *      PHY will be set to 10H, 10F, 100H, or 100F
1786          *      depending on value parsed from forced_speed_duplex.
1787          */
1788         
1789         /* Is autoneg enabled?  This is enabled by default or by software
1790          * override.  If so, call e1000_phy_setup_autoneg routine to parse the
1791          * autoneg_advertised and fc options. If autoneg is NOT enabled, then
1792          * the user should have provided a speed/duplex override.  If so, then
1793          * call e1000_phy_force_speed_duplex to parse and set this up.
1794          */
1795         /* Perform some bounds checking on the hw->autoneg_advertised
1796          * parameter.  If this variable is zero, then set it to the default.
1797          */
1798         hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1799         
1800         /* If autoneg_advertised is zero, we assume it was not defaulted
1801          * by the calling code so we set to advertise full capability.
1802          */
1803         if(hw->autoneg_advertised == 0)
1804                 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1805         
1806         DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1807         if((ret_val = e1000_phy_setup_autoneg(hw))) {
1808                 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1809                 return ret_val;
1810         }
1811         DEBUGOUT("Restarting Auto-Neg\n");
1812         
1813         /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1814          * the Auto Neg Restart bit in the PHY control register.
1815          */
1816         if((ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data)))
1817                 return ret_val;
1818
1819         phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1820         if((ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data)))
1821                 return ret_val;
1822
1823 #if 0   
1824         /* Does the user want to wait for Auto-Neg to complete here, or
1825          * check at a later time (for example, callback routine).
1826          */
1827         if(hw->wait_autoneg_complete) {
1828                 if((ret_val = e1000_wait_autoneg(hw))) {
1829                         DEBUGOUT("Error while waiting for autoneg to complete\n");
1830                         return ret_val;
1831                 }
1832         }
1833 #else
1834         /* If we do not wait for autonegotiation to complete I 
1835          * do not see a valid link status.
1836          */
1837         if((ret_val = e1000_wait_autoneg(hw))) {
1838                 DEBUGOUT("Error while waiting for autoneg to complete\n");
1839                 return ret_val;
1840         }
1841 #endif
1842         } /* !hw->phy_reset_disable */
1843         
1844         /* Check link status. Wait up to 100 microseconds for link to become
1845          * valid.
1846          */
1847         for(i = 0; i < 10; i++) {
1848                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
1849                         return ret_val;
1850                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
1851                         return ret_val;
1852
1853                 if(phy_data & MII_SR_LINK_STATUS) {
1854                         /* We have link, so we need to finish the config process:
1855                          *   1) Set up the MAC to the current PHY speed/duplex
1856                          *      if we are on 82543.  If we
1857                          *      are on newer silicon, we only need to configure
1858                          *      collision distance in the Transmit Control Register.
1859                          *   2) Set up flow control on the MAC to that established with
1860                          *      the link partner.
1861                          */
1862                         if(hw->mac_type >= e1000_82544) {
1863                                 e1000_config_collision_dist(hw);
1864                         } else {
1865                                 if((ret_val = e1000_config_mac_to_phy(hw))) {
1866                                         DEBUGOUT("Error configuring MAC to PHY settings\n");
1867                                         return ret_val;
1868                                 }
1869                         }
1870                         if((ret_val = e1000_config_fc_after_link_up(hw))) {
1871                                 DEBUGOUT("Error Configuring Flow Control\n");
1872                                 return ret_val;
1873                         }
1874 #if 0
1875                         if(hw->phy_type == e1000_phy_igp) {
1876                                 if((ret_val = e1000_config_dsp_after_link_change(hw, TRUE))) {
1877                                         DEBUGOUT("Error Configuring DSP after link up\n");
1878                                         return ret_val;
1879                                 }
1880                         }
1881 #endif
1882                         DEBUGOUT("Valid link established!!!\n");
1883                         return E1000_SUCCESS;
1884                 }
1885                 udelay(10);
1886         }
1887         
1888         DEBUGOUT("Unable to establish link!!!\n");
1889         return -E1000_ERR_NOLINK;
1890 }
1891
1892 /******************************************************************************
1893 * Configures PHY autoneg and flow control advertisement settings
1894 *
1895 * hw - Struct containing variables accessed by shared code
1896 ******************************************************************************/
1897 static int
1898 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1899 {
1900         int32_t ret_val;
1901         uint16_t mii_autoneg_adv_reg;
1902         uint16_t mii_1000t_ctrl_reg;
1903
1904         DEBUGFUNC("e1000_phy_setup_autoneg");
1905         
1906         /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1907         if((ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
1908                                          &mii_autoneg_adv_reg)))
1909                 return ret_val;
1910
1911         /* Read the MII 1000Base-T Control Register (Address 9). */
1912         if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg)))
1913                 return ret_val;
1914
1915         /* Need to parse both autoneg_advertised and fc and set up
1916          * the appropriate PHY registers.  First we will parse for
1917          * autoneg_advertised software override.  Since we can advertise
1918          * a plethora of combinations, we need to check each bit
1919          * individually.
1920          */
1921         
1922         /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1923          * Advertisement Register (Address 4) and the 1000 mb speed bits in
1924          * the  1000Base-T Control Register (Address 9).
1925          */
1926         mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
1927         mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1928
1929         DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
1930
1931         /* Do we want to advertise 10 Mb Half Duplex? */
1932         if(hw->autoneg_advertised & ADVERTISE_10_HALF) {
1933                 DEBUGOUT("Advertise 10mb Half duplex\n");
1934                 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1935         }
1936
1937         /* Do we want to advertise 10 Mb Full Duplex? */
1938         if(hw->autoneg_advertised & ADVERTISE_10_FULL) {
1939                 DEBUGOUT("Advertise 10mb Full duplex\n");
1940                 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1941         }
1942
1943         /* Do we want to advertise 100 Mb Half Duplex? */
1944         if(hw->autoneg_advertised & ADVERTISE_100_HALF) {
1945                 DEBUGOUT("Advertise 100mb Half duplex\n");
1946                 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1947         }
1948
1949         /* Do we want to advertise 100 Mb Full Duplex? */
1950         if(hw->autoneg_advertised & ADVERTISE_100_FULL) {
1951                 DEBUGOUT("Advertise 100mb Full duplex\n");
1952                 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1953         }
1954
1955         /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1956         if(hw->autoneg_advertised & ADVERTISE_1000_HALF) {
1957                 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
1958         }
1959
1960         /* Do we want to advertise 1000 Mb Full Duplex? */
1961         if(hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1962                 DEBUGOUT("Advertise 1000mb Full duplex\n");
1963                 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1964         }
1965
1966         /* Check for a software override of the flow control settings, and
1967          * setup the PHY advertisement registers accordingly.  If
1968          * auto-negotiation is enabled, then software will have to set the
1969          * "PAUSE" bits to the correct value in the Auto-Negotiation
1970          * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
1971          *
1972          * The possible values of the "fc" parameter are:
1973          *      0:  Flow control is completely disabled
1974          *      1:  Rx flow control is enabled (we can receive pause frames
1975          *          but not send pause frames).
1976          *      2:  Tx flow control is enabled (we can send pause frames
1977          *          but we do not support receiving pause frames).
1978          *      3:  Both Rx and TX flow control (symmetric) are enabled.
1979          *  other:  No software override.  The flow control configuration
1980          *          in the EEPROM is used.
1981          */
1982         switch (hw->fc) {
1983         case e1000_fc_none: /* 0 */
1984                 /* Flow control (RX & TX) is completely disabled by a
1985                  * software over-ride.
1986                  */
1987                 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1988                 break;
1989         case e1000_fc_rx_pause: /* 1 */
1990                 /* RX Flow control is enabled, and TX Flow control is
1991                  * disabled, by a software over-ride.
1992                  */
1993                 /* Since there really isn't a way to advertise that we are
1994                  * capable of RX Pause ONLY, we will advertise that we
1995                  * support both symmetric and asymmetric RX PAUSE.  Later
1996                  * (in e1000_config_fc_after_link_up) we will disable the
1997                  *hw's ability to send PAUSE frames.
1998                  */
1999                 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2000                 break;
2001         case e1000_fc_tx_pause: /* 2 */
2002                 /* TX Flow control is enabled, and RX Flow control is
2003                  * disabled, by a software over-ride.
2004                  */
2005                 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
2006                 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
2007                 break;
2008         case e1000_fc_full: /* 3 */
2009                 /* Flow control (both RX and TX) is enabled by a software
2010                  * over-ride.
2011                  */
2012                 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2013                 break;
2014         default:
2015                 DEBUGOUT("Flow control param set incorrectly\n");
2016                 return -E1000_ERR_CONFIG;
2017         }
2018
2019         if((ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV,
2020                                mii_autoneg_adv_reg)))
2021                 return ret_val;
2022
2023         DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
2024
2025         if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg)))
2026                 return ret_val;
2027
2028         return E1000_SUCCESS;
2029 }
2030
2031 /******************************************************************************
2032 * Sets the collision distance in the Transmit Control register
2033 *
2034 * hw - Struct containing variables accessed by shared code
2035 *
2036 * Link should have been established previously. Reads the speed and duplex
2037 * information from the Device Status register.
2038 ******************************************************************************/
2039 static void
2040 e1000_config_collision_dist(struct e1000_hw *hw)
2041 {
2042         uint32_t tctl;
2043
2044         tctl = E1000_READ_REG(hw, TCTL);
2045         
2046         tctl &= ~E1000_TCTL_COLD;
2047         tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
2048         
2049         E1000_WRITE_REG(hw, TCTL, tctl);
2050         E1000_WRITE_FLUSH(hw);
2051 }
2052
2053 /******************************************************************************
2054 * Sets MAC speed and duplex settings to reflect the those in the PHY
2055 *
2056 * hw - Struct containing variables accessed by shared code
2057 * mii_reg - data to write to the MII control register
2058 *
2059 * The contents of the PHY register containing the needed information need to
2060 * be passed in.
2061 ******************************************************************************/
2062 static int
2063 e1000_config_mac_to_phy(struct e1000_hw *hw)
2064 {
2065         uint32_t ctrl;
2066         int32_t ret_val;
2067         uint16_t phy_data;
2068
2069         DEBUGFUNC("e1000_config_mac_to_phy");
2070
2071         /* Read the Device Control Register and set the bits to Force Speed
2072          * and Duplex.
2073          */
2074         ctrl = E1000_READ_REG(hw, CTRL);
2075         ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2076         ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
2077
2078         /* Set up duplex in the Device Control and Transmit Control
2079          * registers depending on negotiated values.
2080          */
2081         if (hw->phy_type == e1000_phy_igp) {
2082                 if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
2083                                                  &phy_data)))
2084                         return ret_val;
2085
2086                 if(phy_data & IGP01E1000_PSSR_FULL_DUPLEX) ctrl |= E1000_CTRL_FD;
2087                 else ctrl &= ~E1000_CTRL_FD;
2088
2089                 e1000_config_collision_dist(hw);
2090
2091                 /* Set up speed in the Device Control register depending on
2092                  * negotiated values.
2093                  */
2094                 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
2095                    IGP01E1000_PSSR_SPEED_1000MBPS)
2096                         ctrl |= E1000_CTRL_SPD_1000;
2097                 else if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
2098                         IGP01E1000_PSSR_SPEED_100MBPS)
2099                         ctrl |= E1000_CTRL_SPD_100;
2100         } else {
2101                 if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
2102                                                  &phy_data)))
2103                         return ret_val;
2104                 
2105                 if(phy_data & M88E1000_PSSR_DPLX) ctrl |= E1000_CTRL_FD;
2106                 else ctrl &= ~E1000_CTRL_FD;
2107
2108                 e1000_config_collision_dist(hw);
2109
2110                 /* Set up speed in the Device Control register depending on
2111                  * negotiated values.
2112                  */
2113                 if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
2114                         ctrl |= E1000_CTRL_SPD_1000;
2115                 else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
2116                         ctrl |= E1000_CTRL_SPD_100;
2117         }
2118         /* Write the configured values back to the Device Control Reg. */
2119         E1000_WRITE_REG(hw, CTRL, ctrl);
2120         return E1000_SUCCESS;
2121 }
2122
2123 /******************************************************************************
2124  * Forces the MAC's flow control settings.
2125  * 
2126  * hw - Struct containing variables accessed by shared code
2127  *
2128  * Sets the TFCE and RFCE bits in the device control register to reflect
2129  * the adapter settings. TFCE and RFCE need to be explicitly set by
2130  * software when a Copper PHY is used because autonegotiation is managed
2131  * by the PHY rather than the MAC. Software must also configure these
2132  * bits when link is forced on a fiber connection.
2133  *****************************************************************************/
2134 static int
2135 e1000_force_mac_fc(struct e1000_hw *hw)
2136 {
2137         uint32_t ctrl;
2138         
2139         DEBUGFUNC("e1000_force_mac_fc");
2140         
2141         /* Get the current configuration of the Device Control Register */
2142         ctrl = E1000_READ_REG(hw, CTRL);
2143         
2144         /* Because we didn't get link via the internal auto-negotiation
2145          * mechanism (we either forced link or we got link via PHY
2146          * auto-neg), we have to manually enable/disable transmit an
2147          * receive flow control.
2148          *
2149          * The "Case" statement below enables/disable flow control
2150          * according to the "hw->fc" parameter.
2151          *
2152          * The possible values of the "fc" parameter are:
2153          *      0:  Flow control is completely disabled
2154          *      1:  Rx flow control is enabled (we can receive pause
2155          *          frames but not send pause frames).
2156          *      2:  Tx flow control is enabled (we can send pause frames
2157          *          frames but we do not receive pause frames).
2158          *      3:  Both Rx and TX flow control (symmetric) is enabled.
2159          *  other:  No other values should be possible at this point.
2160          */
2161         
2162         switch (hw->fc) {
2163         case e1000_fc_none:
2164                 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
2165                 break;
2166         case e1000_fc_rx_pause:
2167                 ctrl &= (~E1000_CTRL_TFCE);
2168                 ctrl |= E1000_CTRL_RFCE;
2169                 break;
2170         case e1000_fc_tx_pause:
2171                 ctrl &= (~E1000_CTRL_RFCE);
2172                 ctrl |= E1000_CTRL_TFCE;
2173                 break;
2174         case e1000_fc_full:
2175                 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
2176                 break;
2177         default:
2178                 DEBUGOUT("Flow control param set incorrectly\n");
2179                 return -E1000_ERR_CONFIG;
2180         }
2181         
2182         /* Disable TX Flow Control for 82542 (rev 2.0) */
2183         if(hw->mac_type == e1000_82542_rev2_0)
2184                 ctrl &= (~E1000_CTRL_TFCE);
2185         
2186         E1000_WRITE_REG(hw, CTRL, ctrl);
2187         return E1000_SUCCESS;
2188 }
2189
2190 /******************************************************************************
2191  * Configures flow control settings after link is established
2192  * 
2193  * hw - Struct containing variables accessed by shared code
2194  *
2195  * Should be called immediately after a valid link has been established.
2196  * Forces MAC flow control settings if link was forced. When in MII/GMII mode
2197  * and autonegotiation is enabled, the MAC flow control settings will be set
2198  * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
2199  * and RFCE bits will be automaticaly set to the negotiated flow control mode.
2200  *****************************************************************************/
2201 static int
2202 e1000_config_fc_after_link_up(struct e1000_hw *hw)
2203 {
2204         int32_t ret_val;
2205         uint16_t mii_status_reg;
2206         uint16_t mii_nway_adv_reg;
2207         uint16_t mii_nway_lp_ability_reg;
2208         uint16_t speed;
2209         uint16_t duplex;
2210         
2211         DEBUGFUNC("e1000_config_fc_after_link_up");
2212         
2213         /* Check for the case where we have fiber media and auto-neg failed
2214          * so we had to force link.  In this case, we need to force the
2215          * configuration of the MAC to match the "fc" parameter.
2216          */
2217         if(((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
2218            ((hw->media_type == e1000_media_type_internal_serdes) && (hw->autoneg_failed))) { 
2219                 if((ret_val = e1000_force_mac_fc(hw))) {
2220                         DEBUGOUT("Error forcing flow control settings\n");
2221                         return ret_val;
2222                 }
2223         }
2224         
2225         /* Check for the case where we have copper media and auto-neg is
2226          * enabled.  In this case, we need to check and see if Auto-Neg
2227          * has completed, and if so, how the PHY and link partner has
2228          * flow control configured.
2229          */
2230         if(hw->media_type == e1000_media_type_copper) {
2231                 /* Read the MII Status Register and check to see if AutoNeg
2232                  * has completed.  We read this twice because this reg has
2233                  * some "sticky" (latched) bits.
2234                  */
2235                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
2236                         return ret_val;
2237                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
2238                         return ret_val;
2239                 
2240                 if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
2241                         /* The AutoNeg process has completed, so we now need to
2242                          * read both the Auto Negotiation Advertisement Register
2243                          * (Address 4) and the Auto_Negotiation Base Page Ability
2244                          * Register (Address 5) to determine how flow control was
2245                          * negotiated.
2246                          */
2247                         if((ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
2248                                                          &mii_nway_adv_reg)))
2249                                 return ret_val;
2250                         if((ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2251                                                          &mii_nway_lp_ability_reg)))
2252                                 return ret_val;
2253
2254                         /* Two bits in the Auto Negotiation Advertisement Register
2255                          * (Address 4) and two bits in the Auto Negotiation Base
2256                          * Page Ability Register (Address 5) determine flow control
2257                          * for both the PHY and the link partner.  The following
2258                          * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
2259                          * 1999, describes these PAUSE resolution bits and how flow
2260                          * control is determined based upon these settings.
2261                          * NOTE:  DC = Don't Care
2262                          *
2263                          *   LOCAL DEVICE  |   LINK PARTNER
2264                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
2265                          *-------|---------|-------|---------|--------------------
2266                          *   0   |    0    |  DC   |   DC    | e1000_fc_none
2267                          *   0   |    1    |   0   |   DC    | e1000_fc_none
2268                          *   0   |    1    |   1   |    0    | e1000_fc_none
2269                          *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
2270                          *   1   |    0    |   0   |   DC    | e1000_fc_none
2271                          *   1   |   DC    |   1   |   DC    | e1000_fc_full
2272                          *   1   |    1    |   0   |    0    | e1000_fc_none
2273                          *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
2274                          *
2275                          */
2276                         /* Are both PAUSE bits set to 1?  If so, this implies
2277                          * Symmetric Flow Control is enabled at both ends.  The
2278                          * ASM_DIR bits are irrelevant per the spec.
2279                          *
2280                          * For Symmetric Flow Control:
2281                          *
2282                          *   LOCAL DEVICE  |   LINK PARTNER
2283                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2284                          *-------|---------|-------|---------|--------------------
2285                          *   1   |   DC    |   1   |   DC    | e1000_fc_full
2286                          *
2287                          */
2288                         if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2289                                 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
2290                                 /* Now we need to check if the user selected RX ONLY
2291                                  * of pause frames.  In this case, we had to advertise
2292                                  * FULL flow control because we could not advertise RX
2293                                  * ONLY. Hence, we must now check to see if we need to
2294                                  * turn OFF  the TRANSMISSION of PAUSE frames.
2295                                  */
2296 #if 0
2297                                 if(hw->original_fc == e1000_fc_full) {
2298                                         hw->fc = e1000_fc_full;
2299 #else
2300                                 if(hw->fc == e1000_fc_full) {
2301 #endif
2302                                         DEBUGOUT("Flow Control = FULL.\r\n");
2303                                 } else {
2304                                         hw->fc = e1000_fc_rx_pause;
2305                                         DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
2306                                 }
2307                         }
2308                         /* For receiving PAUSE frames ONLY.
2309                          *
2310                          *   LOCAL DEVICE  |   LINK PARTNER
2311                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2312                          *-------|---------|-------|---------|--------------------
2313                          *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
2314                          *
2315                          */
2316                         else if(!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2317                                 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2318                                 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2319                                 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2320                                 hw->fc = e1000_fc_tx_pause;
2321                                 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n");
2322                         }
2323                         /* For transmitting PAUSE frames ONLY.
2324                          *
2325                          *   LOCAL DEVICE  |   LINK PARTNER
2326                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2327                          *-------|---------|-------|---------|--------------------
2328                          *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
2329                          *
2330                          */
2331                         else if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2332                                 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2333                                 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2334                                 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2335                                 hw->fc = e1000_fc_rx_pause;
2336                                 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
2337                         }
2338                         /* Per the IEEE spec, at this point flow control should be
2339                          * disabled.  However, we want to consider that we could
2340                          * be connected to a legacy switch that doesn't advertise
2341                          * desired flow control, but can be forced on the link
2342                          * partner.  So if we advertised no flow control, that is
2343                          * what we will resolve to.  If we advertised some kind of
2344                          * receive capability (Rx Pause Only or Full Flow Control)
2345                          * and the link partner advertised none, we will configure
2346                          * ourselves to enable Rx Flow Control only.  We can do
2347                          * this safely for two reasons:  If the link partner really
2348                          * didn't want flow control enabled, and we enable Rx, no
2349                          * harm done since we won't be receiving any PAUSE frames
2350                          * anyway.  If the intent on the link partner was to have
2351                          * flow control enabled, then by us enabling RX only, we
2352                          * can at least receive pause frames and process them.
2353                          * This is a good idea because in most cases, since we are
2354                          * predominantly a server NIC, more times than not we will
2355                          * be asked to delay transmission of packets than asking
2356                          * our link partner to pause transmission of frames.
2357                          */
2358 #if 0
2359                         else if(hw->original_fc == e1000_fc_none ||
2360                                 hw->original_fc == e1000_fc_tx_pause) {
2361 #else
2362                         else if(hw->fc == e1000_fc_none)
2363                                 DEBUGOUT("Flow Control = NONE.\r\n");
2364                         else if(hw->fc == e1000_fc_tx_pause) {
2365 #endif
2366                                 hw->fc = e1000_fc_none;
2367                                 DEBUGOUT("Flow Control = NONE.\r\n");
2368                         } else {
2369                                 hw->fc = e1000_fc_rx_pause;
2370                                 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
2371                         }
2372                         
2373                         /* Now we need to do one last check...  If we auto-
2374                          * negotiated to HALF DUPLEX, flow control should not be
2375                          * enabled per IEEE 802.3 spec.
2376                          */
2377                         e1000_get_speed_and_duplex(hw, &speed, &duplex);
2378                         
2379                         if(duplex == HALF_DUPLEX)
2380                                 hw->fc = e1000_fc_none;
2381                         
2382                         /* Now we call a subroutine to actually force the MAC
2383                          * controller to use the correct flow control settings.
2384                          */
2385                         if((ret_val = e1000_force_mac_fc(hw))) {
2386                                 DEBUGOUT("Error forcing flow control settings\n");
2387                                 return ret_val;
2388                         }
2389                 } else {
2390                         DEBUGOUT("Copper PHY and Auto Neg has not completed.\r\n");
2391                 }
2392         }
2393         return E1000_SUCCESS;
2394 }
2395
2396 /******************************************************************************
2397  * Checks to see if the link status of the hardware has changed.
2398  *
2399  * hw - Struct containing variables accessed by shared code
2400  *
2401  * Called by any function that needs to check the link status of the adapter.
2402  *****************************************************************************/
2403 static int
2404 e1000_check_for_link(struct e1000_hw *hw)
2405 {
2406         uint32_t rxcw;
2407         uint32_t ctrl;
2408         uint32_t status;
2409         uint32_t rctl;
2410         uint32_t signal = 0;
2411         int32_t ret_val;
2412         uint16_t phy_data;
2413         uint16_t lp_capability;
2414         
2415         DEBUGFUNC("e1000_check_for_link");
2416         
2417         /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be 
2418          * set when the optics detect a signal. On older adapters, it will be 
2419          * cleared when there is a signal.  This applies to fiber media only.
2420          */
2421         if(hw->media_type == e1000_media_type_fiber)
2422                 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
2423
2424         ctrl = E1000_READ_REG(hw, CTRL);
2425         status = E1000_READ_REG(hw, STATUS);
2426         rxcw = E1000_READ_REG(hw, RXCW);
2427         
2428         /* If we have a copper PHY then we only want to go out to the PHY
2429          * registers to see if Auto-Neg has completed and/or if our link
2430          * status has changed.  The get_link_status flag will be set if we
2431          * receive a Link Status Change interrupt or we have Rx Sequence
2432          * Errors.
2433          */
2434 #if 0
2435         if((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
2436 #else
2437         if(hw->media_type == e1000_media_type_copper) {
2438 #endif
2439                 /* First we want to see if the MII Status Register reports
2440                  * link.  If so, then we want to get the current speed/duplex
2441                  * of the PHY.
2442                  * Read the register twice since the link bit is sticky.
2443                  */
2444                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2445                         return ret_val;
2446                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2447                         return ret_val;
2448                 
2449                 if(phy_data & MII_SR_LINK_STATUS) {
2450 #if 0
2451                         hw->get_link_status = FALSE;
2452 #endif
2453                 } else {
2454                         /* No link detected */
2455                         return -E1000_ERR_NOLINK;
2456                 }
2457
2458                 /* We have a M88E1000 PHY and Auto-Neg is enabled.  If we
2459                  * have Si on board that is 82544 or newer, Auto
2460                  * Speed Detection takes care of MAC speed/duplex
2461                  * configuration.  So we only need to configure Collision
2462                  * Distance in the MAC.  Otherwise, we need to force
2463                  * speed/duplex on the MAC to the current PHY speed/duplex
2464                  * settings.
2465                  */
2466                 if(hw->mac_type >= e1000_82544)
2467                         e1000_config_collision_dist(hw);
2468                 else {
2469                         if((ret_val = e1000_config_mac_to_phy(hw))) {
2470                                 DEBUGOUT("Error configuring MAC to PHY settings\n");
2471                                 return ret_val;
2472                         }
2473                 }
2474                 
2475                 /* Configure Flow Control now that Auto-Neg has completed. First, we 
2476                  * need to restore the desired flow control settings because we may
2477                  * have had to re-autoneg with a different link partner.
2478                  */
2479                 if((ret_val = e1000_config_fc_after_link_up(hw))) {
2480                         DEBUGOUT("Error configuring flow control\n");
2481                         return ret_val;
2482                 }
2483                 
2484                 /* At this point we know that we are on copper and we have
2485                  * auto-negotiated link.  These are conditions for checking the link
2486                  * parter capability register.  We use the link partner capability to
2487                  * determine if TBI Compatibility needs to be turned on or off.  If
2488                  * the link partner advertises any speed in addition to Gigabit, then
2489                  * we assume that they are GMII-based, and TBI compatibility is not
2490                  * needed. If no other speeds are advertised, we assume the link
2491                  * partner is TBI-based, and we turn on TBI Compatibility.
2492                  */
2493                 if(hw->tbi_compatibility_en) {
2494                         if((ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2495                                                          &lp_capability)))
2496                                 return ret_val;
2497                         if(lp_capability & (NWAY_LPAR_10T_HD_CAPS |
2498                                 NWAY_LPAR_10T_FD_CAPS |
2499                                 NWAY_LPAR_100TX_HD_CAPS |
2500                                 NWAY_LPAR_100TX_FD_CAPS |
2501                                 NWAY_LPAR_100T4_CAPS)) {
2502                                 /* If our link partner advertises anything in addition to 
2503                                  * gigabit, we do not need to enable TBI compatibility.
2504                                  */
2505                                 if(hw->tbi_compatibility_on) {
2506                                         /* If we previously were in the mode, turn it off. */
2507                                         rctl = E1000_READ_REG(hw, RCTL);
2508                                         rctl &= ~E1000_RCTL_SBP;
2509                                         E1000_WRITE_REG(hw, RCTL, rctl);
2510                                         hw->tbi_compatibility_on = FALSE;
2511                                 }
2512                         } else {
2513                                 /* If TBI compatibility is was previously off, turn it on. For
2514                                  * compatibility with a TBI link partner, we will store bad
2515                                  * packets. Some frames have an additional byte on the end and
2516                                  * will look like CRC errors to to the hardware.
2517                                  */
2518                                 if(!hw->tbi_compatibility_on) {
2519                                         hw->tbi_compatibility_on = TRUE;
2520                                         rctl = E1000_READ_REG(hw, RCTL);
2521                                         rctl |= E1000_RCTL_SBP;
2522                                         E1000_WRITE_REG(hw, RCTL, rctl);
2523                                 }
2524                         }
2525                 }
2526         }
2527         /* If we don't have link (auto-negotiation failed or link partner cannot
2528          * auto-negotiate), the cable is plugged in (we have signal), and our
2529          * link partner is not trying to auto-negotiate with us (we are receiving
2530          * idles or data), we need to force link up. We also need to give
2531          * auto-negotiation time to complete, in case the cable was just plugged
2532          * in. The autoneg_failed flag does this.
2533          */
2534         else if((((hw->media_type == e1000_media_type_fiber) &&
2535                 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
2536                 (hw->media_type == e1000_media_type_internal_serdes)) &&
2537                 (!(status & E1000_STATUS_LU)) &&
2538                 (!(rxcw & E1000_RXCW_C))) {
2539                 if(hw->autoneg_failed == 0) {
2540                         hw->autoneg_failed = 1;
2541                         return 0;
2542                 }
2543                 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
2544                 
2545                 /* Disable auto-negotiation in the TXCW register */
2546                 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
2547                 
2548                 /* Force link-up and also force full-duplex. */
2549                 ctrl = E1000_READ_REG(hw, CTRL);
2550                 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
2551                 E1000_WRITE_REG(hw, CTRL, ctrl);
2552                 
2553                 /* Configure Flow Control after forcing link up. */
2554                 if((ret_val = e1000_config_fc_after_link_up(hw))) {
2555                         DEBUGOUT("Error configuring flow control\n");
2556                         return ret_val;
2557                 }
2558         }
2559         /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
2560          * auto-negotiation in the TXCW register and disable forced link in the
2561          * Device Control register in an attempt to auto-negotiate with our link
2562          * partner.
2563          */
2564         else if(((hw->media_type == e1000_media_type_fiber)  ||
2565                  (hw->media_type == e1000_media_type_internal_serdes)) &&
2566                 (ctrl & E1000_CTRL_SLU) &&
2567                 (rxcw & E1000_RXCW_C)) {
2568                 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
2569                 E1000_WRITE_REG(hw, TXCW, hw->txcw);
2570                 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
2571         }
2572 #if 0
2573         /* If we force link for non-auto-negotiation switch, check link status
2574          * based on MAC synchronization for internal serdes media type.
2575          */
2576         else if((hw->media_type == e1000_media_type_internal_serdes) &&
2577                         !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
2578                 /* SYNCH bit and IV bit are sticky. */
2579                 udelay(10);
2580                 if(E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
2581                         if(!(rxcw & E1000_RXCW_IV)) {
2582                                 hw->serdes_link_down = FALSE;
2583                                 DEBUGOUT("SERDES: Link is up.\n");
2584                         }
2585                 } else {
2586                         hw->serdes_link_down = TRUE;
2587                         DEBUGOUT("SERDES: Link is down.\n");
2588                 }
2589         }
2590 #endif
2591         return E1000_SUCCESS;
2592 }
2593
2594 /******************************************************************************
2595  * Detects the current speed and duplex settings of the hardware.
2596  *
2597  * hw - Struct containing variables accessed by shared code
2598  * speed - Speed of the connection
2599  * duplex - Duplex setting of the connection
2600  *****************************************************************************/
2601 static void 
2602 e1000_get_speed_and_duplex(struct e1000_hw *hw,
2603                            uint16_t *speed,
2604                            uint16_t *duplex)
2605 {
2606         uint32_t status;
2607         
2608         DEBUGFUNC("e1000_get_speed_and_duplex");
2609         
2610         if(hw->mac_type >= e1000_82543) {
2611                 status = E1000_READ_REG(hw, STATUS);
2612                 if(status & E1000_STATUS_SPEED_1000) {
2613                         *speed = SPEED_1000;
2614                         DEBUGOUT("1000 Mbs, ");
2615                 } else if(status & E1000_STATUS_SPEED_100) {
2616                         *speed = SPEED_100;
2617                         DEBUGOUT("100 Mbs, ");
2618                 } else {
2619                         *speed = SPEED_10;
2620                         DEBUGOUT("10 Mbs, ");
2621                 }
2622                 
2623                 if(status & E1000_STATUS_FD) {
2624                         *duplex = FULL_DUPLEX;
2625                         DEBUGOUT("Full Duplex\r\n");
2626                 } else {
2627                         *duplex = HALF_DUPLEX;
2628                         DEBUGOUT(" Half Duplex\r\n");
2629                 }
2630         } else {
2631                 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
2632                 *speed = SPEED_1000;
2633                 *duplex = FULL_DUPLEX;
2634         }
2635 }
2636
2637 /******************************************************************************
2638 * Blocks until autoneg completes or times out (~4.5 seconds)
2639 *
2640 * hw - Struct containing variables accessed by shared code
2641 ******************************************************************************/
2642 static int
2643 e1000_wait_autoneg(struct e1000_hw *hw)
2644 {
2645         int32_t ret_val;
2646         uint16_t i;
2647         uint16_t phy_data;
2648         
2649         DEBUGFUNC("e1000_wait_autoneg");
2650         DEBUGOUT("Waiting for Auto-Neg to complete.\n");
2651         
2652         /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2653         for(i = PHY_AUTO_NEG_TIME; i > 0; i--) {
2654                 /* Read the MII Status Register and wait for Auto-Neg
2655                  * Complete bit to be set.
2656                  */
2657                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2658                         return ret_val;
2659                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2660                         return ret_val;
2661                 if(phy_data & MII_SR_AUTONEG_COMPLETE) {
2662                         DEBUGOUT("Auto-Neg complete.\n");
2663                         return E1000_SUCCESS;
2664                 }
2665                 mdelay(100);
2666         }
2667         DEBUGOUT("Auto-Neg timedout.\n");
2668         return -E1000_ERR_TIMEOUT;
2669 }
2670
2671 /******************************************************************************
2672 * Raises the Management Data Clock
2673 *
2674 * hw - Struct containing variables accessed by shared code
2675 * ctrl - Device control register's current value
2676 ******************************************************************************/
2677 static void
2678 e1000_raise_mdi_clk(struct e1000_hw *hw,
2679                     uint32_t *ctrl)
2680 {
2681         /* Raise the clock input to the Management Data Clock (by setting the MDC
2682          * bit), and then delay 10 microseconds.
2683          */
2684         E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
2685         E1000_WRITE_FLUSH(hw);
2686         udelay(10);
2687 }
2688
2689 /******************************************************************************
2690 * Lowers the Management Data Clock
2691 *
2692 * hw - Struct containing variables accessed by shared code
2693 * ctrl - Device control register's current value
2694 ******************************************************************************/
2695 static void
2696 e1000_lower_mdi_clk(struct e1000_hw *hw,
2697                     uint32_t *ctrl)
2698 {
2699         /* Lower the clock input to the Management Data Clock (by clearing the MDC
2700          * bit), and then delay 10 microseconds.
2701          */
2702         E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
2703         E1000_WRITE_FLUSH(hw);
2704         udelay(10);
2705 }
2706
2707 /******************************************************************************
2708 * Shifts data bits out to the PHY
2709 *
2710 * hw - Struct containing variables accessed by shared code
2711 * data - Data to send out to the PHY
2712 * count - Number of bits to shift out
2713 *
2714 * Bits are shifted out in MSB to LSB order.
2715 ******************************************************************************/
2716 static void
2717 e1000_shift_out_mdi_bits(struct e1000_hw *hw,
2718                          uint32_t data,
2719                          uint16_t count)
2720 {
2721         uint32_t ctrl;
2722         uint32_t mask;
2723
2724         /* We need to shift "count" number of bits out to the PHY. So, the value
2725          * in the "data" parameter will be shifted out to the PHY one bit at a 
2726          * time. In order to do this, "data" must be broken down into bits.
2727          */
2728         mask = 0x01;
2729         mask <<= (count - 1);
2730         
2731         ctrl = E1000_READ_REG(hw, CTRL);
2732         
2733         /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
2734         ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
2735         
2736         while(mask) {
2737                 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
2738                  * then raising and lowering the Management Data Clock. A "0" is
2739                  * shifted out to the PHY by setting the MDIO bit to "0" and then
2740                  * raising and lowering the clock.
2741                  */
2742                 if(data & mask) ctrl |= E1000_CTRL_MDIO;
2743                 else ctrl &= ~E1000_CTRL_MDIO;
2744                 
2745                 E1000_WRITE_REG(hw, CTRL, ctrl);
2746                 E1000_WRITE_FLUSH(hw);
2747                 
2748                 udelay(10);
2749
2750                 e1000_raise_mdi_clk(hw, &ctrl);
2751                 e1000_lower_mdi_clk(hw, &ctrl);
2752
2753                 mask = mask >> 1;
2754         }
2755 }
2756
2757 /******************************************************************************
2758 * Shifts data bits in from the PHY
2759 *
2760 * hw - Struct containing variables accessed by shared code
2761 *
2762 * Bits are shifted in in MSB to LSB order. 
2763 ******************************************************************************/
2764 static uint16_t
2765 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
2766 {
2767         uint32_t ctrl;
2768         uint16_t data = 0;
2769         uint8_t i;
2770
2771         /* In order to read a register from the PHY, we need to shift in a total
2772          * of 18 bits from the PHY. The first two bit (turnaround) times are used
2773          * to avoid contention on the MDIO pin when a read operation is performed.
2774          * These two bits are ignored by us and thrown away. Bits are "shifted in"
2775          * by raising the input to the Management Data Clock (setting the MDC bit),
2776          * and then reading the value of the MDIO bit.
2777          */ 
2778         ctrl = E1000_READ_REG(hw, CTRL);
2779         
2780         /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
2781         ctrl &= ~E1000_CTRL_MDIO_DIR;
2782         ctrl &= ~E1000_CTRL_MDIO;
2783         
2784         E1000_WRITE_REG(hw, CTRL, ctrl);
2785         E1000_WRITE_FLUSH(hw);
2786         
2787         /* Raise and Lower the clock before reading in the data. This accounts for
2788          * the turnaround bits. The first clock occurred when we clocked out the
2789          * last bit of the Register Address.
2790          */
2791         e1000_raise_mdi_clk(hw, &ctrl);
2792         e1000_lower_mdi_clk(hw, &ctrl);
2793         
2794         for(data = 0, i = 0; i < 16; i++) {
2795                 data = data << 1;
2796                 e1000_raise_mdi_clk(hw, &ctrl);
2797                 ctrl = E1000_READ_REG(hw, CTRL);
2798                 /* Check to see if we shifted in a "1". */
2799                 if(ctrl & E1000_CTRL_MDIO) data |= 1;
2800                 e1000_lower_mdi_clk(hw, &ctrl);
2801         }
2802         
2803         e1000_raise_mdi_clk(hw, &ctrl);
2804         e1000_lower_mdi_clk(hw, &ctrl);
2805         
2806         return data;
2807 }
2808
2809 /*****************************************************************************
2810 * Reads the value from a PHY register, if the value is on a specific non zero
2811 * page, sets the page first.
2812 *
2813 * hw - Struct containing variables accessed by shared code
2814 * reg_addr - address of the PHY register to read
2815 ******************************************************************************/
2816 static int
2817 e1000_read_phy_reg(struct e1000_hw *hw,
2818                    uint32_t reg_addr,
2819                    uint16_t *phy_data)
2820 {
2821         uint32_t ret_val;
2822
2823         DEBUGFUNC("e1000_read_phy_reg");
2824
2825         if(hw->phy_type == e1000_phy_igp &&
2826            (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2827                 if((ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2828                                                      (uint16_t)reg_addr)))
2829                         return ret_val;
2830         }
2831
2832         ret_val = e1000_read_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr,
2833                                         phy_data);
2834
2835         return ret_val;
2836 }
2837
2838 static int
2839 e1000_read_phy_reg_ex(struct e1000_hw *hw,
2840                       uint32_t reg_addr,
2841                       uint16_t *phy_data)
2842 {
2843         uint32_t i;
2844         uint32_t mdic = 0;
2845         const uint32_t phy_addr = 1;
2846
2847         DEBUGFUNC("e1000_read_phy_reg_ex");
2848         
2849         if(reg_addr > MAX_PHY_REG_ADDRESS) {
2850                 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2851                 return -E1000_ERR_PARAM;
2852         }
2853         
2854         if(hw->mac_type > e1000_82543) {
2855                 /* Set up Op-code, Phy Address, and register address in the MDI
2856                  * Control register.  The MAC will take care of interfacing with the
2857                  * PHY to retrieve the desired data.
2858                  */
2859                 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
2860                         (phy_addr << E1000_MDIC_PHY_SHIFT) | 
2861                         (E1000_MDIC_OP_READ));
2862                 
2863                 E1000_WRITE_REG(hw, MDIC, mdic);
2864
2865                 /* Poll the ready bit to see if the MDI read completed */
2866                 for(i = 0; i < 64; i++) {
2867                         udelay(50);
2868                         mdic = E1000_READ_REG(hw, MDIC);
2869                         if(mdic & E1000_MDIC_READY) break;
2870                 }
2871                 if(!(mdic & E1000_MDIC_READY)) {
2872                         DEBUGOUT("MDI Read did not complete\n");
2873                         return -E1000_ERR_PHY;
2874                 }
2875                 if(mdic & E1000_MDIC_ERROR) {
2876                         DEBUGOUT("MDI Error\n");
2877                         return -E1000_ERR_PHY;
2878                 }
2879                 *phy_data = (uint16_t) mdic;
2880         } else {
2881                 /* We must first send a preamble through the MDIO pin to signal the
2882                  * beginning of an MII instruction.  This is done by sending 32
2883                  * consecutive "1" bits.
2884                  */
2885                 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2886                 
2887                 /* Now combine the next few fields that are required for a read
2888                  * operation.  We use this method instead of calling the
2889                  * e1000_shift_out_mdi_bits routine five different times. The format of
2890                  * a MII read instruction consists of a shift out of 14 bits and is
2891                  * defined as follows:
2892                  *    <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
2893                  * followed by a shift in of 18 bits.  This first two bits shifted in
2894                  * are TurnAround bits used to avoid contention on the MDIO pin when a
2895                  * READ operation is performed.  These two bits are thrown away
2896                  * followed by a shift in of 16 bits which contains the desired data.
2897                  */
2898                 mdic = ((reg_addr) | (phy_addr << 5) | 
2899                         (PHY_OP_READ << 10) | (PHY_SOF << 12));
2900                 
2901                 e1000_shift_out_mdi_bits(hw, mdic, 14);
2902                 
2903                 /* Now that we've shifted out the read command to the MII, we need to
2904                  * "shift in" the 16-bit value (18 total bits) of the requested PHY
2905                  * register address.
2906                  */
2907                 *phy_data = e1000_shift_in_mdi_bits(hw);
2908         }
2909         return E1000_SUCCESS;
2910 }
2911
2912 /******************************************************************************
2913 * Writes a value to a PHY register
2914 *
2915 * hw - Struct containing variables accessed by shared code
2916 * reg_addr - address of the PHY register to write
2917 * data - data to write to the PHY
2918 ******************************************************************************/
2919 static int 
2920 e1000_write_phy_reg(struct e1000_hw *hw,
2921                     uint32_t reg_addr,
2922                     uint16_t phy_data)
2923 {
2924         uint32_t ret_val;
2925
2926         DEBUGFUNC("e1000_write_phy_reg");
2927
2928         if(hw->phy_type == e1000_phy_igp &&
2929            (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2930                 if((ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2931                                                      (uint16_t)reg_addr)))
2932                         return ret_val;
2933         }
2934
2935         ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr,
2936                                          phy_data);
2937
2938         return ret_val;
2939 }
2940
2941 static int
2942 e1000_write_phy_reg_ex(struct e1000_hw *hw,
2943                        uint32_t reg_addr,
2944                        uint16_t phy_data)
2945 {
2946         uint32_t i;
2947         uint32_t mdic = 0;
2948         const uint32_t phy_addr = 1;
2949         
2950         DEBUGFUNC("e1000_write_phy_reg_ex");
2951         
2952         if(reg_addr > MAX_PHY_REG_ADDRESS) {
2953                 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2954                 return -E1000_ERR_PARAM;
2955         }
2956         
2957         if(hw->mac_type > e1000_82543) {
2958                 /* Set up Op-code, Phy Address, register address, and data intended
2959                  * for the PHY register in the MDI Control register.  The MAC will take
2960                  * care of interfacing with the PHY to send the desired data.
2961                  */
2962                 mdic = (((uint32_t) phy_data) |
2963                         (reg_addr << E1000_MDIC_REG_SHIFT) |
2964                         (phy_addr << E1000_MDIC_PHY_SHIFT) | 
2965                         (E1000_MDIC_OP_WRITE));
2966                 
2967                 E1000_WRITE_REG(hw, MDIC, mdic);
2968                 
2969                 /* Poll the ready bit to see if the MDI read completed */
2970                 for(i = 0; i < 640; i++) {
2971                         udelay(5);
2972                         mdic = E1000_READ_REG(hw, MDIC);
2973                         if(mdic & E1000_MDIC_READY) break;
2974                 }
2975                 if(!(mdic & E1000_MDIC_READY)) {
2976                         DEBUGOUT("MDI Write did not complete\n");
2977                         return -E1000_ERR_PHY;
2978                 }
2979         } else {
2980                 /* We'll need to use the SW defined pins to shift the write command
2981                  * out to the PHY. We first send a preamble to the PHY to signal the
2982                  * beginning of the MII instruction.  This is done by sending 32 
2983                  * consecutive "1" bits.
2984                  */
2985                 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2986                 
2987                 /* Now combine the remaining required fields that will indicate a 
2988                  * write operation. We use this method instead of calling the
2989                  * e1000_shift_out_mdi_bits routine for each field in the command. The
2990                  * format of a MII write instruction is as follows:
2991                  * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
2992                  */
2993                 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
2994                         (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
2995                 mdic <<= 16;
2996                 mdic |= (uint32_t) phy_data;
2997                 
2998                 e1000_shift_out_mdi_bits(hw, mdic, 32);
2999         }
3000
3001         return E1000_SUCCESS;
3002 }
3003
3004 /******************************************************************************
3005 * Returns the PHY to the power-on reset state
3006 *
3007 * hw - Struct containing variables accessed by shared code
3008 ******************************************************************************/
3009 static void
3010 e1000_phy_hw_reset(struct e1000_hw *hw)
3011 {
3012         uint32_t ctrl, ctrl_ext;
3013
3014         DEBUGFUNC("e1000_phy_hw_reset");
3015         
3016         DEBUGOUT("Resetting Phy...\n");
3017         
3018         if(hw->mac_type > e1000_82543) {
3019                 /* Read the device control register and assert the E1000_CTRL_PHY_RST
3020                  * bit. Then, take it out of reset.
3021                  */
3022                 ctrl = E1000_READ_REG(hw, CTRL);
3023                 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
3024                 E1000_WRITE_FLUSH(hw);
3025                 mdelay(10);
3026                 E1000_WRITE_REG(hw, CTRL, ctrl);
3027                 E1000_WRITE_FLUSH(hw);
3028         } else {
3029                 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
3030                  * bit to put the PHY into reset. Then, take it out of reset.
3031                  */
3032                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
3033                 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
3034                 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
3035                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3036                 E1000_WRITE_FLUSH(hw);
3037                 mdelay(10);
3038                 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
3039                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3040                 E1000_WRITE_FLUSH(hw);
3041         }
3042         udelay(150);
3043 }
3044
3045 /******************************************************************************
3046 * Resets the PHY
3047 *
3048 * hw - Struct containing variables accessed by shared code
3049 *
3050 * Sets bit 15 of the MII Control regiser
3051 ******************************************************************************/
3052 static int 
3053 e1000_phy_reset(struct e1000_hw *hw)
3054 {
3055         int32_t ret_val;
3056         uint16_t phy_data;
3057
3058         DEBUGFUNC("e1000_phy_reset");
3059
3060         if(hw->mac_type != e1000_82541_rev_2) {
3061                 if((ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data)))
3062                         return ret_val;
3063                 
3064                 phy_data |= MII_CR_RESET;
3065                 if((ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data)))
3066                         return ret_val;
3067                 
3068                 udelay(1);
3069         } else e1000_phy_hw_reset(hw);
3070
3071         if(hw->phy_type == e1000_phy_igp)
3072                 e1000_phy_init_script(hw);
3073
3074         return E1000_SUCCESS;
3075 }
3076
3077 /******************************************************************************
3078 * Probes the expected PHY address for known PHY IDs
3079 *
3080 * hw - Struct containing variables accessed by shared code
3081 ******************************************************************************/
3082 static int
3083 e1000_detect_gig_phy(struct e1000_hw *hw)
3084 {
3085         int32_t phy_init_status, ret_val;
3086         uint16_t phy_id_high, phy_id_low;
3087         boolean_t match = FALSE;
3088
3089         DEBUGFUNC("e1000_detect_gig_phy");
3090         
3091         /* Read the PHY ID Registers to identify which PHY is onboard. */
3092         if((ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high)))
3093                 return ret_val;
3094
3095         hw->phy_id = (uint32_t) (phy_id_high << 16);
3096         udelay(20);
3097         if((ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low)))
3098                 return ret_val;
3099         
3100         hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
3101 #ifdef LINUX_DRIVER
3102         hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
3103 #endif
3104         
3105         switch(hw->mac_type) {
3106         case e1000_82543:
3107                 if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
3108                 break;
3109         case e1000_82544:
3110                 if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
3111                 break;
3112         case e1000_82540:
3113         case e1000_82545:
3114         case e1000_82545_rev_3:
3115         case e1000_82546:
3116         case e1000_82546_rev_3:
3117                 if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
3118                 break;
3119         case e1000_82541:
3120         case e1000_82541_rev_2:
3121         case e1000_82547:
3122         case e1000_82547_rev_2:
3123                 if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
3124                 break;
3125         default:
3126                 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
3127                 return -E1000_ERR_CONFIG;
3128         }
3129         phy_init_status = e1000_set_phy_type(hw);
3130
3131         if ((match) && (phy_init_status == E1000_SUCCESS)) {
3132                 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
3133                 return E1000_SUCCESS;
3134         }
3135         DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
3136         return -E1000_ERR_PHY;
3137 }
3138
3139 /******************************************************************************
3140  * Sets up eeprom variables in the hw struct.  Must be called after mac_type
3141  * is configured.
3142  *
3143  * hw - Struct containing variables accessed by shared code
3144  *****************************************************************************/
3145 static void
3146 e1000_init_eeprom_params(struct e1000_hw *hw)
3147 {
3148         struct e1000_eeprom_info *eeprom = &hw->eeprom;
3149         uint32_t eecd = E1000_READ_REG(hw, EECD);
3150         uint16_t eeprom_size;
3151
3152         DEBUGFUNC("e1000_init_eeprom_params");
3153
3154         switch (hw->mac_type) {
3155         case e1000_82542_rev2_0:
3156         case e1000_82542_rev2_1:
3157         case e1000_82543:
3158         case e1000_82544:
3159                 eeprom->type = e1000_eeprom_microwire;
3160                 eeprom->word_size = 64;
3161                 eeprom->opcode_bits = 3;
3162                 eeprom->address_bits = 6;
3163                 eeprom->delay_usec = 50;
3164                 break;
3165         case e1000_82540:
3166         case e1000_82545:
3167         case e1000_82545_rev_3:
3168         case e1000_82546:
3169         case e1000_82546_rev_3:
3170                 eeprom->type = e1000_eeprom_microwire;
3171                 eeprom->opcode_bits = 3;
3172                 eeprom->delay_usec = 50;
3173                 if(eecd & E1000_EECD_SIZE) {
3174                         eeprom->word_size = 256;
3175                         eeprom->address_bits = 8;
3176                 } else {
3177                         eeprom->word_size = 64;
3178                         eeprom->address_bits = 6;
3179                 }
3180                 break;
3181         case e1000_82541:
3182         case e1000_82541_rev_2:
3183         case e1000_82547:
3184         case e1000_82547_rev_2:
3185                 if (eecd & E1000_EECD_TYPE) {
3186                         eeprom->type = e1000_eeprom_spi;
3187                         if (eecd & E1000_EECD_ADDR_BITS) {
3188                                 eeprom->page_size = 32;
3189                                 eeprom->address_bits = 16;
3190                         } else {
3191                                 eeprom->page_size = 8;
3192                                 eeprom->address_bits = 8;
3193                         }
3194                 } else {
3195                         eeprom->type = e1000_eeprom_microwire;
3196                         eeprom->opcode_bits = 3;
3197                         eeprom->delay_usec = 50;
3198                         if (eecd & E1000_EECD_ADDR_BITS) {
3199                                 eeprom->word_size = 256;
3200                                 eeprom->address_bits = 8;
3201                         } else {
3202                                 eeprom->word_size = 64;
3203                                 eeprom->address_bits = 6;
3204                         }
3205                 }
3206                 break;
3207         default:
3208                 eeprom->type = e1000_eeprom_spi;
3209                 if (eecd & E1000_EECD_ADDR_BITS) {
3210                         eeprom->page_size = 32;
3211                         eeprom->address_bits = 16;
3212                 } else {
3213                         eeprom->page_size = 8;
3214                         eeprom->address_bits = 8;
3215                 }
3216                 break;
3217         }
3218
3219         if (eeprom->type == e1000_eeprom_spi) {
3220                 eeprom->opcode_bits = 8;
3221                 eeprom->delay_usec = 1;
3222                 eeprom->word_size = 64;
3223                 if (e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size) == 0) {
3224                         eeprom_size &= EEPROM_SIZE_MASK;
3225
3226                         switch (eeprom_size) {
3227                         case EEPROM_SIZE_16KB:
3228                                 eeprom->word_size = 8192;
3229                                 break;
3230                         case EEPROM_SIZE_8KB:
3231                                 eeprom->word_size = 4096;
3232                                 break;
3233                         case EEPROM_SIZE_4KB:
3234                                 eeprom->word_size = 2048;
3235                                 break;
3236                         case EEPROM_SIZE_2KB:
3237                                 eeprom->word_size = 1024;
3238                                 break;
3239                         case EEPROM_SIZE_1KB:
3240                                 eeprom->word_size = 512;
3241                                 break;
3242                         case EEPROM_SIZE_512B:
3243                                 eeprom->word_size = 256;
3244                                 break;
3245                         case EEPROM_SIZE_128B:
3246                         default:
3247                                 break;
3248                         }
3249                 }
3250         }
3251 }
3252
3253 /**
3254  * e1000_reset - Reset the adapter
3255  */
3256
3257 static int
3258 e1000_reset(struct e1000_hw *hw)
3259 {
3260         uint32_t pba;
3261         /* Repartition Pba for greater than 9k mtu
3262          * To take effect CTRL.RST is required.
3263          */
3264
3265         if(hw->mac_type < e1000_82547) {
3266                 pba = E1000_PBA_48K;
3267         } else {
3268                 pba = E1000_PBA_30K;
3269         }
3270         E1000_WRITE_REG(hw, PBA, pba);
3271
3272         /* flow control settings */
3273 #if 0
3274         hw->fc_high_water = FC_DEFAULT_HI_THRESH;
3275         hw->fc_low_water = FC_DEFAULT_LO_THRESH;
3276         hw->fc_pause_time = FC_DEFAULT_TX_TIMER;
3277         hw->fc_send_xon = 1;
3278         hw->fc = hw->original_fc;
3279 #endif
3280         
3281         e1000_reset_hw(hw);
3282         if(hw->mac_type >= e1000_82544)
3283                 E1000_WRITE_REG(hw, WUC, 0);
3284         return e1000_init_hw(hw);
3285 }
3286
3287 /**
3288  * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
3289  * @adapter: board private structure to initialize
3290  *
3291  * e1000_sw_init initializes the Adapter private data structure.
3292  * Fields are initialized based on PCI device information and
3293  * OS network device settings (MTU size).
3294  **/
3295
3296 static int 
3297 e1000_sw_init(struct pci_device *pdev, struct e1000_hw *hw)
3298 {
3299         int result;
3300
3301         /* PCI config space info */
3302         pci_read_config_word(pdev, PCI_VENDOR_ID, &hw->vendor_id);
3303         pci_read_config_word(pdev, PCI_DEVICE_ID, &hw->device_id);
3304         pci_read_config_byte(pdev, PCI_REVISION, &hw->revision_id);
3305 #if 0
3306         pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID,
3307                              &hw->subsystem_vendor_id);
3308         pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
3309 #endif
3310
3311         pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
3312
3313         /* identify the MAC */
3314
3315         result = e1000_set_mac_type(hw);
3316         if (result) {
3317                 E1000_ERR("Unknown MAC Type\n");
3318                 return result;
3319         }
3320
3321         /* initialize eeprom parameters */
3322
3323         e1000_init_eeprom_params(hw);
3324
3325 #if 0
3326         if((hw->mac_type == e1000_82541) ||
3327            (hw->mac_type == e1000_82547) ||
3328            (hw->mac_type == e1000_82541_rev_2) ||
3329            (hw->mac_type == e1000_82547_rev_2))
3330                 hw->phy_init_script = 1;
3331 #endif
3332
3333         e1000_set_media_type(hw);
3334
3335 #if 0
3336         if(hw->mac_type < e1000_82543)
3337                 hw->report_tx_early = 0;
3338         else
3339                 hw->report_tx_early = 1;
3340
3341         hw->wait_autoneg_complete = FALSE;
3342 #endif
3343         hw->tbi_compatibility_en = TRUE;
3344 #if 0
3345         hw->adaptive_ifs = TRUE;
3346
3347         /* Copper options */
3348
3349         if(hw->media_type == e1000_media_type_copper) {
3350                 hw->mdix = AUTO_ALL_MODES;
3351                 hw->disable_polarity_correction = FALSE;
3352                 hw->master_slave = E1000_MASTER_SLAVE;
3353         }
3354 #endif
3355         return E1000_SUCCESS;
3356 }
3357
3358 static void fill_rx (void)
3359 {
3360         struct e1000_rx_desc *rd;
3361         rx_last = rx_tail;
3362         rd = rx_base + rx_tail;
3363         rx_tail = (rx_tail + 1) % 8;
3364         memset (rd, 0, 16);
3365         rd->buffer_addr = virt_to_bus(&packet);
3366         E1000_WRITE_REG (&hw, RDT, rx_tail);
3367 }
3368
3369 static void init_descriptor (void)
3370 {
3371         unsigned long ptr;
3372         unsigned long tctl;
3373
3374         ptr = virt_to_phys(tx_pool);
3375         if (ptr & 0xf)
3376                 ptr = (ptr + 0x10) & (~0xf);
3377
3378         tx_base = phys_to_virt(ptr);
3379
3380         E1000_WRITE_REG (&hw, TDBAL, virt_to_bus(tx_base));
3381         E1000_WRITE_REG (&hw, TDBAH, 0);
3382         E1000_WRITE_REG (&hw, TDLEN, 128);
3383
3384         /* Setup the HW Tx Head and Tail descriptor pointers */
3385
3386         E1000_WRITE_REG (&hw, TDH, 0);
3387         E1000_WRITE_REG (&hw, TDT, 0);
3388         tx_tail = 0;
3389
3390         /* Program the Transmit Control Register */
3391
3392 #ifdef LINUX_DRIVER_TCTL
3393         tctl = E1000_READ_REG(&hw, TCTL);
3394
3395         tctl &= ~E1000_TCTL_CT;
3396         tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
3397                 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
3398 #else
3399         tctl = E1000_TCTL_PSP | E1000_TCTL_EN |
3400                 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT) | 
3401                 (E1000_HDX_COLLISION_DISTANCE << E1000_COLD_SHIFT);
3402 #endif
3403
3404         E1000_WRITE_REG (&hw, TCTL, tctl);
3405
3406         e1000_config_collision_dist(&hw);
3407
3408
3409         rx_tail = 0;
3410         /* disable receive */
3411         E1000_WRITE_REG (&hw, RCTL, 0);
3412         ptr = virt_to_phys(rx_pool);
3413         if (ptr & 0xf)
3414                 ptr = (ptr + 0x10) & (~0xf);
3415         rx_base = phys_to_virt(ptr);
3416
3417         /* Setup the Base and Length of the Rx Descriptor Ring */
3418
3419         E1000_WRITE_REG (&hw, RDBAL, virt_to_bus(rx_base));
3420         E1000_WRITE_REG (&hw, RDBAH, 0);
3421
3422         E1000_WRITE_REG (&hw, RDLEN, 128);
3423
3424         /* Setup the HW Rx Head and Tail Descriptor Pointers */
3425         E1000_WRITE_REG (&hw, RDH, 0);
3426         E1000_WRITE_REG (&hw, RDT, 0);
3427
3428         E1000_WRITE_REG (&hw, RCTL, 
3429                 E1000_RCTL_EN | 
3430                 E1000_RCTL_BAM | 
3431                 E1000_RCTL_SZ_2048 | 
3432                 E1000_RCTL_MPE);
3433         fill_rx();
3434 }
3435
3436
3437
3438 /**************************************************************************
3439 POLL - Wait for a frame
3440 ***************************************************************************/
3441 static int
3442 e1000_poll (struct nic *nic, int retrieve)
3443 {
3444         /* return true if there's an ethernet packet ready to read */
3445         /* nic->packet should contain data on return */
3446         /* nic->packetlen should contain length of data */
3447         struct e1000_rx_desc *rd;
3448         uint32_t icr;
3449
3450         rd = rx_base + rx_last;
3451         if (!rd->status & E1000_RXD_STAT_DD)
3452                 return 0;
3453
3454  &nb