src/drivers/net/r8169.c

   1 /**************************************************************************
   2 *    r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit
   3 *    Written 2003 by Timothy Legge <tlegge@rogers.com>
   4 *
   5 *    This program is free software; you can redistribute it and/or modify
   6 *    it under the terms of the GNU General Public License as published by
   7 *    the Free Software Foundation; either version 2 of the License, or
   8 *    (at your option) any later version.
   9 *
  10 *    This program is distributed in the hope that it will be useful,
  11 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 *    GNU General Public License for more details.
  14 *
  15 *    You should have received a copy of the GNU General Public License
  16 *    along with this program; if not, write to the Free Software
  17 *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18 *
  19 *    Portions of this code based on:
  20 *       r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver
  21 *               for Linux kernel 2.4.x.
  22 *
  23 *    Written 2002 ShuChen <shuchen@realtek.com.tw>
  24 *         See Linux Driver for full information
  25 *
  26 *    Linux Driver Versions:
  27 *       1.27a, 10.02.2002
  28 *       RTL8169_VERSION "2.2"   <2004/08/09>
  29 *
  30 *    Thanks to:
  31 *       Jean Chen of RealTek Semiconductor Corp. for
  32 *       providing the evaluation NIC used to develop
  33 *       this driver.  RealTek's support for Etherboot
  34 *       is appreciated.
  35 *
  36 *    REVISION HISTORY:
  37 *    ================
  38 *
  39 *    v1.0       11-26-2003      timlegge        Initial port of Linux driver
  40 *    v1.5       01-17-2004      timlegge        Initial driver output cleanup
  41 *    v1.6       03-27-2004      timlegge        Additional Cleanup
  42 *    v1.7       11-22-2005      timlegge        Update to RealTek Driver Version 2.2
  43 *
  44 *    Indent Options: indent -kr -i8
  45 ***************************************************************************/
  46
  47 /* to get some global routines like printf */
  48 #include "etherboot.h"
  49 /* to get the interface to the body of the program */
  50 #include "nic.h"
  51 /* to get the PCI support functions, if this is a PCI NIC */
  52 #include "pci.h"
  53 #include "timer.h"
  54
  55 #define drv_version "v1.6"
  56 #define drv_date "03-27-2004"
  57
  58 #define HZ 1000
  59
  60 static u32 ioaddr;
  61
  62 #ifdef EDEBUG
  63 #define dprintf(x) printf x
  64 #else
  65 #define dprintf(x)
  66 #endif
  67
  68 /* Condensed operations for readability. */
  69 #define virt_to_le32desc(addr)  cpu_to_le32(virt_to_bus(addr))
  70 #define le32desc_to_virt(addr)  bus_to_virt(le32_to_cpu(addr))
  71
  72 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
  73
  74 #undef RTL8169_DEBUG
  75 #undef RTL8169_JUMBO_FRAME_SUPPORT
  76 #undef RTL8169_HW_FLOW_CONTROL_SUPPORT
  77
  78
  79 #undef RTL8169_IOCTL_SUPPORT
  80 #undef RTL8169_DYNAMIC_CONTROL
  81 #define RTL8169_USE_IO
  82
  83
  84 #ifdef RTL8169_DEBUG
  85 #define assert(expr) \
  86                if(!(expr)) { printk( "Assertion failed! %s,%s,%s,line=%d\n", #expr,__FILE__,__FUNCTION__,__LINE__); }
  87 #define DBG_PRINT( fmt, args...)   printk("r8169: " fmt, ## args);
  88 #else
  89 #define assert(expr) do {} while (0)
  90 #define DBG_PRINT( fmt, args...)   ;
  91 #endif                          // end of #ifdef RTL8169_DEBUG
  92
  93 /* media options
  94         _10_Half = 0x01,
  95         _10_Full = 0x02,
  96         _100_Half = 0x04,
  97         _100_Full = 0x08,
  98         _1000_Full = 0x10,
  99 */
 100 static int media = -1;
 101
 102 #if 0
 103 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
 104 static int max_interrupt_work = 20;
 105 #endif
 106
 107 #if 0
 108 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
 109    The RTL chips use a 64 element hash table based on the Ethernet CRC.  */
 110 static int multicast_filter_limit = 32;
 111 #endif
 112
 113 /* MAC address length*/
 114 #define MAC_ADDR_LEN    6
 115
 116 /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/
 117 #define MAX_ETH_FRAME_SIZE      1536
 118
 119 #define TX_FIFO_THRESH 256      /* In bytes */
 120
 121 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer.  */
 122 #define RX_DMA_BURST    7       /* Maximum PCI burst, '6' is 1024 */
 123 #define TX_DMA_BURST    7       /* Maximum PCI burst, '6' is 1024 */
 124 #define ETTh                0x3F        /* 0x3F means NO threshold */
 125
 126 #define EarlyTxThld     0x3F    /* 0x3F means NO early transmit */
 127 #define RxPacketMaxSize 0x0800  /* Maximum size supported is 16K-1 */
 128 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
 129
 130 #define NUM_TX_DESC     1       /* Number of Tx descriptor registers */
 131 #define NUM_RX_DESC     4       /* Number of Rx descriptor registers */
 132 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
 133
 134 #define RTL_MIN_IO_SIZE 0x80
 135 #define TX_TIMEOUT  (6*HZ)
 136
 137 #define RTL8169_TIMER_EXPIRE_TIME 100   //100
 138
 139 #define ETH_HDR_LEN         14
 140 #define DEFAULT_MTU         1500
 141 #define DEFAULT_RX_BUF_LEN  1536
 142
 143
 144 #ifdef RTL8169_JUMBO_FRAME_SUPPORT
 145 #define MAX_JUMBO_FRAME_MTU    ( 10000 )
 146 #define MAX_RX_SKBDATA_SIZE    ( MAX_JUMBO_FRAME_MTU + ETH_HDR_LEN )
 147 #else
 148 #define MAX_RX_SKBDATA_SIZE 1600
 149 #endif                          //end #ifdef RTL8169_JUMBO_FRAME_SUPPORT
 150
 151 #ifdef RTL8169_USE_IO
 152 #define RTL_W8(reg, val8)   outb ((val8), ioaddr + (reg))
 153 #define RTL_W16(reg, val16) outw ((val16), ioaddr + (reg))
 154 #define RTL_W32(reg, val32) outl ((val32), ioaddr + (reg))
 155 #define RTL_R8(reg)         inb (ioaddr + (reg))
 156 #define RTL_R16(reg)        inw (ioaddr + (reg))
 157 #define RTL_R32(reg)        ((unsigned long) inl (ioaddr + (reg)))
 158 #else
 159 /* write/read MMIO register */
 160 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
 161 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
 162 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
 163 #define RTL_R8(reg)             readb (ioaddr + (reg))
 164 #define RTL_R16(reg)            readw (ioaddr + (reg))
 165 #define RTL_R32(reg)            ((unsigned long) readl (ioaddr + (reg)))
 166 #endif
 167
 168 #define MCFG_METHOD_1           0x01
 169 #define MCFG_METHOD_2           0x02
 170 #define MCFG_METHOD_3           0x03
 171 #define MCFG_METHOD_4           0x04
 172
 173 #define PCFG_METHOD_1           0x01    //PHY Reg 0x03 bit0-3 == 0x0000
 174 #define PCFG_METHOD_2           0x02    //PHY Reg 0x03 bit0-3 == 0x0001
 175 #define PCFG_METHOD_3           0x03    //PHY Reg 0x03 bit0-3 == 0x0002
 176
 177 static struct {
 178         const char *name;
 179         u8 mcfg;                /* depend on RTL8169 docs */
 180         u32 RxConfigMask;       /* should clear the bits supported by this chip */
 181 } rtl_chip_info[] = {
 182         {
 183         "RTL-8169", MCFG_METHOD_1, 0xff7e1880,}, {
 184         "RTL8169s/8110s", MCFG_METHOD_2, 0xff7e1880}, {
 185 "RTL8169s/8110s", MCFG_METHOD_3, 0xff7e1880},};
 186
 187 enum RTL8169_registers {
 188         MAC0 = 0x0,             /* Ethernet hardware address. */
 189         MAR0 = 0x8,             /* Multicast filter. */
 190         TxDescStartAddr = 0x20,
 191         TxHDescStartAddr = 0x28,
 192         FLASH = 0x30,
 193         ERSR = 0x36,
 194         ChipCmd = 0x37,
 195         TxPoll = 0x38,
 196         IntrMask = 0x3C,
 197         IntrStatus = 0x3E,
 198         TxConfig = 0x40,
 199         RxConfig = 0x44,
 200         RxMissed = 0x4C,
 201         Cfg9346 = 0x50,
 202         Config0 = 0x51,
 203         Config1 = 0x52,
 204         Config2 = 0x53,
 205         Config3 = 0x54,
 206         Config4 = 0x55,
 207         Config5 = 0x56,
 208         MultiIntr = 0x5C,
 209         PHYAR = 0x60,
 210         TBICSR = 0x64,
 211         TBI_ANAR = 0x68,
 212         TBI_LPAR = 0x6A,
 213         PHYstatus = 0x6C,
 214         RxMaxSize = 0xDA,
 215         CPlusCmd = 0xE0,
 216         RxDescStartAddr = 0xE4,
 217         ETThReg = 0xEC,
 218         FuncEvent = 0xF0,
 219         FuncEventMask = 0xF4,
 220         FuncPresetState = 0xF8,
 221         FuncForceEvent = 0xFC,
 222 };
 223
 224 enum RTL8169_register_content {
 225         /*InterruptStatusBits */
 226         SYSErr = 0x8000,
 227         PCSTimeout = 0x4000,
 228         SWInt = 0x0100,
 229         TxDescUnavail = 0x80,
 230         RxFIFOOver = 0x40,
 231         LinkChg = 0x20,
 232         RxOverflow = 0x10,
 233         TxErr = 0x08,
 234         TxOK = 0x04,
 235         RxErr = 0x02,
 236         RxOK = 0x01,
 237
 238         /*RxStatusDesc */
 239         RxRES = 0x00200000,
 240         RxCRC = 0x00080000,
 241         RxRUNT = 0x00100000,
 242         RxRWT = 0x00400000,
 243
 244         /*ChipCmdBits */
 245         CmdReset = 0x10,
 246         CmdRxEnb = 0x08,
 247         CmdTxEnb = 0x04,
 248         RxBufEmpty = 0x01,
 249
 250         /*Cfg9346Bits */
 251         Cfg9346_Lock = 0x00,
 252         Cfg9346_Unlock = 0xC0,
 253
 254         /*rx_mode_bits */
 255         AcceptErr = 0x20,
 256         AcceptRunt = 0x10,
 257         AcceptBroadcast = 0x08,
 258         AcceptMulticast = 0x04,
 259         AcceptMyPhys = 0x02,
 260         AcceptAllPhys = 0x01,
 261
 262         /*RxConfigBits */
 263         RxCfgFIFOShift = 13,
 264         RxCfgDMAShift = 8,
 265
 266         /*TxConfigBits */
 267         TxInterFrameGapShift = 24,
 268         TxDMAShift = 8,         /* DMA burst value (0-7) is shift this many bits */
 269
 270         /*rtl8169_PHYstatus */
 271         TBI_Enable = 0x80,
 272         TxFlowCtrl = 0x40,
 273         RxFlowCtrl = 0x20,
 274         _1000bpsF = 0x10,
 275         _100bps = 0x08,
 276         _10bps = 0x04,
 277         LinkStatus = 0x02,
 278         FullDup = 0x01,
 279
 280         /*GIGABIT_PHY_registers */
 281         PHY_CTRL_REG = 0,
 282         PHY_STAT_REG = 1,
 283         PHY_AUTO_NEGO_REG = 4,
 284         PHY_1000_CTRL_REG = 9,
 285
 286         /*GIGABIT_PHY_REG_BIT */
 287         PHY_Restart_Auto_Nego = 0x0200,
 288         PHY_Enable_Auto_Nego = 0x1000,
 289
 290         /* PHY_STAT_REG = 1; */
 291         PHY_Auto_Neco_Comp = 0x0020,
 292
 293         /* PHY_AUTO_NEGO_REG = 4; */
 294         PHY_Cap_10_Half = 0x0020,
 295         PHY_Cap_10_Full = 0x0040,
 296         PHY_Cap_100_Half = 0x0080,
 297         PHY_Cap_100_Full = 0x0100,
 298
 299         /* PHY_1000_CTRL_REG = 9; */
 300         PHY_Cap_1000_Full = 0x0200,
 301         PHY_Cap_1000_Half = 0x0100,
 302
 303         PHY_Cap_PAUSE = 0x0400,
 304         PHY_Cap_ASYM_PAUSE = 0x0800,
 305
 306         PHY_Cap_Null = 0x0,
 307
 308         /*_MediaType*/
 309         _10_Half = 0x01,
 310         _10_Full = 0x02,
 311         _100_Half = 0x04,
 312         _100_Full = 0x08,
 313         _1000_Full = 0x10,
 314
 315         /*_TBICSRBit*/
 316         TBILinkOK = 0x02000000,
 317 };
 318
 319 enum _DescStatusBit {
 320         OWNbit = 0x80000000,
 321         EORbit = 0x40000000,
 322         FSbit = 0x20000000,
 323         LSbit = 0x10000000,
 324 };
 325
 326 struct TxDesc {
 327         u32 status;
 328         u32 vlan_tag;
 329         u32 buf_addr;
 330         u32 buf_Haddr;
 331 };
 332
 333 struct RxDesc {
 334         u32 status;
 335         u32 vlan_tag;
 336         u32 buf_addr;
 337         u32 buf_Haddr;
 338 };
 339
 340 /* The descriptors for this card are required to be aligned on 256
 341  * byte boundaries.  As the align attribute does not do more than 16
 342  * bytes of alignment it requires some extra steps.  Add 256 to the
 343  * size of the array and the init_ring adjusts the alignment.
 344  *
 345  * UPDATE: This is no longer true; we can request arbitrary alignment.
 346  */
 347
 348 /* Define the TX and RX Descriptors and Buffers */
 349 #define __align_256 __attribute__ (( aligned ( 256 ) ))
 350 struct {
 351         struct TxDesc tx_ring[NUM_TX_DESC] __align_256;
 352         unsigned char txb[NUM_TX_DESC * RX_BUF_SIZE];
 353         struct RxDesc rx_ring[NUM_RX_DESC] __align_256;
 354         unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE];
 355 } r8169_bufs __shared;
 356 #define tx_ring r8169_bufs.tx_ring
 357 #define rx_ring r8169_bufs.rx_ring
 358 #define txb r8169_bufs.txb
 359 #define rxb r8169_bufs.rxb
 360
 361 static struct rtl8169_private {
 362         void *mmio_addr;        /* memory map physical address */
 363         int chipset;
 364         int pcfg;
 365         int mcfg;
 366         unsigned long cur_rx;   /* Index into the Rx descriptor buffer of next Rx pkt. */
 367         unsigned long cur_tx;   /* Index into the Tx descriptor buffer of next Rx pkt. */
 368         struct TxDesc *TxDescArray;     /* Index of 256-alignment Tx Descriptor buffer */
 369         struct RxDesc *RxDescArray;     /* Index of 256-alignment Rx Descriptor buffer */
 370         unsigned char *RxBufferRing[NUM_RX_DESC];       /* Index of Rx Buffer array */
 371         unsigned char *Tx_skbuff[NUM_TX_DESC];
 372 } tpx;
 373
 374 static struct rtl8169_private *tpc;
 375
 376 static const u16 rtl8169_intr_mask =
 377     LinkChg | RxOverflow | RxFIFOOver | TxErr | TxOK | RxErr | RxOK;
 378 static const unsigned int rtl8169_rx_config =
 379     (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift) |
 380     0x0000000E;
 381
 382 static void rtl8169_hw_PHY_config(struct nic *nic __unused);
 383 //static void rtl8169_hw_PHY_reset(struct net_device *dev);
 384
 385 #define RTL8169_WRITE_GMII_REG_BIT( ioaddr, reg, bitnum, bitval )\
 386 { \
 387        int val; \
 388        if( bitval == 1 ){ val = ( RTL8169_READ_GMII_REG( ioaddr, reg ) | (bitval<<bitnum) ) & 0xffff ; } \
 389        else{ val = ( RTL8169_READ_GMII_REG( ioaddr, reg ) & (~(0x0001<<bitnum)) ) & 0xffff ; } \
 390        RTL8169_WRITE_GMII_REG( ioaddr, reg, val ); \
 391  }
 392
 393 //=================================================================
 394 //      PHYAR
 395 //      bit             Symbol
 396 //      31              Flag
 397 //      30-21   reserved
 398 //      20-16   5-bit GMII/MII register address
 399 //      15-0    16-bit GMII/MII register data
 400 //=================================================================
 401 void RTL8169_WRITE_GMII_REG(unsigned long ioaddr, int RegAddr, int value)
 402 {
 403         int i;
 404
 405         RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
 406         udelay(1000);
 407
 408         for (i = 2000; i > 0; i--) {
 409                 // Check if the RTL8169 has completed writing to the specified MII register
 410                 if (!(RTL_R32(PHYAR) & 0x80000000)) {
 411                         break;
 412                 } else {
 413                         udelay(100);
 414                 }               // end of if( ! (RTL_R32(PHYAR)&0x80000000) )
 415         }                       // end of for() loop
 416 }
 417
 418 //=================================================================
 419 int RTL8169_READ_GMII_REG(unsigned long ioaddr, int RegAddr)
 420 {
 421         int i, value = -1;
 422
 423         RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
 424         udelay(1000);
 425
 426         for (i = 2000; i > 0; i--) {
 427                 // Check if the RTL8169 has completed retrieving data from the specified MII register
 428                 if (RTL_R32(PHYAR) & 0x80000000) {
 429                         value = (int) (RTL_R32(PHYAR) & 0xFFFF);
 430                         break;
 431                 } else {
 432                         udelay(100);
 433                 }               // end of if( RTL_R32(PHYAR) & 0x80000000 )
 434         }                       // end of for() loop
 435         return value;
 436 }
 437
 438
 439 static void mdio_write(int RegAddr, int value)
 440 {
 441         int i;
 442
 443         RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
 444         udelay(1000);
 445
 446         for (i = 2000; i > 0; i--) {
 447                 /* Check if the RTL8169 has completed writing to the specified MII register */
 448                 if (!(RTL_R32(PHYAR) & 0x80000000)) {
 449                         break;
 450                 } else {
 451                         udelay(100);
 452                 }
 453         }
 454 }
 455
 456 static int mdio_read(int RegAddr)
 457 {
 458         int i, value = -1;
 459
 460         RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
 461         udelay(1000);
 462
 463         for (i = 2000; i > 0; i--) {
 464                 /* Check if the RTL8169 has completed retrieving data from the specified MII register */
 465                 if (RTL_R32(PHYAR) & 0x80000000) {
 466                         value = (int) (RTL_R32(PHYAR) & 0xFFFF);
 467                         break;
 468                 } else {
 469                         udelay(100);
 470                 }
 471         }
 472         return value;
 473 }
 474
 475 #define IORESOURCE_MEM 0x00000200
 476
 477 static int rtl8169_init_board(struct pci_device *pdev)
 478 {
 479         int i;
 480         unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
 481
 482         adjust_pci_device(pdev);
 483
 484         mmio_start = pci_bar_start(pdev, PCI_BASE_ADDRESS_1);
 485 //       mmio_end = pci_resource_end (pdev, 1);
 486 //       mmio_flags = pci_resource_flags (pdev, PCI_BASE_ADDRESS_1);
 487         mmio_len = pci_bar_size(pdev, PCI_BASE_ADDRESS_1);
 488
 489         // make sure PCI base addr 1 is MMIO
 490 //     if (!(mmio_flags & IORESOURCE_MEM)) {
 491 //             printf ("region #1 not an MMIO resource, aborting\n");
 492 //             return 0;
 493 //     }
 494
 495         // check for weird/broken PCI region reporting
 496         if (mmio_len < RTL_MIN_IO_SIZE) {
 497                 printf("Invalid PCI region size(s), aborting\n");
 498                 return 0;
 499         }
 500 #ifdef RTL8169_USE_IO
 501         ioaddr = pci_bar_start(pdev, PCI_BASE_ADDRESS_0);
 502 #else
 503         // ioremap MMIO region
 504         ioaddr = (unsigned long) ioremap(mmio_start, mmio_len);
 505         if (ioaddr == 0) {
 506                 printk("cannot remap MMIO, aborting\n");
 507                 return 0;
 508         }
 509 #endif
 510
 511         tpc->mmio_addr = &ioaddr;
 512         /* Soft reset the chip. */
 513         RTL_W8(ChipCmd, CmdReset);
 514
 515         /* Check that the chip has finished the reset. */
 516         for (i = 1000; i > 0; i--)
 517                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
 518                         break;
 519                 else
 520                         udelay(10);
 521         // identify config method
 522         {
 523                 unsigned long val32 = (RTL_R32(TxConfig) & 0x7c800000);
 524                 if (val32 == (0x1 << 28)) {
 525                         tpc->mcfg = MCFG_METHOD_4;
 526                 } else if (val32 == (0x1 << 26)) {
 527                         tpc->mcfg = MCFG_METHOD_3;
 528                 } else if (val32 == (0x1 << 23)) {
 529                         tpc->mcfg = MCFG_METHOD_2;
 530                 } else if (val32 == 0x00000000) {
 531                         tpc->mcfg = MCFG_METHOD_1;
 532                 } else {
 533                         tpc->mcfg = MCFG_METHOD_1;
 534                 }
 535         }
 536         {
 537                 unsigned char val8 =
 538                     (unsigned char) (RTL8169_READ_GMII_REG(ioaddr, 3) &
 539                                      0x000f);
 540                 if (val8 == 0x00) {
 541                         tpc->pcfg = PCFG_METHOD_1;
 542                 } else if (val8 == 0x01) {
 543                         tpc->pcfg = PCFG_METHOD_2;
 544                 } else if (val8 == 0x02) {
 545                         tpc->pcfg = PCFG_METHOD_3;
 546                 } else {
 547                         tpc->pcfg = PCFG_METHOD_3;
 548                 }
 549         }
 550
 551         /* identify chip attached to board */
 552
 553         for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--)
 554                 if (tpc->mcfg == rtl_chip_info[i].mcfg) {
 555                         tpc->chipset = i;
 556                         goto match;
 557                 }
 558         /* if unknown chip, assume array element #0, original RTL-8169 in this case */
 559         dprintf(("PCI device: unknown chip version, assuming RTL-8169\n"));
 560         dprintf(("PCI device: TxConfig = 0x%hX\n",
 561                  (unsigned long) RTL_R32(TxConfig)));
 562
 563         tpc->chipset = 0;
 564         return 1;
 565
 566       match:
 567         return 0;
 568
 569 }
 570
 571 /**************************************************************************
 572 IRQ - Wait for a frame
 573 ***************************************************************************/
 574 void r8169_irq(struct nic *nic __unused, irq_action_t action)
 575 {
 576         int intr_status = 0;
 577         int interested = RxOverflow | RxFIFOOver | RxErr | RxOK;
 578
 579         switch (action) {
 580         case DISABLE:
 581         case ENABLE:
 582                 intr_status = RTL_R16(IntrStatus);
 583                 /* h/w no longer present (hotplug?) or major error,
 584                    bail */
 585                 if (intr_status == 0xFFFF)
 586                         break;
 587
 588                 intr_status = intr_status & ~interested;
 589                 if (action == ENABLE)
 590                         intr_status = intr_status | interested;
 591                 RTL_W16(IntrMask, intr_status);
 592                 break;
 593         case FORCE:
 594                 RTL_W8(TxPoll, (RTL_R8(TxPoll) | 0x01));
 595                 break;
 596         }
 597 }
 598
 599 static void r8169_irq ( struct nic *nic __unused, irq_action_t action ) {
 600         int intr_status = 0;
 601         int interested = RxUnderrun | RxOverflow | RxFIFOOver | RxErr | RxOK;
 602
 603         switch ( action ) {
 604                 case DISABLE:
 605                 case ENABLE:
 606                         intr_status = RTL_R16(IntrStatus);
 607                         /* h/w no longer present (hotplug?) or major error,
 608                                 bail */
 609                         if (intr_status == 0xFFFF)
 610                                 break;
 611
 612                         intr_status = intr_status & ~interested;
 613                         if ( action == ENABLE )
 614                                 intr_status = intr_status | interested;
 615                         RTL_W16(IntrMask, intr_status);
 616                         break;
 617                 case FORCE :
 618                         RTL_W8(TxPoll, (RTL_R8(TxPoll) | 0x01));
 619                         break;
 620         }
 621 }
 622
 623 /**************************************************************************
 624 POLL - Wait for a frame
 625 ***************************************************************************/
 626 static int r8169_poll(struct nic *nic, int retreive)
 627 {
 628         /* return true if there's an ethernet packet ready to read */
 629         /* nic->packet should contain data on return */
 630         /* nic->packetlen should contain length of data */
 631         int cur_rx;
 632         unsigned int intr_status = 0;
 633         cur_rx = tpc->cur_rx;
 634         if ((tpc->RxDescArray[cur_rx].status & OWNbit) == 0) {
 635                 /* There is a packet ready */
 636                 if (!retreive)
 637                         return 1;
 638                 intr_status = RTL_R16(IntrStatus);
 639                 /* h/w no longer present (hotplug?) or major error,
 640                    bail */
 641                 if (intr_status == 0xFFFF)
 642                         return 0;
 643                 RTL_W16(IntrStatus, intr_status &
 644                         ~(RxFIFOOver | RxOverflow | RxOK));
 645
 646                 if (!(tpc->RxDescArray[cur_rx].status & RxRES)) {
 647                         nic->packetlen = (int) (tpc->RxDescArray[cur_rx].
 648                                                 status & 0x00001FFF) - 4;
 649                         memcpy(nic->packet, tpc->RxBufferRing[cur_rx],
 650                                nic->packetlen);
 651                         if (cur_rx == NUM_RX_DESC - 1)
 652                                 tpc->RxDescArray[cur_rx].status =
 653                                     (OWNbit | EORbit) + RX_BUF_SIZE;
 654                         else
 655                                 tpc->RxDescArray[cur_rx].status =
 656                                     OWNbit + RX_BUF_SIZE;
 657                         tpc->RxDescArray[cur_rx].buf_addr =
 658                             virt_to_bus(tpc->RxBufferRing[cur_rx]);
 659                 } else
 660                         printf("Error Rx");
 661                 /* FIXME: shouldn't I reset the status on an error */
 662                 cur_rx = (cur_rx + 1) % NUM_RX_DESC;
 663                 tpc->cur_rx = cur_rx;
 664                 RTL_W16(IntrStatus, intr_status &
 665                         (RxFIFOOver | RxOverflow | RxOK));
 666
 667                 return 1;
 668
 669         }
 670         tpc->cur_rx = cur_rx;
 671         /* FIXME: There is no reason to do this as cur_rx did not change */
 672
 673         return (0);             /* initially as this is called to flush the input */
 674
 675 }
 676
 677 /**************************************************************************
 678 TRANSMIT - Transmit a frame
 679 ***************************************************************************/
 680 static void r8169_transmit(struct nic *nic, const char *d,      /* Destination */
 681                            unsigned int t,      /* Type */
 682                            unsigned int s,      /* size */
 683                            const char *p)
 684 {                               /* Packet */
 685         /* send the packet to destination */
 686
 687         u16 nstype;
 688         u32 to;
 689         u8 *ptxb;
 690         int entry = tpc->cur_tx % NUM_TX_DESC;
 691
 692         /* point to the current txb incase multiple tx_rings are used */
 693         ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE];
 694         memcpy(ptxb, d, ETH_ALEN);
 695         memcpy(ptxb + ETH_ALEN, nic->node_addr, ETH_ALEN);
 696         nstype = htons((u16) t);
 697         memcpy(ptxb + 2 * ETH_ALEN, (u8 *) & nstype, 2);
 698         memcpy(ptxb + ETH_HLEN, p, s);
 699         s += ETH_HLEN;
 700         s &= 0x0FFF;
 701         while (s < ETH_ZLEN)
 702                 ptxb[s++] = '\0';
 703
 704         tpc->TxDescArray[entry].buf_addr = virt_to_bus(ptxb);
 705         if (entry != (NUM_TX_DESC - 1))
 706                 tpc->TxDescArray[entry].status =
 707                     (OWNbit | FSbit | LSbit) | ((s > ETH_ZLEN) ? s :
 708                                                 ETH_ZLEN);
 709         else
 710                 tpc->TxDescArray[entry].status =
 711                     (OWNbit | EORbit | FSbit | LSbit) | ((s > ETH_ZLEN) ? s
 712                                                          : ETH_ZLEN);
 713         RTL_W8(TxPoll, 0x40);   /* set polling bit */
 714
 715         tpc->cur_tx++;
 716         to = currticks() + TX_TIMEOUT;
 717         while ((tpc->TxDescArray[entry].status & OWNbit) && (currticks() < to));        /* wait */
 718
 719         if (currticks() >= to) {
 720                 printf("TX Time Out");
 721         }
 722 }
 723
 724 static void rtl8169_set_rx_mode(struct nic *nic __unused)
 725 {
 726         u32 mc_filter[2];       /* Multicast hash filter */
 727         int rx_mode;
 728         u32 tmp = 0;
 729
 730         /* IFF_ALLMULTI */
 731         /* Too many to filter perfectly -- accept all multicasts. */
 732         rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
 733         mc_filter[1] = mc_filter[0] = 0xffffffff;
 734
 735         tmp =
 736             rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) &
 737                                            rtl_chip_info[tpc->chipset].
 738                                            RxConfigMask);
 739
 740         RTL_W32(RxConfig, tmp);
 741         RTL_W32(MAR0 + 0, mc_filter[0]);
 742         RTL_W32(MAR0 + 4, mc_filter[1]);
 743 }
 744 static void rtl8169_hw_start(struct nic *nic)
 745 {
 746         u32 i;
 747
 748         /* Soft reset the chip. */
 749         RTL_W8(ChipCmd, CmdReset);
 750
 751         /* Check that the chip has finished the reset. */
 752         for (i = 1000; i > 0; i--) {
 753                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
 754                         break;
 755                 else
 756                         udelay(10);
 757         }
 758
 759         RTL_W8(Cfg9346, Cfg9346_Unlock);
 760         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
 761         RTL_W8(ETThReg, ETTh);
 762
 763         /* For gigabit rtl8169 */
 764         RTL_W16(RxMaxSize, RxPacketMaxSize);
 765
 766         /* Set Rx Config register */
 767         i = rtl8169_rx_config | (RTL_R32(RxConfig) &
 768                                  rtl_chip_info[tpc->chipset].RxConfigMask);
 769         RTL_W32(RxConfig, i);
 770
 771         /* Set DMA burst size and Interframe Gap Time */
 772         RTL_W32(TxConfig,
 773                 (TX_DMA_BURST << TxDMAShift) | (InterFrameGap <<
 774                                                 TxInterFrameGapShift));
 775
 776
 777         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd));
 778
 779         if (tpc->mcfg == MCFG_METHOD_2 || tpc->mcfg == MCFG_METHOD_3) {
 780                 RTL_W16(CPlusCmd,
 781                         (RTL_R16(CPlusCmd) | (1 << 14) | (1 << 3)));
 782                 DBG_PRINT
 783                     ("Set MAC Reg C+CR Offset 0xE0: bit-3 and bit-14\n");
 784         } else {
 785                 RTL_W16(CPlusCmd, (RTL_R16(CPlusCmd) | (1 << 3)));
 786                 DBG_PRINT("Set MAC Reg C+CR Offset 0xE0: bit-3.\n");
 787         }
 788
 789         {
 790                 //RTL_W16(0xE2, 0x1517);
 791                 //RTL_W16(0xE2, 0x152a);
 792                 //RTL_W16(0xE2, 0x282a);
 793                 RTL_W16(0xE2, 0x0000);
 794         }
 795
 796
 797
 798         tpc->cur_rx = 0;
 799
 800         RTL_W32(TxDescStartAddr, virt_to_le32desc(tpc->TxDescArray));
 801         RTL_W32(RxDescStartAddr, virt_to_le32desc(tpc->RxDescArray));
 802         RTL_W8(Cfg9346, Cfg9346_Lock);
 803         udelay(10);
 804
 805         RTL_W32(RxMissed, 0);
 806
 807         rtl8169_set_rx_mode(nic);
 808
 809         /* no early-rx interrupts */
 810         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
 811
 812         RTL_W16(IntrMask, rtl8169_intr_mask);
 813
 814 }
 815
 816 static void rtl8169_init_ring(struct nic *nic __unused)
 817 {
 818         int i;
 819
 820         tpc->cur_rx = 0;
 821         tpc->cur_tx = 0;
 822         memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc));
 823         memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc));
 824
 825         for (i = 0; i < NUM_TX_DESC; i++) {
 826                 tpc->Tx_skbuff[i] = &txb[i];
 827         }
 828
 829         for (i = 0; i < NUM_RX_DESC; i++) {
 830                 if (i == (NUM_RX_DESC - 1))
 831                         tpc->RxDescArray[i].status =
 832                             (OWNbit | EORbit) | RX_BUF_SIZE;
 833                 else
 834                         tpc->RxDescArray[i].status = OWNbit | RX_BUF_SIZE;
 835
 836                 tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE];
 837                 tpc->RxDescArray[i].buf_addr =
 838                     virt_to_bus(tpc->RxBufferRing[i]);
 839         }
 840 }
 841
 842 /**************************************************************************
 843 RESET - Finish setting up the ethernet interface
 844 ***************************************************************************/
 845 static void r8169_reset(struct nic *nic)
 846 {
 847         int i;
 848
 849         tpc->TxDescArray = tx_ring;
 850         tpc->RxDescArray = rx_ring;
 851
 852         rtl8169_init_ring(nic);
 853         rtl8169_hw_start(nic);
 854         /* Construct a perfect filter frame with the mac address as first match
 855          * and broadcast for all others */
 856         for (i = 0; i < 192; i++)
 857                 txb[i] = 0xFF;
 858
 859         txb[0] = nic->node_addr[0];
 860         txb[1] = nic->node_addr[1];
 861         txb[2] = nic->node_addr[2];
 862         txb[3] = nic->node_addr[3];
 863         txb[4] = nic->node_addr[4];
 864         txb[5] = nic->node_addr[5];
 865 }
 866
 867 /**************************************************************************
 868 DISABLE - Turn off ethernet interface
 869 ***************************************************************************/
 870 static void r8169_disable ( struct nic *nic __unused ) {
 871         int i;
 872         /* Stop the chip's Tx and Rx DMA processes. */
 873         RTL_W8(ChipCmd, 0x00);
 874
 875         /* Disable interrupts by clearing the interrupt mask. */
 876         RTL_W16(IntrMask, 0x0000);
 877
 878         RTL_W32(RxMissed, 0);
 879
 880         tpc->TxDescArray = NULL;
 881         tpc->RxDescArray = NULL;
 882         for (i = 0; i < NUM_RX_DESC; i++) {
 883                 tpc->RxBufferRing[i] = NULL;
 884         }
 885 }
 886
 887 static struct nic_operations r8169_operations = {
 888         .connect        = dummy_connect,
 889         .poll           = r8169_poll,
 890         .transmit       = r8169_transmit,
 891         .irq            = r8169_irq,
 892
 893 };
 894
 895 static struct pci_id r8169_nics[] = {
 896         PCI_ROM(0x10ec, 0x8169, "r8169", "RealTek RTL8169 Gigabit Ethernet"),
 897         PCI_ROM(0x16ec, 0x0116, "usr-r8169", "US Robotics RTL8169 Gigabit Ethernet"),
 898         PCI_ROM(0x1186, 0x4300, "dlink-r8169", "D-Link RTL8169 Gigabit Ethernet"),
 899 };
 900
 901 PCI_DRIVER ( r8169_driver, r8169_nics, PCI_NO_CLASS );
 902
 903 /**************************************************************************
 904 PROBE - Look for an adapter, this routine's visible to the outside
 905 ***************************************************************************/
 906
 907 #define board_found 1
 908 #define valid_link 0
 909 static int r8169_probe ( struct nic *nic, struct pci_device *pci ) {
 910
 911         static int board_idx = -1;
 912         static int printed_version = 0;
 913         int i, rc;
 914         int option = -1, Cap10_100 = 0, Cap1000 = 0;
 915
 916         printf("r8169.c: Found %s, Vendor=%hX Device=%hX\n",
 917                pci->name, pci->vendor_id, pci->device_id);
 918
 919         board_idx++;
 920
 921         printed_version = 1;
 922
 923         /* point to private storage */
 924         tpc = &tpx;
 925
 926         rc = rtl8169_init_board(pci);   /* Return code is meaningless */
 927
 928         /* Get MAC address.  FIXME: read EEPROM */
 929         for (i = 0; i < MAC_ADDR_LEN; i++)
 930                 nic->node_addr[i] = RTL_R8(MAC0 + i);
 931
 932         dprintf(("%s: Identified chip type is '%s'.\n", pci->name,
 933                  rtl_chip_info[tpc->chipset].name));
 934         /* Print out some hardware info */
 935         printf("%s: %! at ioaddr %hX, ", pci->name, nic->node_addr,
 936                ioaddr);
 937
 938         // Config PHY
 939         rtl8169_hw_PHY_config(nic);
 940
 941         DBG_PRINT("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
 942         RTL_W8(0x82, 0x01);
 943
 944         if (tpc->mcfg < MCFG_METHOD_3) {
 945                 DBG_PRINT("Set PCI Latency=0x40\n");
 946                 pci_write_config_byte(pci, PCI_LATENCY_TIMER, 0x40);
 947         }
 948
 949         if (tpc->mcfg == MCFG_METHOD_2) {
 950                 DBG_PRINT("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
 951                 RTL_W8(0x82, 0x01);
 952                 DBG_PRINT("Set PHY Reg 0x0bh = 0x00h\n");
 953                 RTL8169_WRITE_GMII_REG(ioaddr, 0x0b, 0x0000);   //w 0x0b 15 0 0
 954         }
 955
 956         /* if TBI is not endbled */
 957         if (!(RTL_R8(PHYstatus) & TBI_Enable)) {
 958                 int val = RTL8169_READ_GMII_REG(ioaddr, PHY_AUTO_NEGO_REG);
 959
 960 #ifdef RTL8169_HW_FLOW_CONTROL_SUPPORT
 961                 val |= PHY_Cap_PAUSE | PHY_Cap_ASYM_PAUSE;
 962 #endif                          //end #define RTL8169_HW_FLOW_CONTROL_SUPPORT
 963
 964                 option = media;
 965                 /* Force RTL8169 in 10/100/1000 Full/Half mode. */
 966                 if (option > 0) {
 967                         printf(" Force-mode Enabled.\n");
 968                         Cap10_100 = 0, Cap1000 = 0;
 969                         switch (option) {
 970                         case _10_Half:
 971                                 Cap10_100 = PHY_Cap_10_Half;
 972                                 Cap1000 = PHY_Cap_Null;
 973                                 break;
 974                         case _10_Full:
 975                                 Cap10_100 = PHY_Cap_10_Full;
 976                                 Cap1000 = PHY_Cap_Null;
 977                                 break;
 978                         case _100_Half:
 979                                 Cap10_100 = PHY_Cap_100_Half;
 980                                 Cap1000 = PHY_Cap_Null;
 981                                 break;
 982                         case _100_Full:
 983                                 Cap10_100 = PHY_Cap_100_Full;
 984                                 Cap1000 = PHY_Cap_Null;
 985                                 break;
 986                         case _1000_Full:
 987                                 Cap10_100 = PHY_Cap_Null;
 988                                 Cap1000 = PHY_Cap_1000_Full;
 989                                 break;
 990                         default:
 991                                 break;
 992                         }
 993                         RTL8169_WRITE_GMII_REG(ioaddr, PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0xC1F));   //leave PHY_AUTO_NEGO_REG bit4:0 unchanged
 994                         RTL8169_WRITE_GMII_REG(ioaddr, PHY_1000_CTRL_REG,
 995                                                Cap1000);
 996                 } else {
 997                         dprintf(("Auto-negotiation Enabled.\n",
 998                                  pci->name));
 999
1000                         // enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged
1001                         RTL8169_WRITE_GMII_REG(ioaddr, PHY_AUTO_NEGO_REG,
1002                                                PHY_Cap_10_Half |
1003                                                PHY_Cap_10_Full |
1004                                                PHY_Cap_100_Half |
1005                                                PHY_Cap_100_Full | (val &
1006                                                                    0xC1F));
1007
1008                         // enable 1000 Full Mode
1009 //                     RTL8169_WRITE_GMII_REG( ioaddr, PHY_1000_CTRL_REG, PHY_Cap_1000_Full );
1010                         RTL8169_WRITE_GMII_REG(ioaddr, PHY_1000_CTRL_REG, PHY_Cap_1000_Full | PHY_Cap_1000_Half);       //rtl8168
1011
1012                 }               // end of if( option > 0 )
1013
1014                 // Enable auto-negotiation and restart auto-nigotiation
1015                 RTL8169_WRITE_GMII_REG(ioaddr, PHY_CTRL_REG,
1016                                        PHY_Enable_Auto_Nego |
1017                                        PHY_Restart_Auto_Nego);
1018                 udelay(100);
1019
1020                 // wait for auto-negotiation process
1021                 for (i = 10000; i > 0; i--) {
1022                         //check if auto-negotiation complete
1023                         if (RTL8169_READ_GMII_REG(ioaddr, PHY_STAT_REG) &
1024                             PHY_Auto_Neco_Comp) {
1025                                 udelay(100);
1026                                 option = RTL_R8(PHYstatus);
1027                                 if (option & _1000bpsF) {
1028                                         printf
1029                                             ("1000Mbps Full-duplex operation.\n");
1030                                 } else {
1031                                         printf
1032                                             ("%sMbps %s-duplex operation.\n",
1033                                              (option & _100bps) ? "100" :
1034                                              "10",
1035                                              (option & FullDup) ? "Full" :
1036                                              "Half");
1037                                 }
1038                                 break;
1039                         } else {
1040                                 udelay(100);
1041                         }       // end of if( RTL8169_READ_GMII_REG(ioaddr, 1) & 0x20 )
1042                 }               // end for-loop to wait for auto-negotiation process
1043
1044
1045         } else {
1046                 udelay(100);
1047                 printf
1048                     ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n",
1049                      pci->name,
1050                      (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed");
1051
1052         }
1053
1054         r8169_reset(nic);
1055         /* point to NIC specific routines */
1056         nic->nic_op     = &r8169_operations;
1057         pci_fill_nic ( nic, pci );
1058         nic->irqno = pci->irq;
1059         nic->ioaddr = ioaddr;
1060         return 1;
1061
1062 }
1063
1064 //======================================================================================================
1065 /*
1066 static void rtl8169_hw_PHY_reset(struct nic *nic __unused)
1067 {
1068         int val, phy_reset_expiretime = 50;
1069         struct rtl8169_private *priv = dev->priv;
1070         unsigned long ioaddr = priv->ioaddr;
1071
1072         DBG_PRINT("%s: Reset RTL8169s PHY\n", dev->name);
1073
1074         val = ( RTL8169_READ_GMII_REG( ioaddr, 0 ) | 0x8000 ) & 0xffff;
1075         RTL8169_WRITE_GMII_REG( ioaddr, 0, val );
1076
1077         do //waiting for phy reset
1078         {
1079                 if( RTL8169_READ_GMII_REG( ioaddr, 0 ) & 0x8000 ){
1080                         phy_reset_expiretime --;
1081                         udelay(100);
1082                 }
1083                 else{
1084                         break;
1085                 }
1086         }while( phy_reset_expiretime >= 0 );
1087
1088         assert( phy_reset_expiretime > 0 );
1089 }
1090
1091 */
1092
1093 //======================================================================================================
1094 static void rtl8169_hw_PHY_config(struct nic *nic __unused)
1095 {
1096
1097         DBG_PRINT("priv->mcfg=%d, priv->pcfg=%d\n", tpc->mcfg, tpc->pcfg);
1098
1099         if (tpc->mcfg == MCFG_METHOD_4) {
1100 /*
1101                 RTL8169_WRITE_GMII_REG( (unsigned long)ioaddr, 0x1F, 0x0001 );
1102                 RTL8169_WRITE_GMII_REG( (unsigned long)ioaddr, 0x1b, 0x841e );
1103                 RTL8169_WRITE_GMII_REG( (unsigned long)ioaddr, 0x0e, 0x7bfb );
1104                 RTL8169_WRITE_GMII_REG( (unsigned long)ioaddr, 0x09, 0x273a );
1105 */
1106
1107                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x1F,
1108                                        0x0002);
1109                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x01,
1110                                        0x90D0);
1111                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x1F,
1112                                        0x0000);
1113         } else if ((tpc->mcfg == MCFG_METHOD_2)
1114                    || (tpc->mcfg == MCFG_METHOD_3)) {
1115                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x1F,
1116                                        0x0001);
1117                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x15,
1118                                        0x1000);
1119                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x18,
1120                                        0x65C7);
1121                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1122                                        0x0000);
1123                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x03,
1124                                        0x00A1);
1125                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x02,
1126                                        0x0008);
1127                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x01,
1128                                        0x1020);
1129                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x00,
1130                                        0x1000);
1131                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1132                                        0x0800);
1133                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1134                                        0x0000);
1135                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1136                                        0x7000);
1137                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x03,
1138                                        0xFF41);
1139                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x02,
1140                                        0xDE60);
1141                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x01,
1142                                        0x0140);
1143                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x00,
1144                                        0x0077);
1145                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1146                                        0x7800);
1147                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1148                                        0x7000);
1149                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1150                                        0xA000);
1151                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x03,
1152                                        0xDF01);
1153                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x02,
1154                                        0xDF20);
1155                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x01,
1156                                        0xFF95);
1157                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x00,
1158                                        0xFA00);
1159                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1160                                        0xA800);
1161                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1162                                        0xA000);
1163                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1164                                        0xB000);
1165                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x03,
1166                                        0xFF41);
1167                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x02,
1168                                        0xDE20);
1169                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x01,
1170                                        0x0140);
1171                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x00,
1172                                        0x00BB);
1173                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1174                                        0xB800);
1175                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1176                                        0xB000);
1177                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1178                                        0xF000);
1179                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x03,
1180                                        0xDF01);
1181                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x02,
1182                                        0xDF20);
1183                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x01,
1184                                        0xFF95);
1185                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x00,
1186                                        0xBF00);
1187                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1188                                        0xF800);
1189                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1190                                        0xF000);
1191                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1192                                        0x0000);
1193                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x1F,
1194                                        0x0000);
1195                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x0B,
1196                                        0x0000);
1197         } else {
1198                 DBG_PRINT("tpc->mcfg=%d. Discard hw PHY config.\n",
1199                           tpc->mcfg);
1200         }
1201 }
1202
1203 DRIVER ( "r8169/PCI", nic_driver, pci_driver, r8169_driver,
1204          r8169_probe, r8169_disable );