2 This software is available to you under a choice of one of two
3 licenses. You may choose to be licensed under the terms of the GNU
4 General Public License (GPL) Version 2, available at
5 <http://www.fsf.org/copyleft/gpl.html>, or the OpenIB.org BSD
6 license, available in the LICENSE.TXT file accompanying this
7 software. These details are also available at
8 <http://openib.org/license.html>.
10 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
19 Copyright (c) 2004 Mellanox Technologies Ltd. All rights reserved.
23 *** This file was generated at "Tue Nov 22 15:21:23 2005"
25 *** % csp_bf -copyright=/mswg/misc/license-header.txt -prefix arbelprm_ -bits -fixnames MT25218_PRM.csp
28 #ifndef H_prefix_arbelprm_bits_fixnames_MT25218_PRM_csp_H
29 #define H_prefix_arbelprm_bits_fixnames_MT25218_PRM_csp_H
34 /* UD Address Vector */
36 struct arbelprm_ud_address_vector_st { /* Little Endian */
37 pseudo_bit_t pd[0x00018]; /* Protection Domain */
38 pseudo_bit_t port_number[0x00002]; /* Port number
42 pseudo_bit_t reserved0[0x00006];
44 pseudo_bit_t rlid[0x00010]; /* Remote (Destination) LID */
45 pseudo_bit_t my_lid_path_bits[0x00007];/* Source LID - the lower 7 bits (upper bits are taken from PortInfo) */
46 pseudo_bit_t g[0x00001]; /* Global address enable - if set, GRH will be formed for packet header */
47 pseudo_bit_t reserved1[0x00008];
49 pseudo_bit_t hop_limit[0x00008]; /* IPv6 hop limit */
50 pseudo_bit_t max_stat_rate[0x00003];/* Maximum static rate control.
55 pseudo_bit_t reserved2[0x00001];
56 pseudo_bit_t msg[0x00002]; /* Max Message size, size is 256*2^MSG bytes */
57 pseudo_bit_t reserved3[0x00002];
58 pseudo_bit_t mgid_index[0x00006]; /* Index to port GID table
59 mgid_index = (port_number-1) * 2^log_max_gid + gid_index
61 1. log_max_gid is taken from QUERY_DEV_LIM command
62 2. gid_index is the index to the GID table */
63 pseudo_bit_t reserved4[0x0000a];
65 pseudo_bit_t flow_label[0x00014]; /* IPv6 flow label */
66 pseudo_bit_t tclass[0x00008]; /* IPv6 TClass */
67 pseudo_bit_t sl[0x00004]; /* InfiniBand Service Level (SL) */
69 pseudo_bit_t rgid_127_96[0x00020]; /* Remote GID[127:96] */
71 pseudo_bit_t rgid_95_64[0x00020]; /* Remote GID[95:64] */
73 pseudo_bit_t rgid_63_32[0x00020]; /* Remote GID[63:32] */
75 pseudo_bit_t rgid_31_0[0x00020]; /* Remote GID[31:0] if G bit is set. Must be set to 0x2 if G bit is cleared. */
81 struct arbelprm_send_doorbell_st { /* Little Endian */
82 pseudo_bit_t nopcode[0x00005]; /* Opcode of descriptor to be executed */
83 pseudo_bit_t f[0x00001]; /* Fence bit. If set, descriptor is fenced */
84 pseudo_bit_t reserved0[0x00002];
85 pseudo_bit_t wqe_counter[0x00010]; /* Modulo-64K counter of WQEs posted to the QP since its creation excluding the newly posted WQEs in this doorbell. Should be zero for the first doorbell on the QP */
86 pseudo_bit_t wqe_cnt[0x00008]; /* Number of WQEs posted with this doorbell. Must be grater then zero. */
88 pseudo_bit_t nds[0x00006]; /* Next descriptor size (in 16-byte chunks) */
89 pseudo_bit_t reserved1[0x00002];
90 pseudo_bit_t qpn[0x00018]; /* QP number this doorbell is rung on */
94 /* ACCESS_LAM_inject_errors_input_modifier */
96 struct arbelprm_access_lam_inject_errors_input_modifier_st { /* Little Endian */
97 pseudo_bit_t index3[0x00007];
98 pseudo_bit_t q3[0x00001];
99 pseudo_bit_t index2[0x00007];
100 pseudo_bit_t q2[0x00001];
101 pseudo_bit_t index1[0x00007];
102 pseudo_bit_t q1[0x00001];
103 pseudo_bit_t index0[0x00007];
104 pseudo_bit_t q0[0x00001];
108 /* ACCESS_LAM_inject_errors_input_parameter */
110 struct arbelprm_access_lam_inject_errors_input_parameter_st { /* Little Endian */
111 pseudo_bit_t ba[0x00002]; /* Bank Address */
112 pseudo_bit_t da[0x00002]; /* Dimm Address */
113 pseudo_bit_t reserved0[0x0001c];
115 pseudo_bit_t ra[0x00010]; /* Row Address */
116 pseudo_bit_t ca[0x00010]; /* Column Address */
122 struct arbelprm_recv_wqe_segment_next_st { /* Little Endian */
123 pseudo_bit_t reserved0[0x00006];
124 pseudo_bit_t nda_31_6[0x0001a]; /* Next WQE address, low 32 bit. WQE address must be aligned to 64-byte boundary (6 LSB are forced ZERO). */
126 pseudo_bit_t nds[0x00006]; /* Next WQE size in OctoWords (16 bytes).
127 Zero value in NDS field signals end of WQEs? chain.
129 pseudo_bit_t reserved1[0x0001a];
133 /* Send wqe segment data inline */
135 struct arbelprm_wqe_segment_data_inline_st { /* Little Endian */
136 pseudo_bit_t byte_count[0x0000a]; /* Not including padding for 16Byte chunks */
137 pseudo_bit_t reserved0[0x00015];
138 pseudo_bit_t always1[0x00001];
140 pseudo_bit_t data[0x00018]; /* Data may be more this segment size - in 16Byte chunks */
141 pseudo_bit_t reserved1[0x00008];
143 pseudo_bit_t reserved2[0x00040];
147 /* Send wqe segment data ptr */
149 struct arbelprm_wqe_segment_data_ptr_st { /* Little Endian */
150 pseudo_bit_t byte_count[0x0001f];
151 pseudo_bit_t always0[0x00001];
153 pseudo_bit_t l_key[0x00020];
155 pseudo_bit_t local_address_h[0x00020];
157 pseudo_bit_t local_address_l[0x00020];
161 /* Send wqe segment rd */
163 struct arbelprm_local_invalidate_segment_st { /* Little Endian */
164 pseudo_bit_t reserved0[0x00040];
166 pseudo_bit_t mem_key[0x00018];
167 pseudo_bit_t reserved1[0x00008];
169 pseudo_bit_t reserved2[0x000a0];
173 /* Fast_Registration_Segment */
175 struct arbelprm_fast_registration_segment_st { /* Little Endian */
176 pseudo_bit_t reserved0[0x0001b];
177 pseudo_bit_t lr[0x00001]; /* If set - Local Read access will be enabled */
178 pseudo_bit_t lw[0x00001]; /* If set - Local Write access will be enabled */
179 pseudo_bit_t rr[0x00001]; /* If set - Remote Read access will be enabled */
180 pseudo_bit_t rw[0x00001]; /* If set - Remote Write access will be enabled */
181 pseudo_bit_t a[0x00001]; /* If set - Remote Atomic access will be enabled */
183 pseudo_bit_t pbl_ptr_63_32[0x00020];/* Physical address pointer [63:32] to the physical buffer list */
185 pseudo_bit_t mem_key[0x00020]; /* Memory Key on which the fast registration is executed on. */
187 pseudo_bit_t page_size[0x00005]; /* Page size used for the region. Actual size is [4K]*2^Page_size bytes.
188 page_size should be less than 20. */
189 pseudo_bit_t reserved1[0x00002];
190 pseudo_bit_t zb[0x00001]; /* Zero Based Region */
191 pseudo_bit_t pbl_ptr_31_8[0x00018]; /* Physical address pointer [31:8] to the physical buffer list */
193 pseudo_bit_t start_address_h[0x00020];/* Start Address[63:32] - Virtual Address where this region starts */
195 pseudo_bit_t start_address_l[0x00020];/* Start Address[31:0] - Virtual Address where this region starts */
197 pseudo_bit_t reg_len_h[0x00020]; /* Region Length[63:32] */
199 pseudo_bit_t reg_len_l[0x00020]; /* Region Length[31:0] */
203 /* Send wqe segment atomic */
205 struct arbelprm_wqe_segment_atomic_st { /* Little Endian */
206 pseudo_bit_t swap_add_h[0x00020];
208 pseudo_bit_t swap_add_l[0x00020];
210 pseudo_bit_t compare_h[0x00020];
212 pseudo_bit_t compare_l[0x00020];
216 /* Send wqe segment remote address */
218 struct arbelprm_wqe_segment_remote_address_st { /* Little Endian */
219 pseudo_bit_t remote_virt_addr_h[0x00020];
221 pseudo_bit_t remote_virt_addr_l[0x00020];
223 pseudo_bit_t rkey[0x00020];
225 pseudo_bit_t reserved0[0x00020];
229 /* end wqe segment bind */
231 struct arbelprm_wqe_segment_bind_st { /* Little Endian */
232 pseudo_bit_t reserved0[0x0001d];
233 pseudo_bit_t rr[0x00001]; /* If set, Remote Read Enable for bound window. */
234 pseudo_bit_t rw[0x00001]; /* If set, Remote Write Enable for bound window.
236 pseudo_bit_t a[0x00001]; /* If set, Atomic Enable for bound window. */
238 pseudo_bit_t reserved1[0x0001e];
239 pseudo_bit_t zb[0x00001]; /* If set, Window is Zero Based. */
240 pseudo_bit_t type[0x00001]; /* Window type.
245 pseudo_bit_t new_rkey[0x00020]; /* The new RKey of window to bind */
247 pseudo_bit_t region_lkey[0x00020]; /* Local key of region, which window will be bound to */
249 pseudo_bit_t start_address_h[0x00020];
251 pseudo_bit_t start_address_l[0x00020];
253 pseudo_bit_t length_h[0x00020];
255 pseudo_bit_t length_l[0x00020];
259 /* Send wqe segment ud */
261 struct arbelprm_wqe_segment_ud_st { /* Little Endian */
262 struct arbelprm_ud_address_vector_st ud_address_vector;/* UD Address Vector */
264 pseudo_bit_t destination_qp[0x00018];
265 pseudo_bit_t reserved0[0x00008];
267 pseudo_bit_t q_key[0x00020];
269 pseudo_bit_t reserved1[0x00040];
273 /* Send wqe segment rd */
275 struct arbelprm_wqe_segment_rd_st { /* Little Endian */
276 pseudo_bit_t destination_qp[0x00018];
277 pseudo_bit_t reserved0[0x00008];
279 pseudo_bit_t q_key[0x00020];
281 pseudo_bit_t reserved1[0x00040];
285 /* Send wqe segment ctrl */
287 struct arbelprm_wqe_segment_ctrl_send_st { /* Little Endian */
288 pseudo_bit_t always1[0x00001];
289 pseudo_bit_t s[0x00001]; /* Solicited Event bit. If set, SE (Solicited Event) bit is set in the (last packet of) message. */
290 pseudo_bit_t e[0x00001]; /* Event bit. If set, event is generated upon WQE?s completion, if QP is allowed to generate an event. Every WQE with E-bit set generates an event. The C bit must be set on unsignalled QPs if the E bit is set. */
291 pseudo_bit_t c[0x00001]; /* Completion Queue bit. Valid for unsignalled QPs only. If set, the CQ is updated upon WQE?s completion */
292 pseudo_bit_t ip[0x00001]; /* When set, InfiniHost III Ex will calculate the IP checksum of the IP header that is present immediately after the IPoverIB encapsulation header. In the case of multiple headers (encapsulation), InfiniHost III Ex will calculate the checksum only for the first IP header following the IPoverIB encapsulation header. Not Valid for IPv6 packets */
293 pseudo_bit_t tcp_udp[0x00001]; /* When set, InfiniHost III Ex will calculate the TCP/UDP checksum of the packet that is present immediately after the IP header. In the case of multiple headers (encapsulation), InfiniHost III Ex will calculate the checksum only for the first TCP header following the IP header. This bit may be set only if the entire TCP/UDP segment is present in one IB packet */
294 pseudo_bit_t reserved0[0x00001];
295 pseudo_bit_t so[0x00001]; /* Strong Ordering - when set, the WQE will be executed only after all previous WQEs have been executed. Can be set for RC WQEs only. This bit must be set in type two BIND, Fast Registration and Local invalidate operations. */
296 pseudo_bit_t reserved1[0x00018];
298 pseudo_bit_t immediate[0x00020]; /* If the OpCode encodes an operation with Immediate (RDMA-write/SEND), This field will hold the Immediate data to be sent. If the OpCode encodes send and invalidate operations, this field holds the Invalidation key to be inserted into the packet; otherwise, this field is reserved. */
302 /* Send wqe segment next */
304 struct arbelprm_wqe_segment_next_st { /* Little Endian */
305 pseudo_bit_t nopcode[0x00005]; /* Next Opcode: OpCode to be used in the next WQE. Encodes the type of operation to be executed on the QP:
306 ?00000? - NOP. WQE with this opcode creates a completion, but does nothing else
308 ?01001? - RDMA-Write with Immediate
310 ?10001? - Atomic Compare & swap
311 ?10010? - Atomic Fetch & Add
312 ?11000? - Bind memory window
314 The encoding for the following operations depends on the QP type:
315 For RC, UC and RD QP:
317 ?01011? - SEND with Immediate
320 the encoding depends on the values of bit[31] of the Q_key field in the Datagram Segment (see Table 39, ?Unreliable Datagram Segment Format - Pointers,? on page 101) of
321 both the current WQE and the next WQE, as follows:
323 If the last WQE Q_Key bit[31] is clear and the next WQE Q_key bit[31] is set :
325 ?01001? - SEND with Immediate
327 otherwise (if the next WQE Q_key bit[31] is cleared, or the last WQE Q_Key bit[31] is set):
329 ?01011? - SEND with Immediate
331 All other opcode values are RESERVED, and will result in invalid operation execution. */
332 pseudo_bit_t reserved0[0x00001];
333 pseudo_bit_t nda_31_6[0x0001a]; /* Next WQE address, low 32 bit. WQE address must be aligned to 64-byte boundary (6 LSB are forced ZERO). */
335 pseudo_bit_t nds[0x00006]; /* Next WQE size in OctoWords (16 bytes).
336 Zero value in NDS field signals end of WQEs? chain.
338 pseudo_bit_t f[0x00001]; /* Fence bit. If set, next WQE will start execution only after all previous Read/Atomic WQEs complete. */
339 pseudo_bit_t always1[0x00001];
340 pseudo_bit_t reserved1[0x00018];
346 struct arbelprm_address_path_st { /* Little Endian */
347 pseudo_bit_t pkey_index[0x00007]; /* PKey table index */
348 pseudo_bit_t reserved0[0x00011];
349 pseudo_bit_t port_number[0x00002]; /* Specific port associated with this QP/EE.
353 pseudo_bit_t reserved1[0x00006];
355 pseudo_bit_t rlid[0x00010]; /* Remote (Destination) LID */
356 pseudo_bit_t my_lid_path_bits[0x00007];/* Source LID - the lower 7 bits (upper bits are taken from PortInfo) */
357 pseudo_bit_t g[0x00001]; /* Global address enable - if set, GRH will be formed for packet header */
358 pseudo_bit_t reserved2[0x00005];
359 pseudo_bit_t rnr_retry[0x00003]; /* RNR retry count (see C9-132 in IB spec Vol 1)
360 0-6 - number of retries
363 pseudo_bit_t hop_limit[0x00008]; /* IPv6 hop limit */
364 pseudo_bit_t max_stat_rate[0x00003];/* Maximum static rate control.
365 0 - 100% injection rate
366 1 - 25% injection rate
367 2 - 12.5% injection rate
368 3 - 50% injection rate
370 pseudo_bit_t reserved3[0x00005];
371 pseudo_bit_t mgid_index[0x00006]; /* Index to port GID table */
372 pseudo_bit_t reserved4[0x00005];
373 pseudo_bit_t ack_timeout[0x00005]; /* Local ACK timeout - Transport timer for activation of retransmission mechanism. Refer to IB spec Vol1 9.7.6.1.3 for further details.
374 The transport timer is set to 4.096us*2^ack_timeout, if ack_timeout is 0 then transport timer is disabled. */
376 pseudo_bit_t flow_label[0x00014]; /* IPv6 flow label */
377 pseudo_bit_t tclass[0x00008]; /* IPv6 TClass */
378 pseudo_bit_t sl[0x00004]; /* InfiniBand Service Level (SL) */
380 pseudo_bit_t rgid_127_96[0x00020]; /* Remote GID[127:96] */
382 pseudo_bit_t rgid_95_64[0x00020]; /* Remote GID[95:64] */
384 pseudo_bit_t rgid_63_32[0x00020]; /* Remote GID[63:32] */
386 pseudo_bit_t rgid_31_0[0x00020]; /* Remote GID[31:0] */
390 /* HCA Command Register (HCR) */
392 struct arbelprm_hca_command_register_st { /* Little Endian */
393 pseudo_bit_t in_param_h[0x00020]; /* Input Parameter: parameter[63:32] or pointer[63:32] to input mailbox (see command description) */
395 pseudo_bit_t in_param_l[0x00020]; /* Input Parameter: parameter[31:0] or pointer[31:0] to input mailbox (see command description) */
397 pseudo_bit_t input_modifier[0x00020];/* Input Parameter Modifier */
399 pseudo_bit_t out_param_h[0x00020]; /* Output Parameter: parameter[63:32] or pointer[63:32] to output mailbox (see command description) */
401 pseudo_bit_t out_param_l[0x00020]; /* Output Parameter: parameter[31:0] or pointer[31:0] to output mailbox (see command description) */
403 pseudo_bit_t reserved0[0x00010];
404 pseudo_bit_t token[0x00010]; /* Software assigned token to the command, to uniquely identify it. The token is returned to the software in the EQE reported. */
406 pseudo_bit_t opcode[0x0000c]; /* Command opcode */
407 pseudo_bit_t opcode_modifier[0x00004];/* Opcode Modifier, see specific description for each command. */
408 pseudo_bit_t reserved1[0x00006];
409 pseudo_bit_t e[0x00001]; /* Event Request
410 0 - Don't report event (software will poll the GO bit)
411 1 - Report event to EQ when the command completes */
412 pseudo_bit_t go[0x00001]; /* Go (0=Software ownership for the HCR, 1=Hardware ownership for the HCR)
413 Software can write to the HCR only if Go bit is cleared.
414 Software must set the Go bit to trigger the HW to execute the command. Software must not write to this register value other than 1 for the Go bit. */
415 pseudo_bit_t status[0x00008]; /* Command execution status report. Valid only if command interface in under SW ownership (Go bit is cleared)
416 0 - command completed without error. If different than zero, command execution completed with error. Syndrom encoding is depended on command executed and is defined for each command */
422 struct arbelprm_cq_cmd_doorbell_st { /* Little Endian */
423 pseudo_bit_t cqn[0x00018]; /* CQ number accessed */
424 pseudo_bit_t cmd[0x00003]; /* Command to be executed on CQ
426 0x1 - Request notification for next Solicited completion event. CQ_param specifies the current CQ Consumer Counter.
427 0x2 - Request notification for next Solicited or Unsolicited completion event. CQ_param specifies the current CQ Consumer Counter.
428 0x3 - Request notification for multiple completions (Arm-N). CQ_param specifies the value of the CQ Counter that when reached by HW (i.e. HW generates a CQE into this Counter) Event will be generated
430 pseudo_bit_t reserved0[0x00001];
431 pseudo_bit_t cmd_sn[0x00002]; /* Command Sequence Number - This field should be incremented upon receiving completion notification of the respective CQ.
432 This transition is done by ringing Request notification for next Solicited, Request notification for next Solicited or Unsolicited
433 completion or Request notification for multiple completions doorbells after receiving completion notification.
434 This field is initialized to Zero */
435 pseudo_bit_t reserved1[0x00002];
437 pseudo_bit_t cq_param[0x00020]; /* parameter to be used by CQ command */
441 /* RD-send doorbell */
443 struct arbelprm_rd_send_doorbell_st { /* Little Endian */
444 pseudo_bit_t reserved0[0x00008];
445 pseudo_bit_t een[0x00018]; /* End-to-end context number (reliable datagram)
446 Must be zero for Nop and Bind operations */
448 pseudo_bit_t reserved1[0x00008];
449 pseudo_bit_t qpn[0x00018]; /* QP number this doorbell is rung on */
451 struct arbelprm_send_doorbell_st send_doorbell;/* Send Parameters */
455 /* Multicast Group Member QP */
457 struct arbelprm_mgmqp_st { /* Little Endian */
458 pseudo_bit_t qpn_i[0x00018]; /* QPN_i: QP number which is a member in this multicast group. Valid only if Qi bit is set. Length of the QPN_i list is set in INIT_HCA */
459 pseudo_bit_t reserved0[0x00007];
460 pseudo_bit_t qi[0x00001]; /* Qi: QPN_i is valid */
466 struct arbelprm_vsd_st { /* Little Endian */
467 pseudo_bit_t vsd_dw0[0x00020];
469 pseudo_bit_t vsd_dw1[0x00020];
471 pseudo_bit_t vsd_dw2[0x00020];
473 pseudo_bit_t vsd_dw3[0x00020];
475 pseudo_bit_t vsd_dw4[0x00020];
477 pseudo_bit_t vsd_dw5[0x00020];
479 pseudo_bit_t vsd_dw6[0x00020];
481 pseudo_bit_t vsd_dw7[0x00020];
483 pseudo_bit_t vsd_dw8[0x00020];
485 pseudo_bit_t vsd_dw9[0x00020];
487 pseudo_bit_t vsd_dw10[0x00020];
489 pseudo_bit_t vsd_dw11[0x00020];
491 pseudo_bit_t vsd_dw12[0x00020];
493 pseudo_bit_t vsd_dw13[0x00020];
495 pseudo_bit_t vsd_dw14[0x00020];
497 pseudo_bit_t vsd_dw15[0x00020];
499 pseudo_bit_t vsd_dw16[0x00020];
501 pseudo_bit_t vsd_dw17[0x00020];
503 pseudo_bit_t vsd_dw18[0x00020];
505 pseudo_bit_t vsd_dw19[0x00020];
507 pseudo_bit_t vsd_dw20[0x00020];
509 pseudo_bit_t vsd_dw21[0x00020];
511 pseudo_bit_t vsd_dw22[0x00020];
513 pseudo_bit_t vsd_dw23[0x00020];
515 pseudo_bit_t vsd_dw24[0x00020];
517 pseudo_bit_t vsd_dw25[0x00020];
519 pseudo_bit_t vsd_dw26[0x00020];
521 pseudo_bit_t vsd_dw27[0x00020];
523 pseudo_bit_t vsd_dw28[0x00020];
525 pseudo_bit_t vsd_dw29[0x00020];
527 pseudo_bit_t vsd_dw30[0x00020];
529 pseudo_bit_t vsd_dw31[0x00020];
531 pseudo_bit_t vsd_dw32[0x00020];
533 pseudo_bit_t vsd_dw33[0x00020];
535 pseudo_bit_t vsd_dw34[0x00020];
537 pseudo_bit_t vsd_dw35[0x00020];
539 pseudo_bit_t vsd_dw36[0x00020];
541 pseudo_bit_t vsd_dw37[0x00020];
543 pseudo_bit_t vsd_dw38[0x00020];
545 pseudo_bit_t vsd_dw39[0x00020];
547 pseudo_bit_t vsd_dw40[0x00020];
549 pseudo_bit_t vsd_dw41[0x00020];
551 pseudo_bit_t vsd_dw42[0x00020];
553 pseudo_bit_t vsd_dw43[0x00020];
555 pseudo_bit_t vsd_dw44[0x00020];
557 pseudo_bit_t vsd_dw45[0x00020];
559 pseudo_bit_t vsd_dw46[0x00020];
561 pseudo_bit_t vsd_dw47[0x00020];
563 pseudo_bit_t vsd_dw48[0x00020];
565 pseudo_bit_t vsd_dw49[0x00020];
567 pseudo_bit_t vsd_dw50[0x00020];
569 pseudo_bit_t vsd_dw51[0x00020];
571 pseudo_bit_t vsd_dw52[0x00020];
573 pseudo_bit_t vsd_dw53[0x00020];
575 pseudo_bit_t vsd_dw54[0x00020];
577 pseudo_bit_t vsd_dw55[0x00020];
581 /* ACCESS_LAM_inject_errors */
583 struct arbelprm_access_lam_inject_errors_st { /* Little Endian */
584 struct arbelprm_access_lam_inject_errors_input_parameter_st access_lam_inject_errors_input_parameter;
586 struct arbelprm_access_lam_inject_errors_input_modifier_st access_lam_inject_errors_input_modifier;
588 pseudo_bit_t reserved0[0x00020];
592 /* Logical DIMM Information */
594 struct arbelprm_dimminfo_st { /* Little Endian */
595 pseudo_bit_t dimmsize[0x00010]; /* Size of DIMM in units of 2^20 Bytes. This value is valid only when DIMMStatus is 0. */
596 pseudo_bit_t reserved0[0x00008];
597 pseudo_bit_t dimmstatus[0x00001]; /* DIMM Status
601 pseudo_bit_t dh[0x00001]; /* When set, the DIMM is Hidden and can not be accessed from the PCI bus. */
602 pseudo_bit_t wo[0x00001]; /* When set, the DIMM is write only.
603 If data integrity is configured (other than none), the DIMM must be
604 only targeted by write transactions where the address and size are multiples of 16 bytes. */
605 pseudo_bit_t reserved1[0x00005];
607 pseudo_bit_t spd[0x00001]; /* 0 - DIMM SPD was read from DIMM
608 1 - DIMM SPD was read from InfiniHost-III-EX NVMEM */
609 pseudo_bit_t sladr[0x00003]; /* SPD Slave Address 3 LSBits.
610 Valid only if spd bit is 0. */
611 pseudo_bit_t sock_num[0x00002]; /* DIMM socket number (for double sided DIMM one of the two numbers will be reported) */
612 pseudo_bit_t syn[0x00004]; /* Error syndrome (valid regardless of status value)
613 0 - DIMM has no error
614 1 - SPD error (e.g. checksum error, no response, error while reading)
615 2 - DIMM out of bounds (e.g. DIMM rows number is not between 7 and 14, DIMM type is not 2)
616 3 - DIMM conflict (e.g. mix of registered and unbuffered DIMMs, CAS latency conflict)
617 5 - DIMM size trimmed due to configuration (size exceeds)
618 other - Error, reserved
620 pseudo_bit_t reserved2[0x00016];
622 pseudo_bit_t reserved3[0x00040];
624 pseudo_bit_t dimm_start_adr_h[0x00020];/* DIMM memory start address [63:32]. This value is valid only when DIMMStatus is 0. */
626 pseudo_bit_t dimm_start_adr_l[0x00020];/* DIMM memory start address [31:0]. This value is valid only when DIMMStatus is 0. */
628 pseudo_bit_t reserved4[0x00040];
634 struct arbelprm_uar_params_st { /* Little Endian */
635 pseudo_bit_t uar_base_addr_h[0x00020];/* UAR Base (pyhsical) Address [63:32] (QUERY_HCA only) */
637 pseudo_bit_t reserved0[0x00014];
638 pseudo_bit_t uar_base_addr_l[0x0000c];/* UAR Base (pyhsical) Address [31:20] (QUERY_HCA only) */
640 pseudo_bit_t uar_page_sz[0x00008]; /* This field defines the size of each UAR page.
641 Size of UAR Page is 4KB*2^UAR_Page_Size */
642 pseudo_bit_t log_max_uars[0x00004]; /* Number of UARs supported is 2^log_max_UARs */
643 pseudo_bit_t reserved1[0x00004];
644 pseudo_bit_t log_uar_entry_sz[0x00006];/* Size of UAR Context entry is 2^log_uar_sz in 4KByte pages */
645 pseudo_bit_t reserved2[0x0000a];
647 pseudo_bit_t reserved3[0x00020];
649 pseudo_bit_t uar_scratch_base_addr_h[0x00020];/* Base address of UAR scratchpad [63:32].
650 Number of entries in table is 2^log_max_uars.
651 Table must be aligned to its size */
653 pseudo_bit_t uar_scratch_base_addr_l[0x00020];/* Base address of UAR scratchpad [31:0].
654 Number of entries in table is 2^log_max_uars.
655 Table must be aligned to its size. */
657 pseudo_bit_t uar_context_base_addr_h[0x00020];/* Base address of UAR Context [63:32].
658 Number of entries in table is 2^log_max_uars.
659 Table must be aligned to its size. */
661 pseudo_bit_t uar_context_base_addr_l[0x00020];/* Base address of UAR Context [31:0].
662 Number of entries in table is 2^log_max_uars.
663 Table must be aligned to its size. */
667 /* Translation and Protection Tables Parameters */
669 struct arbelprm_tptparams_st { /* Little Endian */
670 pseudo_bit_t mpt_base_adr_h[0x00020];/* MPT - Memory Protection Table base physical address [63:32].
671 Entry size is 64 bytes.
672 Table must be aligned to its size.
673 Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */
675 pseudo_bit_t mpt_base_adr_l[0x00020];/* MPT - Memory Protection Table base physical address [31:0].
676 Entry size is 64 bytes.
677 Table must be aligned to its size.
678 Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */
680 pseudo_bit_t log_mpt_sz[0x00006]; /* Log (base 2) of the number of region/windows entries in the MPT table. */
681 pseudo_bit_t reserved0[0x00002];
682 pseudo_bit_t pfto[0x00005]; /* Page Fault RNR Timeout -
683 The field returned in RNR Naks generated when a page fault is detected.
684 It has no effect when on-demand-paging is not used. */
685 pseudo_bit_t reserved1[0x00013];
687 pseudo_bit_t reserved2[0x00020];
689 pseudo_bit_t mtt_base_addr_h[0x00020];/* MTT - Memory Translation table base physical address [63:32].
690 Table must be aligned to its size.
691 Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */
693 pseudo_bit_t mtt_base_addr_l[0x00020];/* MTT - Memory Translation table base physical address [31:0].
694 Table must be aligned to its size.
695 Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */
697 pseudo_bit_t reserved3[0x00040];
701 /* Multicast Support Parameters */
703 struct arbelprm_multicastparam_st { /* Little Endian */
704 pseudo_bit_t mc_base_addr_h[0x00020];/* Base Address of the Multicast Table [63:32].
705 The base address must be aligned to the entry size.
706 Address may be set to 0xFFFFFFFF if multicast is not supported. */
708 pseudo_bit_t mc_base_addr_l[0x00020];/* Base Address of the Multicast Table [31:0].
709 The base address must be aligned to the entry size.
710 Address may be set to 0xFFFFFFFF if multicast is not supported. */
712 pseudo_bit_t reserved0[0x00040];
714 pseudo_bit_t log_mc_table_entry_sz[0x00010];/* Log2 of the Size of multicast group member (MGM) entry.
715 Must be greater than 5 (to allow CTRL and GID sections).
716 That implies the number of QPs per MC table entry. */
717 pseudo_bit_t reserved1[0x00010];
719 pseudo_bit_t mc_table_hash_sz[0x00011];/* Number of entries in multicast DGID hash table (must be power of 2)
720 INIT_HCA - the required number of entries
721 QUERY_HCA - the actual number of entries assigned by firmware (will be less than or equal to the amount required in INIT_HCA) */
722 pseudo_bit_t reserved2[0x0000f];
724 pseudo_bit_t log_mc_table_sz[0x00005];/* Log2 of the overall number of MC entries in the MCG table (includes both hash and auxiliary tables) */
725 pseudo_bit_t reserved3[0x00013];
726 pseudo_bit_t mc_hash_fn[0x00003]; /* Multicast hash function
727 0 - Default hash function
729 pseudo_bit_t reserved4[0x00005];
731 pseudo_bit_t reserved5[0x00020];
735 /* QPC/EEC/CQC/EQC/RDB Parameters */
737 struct arbelprm_qpcbaseaddr_st { /* Little Endian */
738 pseudo_bit_t reserved0[0x00080];
740 pseudo_bit_t qpc_base_addr_h[0x00020];/* QPC Base Address [63:32]
741 Table must be aligned on its size */
743 pseudo_bit_t log_num_of_qp[0x00005];/* Log base 2 of number of supported QPs */
744 pseudo_bit_t reserved1[0x00002];
745 pseudo_bit_t qpc_base_addr_l[0x00019];/* QPC Base Address [31:7]
746 Table must be aligned on its size */
748 pseudo_bit_t reserved2[0x00040];
750 pseudo_bit_t eec_base_addr_h[0x00020];/* EEC Base Address [63:32]
751 Table must be aligned on its size.
752 Address may be set to 0xFFFFFFFF if RD is not supported. */
754 pseudo_bit_t log_num_of_ee[0x00005];/* Log base 2 of number of supported EEs. */
755 pseudo_bit_t reserved3[0x00002];
756 pseudo_bit_t eec_base_addr_l[0x00019];/* EEC Base Address [31:7]
757 Table must be aligned on its size
758 Address may be set to 0xFFFFFFFF if RD is not supported. */
760 pseudo_bit_t srqc_base_addr_h[0x00020];/* SRQ Context Base Address [63:32]
761 Table must be aligned on its size
762 Address may be set to 0xFFFFFFFF if SRQ is not supported. */
764 pseudo_bit_t log_num_of_srq[0x00005];/* Log base 2 of number of supported SRQs. */
765 pseudo_bit_t srqc_base_addr_l[0x0001b];/* SRQ Context Base Address [31:5]
766 Table must be aligned on its size
767 Address may be set to 0xFFFFFFFF if SRQ is not supported. */
769 pseudo_bit_t cqc_base_addr_h[0x00020];/* CQC Base Address [63:32]
770 Table must be aligned on its size */
772 pseudo_bit_t log_num_of_cq[0x00005];/* Log base 2 of number of supported CQs. */
773 pseudo_bit_t reserved4[0x00001];
774 pseudo_bit_t cqc_base_addr_l[0x0001a];/* CQC Base Address [31:6]
775 Table must be aligned on its size */
777 pseudo_bit_t reserved5[0x00040];
779 pseudo_bit_t eqpc_base_addr_h[0x00020];/* Extended QPC Base Address [63:32]
780 Table has same number of entries as QPC table.
781 Table must be aligned to entry size. */
783 pseudo_bit_t eqpc_base_addr_l[0x00020];/* Extended QPC Base Address [31:0]
784 Table has same number of entries as QPC table.
785 Table must be aligned to entry size. */
787 pseudo_bit_t reserved6[0x00040];
789 pseudo_bit_t eeec_base_addr_h[0x00020];/* Extended EEC Base Address [63:32]
790 Table has same number of entries as EEC table.
791 Table must be aligned to entry size.
792 Address may be set to 0xFFFFFFFF if RD is not supported. */
794 pseudo_bit_t eeec_base_addr_l[0x00020];/* Extended EEC Base Address [31:0]
795 Table has same number of entries as EEC table.
796 Table must be aligned to entry size.
797 Address may be set to 0xFFFFFFFF if RD is not supported. */
799 pseudo_bit_t reserved7[0x00040];
801 pseudo_bit_t eqc_base_addr_h[0x00020];/* EQC Base Address [63:32]
802 Address may be set to 0xFFFFFFFF if EQs are not supported.
803 Table must be aligned to entry size. */
805 pseudo_bit_t log_num_eq[0x00004]; /* Log base 2 of number of supported EQs.
806 Must be 6 or less in InfiniHost-III-EX. */
807 pseudo_bit_t reserved8[0x00002];
808 pseudo_bit_t eqc_base_addr_l[0x0001a];/* EQC Base Address [31:6]
809 Address may be set to 0xFFFFFFFF if EQs are not supported.
810 Table must be aligned to entry size. */
812 pseudo_bit_t reserved9[0x00040];
814 pseudo_bit_t rdb_base_addr_h[0x00020];/* Base address of table that holds remote read and remote atomic requests [63:32].
815 Address may be set to 0xFFFFFFFF if remote RDMA reads are not supported.
816 Please refer to QP and EE chapter for further explanation on RDB allocation. */
818 pseudo_bit_t rdb_base_addr_l[0x00020];/* Base address of table that holds remote read and remote atomic requests [31:0].
819 Table must be aligned to RDB entry size (32 bytes).
820 Address may be set to zero if remote RDMA reads are not supported.
821 Please refer to QP and EE chapter for further explanation on RDB allocation. */
823 pseudo_bit_t reserved10[0x00040];
827 /* Header_Log_Register */
829 struct arbelprm_header_log_register_st { /* Little Endian */
830 pseudo_bit_t place_holder[0x00020];
832 pseudo_bit_t reserved0[0x00060];
836 /* Performance Monitors */
838 struct arbelprm_performance_monitors_st { /* Little Endian */
839 pseudo_bit_t e0[0x00001]; /* Enables counting of respective performance counter */
840 pseudo_bit_t e1[0x00001]; /* Enables counting of respective performance counter */
841 pseudo_bit_t e2[0x00001]; /* Enables counting of respective performance counter */
842 pseudo_bit_t reserved0[0x00001];
843 pseudo_bit_t r0[0x00001]; /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */
844 pseudo_bit_t r1[0x00001]; /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */
845 pseudo_bit_t r2[0x00001]; /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */
846 pseudo_bit_t reserved1[0x00001];
847 pseudo_bit_t i0[0x00001]; /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */
848 pseudo_bit_t i1[0x00001]; /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */
849 pseudo_bit_t i2[0x00001]; /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */
850 pseudo_bit_t reserved2[0x00001];
851 pseudo_bit_t f0[0x00001]; /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */
852 pseudo_bit_t f1[0x00001]; /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */
853 pseudo_bit_t f2[0x00001]; /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */
854 pseudo_bit_t reserved3[0x00001];
855 pseudo_bit_t ev_cnt1[0x00005]; /* Specifies event to be counted by Event_counter1 See XXX for events' definition. */
856 pseudo_bit_t reserved4[0x00003];
857 pseudo_bit_t ev_cnt2[0x00005]; /* Specifies event to be counted by Event_counter2 See XXX for events' definition. */
858 pseudo_bit_t reserved5[0x00003];
860 pseudo_bit_t clock_counter[0x00020];
862 pseudo_bit_t event_counter1[0x00020];
864 pseudo_bit_t event_counter2[0x00020];/* Read/write event counter, counting events specified by EvCntl and EvCnt2 fields repsectively. When the event counter reaches is maximum value of 0xFFFFFF, the next event will cause it to roll over to zero, set F1 or F2 bit respectively and generate interrupt by I1 I2 bit respectively. */
868 /* Receive segment format */
870 struct arbelprm_wqe_segment_ctrl_recv_st { /* Little Endian */
871 struct arbelprm_recv_wqe_segment_next_st wqe_segment_next;
873 pseudo_bit_t reserved0[0x00002];
874 pseudo_bit_t reserved1[0x00001];
875 pseudo_bit_t reserved2[0x00001];
876 pseudo_bit_t reserved3[0x0001c];
878 pseudo_bit_t reserved4[0x00020];
882 /* MLX WQE segment format */
884 struct arbelprm_wqe_segment_ctrl_mlx_st { /* Little Endian */
885 pseudo_bit_t reserved0[0x00002];
886 pseudo_bit_t e[0x00001]; /* WQE event */
887 pseudo_bit_t c[0x00001]; /* Create CQE (for "requested signalling" QP) */
888 pseudo_bit_t icrc[0x00002]; /* icrc field detemines what to do with the last dword of the packet: 0 - Calculate ICRC and put it instead of last dword. Last dword must be 0x0. 1,2 - reserved. 3 - Leave last dword as is. Last dword must not be 0x0. */
889 pseudo_bit_t reserved1[0x00002];
890 pseudo_bit_t sl[0x00004];
891 pseudo_bit_t max_statrate[0x00004];
892 pseudo_bit_t slr[0x00001]; /* 0= take slid from port. 1= take slid from given headers */
893 pseudo_bit_t v15[0x00001]; /* Send packet over VL15 */
894 pseudo_bit_t reserved2[0x0000e];
896 pseudo_bit_t vcrc[0x00010]; /* Packet's VCRC (if not 0 - otherwise computed by HW) */
897 pseudo_bit_t rlid[0x00010]; /* Destination LID (must match given headers) */
899 pseudo_bit_t reserved3[0x00040];
903 /* Send WQE segment format */
905 struct arbelprm_send_wqe_segment_st { /* Little Endian */
906 struct arbelprm_wqe_segment_next_st wqe_segment_next;/* Send wqe segment next */
908 struct arbelprm_wqe_segment_ctrl_send_st wqe_segment_ctrl_send;/* Send wqe segment ctrl */
910 struct arbelprm_wqe_segment_rd_st wqe_segment_rd;/* Send wqe segment rd */
912 struct arbelprm_wqe_segment_ud_st wqe_segment_ud;/* Send wqe segment ud */
914 struct arbelprm_wqe_segment_bind_st wqe_segment_bind;/* Send wqe segment bind */
916 pseudo_bit_t reserved0[0x00180];
918 struct arbelprm_wqe_segment_remote_address_st wqe_segment_remote_address;/* Send wqe segment remote address */
920 struct arbelprm_wqe_segment_atomic_st wqe_segment_atomic;/* Send wqe segment atomic */
922 struct arbelprm_fast_registration_segment_st fast_registration_segment;/* Fast Registration Segment */
924 struct arbelprm_local_invalidate_segment_st local_invalidate_segment;/* local invalidate segment */
926 struct arbelprm_wqe_segment_data_ptr_st wqe_segment_data_ptr;/* Send wqe segment data ptr */
928 struct arbelprm_wqe_segment_data_inline_st wqe_segment_data_inline;/* Send wqe segment data inline */
930 pseudo_bit_t reserved1[0x00200];
934 /* QP and EE Context Entry */
936 struct arbelprm_queue_pair_ee_context_entry_st { /* Little Endian */
937 pseudo_bit_t reserved0[0x00008];
938 pseudo_bit_t de[0x00001]; /* Send/Receive Descriptor Event enable - if set, events can be generated upon descriptors' completion on send/receive queue (controlled by E bit in WQE). Invalid in EE context */
939 pseudo_bit_t reserved1[0x00002];
940 pseudo_bit_t pm_state[0x00002]; /* Path migration state (Migrated, Armed or Rearm)
945 Should be set to 11 for UD QPs and for QPs which do not support APM */
946 pseudo_bit_t reserved2[0x00003];
947 pseudo_bit_t st[0x00003]; /* Service type (invalid in EE context):
948 000-Reliable Connection
949 001-Unreliable Connection
950 010-Reliable Datagram
951 011-Unreliable Datagram
952 111-MLX transport (raw bits injection). Used for management QPs and RAW */
953 pseudo_bit_t reserved3[0x00009];
954 pseudo_bit_t state[0x00004]; /* QP/EE state:
960 5 - SQD (Send Queue Drained)
962 7 - Send Queue Draining
966 (Valid for QUERY_QPEE and ERR2RST_QPEE commands only) */
968 pseudo_bit_t reserved4[0x00020];
970 pseudo_bit_t sched_queue[0x00004]; /* Schedule queue to be used for WQE scheduling to execution. Determines QOS for this QP. */
971 pseudo_bit_t rlky[0x00001]; /* When set this QP can use the Reserved L_Key */
972 pseudo_bit_t reserved5[0x00003];
973 pseudo_bit_t log_sq_stride[0x00003];/* Stride on the send queue. WQ entry is 16*(2^log_SQ_stride) bytes.
974 Stride must be equal or bigger then 64 bytes (minimum log_RQ_stride value allowed is 2). */
975 pseudo_bit_t log_sq_size[0x00004]; /* Log2 of the Number of WQEs in the Send Queue. */
976 pseudo_bit_t reserved6[0x00001];
977 pseudo_bit_t log_rq_stride[0x00003];/* Stride on the receive queue. WQ entry is 16*(2^log_RQ_stride) bytes.
978 Stride must be equal or bigger then 64 bytes (minimum log_RQ_stride value allowed is 2). */
979 pseudo_bit_t log_rq_size[0x00004]; /* Log2 of the Number of WQEs in the Receive Queue. */
980 pseudo_bit_t reserved7[0x00001];
981 pseudo_bit_t msg_max[0x00005]; /* Max message size allowed on the QP. Maximum message size is 2^msg_Max.
982 Must be equal to MTU for UD and MLX QPs. */
983 pseudo_bit_t mtu[0x00003]; /* MTU of the QP (Must be the same for both paths: primary and alternative):
990 Should be configured to 0x4 for UD and MLX QPs. */
992 pseudo_bit_t usr_page[0x00018]; /* QP (see "non_privileged Access to the HCA Hardware"). Not valid (reserved) in EE context. */
993 pseudo_bit_t reserved8[0x00008];
995 pseudo_bit_t local_qpn_een[0x00018];/* Local QP/EE number Lower bits determine position of this record in QPC table, and - thus - constrained
996 This field is valid for QUERY and ERR2RST commands only. */
997 pseudo_bit_t reserved9[0x00008];
999 pseudo_bit_t remote_qpn_een[0x00018];/* Remote QP/EE number */
1000 pseudo_bit_t reserved10[0x00008];
1001 /* -------------- */
1002 pseudo_bit_t reserved11[0x00040];
1003 /* -------------- */
1004 struct arbelprm_address_path_st primary_address_path;/* Primary address path for the QP/EE */
1005 /* -------------- */
1006 struct arbelprm_address_path_st alternative_address_path;/* Alternate address path for the QP/EE */
1007 /* -------------- */
1008 pseudo_bit_t rdd[0x00018]; /* Reliable Datagram Domain */
1009 pseudo_bit_t reserved12[0x00008];
1010 /* -------------- */
1011 pseudo_bit_t pd[0x00018]; /* QP protection domain. Not valid (reserved) in EE context. */
1012 pseudo_bit_t reserved13[0x00008];
1013 /* -------------- */
1014 pseudo_bit_t wqe_base_adr_h[0x00020];/* Bits 63:32 of WQE address for both SQ and RQ.
1015 Reserved for EE context. */
1016 /* -------------- */
1017 pseudo_bit_t wqe_lkey[0x00020]; /* memory key (L-Key) to be used to access WQEs. Not valid (reserved) in EE context. */
1018 /* -------------- */
1019 pseudo_bit_t reserved14[0x00003];
1020 pseudo_bit_t ssc[0x00001]; /* Send Signaled Completion
1021 1 - all send WQEs generate CQEs.
1022 0 - only send WQEs with C bit set generate completion.
1023 Not valid (reserved) in EE context. */
1024 pseudo_bit_t sic[0x00001]; /* If set - Ignore end to end credits on send queue. Not valid (reserved) in EE context. */
1025 pseudo_bit_t cur_retry_cnt[0x00003];/* Current transport retry counter (QUERY_QPEE only).
1026 The current transport retry counter can vary from retry_count down to 1, where 1 means that the last retry attempt is currently executing. */
1027 pseudo_bit_t cur_rnr_retry[0x00003];/* Current RNR retry counter (QUERY_QPEE only).
1028 The current RNR retry counter can vary from rnr_retry to 1, where 1 means that the last retry attempt is currently executing. */
1029 pseudo_bit_t fre[0x00001]; /* Fast Registration Work Request Enabled. (Reserved for EE) */
1030 pseudo_bit_t reserved15[0x00001];
1031 pseudo_bit_t sae[0x00001]; /* If set - Atomic operations enabled on send queue. Not valid (reserved) in EE context. */
1032 pseudo_bit_t swe[0x00001]; /* If set - RDMA - write enabled on send queue. Not valid (reserved) in EE context. */
1033 pseudo_bit_t sre[0x00001]; /* If set - RDMA - read enabled on send queue. Not valid (reserved) in EE context. */
1034 pseudo_bit_t retry_count[0x00003]; /* Transport timeout Retry count */
1035 pseudo_bit_t reserved16[0x00002];
1036 pseudo_bit_t sra_max[0x00003]; /* Maximum number of outstanding RDMA-read/Atomic operations allowed in the send queue. Maximum number is 2^SRA_Max. Must be zero in EE context. */
1037 pseudo_bit_t flight_lim[0x00004]; /* Number of outstanding (in-flight) messages on the wire allowed for this send queue.
1038 Number of outstanding messages is 2^Flight_Lim.
1039 Use 0xF for unlimited number of outstanding messages. */
1040 pseudo_bit_t ack_req_freq[0x00004]; /* ACK required frequency. ACK required bit will be set in every 2^AckReqFreq packets at least. Not valid for RD QP. */
1041 /* -------------- */
1042 pseudo_bit_t reserved17[0x00020];
1043 /* -------------- */
1044 pseudo_bit_t next_send_psn[0x00018];/* Next PSN to be sent */
1045 pseudo_bit_t reserved18[0x00008];
1046 /* -------------- */
1047 pseudo_bit_t cqn_snd[0x00018]; /* CQ number completions from the send queue to be reported to. Not valid (reserved) in EE context. */
1048 pseudo_bit_t reserved19[0x00008];
1049 /* -------------- */
1050 pseudo_bit_t reserved20[0x00006];
1051 pseudo_bit_t snd_wqe_base_adr_l[0x0001a];/* While opening (creating) the WQ, this field should contain the address of first descriptor to be posted. Not valid (reserved) in EE context. */
1052 /* -------------- */
1053 pseudo_bit_t snd_db_record_index[0x00020];/* Index in the UAR Context Table Entry.
1054 HW uses this index as an offset from the UAR Context Table Entry in order to read this SQ doorbell record.
1055 The entry is obtained via the usr_page field.
1056 Not valid for EE. */
1057 /* -------------- */
1058 pseudo_bit_t last_acked_psn[0x00018];/* The last acknowledged PSN for the requester (QUERY_QPEE only) */
1059 pseudo_bit_t reserved21[0x00008];
1060 /* -------------- */
1061 pseudo_bit_t ssn[0x00018]; /* Requester Send Sequence Number (QUERY_QPEE only) */
1062 pseudo_bit_t reserved22[0x00008];
1063 /* -------------- */
1064 pseudo_bit_t reserved23[0x00003];
1065 pseudo_bit_t rsc[0x00001]; /* 1 - all receive WQEs generate CQEs.
1066 0 - only receive WQEs with C bit set generate completion.
1067 Not valid (reserved) in EE context.
1069 pseudo_bit_t ric[0x00001]; /* Invalid Credits.
1070 1 - place "Invalid Credits" to ACKs sent from this queue.
1071 0 - ACKs report the actual number of end to end credits on the connection.
1072 Not valid (reserved) in EE context.
1073 Must be set to 1 on QPs which are attached to SRQ. */
1074 pseudo_bit_t reserved24[0x00008];
1075 pseudo_bit_t rae[0x00001]; /* If set - Atomic operations enabled. on receive queue. Not valid (reserved) in EE context. */
1076 pseudo_bit_t rwe[0x00001]; /* If set - RDMA - write enabled on receive queue. Not valid (reserved) in EE context. */
1077 pseudo_bit_t rre[0x00001]; /* If set - RDMA - read enabled on receive queue. Not valid (reserved) in EE context. */
1078 pseudo_bit_t reserved25[0x00005];
1079 pseudo_bit_t rra_max[0x00003]; /* Maximum number of outstanding RDMA-read/Atomic operations allowed on receive queue is 2^RRA_Max.
1080 Must be 0 for EE context. */
1081 pseudo_bit_t reserved26[0x00008];
1082 /* -------------- */
1083 pseudo_bit_t next_rcv_psn[0x00018]; /* Next (expected) PSN on receive */
1084 pseudo_bit_t min_rnr_nak[0x00005]; /* Minimum RNR NAK timer value (TTTTT field encoding according to the IB spec Vol1 9.7.5.2.8).
1085 Not valid (reserved) in EE context. */
1086 pseudo_bit_t reserved27[0x00003];
1087 /* -------------- */
1088 pseudo_bit_t reserved28[0x00005];
1089 pseudo_bit_t ra_buff_indx[0x0001b]; /* Index to outstanding read/atomic buffer.
1090 This field constructs the address to the RDB for maintaining the incoming RDMA read and atomic requests. */
1091 /* -------------- */
1092 pseudo_bit_t cqn_rcv[0x00018]; /* CQ number completions from receive queue to be reported to. Not valid (reserved) in EE context. */
1093 pseudo_bit_t reserved29[0x00008];
1094 /* -------------- */
1095 pseudo_bit_t reserved30[0x00006];
1096 pseudo_bit_t rcv_wqe_base_adr_l[0x0001a];/* While opening (creating) the WQ, this field should contain the address of first descriptor to be posted. Not valid (reserved) in EE context. */
1097 /* -------------- */
1098 pseudo_bit_t rcv_db_record_index[0x00020];/* Index in the UAR Context Table Entry containing the doorbell record for the receive queue.
1099 HW uses this index as an offset from the UAR Context Table Entry in order to read this RQ doorbell record.
1100 The entry is obtained via the usr_page field.
1101 Not valid for EE. */
1102 /* -------------- */
1103 pseudo_bit_t q_key[0x00020]; /* Q_Key to be validated against received datagrams.
1104 On send datagrams, if Q_Key[31] specified in the WQE is set, then this Q_Key will be transmitted in the outgoing message.
1105 Not valid (reserved) in EE context. */
1106 /* -------------- */
1107 pseudo_bit_t srqn[0x00018]; /* SRQN - Shared Receive Queue Number - specifies the SRQ number from which the QP dequeues receive descriptors.
1108 SRQN is valid only if SRQ bit is set. Not valid (reserved) in EE context. */
1109 pseudo_bit_t srq[0x00001]; /* SRQ - Shared Receive Queue. If this bit is set, then the QP is associated with a SRQ. Not valid (reserved) in EE context. */
1110 pseudo_bit_t reserved31[0x00007];
1111 /* -------------- */
1112 pseudo_bit_t rmsn[0x00018]; /* Responder current message sequence number (QUERY_QPEE only) */
1113 pseudo_bit_t reserved32[0x00008];
1114 /* -------------- */
1115 pseudo_bit_t sq_wqe_counter[0x00010];/* A 16bits counter that is incremented for each WQE posted to the SQ.
1116 Must be 0x0 in SQ initialization.
1117 (QUERY_QPEE only). */
1118 pseudo_bit_t rq_wqe_counter[0x00010];/* A 16bits counter that is incremented for each WQE posted to the RQ.
1119 Must be 0x0 in RQ initialization.
1120 (QUERY_QPEE only). */
1121 /* -------------- */
1122 pseudo_bit_t reserved33[0x00040];
1123 /* -------------- */
1126 /* Clear Interrupt [63:0] */
1128 struct arbelprm_clr_int_st { /* Little Endian */
1129 pseudo_bit_t clr_int_h[0x00020]; /* Clear Interrupt [63:32]
1130 Write transactions to this register will clear (de-assert) the virtual interrupt output pins of InfiniHost-III-EX. The value to be written in this register is obtained by executing QUERY_ADAPTER command on command interface after system boot.
1131 This register is write-only. Reading from this register will cause undefined result
1133 /* -------------- */
1134 pseudo_bit_t clr_int_l[0x00020]; /* Clear Interrupt [31:0]
1135 Write transactions to this register will clear (de-assert) the virtual interrupt output pins of InfiniHost-III-EX. The value to be written in this register is obtained by executing QUERY_ADAPTER command on command interface after system boot.
1136 This register is write-only. Reading from this register will cause undefined result */
1137 /* -------------- */
1140 /* EQ_Arm_DB_Region */
1142 struct arbelprm_eq_arm_db_region_st { /* Little Endian */
1143 pseudo_bit_t eq_x_arm_h[0x00020]; /* EQ[63:32] X state.
1144 This register is used to Arm EQs when setting the appropriate bits. */
1145 /* -------------- */
1146 pseudo_bit_t eq_x_arm_l[0x00020]; /* EQ[31:0] X state.
1147 This register is used to Arm EQs when setting the appropriate bits. */
1148 /* -------------- */
1151 /* EQ Set CI DBs Table */
1153 struct arbelprm_eq_set_ci_table_st { /* Little Endian */
1154 pseudo_bit_t eq0_set_ci[0x00020]; /* EQ0_Set_CI */
1155 /* -------------- */
1156 pseudo_bit_t reserved0[0x00020];
1157 /* -------------- */
1158 pseudo_bit_t eq1_set_ci[0x00020]; /* EQ1_Set_CI */
1159 /* -------------- */
1160 pseudo_bit_t reserved1[0x00020];
1161 /* -------------- */
1162 pseudo_bit_t eq2_set_ci[0x00020]; /* EQ2_Set_CI */
1163 /* -------------- */
1164 pseudo_bit_t reserved2[0x00020];
1165 /* -------------- */
1166 pseudo_bit_t eq3_set_ci[0x00020]; /* EQ3_Set_CI */
1167 /* -------------- */
1168 pseudo_bit_t reserved3[0x00020];
1169 /* -------------- */
1170 pseudo_bit_t eq4_set_ci[0x00020]; /* EQ4_Set_CI */
1171 /* -------------- */
1172 pseudo_bit_t reserved4[0x00020];
1173 /* -------------- */
1174 pseudo_bit_t eq5_set_ci[0x00020]; /* EQ5_Set_CI */
1175 /* -------------- */
1176 pseudo_bit_t reserved5[0x00020];
1177 /* -------------- */
1178 pseudo_bit_t eq6_set_ci[0x00020]; /* EQ6_Set_CI */
1179 /* -------------- */
1180 pseudo_bit_t reserved6[0x00020];
1181 /* -------------- */
1182 pseudo_bit_t eq7_set_ci[0x00020]; /* EQ7_Set_CI */
1183 /* -------------- */
1184 pseudo_bit_t reserved7[0x00020];
1185 /* -------------- */
1186 pseudo_bit_t eq8_set_ci[0x00020]; /* EQ8_Set_CI */
1187 /* -------------- */
1188 pseudo_bit_t reserved8[0x00020];
1189 /* -------------- */
1190 pseudo_bit_t eq9_set_ci[0x00020]; /* EQ9_Set_CI */
1191 /* -------------- */
1192 pseudo_bit_t reserved9[0x00020];
1193 /* -------------- */
1194 pseudo_bit_t eq10_set_ci[0x00020]; /* EQ10_Set_CI */
1195 /* -------------- */
1196 pseudo_bit_t reserved10[0x00020];
1197 /* -------------- */
1198 pseudo_bit_t eq11_set_ci[0x00020]; /* EQ11_Set_CI */
1199 /* -------------- */
1200 pseudo_bit_t reserved11[0x00020];
1201 /* -------------- */
1202 pseudo_bit_t eq12_set_ci[0x00020]; /* EQ12_Set_CI */
1203 /* -------------- */
1204 pseudo_bit_t reserved12[0x00020];
1205 /* -------------- */
1206 pseudo_bit_t eq13_set_ci[0x00020]; /* EQ13_Set_CI */
1207 /* -------------- */
1208 pseudo_bit_t reserved13[0x00020];
1209 /* -------------- */
1210 pseudo_bit_t eq14_set_ci[0x00020]; /* EQ14_Set_CI */
1211 /* -------------- */
1212 pseudo_bit_t reserved14[0x00020];
1213 /* -------------- */
1214 pseudo_bit_t eq15_set_ci[0x00020]; /* EQ15_Set_CI */
1215 /* -------------- */
1216 pseudo_bit_t reserved15[0x00020];
1217 /* -------------- */
1218 pseudo_bit_t eq16_set_ci[0x00020]; /* EQ16_Set_CI */
1219 /* -------------- */
1220 pseudo_bit_t reserved16[0x00020];
1221 /* -------------- */
1222 pseudo_bit_t eq17_set_ci[0x00020]; /* EQ17_Set_CI */
1223 /* -------------- */
1224 pseudo_bit_t reserved17[0x00020];
1225 /* -------------- */
1226 pseudo_bit_t eq18_set_ci[0x00020]; /* EQ18_Set_CI */
1227 /* -------------- */
1228 pseudo_bit_t reserved18[0x00020];
1229 /* -------------- */
1230 pseudo_bit_t eq19_set_ci[0x00020]; /* EQ19_Set_CI */
1231 /* -------------- */
1232 pseudo_bit_t reserved19[0x00020];
1233 /* -------------- */
1234 pseudo_bit_t eq20_set_ci[0x00020]; /* EQ20_Set_CI */
1235 /* -------------- */
1236 pseudo_bit_t reserved20[0x00020];
1237 /* -------------- */
1238 pseudo_bit_t eq21_set_ci[0x00020]; /* EQ21_Set_CI */
1239 /* -------------- */
1240 pseudo_bit_t reserved21[0x00020];
1241 /* -------------- */
1242 pseudo_bit_t eq22_set_ci[0x00020]; /* EQ22_Set_CI */
1243 /* -------------- */
1244 pseudo_bit_t reserved22[0x00020];
1245 /* -------------- */
1246 pseudo_bit_t eq23_set_ci[0x00020]; /* EQ23_Set_CI */
1247 /* -------------- */
1248 pseudo_bit_t reserved23[0x00020];
1249 /* -------------- */
1250 pseudo_bit_t eq24_set_ci[0x00020]; /* EQ24_Set_CI */
1251 /* -------------- */
1252 pseudo_bit_t reserved24[0x00020];
1253 /* -------------- */
1254 pseudo_bit_t eq25_set_ci[0x00020]; /* EQ25_Set_CI */
1255 /* -------------- */
1256 pseudo_bit_t reserved25[0x00020];
1257 /* -------------- */
1258 pseudo_bit_t eq26_set_ci[0x00020]; /* EQ26_Set_CI */
1259 /* -------------- */
1260 pseudo_bit_t reserved26[0x00020];
1261 /* -------------- */
1262 pseudo_bit_t eq27_set_ci[0x00020]; /* EQ27_Set_CI */
1263 /* -------------- */
1264 pseudo_bit_t reserved27[0x00020];
1265 /* -------------- */
1266 pseudo_bit_t eq28_set_ci[0x00020]; /* EQ28_Set_CI */
1267 /* -------------- */
1268 pseudo_bit_t reserved28[0x00020];
1269 /* -------------- */
1270 pseudo_bit_t eq29_set_ci[0x00020]; /* EQ29_Set_CI */
1271 /* -------------- */
1272 pseudo_bit_t reserved29[0x00020];
1273 /* -------------- */
1274 pseudo_bit_t eq30_set_ci[0x00020]; /* EQ30_Set_CI */
1275 /* -------------- */
1276 pseudo_bit_t reserved30[0x00020];
1277 /* -------------- */
1278 pseudo_bit_t eq31_set_ci[0x00020]; /* EQ31_Set_CI */
1279 /* -------------- */
1280 pseudo_bit_t reserved31[0x00020];
1281 /* -------------- */
1282 pseudo_bit_t eq32_set_ci[0x00020]; /* EQ32_Set_CI */
1283 /* -------------- */
1284 pseudo_bit_t reserved32[0x00020];
1285 /* -------------- */
1286 pseudo_bit_t eq33_set_ci[0x00020]; /* EQ33_Set_CI */
1287 /* -------------- */
1288 pseudo_bit_t reserved33[0x00020];
1289 /* -------------- */
1290 pseudo_bit_t eq34_set_ci[0x00020]; /* EQ34_Set_CI */
1291 /* -------------- */
1292 pseudo_bit_t reserved34[0x00020];
1293 /* -------------- */
1294 pseudo_bit_t eq35_set_ci[0x00020]; /* EQ35_Set_CI */
1295 /* -------------- */
1296 pseudo_bit_t reserved35[0x00020];
1297 /* -------------- */
1298 pseudo_bit_t eq36_set_ci[0x00020]; /* EQ36_Set_CI */
1299 /* -------------- */
1300 pseudo_bit_t reserved36[0x00020];
1301 /* -------------- */
1302 pseudo_bit_t eq37_set_ci[0x00020]; /* EQ37_Set_CI */
1303 /* -------------- */
1304 pseudo_bit_t reserved37[0x00020];
1305 /* -------------- */
1306 pseudo_bit_t eq38_set_ci[0x00020]; /* EQ38_Set_CI */
1307 /* -------------- */
1308 pseudo_bit_t reserved38[0x00020];
1309 /* -------------- */
1310 pseudo_bit_t eq39_set_ci[0x00020]; /* EQ39_Set_CI */
1311 /* -------------- */
1312 pseudo_bit_t reserved39[0x00020];
1313 /* -------------- */
1314 pseudo_bit_t eq40_set_ci[0x00020]; /* EQ40_Set_CI */
1315 /* -------------- */
1316 pseudo_bit_t reserved40[0x00020];
1317 /* -------------- */
1318 pseudo_bit_t eq41_set_ci[0x00020]; /* EQ41_Set_CI */
1319 /* -------------- */
1320 pseudo_bit_t reserved41[0x00020];
1321 /* -------------- */
1322 pseudo_bit_t eq42_set_ci[0x00020]; /* EQ42_Set_CI */
1323 /* -------------- */
1324 pseudo_bit_t reserved42[0x00020];
1325 /* -------------- */
1326 pseudo_bit_t eq43_set_ci[0x00020]; /* EQ43_Set_CI */
1327 /* -------------- */
1328 pseudo_bit_t reserved43[0x00020];
1329 /* -------------- */
1330 pseudo_bit_t eq44_set_ci[0x00020]; /* EQ44_Set_CI */
1331 /* -------------- */
1332 pseudo_bit_t reserved44[0x00020];
1333 /* -------------- */
1334 pseudo_bit_t eq45_set_ci[0x00020]; /* EQ45_Set_CI */
1335 /* -------------- */
1336 pseudo_bit_t reserved45[0x00020];
1337 /* -------------- */
1338 pseudo_bit_t eq46_set_ci[0x00020]; /* EQ46_Set_CI */
1339 /* -------------- */
1340 pseudo_bit_t reserved46[0x00020];
1341 /* -------------- */
1342 pseudo_bit_t eq47_set_ci[0x00020]; /* EQ47_Set_CI */
1343 /* -------------- */
1344 pseudo_bit_t reserved47[0x00020];
1345 /* -------------- */
1346 pseudo_bit_t eq48_set_ci[0x00020]; /* EQ48_Set_CI */
1347 /* -------------- */
1348 pseudo_bit_t reserved48[0x00020];
1349 /* -------------- */
1350 pseudo_bit_t eq49_set_ci[0x00020]; /* EQ49_Set_CI */
1351 /* -------------- */
1352 pseudo_bit_t reserved49[0x00020];
1353 /* -------------- */
1354 pseudo_bit_t eq50_set_ci[0x00020]; /* EQ50_Set_CI */
1355 /* -------------- */
1356 pseudo_bit_t reserved50[0x00020];
1357 /* -------------- */
1358 pseudo_bit_t eq51_set_ci[0x00020]; /* EQ51_Set_CI */
1359 /* -------------- */
1360 pseudo_bit_t reserved51[0x00020];
1361 /* -------------- */
1362 pseudo_bit_t eq52_set_ci[0x00020]; /* EQ52_Set_CI */
1363 /* -------------- */
1364 pseudo_bit_t reserved52[0x00020];
1365 /* -------------- */
1366 pseudo_bit_t eq53_set_ci[0x00020]; /* EQ53_Set_CI */
1367 /* -------------- */
1368 pseudo_bit_t reserved53[0x00020];
1369 /* -------------- */
1370 pseudo_bit_t eq54_set_ci[0x00020]; /* EQ54_Set_CI */
1371 /* -------------- */
1372 pseudo_bit_t reserved54[0x00020];
1373 /* -------------- */
1374 pseudo_bit_t eq55_set_ci[0x00020]; /* EQ55_Set_CI */
1375 /* -------------- */
1376 pseudo_bit_t reserved55[0x00020];
1377 /* -------------- */
1378 pseudo_bit_t eq56_set_ci[0x00020]; /* EQ56_Set_CI */
1379 /* -------------- */
1380 pseudo_bit_t reserved56[0x00020];
1381 /* -------------- */
1382 pseudo_bit_t eq57_set_ci[0x00020]; /* EQ57_Set_CI */
1383 /* -------------- */
1384 pseudo_bit_t reserved57[0x00020];
1385 /* -------------- */
1386 pseudo_bit_t eq58_set_ci[0x00020]; /* EQ58_Set_CI */
1387 /* -------------- */
1388 pseudo_bit_t reserved58[0x00020];
1389 /* -------------- */
1390 pseudo_bit_t eq59_set_ci[0x00020]; /* EQ59_Set_CI */
1391 /* -------------- */
1392 pseudo_bit_t reserved59[0x00020];
1393 /* -------------- */
1394 pseudo_bit_t eq60_set_ci[0x00020]; /* EQ60_Set_CI */
1395 /* -------------- */
1396 pseudo_bit_t reserved60[0x00020];
1397 /* -------------- */
1398 pseudo_bit_t eq61_set_ci[0x00020]; /* EQ61_Set_CI */
1399 /* -------------- */
1400 pseudo_bit_t reserved61[0x00020];
1401 /* -------------- */
1402 pseudo_bit_t eq62_set_ci[0x00020]; /* EQ62_Set_CI */
1403 /* -------------- */
1404 pseudo_bit_t reserved62[0x00020];
1405 /* -------------- */
1406 pseudo_bit_t eq63_set_ci[0x00020]; /* EQ63_Set_CI */
1407 /* -------------- */
1408 pseudo_bit_t reserved63[0x00020];
1409 /* -------------- */
1412 /* InfiniHost-III-EX Configuration Registers */
1414 struct arbelprm_configuration_registers_st { /* Little Endian */
1415 pseudo_bit_t reserved0[0x403400];
1416 /* -------------- */
1417 struct arbelprm_hca_command_register_st hca_command_interface_register;/* HCA Command Register */
1418 /* -------------- */
1419 pseudo_bit_t reserved1[0x3fcb20];
1420 /* -------------- */
1425 struct arbelprm_qp_db_record_st { /* Little Endian */
1426 pseudo_bit_t counter[0x00010]; /* Modulo-64K counter of WQEs posted to the QP since its creation. Should be initialized to zero. */
1427 pseudo_bit_t reserved0[0x00010];
1428 /* -------------- */
1429 pseudo_bit_t reserved1[0x00005];
1430 pseudo_bit_t res[0x00003]; /* 0x3 for SQ
1433 pseudo_bit_t qp_number[0x00018]; /* QP number */
1434 /* -------------- */
1437 /* CQ_ARM_DB_Record */
1439 struct arbelprm_cq_arm_db_record_st { /* Little Endian */
1440 pseudo_bit_t counter[0x00020]; /* CQ counter for the arming request */
1441 /* -------------- */
1442 pseudo_bit_t cmd[0x00003]; /* 0x0 - No command
1443 0x1 - Request notification for next Solicited completion event. Counter filed specifies the current CQ Consumer Counter.
1444 0x2 - Request notification for next Solicited or Unsolicited completion event. Counter filed specifies the current CQ Consumer counter.
1445 0x3 - Request notification for multiple completions (Arm-N). Counter filed specifies the value of the CQ Index that when reached by HW (i.e. HW generates a CQE into this Index) Event will be generated
1447 pseudo_bit_t cmd_sn[0x00002]; /* Command Sequence Number - See Table 35, "CQ Doorbell Layout" for definition of this filed */
1448 pseudo_bit_t res[0x00003]; /* Must be 0x2 */
1449 pseudo_bit_t cq_number[0x00018]; /* CQ number */
1450 /* -------------- */
1453 /* CQ_CI_DB_Record */
1455 struct arbelprm_cq_ci_db_record_st { /* Little Endian */
1456 pseudo_bit_t counter[0x00020]; /* CQ counter */
1457 /* -------------- */
1458 pseudo_bit_t reserved0[0x00005];
1459 pseudo_bit_t res[0x00003]; /* Must be 0x1 */
1460 pseudo_bit_t cq_number[0x00018]; /* CQ number */
1461 /* -------------- */
1464 /* Virtual_Physical_Mapping */
1466 struct arbelprm_virtual_physical_mapping_st { /* Little Endian */
1467 pseudo_bit_t va_h[0x00020]; /* Virtual Address[63:32]. Valid only for MAP_ICM command. */
1468 /* -------------- */
1469 pseudo_bit_t reserved0[0x0000c];
1470 pseudo_bit_t va_l[0x00014]; /* Virtual Address[31:12]. Valid only for MAP_ICM command. */
1471 /* -------------- */
1472 pseudo_bit_t pa_h[0x00020]; /* Physical Address[63:32] */
1473 /* -------------- */
1474 pseudo_bit_t log2size[0x00006]; /* Log2 of the size in 4KB pages of the physical and virtual contiguous memory that starts at PA_L/H and VA_L/H */
1475 pseudo_bit_t reserved1[0x00006];
1476 pseudo_bit_t pa_l[0x00014]; /* Physical Address[31:12] */
1477 /* -------------- */
1482 struct arbelprm_mod_stat_cfg_st { /* Little Endian */
1483 pseudo_bit_t log_max_srqs[0x00005]; /* Log (base 2) of the number of SRQs to allocate (0 if no SRQs are required), valid only if srq bit is set. */
1484 pseudo_bit_t reserved0[0x00001];
1485 pseudo_bit_t srq[0x00001]; /* When set SRQs are supported */
1486 pseudo_bit_t srq_m[0x00001]; /* Modify SRQ parameters */
1487 pseudo_bit_t reserved1[0x00018];
1488 /* -------------- */
1489 pseudo_bit_t reserved2[0x007e0];
1490 /* -------------- */
1495 struct arbelprm_srq_context_st { /* Little Endian */
1496 pseudo_bit_t srqn[0x00018]; /* SRQ number */
1497 pseudo_bit_t log_srq_size[0x00004]; /* Log2 of the Number of WQEs in the Receive Queue.
1498 Maximum value is 0x10, i.e. 16M WQEs. */
1499 pseudo_bit_t state[0x00004]; /* SRQ State:
1503 Valid only on QUERY_SRQ and HW2SW_SRQ commands. */
1504 /* -------------- */
1505 pseudo_bit_t l_key[0x00020]; /* memory key (L-Key) to be used to access WQEs. */
1506 /* -------------- */
1507 pseudo_bit_t srq_db_record_index[0x00020];/* Index in the UAR Context Table Entry containing the doorbell record for the receive queue.
1508 HW uses this index as an offset from the UAR Context Table Entry in order to read this SRQ doorbell record.
1509 The entry is obtained via the usr_page field. */
1510 /* -------------- */
1511 pseudo_bit_t usr_page[0x00018]; /* Index (offset) of user page allocated for this SRQ (see "non_privileged Access to the HCA Hardware"). Not valid (reserved) in EE context. */
1512 pseudo_bit_t reserved0[0x00005];
1513 pseudo_bit_t log_rq_stride[0x00003];/* Stride (max WQE size) on the receive queue. WQ entry is 16*(2^log_RQ_stride) bytes. */
1514 /* -------------- */
1515 pseudo_bit_t wqe_addr_h[0x00020]; /* Bits 63:32 of WQE address (WQE base address) */
1516 /* -------------- */
1517 pseudo_bit_t reserved1[0x00006];
1518 pseudo_bit_t srq_wqe_base_adr_l[0x0001a];/* While opening (creating) the SRQ, this field should contain the address of first descriptor to be posted. */
1519 /* -------------- */
1520 pseudo_bit_t pd[0x00018]; /* SRQ protection domain. */
1521 pseudo_bit_t reserved2[0x00008];
1522 /* -------------- */
1523 pseudo_bit_t wqe_cnt[0x00010]; /* WQE count on the SRQ.
1524 Valid only on QUERY_SRQ and HW2SW_SRQ commands. */
1525 pseudo_bit_t lwm[0x00010]; /* Limit Water Mark - if the LWM is not zero, and the wqe_cnt drops below LWM when a WQE is dequeued from the SRQ, then a SRQ limit event is fired and the LWM is set to zero. */
1526 /* -------------- */
1527 pseudo_bit_t srq_wqe_counter[0x00010];/* A 16bits counter that is incremented for each WQE posted to the SQ.
1528 Must be 0x0 in SRQ initialization.
1529 (QUERY_SRQ only). */
1530 pseudo_bit_t reserved3[0x00010];
1531 /* -------------- */
1532 pseudo_bit_t reserved4[0x00060];
1533 /* -------------- */
1538 struct arbelprm_pbl_st { /* Little Endian */
1539 pseudo_bit_t mtt_0_h[0x00020]; /* First MTT[63:32] */
1540 /* -------------- */
1541 pseudo_bit_t mtt_0_l[0x00020]; /* First MTT[31:0] */
1542 /* -------------- */
1543 pseudo_bit_t mtt_1_h[0x00020]; /* Second MTT[63:32] */
1544 /* -------------- */
1545 pseudo_bit_t mtt_1_l[0x00020]; /* Second MTT[31:0] */
1546 /* -------------- */
1547 pseudo_bit_t mtt_2_h[0x00020]; /* Third MTT[63:32] */
1548 /* -------------- */
1549 pseudo_bit_t mtt_2_l[0x00020]; /* Third MTT[31:0] */
1550 /* -------------- */
1551 pseudo_bit_t mtt_3_h[0x00020]; /* Fourth MTT[63:32] */
1552 /* -------------- */
1553 pseudo_bit_t mtt_3_l[0x00020]; /* Fourth MTT[31:0] */
1554 /* -------------- */
1557 /* Performance Counters */
1559 struct arbelprm_performance_counters_st { /* Little Endian */
1560 pseudo_bit_t sqpc_access_cnt[0x00020];/* SQPC cache access count */
1561 /* -------------- */
1562 pseudo_bit_t sqpc_miss_cnt[0x00020];/* SQPC cache miss count */
1563 /* -------------- */
1564 pseudo_bit_t reserved0[0x00040];
1565 /* -------------- */
1566 pseudo_bit_t rqpc_access_cnt[0x00020];/* RQPC cache access count */
1567 /* -------------- */
1568 pseudo_bit_t rqpc_miss_cnt[0x00020];/* RQPC cache miss count */
1569 /* -------------- */
1570 pseudo_bit_t reserved1[0x00040];
1571 /* -------------- */
1572 pseudo_bit_t cqc_access_cnt[0x00020];/* CQC cache access count */
1573 /* -------------- */
1574 pseudo_bit_t cqc_miss_cnt[0x00020]; /* CQC cache miss count */
1575 /* -------------- */
1576 pseudo_bit_t reserved2[0x00040];
1577 /* -------------- */
1578 pseudo_bit_t tpt_access_cnt[0x00020];/* TPT cache access count */
1579 /* -------------- */
1580 pseudo_bit_t mpt_miss_cnt[0x00020]; /* MPT cache miss count */
1581 /* -------------- */
1582 pseudo_bit_t mtt_miss_cnt[0x00020]; /* MTT cache miss count */
1583 /* -------------- */
1584 pseudo_bit_t reserved3[0x00620];
1585 /* -------------- */
1588 /* Transport and CI Error Counters */
1590 struct arbelprm_transport_and_ci_error_counters_st { /* Little Endian */
1591 pseudo_bit_t rq_num_lle[0x00020]; /* Responder - number of local length errors */
1592 /* -------------- */
1593 pseudo_bit_t sq_num_lle[0x00020]; /* Requester - number of local length errors */
1594 /* -------------- */
1595 pseudo_bit_t rq_num_lqpoe[0x00020]; /* Responder - number local QP operation error */
1596 /* -------------- */
1597 pseudo_bit_t sq_num_lqpoe[0x00020]; /* Requester - number local QP operation error */
1598 /* -------------- */
1599 pseudo_bit_t rq_num_leeoe[0x00020]; /* Responder - number local EE operation error */
1600 /* -------------- */
1601 pseudo_bit_t sq_num_leeoe[0x00020]; /* Requester - number local EE operation error */
1602 /* -------------- */
1603 pseudo_bit_t rq_num_lpe[0x00020]; /* Responder - number of local protection errors */
1604 /* -------------- */
1605 pseudo_bit_t sq_num_lpe[0x00020]; /* Requester - number of local protection errors */
1606 /* -------------- */
1607 pseudo_bit_t rq_num_wrfe[0x00020]; /* Responder - number of CQEs with error.
1608 Incremented each time a CQE with error is generated */
1609 /* -------------- */
1610 pseudo_bit_t sq_num_wrfe[0x00020]; /* Requester - number of CQEs with error.
1611 Incremented each time a CQE with error is generated */
1612 /* -------------- */
1613 pseudo_bit_t reserved0[0x00020];
1614 /* -------------- */
1615 pseudo_bit_t sq_num_mwbe[0x00020]; /* Requester - number of memory window bind errors */
1616 /* -------------- */
1617 pseudo_bit_t reserved1[0x00020];
1618 /* -------------- */
1619 pseudo_bit_t sq_num_bre[0x00020]; /* Requester - number of bad response errors */
1620 /* -------------- */
1621 pseudo_bit_t rq_num_lae[0x00020]; /* Responder - number of local access errors */
1622 /* -------------- */
1623 pseudo_bit_t reserved2[0x00040];
1624 /* -------------- */
1625 pseudo_bit_t sq_num_rire[0x00020]; /* Requester - number of remote invalid request errors
1626 NAK-Invalid Request on:
1627 1. Unsupported OpCode: Responder detected an unsupported OpCode.
1628 2. Unexpected OpCode: Responder detected an error in the sequence of OpCodes, such
1629 as a missing "Last" packet.
1630 Note: there is no PSN error, thus this does not indicate a dropped packet. */
1631 /* -------------- */
1632 pseudo_bit_t rq_num_rire[0x00020]; /* Responder - number of remote invalid request errors.
1633 NAK may or may not be sent.
1634 1. QP Async Affiliated Error: Unsupported or Reserved OpCode (RC,RD only):
1635 Inbound request OpCode was either reserved, or was for a function not supported by this
1636 QP. (E.g. RDMA or ATOMIC on QP not set up for this).
1637 2. Misaligned ATOMIC: VA does not point to an aligned address on an atomic opera-tion.
1638 3. Too many RDMA READ or ATOMIC Requests: There were more requests received
1639 and not ACKed than allowed for the connection.
1640 4. Out of Sequence OpCode, current packet is "First" or "Only": The Responder
1641 detected an error in the sequence of OpCodes; a missing "Last" packet
1642 5. Out of Sequence OpCode, current packet is not "First" or "Only": The Responder
1643 detected an error in the sequence of OpCodes; a missing "First" packet
1644 6. Local Length Error: Inbound "Send" request message exceeded the responder.s avail-able
1646 7. Length error: RDMA WRITE request message contained too much or too little pay-load
1647 data compared to the DMA length advertised in the first or only packet.
1648 8. Length error: Payload length was not consistent with the opcode:
1649 a: 0 byte <= "only" <= PMTU bytes
1650 b: ("first" or "middle") == PMTU bytes
1651 c: 1byte <= "last" <= PMTU bytes
1652 9. Length error: Inbound message exceeded the size supported by the CA port. */
1653 /* -------------- */
1654 pseudo_bit_t sq_num_rae[0x00020]; /* Requester - number of remote access errors.
1655 NAK-Remote Access Error on:
1656 R_Key Violation: Responder detected an invalid R_Key while executing an RDMA
1658 /* -------------- */
1659 pseudo_bit_t rq_num_rae[0x00020]; /* Responder - number of remote access errors.
1660 R_Key Violation Responder detected an R_Key violation while executing an RDMA
1662 NAK may or may not be sent. */
1663 /* -------------- */
1664 pseudo_bit_t sq_num_roe[0x00020]; /* Requester - number of remote operation errors.
1665 NAK-Remote Operation Error on:
1666 Remote Operation Error: Responder encountered an error, (local to the responder),
1667 which prevented it from completing the request. */
1668 /* -------------- */
1669 pseudo_bit_t rq_num_roe[0x00020]; /* Responder - number of remote operation errors.
1670 NAK-Remote Operation Error on:
1671 1. Malformed WQE: Responder detected a malformed Receive Queue WQE while pro-cessing
1673 2. Remote Operation Error: Responder encountered an error, (local to the responder),
1674 which prevented it from completing the request. */
1675 /* -------------- */
1676 pseudo_bit_t sq_num_tree[0x00020]; /* Requester - number of transport retries exceeded errors */
1677 /* -------------- */
1678 pseudo_bit_t reserved3[0x00020];
1679 /* -------------- */
1680 pseudo_bit_t sq_num_rree[0x00020]; /* Requester - number of RNR nak retries exceeded errors */
1681 /* -------------- */
1682 pseudo_bit_t reserved4[0x00020];
1683 /* -------------- */
1684 pseudo_bit_t sq_num_lrdve[0x00020]; /* Requester - number of local RDD violation errors */
1685 /* -------------- */
1686 pseudo_bit_t rq_num_rirdre[0x00020];/* Responder - number of remote invalid RD request errors */
1687 /* -------------- */
1688 pseudo_bit_t reserved5[0x00040];
1689 /* -------------- */
1690 pseudo_bit_t sq_num_rabrte[0x00020];/* Requester - number of remote aborted errors */
1691 /* -------------- */
1692 pseudo_bit_t reserved6[0x00020];
1693 /* -------------- */
1694 pseudo_bit_t sq_num_ieecne[0x00020];/* Requester - number of invalid EE context number errors */
1695 /* -------------- */
1696 pseudo_bit_t reserved7[0x00020];
1697 /* -------------- */
1698 pseudo_bit_t sq_num_ieecse[0x00020];/* Requester - invalid EE context state errors */
1699 /* -------------- */
1700 pseudo_bit_t reserved8[0x00380];
1701 /* -------------- */
1702 pseudo_bit_t rq_num_oos[0x00020]; /* Responder - number of out of sequence requests received */
1703 /* -------------- */
1704 pseudo_bit_t sq_num_oos[0x00020]; /* Requester - number of out of sequence Naks received */
1705 /* -------------- */
1706 pseudo_bit_t rq_num_mce[0x00020]; /* Responder - number of bad multicast packets received */
1707 /* -------------- */
1708 pseudo_bit_t reserved9[0x00020];
1709 /* -------------- */
1710 pseudo_bit_t rq_num_rsync[0x00020]; /* Responder - number of RESYNC operations */
1711 /* -------------- */
1712 pseudo_bit_t sq_num_rsync[0x00020]; /* Requester - number of RESYNC operations */
1713 /* -------------- */
1714 pseudo_bit_t rq_num_udsdprd[0x00020];/* The number of UD packets silently discarded on the receive queue due to lack of receive descriptor. */
1715 /* -------------- */
1716 pseudo_bit_t reserved10[0x00020];
1717 /* -------------- */
1718 pseudo_bit_t rq_num_ucsdprd[0x00020];/* The number of UC packets silently discarded on the receive queue due to lack of receive descriptor. */
1719 /* -------------- */
1720 pseudo_bit_t reserved11[0x003e0];
1721 /* -------------- */
1722 pseudo_bit_t num_cqovf[0x00020]; /* Number of CQ overflows */
1723 /* -------------- */
1724 pseudo_bit_t num_eqovf[0x00020]; /* Number of EQ overflows */
1725 /* -------------- */
1726 pseudo_bit_t num_baddb[0x00020]; /* Number of bad doorbells */
1727 /* -------------- */
1728 pseudo_bit_t reserved12[0x002a0];
1729 /* -------------- */
1732 /* Event_data Field - HCR Completion Event */
1734 struct arbelprm_hcr_completion_event_st { /* Little Endian */
1735 pseudo_bit_t token[0x00010]; /* HCR Token */
1736 pseudo_bit_t reserved0[0x00010];
1737 /* -------------- */
1738 pseudo_bit_t reserved1[0x00020];
1739 /* -------------- */
1740 pseudo_bit_t status[0x00008]; /* HCR Status */
1741 pseudo_bit_t reserved2[0x00018];
1742 /* -------------- */
1743 pseudo_bit_t out_param_h[0x00020]; /* HCR Output Parameter [63:32] */
1744 /* -------------- */
1745 pseudo_bit_t out_param_l[0x00020]; /* HCR Output Parameter [31:0] */
1746 /* -------------- */
1747 pseudo_bit_t reserved3[0x00020];
1748 /* -------------- */
1751 /* Completion with Error CQE */
1753 struct arbelprm_completion_with_error_st { /* Little Endian */
1754 pseudo_bit_t myqpn[0x00018]; /* Indicates the QP for which completion is being reported */
1755 pseudo_bit_t reserved0[0x00008];
1756 /* -------------- */
1757 pseudo_bit_t reserved1[0x00060];
1758 /* -------------- */
1759 pseudo_bit_t reserved2[0x00010];
1760 pseudo_bit_t vendor_code[0x00008];
1761 pseudo_bit_t syndrome[0x00008]; /* Completion with error syndrome:
1762 0x01 - Local Length Error
1763 0x02 - Local QP Operation Error
1764 0x03 - Local EE Context Operation Error
1765 0x04 - Local Protection Error
1766 0x05 - Work Request Flushed Error
1767 0x06 - Memory Window Bind Error
1768 0x10 - Bad Response Error
1769 0x11 - Local Access Error
1770 0x12 - Remote Invalid Request Error
1771 0x13 - Remote Access Error
1772 0x14 - Remote Operation Error
1773 0x15 - Transport Retry Counter Exceeded
1774 0x16 - RNR Retry Counter Exceeded
1775 0x20 - Local RDD Violation Error
1776 0x21 - Remote Invalid RD Request
1777 0x22 - Remote Aborted Error
1778 0x23 - Invalid EE Context Number
1779 0x24 - Invalid EE Context State
1781 Syndrome is defined according to the IB specification volume 1. For detailed explanation of the syndromes, refer to chapters 10-11 of the IB specification rev 1.1. */
1782 /* -------------- */
1783 pseudo_bit_t reserved3[0x00020];
1784 /* -------------- */
1785 pseudo_bit_t reserved4[0x00006];
1786 pseudo_bit_t wqe_addr[0x0001a]; /* Bits 31:6 of WQE virtual address completion is reported for. The 6 least significant bits are zero. */
1787 /* -------------- */
1788 pseudo_bit_t reserved5[0x00007];
1789 pseudo_bit_t owner[0x00001]; /* Owner field. Zero value of this field means SW ownership of CQE. */
1790 pseudo_bit_t reserved6[0x00010];
1791 pseudo_bit_t opcode[0x00008]; /* The opcode of WQE completion is reported for.
1793 The following values are reported in case of completion with error:
1794 0xFE - For completion with error on Receive Queues
1795 0xFF - For completion with error on Send Queues */
1796 /* -------------- */
1799 /* Resize CQ Input Mailbox */
1801 struct arbelprm_resize_cq_st { /* Little Endian */
1802 pseudo_bit_t reserved0[0x00020];
1803 /* -------------- */
1804 pseudo_bit_t start_addr_h[0x00020]; /* Start address of CQ[63:32].
1805 Must be aligned on CQE size (32 bytes) */
1806 /* -------------- */
1807 pseudo_bit_t start_addr_l[0x00020]; /* Start address of CQ[31:0].
1808 Must be aligned on CQE size (32 bytes) */
1809 /* -------------- */
1810 pseudo_bit_t reserved1[0x00018];
1811 pseudo_bit_t log_cq_size[0x00005]; /* Log (base 2) of the CQ size (in entries) */
1812 pseudo_bit_t reserved2[0x00003];
1813 /* -------------- */
1814 pseudo_bit_t reserved3[0x00060];
1815 /* -------------- */
1816 pseudo_bit_t l_key[0x00020]; /* Memory key (L_Key) to be used to access CQ */
1817 /* -------------- */
1818 pseudo_bit_t reserved4[0x00100];
1819 /* -------------- */
1822 /* MAD_IFC Input Modifier */
1824 struct arbelprm_mad_ifc_input_modifier_st { /* Little Endian */
1825 pseudo_bit_t port_number[0x00008]; /* The packet reception port number (1 or 2). */
1826 pseudo_bit_t mad_extended_info[0x00001];/* Mad_Extended_Info valid bit (MAD_IFC Input Mailbox data from offset 00100h and down). MAD_Extended_Info is read only if this bit is set.
1827 Required for trap generation when BKey check is enabled and for global routed packets. */
1828 pseudo_bit_t reserved0[0x00007];
1829 pseudo_bit_t rlid[0x00010]; /* Remote (source) LID from the received MAD.
1830 This field is required for trap generation upon MKey/BKey validation. */
1831 /* -------------- */
1834 /* MAD_IFC Input Mailbox */
1836 struct arbelprm_mad_ifc_st { /* Little Endian */
1837 pseudo_bit_t request_mad_packet[64][0x00020];/* Request MAD Packet (256bytes) */
1838 /* -------------- */
1839 pseudo_bit_t my_qpn[0x00018]; /* Destination QP number from the received MAD.
1840 This field is reserved if Mad_extended_info indication in the input modifier is clear. */
1841 pseudo_bit_t reserved0[0x00008];
1842 /* -------------- */
1843 pseudo_bit_t rqpn[0x00018]; /* Remote (source) QP number from the received MAD.
1844 This field is reserved if Mad_extended_info indication in the input modifier is clear. */
1845 pseudo_bit_t reserved1[0x00008];
1846 /* -------------- */
1847 pseudo_bit_t rlid[0x00010]; /* Remote (source) LID from the received MAD.
1848 This field is reserved if Mad_extended_info indication in the input modifier is clear. */
1849 pseudo_bit_t ml_path[0x00007]; /* My (destination) LID path bits from the received MAD.
1850 This field is reserved if Mad_extended_info indication in the input modifier is clear. */
1851 pseudo_bit_t g[0x00001]; /* If set, the GRH field in valid.
1852 This field is reserved if Mad_extended_info indication in the input modifier is clear. */
1853 pseudo_bit_t reserved2[0x00004];
1854 pseudo_bit_t sl[0x00004]; /* Service Level of the received MAD.
1855 This field is reserved if Mad_extended_info indication in the input modifier is clear. */
1856 /* -------------- */
1857 pseudo_bit_t pkey_indx[0x00010]; /* Index in PKey table that matches PKey of the received MAD.
1858 This field is reserved if Mad_extended_info indication in the input modifier is clear. */
1859 pseudo_bit_t reserved3[0x00010];
1860 /* -------------- */
1861 pseudo_bit_t reserved4[0x00180];
1862 /* -------------- */
1863 pseudo_bit_t grh[10][0x00020]; /* The GRH field of the MAD packet that was scattered to the first 40 bytes pointed to by the scatter list.
1864 Valid if Mad_extended_info bit (in the input modifier) and g bit are set.
1865 Otherwise this field is reserved. */
1866 /* -------------- */
1867 pseudo_bit_t reserved5[0x004c0];
1868 /* -------------- */
1871 /* Query Debug Message */
1873 struct arbelprm_query_debug_msg_st { /* Little Endian */
1874 pseudo_bit_t phy_addr_h[0x00020]; /* Translation of the address in firmware area. High 32 bits. */
1875 /* -------------- */
1876 pseudo_bit_t v[0x00001]; /* Physical translation is valid */
1877 pseudo_bit_t reserved0[0x0000b];
1878 pseudo_bit_t phy_addr_l[0x00014]; /* Translation of the address in firmware area. Low 32 bits. */
1879 /* -------------- */
1880 pseudo_bit_t fw_area_base[0x00020]; /* Firmware area base address. The format strings and the trace buffers may be located starting from this address. */
1881 /* -------------- */
1882 pseudo_bit_t fw_area_size[0x00020]; /* Firmware area size */
1883 /* -------------- */
1884 pseudo_bit_t trc_hdr_sz[0x00020]; /* Trace message header size in dwords. */
1885 /* -------------- */
1886 pseudo_bit_t trc_arg_num[0x00020]; /* The number of arguments per trace message. */
1887 /* -------------- */
1888 pseudo_bit_t reserved1[0x000c0];
1889 /* -------------- */
1890 pseudo_bit_t dbg_msk_h[0x00020]; /* Debug messages mask [63:32] */
1891 /* -------------- */
1892 pseudo_bit_t dbg_msk_l[0x00020]; /* Debug messages mask [31:0] */
1893 /* -------------- */
1894 pseudo_bit_t reserved2[0x00040];
1895 /* -------------- */
1896 pseudo_bit_t buff0_addr[0x00020]; /* Address in firmware area of Trace Buffer 0 */
1897 /* -------------- */
1898 pseudo_bit_t buff0_size[0x00020]; /* Size of Trace Buffer 0 */
1899 /* -------------- */
1900 pseudo_bit_t buff1_addr[0x00020]; /* Address in firmware area of Trace Buffer 1 */
1901 /* -------------- */
1902 pseudo_bit_t buff1_size[0x00020]; /* Size of Trace Buffer 1 */
1903 /* -------------- */
1904 pseudo_bit_t buff2_addr[0x00020]; /* Address in firmware area of Trace Buffer 2 */
1905 /* -------------- */
1906 pseudo_bit_t buff2_size[0x00020]; /* Size of Trace Buffer 2 */
1907 /* -------------- */
1908 pseudo_bit_t buff3_addr[0x00020]; /* Address in firmware area of Trace Buffer 3 */
1909 /* -------------- */
1910 pseudo_bit_t buff3_size[0x00020]; /* Size of Trace Buffer 3 */
1911 /* -------------- */
1912 pseudo_bit_t buff4_addr[0x00020]; /* Address in firmware area of Trace Buffer 4 */
1913 /* -------------- */
1914 pseudo_bit_t buff4_size[0x00020]; /* Size of Trace Buffer 4 */
1915 /* -------------- */
1916 pseudo_bit_t buff5_addr[0x00020]; /* Address in firmware area of Trace Buffer 5 */
1917 /* -------------- */
1918 pseudo_bit_t buff5_size[0x00020]; /* Size of Trace Buffer 5 */
1919 /* -------------- */
1920 pseudo_bit_t buff6_addr[0x00020]; /* Address in firmware area of Trace Buffer 6 */
1921 /* -------------- */
1922 pseudo_bit_t buff6_size[0x00020]; /* Size of Trace Buffer 6 */
1923 /* -------------- */
1924 pseudo_bit_t buff7_addr[0x00020]; /* Address in firmware area of Trace Buffer 7 */
1925 /* -------------- */
1926 pseudo_bit_t buff7_size[0x00020]; /* Size of Trace Buffer 7 */
1927 /* -------------- */
1928 pseudo_bit_t reserved3[0x00400];
1929 /* -------------- */
1932 /* User Access Region */
1934 struct arbelprm_uar_st { /* Little Endian */
1935 struct arbelprm_rd_send_doorbell_st rd_send_doorbell;/* Reliable Datagram send doorbell */
1936 /* -------------- */
1937 struct arbelprm_send_doorbell_st send_doorbell;/* Send doorbell */
1938 /* -------------- */
1939 pseudo_bit_t reserved0[0x00040];
1940 /* -------------- */
1941 struct arbelprm_cq_cmd_doorbell_st cq_command_doorbell;/* CQ Doorbell */
1942 /* -------------- */
1943 pseudo_bit_t reserved1[0x03ec0];
1944 /* -------------- */
1947 /* Receive doorbell */
1949 struct arbelprm_receive_doorbell_st { /* Little Endian */
1950 pseudo_bit_t reserved0[0x00008];
1951 pseudo_bit_t wqe_counter[0x00010]; /* Modulo-64K counter of WQEs posted on this queue since its creation. Should be zero for the first doorbell on the QP */
1952 pseudo_bit_t reserved1[0x00008];
1953 /* -------------- */
1954 pseudo_bit_t reserved2[0x00005];
1955 pseudo_bit_t srq[0x00001]; /* If set, this is a Shared Receive Queue */
1956 pseudo_bit_t reserved3[0x00002];
1957 pseudo_bit_t qpn[0x00018]; /* QP number or SRQ number this doorbell is rung on */
1958 /* -------------- */
1961 /* SET_IB Parameters */
1963 struct arbelprm_set_ib_st { /* Little Endian */
1964 pseudo_bit_t rqk[0x00001]; /* Reset QKey Violation Counter */
1965 pseudo_bit_t reserved0[0x00011];
1966 pseudo_bit_t sig[0x00001]; /* Set System Image GUID to system_image_guid specified.
1967 system_image_guid and sig must be the same for all ports. */
1968 pseudo_bit_t reserved1[0x0000d];
1969 /* -------------- */
1970 pseudo_bit_t capability_mask[0x00020];/* PortInfo Capability Mask */
1971 /* -------------- */
1972 pseudo_bit_t system_image_guid_h[0x00020];/* System Image GUID[63:32], takes effect only if the SIG bit is set
1973 Must be the same for both ports. */
1974 /* -------------- */
1975 pseudo_bit_t system_image_guid_l[0x00020];/* System Image GUID[31:0], takes effect only if the SIG bit is set
1976 Must be the same for both ports. */
1977 /* -------------- */
1978 pseudo_bit_t reserved2[0x00180];
1979 /* -------------- */
1982 /* Multicast Group Member */
1984 struct arbelprm_mgm_entry_st { /* Little Endian */
1985 pseudo_bit_t reserved0[0x00006];
1986 pseudo_bit_t next_gid_index[0x0001a];/* Index of next Multicast Group Member whose GID maps to same MGID_HASH number.
1987 The index is into the Multicast Group Table, which is the comprised the MGHT and AMGM tables.
1988 next_gid_index=0 means end of the chain. */
1989 /* -------------- */
1990 pseudo_bit_t reserved1[0x00060];
1991 /* -------------- */
1992 pseudo_bit_t mgid_128_96[0x00020]; /* Multicast group GID[128:96] in big endian format.
1993 Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */
1994 /* -------------- */
1995 pseudo_bit_t mgid_95_64[0x00020]; /* Multicast group GID[95:64] in big endian format.
1996 Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */
1997 /* -------------- */
1998 pseudo_bit_t mgid_63_32[0x00020]; /* Multicast group GID[63:32] in big endian format.
1999 Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */
2000 /* -------------- */
2001 pseudo_bit_t mgid_31_0[0x00020]; /* Multicast group GID[31:0] in big endian format.
2002 Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */
2003 /* -------------- */
2004 struct arbelprm_mgmqp_st mgmqp_0; /* Multicast Group Member QP */
2005 /* -------------- */
2006 struct arbelprm_mgmqp_st mgmqp_1; /* Multicast Group Member QP */
2007 /* -------------- */
2008 struct arbelprm_mgmqp_st mgmqp_2; /* Multicast Group Member QP */
2009 /* -------------- */
2010 struct arbelprm_mgmqp_st mgmqp_3; /* Multicast Group Member QP */
2011 /* -------------- */
2012 struct arbelprm_mgmqp_st mgmqp_4; /* Multicast Group Member QP */
2013 /* -------------- */
2014 struct arbelprm_mgmqp_st mgmqp_5; /* Multicast Group Member QP */
2015 /* -------------- */
2016 struct arbelprm_mgmqp_st mgmqp_6; /* Multicast Group Member QP */
2017 /* -------------- */
2018 struct arbelprm_mgmqp_st mgmqp_7; /* Multicast Group Member QP */
2019 /* -------------- */
2022 /* INIT_IB Parameters */
2024 struct arbelprm_init_ib_st { /* Little Endian */
2025 pseudo_bit_t reserved0[0x00004];
2026 pseudo_bit_t vl_cap[0x00004]; /* Maximum VLs supported on the port, excluding VL15.
2027 Legal values are 1,2,4 and 8. */
2028 pseudo_bit_t port_width_cap[0x00004];/* IB Port Width
2031 11 - 1x, 4x or 12x (must not be used in InfiniHost-III-EX MT25208)
2033 pseudo_bit_t mtu_cap[0x00004]; /* Maximum MTU Supported
2039 0x5 - 0xF Reserved */
2040 pseudo_bit_t g0[0x00001]; /* Set port GUID0 to GUID0 specified */
2041 pseudo_bit_t ng[0x00001]; /* Set node GUID to node_guid specified.
2042 node_guid and ng must be the same for all ports. */
2043 pseudo_bit_t sig[0x00001]; /* Set System Image GUID to system_image_guid specified.
2044 system_image_guid and sig must be the same for all ports. */
2045 pseudo_bit_t reserved1[0x0000d];
2046 /* -------------- */
2047 pseudo_bit_t max_gid[0x00010]; /* Maximum number of GIDs for the port */
2048 pseudo_bit_t reserved2[0x00010];
2049 /* -------------- */
2050 pseudo_bit_t max_pkey[0x00010]; /* Maximum pkeys for the port.
2051 Must be the same for both ports. */
2052 pseudo_bit_t reserved3[0x00010];
2053 /* -------------- */
2054 pseudo_bit_t reserved4[0x00020];
2055 /* -------------- */
2056 pseudo_bit_t guid0_h[0x00020]; /* EUI-64 GUID assigned by the manufacturer, takes effect only if the G0 bit is set (bits 63:32) */
2057 /* -------------- */
2058 pseudo_bit_t guid0_l[0x00020]; /* EUI-64 GUID assigned by the manufacturer, takes effect only if the G0 bit is set (bits 31:0) */
2059 /* -------------- */
2060 pseudo_bit_t node_guid_h[0x00020]; /* Node GUID[63:32], takes effect only if the NG bit is set
2061 Must be the same for both ports. */
2062 /* -------------- */
2063 pseudo_bit_t node_guid_l[0x00020]; /* Node GUID[31:0], takes effect only if the NG bit is set
2064 Must be the same for both ports. */
2065 /* -------------- */
2066 pseudo_bit_t system_image_guid_h[0x00020];/* System Image GUID[63:32], takes effect only if the SIG bit is set
2067 Must be the same for both ports. */
2068 /* -------------- */
2069 pseudo_bit_t system_image_guid_l[0x00020];/* System Image GUID[31:0], takes effect only if the SIG bit is set
2070 Must be the same for both ports. */
2071 /* -------------- */
2072 pseudo_bit_t reserved5[0x006c0];
2073 /* -------------- */
2076 /* Query Device Limitations */
2078 struct arbelprm_query_dev_lim_st { /* Little Endian */
2079 pseudo_bit_t reserved0[0x00080];
2080 /* -------------- */
2081 pseudo_bit_t log_max_qp[0x00005]; /* Log2 of the Maximum number of QPs supported */
2082 pseudo_bit_t reserved1[0x00003];
2083 pseudo_bit_t log2_rsvd_qps[0x00004];/* Log (base 2) of the number of QPs reserved for firmware use
2084 The reserved resources are numbered from 0 to 2^log2_rsvd_qps-1 */
2085 pseudo_bit_t reserved2[0x00004];
2086 pseudo_bit_t log_max_qp_sz[0x00008];/* The maximum number of WQEs allowed on the RQ or the SQ is 2^log_max_qp_sz-1 */
2087 pseudo_bit_t log_max_srq_sz[0x00008];/* The maximum number of WQEs allowed on the SRQ is 2^log_max_srq_sz-1 */
2088 /* -------------- */
2089 pseudo_bit_t log_max_ee[0x00005]; /* Log2 of the Maximum number of EE contexts supported */
2090 pseudo_bit_t reserved3[0x00003];
2091 pseudo_bit_t log2_rsvd_ees[0x00004];/* Log (base 2) of the number of EECs reserved for firmware use
2092 The reserved resources are numbered from 0 to 2^log2_rsvd_ees-1 */
2093 pseudo_bit_t reserved4[0x00004];
2094 pseudo_bit_t log_max_srqs[0x00005]; /* Log base 2 of the maximum number of SRQs supported, valid only if SRQ bit is set.
2096 pseudo_bit_t reserved5[0x00007];
2097 pseudo_bit_t log2_rsvd_srqs[0x00004];/* Log (base 2) of the number of reserved SRQs for firmware use
2098 The reserved resources are numbered from 0 to 2^log2_rsvd_srqs-1
2099 This parameter is valid only if the SRQ bit is set. */
2100 /* -------------- */
2101 pseudo_bit_t log_max_cq[0x00005]; /* Log2 of the Maximum number of CQs supported */
2102 pseudo_bit_t reserved6[0x00003];
2103 pseudo_bit_t log2_rsvd_cqs[0x00004];/* Log (base 2) of the number of CQs reserved for firmware use
2104 The reserved resources are numbered from 0 to 2^log2_rsrvd_cqs-1 */
2105 pseudo_bit_t reserved7[0x00004];
2106 pseudo_bit_t log_max_cq_sz[0x00008];/* Log2 of the Maximum CQEs allowed in a CQ */
2107 pseudo_bit_t reserved8[0x00008];
2108 /* -------------- */
2109 pseudo_bit_t log_max_eq[0x00003]; /* Log2 of the Maximum number of EQs */
2110 pseudo_bit_t reserved9[0x00005];
2111 pseudo_bit_t num_rsvd_eqs[0x00004]; /* The number of EQs reserved for firmware use
2112 The reserved resources are numbered from 0 to num_rsvd_eqs-1
2113 If 0 - no resources are reserved. */
2114 pseudo_bit_t reserved10[0x00004];
2115 pseudo_bit_t log_max_mpts[0x00006]; /* Log (base 2) of the maximum number of MPT entries (the number of Regions/Windows) */
2116 pseudo_bit_t reserved11[0x00002];
2117 pseudo_bit_t log_max_eq_sz[0x00008];/* Log2 of the Maximum EQEs allowed in a EQ */
2118 /* -------------- */
2119 pseudo_bit_t log_max_mtts[0x00006]; /* Log2 of the Maximum number of MTT entries */
2120 pseudo_bit_t reserved12[0x00002];
2121 pseudo_bit_t log2_rsvd_mrws[0x00004];/* Log (base 2) of the number of MPTs reserved for firmware use
2122 The reserved resources are numbered from 0 to 2^log2_rsvd_mrws-1 */
2123 pseudo_bit_t reserved13[0x00004];
2124 pseudo_bit_t log_max_mrw_sz[0x00008];/* Log2 of the Maximum Size of Memory Region/Window */
2125 pseudo_bit_t reserved14[0x00004];
2126 pseudo_bit_t log2_rsvd_mtts[0x00004];/* Log (base 2) of the number of MTT entries reserved for firmware use
2127 The reserved resources are numbered from 0 to 2^log2_rsvd_mtts-1
2129 /* -------------- */
2130 pseudo_bit_t reserved15[0x00020];
2131 /* -------------- */
2132 pseudo_bit_t log_max_ra_res_qp[0x00006];/* Log2 of the Maximum number of outstanding RDMA read/Atomic per QP as a responder */
2133 pseudo_bit_t reserved16[0x0000a];
2134 pseudo_bit_t log_max_ra_req_qp[0x00006];/* Log2 of the maximum number of outstanding RDMA read/Atomic per QP as a requester */
2135 pseudo_bit_t reserved17[0x0000a];
2136 /* -------------- */
2137 pseudo_bit_t log_max_ra_res_global[0x00006];/* Log2 of the maximum number of RDMA read/atomic operations the HCA responder can support globally. That implies the RDB table size. */
2138 pseudo_bit_t reserved18[0x00016];
2139 pseudo_bit_t log2_rsvd_rdbs[0x00004];/* Log (base 2) of the number of RDB entries reserved for firmware use
2140 The reserved resources are numbered from 0 to 2^log2_rsvd_rdbs-1 */
2141 /* -------------- */
2142 pseudo_bit_t rsz_srq[0x00001]; /* Ability to modify the maximum number of WRs per SRQ. */
2143 pseudo_bit_t reserved19[0x0001f];
2144 /* -------------- */
2145 pseudo_bit_t num_ports[0x00004]; /* Number of IB ports. */
2146 pseudo_bit_t max_vl[0x00004]; /* Maximum VLs supported on each port, excluding VL15 */
2147 pseudo_bit_t max_port_width[0x00004];/* IB Port Width
2152 pseudo_bit_t max_mtu[0x00004]; /* Maximum MTU Supported
2158 0x5 - 0xF Reserved */
2159 pseudo_bit_t local_ca_ack_delay[0x00005];/* The Local CA ACK Delay. This is the value recommended to be returned in Query HCA verb.
2160 The delay value in microseconds is computed using 4.096us * 2^(local_ca_ack_delay). */
2161 pseudo_bit_t reserved20[0x0000b];
2162 /* -------------- */
2163 pseudo_bit_t log_max_gid[0x00004]; /* Log2 of the maximum number of GIDs per port */
2164 pseudo_bit_t reserved21[0x0001c];
2165 /* -------------- */
2166 pseudo_bit_t log_max_pkey[0x00004]; /* Log2 of the max PKey Table Size (per IB port) */
2167 pseudo_bit_t reserved22[0x0000c];
2168 pseudo_bit_t stat_rate_support[0x00010];/* bit mask of stat rate supported
2173 /* -------------- */
2174 pseudo_bit_t reserved23[0x00020];
2175 /* -------------- */
2176 pseudo_bit_t rc[0x00001]; /* RC Transport supported */
2177 pseudo_bit_t uc[0x00001]; /* UC Transport Supported */
2178 pseudo_bit_t ud[0x00001]; /* UD Transport Supported */
2179 pseudo_bit_t rd[0x00001]; /* RD Transport Supported */
2180 pseudo_bit_t raw_ipv6[0x00001]; /* Raw IPv6 Transport Supported */
2181 pseudo_bit_t raw_ether[0x00001]; /* Raw Ethertype Transport Supported */
2182 pseudo_bit_t srq[0x00001]; /* SRQ is supported
2184 pseudo_bit_t ipo_ib_checksum[0x00001];/* IP over IB checksum is supported */
2185 pseudo_bit_t pkv[0x00001]; /* PKey Violation Counter Supported */
2186 pseudo_bit_t qkv[0x00001]; /* QKey Violation Coutner Supported */
2187 pseudo_bit_t reserved24[0x00006];
2188 pseudo_bit_t mw[0x00001]; /* Memory windows supported */
2189 pseudo_bit_t apm[0x00001]; /* Automatic Path Migration Supported */
2190 pseudo_bit_t atm[0x00001]; /* Atomic operations supported (atomicity is guaranteed between QPs on this HCA) */
2191 pseudo_bit_t rm[0x00001]; /* Raw Multicast Supported */
2192 pseudo_bit_t avp[0x00001]; /* Address Vector Port checking supported */
2193 pseudo_bit_t udm[0x00001]; /* UD Multicast Supported */
2194 pseudo_bit_t reserved25[0x00002];
2195 pseudo_bit_t pg[0x00001]; /* Paging on demand supported */
2196 pseudo_bit_t r[0x00001]; /* Router mode supported */
2197 pseudo_bit_t reserved26[0x00006];
2198 /* -------------- */
2199 pseudo_bit_t log_pg_sz[0x00008]; /* Minimum system page size supported (log2).
2200 For proper operation it must be less than or equal the hosting platform (CPU) minimum page size. */
2201 pseudo_bit_t reserved27[0x00008];
2202 pseudo_bit_t uar_sz[0x00006]; /* UAR Area Size = 1MB * 2^uar_sz */
2203 pseudo_bit_t reserved28[0x00006];
2204 pseudo_bit_t num_rsvd_uars[0x00004];/* The number of UARs reserved for firmware use
2205 The reserved resources are numbered from 0 to num_reserved_uars-1
2206 Note that UAR number num_reserved_uars is always for the kernel. */
2207 /* -------------- */
2208 pseudo_bit_t reserved29[0x00020];
2209 /* -------------- */
2210 pseudo_bit_t max_desc_sz_sq[0x00010];/* Max descriptor size in bytes for the send queue */
2211 pseudo_bit_t max_sg_sq[0x00008]; /* The maximum S/G list elements in a SQ WQE (max_desc_sz/16 - 3) */
2212 pseudo_bit_t reserved30[0x00008];
2213 /* -------------- */
2214 pseudo_bit_t max_desc_sz_rq[0x00010];/* Max descriptor size in bytes for the receive queue */
2215 pseudo_bit_t max_sg_rq[0x00008]; /* The maximum S/G list elements in a RQ WQE (max_desc_sz/16 - 3) */
2216 pseudo_bit_t reserved31[0x00008];
2217 /* -------------- */
2218 pseudo_bit_t reserved32[0x00040];
2219 /* -------------- */
2220 pseudo_bit_t log_max_mcg[0x00008]; /* Log2 of the maximum number of multicast groups */
2221 pseudo_bit_t num_rsvd_mcgs[0x00004];/* The number of MGMs reserved for firmware use in the MGHT.
2222 The reserved resources are numbered from 0 to num_reserved_mcgs-1
2223 If 0 - no resources are reserved. */
2224 pseudo_bit_t reserved33[0x00004];
2225 pseudo_bit_t log_max_qp_mcg[0x00008];/* Log2 of the maximum number of QPs per multicast group */
2226 pseudo_bit_t reserved34[0x00008];
2227 /* -------------- */
2228 pseudo_bit_t log_max_rdds[0x00006]; /* Log2 of the maximum number of RDDs */
2229 pseudo_bit_t reserved35[0x00006];
2230 pseudo_bit_t num_rsvd_rdds[0x00004];/* The number of RDDs reserved for firmware use
2231 The reserved resources are numbered from 0 to num_reserved_rdds-1.
2232 If 0 - no resources are reserved. */
2233 pseudo_bit_t log_max_pd[0x00006]; /* Log2 of the maximum number of PDs */
2234 pseudo_bit_t reserved36[0x00006];
2235 pseudo_bit_t num_rsvd_pds[0x00004]; /* The number of PDs reserved for firmware use
2236 The reserved resources are numbered from 0 to num_reserved_pds-1
2237 If 0 - no resources are reserved. */
2238 /* -------------- */
2239 pseudo_bit_t reserved37[0x000c0];
2240 /* -------------- */
2241 pseudo_bit_t qpc_entry_sz[0x00010]; /* QPC Entry Size for the device
2242 For the InfiniHost-III-EX MT25208 entry size is 256 bytes */
2243 pseudo_bit_t eec_entry_sz[0x00010]; /* EEC Entry Size for the device
2244 For the InfiniHost-III-EX MT25208 entry size is 256 bytes */
2245 /* -------------- */
2246 pseudo_bit_t eqpc_entry_sz[0x00010];/* Extended QPC entry size for the device
2247 For the InfiniHost-III-EX MT25208 entry size is 32 bytes */
2248 pseudo_bit_t eeec_entry_sz[0x00010];/* Extended EEC entry size for the device
2249 For the InfiniHost-III-EX MT25208 entry size is 32 bytes */
2250 /* -------------- */
2251 pseudo_bit_t cqc_entry_sz[0x00010]; /* CQC entry size for the device
2252 For the InfiniHost-III-EX MT25208 entry size is 64 bytes */
2253 pseudo_bit_t eqc_entry_sz[0x00010]; /* EQ context entry size for the device
2254 For the InfiniHost-III-EX MT25208 entry size is 64 bytes */
2255 /* -------------- */
2256 pseudo_bit_t uar_scratch_entry_sz[0x00010];/* UAR Scratchpad Entry Size
2257 For the InfiniHost-III-EX MT25208 entry size is 32 bytes */
2258 pseudo_bit_t srq_entry_sz[0x00010]; /* SRQ context entry size for the device
2259 For the InfiniHost-III-EX MT25208 entry size is 32 bytes */
2260 /* -------------- */
2261 pseudo_bit_t mpt_entry_sz[0x00010]; /* MPT entry size in Bytes for the device.
2262 For the InfiniHost-III-EX MT25208 entry size is 64 bytes */
2263 pseudo_bit_t mtt_entry_sz[0x00010]; /* MTT entry size in Bytes for the device.
2264 For the InfiniHost-III-EX MT25208 entry size is 8 bytes */
2265 /* -------------- */
2266 pseudo_bit_t bmme[0x00001]; /* Base Memory Management Extension Support */
2267 pseudo_bit_t win_type[0x00001]; /* Bound Type 2 Memory Window Association mechanism:
2268 0 - Type 2A - QP Number Association; or
2269 1 - Type 2B - QP Number and PD Association. */
2270 pseudo_bit_t mps[0x00001]; /* Ability of this HCA to support multiple page sizes per Memory Region. */
2271 pseudo_bit_t bl[0x00001]; /* Ability of this HCA to support Block List Physical Buffer Lists. (The device does not supports Block List) */
2272 pseudo_bit_t zb[0x00001]; /* Zero Based region/windows supported */
2273 pseudo_bit_t lif[0x00001]; /* Ability of this HCA to support Local Invalidate Fencing. */
2274 pseudo_bit_t reserved38[0x00002];
2275 pseudo_bit_t log_pbl_sz[0x00006]; /* Log2 of the Maximum Physical Buffer List size in Bytes supported by this HCA when invoking the Allocate L_Key verb.
2277 pseudo_bit_t reserved39[0x00012];
2278 /* -------------- */
2279 pseudo_bit_t resd_lkey[0x00020]; /* The value of the reserved Lkey for Base Memory Management Extension */
2280 /* -------------- */
2281 pseudo_bit_t lamr[0x00001]; /* When set the device requires local attached memory in order to operate.
2282 When set, ICM pages, Firmware Area and ICM auxiliary pages must be allocated in the local attached memory. */
2283 pseudo_bit_t reserved40[0x0001f];
2284 /* -------------- */
2285 pseudo_bit_t max_icm_size_h[0x00020];/* Bits [63:32] of maximum ICM size InfiniHost III Ex support in bytes. */
2286 /* -------------- */
2287 pseudo_bit_t max_icm_size_l[0x00020];/* Bits [31:0] of maximum ICM size InfiniHost III Ex support in bytes. */
2288 /* -------------- */
2289 pseudo_bit_t reserved41[0x002c0];
2290 /* -------------- */
2293 /* QUERY_ADAPTER Parameters Block */
2295 struct arbelprm_query_adapter_st { /* Little Endian */
2296 pseudo_bit_t reserved0[0x00080];
2297 /* -------------- */
2298 pseudo_bit_t reserved1[0x00018];
2299 pseudo_bit_t intapin[0x00008]; /* Driver should set this field to INTR value in the event queue in order to get Express interrupt messages. */
2300 /* -------------- */
2301 pseudo_bit_t reserved2[0x00060];
2302 /* -------------- */
2303 struct arbelprm_vsd_st vsd;
2304 /* -------------- */
2307 /* QUERY_FW Parameters Block */
2309 struct arbelprm_query_fw_st { /* Little Endian */
2310 pseudo_bit_t fw_rev_major[0x00010]; /* Firmware Revision - Major */
2311 pseudo_bit_t fw_pages[0x00010]; /* Amount of physical memory to be allocated for FW usage is in 4KByte pages. */
2312 /* -------------- */
2313 pseudo_bit_t fw_rev_minor[0x00010]; /* Firmware Revision - Minor */
2314 pseudo_bit_t fw_rev_subminor[0x00010];/* Firmware Sub-minor version (Patch level). */
2315 /* -------------- */
2316 pseudo_bit_t cmd_interface_rev[0x00010];/* Command Interface Interpreter Revision ID */
2317 pseudo_bit_t reserved0[0x0000e];
2318 pseudo_bit_t wqe_h_mode[0x00001]; /* Hermon mode. If '1', then WQE and AV format is the advanced format */
2319 pseudo_bit_t zb_wq_cq[0x00001]; /* If '1', then ZB mode of WQ and CQ are enabled (i.e. real Memfree PRM is supported) */
2320 /* -------------- */
2321 pseudo_bit_t log_max_outstanding_cmd[0x00008];/* Log2 of the maximum number of commands the HCR can support simultaneously */
2322 pseudo_bit_t reserved1[0x00017];
2323 pseudo_bit_t dt[0x00001]; /* Debug Trace Support
2324 0 - Debug trace is not supported
2325 1 - Debug trace is supported */
2326 /* -------------- */
2327 pseudo_bit_t cmd_interface_db[0x00001];/* Set if the device accepts commands by means of special doorbells */
2328 pseudo_bit_t reserved2[0x0001f];
2329 /* -------------- */
2330 pseudo_bit_t reserved3[0x00060];
2331 /* -------------- */
2332 pseudo_bit_t clr_int_base_addr_h[0x00020];/* Bits [63:32] of Clear interrupt register physical address.
2333 Points to 64 bit register. */
2334 /* -------------- */
2335 pseudo_bit_t clr_int_base_addr_l[0x00020];/* Bits [31:0] of Clear interrupt register physical address.
2336 Points to 64 bit register. */
2337 /* -------------- */
2338 pseudo_bit_t reserved4[0x00040];
2339 /* -------------- */
2340 pseudo_bit_t error_buf_start_h[0x00020];/* Read Only buffer for catastrophic error reports (physical address) */
2341 /* -------------- */
2342 pseudo_bit_t error_buf_start_l[0x00020];/* Read Only buffer for catastrophic error reports (physical address) */
2343 /* -------------- */
2344 pseudo_bit_t error_buf_size[0x00020];/* Size in words */
2345 /* -------------- */
2346 pseudo_bit_t reserved5[0x00020];
2347 /* -------------- */
2348 pseudo_bit_t eq_arm_base_addr_h[0x00020];/* Bits [63:32] of EQ Arm DBs physical address.
2349 Points to 64 bit register.
2350 Setting bit x in the offset, arms EQ number x.
2352 /* -------------- */
2353 pseudo_bit_t eq_arm_base_addr_l[0x00020];/* Bits [31:0] of EQ Arm DBs physical address.
2354 Points to 64 bit register.
2355 Setting bit x in the offset, arms EQ number x. */
2356 /* -------------- */
2357 pseudo_bit_t eq_set_ci_base_addr_h[0x00020];/* Bits [63:32] of EQ Set CI DBs Table physical address.
2358 Points to a the EQ Set CI DBs Table base address. */
2359 /* -------------- */
2360 pseudo_bit_t eq_set_ci_base_addr_l[0x00020];/* Bits [31:0] of EQ Set CI DBs Table physical address.
2361 Points to a the EQ Set CI DBs Table base address. */
2362 /* -------------- */
2363 pseudo_bit_t cmd_db_dw1[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 1 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
2364 pseudo_bit_t cmd_db_dw0[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 0 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
2365 /* -------------- */
2366 pseudo_bit_t cmd_db_dw3[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 3 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
2367 pseudo_bit_t cmd_db_dw2[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 2 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
2368 /* -------------- */
2369 pseudo_bit_t cmd_db_dw5[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 5 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
2370 pseudo_bit_t cmd_db_dw4[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 4 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
2371 /* -------------- */
2372 pseudo_bit_t cmd_db_dw7[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 7 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
2373 pseudo_bit_t cmd_db_dw6[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 6 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
2374 /* -------------- */
2375 pseudo_bit_t cmd_db_addr_base_h[0x00020];/* High bits of cmd_db_addr_base, which cmd_db_dw offsets refer to. Valid only if CmdInterfaceDb bit is '1' */
2376 /* -------------- */
2377 pseudo_bit_t cmd_db_addr_base_l[0x00020];/* Low bits of cmd_db_addr_base, which cmd_db_dw offsets refer to. Valid only if CmdInterfaceDb bit is '1' */
2378 /* -------------- */
2379 pseudo_bit_t reserved6[0x004c0];
2380 /* -------------- */
2385 struct arbelprm_access_lam_st { /* Little Endian */
2386 struct arbelprm_access_lam_inject_errors_st access_lam_inject_errors;
2387 /* -------------- */
2388 pseudo_bit_t reserved0[0x00080];
2389 /* -------------- */
2392 /* ENABLE_LAM Parameters Block */
2394 struct arbelprm_enable_lam_st { /* Little Endian */
2395 pseudo_bit_t lam_start_adr_h[0x00020];/* LAM start address [63:32] */
2396 /* -------------- */
2397 pseudo_bit_t lam_start_adr_l[0x00020];/* LAM start address [31:0] */
2398 /* -------------- */
2399 pseudo_bit_t lam_end_adr_h[0x00020];/* LAM end address [63:32] */
2400 /* -------------- */
2401 pseudo_bit_t lam_end_adr_l[0x00020];/* LAM end address [31:0] */
2402 /* -------------- */
2403 pseudo_bit_t di[0x00002]; /* Data Integrity Configuration:
2406 10 - ECC Detection Only
2407 11 - ECC With Correction */
2408 pseudo_bit_t ap[0x00002]; /* Auto Precharge Mode
2409 00 - No auto precharge
2410 01 - Auto precharge per transaction
2411 10 - Auto precharge per 64 bytes
2413 pseudo_bit_t dh[0x00001]; /* When set, LAM is Hidden and can not be accessed directly from the PCI bus. */
2414 pseudo_bit_t reserved0[0x0001b];
2415 /* -------------- */
2416 pseudo_bit_t reserved1[0x00160];
2417 /* -------------- */
2418 struct arbelprm_dimminfo_st dimm0; /* Logical DIMM 0 Parameters */
2419 /* -------------- */
2420 struct arbelprm_dimminfo_st dimm1; /* Logical DIMM 1 Parameters */
2421 /* -------------- */
2422 pseudo_bit_t reserved2[0x00400];
2423 /* -------------- */
2426 /* Memory Access Parameters for UD Address Vector Table */
2428 struct arbelprm_udavtable_memory_parameters_st { /* Little Endian */
2429 pseudo_bit_t l_key[0x00020]; /* L_Key used to access TPT */
2430 /* -------------- */
2431 pseudo_bit_t pd[0x00018]; /* PD used by TPT for matching against PD of region entry being accessed. */
2432 pseudo_bit_t reserved0[0x00005];
2433 pseudo_bit_t xlation_en[0x00001]; /* When cleared, address is physical address and no translation will be done. When set, address is virtual. */
2434 pseudo_bit_t reserved1[0x00002];
2435 /* -------------- */
2438 /* INIT_HCA & QUERY_HCA Parameters Block */
2440 struct arbelprm_init_hca_st { /* Little Endian */
2441 pseudo_bit_t reserved0[0x00060];
2442 /* -------------- */
2443 pseudo_bit_t reserved1[0x00010];
2444 pseudo_bit_t time_stamp_granularity[0x00008];/* This field controls the granularity in which CQE Timestamp counter is incremented.
2445 The TimeStampGranularity units is 1/4 of a microseconds. (e.g is TimeStampGranularity is configured to 0x2, CQE Timestamp will be incremented every one microsecond)
2446 When sets to Zero, timestamp reporting in the CQE is disabled.
2447 This feature is currently not supported.
2449 pseudo_bit_t hca_core_clock[0x00008];/* Internal Clock Period (in units of 1/16 ns) (QUERY_HCA only) */
2450 /* -------------- */
2451 pseudo_bit_t reserved2[0x00008];
2452 pseudo_bit_t router_qp[0x00010]; /* Upper 16 bit to be used as a QP number for router mode. Low order 8 bits are taken from the TClass field of the incoming packet.
2453 Valid only if RE bit is set */
2454 pseudo_bit_t reserved3[0x00007];
2455 pseudo_bit_t re[0x00001]; /* Router Mode Enable
2456 If this bit is set, entire packet (including all headers and ICRC) will be considered as a data payload and will be scattered to memory as specified in the descriptor that is posted on the QP matching the TClass field of packet. */
2457 /* -------------- */
2458 pseudo_bit_t udp[0x00001]; /* UD Port Check Enable
2459 0 - Port field in Address Vector is ignored
2460 1 - HCA will check the port field in AV entry (fetched for UD descriptor) against the Port of the UD QP executing the descriptor. */
2461 pseudo_bit_t he[0x00001]; /* Host Endianess - Used for Atomic Operations
2462 0 - Host is Little Endian
2463 1 - Host is Big endian
2465 pseudo_bit_t reserved4[0x00001];
2466 pseudo_bit_t ce[0x00001]; /* Checksum Enabled - when Set IPoverIB checksum generation & checking is enabled */
2467 pseudo_bit_t sph[0x00001]; /* 0 - SW calculates TCP/UDP Pseudo-Header checksum and inserts it into the TCP/UDP checksum field when sending a packet
2468 1 - HW calculates TCP/UDP Pseudo-Header checksum when sending a packet
2470 pseudo_bit_t rph[0x00001]; /* 0 - Not HW calculation of TCP/UDP Pseudo-Header checksum are done when receiving a packet
2471 1 - HW calculates TCP/UDP Pseudo-Header checksum when receiving a packet
2473 pseudo_bit_t reserved5[0x00002];
2474 pseudo_bit_t responder_exu[0x00004];/* Indicate the relation between the execution enegines allocation dedicated for responder versus the engines dedicated for reqvester .
2475 responder_exu/16 = (number of responder exu engines)/(total number of engines)
2476 Legal values are 0x0-0xF. 0 is "auto".
2479 pseudo_bit_t reserved6[0x00004];
2480 pseudo_bit_t wqe_quota[0x0000f]; /* Maximum number of WQEs that are executed prior to preemption of execution unit. 0 - reserved. */
2481 pseudo_bit_t wqe_quota_en[0x00001]; /* If set - wqe_quota field is used. If cleared - WQE quota is set to "auto" value */
2482 /* -------------- */
2483 pseudo_bit_t reserved7[0x00040];
2484 /* -------------- */
2485 struct arbelprm_qpcbaseaddr_st qpc_eec_cqc_eqc_rdb_parameters;
2486 /* -------------- */
2487 pseudo_bit_t reserved8[0x00100];
2488 /* -------------- */
2489 struct arbelprm_multicastparam_st multicast_parameters;
2490 /* -------------- */
2491 pseudo_bit_t reserved9[0x00080];
2492 /* -------------- */
2493 struct arbelprm_tptparams_st tpt_parameters;
2494 /* -------------- */
2495 pseudo_bit_t reserved10[0x00080];
2496 /* -------------- */
2497 struct arbelprm_uar_params_st uar_parameters;/* UAR Parameters */
2498 /* -------------- */
2499 pseudo_bit_t reserved11[0x00600];
2500 /* -------------- */
2503 /* Event Queue Context Table Entry */
2505 struct arbelprm_eqc_st { /* Little Endian */
2506 pseudo_bit_t reserved0[0x00008];
2507 pseudo_bit_t st[0x00004]; /* Event delivery state machine
2510 0xB - Always_Armed (auto-rearm)
2512 pseudo_bit_t reserved1[0x00005];
2513 pseudo_bit_t oi[0x00001]; /* Oerrun ignore.
2514 If set, HW will not check EQ full condition when writing new EQEs. */
2515 pseudo_bit_t tr[0x00001]; /* Translation Required. If set - EQ access undergo address translation. */
2516 pseudo_bit_t reserved2[0x00005];
2517 pseudo_bit_t owner[0x00004]; /* 0 - SW ownership
2519 Valid for the QUERY_EQ and HW2SW_EQ commands only */
2520 pseudo_bit_t status[0x00004]; /* EQ status:
2522 1010 - EQ write failure
2523 Valid for the QUERY_EQ and HW2SW_EQ commands only */
2524 /* -------------- */
2525 pseudo_bit_t start_address_h[0x00020];/* Start Address of Event Queue[63:32]. */
2526 /* -------------- */
2527 pseudo_bit_t start_address_l[0x00020];/* Start Address of Event Queue[31:0].
2528 Must be aligned on 32-byte boundary */
2529 /* -------------- */
2530 pseudo_bit_t reserved3[0x00018];
2531 pseudo_bit_t log_eq_size[0x00005]; /* Amount of entries in this EQ is 2^log_eq_size.
2532 Log_eq_size must be bigger than 1.
2533 Maximum EQ size is 2^17 EQEs (max Log_eq_size is 17). */
2534 pseudo_bit_t reserved4[0x00003];
2535 /* -------------- */
2536 pseudo_bit_t reserved5[0x00020];
2537 /* -------------- */
2538 pseudo_bit_t intr[0x00008]; /* Interrupt (message) to be generated to report event to INT layer.
2539 00iiiiii - set to INTA given in QUERY_ADAPTER in order to generate INTA messages on Express.
2540 10jjjjjj - specificies type of interrupt message to be generated (total 64 different messages supported).
2541 All other values are reserved and should not be used.
2543 If interrupt generation is not required, ST field must be set upon creation to Fired state. No EQ arming doorbell should be performed. In this case hardware will not generate any interrupt. */
2544 pseudo_bit_t reserved6[0x00018];
2545 /* -------------- */
2546 pseudo_bit_t pd[0x00018]; /* PD to be used to access EQ */
2547 pseudo_bit_t reserved7[0x00008];
2548 /* -------------- */
2549 pseudo_bit_t lkey[0x00020]; /* Memory key (L-Key) to be used to access EQ */
2550 /* -------------- */
2551 pseudo_bit_t reserved8[0x00040];
2552 /* -------------- */
2553 pseudo_bit_t consumer_indx[0x00020];/* Contains next entry to be read upon polling the event queue.
2554 Must be initalized to zero while opening EQ */
2555 /* -------------- */
2556 pseudo_bit_t producer_indx[0x00020];/* Contains next entry in EQ to be written by the HCA.
2557 Must be initalized to zero while opening EQ. */
2558 /* -------------- */
2559 pseudo_bit_t reserved9[0x00080];
2560 /* -------------- */
2563 /* Memory Translation Table (MTT) Entry */
2565 struct arbelprm_mtt_st { /* Little Endian */
2566 pseudo_bit_t ptag_h[0x00020]; /* High-order bits of physical tag. The size of the field depends on the page size of the region. Maximum PTAG size is 52 bits. */
2567 /* -------------- */
2568 pseudo_bit_t p[0x00001]; /* Present bit. If set, page entry is valid. If cleared, access to this page will generate non-present page access fault. */
2569 pseudo_bit_t reserved0[0x0000b];
2570 pseudo_bit_t ptag_l[0x00014]; /* Low-order bits of Physical tag. The size of the field depends on the page size of the region. Maximum PTAG size is 52 bits. */
2571 /* -------------- */
2574 /* Memory Protection Table (MPT) Entry */
2576 struct arbelprm_mpt_st { /* Little Endian */
2577 pseudo_bit_t reserved0[0x00008];
2578 pseudo_bit_t r_w[0x00001]; /* Defines whether this entry is Region (1) or Window (0) */
2579 pseudo_bit_t pa[0x00001]; /* Physical address. If set, no virtual-to-physical address translation will be performed for this region */
2580 pseudo_bit_t lr[0x00001]; /* If set - local read access enabled */
2581 pseudo_bit_t lw[0x00001]; /* If set - local write access enabled */
2582 pseudo_bit_t rr[0x00001]; /* If set - remote read access enabled. */
2583 pseudo_bit_t rw[0x00001]; /* If set - remote write access enabled */
2584 pseudo_bit_t a[0x00001]; /* If set - remote Atomic access is enabled */
2585 pseudo_bit_t eb[0x00001]; /* If set - Bind is enabled. Valid for region entry only. */
2586 pseudo_bit_t reserved1[0x0000c];
2587 pseudo_bit_t status[0x00004]; /* Region/Window Status
2588 0xF - not valid (SW ownership)
2591 Unbound Type I windows are doneted reg_wnd_len field equals zero.
2592 Unbound Type II windows are donated by Status=FREE. */
2593 /* -------------- */
2594 pseudo_bit_t page_size[0x00005]; /* Page size used for the region. Actual size is [4K]*2^Page_size bytes.
2595 page_size should be less than 20. */
2596 pseudo_bit_t reserved2[0x00002];
2597 pseudo_bit_t type[0x00001]; /* Applicable for windows only, must be zero for regions
2599 1 - Type two window */
2600 pseudo_bit_t qpn[0x00018]; /* QP number this MW is attached to. Valid for type2 memory windows and on QUERY_MPT only */
2601 /* -------------- */
2602 pseudo_bit_t mem_key[0x00020]; /* The memory Key. The field holds the mem_key field in the following semantics: {key[7:0],key[31:8]}.
2604 /* -------------- */
2605 pseudo_bit_t pd[0x00018]; /* Protection Domain */
2606 pseudo_bit_t reserved3[0x00001];
2607 pseudo_bit_t ei[0x00001]; /* Enable Invalidation - When set, Local/Remote invalidation can be executed on this window/region.
2608 Must be set for type2 windows and non-shared physical memory regions.
2609 Must be clear for regions that are used to access Work Queues, Completion Queues and Event Queues */
2610 pseudo_bit_t zb[0x00001]; /* When set, this region is Zero Based Region */
2611 pseudo_bit_t fre[0x00001]; /* When set, Fast Registration Operations can be executed on this region */
2612 pseudo_bit_t rae[0x00001]; /* When set, remote access can be enabled on this region.
2613 Used when executing Fast Registration Work Request to validate that remote access rights can be granted to this MPT.
2614 If the bit is cleared, Fast Registration Work Request requesting remote access rights will fail.
2616 pseudo_bit_t reserved4[0x00003];
2617 /* -------------- */
2618 pseudo_bit_t start_address_h[0x00020];/* Start Address[63:32] - Virtual Address where this region/window starts */
2619 /* -------------- */
2620 pseudo_bit_t start_address_l[0x00020];/* Start Address[31:0] - Virtual Address where this region/window starts */
2621 /* -------------- */
2622 pseudo_bit_t reg_wnd_len_h[0x00020];/* Region/Window Length[63:32] */
2623 /* -------------- */
2624 pseudo_bit_t reg_wnd_len_l[0x00020];/* Region/Window Length[31:0] */
2625 /* -------------- */
2626 pseudo_bit_t lkey[0x00020]; /* Must be 0 for SW2HW_MPT.
2627 On QUERY_MPT and HW2SW_MPT commands for Memory Window it reflects the LKey of the Region that the Window is bound to.
2628 The field holds the lkey field in the following semantics: {key[7:0],key[31:8]}. */
2629 /* -------------- */
2630 pseudo_bit_t win_cnt[0x00020]; /* Number of windows bound to this region. Valid for regions only.
2631 The field is valid only for the QUERY_MPT and HW2SW_MPT commands. */
2632 /* -------------- */
2633 pseudo_bit_t reserved5[0x00020];
2634 /* -------------- */
2635 pseudo_bit_t mtt_adr_h[0x00006]; /* Base (first) address of the MTT relative to MTT base in the ICM */
2636 pseudo_bit_t reserved6[0x0001a];
2637 /* -------------- */
2638 pseudo_bit_t reserved7[0x00003];
2639 pseudo_bit_t mtt_adr_l[0x0001d]; /* Base (first) address of the MTT relative to MTT base address in the ICM. Must be aligned on 8 bytes. */
2640 /* -------------- */
2641 pseudo_bit_t mtt_sz[0x00020]; /* Number of MTT entries allocated for this MR.
2642 When Fast Registration Operations can not be executed on this region (FRE bit is zero) this field is reserved.
2643 When Fast Registration Operation is enabled (FRE bit is set) this field indicates the number of MTTs allocated for this MR. If mtt_sz value is zero, there is no limit for the numbers of MTTs and the HCA does not check this field when executing fast register WQE. */
2644 /* -------------- */
2645 pseudo_bit_t reserved8[0x00040];
2646 /* -------------- */
2649 /* Completion Queue Context Table Entry */
2651 struct arbelprm_completion_queue_context_st { /* Little Endian */
2652 pseudo_bit_t reserved0[0x00008];
2653 pseudo_bit_t st[0x00004]; /* Event delivery state machine
2655 0x9 - ARMED (Request for Notification)
2656 0x6 - ARMED SOLICITED (Request Solicited Notification)
2660 Must be 0x0 in CQ initialization.
2661 Valid for the QUERY_CQ and HW2SW_CQ commands only. */
2662 pseudo_bit_t reserved1[0x00005];
2663 pseudo_bit_t oi[0x00001]; /* When set, overrun ignore is enabled.
2664 When set, Updates of CQ consumer counter (poll for completion) or Request completion notifications (Arm CQ) doorbells should not be rang on that CQ. */
2665 pseudo_bit_t reserved2[0x0000a];
2666 pseudo_bit_t status[0x00004]; /* CQ status
2669 1010 - CQ write failure
2670 Valid for the QUERY_CQ and HW2SW_CQ commands only */
2671 /* -------------- */
2672 pseudo_bit_t start_address_h[0x00020];/* Start address of CQ[63:32].
2673 Must be aligned on CQE size (32 bytes) */
2674 /* -------------- */
2675 pseudo_bit_t start_address_l[0x00020];/* Start address of CQ[31:0].
2676 Must be aligned on CQE size (32 bytes) */
2677 /* -------------- */
2678 pseudo_bit_t usr_page[0x00018]; /* UAR page this CQ can be accessed through (ringinig CQ doorbells) */
2679 pseudo_bit_t log_cq_size[0x00005]; /* Log (base 2) of the CQ size (in entries).
2680 Maximum CQ size is 2^17 CQEs (max log_cq_size is 17) */
2681 pseudo_bit_t reserved3[0x00003];
2682 /* -------------- */
2683 pseudo_bit_t reserved4[0x00020];
2684 /* -------------- */
2685 pseudo_bit_t c_eqn[0x00008]; /* Event Queue this CQ reports completion events to.
2686 Valid values are 0 to 63
2687 If configured to value other than 0-63, completion events will not be reported on the CQ. */
2688 pseudo_bit_t reserved5[0x00018];
2689 /* -------------- */
2690 pseudo_bit_t pd[0x00018]; /* Protection Domain to be used to access CQ.
2691 Must be the same PD of the CQ L_Key. */
2692 pseudo_bit_t reserved6[0x00008];
2693 /* -------------- */
2694 pseudo_bit_t l_key[0x00020]; /* Memory key (L_Key) to be used to access CQ */
2695 /* -------------- */
2696 pseudo_bit_t last_notified_indx[0x00020];/* Maintained by HW.
2697 Valid for QUERY_CQ and HW2SW_CQ commands only. */
2698 /* -------------- */
2699 pseudo_bit_t solicit_producer_indx[0x00020];/* Maintained by HW.
2700 Valid for QUERY_CQ and HW2SW_CQ commands only.
2702 /* -------------- */
2703 pseudo_bit_t consumer_counter[0x00020];/* Consumer counter is a 32bits counter that is incremented for each CQE pooled from the CQ.
2704 Must be 0x0 in CQ initialization.
2705 Valid for the QUERY_CQ and HW2SW_CQ commands only. */
2706 /* -------------- */
2707 pseudo_bit_t producer_counter[0x00020];/* Producer counter is a 32bits counter that is incremented for each CQE that is written by the HW to the CQ.
2708 CQ overrun is reported if Producer_counter + 1 equals to Consumer_counter and a CQE needs to be added..
2709 Maintained by HW (valid for the QUERY_CQ and HW2SW_CQ commands only) */
2710 /* -------------- */
2711 pseudo_bit_t cqn[0x00018]; /* CQ number. Least significant bits are constrained by the position of this CQ in CQC table
2712 Valid for the QUERY_CQ and HW2SW_CQ commands only */
2713 pseudo_bit_t reserved7[0x00008];
2714 /* -------------- */
2715 pseudo_bit_t cq_ci_db_record[0x00020];/* Index in the UAR Context Table Entry.
2716 HW uses this index as an offset from the UAR Context Table Entry in order to read this CQ Consumer Counter doorbell record.
2717 This value can be retrieved from the HW in the QUERY_CQ command. */
2718 /* -------------- */
2719 pseudo_bit_t cq_state_db_record[0x00020];/* Index in the UAR Context Table Entry.
2720 HW uses this index as an offset from the UAR Context Table Entry in order to read this CQ state doorbell record.
2721 This value can be retrieved from the HW in the QUERY_CQ command. */
2722 /* -------------- */
2723 pseudo_bit_t reserved8[0x00020];
2724 /* -------------- */
2727 /* GPIO_event_data */
2729 struct arbelprm_gpio_event_data_st { /* Little Endian */
2730 pseudo_bit_t reserved0[0x00060];
2731 /* -------------- */
2732 pseudo_bit_t gpio_event_hi[0x00020];/* If any bit is set to 1, then a rising/falling event has occurred on the corrsponding GPIO pin. */
2733 /* -------------- */
2734 pseudo_bit_t gpio_event_lo[0x00020];/* If any bit is set to 1, then a rising/falling event has occurred on the corrsponding GPIO pin. */
2735 /* -------------- */
2736 pseudo_bit_t reserved1[0x00020];
2737 /* -------------- */
2740 /* Event_data Field - QP/EE Events */
2742 struct arbelprm_qp_ee_event_st { /* Little Endian */
2743 pseudo_bit_t qpn_een[0x00018]; /* QP/EE/SRQ number event is reported for */
2744 pseudo_bit_t reserved0[0x00008];
2745 /* -------------- */
2746 pseudo_bit_t reserved1[0x00020];
2747 /* -------------- */
2748 pseudo_bit_t reserved2[0x0001c];
2749 pseudo_bit_t e_q[0x00001]; /* If set - EEN if cleared - QP in the QPN/EEN field
2750 Not valid on SRQ events */
2751 pseudo_bit_t reserved3[0x00003];
2752 /* -------------- */
2753 pseudo_bit_t reserved4[0x00060];
2754 /* -------------- */
2757 /* InfiniHost-III-EX Type0 Configuration Header */
2759 struct arbelprm_mt25208_type0_st { /* Little Endian */
2760 pseudo_bit_t vendor_id[0x00010]; /* Hardwired to 0x15B3 */
2761 pseudo_bit_t device_id[0x00010]; /* 25208 (decimal) - InfiniHost-III compatible mode
2762 25218 (decimal) - InfiniHost-III EX mode (the mode described in this manual)
2763 25209 (decimal) - Flash burner mode - see Flash burning application note for further details on this mode
2765 /* -------------- */
2766 pseudo_bit_t command[0x00010]; /* PCI Command Register */
2767 pseudo_bit_t status[0x00010]; /* PCI Status Register */
2768 /* -------------- */
2769 pseudo_bit_t revision_id[0x00008];
2770 pseudo_bit_t class_code_hca_class_code[0x00018];
2771 /* -------------- */
2772 pseudo_bit_t cache_line_size[0x00008];/* Cache Line Size */
2773 pseudo_bit_t latency_timer[0x00008];
2774 pseudo_bit_t header_type[0x00008]; /* hardwired to zero */
2775 pseudo_bit_t bist[0x00008];
2776 /* -------------- */
2777 pseudo_bit_t bar0_ctrl[0x00004]; /* hard-wired to 0100 */
2778 pseudo_bit_t reserved0[0x00010];
2779 pseudo_bit_t bar0_l[0x0000c]; /* Lower bits of BAR0 (Device Configuration Space) */
2780 /* -------------- */
2781 pseudo_bit_t bar0_h[0x00020]; /* Upper 32 bits of BAR0 (Device Configuration Space) */
2782 /* -------------- */
2783 pseudo_bit_t bar1_ctrl[0x00004]; /* Hardwired to 1100 */
2784 pseudo_bit_t reserved1[0x00010];
2785 pseudo_bit_t bar1_l[0x0000c]; /* Lower bits of BAR1 (User Access Region - UAR - space) */
2786 /* -------------- */
2787 pseudo_bit_t bar1_h[0x00020]; /* upper 32 bits of BAR1 (User Access Region - UAR - space) */
2788 /* -------------- */
2789 pseudo_bit_t bar2_ctrl[0x00004]; /* Hardwired to 1100 */
2790 pseudo_bit_t reserved2[0x00010];
2791 pseudo_bit_t bar2_l[0x0000c]; /* Lower bits of BAR2 - Local Attached Memory if present and enabled. Else zeroed. */
2792 /* -------------- */
2793 pseudo_bit_t bar2_h[0x00020]; /* Upper 32 bits of BAR2 - Local Attached Memory if present and enabled. Else zeroed. */
2794 /* -------------- */
2795 pseudo_bit_t cardbus_cis_pointer[0x00020];
2796 /* -------------- */
2797 pseudo_bit_t subsystem_vendor_id[0x00010];/* Specified by the device NVMEM configuration */
2798 pseudo_bit_t subsystem_id[0x00010]; /* Specified by the device NVMEM configuration */
2799 /* -------------- */
2800 pseudo_bit_t expansion_rom_enable[0x00001];/* Expansion ROM Enable. Hardwired to 0 if expansion ROM is disabled in the device NVMEM configuration. */
2801 pseudo_bit_t reserved3[0x0000a];
2802 pseudo_bit_t expansion_rom_base_address[0x00015];/* Expansion ROM Base Address (upper 21 bit). Hardwired to 0 if expansion ROM is disabled in the device NVMEM configuration. */
2803 /* -------------- */
2804 pseudo_bit_t capabilities_pointer[0x00008];/* Specified by the device NVMEM configuration */
2805 pseudo_bit_t reserved4[0x00018];
2806 /* -------------- */
2807 pseudo_bit_t reserved5[0x00020];
2808 /* -------------- */
2809 pseudo_bit_t interrupt_line[0x00008];
2810 pseudo_bit_t interrupt_pin[0x00008];
2811 pseudo_bit_t min_gnt[0x00008];
2812 pseudo_bit_t max_latency[0x00008];
2813 /* -------------- */
2814 pseudo_bit_t reserved6[0x00100];
2815 /* -------------- */
2816 pseudo_bit_t msi_cap_id[0x00008];
2817 pseudo_bit_t msi_next_cap_ptr[0x00008];
2818 pseudo_bit_t msi_en[0x00001];
2819 pseudo_bit_t multiple_msg_cap[0x00003];
2820 pseudo_bit_t multiple_msg_en[0x00003];
2821 pseudo_bit_t cap_64_bit_addr[0x00001];
2822 pseudo_bit_t reserved7[0x00008];
2823 /* -------------- */
2824 pseudo_bit_t msg_addr_l[0x00020];
2825 /* -------------- */
2826 pseudo_bit_t msg_addr_h[0x00020];
2827 /* -------------- */
2828 pseudo_bit_t msg_data[0x00010];
2829 pseudo_bit_t reserved8[0x00010];
2830 /* -------------- */
2831 pseudo_bit_t reserved9[0x00080];
2832 /* -------------- */
2833 pseudo_bit_t pm_cap_id[0x00008]; /* Power management capability ID - 01h */
2834 pseudo_bit_t pm_next_cap_ptr[0x00008];
2835 pseudo_bit_t pm_cap[0x00010]; /* [2:0] Version - 02h
2838 [5] Device specific initialization - 0h
2839 [8:6] AUX current - 0h
2841 [10] D2 support - 0h
2842 [15:11] PME support - 0h */
2843 /* -------------- */
2844 pseudo_bit_t pm_status_control[0x00010];/* [14:13] - Data scale - 0h */
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