[ath5k] Add support for non-802.11n Atheros wireless NICs
authorJoshua Oreman <oremanj@rwcr.net>
Fri, 7 Aug 2009 09:25:35 +0000 (02:25 -0700)
committerMichael Brown <mcb30@etherboot.org>
Sat, 8 Aug 2009 23:16:13 +0000 (00:16 +0100)
Signed-off-by: Michael Brown <mcb30@etherboot.org>
21 files changed:
src/Makefile
src/drivers/net/ath5k/ath5k.c [new file with mode: 0644]
src/drivers/net/ath5k/ath5k.h [new file with mode: 0644]
src/drivers/net/ath5k/ath5k_attach.c [new file with mode: 0644]
src/drivers/net/ath5k/ath5k_caps.c [new file with mode: 0644]
src/drivers/net/ath5k/ath5k_desc.c [new file with mode: 0644]
src/drivers/net/ath5k/ath5k_dma.c [new file with mode: 0644]
src/drivers/net/ath5k/ath5k_eeprom.c [new file with mode: 0644]
src/drivers/net/ath5k/ath5k_gpio.c [new file with mode: 0644]
src/drivers/net/ath5k/ath5k_initvals.c [new file with mode: 0644]
src/drivers/net/ath5k/ath5k_pcu.c [new file with mode: 0644]
src/drivers/net/ath5k/ath5k_phy.c [new file with mode: 0644]
src/drivers/net/ath5k/ath5k_qcu.c [new file with mode: 0644]
src/drivers/net/ath5k/ath5k_reset.c [new file with mode: 0644]
src/drivers/net/ath5k/base.h [new file with mode: 0644]
src/drivers/net/ath5k/desc.h [new file with mode: 0644]
src/drivers/net/ath5k/eeprom.h [new file with mode: 0644]
src/drivers/net/ath5k/reg.h [new file with mode: 0644]
src/drivers/net/ath5k/rfbuffer.h [new file with mode: 0644]
src/drivers/net/ath5k/rfgain.h [new file with mode: 0644]
src/include/gpxe/errfile.h

index b246faa..0dbe8d3 100644 (file)
@@ -62,6 +62,7 @@ SRCDIRS               += drivers/net
 SRCDIRS                += drivers/net/e1000
 SRCDIRS                += drivers/net/phantom
 SRCDIRS                += drivers/net/rtl818x
+SRCDIRS                += drivers/net/ath5k
 SRCDIRS                += drivers/block
 SRCDIRS                += drivers/nvs
 SRCDIRS                += drivers/bitbash
diff --git a/src/drivers/net/ath5k/ath5k.c b/src/drivers/net/ath5k/ath5k.c
new file mode 100644 (file)
index 0000000..5101a54
--- /dev/null
@@ -0,0 +1,1694 @@
+/*
+ * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
+ * Copyright (c) 2004-2005 Atheros Communications, Inc.
+ * Copyright (c) 2006 Devicescape Software, Inc.
+ * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
+ * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
+ *
+ * Modified for gPXE, July 2009, by Joshua Oreman <oremanj@rwcr.net>
+ * Original from Linux kernel 2.6.30.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer,
+ *    without modification.
+ * 2. Redistributions in binary form must reproduce at minimum a disclaimer
+ *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
+ *    redistribution must be conditioned upon including a substantially
+ *    similar Disclaimer requirement for further binary redistribution.
+ * 3. Neither the names of the above-listed copyright holders nor the names
+ *    of any contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
+ *
+ * NO WARRANTY
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
+ * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.
+ *
+ */
+
+FILE_LICENCE ( BSD3 );
+
+#include <stdlib.h>
+#include <gpxe/malloc.h>
+#include <gpxe/timer.h>
+#include <gpxe/netdevice.h>
+#include <gpxe/pci.h>
+#include <gpxe/pci_io.h>
+
+#include "base.h"
+#include "reg.h"
+
+#define ATH5K_CALIB_INTERVAL   10 /* Calibrate PHY every 10 seconds */
+#define ATH5K_RETRIES          4  /* Number of times to retry packet sends */
+#define ATH5K_DESC_ALIGN       16 /* Alignment for TX/RX descriptors */
+
+/******************\
+* Internal defines *
+\******************/
+
+/* Known PCI ids */
+static struct pci_device_id ath5k_nics[] = {
+       PCI_ROM(0x168c, 0x0207, "ath5210e", "Atheros 5210 early", AR5K_AR5210),
+       PCI_ROM(0x168c, 0x0007, "ath5210", "Atheros 5210", AR5K_AR5210),
+       PCI_ROM(0x168c, 0x0011, "ath5311", "Atheros 5311 (AHB)", AR5K_AR5211),
+       PCI_ROM(0x168c, 0x0012, "ath5211", "Atheros 5211", AR5K_AR5211),
+       PCI_ROM(0x168c, 0x0013, "ath5212", "Atheros 5212", AR5K_AR5212),
+       PCI_ROM(0xa727, 0x0013, "ath5212c","3com Ath 5212", AR5K_AR5212),
+       PCI_ROM(0x10b7, 0x0013, "rdag675", "3com 3CRDAG675", AR5K_AR5212),
+       PCI_ROM(0x168c, 0x1014, "ath5212m", "Ath 5212 miniPCI", AR5K_AR5212),
+       PCI_ROM(0x168c, 0x0014, "ath5212x14", "Atheros 5212 x14", AR5K_AR5212),
+       PCI_ROM(0x168c, 0x0015, "ath5212x15", "Atheros 5212 x15", AR5K_AR5212),
+       PCI_ROM(0x168c, 0x0016, "ath5212x16", "Atheros 5212 x16", AR5K_AR5212),
+       PCI_ROM(0x168c, 0x0017, "ath5212x17", "Atheros 5212 x17", AR5K_AR5212),
+       PCI_ROM(0x168c, 0x0018, "ath5212x18", "Atheros 5212 x18", AR5K_AR5212),
+       PCI_ROM(0x168c, 0x0019, "ath5212x19", "Atheros 5212 x19", AR5K_AR5212),
+       PCI_ROM(0x168c, 0x001a, "ath2413", "Atheros 2413 Griffin", AR5K_AR5212),
+       PCI_ROM(0x168c, 0x001b, "ath5413", "Atheros 5413 Eagle", AR5K_AR5212),
+       PCI_ROM(0x168c, 0x001c, "ath5212e", "Atheros 5212 PCI-E", AR5K_AR5212),
+       PCI_ROM(0x168c, 0x001d, "ath2417", "Atheros 2417 Nala", AR5K_AR5212),
+};
+
+/* Known SREVs */
+static const struct ath5k_srev_name srev_names[] = {
+       { "5210",       AR5K_VERSION_MAC,       AR5K_SREV_AR5210 },
+       { "5311",       AR5K_VERSION_MAC,       AR5K_SREV_AR5311 },
+       { "5311A",      AR5K_VERSION_MAC,       AR5K_SREV_AR5311A },
+       { "5311B",      AR5K_VERSION_MAC,       AR5K_SREV_AR5311B },
+       { "5211",       AR5K_VERSION_MAC,       AR5K_SREV_AR5211 },
+       { "5212",       AR5K_VERSION_MAC,       AR5K_SREV_AR5212 },
+       { "5213",       AR5K_VERSION_MAC,       AR5K_SREV_AR5213 },
+       { "5213A",      AR5K_VERSION_MAC,       AR5K_SREV_AR5213A },
+       { "2413",       AR5K_VERSION_MAC,       AR5K_SREV_AR2413 },
+       { "2414",       AR5K_VERSION_MAC,       AR5K_SREV_AR2414 },
+       { "5424",       AR5K_VERSION_MAC,       AR5K_SREV_AR5424 },
+       { "5413",       AR5K_VERSION_MAC,       AR5K_SREV_AR5413 },
+       { "5414",       AR5K_VERSION_MAC,       AR5K_SREV_AR5414 },
+       { "2415",       AR5K_VERSION_MAC,       AR5K_SREV_AR2415 },
+       { "5416",       AR5K_VERSION_MAC,       AR5K_SREV_AR5416 },
+       { "5418",       AR5K_VERSION_MAC,       AR5K_SREV_AR5418 },
+       { "2425",       AR5K_VERSION_MAC,       AR5K_SREV_AR2425 },
+       { "2417",       AR5K_VERSION_MAC,       AR5K_SREV_AR2417 },
+       { "xxxxx",      AR5K_VERSION_MAC,       AR5K_SREV_UNKNOWN },
+       { "5110",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5110 },
+       { "5111",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5111 },
+       { "5111A",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_5111A },
+       { "2111",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2111 },
+       { "5112",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5112 },
+       { "5112A",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_5112A },
+       { "5112B",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_5112B },
+       { "2112",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2112 },
+       { "2112A",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_2112A },
+       { "2112B",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_2112B },
+       { "2413",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2413 },
+       { "5413",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5413 },
+       { "2316",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2316 },
+       { "2317",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2317 },
+       { "5424",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5424 },
+       { "5133",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5133 },
+       { "xxxxx",      AR5K_VERSION_RAD,       AR5K_SREV_UNKNOWN },
+};
+
+#define ATH5K_SPMBL_NO   1
+#define ATH5K_SPMBL_YES  2
+#define ATH5K_SPMBL_BOTH 3
+
+static const struct {
+       u16 bitrate;
+       u8 short_pmbl;
+       u8 hw_code;
+} ath5k_rates[] = {
+       { 10, ATH5K_SPMBL_BOTH, ATH5K_RATE_CODE_1M },
+       { 20, ATH5K_SPMBL_NO, ATH5K_RATE_CODE_2M },
+       { 55, ATH5K_SPMBL_NO, ATH5K_RATE_CODE_5_5M },
+       { 110, ATH5K_SPMBL_NO, ATH5K_RATE_CODE_11M },
+       { 60, ATH5K_SPMBL_BOTH, ATH5K_RATE_CODE_6M },
+       { 90, ATH5K_SPMBL_BOTH, ATH5K_RATE_CODE_9M },
+       { 120, ATH5K_SPMBL_BOTH, ATH5K_RATE_CODE_12M },
+       { 180, ATH5K_SPMBL_BOTH, ATH5K_RATE_CODE_18M },
+       { 240, ATH5K_SPMBL_BOTH, ATH5K_RATE_CODE_24M },
+       { 360, ATH5K_SPMBL_BOTH, ATH5K_RATE_CODE_36M },
+       { 480, ATH5K_SPMBL_BOTH, ATH5K_RATE_CODE_48M },
+       { 540, ATH5K_SPMBL_BOTH, ATH5K_RATE_CODE_54M },
+       { 20, ATH5K_SPMBL_YES, ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE },
+       { 55, ATH5K_SPMBL_YES, ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE },
+       { 110, ATH5K_SPMBL_YES, ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE },
+       { 0, 0, 0 },
+};
+
+#define ATH5K_NR_RATES 15
+
+/*
+ * Prototypes - PCI stack related functions
+ */
+static int             ath5k_probe(struct pci_device *pdev,
+                                   const struct pci_device_id *id);
+static void            ath5k_remove(struct pci_device *pdev);
+
+struct pci_driver ath5k_pci_driver __pci_driver = {
+       .ids            = ath5k_nics,
+       .id_count       = sizeof(ath5k_nics) / sizeof(ath5k_nics[0]),
+       .probe          = ath5k_probe,
+       .remove         = ath5k_remove,
+};
+
+
+
+/*
+ * Prototypes - MAC 802.11 stack related functions
+ */
+static int ath5k_tx(struct net80211_device *dev, struct io_buffer *skb);
+static int ath5k_reset(struct ath5k_softc *sc, struct net80211_channel *chan);
+static int ath5k_reset_wake(struct ath5k_softc *sc);
+static int ath5k_start(struct net80211_device *dev);
+static void ath5k_stop(struct net80211_device *dev);
+static int ath5k_config(struct net80211_device *dev, int changed);
+static void ath5k_poll(struct net80211_device *dev);
+static void ath5k_irq(struct net80211_device *dev, int enable);
+
+static struct net80211_device_operations ath5k_ops = {
+       .open           = ath5k_start,
+       .close          = ath5k_stop,
+       .transmit       = ath5k_tx,
+       .poll           = ath5k_poll,
+       .irq            = ath5k_irq,
+       .config         = ath5k_config,
+};
+
+/*
+ * Prototypes - Internal functions
+ */
+/* Attach detach */
+static int     ath5k_attach(struct net80211_device *dev);
+static void    ath5k_detach(struct net80211_device *dev);
+/* Channel/mode setup */
+static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
+                               struct net80211_channel *channels,
+                               unsigned int mode,
+                               unsigned int max);
+static int     ath5k_setup_bands(struct net80211_device *dev);
+static int     ath5k_chan_set(struct ath5k_softc *sc,
+                               struct net80211_channel *chan);
+static void    ath5k_setcurmode(struct ath5k_softc *sc,
+                               unsigned int mode);
+static void    ath5k_mode_setup(struct ath5k_softc *sc);
+
+/* Descriptor setup */
+static int     ath5k_desc_alloc(struct ath5k_softc *sc);
+static void    ath5k_desc_free(struct ath5k_softc *sc);
+/* Buffers setup */
+static int     ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf);
+static int     ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf);
+
+static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
+                                   struct ath5k_buf *bf)
+{
+       if (!bf->iob)
+               return;
+
+       net80211_tx_complete(sc->dev, bf->iob, 0, ECANCELED);
+       bf->iob = NULL;
+}
+
+static inline void ath5k_rxbuf_free(struct ath5k_softc *sc __unused,
+                                   struct ath5k_buf *bf)
+{
+       free_iob(bf->iob);
+       bf->iob = NULL;
+}
+
+/* Queues setup */
+static int     ath5k_txq_setup(struct ath5k_softc *sc,
+                                          int qtype, int subtype);
+static void    ath5k_txq_drainq(struct ath5k_softc *sc,
+                                struct ath5k_txq *txq);
+static void    ath5k_txq_cleanup(struct ath5k_softc *sc);
+static void    ath5k_txq_release(struct ath5k_softc *sc);
+/* Rx handling */
+static int     ath5k_rx_start(struct ath5k_softc *sc);
+static void    ath5k_rx_stop(struct ath5k_softc *sc);
+/* Tx handling */
+static void    ath5k_tx_processq(struct ath5k_softc *sc,
+                                 struct ath5k_txq *txq);
+
+/* Interrupt handling */
+static int     ath5k_init(struct ath5k_softc *sc);
+static int     ath5k_stop_hw(struct ath5k_softc *sc);
+
+static void    ath5k_calibrate(struct ath5k_softc *sc);
+
+/* Filter */
+static void    ath5k_configure_filter(struct ath5k_softc *sc);
+
+/********************\
+* PCI Initialization *
+\********************/
+
+#if DBGLVL_MAX
+static const char *
+ath5k_chip_name(enum ath5k_srev_type type, u16 val)
+{
+       const char *name = "xxxxx";
+       unsigned int i;
+
+       for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
+               if (srev_names[i].sr_type != type)
+                       continue;
+
+               if ((val & 0xf0) == srev_names[i].sr_val)
+                       name = srev_names[i].sr_name;
+
+               if ((val & 0xff) == srev_names[i].sr_val) {
+                       name = srev_names[i].sr_name;
+                       break;
+               }
+       }
+
+       return name;
+}
+#endif
+
+static int ath5k_probe(struct pci_device *pdev,
+                      const struct pci_device_id *id)
+{
+       void *mem;
+       struct ath5k_softc *sc;
+       struct net80211_device *dev;
+       int ret;
+       u8 csz;
+
+       adjust_pci_device(pdev);
+
+       /*
+        * Cache line size is used to size and align various
+        * structures used to communicate with the hardware.
+        */
+       pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
+       if (csz == 0) {
+               /*
+                * We must have this setup properly for rx buffer
+                * DMA to work so force a reasonable value here if it
+                * comes up zero.
+                */
+               pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 16);
+       }
+       /*
+        * The default setting of latency timer yields poor results,
+        * set it to the value used by other systems.  It may be worth
+        * tweaking this setting more.
+        */
+       pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
+
+       /*
+        * Disable the RETRY_TIMEOUT register (0x41) to keep
+        * PCI Tx retries from interfering with C3 CPU state.
+        */
+       pci_write_config_byte(pdev, 0x41, 0);
+
+       mem = ioremap(pdev->membase, 0x10000);
+       if (!mem) {
+               DBG("ath5k: cannot remap PCI memory region\n");
+               ret = -EIO;
+               goto err;
+       }
+
+       /*
+        * Allocate dev (net80211 main struct)
+        * and dev->priv (driver private data)
+        */
+       dev = net80211_alloc(sizeof(*sc));
+       if (!dev) {
+               DBG("ath5k: cannot allocate 802.11 device\n");
+               ret = -ENOMEM;
+               goto err_map;
+       }
+
+       /* Initialize driver private data */
+       sc = dev->priv;
+       sc->dev = dev;
+       sc->pdev = pdev;
+
+       sc->hwinfo = zalloc(sizeof(*sc->hwinfo));
+       if (!sc->hwinfo) {
+               DBG("ath5k: cannot allocate 802.11 hardware info structure\n");
+               ret = -ENOMEM;
+               goto err_free;
+       }
+
+       sc->hwinfo->flags = NET80211_HW_RX_HAS_FCS;
+       sc->hwinfo->signal_type = NET80211_SIGNAL_DB;
+       sc->hwinfo->signal_max = 40; /* 35dB should give perfect 54Mbps */
+       sc->hwinfo->channel_change_time = 5000;
+
+       /* Avoid working with the device until setup is complete */
+       sc->status |= ATH_STAT_INVALID;
+
+       sc->iobase = mem;
+       sc->cachelsz = csz * 4; /* convert to bytes */
+
+       DBG("ath5k: register base at %p (%08lx)\n", sc->iobase, pdev->membase);
+       DBG("ath5k: cache line size %d\n", sc->cachelsz);
+
+       /* Set private data */
+       pci_set_drvdata(pdev, dev);
+       dev->netdev->dev = (struct device *)pdev;
+
+       /* Initialize device */
+       ret = ath5k_hw_attach(sc, id->driver_data, &sc->ah);
+       if (ret)
+               goto err_free_hwinfo;
+
+       /* Finish private driver data initialization */
+       ret = ath5k_attach(dev);
+       if (ret)
+               goto err_ah;
+
+#if DBGLVL_MAX
+       DBG("Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
+           ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
+           sc->ah->ah_mac_srev, sc->ah->ah_phy_revision);
+
+       if (!sc->ah->ah_single_chip) {
+               /* Single chip radio (!RF5111) */
+               if (sc->ah->ah_radio_5ghz_revision &&
+                   !sc->ah->ah_radio_2ghz_revision) {
+                       /* No 5GHz support -> report 2GHz radio */
+                       if (!(sc->ah->ah_capabilities.cap_mode & AR5K_MODE_BIT_11A)) {
+                               DBG("RF%s 2GHz radio found (0x%x)\n",
+                                   ath5k_chip_name(AR5K_VERSION_RAD,
+                                                   sc->ah->ah_radio_5ghz_revision),
+                                   sc->ah->ah_radio_5ghz_revision);
+                       /* No 2GHz support (5110 and some
+                        * 5Ghz only cards) -> report 5Ghz radio */
+                       } else if (!(sc->ah->ah_capabilities.cap_mode & AR5K_MODE_BIT_11B)) {
+                               DBG("RF%s 5GHz radio found (0x%x)\n",
+                                   ath5k_chip_name(AR5K_VERSION_RAD,
+                                                   sc->ah->ah_radio_5ghz_revision),
+                                   sc->ah->ah_radio_5ghz_revision);
+                       /* Multiband radio */
+                       } else {
+                               DBG("RF%s multiband radio found (0x%x)\n",
+                                   ath5k_chip_name(AR5K_VERSION_RAD,
+                                                   sc->ah->ah_radio_5ghz_revision),
+                                   sc->ah->ah_radio_5ghz_revision);
+                       }
+               }
+               /* Multi chip radio (RF5111 - RF2111) ->
+                * report both 2GHz/5GHz radios */
+               else if (sc->ah->ah_radio_5ghz_revision &&
+                        sc->ah->ah_radio_2ghz_revision) {
+                       DBG("RF%s 5GHz radio found (0x%x)\n",
+                           ath5k_chip_name(AR5K_VERSION_RAD,
+                                           sc->ah->ah_radio_5ghz_revision),
+                           sc->ah->ah_radio_5ghz_revision);
+                       DBG("RF%s 2GHz radio found (0x%x)\n",
+                           ath5k_chip_name(AR5K_VERSION_RAD,
+                                           sc->ah->ah_radio_2ghz_revision),
+                           sc->ah->ah_radio_2ghz_revision);
+               }
+       }
+#endif
+
+       /* Ready to go */
+       sc->status &= ~ATH_STAT_INVALID;
+
+       return 0;
+err_ah:
+       ath5k_hw_detach(sc->ah);
+err_free_hwinfo:
+       free(sc->hwinfo);
+err_free:
+       net80211_free(dev);
+err_map:
+       iounmap(mem);
+err:
+       return ret;
+}
+
+static void ath5k_remove(struct pci_device *pdev)
+{
+       struct net80211_device *dev = pci_get_drvdata(pdev);
+       struct ath5k_softc *sc = dev->priv;
+
+       ath5k_detach(dev);
+       ath5k_hw_detach(sc->ah);
+       iounmap(sc->iobase);
+       free(sc->hwinfo);
+       net80211_free(dev);
+}
+
+
+/***********************\
+* Driver Initialization *
+\***********************/
+
+static int
+ath5k_attach(struct net80211_device *dev)
+{
+       struct ath5k_softc *sc = dev->priv;
+       struct ath5k_hw *ah = sc->ah;
+       int ret;
+
+       /*
+        * Collect the channel list.  The 802.11 layer
+        * is resposible for filtering this list based
+        * on settings like the phy mode and regulatory
+        * domain restrictions.
+        */
+       ret = ath5k_setup_bands(dev);
+       if (ret) {
+               DBG("ath5k: can't get channels\n");
+               goto err;
+       }
+
+       /* NB: setup here so ath5k_rate_update is happy */
+       if (ah->ah_modes & AR5K_MODE_BIT_11A)
+               ath5k_setcurmode(sc, AR5K_MODE_11A);
+       else
+               ath5k_setcurmode(sc, AR5K_MODE_11B);
+
+       /*
+        * Allocate tx+rx descriptors and populate the lists.
+        */
+       ret = ath5k_desc_alloc(sc);
+       if (ret) {
+               DBG("ath5k: can't allocate descriptors\n");
+               goto err;
+       }
+
+       /*
+        * Allocate hardware transmit queues. Note that hw functions
+        * handle reseting these queues at the needed time.
+        */
+       ret = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
+       if (ret) {
+               DBG("ath5k: can't setup xmit queue\n");
+               goto err_desc;
+       }
+
+       sc->last_calib_ticks = currticks();
+
+       ret = ath5k_eeprom_read_mac(ah, sc->hwinfo->hwaddr);
+       if (ret) {
+               DBG("ath5k: unable to read address from EEPROM: 0x%04x\n",
+                   sc->pdev->device);
+               goto err_queues;
+       }
+
+       memset(sc->bssidmask, 0xff, ETH_ALEN);
+       ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
+
+       ret = net80211_register(sc->dev, &ath5k_ops, sc->hwinfo);
+       if (ret) {
+               DBG("ath5k: can't register ieee80211 hw\n");
+               goto err_queues;
+       }
+
+       return 0;
+err_queues:
+       ath5k_txq_release(sc);
+err_desc:
+       ath5k_desc_free(sc);
+err:
+       return ret;
+}
+
+static void
+ath5k_detach(struct net80211_device *dev)
+{
+       struct ath5k_softc *sc = dev->priv;
+
+       net80211_unregister(dev);
+       ath5k_desc_free(sc);
+       ath5k_txq_release(sc);
+}
+
+
+
+
+/********************\
+* Channel/mode setup *
+\********************/
+
+/*
+ * Convert IEEE channel number to MHz frequency.
+ */
+static inline short
+ath5k_ieee2mhz(short chan)
+{
+       if (chan < 14)
+               return 2407 + 5 * chan;
+       if (chan == 14)
+               return 2484;
+       if (chan < 27)
+               return 2212 + 20 * chan;
+       return 5000 + 5 * chan;
+}
+
+static unsigned int
+ath5k_copy_channels(struct ath5k_hw *ah,
+                   struct net80211_channel *channels,
+                   unsigned int mode, unsigned int max)
+{
+       unsigned int i, count, size, chfreq, freq, ch;
+
+       if (!(ah->ah_modes & (1 << mode)))
+               return 0;
+
+       switch (mode) {
+       case AR5K_MODE_11A:
+       case AR5K_MODE_11A_TURBO:
+               /* 1..220, but 2GHz frequencies are filtered by check_channel */
+               size = 220;
+               chfreq = CHANNEL_5GHZ;
+               break;
+       case AR5K_MODE_11B:
+       case AR5K_MODE_11G:
+       case AR5K_MODE_11G_TURBO:
+               size = 26;
+               chfreq = CHANNEL_2GHZ;
+               break;
+       default:
+               return 0;
+       }
+
+       for (i = 0, count = 0; i < size && max > 0; i++) {
+               ch = i + 1 ;
+               freq = ath5k_ieee2mhz(ch);
+
+               /* Check if channel is supported by the chipset */
+               if (!ath5k_channel_ok(ah, freq, chfreq))
+                       continue;
+
+               /* Write channel info and increment counter */
+               channels[count].center_freq = freq;
+               channels[count].maxpower = 0; /* use regulatory */
+               channels[count].band = (chfreq == CHANNEL_2GHZ) ?
+                       NET80211_BAND_2GHZ : NET80211_BAND_5GHZ;
+               switch (mode) {
+               case AR5K_MODE_11A:
+               case AR5K_MODE_11G:
+                       channels[count].hw_value = chfreq | CHANNEL_OFDM;
+                       break;
+               case AR5K_MODE_11A_TURBO:
+               case AR5K_MODE_11G_TURBO:
+                       channels[count].hw_value = chfreq |
+                               CHANNEL_OFDM | CHANNEL_TURBO;
+                       break;
+               case AR5K_MODE_11B:
+                       channels[count].hw_value = CHANNEL_B;
+               }
+
+               count++;
+               max--;
+       }
+
+       return count;
+}
+
+static int
+ath5k_setup_bands(struct net80211_device *dev)
+{
+       struct ath5k_softc *sc = dev->priv;
+       struct ath5k_hw *ah = sc->ah;
+       int max_c, count_c = 0;
+       int i;
+       int band;
+
+       max_c = sizeof(sc->hwinfo->channels) / sizeof(sc->hwinfo->channels[0]);
+
+       /* 2GHz band */
+       if (sc->ah->ah_capabilities.cap_mode & AR5K_MODE_BIT_11G) {
+               /* G mode */
+               band = NET80211_BAND_2GHZ;
+               sc->hwinfo->bands = NET80211_BAND_BIT_2GHZ;
+               sc->hwinfo->modes = (NET80211_MODE_G | NET80211_MODE_B);
+
+               for (i = 0; i < 12; i++)
+                       sc->hwinfo->rates[band][i] = ath5k_rates[i].bitrate;
+               sc->hwinfo->nr_rates[band] = 12;
+
+               sc->hwinfo->nr_channels =
+                       ath5k_copy_channels(ah, sc->hwinfo->channels,
+                                           AR5K_MODE_11G, max_c);
+               count_c = sc->hwinfo->nr_channels;
+               max_c -= count_c;
+       } else if (sc->ah->ah_capabilities.cap_mode & AR5K_MODE_BIT_11B) {
+               /* B mode */
+               band = NET80211_BAND_2GHZ;
+               sc->hwinfo->bands = NET80211_BAND_BIT_2GHZ;
+               sc->hwinfo->modes = NET80211_MODE_B;
+
+               for (i = 0; i < 4; i++)
+                       sc->hwinfo->rates[band][i] = ath5k_rates[i].bitrate;
+               sc->hwinfo->nr_rates[band] = 4;
+
+               sc->hwinfo->nr_channels =
+                       ath5k_copy_channels(ah, sc->hwinfo->channels,
+                                           AR5K_MODE_11B, max_c);
+               count_c = sc->hwinfo->nr_channels;
+               max_c -= count_c;
+       }
+
+       /* 5GHz band, A mode */
+       if (sc->ah->ah_capabilities.cap_mode & AR5K_MODE_BIT_11A) {
+               band = NET80211_BAND_5GHZ;
+               sc->hwinfo->bands |= NET80211_BAND_BIT_5GHZ;
+               sc->hwinfo->modes |= NET80211_MODE_A;
+
+               for (i = 0; i < 8; i++)
+                       sc->hwinfo->rates[band][i] = ath5k_rates[i+4].bitrate;
+               sc->hwinfo->nr_rates[band] = 8;
+
+               sc->hwinfo->nr_channels =
+                       ath5k_copy_channels(ah, sc->hwinfo->channels,
+                                           AR5K_MODE_11B, max_c);
+               count_c = sc->hwinfo->nr_channels;
+               max_c -= count_c;
+       }
+
+       return 0;
+}
+
+/*
+ * Set/change channels.  If the channel is really being changed,
+ * it's done by reseting the chip.  To accomplish this we must
+ * first cleanup any pending DMA, then restart stuff after a la
+ * ath5k_init.
+ */
+static int
+ath5k_chan_set(struct ath5k_softc *sc, struct net80211_channel *chan)
+{
+       if (chan->center_freq != sc->curchan->center_freq ||
+           chan->hw_value != sc->curchan->hw_value) {
+               /*
+                * To switch channels clear any pending DMA operations;
+                * wait long enough for the RX fifo to drain, reset the
+                * hardware at the new frequency, and then re-enable
+                * the relevant bits of the h/w.
+                */
+               DBG2("ath5k: resetting for channel change (%d -> %d MHz)\n",
+                    sc->curchan->center_freq, chan->center_freq);
+               return ath5k_reset(sc, chan);
+       }
+
+       return 0;
+}
+
+static void
+ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
+{
+       sc->curmode = mode;
+
+       if (mode == AR5K_MODE_11A) {
+               sc->curband = NET80211_BAND_5GHZ;
+       } else {
+               sc->curband = NET80211_BAND_2GHZ;
+       }
+}
+
+static void
+ath5k_mode_setup(struct ath5k_softc *sc)
+{
+       struct ath5k_hw *ah = sc->ah;
+       u32 rfilt;
+
+       /* configure rx filter */
+       rfilt = sc->filter_flags;
+       ath5k_hw_set_rx_filter(ah, rfilt);
+
+       if (ath5k_hw_hasbssidmask(ah))
+               ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
+
+       /* configure operational mode */
+       ath5k_hw_set_opmode(ah);
+
+       ath5k_hw_set_mcast_filter(ah, 0, 0);
+}
+
+static inline int
+ath5k_hw_rix_to_bitrate(int hw_rix)
+{
+       int i;
+
+       for (i = 0; i < ATH5K_NR_RATES; i++) {
+               if (ath5k_rates[i].hw_code == hw_rix)
+                       return ath5k_rates[i].bitrate;
+       }
+
+       DBG("ath5k: invalid rix %02x\n", hw_rix);
+       return 10;              /* use lowest rate */
+}
+
+int ath5k_bitrate_to_hw_rix(int bitrate)
+{
+       int i;
+
+       for (i = 0; i < ATH5K_NR_RATES; i++) {
+               if (ath5k_rates[i].bitrate == bitrate)
+                       return ath5k_rates[i].hw_code;
+       }
+
+       DBG("ath5k: invalid bitrate %d\n", bitrate);
+       return ATH5K_RATE_CODE_1M; /* use lowest rate */
+}
+
+/***************\
+* Buffers setup *
+\***************/
+
+static struct io_buffer *
+ath5k_rx_iob_alloc(struct ath5k_softc *sc, u32 *iob_addr)
+{
+       struct io_buffer *iob;
+       unsigned int off;
+
+       /*
+        * Allocate buffer with headroom_needed space for the
+        * fake physical layer header at the start.
+        */
+       iob = alloc_iob(sc->rxbufsize + sc->cachelsz - 1);
+
+       if (!iob) {
+               DBG("ath5k: can't alloc iobuf of size %d\n",
+                   sc->rxbufsize + sc->cachelsz - 1);
+               return NULL;
+       }
+
+       *iob_addr = virt_to_bus(iob->data);
+
+       /*
+        * Cache-line-align.  This is important (for the
+        * 5210 at least) as not doing so causes bogus data
+        * in rx'd frames.
+        */
+       off = *iob_addr % sc->cachelsz;
+       if (off != 0) {
+               iob_reserve(iob, sc->cachelsz - off);
+               *iob_addr += sc->cachelsz - off;
+       }
+
+       return iob;
+}
+
+static int
+ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
+{
+       struct ath5k_hw *ah = sc->ah;
+       struct io_buffer *iob = bf->iob;
+       struct ath5k_desc *ds;
+
+       if (!iob) {
+               iob = ath5k_rx_iob_alloc(sc, &bf->iobaddr);
+               if (!iob)
+                       return -ENOMEM;
+               bf->iob = iob;
+       }
+
+       /*
+        * Setup descriptors.  For receive we always terminate
+        * the descriptor list with a self-linked entry so we'll
+        * not get overrun under high load (as can happen with a
+        * 5212 when ANI processing enables PHY error frames).
+        *
+        * To insure the last descriptor is self-linked we create
+        * each descriptor as self-linked and add it to the end.  As
+        * each additional descriptor is added the previous self-linked
+        * entry is ``fixed'' naturally.  This should be safe even
+        * if DMA is happening.  When processing RX interrupts we
+        * never remove/process the last, self-linked, entry on the
+        * descriptor list.  This insures the hardware always has
+        * someplace to write a new frame.
+        */
+       ds = bf->desc;
+       ds->ds_link = bf->daddr;        /* link to self */
+       ds->ds_data = bf->iobaddr;
+       if (ah->ah_setup_rx_desc(ah, ds,
+                                iob_tailroom(iob),     /* buffer size */
+                                0) != 0) {
+               DBG("ath5k: error setting up RX descriptor for %d bytes\n", iob_tailroom(iob));
+               return -EINVAL;
+       }
+
+       if (sc->rxlink != NULL)
+               *sc->rxlink = bf->daddr;
+       sc->rxlink = &ds->ds_link;
+       return 0;
+}
+
+static int
+ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
+{
+       struct ath5k_hw *ah = sc->ah;
+       struct ath5k_txq *txq = &sc->txq;
+       struct ath5k_desc *ds = bf->desc;
+       struct io_buffer *iob = bf->iob;
+       unsigned int pktlen, flags;
+       int ret;
+       u16 duration = 0;
+       u16 cts_rate = 0;
+
+       flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
+       bf->iobaddr = virt_to_bus(iob->data);
+       pktlen = iob_len(iob);
+
+       /* FIXME: If we are in g mode and rate is a CCK rate
+        * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
+        * from tx power (value is in dB units already) */
+       if (sc->dev->phy_flags & NET80211_PHY_USE_PROTECTION) {
+               struct net80211_device *dev = sc->dev;
+
+               flags |= AR5K_TXDESC_CTSENA;
+               cts_rate = sc->hw_rtscts_rate;
+               duration = net80211_cts_duration(dev, pktlen);
+       }
+       ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
+                                  IEEE80211_TYP_FRAME_HEADER_LEN,
+                                  AR5K_PKT_TYPE_NORMAL, sc->power_level * 2,
+                                  sc->hw_rate, ATH5K_RETRIES,
+                                  AR5K_TXKEYIX_INVALID, 0, flags,
+                                  cts_rate, duration);
+       if (ret)
+               return ret;
+
+       ds->ds_link = 0;
+       ds->ds_data = bf->iobaddr;
+
+       list_add_tail(&bf->list, &txq->q);
+       if (txq->link == NULL) /* is this first packet? */
+               ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
+       else /* no, so only link it */
+               *txq->link = bf->daddr;
+
+       txq->link = &ds->ds_link;
+       ath5k_hw_start_tx_dma(ah, txq->qnum);
+       mb();
+
+       return 0;
+}
+
+/*******************\
+* Descriptors setup *
+\*******************/
+
+static int
+ath5k_desc_alloc(struct ath5k_softc *sc)
+{
+       struct ath5k_desc *ds;
+       struct ath5k_buf *bf;
+       u32 da;
+       unsigned int i;
+       int ret;
+
+       /* allocate descriptors */
+       sc->desc_len = sizeof(struct ath5k_desc) * (ATH_TXBUF + ATH_RXBUF + 1);
+       sc->desc = malloc_dma(sc->desc_len, ATH5K_DESC_ALIGN);
+       if (sc->desc == NULL) {
+               DBG("ath5k: can't allocate descriptors\n");
+               ret = -ENOMEM;
+               goto err;
+       }
+       memset(sc->desc, 0, sc->desc_len);
+       sc->desc_daddr = virt_to_bus(sc->desc);
+
+       ds = sc->desc;
+       da = sc->desc_daddr;
+
+       bf = calloc(ATH_TXBUF + ATH_RXBUF + 1, sizeof(struct ath5k_buf));
+       if (bf == NULL) {
+               DBG("ath5k: can't allocate buffer pointers\n");
+               ret = -ENOMEM;
+               goto err_free;
+       }
+       sc->bufptr = bf;
+
+       INIT_LIST_HEAD(&sc->rxbuf);
+       for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
+               bf->desc = ds;
+               bf->daddr = da;
+               list_add_tail(&bf->list, &sc->rxbuf);
+       }
+
+       INIT_LIST_HEAD(&sc->txbuf);
+       sc->txbuf_len = ATH_TXBUF;
+       for (i = 0; i < ATH_TXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
+               bf->desc = ds;
+               bf->daddr = da;
+               list_add_tail(&bf->list, &sc->txbuf);
+       }
+
+       return 0;
+
+err_free:
+       free_dma(sc->desc, sc->desc_len);
+err:
+       sc->desc = NULL;
+       return ret;
+}
+
+static void
+ath5k_desc_free(struct ath5k_softc *sc)
+{
+       struct ath5k_buf *bf;
+
+       list_for_each_entry(bf, &sc->txbuf, list)
+               ath5k_txbuf_free(sc, bf);
+       list_for_each_entry(bf, &sc->rxbuf, list)
+               ath5k_rxbuf_free(sc, bf);
+
+       /* Free memory associated with all descriptors */
+       free_dma(sc->desc, sc->desc_len);
+
+       free(sc->bufptr);
+       sc->bufptr = NULL;
+}
+
+
+
+
+
+/**************\
+* Queues setup *
+\**************/
+
+static int
+ath5k_txq_setup(struct ath5k_softc *sc, int qtype, int subtype)
+{
+       struct ath5k_hw *ah = sc->ah;
+       struct ath5k_txq *txq;
+       struct ath5k_txq_info qi = {
+               .tqi_subtype = subtype,
+               .tqi_aifs = AR5K_TXQ_USEDEFAULT,
+               .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
+               .tqi_cw_max = AR5K_TXQ_USEDEFAULT
+       };
+       int qnum;
+
+       /*
+        * Enable interrupts only for EOL and DESC conditions.
+        * We mark tx descriptors to receive a DESC interrupt
+        * when a tx queue gets deep; otherwise waiting for the
+        * EOL to reap descriptors.  Note that this is done to
+        * reduce interrupt load and this only defers reaping
+        * descriptors, never transmitting frames.  Aside from
+        * reducing interrupts this also permits more concurrency.
+        * The only potential downside is if the tx queue backs
+        * up in which case the top half of the kernel may backup
+        * due to a lack of tx descriptors.
+        */
+       qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
+                               AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
+       qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
+       if (qnum < 0) {
+               DBG("ath5k: can't set up a TX queue\n");
+               return -EIO;
+       }
+
+       txq = &sc->txq;
+       if (!txq->setup) {
+               txq->qnum = qnum;
+               txq->link = NULL;
+               INIT_LIST_HEAD(&txq->q);
+               txq->setup = 1;
+       }
+       return 0;
+}
+
+static void
+ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
+{
+       struct ath5k_buf *bf, *bf0;
+
+       list_for_each_entry_safe(bf, bf0, &txq->q, list) {
+               ath5k_txbuf_free(sc, bf);
+
+               list_del(&bf->list);
+               list_add_tail(&bf->list, &sc->txbuf);
+               sc->txbuf_len++;
+       }
+       txq->link = NULL;
+}
+
+/*
+ * Drain the transmit queues and reclaim resources.
+ */
+static void
+ath5k_txq_cleanup(struct ath5k_softc *sc)
+{
+       struct ath5k_hw *ah = sc->ah;
+
+       if (!(sc->status & ATH_STAT_INVALID)) {
+               /* don't touch the hardware if marked invalid */
+               if (sc->txq.setup) {
+                       ath5k_hw_stop_tx_dma(ah, sc->txq.qnum);
+                       DBG("ath5k: txq [%d] %x, link %p\n",
+                           sc->txq.qnum,
+                           ath5k_hw_get_txdp(ah, sc->txq.qnum),
+                           sc->txq.link);
+               }
+       }
+
+       if (sc->txq.setup)
+               ath5k_txq_drainq(sc, &sc->txq);
+}
+
+static void
+ath5k_txq_release(struct ath5k_softc *sc)
+{
+       if (sc->txq.setup) {
+               ath5k_hw_release_tx_queue(sc->ah);
+               sc->txq.setup = 0;
+       }
+}
+
+
+
+
+/*************\
+* RX Handling *
+\*************/
+
+/*
+ * Enable the receive h/w following a reset.
+ */
+static int
+ath5k_rx_start(struct ath5k_softc *sc)
+{
+       struct ath5k_hw *ah = sc->ah;
+       struct ath5k_buf *bf;
+       int ret;
+
+       sc->rxbufsize = IEEE80211_MAX_LEN;
+       if (sc->rxbufsize % sc->cachelsz != 0)
+               sc->rxbufsize += sc->cachelsz - (sc->rxbufsize % sc->cachelsz);
+
+       sc->rxlink = NULL;
+
+       list_for_each_entry(bf, &sc->rxbuf, list) {
+               ret = ath5k_rxbuf_setup(sc, bf);
+               if (ret != 0)
+                       return ret;
+       }
+
+       bf = list_entry(sc->rxbuf.next, struct ath5k_buf, list);
+
+       ath5k_hw_set_rxdp(ah, bf->daddr);
+       ath5k_hw_start_rx_dma(ah);      /* enable recv descriptors */
+       ath5k_mode_setup(sc);           /* set filters, etc. */
+       ath5k_hw_start_rx_pcu(ah);      /* re-enable PCU/DMA engine */
+
+       return 0;
+}
+
+/*
+ * Disable the receive h/w in preparation for a reset.
+ */
+static void
+ath5k_rx_stop(struct ath5k_softc *sc)
+{
+       struct ath5k_hw *ah = sc->ah;
+
+       ath5k_hw_stop_rx_pcu(ah);       /* disable PCU */
+       ath5k_hw_set_rx_filter(ah, 0);  /* clear recv filter */
+       ath5k_hw_stop_rx_dma(ah);       /* disable DMA engine */
+
+       sc->rxlink = NULL;              /* just in case */
+}
+
+static void
+ath5k_handle_rx(struct ath5k_softc *sc)
+{
+       struct ath5k_rx_status rs;
+       struct io_buffer *iob, *next_iob;
+       u32 next_iob_addr;
+       struct ath5k_buf *bf, *bf_last;
+       struct ath5k_desc *ds;
+       int ret;
+
+       memset(&rs, 0, sizeof(rs));
+
+       if (list_empty(&sc->rxbuf)) {
+               DBG("ath5k: empty rx buf pool\n");
+               return;
+       }
+
+       bf_last = list_entry(sc->rxbuf.prev, struct ath5k_buf, list);
+
+       do {
+               bf = list_entry(sc->rxbuf.next, struct ath5k_buf, list);
+               assert(bf->iob != NULL);
+               iob = bf->iob;
+               ds = bf->desc;
+
+               /*
+                * last buffer must not be freed to ensure proper hardware
+                * function. When the hardware finishes also a packet next to
+                * it, we are sure, it doesn't use it anymore and we can go on.
+                */
+               if (bf_last == bf)
+                       bf->flags |= 1;
+               if (bf->flags) {
+                       struct ath5k_buf *bf_next = list_entry(bf->list.next,
+                                       struct ath5k_buf, list);
+                       ret = sc->ah->ah_proc_rx_desc(sc->ah, bf_next->desc,
+                                       &rs);
+                       if (ret)
+                               break;
+                       bf->flags &= ~1;
+                       /* skip the overwritten one (even status is martian) */
+                       goto next;
+               }
+
+               ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
+               if (ret) {
+                       if (ret != -EINPROGRESS) {
+                               DBG("ath5k: error in processing rx desc: %s\n",
+                                   strerror(ret));
+                               net80211_rx_err(sc->dev, NULL, -ret);
+                       } else {
+                               /* normal return, reached end of
+                                  available descriptors */
+                       }
+                       return;
+               }
+
+               if (rs.rs_more) {
+                       DBG("ath5k: unsupported fragmented rx\n");
+                       goto next;
+               }
+
+               if (rs.rs_status) {
+                       if (rs.rs_status & AR5K_RXERR_PHY) {
+                               DBG("ath5k: rx PHY error\n");
+                               goto next;
+                       }
+                       if (rs.rs_status & AR5K_RXERR_CRC) {
+                               net80211_rx_err(sc->dev, NULL, EIO);
+                               goto next;
+                       }
+                       if (rs.rs_status & AR5K_RXERR_DECRYPT) {
+                               /*
+                                * Decrypt error.  If the error occurred
+                                * because there was no hardware key, then
+                                * let the frame through so the upper layers
+                                * can process it.  This is necessary for 5210
+                                * parts which have no way to setup a ``clear''
+                                * key cache entry.
+                                *
+                                * XXX do key cache faulting
+                                */
+                               if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
+                                   !(rs.rs_status & AR5K_RXERR_CRC))
+                                       goto accept;
+                       }
+
+                       /* any other error, unhandled */
+                       DBG("ath5k: packet rx status %x\n", rs.rs_status);
+                       goto next;
+               }
+accept:
+               next_iob = ath5k_rx_iob_alloc(sc, &next_iob_addr);
+
+               /*
+                * If we can't replace bf->iob with a new iob under memory
+                * pressure, just skip this packet
+                */
+               if (!next_iob) {
+                       DBG("ath5k: dropping packet under memory pressure\n");
+                       goto next;
+               }
+
+               iob_put(iob, rs.rs_datalen);
+
+               /* The MAC header is padded to have 32-bit boundary if the
+                * packet payload is non-zero. However, gPXE only
+                * supports standard 802.11 packets with 24-byte
+                * header, so no padding correction should be needed.
+                */
+
+               DBG2("ath5k: rx %d bytes, signal %d\n", rs.rs_datalen,
+                    rs.rs_rssi);
+
+               net80211_rx(sc->dev, iob, rs.rs_rssi,
+                           ath5k_hw_rix_to_bitrate(rs.rs_rate));
+
+               bf->iob = next_iob;
+               bf->iobaddr = next_iob_addr;
+next:
+               list_del(&bf->list);
+               list_add_tail(&bf->list, &sc->rxbuf);
+       } while (ath5k_rxbuf_setup(sc, bf) == 0);
+}
+
+
+
+
+/*************\
+* TX Handling *
+\*************/
+
+static void
+ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
+{
+       struct ath5k_tx_status ts;
+       struct ath5k_buf *bf, *bf0;
+       struct ath5k_desc *ds;
+       struct io_buffer *iob;
+       int ret;
+
+       memset(&ts, 0, sizeof(ts));
+
+       list_for_each_entry_safe(bf, bf0, &txq->q, list) {
+               ds = bf->desc;
+
+               ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
+               if (ret) {
+                       if (ret != -EINPROGRESS) {
+                               DBG("ath5k: error in processing tx desc: %s\n",
+                                   strerror(ret));
+                       } else {
+                               /* normal return, reached end of tx completions */
+                       }
+                       break;
+               }
+
+               iob = bf->iob;
+               bf->iob = NULL;
+
+               DBG2("ath5k: tx %d bytes complete, %d retries\n",
+                    iob_len(iob), ts.ts_retry[0]);
+
+               net80211_tx_complete(sc->dev, iob, ts.ts_retry[0],
+                                    ts.ts_status ? EIO : 0);
+
+               list_del(&bf->list);
+               list_add_tail(&bf->list, &sc->txbuf);
+               sc->txbuf_len++;
+       }
+
+       if (list_empty(&txq->q))
+               txq->link = NULL;
+}
+
+static void
+ath5k_handle_tx(struct ath5k_softc *sc)
+{
+       ath5k_tx_processq(sc, &sc->txq);
+}
+
+
+/********************\
+* Interrupt handling *
+\********************/
+
+static void
+ath5k_irq(struct net80211_device *dev, int enable)
+{
+       struct ath5k_softc *sc = dev->priv;
+       struct ath5k_hw *ah = sc->ah;
+
+       sc->irq_ena = enable;
+       ah->ah_ier = enable ? AR5K_IER_ENABLE : AR5K_IER_DISABLE;
+
+       ath5k_hw_reg_write(ah, ah->ah_ier, AR5K_IER);
+       ath5k_hw_set_imr(ah, sc->imask);
+}
+
+static int
+ath5k_init(struct ath5k_softc *sc)
+{
+       struct ath5k_hw *ah = sc->ah;
+       int ret, i;
+
+       /*
+        * Stop anything previously setup.  This is safe
+        * no matter this is the first time through or not.
+        */
+       ath5k_stop_hw(sc);
+
+       /*
+        * The basic interface to setting the hardware in a good
+        * state is ``reset''.  On return the hardware is known to
+        * be powered up and with interrupts disabled.  This must
+        * be followed by initialization of the appropriate bits
+        * and then setup of the interrupt mask.
+        */
+       sc->curchan = sc->dev->channels + sc->dev->channel;
+       sc->curband = sc->curchan->band;
+       sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
+               AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
+               AR5K_INT_FATAL | AR5K_INT_GLOBAL;
+       ret = ath5k_reset(sc, NULL);
+       if (ret)
+               goto done;
+
+       /*
+        * Reset the key cache since some parts do not reset the
+        * contents on initial power up or resume from suspend.
+        */
+       for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
+               ath5k_hw_reset_key(ah, i);
+
+       /* Set ack to be sent at low bit-rates */
+       ath5k_hw_set_ack_bitrate_high(ah, 0);
+
+       ret = 0;
+done:
+       mb();
+       return ret;
+}
+
+static int
+ath5k_stop_hw(struct ath5k_softc *sc)
+{
+       struct ath5k_hw *ah = sc->ah;
+
+       /*
+        * Shutdown the hardware and driver:
+        *    stop output from above
+        *    disable interrupts
+        *    turn off timers
+        *    turn off the radio
+        *    clear transmit machinery
+        *    clear receive machinery
+        *    drain and release tx queues
+        *    reclaim beacon resources
+        *    power down hardware
+        *
+        * Note that some of this work is not possible if the
+        * hardware is gone (invalid).
+        */
+
+       if (!(sc->status & ATH_STAT_INVALID)) {
+               ath5k_hw_set_imr(ah, 0);
+       }
+       ath5k_txq_cleanup(sc);
+       if (!(sc->status & ATH_STAT_INVALID)) {
+               ath5k_rx_stop(sc);
+               ath5k_hw_phy_disable(ah);
+       } else
+               sc->rxlink = NULL;
+
+       return 0;
+}
+
+static void
+ath5k_poll(struct net80211_device *dev)
+{
+       struct ath5k_softc *sc = dev->priv;
+       struct ath5k_hw *ah = sc->ah;
+       enum ath5k_int status;
+       unsigned int counter = 1000;
+
+       if (currticks() - sc->last_calib_ticks >
+           ATH5K_CALIB_INTERVAL * ticks_per_sec()) {
+               ath5k_calibrate(sc);
+               sc->last_calib_ticks = currticks();
+       }
+
+       if ((sc->status & ATH_STAT_INVALID) ||
+           (sc->irq_ena && !ath5k_hw_is_intr_pending(ah)))
+               return;
+
+       do {
+               ath5k_hw_get_isr(ah, &status);          /* NB: clears IRQ too */
+               DBGP("ath5k: status %#x/%#x\n", status, sc->imask);
+               if (status & AR5K_INT_FATAL) {
+                       /*
+                        * Fatal errors are unrecoverable.
+                        * Typically these are caused by DMA errors.
+                        */
+                       DBG("ath5k: fatal error, resetting\n");
+                       ath5k_reset_wake(sc);
+               } else if (status & AR5K_INT_RXORN) {
+                       DBG("ath5k: rx overrun, resetting\n");
+                       ath5k_reset_wake(sc);
+               } else {
+                       if (status & AR5K_INT_RXEOL) {
+                               /*
+                                * NB: the hardware should re-read the link when
+                                *     RXE bit is written, but it doesn't work at
+                                *     least on older hardware revs.
+                                */
+                               DBG("ath5k: rx EOL\n");
+                               sc->rxlink = NULL;
+                       }
+                       if (status & AR5K_INT_TXURN) {
+                               /* bump tx trigger level */
+                               DBG("ath5k: tx underrun\n");
+                               ath5k_hw_update_tx_triglevel(ah, 1);
+                       }
+                       if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
+                               ath5k_handle_rx(sc);
+                       if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
+                                     | AR5K_INT_TXERR | AR5K_INT_TXEOL))
+                               ath5k_handle_tx(sc);
+               }
+       } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
+
+       if (!counter)
+               DBG("ath5k: too many interrupts, giving up for now\n");
+}
+
+/*
+ * Periodically recalibrate the PHY to account
+ * for temperature/environment changes.
+ */
+static void
+ath5k_calibrate(struct ath5k_softc *sc)
+{
+       struct ath5k_hw *ah = sc->ah;
+
+       if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
+               /*
+                * Rfgain is out of bounds, reset the chip
+                * to load new gain values.
+                */
+               DBG("ath5k: resetting for calibration\n");
+               ath5k_reset_wake(sc);
+       }
+       if (ath5k_hw_phy_calibrate(ah, sc->curchan))
+               DBG("ath5k: calibration of channel %d failed\n",
+                   sc->curchan->channel_nr);
+}
+
+
+/********************\
+* Net80211 functions *
+\********************/
+
+static int
+ath5k_tx(struct net80211_device *dev, struct io_buffer *iob)
+{
+       struct ath5k_softc *sc = dev->priv;
+       struct ath5k_buf *bf;
+       int rc;
+
+       /*
+        * The hardware expects the header padded to 4 byte boundaries.
+        * gPXE only ever sends 24-byte headers, so no action necessary.
+        */
+
+       if (list_empty(&sc->txbuf)) {
+               DBG("ath5k: dropping packet because no tx bufs available\n");
+               return -ENOBUFS;
+       }
+
+       bf = list_entry(sc->txbuf.next, struct ath5k_buf, list);
+       list_del(&bf->list);
+       sc->txbuf_len--;
+
+       bf->iob = iob;
+
+       if ((rc = ath5k_txbuf_setup(sc, bf)) != 0) {
+               bf->iob = NULL;
+               list_add_tail(&bf->list, &sc->txbuf);
+               sc->txbuf_len++;
+               return rc;
+       }
+       return 0;
+}
+
+/*
+ * Reset the hardware.  If chan is not NULL, then also pause rx/tx
+ * and change to the given channel.
+ */
+static int
+ath5k_reset(struct ath5k_softc *sc, struct net80211_channel *chan)
+{
+       struct ath5k_hw *ah = sc->ah;
+       int ret;
+
+       if (chan) {
+               ath5k_hw_set_imr(ah, 0);
+               ath5k_txq_cleanup(sc);
+               ath5k_rx_stop(sc);
+
+               sc->curchan = chan;
+               sc->curband = chan->band;
+       }
+
+       ret = ath5k_hw_reset(ah, sc->curchan, 1);
+       if (ret) {
+               DBG("ath5k: can't reset hardware: %s\n", strerror(ret));
+               return ret;
+       }
+
+       ret = ath5k_rx_start(sc);
+       if (ret) {
+               DBG("ath5k: can't start rx logic: %s\n", strerror(ret));
+               return ret;
+       }
+
+       /*
+        * Change channels and update the h/w rate map if we're switching;
+        * e.g. 11a to 11b/g.
+        *
+        * We may be doing a reset in response to an ioctl that changes the
+        * channel so update any state that might change as a result.
+        *
+        * XXX needed?
+        */
+/*     ath5k_chan_change(sc, c); */
+
+       /* Reenable interrupts if necessary */
+       ath5k_irq(sc->dev, sc->irq_ena);
+
+       return 0;
+}
+
+static int ath5k_reset_wake(struct ath5k_softc *sc)
+{
+       return ath5k_reset(sc, sc->curchan);
+}
+
+static int ath5k_start(struct net80211_device *dev)
+{
+       struct ath5k_softc *sc = dev->priv;
+       int ret;
+
+       if ((ret = ath5k_init(sc)) != 0)
+               return ret;
+
+       sc->assoc = 0;
+       ath5k_configure_filter(sc);
+       ath5k_hw_set_lladdr(sc->ah, dev->netdev->ll_addr);
+
+       return 0;
+}
+
+static void ath5k_stop(struct net80211_device *dev)
+{
+       struct ath5k_softc *sc = dev->priv;
+       u8 mac[ETH_ALEN] = {};
+
+       ath5k_hw_set_lladdr(sc->ah, mac);
+
+       ath5k_stop_hw(sc);
+}
+
+static int
+ath5k_config(struct net80211_device *dev, int changed)
+{
+       struct ath5k_softc *sc = dev->priv;
+       struct ath5k_hw *ah = sc->ah;
+       struct net80211_channel *chan = &dev->channels[dev->channel];
+       int ret;
+
+       if (changed & NET80211_CFG_CHANNEL) {
+               sc->power_level = chan->maxpower;
+               if ((ret = ath5k_chan_set(sc, chan)) != 0)
+                       return ret;
+       }
+
+       if ((changed & NET80211_CFG_RATE) ||
+           (changed & NET80211_CFG_PHY_PARAMS)) {
+               int spmbl = ATH5K_SPMBL_NO;
+               u16 rate = dev->rates[dev->rate];
+               u16 slowrate = dev->rates[dev->rtscts_rate];
+               int i;
+
+               if (dev->phy_flags & NET80211_PHY_USE_SHORT_PREAMBLE)
+                       spmbl = ATH5K_SPMBL_YES;
+
+               for (i = 0; i < ATH5K_NR_RATES; i++) {
+                       if (ath5k_rates[i].bitrate == rate &&
+                           (ath5k_rates[i].short_pmbl & spmbl))
+                               sc->hw_rate = ath5k_rates[i].hw_code;
+
+                       if (ath5k_rates[i].bitrate == slowrate &&
+                           (ath5k_rates[i].short_pmbl & spmbl))
+                               sc->hw_rtscts_rate = ath5k_rates[i].hw_code;
+               }
+       }
+
+       if (changed & NET80211_CFG_ASSOC) {
+               sc->assoc = !!(dev->state & NET80211_ASSOCIATED);
+               if (sc->assoc) {
+                       memcpy(ah->ah_bssid, dev->bssid, ETH_ALEN);
+               } else {
+                       memset(ah->ah_bssid, 0xff, ETH_ALEN);
+               }
+               ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
+       }
+
+       return 0;
+}
+
+/*
+ * o always accept unicast, broadcast, and multicast traffic
+ * o multicast traffic for all BSSIDs will be enabled if mac80211
+ *   says it should be
+ * o maintain current state of phy ofdm or phy cck error reception.
+ *   If the hardware detects any of these type of errors then
+ *   ath5k_hw_get_rx_filter() will pass to us the respective
+ *   hardware filters to be able to receive these type of frames.
+ * o probe request frames are accepted only when operating in
+ *   hostap, adhoc, or monitor modes
+ * o enable promiscuous mode according to the interface state
+ * o accept beacons:
+ *   - when operating in adhoc mode so the 802.11 layer creates
+ *     node table entries for peers,
+ *   - when operating in station mode for collecting rssi data when
+ *     the station is otherwise quiet, or
+ *   - when scanning
+ */
+static void ath5k_configure_filter(struct ath5k_softc *sc)
+{
+       struct ath5k_hw *ah = sc->ah;
+       u32 mfilt[2], rfilt;
+
+       /* Enable all multicast */
+       mfilt[0] = ~0;
+       mfilt[1] = ~0;
+
+       /* Enable data frames and beacons */
+       rfilt = (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
+                AR5K_RX_FILTER_MCAST | AR5K_RX_FILTER_BEACON);
+
+       /* Set filters */
+       ath5k_hw_set_rx_filter(ah, rfilt);
+
+       /* Set multicast bits */
+       ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
+
+       /* Set the cached hw filter flags, this will alter actually
+        * be set in HW */
+       sc->filter_flags = rfilt;
+}
diff --git a/src/drivers/net/ath5k/ath5k.h b/src/drivers/net/ath5k/ath5k.h
new file mode 100644 (file)
index 0000000..c79fbec
--- /dev/null
@@ -0,0 +1,1275 @@
+/*
+ * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
+ * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
+ *
+ * Modified for gPXE, July 2009, by Joshua Oreman <oremanj@rwcr.net>
+ * Original from Linux kernel 2.6.30.
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _ATH5K_H
+#define _ATH5K_H
+
+FILE_LICENCE ( MIT );
+
+#include <stddef.h>
+#include <byteswap.h>
+#include <gpxe/io.h>
+#include <gpxe/netdevice.h>
+#include <gpxe/net80211.h>
+#include <errno.h>
+
+/* Keep all ath5k files under one errfile ID */
+#undef ERRFILE
+#define ERRFILE ERRFILE_ath5k
+
+#define ARRAY_SIZE(a) (sizeof(a)/sizeof((a)[0]))
+
+/* RX/TX descriptor hw structs */
+#include "desc.h"
+
+/* EEPROM structs/offsets */
+#include "eeprom.h"
+
+/* PCI IDs */
+#define PCI_DEVICE_ID_ATHEROS_AR5210           0x0007 /* AR5210 */
+#define PCI_DEVICE_ID_ATHEROS_AR5311           0x0011 /* AR5311 */
+#define PCI_DEVICE_ID_ATHEROS_AR5211           0x0012 /* AR5211 */
+#define PCI_DEVICE_ID_ATHEROS_AR5212           0x0013 /* AR5212 */
+#define PCI_DEVICE_ID_3COM_3CRDAG675           0x0013 /* 3CRDAG675 (Atheros AR5212) */
+#define PCI_DEVICE_ID_3COM_2_3CRPAG175                 0x0013 /* 3CRPAG175 (Atheros AR5212) */
+#define PCI_DEVICE_ID_ATHEROS_AR5210_AP        0x0207 /* AR5210 (Early) */
+#define PCI_DEVICE_ID_ATHEROS_AR5212_IBM       0x1014 /* AR5212 (IBM MiniPCI) */
+#define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT   0x1107 /* AR5210 (no eeprom) */
+#define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT   0x1113 /* AR5212 (no eeprom) */
+#define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT   0x1112 /* AR5211 (no eeprom) */
+#define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA      0xf013 /* AR5212 (emulation board) */
+#define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY    0xff12 /* AR5211 (emulation board) */
+#define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B   0xf11b /* AR5211 (emulation board) */
+#define PCI_DEVICE_ID_ATHEROS_AR5312_REV2      0x0052 /* AR5312 WMAC (AP31) */
+#define PCI_DEVICE_ID_ATHEROS_AR5312_REV7      0x0057 /* AR5312 WMAC (AP30-040) */
+#define PCI_DEVICE_ID_ATHEROS_AR5312_REV8      0x0058 /* AR5312 WMAC (AP43-030) */
+#define PCI_DEVICE_ID_ATHEROS_AR5212_0014      0x0014 /* AR5212 compatible */
+#define PCI_DEVICE_ID_ATHEROS_AR5212_0015      0x0015 /* AR5212 compatible */
+#define PCI_DEVICE_ID_ATHEROS_AR5212_0016      0x0016 /* AR5212 compatible */
+#define PCI_DEVICE_ID_ATHEROS_AR5212_0017      0x0017 /* AR5212 compatible */
+#define PCI_DEVICE_ID_ATHEROS_AR5212_0018      0x0018 /* AR5212 compatible */
+#define PCI_DEVICE_ID_ATHEROS_AR5212_0019      0x0019 /* AR5212 compatible */
+#define PCI_DEVICE_ID_ATHEROS_AR2413           0x001a /* AR2413 (Griffin-lite) */
+#define PCI_DEVICE_ID_ATHEROS_AR5413           0x001b /* AR5413 (Eagle) */
+#define PCI_DEVICE_ID_ATHEROS_AR5424           0x001c /* AR5424 (Condor PCI-E) */
+#define PCI_DEVICE_ID_ATHEROS_AR5416           0x0023 /* AR5416 */
+#define PCI_DEVICE_ID_ATHEROS_AR5418           0x0024 /* AR5418 */
+
+/****************************\
+  GENERIC DRIVER DEFINITIONS
+\****************************/
+
+/*
+ * AR5K REGISTER ACCESS
+ */
+
+/* Some macros to read/write fields */
+
+/* First shift, then mask */
+#define AR5K_REG_SM(_val, _flags)                                      \
+       (((_val) << _flags##_S) & (_flags))
+
+/* First mask, then shift */
+#define AR5K_REG_MS(_val, _flags)                                      \
+       (((_val) & (_flags)) >> _flags##_S)
+
+/* Some registers can hold multiple values of interest. For this
+ * reason when we want to write to these registers we must first
+ * retrieve the values which we do not want to clear (lets call this
+ * old_data) and then set the register with this and our new_value:
+ * ( old_data | new_value) */
+#define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val)                    \
+       ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \
+           (((_val) << _flags##_S) & (_flags)), _reg)
+
+#define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask)                  \
+       ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) &           \
+                       (_mask)) | (_flags), _reg)
+
+#define AR5K_REG_ENABLE_BITS(ah, _reg, _flags)                         \
+       ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg)
+
+#define AR5K_REG_DISABLE_BITS(ah, _reg, _flags)                        \
+       ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg)
+
+/* Access to PHY registers */
+#define AR5K_PHY_READ(ah, _reg)                                        \
+       ath5k_hw_reg_read(ah, (ah)->ah_phy + ((_reg) << 2))
+
+#define AR5K_PHY_WRITE(ah, _reg, _val)                                 \
+       ath5k_hw_reg_write(ah, _val, (ah)->ah_phy + ((_reg) << 2))
+
+/* Access QCU registers per queue */
+#define AR5K_REG_READ_Q(ah, _reg, _queue)                              \
+       (ath5k_hw_reg_read(ah, _reg) & (1 << _queue))                   \
+
+#define AR5K_REG_WRITE_Q(ah, _reg, _queue)                             \
+       ath5k_hw_reg_write(ah, (1 << _queue), _reg)
+
+#define AR5K_Q_ENABLE_BITS(_reg, _queue) do {                          \
+       _reg |= 1 << _queue;                                            \
+} while (0)
+
+#define AR5K_Q_DISABLE_BITS(_reg, _queue) do {                         \
+       _reg &= ~(1 << _queue);                                         \
+} while (0)
+
+/* Used while writing initvals */
+#define AR5K_REG_WAIT(_i) do {                                         \
+       if (_i % 64)                                                    \
+               udelay(1);                                              \
+} while (0)
+
+/* Register dumps are done per operation mode */
+#define AR5K_INI_RFGAIN_5GHZ           0
+#define AR5K_INI_RFGAIN_2GHZ           1
+
+/* TODO: Clean this up */
+#define AR5K_INI_VAL_11A               0
+#define AR5K_INI_VAL_11A_TURBO         1
+#define AR5K_INI_VAL_11B               2
+#define AR5K_INI_VAL_11G               3
+#define AR5K_INI_VAL_11G_TURBO         4
+#define AR5K_INI_VAL_XR                        0
+#define AR5K_INI_VAL_MAX               5
+
+/* Used for BSSID etc manipulation */
+#define AR5K_LOW_ID(_a)(                               \
+(_a)[0] | (_a)[1] << 8 | (_a)[2] << 16 | (_a)[3] << 24 \
+)
+
+#define AR5K_HIGH_ID(_a)       ((_a)[4] | (_a)[5] << 8)
+
+#define IEEE80211_MAX_LEN      2352
+
+/*
+ * Some tuneable values (these should be changeable by the user)
+ */
+#define AR5K_TUNE_DMA_BEACON_RESP              2
+#define AR5K_TUNE_SW_BEACON_RESP               10
+#define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF      0
+#define AR5K_TUNE_RADAR_ALERT                  0
+#define AR5K_TUNE_MIN_TX_FIFO_THRES            1
+#define AR5K_TUNE_MAX_TX_FIFO_THRES            ((IEEE80211_MAX_LEN / 64) + 1)
+#define AR5K_TUNE_REGISTER_TIMEOUT             20000
+/* Register for RSSI threshold has a mask of 0xff, so 255 seems to
+ * be the max value. */
+#define AR5K_TUNE_RSSI_THRES                   129
+/* This must be set when setting the RSSI threshold otherwise it can
+ * prevent a reset. If AR5K_RSSI_THR is read after writing to it
+ * the BMISS_THRES will be seen as 0, seems harware doesn't keep
+ * track of it. Max value depends on harware. For AR5210 this is just 7.
+ * For AR5211+ this seems to be up to 255. */
+#define AR5K_TUNE_BMISS_THRES                  7
+#define AR5K_TUNE_REGISTER_DWELL_TIME          20000
+#define AR5K_TUNE_BEACON_INTERVAL              100
+#define AR5K_TUNE_AIFS                         2
+#define AR5K_TUNE_AIFS_11B                     2
+#define AR5K_TUNE_AIFS_XR                      0
+#define AR5K_TUNE_CWMIN                                15
+#define AR5K_TUNE_CWMIN_11B                    31
+#define AR5K_TUNE_CWMIN_XR                     3
+#define AR5K_TUNE_CWMAX                                1023
+#define AR5K_TUNE_CWMAX_11B                    1023
+#define AR5K_TUNE_CWMAX_XR                     7
+#define AR5K_TUNE_NOISE_FLOOR                  -72
+#define AR5K_TUNE_MAX_TXPOWER                  63
+#define AR5K_TUNE_DEFAULT_TXPOWER              25
+#define AR5K_TUNE_TPC_TXPOWER                  0
+#define AR5K_TUNE_ANT_DIVERSITY                        1
+#define AR5K_TUNE_HWTXTRIES                    4
+
+#define AR5K_INIT_CARR_SENSE_EN                        1
+
+/*Swap RX/TX Descriptor for big endian archs*/
+#if __BYTE_ORDER == __BIG_ENDIAN
+#define AR5K_INIT_CFG  (               \
+       AR5K_CFG_SWTD | AR5K_CFG_SWRD   \
+)
+#else
+#define AR5K_INIT_CFG  0x00000000
+#endif
+
+/* Initial values */
+#define        AR5K_INIT_CYCRSSI_THR1                  2
+#define AR5K_INIT_TX_LATENCY                   502
+#define AR5K_INIT_USEC                         39
+#define AR5K_INIT_USEC_TURBO                   79
+#define AR5K_INIT_USEC_32                      31
+#define AR5K_INIT_SLOT_TIME                    396
+#define AR5K_INIT_SLOT_TIME_TURBO              480
+#define AR5K_INIT_ACK_CTS_TIMEOUT              1024
+#define AR5K_INIT_ACK_CTS_TIMEOUT_TURBO                0x08000800
+#define AR5K_INIT_PROG_IFS                     920
+#define AR5K_INIT_PROG_IFS_TURBO               960
+#define AR5K_INIT_EIFS                         3440
+#define AR5K_INIT_EIFS_TURBO                   6880
+#define AR5K_INIT_SIFS                         560
+#define AR5K_INIT_SIFS_TURBO                   480
+#define AR5K_INIT_SH_RETRY                     10
+#define AR5K_INIT_LG_RETRY                     AR5K_INIT_SH_RETRY
+#define AR5K_INIT_SSH_RETRY                    32
+#define AR5K_INIT_SLG_RETRY                    AR5K_INIT_SSH_RETRY
+#define AR5K_INIT_TX_RETRY                     10
+
+#define AR5K_INIT_TRANSMIT_LATENCY             (                       \
+       (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) |       \
+       (AR5K_INIT_USEC)                                                \
+)
+#define AR5K_INIT_TRANSMIT_LATENCY_TURBO       (                       \
+       (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) |       \
+       (AR5K_INIT_USEC_TURBO)                                          \
+)
+#define AR5K_INIT_PROTO_TIME_CNTRL             (                       \
+       (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS << 12) |      \
+       (AR5K_INIT_PROG_IFS)                                            \
+)
+#define AR5K_INIT_PROTO_TIME_CNTRL_TURBO       (                       \
+       (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS_TURBO << 12) | \
+       (AR5K_INIT_PROG_IFS_TURBO)                                      \
+)
+
+/* token to use for aifs, cwmin, cwmax in MadWiFi */
+#define        AR5K_TXQ_USEDEFAULT     ((u32) -1)
+
+/* GENERIC CHIPSET DEFINITIONS */
+
+/* MAC Chips */
+enum ath5k_version {
+       AR5K_AR5210     = 0,
+       AR5K_AR5211     = 1,
+       AR5K_AR5212     = 2,
+};
+
+/* PHY Chips */
+enum ath5k_radio {
+       AR5K_RF5110     = 0,
+       AR5K_RF5111     = 1,
+       AR5K_RF5112     = 2,
+       AR5K_RF2413     = 3,
+       AR5K_RF5413     = 4,
+       AR5K_RF2316     = 5,
+       AR5K_RF2317     = 6,
+       AR5K_RF2425     = 7,
+};
+
+/*
+ * Common silicon revision/version values
+ */
+
+enum ath5k_srev_type {
+       AR5K_VERSION_MAC,
+       AR5K_VERSION_RAD,
+};
+
+struct ath5k_srev_name {
+       const char              *sr_name;
+       enum ath5k_srev_type    sr_type;
+       unsigned                sr_val;
+};
+
+#define AR5K_SREV_UNKNOWN      0xffff
+
+#define AR5K_SREV_AR5210       0x00 /* Crete */
+#define AR5K_SREV_AR5311       0x10 /* Maui 1 */
+#define AR5K_SREV_AR5311A      0x20 /* Maui 2 */
+#define AR5K_SREV_AR5311B      0x30 /* Spirit */
+#define AR5K_SREV_AR5211       0x40 /* Oahu */
+#define AR5K_SREV_AR5212       0x50 /* Venice */
+#define AR5K_SREV_AR5213       0x55 /* ??? */
+#define AR5K_SREV_AR5213A      0x59 /* Hainan */
+#define AR5K_SREV_AR2413       0x78 /* Griffin lite */
+#define AR5K_SREV_AR2414       0x70 /* Griffin */
+#define AR5K_SREV_AR5424       0x90 /* Condor */
+#define AR5K_SREV_AR5413       0xa4 /* Eagle lite */
+#define AR5K_SREV_AR5414       0xa0 /* Eagle */
+#define AR5K_SREV_AR2415       0xb0 /* Talon */
+#define AR5K_SREV_AR5416       0xc0 /* PCI-E */
+#define AR5K_SREV_AR5418       0xca /* PCI-E */
+#define AR5K_SREV_AR2425       0xe0 /* Swan */
+#define AR5K_SREV_AR2417       0xf0 /* Nala */
+
+#define AR5K_SREV_RAD_5110     0x00
+#define AR5K_SREV_RAD_5111     0x10
+#define AR5K_SREV_RAD_5111A    0x15
+#define AR5K_SREV_RAD_2111     0x20
+#define AR5K_SREV_RAD_5112     0x30
+#define AR5K_SREV_RAD_5112A    0x35
+#define        AR5K_SREV_RAD_5112B     0x36
+#define AR5K_SREV_RAD_2112     0x40
+#define AR5K_SREV_RAD_2112A    0x45
+#define        AR5K_SREV_RAD_2112B     0x46
+#define AR5K_SREV_RAD_2413     0x50
+#define AR5K_SREV_RAD_5413     0x60
+#define AR5K_SREV_RAD_2316     0x70 /* Cobra SoC */
+#define AR5K_SREV_RAD_2317     0x80
+#define AR5K_SREV_RAD_5424     0xa0 /* Mostly same as 5413 */
+#define AR5K_SREV_RAD_2425     0xa2
+#define AR5K_SREV_RAD_5133     0xc0
+
+#define AR5K_SREV_PHY_5211     0x30
+#define AR5K_SREV_PHY_5212     0x41
+#define        AR5K_SREV_PHY_5212A     0x42
+#define AR5K_SREV_PHY_5212B    0x43
+#define AR5K_SREV_PHY_2413     0x45
+#define AR5K_SREV_PHY_5413     0x61
+#define AR5K_SREV_PHY_2425     0x70
+
+/*
+ * Some of this information is based on Documentation from:
+ *
+ * http://madwifi.org/wiki/ChipsetFeatures/SuperAG
+ *
+ * Modulation for Atheros' eXtended Range - range enhancing extension that is
+ * supposed to double the distance an Atheros client device can keep a
+ * connection with an Atheros access point. This is achieved by increasing
+ * the receiver sensitivity up to, -105dBm, which is about 20dB above what
+ * the 802.11 specifications demand. In addition, new (proprietary) data rates
+ * are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s.
+ *
+ * Please note that can you either use XR or TURBO but you cannot use both,
+ * they are exclusive.
+ *
+ */
+#define MODULATION_XR          0x00000200
+
+/*
+ * Modulation for Atheros' Turbo G and Turbo A, its supposed to provide a
+ * throughput transmission speed up to 40Mbit/s-60Mbit/s at a 108Mbit/s
+ * signaling rate achieved through the bonding of two 54Mbit/s 802.11g
+ * channels. To use this feature your Access Point must also suport it.
+ * There is also a distinction between "static" and "dynamic" turbo modes:
+ *
+ * - Static: is the dumb version: devices set to this mode stick to it until
+ *     the mode is turned off.
+ * - Dynamic: is the intelligent version, the network decides itself if it
+ *     is ok to use turbo. As soon as traffic is detected on adjacent channels
+ *     (which would get used in turbo mode), or when a non-turbo station joins
+ *     the network, turbo mode won't be used until the situation changes again.
+ *     Dynamic mode is achieved by Atheros' Adaptive Radio (AR) feature which
+ *     monitors the used radio band in order to decide whether turbo mode may
+ *     be used or not.
+ *
+ * This article claims Super G sticks to bonding of channels 5 and 6 for
+ * USA:
+ *
+ * http://www.pcworld.com/article/id,113428-page,1/article.html
+ *
+ * The channel bonding seems to be driver specific though. In addition to
+ * deciding what channels will be used, these "Turbo" modes are accomplished
+ * by also enabling the following features:
+ *
+ * - Bursting: allows multiple frames to be sent at once, rather than pausing
+ *     after each frame. Bursting is a standards-compliant feature that can be
+ *     used with any Access Point.
+ * - Fast frames: increases the amount of information that can be sent per
+ *     frame, also resulting in a reduction of transmission overhead. It is a
+ *     proprietary feature that needs to be supported by the Access Point.
+ * - Compression: data frames are compressed in real time using a Lempel Ziv
+ *     algorithm. This is done transparently. Once this feature is enabled,
+ *     compression and decompression takes place inside the chipset, without
+ *     putting additional load on the host CPU.
+ *
+ */
+#define MODULATION_TURBO       0x00000080
+
+enum ath5k_driver_mode {
+       AR5K_MODE_11A           = 0,
+       AR5K_MODE_11A_TURBO     = 1,
+       AR5K_MODE_11B           = 2,
+       AR5K_MODE_11G           = 3,
+       AR5K_MODE_11G_TURBO     = 4,
+       AR5K_MODE_XR            = 5,
+};
+
+enum {
+       AR5K_MODE_BIT_11A       = (1 << AR5K_MODE_11A),
+       AR5K_MODE_BIT_11A_TURBO = (1 << AR5K_MODE_11A_TURBO),
+       AR5K_MODE_BIT_11B       = (1 << AR5K_MODE_11B),
+       AR5K_MODE_BIT_11G       = (1 << AR5K_MODE_11G),
+       AR5K_MODE_BIT_11G_TURBO = (1 << AR5K_MODE_11G_TURBO),
+       AR5K_MODE_BIT_XR        = (1 << AR5K_MODE_XR),
+};
+
+/****************\
+  TX DEFINITIONS
+\****************/
+
+/*
+ * TX Status descriptor
+ */
+struct ath5k_tx_status {
+       u16     ts_seqnum;
+       u16     ts_tstamp;
+       u8      ts_status;
+       u8      ts_rate[4];
+       u8      ts_retry[4];
+       u8      ts_final_idx;
+       s8      ts_rssi;
+       u8      ts_shortretry;
+       u8      ts_longretry;
+       u8      ts_virtcol;
+       u8      ts_antenna;
+} __attribute__ ((packed));
+
+#define AR5K_TXSTAT_ALTRATE    0x80
+#define AR5K_TXERR_XRETRY      0x01
+#define AR5K_TXERR_FILT                0x02
+#define AR5K_TXERR_FIFO                0x04
+
+/**
+ * enum ath5k_tx_queue - Queue types used to classify tx queues.
+ * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue
+ * @AR5K_TX_QUEUE_DATA: A normal data queue
+ * @AR5K_TX_QUEUE_XR_DATA: An XR-data queue
+ * @AR5K_TX_QUEUE_BEACON: The beacon queue
+ * @AR5K_TX_QUEUE_CAB: The after-beacon queue
+ * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue
+ */
+enum ath5k_tx_queue {
+       AR5K_TX_QUEUE_INACTIVE = 0,
+       AR5K_TX_QUEUE_DATA,
+       AR5K_TX_QUEUE_XR_DATA,
+       AR5K_TX_QUEUE_BEACON,
+       AR5K_TX_QUEUE_CAB,
+       AR5K_TX_QUEUE_UAPSD,
+};
+
+/*
+ * Queue syb-types to classify normal data queues.
+ * These are the 4 Access Categories as defined in
+ * WME spec. 0 is the lowest priority and 4 is the
+ * highest. Normal data that hasn't been classified
+ * goes to the Best Effort AC.
+ */
+enum ath5k_tx_queue_subtype {
+       AR5K_WME_AC_BK = 0,     /*Background traffic*/
+       AR5K_WME_AC_BE,         /*Best-effort (normal) traffic)*/
+       AR5K_WME_AC_VI,         /*Video traffic*/
+       AR5K_WME_AC_VO,         /*Voice traffic*/
+};
+
+/*
+ * Queue ID numbers as returned by the hw functions, each number
+ * represents a hw queue. If hw does not support hw queues
+ * (eg 5210) all data goes in one queue. These match
+ * d80211 definitions (net80211/MadWiFi don't use them).
+ */
+enum ath5k_tx_queue_id {
+       AR5K_TX_QUEUE_ID_NOQCU_DATA     = 0,
+       AR5K_TX_QUEUE_ID_NOQCU_BEACON   = 1,
+       AR5K_TX_QUEUE_ID_DATA_MIN       = 0, /*IEEE80211_TX_QUEUE_DATA0*/
+       AR5K_TX_QUEUE_ID_DATA_MAX       = 4, /*IEEE80211_TX_QUEUE_DATA4*/
+       AR5K_TX_QUEUE_ID_DATA_SVP       = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/
+       AR5K_TX_QUEUE_ID_CAB            = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/
+       AR5K_TX_QUEUE_ID_BEACON         = 7, /*IEEE80211_TX_QUEUE_BEACON*/
+       AR5K_TX_QUEUE_ID_UAPSD          = 8,
+       AR5K_TX_QUEUE_ID_XR_DATA        = 9,
+};
+
+/*
+ * Flags to set hw queue's parameters...
+ */
+#define AR5K_TXQ_FLAG_TXOKINT_ENABLE           0x0001  /* Enable TXOK interrupt */
+#define AR5K_TXQ_FLAG_TXERRINT_ENABLE          0x0002  /* Enable TXERR interrupt */
+#define AR5K_TXQ_FLAG_TXEOLINT_ENABLE          0x0004  /* Enable TXEOL interrupt -not used- */
+#define AR5K_TXQ_FLAG_TXDESCINT_ENABLE         0x0008  /* Enable TXDESC interrupt -not used- */
+#define AR5K_TXQ_FLAG_TXURNINT_ENABLE          0x0010  /* Enable TXURN interrupt */
+#define AR5K_TXQ_FLAG_CBRORNINT_ENABLE         0x0020  /* Enable CBRORN interrupt */
+#define AR5K_TXQ_FLAG_CBRURNINT_ENABLE         0x0040  /* Enable CBRURN interrupt */
+#define AR5K_TXQ_FLAG_QTRIGINT_ENABLE          0x0080  /* Enable QTRIG interrupt */
+#define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE                0x0100  /* Enable TXNOFRM interrupt */
+#define AR5K_TXQ_FLAG_BACKOFF_DISABLE          0x0200  /* Disable random post-backoff */
+#define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE        0x0300  /* Enable ready time expiry policy (?)*/
+#define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE        0x0800  /* Enable backoff while bursting */
+#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS                0x1000  /* Disable backoff while bursting */
+#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE       0x2000  /* Enable hw compression -not implemented-*/
+
+/*
+ * A struct to hold tx queue's parameters
+ */
+struct ath5k_txq_info {
+       enum ath5k_tx_queue tqi_type;
+       enum ath5k_tx_queue_subtype tqi_subtype;
+       u16     tqi_flags;      /* Tx queue flags (see above) */
+       u32     tqi_aifs;       /* Arbitrated Interframe Space */
+       s32     tqi_cw_min;     /* Minimum Contention Window */
+       s32     tqi_cw_max;     /* Maximum Contention Window */
+       u32     tqi_cbr_period; /* Constant bit rate period */
+       u32     tqi_cbr_overflow_limit;
+       u32     tqi_burst_time;
+       u32     tqi_ready_time; /* Not used */
+};
+
+/*
+ * Transmit packet types.
+ * used on tx control descriptor
+ * TODO: Use them inside base.c corectly
+ */
+enum ath5k_pkt_type {
+       AR5K_PKT_TYPE_NORMAL            = 0,
+       AR5K_PKT_TYPE_ATIM              = 1,
+       AR5K_PKT_TYPE_PSPOLL            = 2,
+       AR5K_PKT_TYPE_BEACON            = 3,
+       AR5K_PKT_TYPE_PROBE_RESP        = 4,
+       AR5K_PKT_TYPE_PIFS              = 5,
+};
+
+/*
+ * TX power and TPC settings
+ */
+#define AR5K_TXPOWER_OFDM(_r, _v)      (                       \
+       ((0 & 1) << ((_v) + 6)) |                               \
+       (((ah->ah_txpower.txp_rates_power_table[(_r)]) & 0x3f) << (_v)) \
+)
+
+#define AR5K_TXPOWER_CCK(_r, _v)       (                       \
+       (ah->ah_txpower.txp_rates_power_table[(_r)] & 0x3f) << (_v)     \
+)
+
+/*
+ * DMA size definitions (2^n+2)
+ */
+enum ath5k_dmasize {
+       AR5K_DMASIZE_4B = 0,
+       AR5K_DMASIZE_8B,
+       AR5K_DMASIZE_16B,
+       AR5K_DMASIZE_32B,
+       AR5K_DMASIZE_64B,
+       AR5K_DMASIZE_128B,
+       AR5K_DMASIZE_256B,
+       AR5K_DMASIZE_512B
+};
+
+
+/****************\
+  RX DEFINITIONS
+\****************/
+
+/*
+ * RX Status descriptor
+ */
+struct ath5k_rx_status {
+       u16     rs_datalen;
+       u16     rs_tstamp;
+       u8      rs_status;
+       u8      rs_phyerr;
+       s8      rs_rssi;
+       u8      rs_keyix;
+       u8      rs_rate;
+       u8      rs_antenna;
+       u8      rs_more;
+};
+
+#define AR5K_RXERR_CRC         0x01
+#define AR5K_RXERR_PHY         0x02
+#define AR5K_RXERR_FIFO                0x04
+#define AR5K_RXERR_DECRYPT     0x08
+#define AR5K_RXERR_MIC         0x10
+#define AR5K_RXKEYIX_INVALID   ((u8) - 1)
+#define AR5K_TXKEYIX_INVALID   ((u32) - 1)
+
+
+/*
+ * TSF to TU conversion:
+ *
+ * TSF is a 64bit value in usec (microseconds).
+ * TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of
+ * time equal to 1024 usec", so it's roughly milliseconds (usec / 1024).
+ */
+#define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10)
+
+
+/*******************************\
+  GAIN OPTIMIZATION DEFINITIONS
+\*******************************/
+
+enum ath5k_rfgain {
+       AR5K_RFGAIN_INACTIVE = 0,
+       AR5K_RFGAIN_ACTIVE,
+       AR5K_RFGAIN_READ_REQUESTED,
+       AR5K_RFGAIN_NEED_CHANGE,
+};
+
+struct ath5k_gain {
+       u8                      g_step_idx;
+       u8                      g_current;
+       u8                      g_target;
+       u8                      g_low;
+       u8                      g_high;
+       u8                      g_f_corr;
+       u8                      g_state;
+};
+
+/********************\
+  COMMON DEFINITIONS
+\********************/
+
+#define AR5K_SLOT_TIME_9       396
+#define AR5K_SLOT_TIME_20      880
+#define AR5K_SLOT_TIME_MAX     0xffff
+
+/* channel_flags */
+#define        CHANNEL_CW_INT  0x0008  /* Contention Window interference detected */
+#define        CHANNEL_TURBO   0x0010  /* Turbo Channel */
+#define        CHANNEL_CCK     0x0020  /* CCK channel */
+#define        CHANNEL_OFDM    0x0040  /* OFDM channel */
+#define        CHANNEL_2GHZ    0x0080  /* 2GHz channel. */
+#define        CHANNEL_5GHZ    0x0100  /* 5GHz channel */
+#define        CHANNEL_PASSIVE 0x0200  /* Only passive scan allowed */
+#define        CHANNEL_DYN     0x0400  /* Dynamic CCK-OFDM channel (for g operation) */
+#define        CHANNEL_XR      0x0800  /* XR channel */
+
+#define        CHANNEL_A       (CHANNEL_5GHZ|CHANNEL_OFDM)
+#define        CHANNEL_B       (CHANNEL_2GHZ|CHANNEL_CCK)
+#define        CHANNEL_G       (CHANNEL_2GHZ|CHANNEL_OFDM)
+#define        CHANNEL_T       (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
+#define        CHANNEL_TG      (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
+#define        CHANNEL_108A    CHANNEL_T
+#define        CHANNEL_108G    CHANNEL_TG
+#define        CHANNEL_X       (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR)
+
+#define        CHANNEL_ALL     (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_2GHZ|CHANNEL_5GHZ| \
+               CHANNEL_TURBO)
+
+#define        CHANNEL_ALL_NOTURBO     (CHANNEL_ALL & ~CHANNEL_TURBO)
+#define CHANNEL_MODES          CHANNEL_ALL
+
+/*
+ * Used internaly for reset_tx_queue).
+ * Also see struct struct net80211_channel.
+ */
+#define IS_CHAN_XR(_c) ((_c->hw_value & CHANNEL_XR) != 0)
+#define IS_CHAN_B(_c)  ((_c->hw_value & CHANNEL_B) != 0)
+
+/*
+ * The following structure is used to map 2GHz channels to
+ * 5GHz Atheros channels.
+ * TODO: Clean up
+ */
+struct ath5k_athchan_2ghz {
+       u32     a2_flags;
+       u16     a2_athchan;
+};
+
+
+/******************\
+  RATE DEFINITIONS
+\******************/
+
+/**
+ * Seems the ar5xxx harware supports up to 32 rates, indexed by 1-32.
+ *
+ * The rate code is used to get the RX rate or set the TX rate on the
+ * hardware descriptors. It is also used for internal modulation control
+ * and settings.
+ *
+ * This is the hardware rate map we are aware of:
+ *
+ * rate_code   0x01    0x02    0x03    0x04    0x05    0x06    0x07    0x08
+ * rate_kbps   3000    1000    ?       ?       ?       2000    500     48000
+ *
+ * rate_code   0x09    0x0A    0x0B    0x0C    0x0D    0x0E    0x0F    0x10
+ * rate_kbps   24000   12000   6000    54000   36000   18000   9000    ?
+ *
+ * rate_code   17      18      19      20      21      22      23      24
+ * rate_kbps   ?       ?       ?       ?       ?       ?       ?       11000
+ *
+ * rate_code   25      26      27      28      29      30      31      32
+ * rate_kbps   5500    2000    1000    11000S  5500S   2000S   ?       ?
+ *
+ * "S" indicates CCK rates with short preamble.
+ *
+ * AR5211 has different rate codes for CCK (802.11B) rates. It only uses the
+ * lowest 4 bits, so they are the same as below with a 0xF mask.
+ * (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M).
+ * We handle this in ath5k_setup_bands().
+ */
+#define AR5K_MAX_RATES 32
+
+/* B */
+#define ATH5K_RATE_CODE_1M     0x1B
+#define ATH5K_RATE_CODE_2M     0x1A
+#define ATH5K_RATE_CODE_5_5M   0x19
+#define ATH5K_RATE_CODE_11M    0x18
+/* A and G */
+#define ATH5K_RATE_CODE_6M     0x0B
+#define ATH5K_RATE_CODE_9M     0x0F
+#define ATH5K_RATE_CODE_12M    0x0A
+#define ATH5K_RATE_CODE_18M    0x0E
+#define ATH5K_RATE_CODE_24M    0x09
+#define ATH5K_RATE_CODE_36M    0x0D
+#define ATH5K_RATE_CODE_48M    0x08
+#define ATH5K_RATE_CODE_54M    0x0C
+/* XR */
+#define ATH5K_RATE_CODE_XR_500K        0x07
+#define ATH5K_RATE_CODE_XR_1M  0x02
+#define ATH5K_RATE_CODE_XR_2M  0x06
+#define ATH5K_RATE_CODE_XR_3M  0x01
+
+/* adding this flag to rate_code enables short preamble */
+#define AR5K_SET_SHORT_PREAMBLE 0x04
+
+/*
+ * Crypto definitions
+ */
+
+#define AR5K_KEYCACHE_SIZE     8
+
+/***********************\
+ HW RELATED DEFINITIONS
+\***********************/
+
+/*
+ * Misc definitions
+ */
+#define        AR5K_RSSI_EP_MULTIPLIER (1<<7)
+
+#define AR5K_ASSERT_ENTRY(_e, _s) do {         \
+       if (_e >= _s)                           \
+               return 0;                       \
+} while (0)
+
+/*
+ * Hardware interrupt abstraction
+ */
+
+/**
+ * enum ath5k_int - Hardware interrupt masks helpers
+ *
+ * @AR5K_INT_RX: mask to identify received frame interrupts, of type
+ *     AR5K_ISR_RXOK or AR5K_ISR_RXERR
+ * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor (?)
+ * @AR5K_INT_RXNOFRM: No frame received (?)
+ * @AR5K_INT_RXEOL: received End Of List for VEOL (Virtual End Of List). The
+ *     Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's
+ *     LinkPtr is NULL. For more details, refer to:
+ *     http://www.freepatentsonline.com/20030225739.html
+ * @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors).
+ *     Note that Rx overrun is not always fatal, on some chips we can continue
+ *     operation without reseting the card, that's why int_fatal is not
+ *     common for all chips.
+ * @AR5K_INT_TX: mask to identify received frame interrupts, of type
+ *     AR5K_ISR_TXOK or AR5K_ISR_TXERR
+ * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?)
+ * @AR5K_INT_TXURN: received when we should increase the TX trigger threshold
+ *     We currently do increments on interrupt by
+ *     (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2
+ * @AR5K_INT_MIB: Indicates the Management Information Base counters should be
+ *     checked. We should do this with ath5k_hw_update_mib_counters() but
+ *     it seems we should also then do some noise immunity work.
+ * @AR5K_INT_RXPHY: RX PHY Error
+ * @AR5K_INT_RXKCM: RX Key cache miss
+ * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a
+ *     beacon that must be handled in software. The alternative is if you
+ *     have VEOL support, in that case you let the hardware deal with things.
+ * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing
+ *     beacons from the AP have associated with, we should probably try to
+ *     reassociate. When in IBSS mode this might mean we have not received
+ *     any beacons from any local stations. Note that every station in an
+ *     IBSS schedules to send beacons at the Target Beacon Transmission Time
+ *     (TBTT) with a random backoff.
+ * @AR5K_INT_BNR: Beacon Not Ready interrupt - ??
+ * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill, disabled for now
+ *     until properly handled
+ * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA
+ *     errors. These types of errors we can enable seem to be of type
+ *     AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR.
+ * @AR5K_INT_GLOBAL: Used to clear and set the IER
+ * @AR5K_INT_NOCARD: signals the card has been removed
+ * @AR5K_INT_COMMON: common interrupts shared amogst MACs with the same
+ *     bit value
+ *
+ * These are mapped to take advantage of some common bits
+ * between the MACs, to be able to set intr properties
+ * easier. Some of them are not used yet inside hw.c. Most map
+ * to the respective hw interrupt value as they are common amogst different
+ * MACs.
+ */
+enum ath5k_int {
+       AR5K_INT_RXOK   = 0x00000001,
+       AR5K_INT_RXDESC = 0x00000002,
+       AR5K_INT_RXERR  = 0x00000004,
+       AR5K_INT_RXNOFRM = 0x00000008,
+       AR5K_INT_RXEOL  = 0x00000010,
+       AR5K_INT_RXORN  = 0x00000020,
+       AR5K_INT_TXOK   = 0x00000040,
+       AR5K_INT_TXDESC = 0x00000080,
+       AR5K_INT_TXERR  = 0x00000100,
+       AR5K_INT_TXNOFRM = 0x00000200,
+       AR5K_INT_TXEOL  = 0x00000400,
+       AR5K_INT_TXURN  = 0x00000800,
+       AR5K_INT_MIB    = 0x00001000,
+       AR5K_INT_SWI    = 0x00002000,
+       AR5K_INT_RXPHY  = 0x00004000,
+       AR5K_INT_RXKCM  = 0x00008000,
+       AR5K_INT_SWBA   = 0x00010000,
+       AR5K_INT_BRSSI  = 0x00020000,
+       AR5K_INT_BMISS  = 0x00040000,
+       AR5K_INT_FATAL  = 0x00080000, /* Non common */
+       AR5K_INT_BNR    = 0x00100000, /* Non common */
+       AR5K_INT_TIM    = 0x00200000, /* Non common */
+       AR5K_INT_DTIM   = 0x00400000, /* Non common */
+       AR5K_INT_DTIM_SYNC =    0x00800000, /* Non common */
+       AR5K_INT_GPIO   =       0x01000000,
+       AR5K_INT_BCN_TIMEOUT =  0x02000000, /* Non common */
+       AR5K_INT_CAB_TIMEOUT =  0x04000000, /* Non common */
+       AR5K_INT_RX_DOPPLER =   0x08000000, /* Non common */
+       AR5K_INT_QCBRORN =      0x10000000, /* Non common */
+       AR5K_INT_QCBRURN =      0x20000000, /* Non common */
+       AR5K_INT_QTRIG  =       0x40000000, /* Non common */
+       AR5K_INT_GLOBAL =       0x80000000,
+
+       AR5K_INT_COMMON  = AR5K_INT_RXOK
+               | AR5K_INT_RXDESC
+               | AR5K_INT_RXERR
+               | AR5K_INT_RXNOFRM
+               | AR5K_INT_RXEOL
+               | AR5K_INT_RXORN
+               | AR5K_INT_TXOK
+               | AR5K_INT_TXDESC
+               | AR5K_INT_TXERR
+               | AR5K_INT_TXNOFRM
+               | AR5K_INT_TXEOL
+               | AR5K_INT_TXURN
+               | AR5K_INT_MIB
+               | AR5K_INT_SWI
+               | AR5K_INT_RXPHY
+               | AR5K_INT_RXKCM
+               | AR5K_INT_SWBA
+               | AR5K_INT_BRSSI
+               | AR5K_INT_BMISS
+               | AR5K_INT_GPIO
+               | AR5K_INT_GLOBAL,
+
+       AR5K_INT_NOCARD = 0xffffffff
+};
+
+/*
+ * Power management
+ */
+enum ath5k_power_mode {
+       AR5K_PM_UNDEFINED = 0,
+       AR5K_PM_AUTO,
+       AR5K_PM_AWAKE,
+       AR5K_PM_FULL_SLEEP,
+       AR5K_PM_NETWORK_SLEEP,
+};
+
+/* GPIO-controlled software LED */
+#define AR5K_SOFTLED_PIN       0
+#define AR5K_SOFTLED_ON                0
+#define AR5K_SOFTLED_OFF       1
+
+/*
+ * Chipset capabilities -see ath5k_hw_get_capability-
+ * get_capability function is not yet fully implemented
+ * in ath5k so most of these don't work yet...
+ * TODO: Implement these & merge with _TUNE_ stuff above
+ */
+enum ath5k_capability_type {
+       AR5K_CAP_REG_DMN                = 0,    /* Used to get current reg. domain id */
+       AR5K_CAP_TKIP_MIC               = 2,    /* Can handle TKIP MIC in hardware */
+       AR5K_CAP_TKIP_SPLIT             = 3,    /* TKIP uses split keys */
+       AR5K_CAP_PHYCOUNTERS            = 4,    /* PHY error counters */
+       AR5K_CAP_DIVERSITY              = 5,    /* Supports fast diversity */
+       AR5K_CAP_NUM_TXQUEUES           = 6,    /* Used to get max number of hw txqueues */
+       AR5K_CAP_VEOL                   = 7,    /* Supports virtual EOL */
+       AR5K_CAP_COMPRESSION            = 8,    /* Supports compression */
+       AR5K_CAP_BURST                  = 9,    /* Supports packet bursting */
+       AR5K_CAP_FASTFRAME              = 10,   /* Supports fast frames */
+       AR5K_CAP_TXPOW                  = 11,   /* Used to get global tx power limit */
+       AR5K_CAP_TPC                    = 12,   /* Can do per-packet tx power control (needed for 802.11a) */
+       AR5K_CAP_BSSIDMASK              = 13,   /* Supports bssid mask */
+       AR5K_CAP_MCAST_KEYSRCH          = 14,   /* Supports multicast key search */
+       AR5K_CAP_TSF_ADJUST             = 15,   /* Supports beacon tsf adjust */
+       AR5K_CAP_XR                     = 16,   /* Supports XR mode */
+       AR5K_CAP_WME_TKIPMIC            = 17,   /* Supports TKIP MIC when using WMM */
+       AR5K_CAP_CHAN_HALFRATE          = 18,   /* Supports half rate channels */
+       AR5K_CAP_CHAN_QUARTERRATE       = 19,   /* Supports quarter rate channels */
+       AR5K_CAP_RFSILENT               = 20,   /* Supports RFsilent */
+};
+
+
+/* XXX: we *may* move cap_range stuff to struct wiphy */
+struct ath5k_capabilities {
+       /*
+        * Supported PHY modes
+        * (ie. CHANNEL_A, CHANNEL_B, ...)
+        */
+       u16 cap_mode;
+
+       /*
+        * Frequency range (without regulation restrictions)
+        */
+       struct {
+               u16     range_2ghz_min;
+               u16     range_2ghz_max;
+               u16     range_5ghz_min;
+               u16     range_5ghz_max;
+       } cap_range;
+
+       /*
+        * Values stored in the EEPROM (some of them...)
+        */
+       struct ath5k_eeprom_info        cap_eeprom;
+
+       /*
+        * Queue information
+        */
+       struct {
+               u8      q_tx_num;
+       } cap_queues;
+};
+
+
+/***************************************\
+  HARDWARE ABSTRACTION LAYER STRUCTURE
+\***************************************/
+
+/*
+ * Misc defines
+ */
+
+#define AR5K_MAX_GPIO          10
+#define AR5K_MAX_RF_BANKS      8
+
+/* TODO: Clean up and merge with ath5k_softc */
+struct ath5k_hw {
+       struct ath5k_softc      *ah_sc;
+       void                    *ah_iobase;
+
+       enum ath5k_int          ah_imr;
+       int                     ah_ier;
+
+       struct net80211_channel *ah_current_channel;
+       int                     ah_turbo;
+       int                     ah_calibration;
+       int                     ah_running;
+       int                     ah_single_chip;
+       int                     ah_combined_mic;
+
+       u32                     ah_mac_srev;
+       u16                     ah_mac_version;
+       u16                     ah_mac_revision;
+       u16                     ah_phy_revision;
+       u16                     ah_radio_5ghz_revision;
+       u16                     ah_radio_2ghz_revision;
+
+       enum ath5k_version      ah_version;
+       enum ath5k_radio        ah_radio;
+       u32                     ah_phy;
+
+       int                     ah_5ghz;
+       int                     ah_2ghz;
+
+#define ah_regdomain           ah_capabilities.cap_regdomain.reg_current
+#define ah_regdomain_hw                ah_capabilities.cap_regdomain.reg_hw
+#define ah_modes               ah_capabilities.cap_mode
+#define ah_ee_version          ah_capabilities.cap_eeprom.ee_version
+
+       u32                     ah_atim_window;
+       u32                     ah_aifs;
+       u32                     ah_cw_min;
+       u32                     ah_cw_max;
+       int                     ah_software_retry;
+       u32                     ah_limit_tx_retries;
+
+       u32                     ah_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
+       int                     ah_ant_diversity;
+
+       u8                      ah_sta_id[ETH_ALEN];
+
+       /* Current BSSID we are trying to assoc to / create.
+        * This is passed by mac80211 on config_interface() and cached here for
+        * use in resets */
+       u8                      ah_bssid[ETH_ALEN];
+       u8                      ah_bssid_mask[ETH_ALEN];
+
+       u32                     ah_gpio[AR5K_MAX_GPIO];
+       int                     ah_gpio_npins;
+
+       struct ath5k_capabilities ah_capabilities;
+
+       struct ath5k_txq_info   ah_txq;
+       u32                     ah_txq_status;
+       u32                     ah_txq_imr_txok;
+       u32                     ah_txq_imr_txerr;
+       u32                     ah_txq_imr_txurn;
+       u32                     ah_txq_imr_txdesc;
+       u32                     ah_txq_imr_txeol;
+       u32                     ah_txq_imr_cbrorn;
+       u32                     ah_txq_imr_cbrurn;
+       u32                     ah_txq_imr_qtrig;
+       u32                     ah_txq_imr_nofrm;
+       u32                     ah_txq_isr;
+       u32                     *ah_rf_banks;
+       size_t                  ah_rf_banks_size;
+       size_t                  ah_rf_regs_count;
+       struct ath5k_gain       ah_gain;
+       u8                      ah_offset[AR5K_MAX_RF_BANKS];
+
+
+       struct {
+               /* Temporary tables used for interpolation */
+               u8              tmpL[AR5K_EEPROM_N_PD_GAINS]
+                                       [AR5K_EEPROM_POWER_TABLE_SIZE];
+               u8              tmpR[AR5K_EEPROM_N_PD_GAINS]
+                                       [AR5K_EEPROM_POWER_TABLE_SIZE];
+               u8              txp_pd_table[AR5K_EEPROM_POWER_TABLE_SIZE * 2];
+               u16             txp_rates_power_table[AR5K_MAX_RATES];
+               u8              txp_min_idx;
+               int             txp_tpc;
+               /* Values in 0.25dB units */
+               s16             txp_min_pwr;
+               s16             txp_max_pwr;
+               s16             txp_offset;
+               s16             txp_ofdm;
+               /* Values in dB units */
+               s16             txp_cck_ofdm_pwr_delta;
+               s16             txp_cck_ofdm_gainf_delta;
+       } ah_txpower;
+
+       /* noise floor from last periodic calibration */
+       s32                     ah_noise_floor;
+
+       /*
+        * Function pointers
+        */
+       int (*ah_setup_rx_desc)(struct ath5k_hw *ah, struct ath5k_desc *desc,
+                               u32 size, unsigned int flags);
+       int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
+               unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int,
+               unsigned int, unsigned int, unsigned int, unsigned int,
+               unsigned int, unsigned int, unsigned int);
+       int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
+               struct ath5k_tx_status *);
+       int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *,
+               struct ath5k_rx_status *);
+};
+
+/*
+ * Prototypes
+ */
+
+extern int ath5k_bitrate_to_hw_rix(int bitrate);
+
+/* Attach/Detach Functions */
+extern int ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version, struct ath5k_hw **ah);
+extern void ath5k_hw_detach(struct ath5k_hw *ah);
+
+/* LED functions */
+extern int ath5k_init_leds(struct ath5k_softc *sc);
+extern void ath5k_led_enable(struct ath5k_softc *sc);
+extern void ath5k_led_off(struct ath5k_softc *sc);
+extern void ath5k_unregister_leds(struct ath5k_softc *sc);
+
+/* Reset Functions */
+extern int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, int initial);
+extern int ath5k_hw_reset(struct ath5k_hw *ah, struct net80211_channel *channel, int change_channel);
+/* Power management functions */
+extern int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode, int set_chip, u16 sleep_duration);
+
+/* DMA Related Functions */
+extern void ath5k_hw_start_rx_dma(struct ath5k_hw *ah);
+extern int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah);
+extern u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah);
+extern void ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr);
+extern int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue);
+extern int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue);
+extern u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue);
+extern int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue,
+                               u32 phys_addr);
+extern int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, int increase);
+/* Interrupt handling */
+extern int ath5k_hw_is_intr_pending(struct ath5k_hw *ah);
+extern int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask);
+extern enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask);
+
+/* EEPROM access functions */
+extern int ath5k_eeprom_init(struct ath5k_hw *ah);
+extern void ath5k_eeprom_detach(struct ath5k_hw *ah);
+extern int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac);
+extern int ath5k_eeprom_is_hb63(struct ath5k_hw *ah);
+
+/* Protocol Control Unit Functions */
+extern int ath5k_hw_set_opmode(struct ath5k_hw *ah);
+/* BSSID Functions */
+extern void ath5k_hw_get_lladdr(struct ath5k_hw *ah, u8 *mac);
+extern int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac);
+extern void ath5k_hw_set_associd(struct ath5k_hw *ah, const u8 *bssid, u16 assoc_id);
+extern int ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask);
+/* Receive start/stop functions */
+extern void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah);
+extern void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah);
+/* RX Filter functions */
+extern void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1);
+extern u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah);
+extern void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter);
+/* ACK bit rate */
+void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, int high);
+/* ACK/CTS Timeouts */
+extern int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout);
+extern unsigned int ath5k_hw_get_ack_timeout(struct ath5k_hw *ah);
+extern int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout);
+extern unsigned int ath5k_hw_get_cts_timeout(struct ath5k_hw *ah);
+/* Key table (WEP) functions */
+extern int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry);
+
+/* Queue Control Unit, DFS Control Unit Functions */
+extern int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, const struct ath5k_txq_info *queue_info);
+extern int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah,
+                               enum ath5k_tx_queue queue_type,
+                               struct ath5k_txq_info *queue_info);
+extern u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah);
+extern void ath5k_hw_release_tx_queue(struct ath5k_hw *ah);
+extern int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah);
+extern int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time);
+
+/* Hardware Descriptor Functions */
+extern int ath5k_hw_init_desc_functions(struct ath5k_hw *ah);
+
+/* GPIO Functions */
+extern int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio);
+extern int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio);
+extern u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio);
+extern int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val);
+extern void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio, u32 interrupt_level);
+
+/* Misc functions */
+int ath5k_hw_set_capabilities(struct ath5k_hw *ah);
+extern int ath5k_hw_get_capability(struct ath5k_hw *ah, enum ath5k_capability_type cap_type, u32 capability, u32 *result);
+extern int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id);
+extern int ath5k_hw_disable_pspoll(struct ath5k_hw *ah);
+
+/* Initial register settings functions */
+extern int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, int change_channel);
+
+/* Initialize RF */
+extern int ath5k_hw_rfregs_init(struct ath5k_hw *ah,
+                               struct net80211_channel *channel,
+                               unsigned int mode);
+extern int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq);
+extern enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah);
+extern int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah);
+/* PHY/RF channel functions */
+extern int ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags);
+extern int ath5k_hw_channel(struct ath5k_hw *ah, struct net80211_channel *channel);
+/* PHY calibration */
+extern int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, struct net80211_channel *channel);
+extern int ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq);
+/* Misc PHY functions */
+extern u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan);
+extern void ath5k_hw_set_def_antenna(struct ath5k_hw *ah, unsigned int ant);
+extern unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah);
+extern int ath5k_hw_phy_disable(struct ath5k_hw *ah);
+/* TX power setup */
+extern int ath5k_hw_txpower(struct ath5k_hw *ah, struct net80211_channel *channel, u8 ee_mode, u8 txpower);
+extern int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 ee_mode, u8 txpower);
+
+/*
+ * Functions used internaly
+ */
+
+/*
+ * Translate usec to hw clock units
+ * TODO: Half/quarter rate
+ */
+static inline unsigned int ath5k_hw_htoclock(unsigned int usec, int turbo)
+{
+       return turbo ? (usec * 80) : (usec * 40);
+}
+
+/*
+ * Translate hw clock units to usec
+ * TODO: Half/quarter rate
+ */
+static inline unsigned int ath5k_hw_clocktoh(unsigned int clock, int turbo)
+{
+       return turbo ? (clock / 80) : (clock / 40);
+}
+
+/*
+ * Read from a register
+ */
+static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
+{
+       return readl(ah->ah_iobase + reg);
+}
+
+/*
+ * Write to a register
+ */
+static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
+{
+       writel(val, ah->ah_iobase + reg);
+}
+
+#if defined(_ATH5K_RESET) || defined(_ATH5K_PHY)
+/*
+ * Check if a register write has been completed
+ */
+static int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag,
+               u32 val, int is_set)
+{
+       int i;
+       u32 data;
+
+       for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
+               data = ath5k_hw_reg_read(ah, reg);
+               if (is_set && (data & flag))
+                       break;
+               else if ((data & flag) == val)
+                       break;
+               udelay(15);
+       }
+
+       return (i <= 0) ? -EAGAIN : 0;
+}
+
+/*
+ * Convert channel frequency to channel number
+ */
+static inline int ath5k_freq_to_channel(int freq)
+{
+       if (freq == 2484)
+               return 14;
+
+       if (freq < 2484)
+               return (freq - 2407) / 5;
+
+       return freq/5 - 1000;
+}
+
+#endif
+
+static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits)
+{
+       u32 retval = 0, bit, i;
+
+       for (i = 0; i < bits; i++) {
+               bit = (val >> i) & 1;
+               retval = (retval << 1) | bit;
+       }
+
+       return retval;
+}
+
+#endif
diff --git a/src/drivers/net/ath5k/ath5k_attach.c b/src/drivers/net/ath5k/ath5k_attach.c
new file mode 100644 (file)
index 0000000..36dc243
--- /dev/null
@@ -0,0 +1,340 @@
+/*
+ * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
+ * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
+ *
+ * Modified for gPXE, July 2009, by Joshua Oreman <oremanj@rwcr.net>
+ * Original from Linux kernel 2.6.30.
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+FILE_LICENCE ( MIT );
+
+/*************************************\
+* Attach/Detach Functions and helpers *
+\*************************************/
+
+#include <gpxe/pci.h>
+#include <unistd.h>
+#include <stdlib.h>
+#include "ath5k.h"
+#include "reg.h"
+#include "base.h"
+
+/**
+ * ath5k_hw_post - Power On Self Test helper function
+ *
+ * @ah: The &struct ath5k_hw
+ */
+static int ath5k_hw_post(struct ath5k_hw *ah)
+{
+
+       static const u32 static_pattern[4] = {
+               0x55555555,     0xaaaaaaaa,
+               0x66666666,     0x99999999
+       };
+       static const u16 regs[2] = { AR5K_STA_ID0, AR5K_PHY(8) };
+       int i, c;
+       u16 cur_reg;
+       u32 var_pattern;
+       u32 init_val;
+       u32 cur_val;
+
+       for (c = 0; c < 2; c++) {
+
+               cur_reg = regs[c];
+
+               /* Save previous value */
+               init_val = ath5k_hw_reg_read(ah, cur_reg);
+
+               for (i = 0; i < 256; i++) {
+                       var_pattern = i << 16 | i;
+                       ath5k_hw_reg_write(ah, var_pattern, cur_reg);
+                       cur_val = ath5k_hw_reg_read(ah, cur_reg);
+
+                       if (cur_val != var_pattern) {
+                               DBG("ath5k: POST failed!\n");
+                               return -EAGAIN;
+                       }
+
+                       /* Found on ndiswrapper dumps */
+                       var_pattern = 0x0039080f;
+                       ath5k_hw_reg_write(ah, var_pattern, cur_reg);
+               }
+
+               for (i = 0; i < 4; i++) {
+                       var_pattern = static_pattern[i];
+                       ath5k_hw_reg_write(ah, var_pattern, cur_reg);
+                       cur_val = ath5k_hw_reg_read(ah, cur_reg);
+
+                       if (cur_val != var_pattern) {
+                               DBG("ath5k: POST failed!\n");
+                               return -EAGAIN;
+                       }
+
+                       /* Found on ndiswrapper dumps */
+                       var_pattern = 0x003b080f;
+                       ath5k_hw_reg_write(ah, var_pattern, cur_reg);
+               }
+
+               /* Restore previous value */
+               ath5k_hw_reg_write(ah, init_val, cur_reg);
+
+       }
+
+       return 0;
+
+}
+
+/**
+ * ath5k_hw_attach - Check if hw is supported and init the needed structs
+ *
+ * @sc: The &struct ath5k_softc we got from the driver's attach function
+ * @mac_version: The mac version id (check out ath5k.h) based on pci id
+ * @hw: Returned newly allocated hardware structure, on success
+ *
+ * Check if the device is supported, perform a POST and initialize the needed
+ * structs. Returns -ENOMEM if we don't have memory for the needed structs,
+ * -ENODEV if the device is not supported or prints an error msg if something
+ * else went wrong.
+ */
+int ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version,
+                   struct ath5k_hw **hw)
+{
+       struct ath5k_hw *ah;
+       struct pci_device *pdev = sc->pdev;
+       int ret;
+       u32 srev;
+
+       ah = zalloc(sizeof(struct ath5k_hw));
+       if (ah == NULL) {
+               ret = -ENOMEM;
+               DBG("ath5k: out of memory\n");
+               goto err;
+       }
+
+       ah->ah_sc = sc;
+       ah->ah_iobase = sc->iobase;
+
+       /*
+        * HW information
+        */
+       ah->ah_turbo = 0;
+       ah->ah_txpower.txp_tpc = 0;
+       ah->ah_imr = 0;
+       ah->ah_atim_window = 0;
+       ah->ah_aifs = AR5K_TUNE_AIFS;
+       ah->ah_cw_min = AR5K_TUNE_CWMIN;
+       ah->ah_limit_tx_retries = AR5K_INIT_TX_RETRY;
+       ah->ah_software_retry = 0;
+       ah->ah_ant_diversity = AR5K_TUNE_ANT_DIVERSITY;
+
+       /*
+        * Set the mac version based on the pci id
+        */
+       ah->ah_version = mac_version;
+
+       /*Fill the ath5k_hw struct with the needed functions*/
+       ret = ath5k_hw_init_desc_functions(ah);
+       if (ret)
+               goto err_free;
+
+       /* Bring device out of sleep and reset it's units */
+       ret = ath5k_hw_nic_wakeup(ah, CHANNEL_B, 1);
+       if (ret)
+               goto err_free;
+
+       /* Get MAC, PHY and RADIO revisions */
+       srev = ath5k_hw_reg_read(ah, AR5K_SREV);
+       ah->ah_mac_srev = srev;
+       ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);
+       ah->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV);
+       ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID);
+       ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah, CHANNEL_5GHZ);
+       ah->ah_phy = AR5K_PHY(0);
+
+       /* Try to identify radio chip based on it's srev */
+       switch (ah->ah_radio_5ghz_revision & 0xf0) {
+       case AR5K_SREV_RAD_5111:
+               ah->ah_radio = AR5K_RF5111;
+               ah->ah_single_chip = 0;
+               ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
+                                                       CHANNEL_2GHZ);
+               break;
+       case AR5K_SREV_RAD_5112:
+       case AR5K_SREV_RAD_2112:
+               ah->ah_radio = AR5K_RF5112;
+               ah->ah_single_chip = 0;
+               ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
+                                                       CHANNEL_2GHZ);
+               break;
+       case AR5K_SREV_RAD_2413:
+               ah->ah_radio = AR5K_RF2413;
+               ah->ah_single_chip = 1;
+               break;
+       case AR5K_SREV_RAD_5413:
+               ah->ah_radio = AR5K_RF5413;
+               ah->ah_single_chip = 1;
+               break;
+       case AR5K_SREV_RAD_2316:
+               ah->ah_radio = AR5K_RF2316;
+               ah->ah_single_chip = 1;
+               break;
+       case AR5K_SREV_RAD_2317:
+               ah->ah_radio = AR5K_RF2317;
+               ah->ah_single_chip = 1;
+               break;
+       case AR5K_SREV_RAD_5424:
+               if (ah->ah_mac_version == AR5K_SREV_AR2425 ||
+                   ah->ah_mac_version == AR5K_SREV_AR2417) {
+                       ah->ah_radio = AR5K_RF2425;
+               } else {
+                       ah->ah_radio = AR5K_RF5413;
+               }
+               ah->ah_single_chip = 1;
+               break;
+       default:
+               /* Identify radio based on mac/phy srev */
+               if (ah->ah_version == AR5K_AR5210) {
+                       ah->ah_radio = AR5K_RF5110;
+                       ah->ah_single_chip = 0;
+               } else if (ah->ah_version == AR5K_AR5211) {
+                       ah->ah_radio = AR5K_RF5111;
+                       ah->ah_single_chip = 0;
+                       ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
+                                                               CHANNEL_2GHZ);
+               } else if (ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4) ||
+                          ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4) ||
+                          ah->ah_phy_revision == AR5K_SREV_PHY_2425) {
+                       ah->ah_radio = AR5K_RF2425;
+                       ah->ah_single_chip = 1;
+                       ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2425;
+               } else if (srev == AR5K_SREV_AR5213A &&
+                          ah->ah_phy_revision == AR5K_SREV_PHY_5212B) {
+                       ah->ah_radio = AR5K_RF5112;
+                       ah->ah_single_chip = 0;
+                       ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5112B;
+               } else if (ah->ah_mac_version == (AR5K_SREV_AR2415 >> 4)) {
+                       ah->ah_radio = AR5K_RF2316;
+                       ah->ah_single_chip = 1;
+                       ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2316;
+               } else if (ah->ah_mac_version == (AR5K_SREV_AR5414 >> 4) ||
+                          ah->ah_phy_revision == AR5K_SREV_PHY_5413) {
+                       ah->ah_radio = AR5K_RF5413;
+                       ah->ah_single_chip = 1;
+                       ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5413;
+               } else if (ah->ah_mac_version == (AR5K_SREV_AR2414 >> 4) ||
+                          ah->ah_phy_revision == AR5K_SREV_PHY_2413) {
+                       ah->ah_radio = AR5K_RF2413;
+                       ah->ah_single_chip = 1;
+                       ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2413;
+               } else {
+                       DBG("ath5k: Couldn't identify radio revision.\n");
+                       ret = -ENOTSUP;
+                       goto err_free;
+               }
+       }
+
+       /* Return on unsuported chips (unsupported eeprom etc) */
+       if ((srev >= AR5K_SREV_AR5416) &&
+           (srev < AR5K_SREV_AR2425)) {
+               DBG("ath5k: Device not yet supported.\n");
+               ret = -ENOTSUP;
+               goto err_free;
+       }
+
+       /*
+        * Write PCI-E power save settings
+        */
+       if ((ah->ah_version == AR5K_AR5212) &&
+           pci_find_capability(pdev, PCI_CAP_ID_EXP)) {
+               ath5k_hw_reg_write(ah, 0x9248fc00, AR5K_PCIE_SERDES);
+               ath5k_hw_reg_write(ah, 0x24924924, AR5K_PCIE_SERDES);
+               /* Shut off RX when elecidle is asserted */
+               ath5k_hw_reg_write(ah, 0x28000039, AR5K_PCIE_SERDES);
+               ath5k_hw_reg_write(ah, 0x53160824, AR5K_PCIE_SERDES);
+               /* TODO: EEPROM work */
+               ath5k_hw_reg_write(ah, 0xe5980579, AR5K_PCIE_SERDES);
+               /* Shut off PLL and CLKREQ active in L1 */
+               ath5k_hw_reg_write(ah, 0x001defff, AR5K_PCIE_SERDES);
+               /* Preserce other settings */
+               ath5k_hw_reg_write(ah, 0x1aaabe40, AR5K_PCIE_SERDES);
+               ath5k_hw_reg_write(ah, 0xbe105554, AR5K_PCIE_SERDES);
+               ath5k_hw_reg_write(ah, 0x000e3007, AR5K_PCIE_SERDES);
+               /* Reset SERDES to load new settings */
+               ath5k_hw_reg_write(ah, 0x00000000, AR5K_PCIE_SERDES_RESET);
+               mdelay(1);
+       }
+
+       /*
+        * POST
+        */
+       ret = ath5k_hw_post(ah);
+       if (ret)
+               goto err_free;
+
+       /* Enable pci core retry fix on Hainan (5213A) and later chips */
+       if (srev >= AR5K_SREV_AR5213A)
+               ath5k_hw_reg_write(ah, AR5K_PCICFG_RETRY_FIX, AR5K_PCICFG);
+
+       /*
+        * Get card capabilities, calibration values etc
+        * TODO: EEPROM work
+        */
+       ret = ath5k_eeprom_init(ah);
+       if (ret) {
+               DBG("ath5k: unable to init EEPROM\n");
+               goto err_free;
+       }
+
+       /* Get misc capabilities */
+       ret = ath5k_hw_set_capabilities(ah);
+       if (ret) {
+               DBG("ath5k: unable to get device capabilities: 0x%04x\n",
+                   sc->pdev->device);
+               goto err_free;
+       }
+
+       if (srev >= AR5K_SREV_AR2414) {
+               ah->ah_combined_mic = 1;
+               AR5K_REG_ENABLE_BITS(ah, AR5K_MISC_MODE,
+                                    AR5K_MISC_MODE_COMBINED_MIC);
+       }
+
+       /* Set BSSID to bcast address: ff:ff:ff:ff:ff:ff for now */
+       memset(ah->ah_bssid, 0xff, ETH_ALEN);
+       ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
+       ath5k_hw_set_opmode(ah);
+
+       ath5k_hw_rfgain_opt_init(ah);
+
+       *hw = ah;
+       return 0;
+err_free:
+       free(ah);
+err:
+       return ret;
+}
+
+/**
+ * ath5k_hw_detach - Free the ath5k_hw struct
+ *
+ * @ah: The &struct ath5k_hw
+ */
+void ath5k_hw_detach(struct ath5k_hw *ah)
+{
+       free(ah->ah_rf_banks);
+       ath5k_eeprom_detach(ah);
+       free(ah);
+}
diff --git a/src/drivers/net/ath5k/ath5k_caps.c b/src/drivers/net/ath5k/ath5k_caps.c
new file mode 100644 (file)
index 0000000..1d60d74
--- /dev/null
@@ -0,0 +1,154 @@
+/*
+ * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
+ * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
+ * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
+ *
+ * Lightly modified for gPXE, July 2009, by Joshua Oreman <oremanj@rwcr.net>.
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+FILE_LICENCE ( MIT );
+
+/**************\
+* Capabilities *
+\**************/
+
+#include "ath5k.h"
+#include "reg.h"
+#include "base.h"
+
+/*
+ * Fill the capabilities struct
+ * TODO: Merge this with EEPROM code when we are done with it
+ */
+int ath5k_hw_set_capabilities(struct ath5k_hw *ah)
+{
+       u16 ee_header;
+
+       /* Capabilities stored in the EEPROM */
+       ee_header = ah->ah_capabilities.cap_eeprom.ee_header;
+
+       if (ah->ah_version == AR5K_AR5210) {
+               /*
+                * Set radio capabilities
+                * (The AR5110 only supports the middle 5GHz band)
+                */
+               ah->ah_capabilities.cap_range.range_5ghz_min = 5120;
+               ah->ah_capabilities.cap_range.range_5ghz_max = 5430;
+               ah->ah_capabilities.cap_range.range_2ghz_min = 0;
+               ah->ah_capabilities.cap_range.range_2ghz_max = 0;
+
+               /* Set supported modes */
+               ah->ah_capabilities.cap_mode |= AR5K_MODE_BIT_11A;
+               ah->ah_capabilities.cap_mode |= AR5K_MODE_BIT_11A_TURBO;
+       } else {
+               /*
+                * XXX The tranceiver supports frequencies from 4920 to 6100GHz
+                * XXX and from 2312 to 2732GHz. There are problems with the
+                * XXX current ieee80211 implementation because the IEEE
+                * XXX channel mapping does not support negative channel
+                * XXX numbers (2312MHz is channel -19). Of course, this
+                * XXX doesn't matter because these channels are out of range
+                * XXX but some regulation domains like MKK (Japan) will
+                * XXX support frequencies somewhere around 4.8GHz.
+                */
+
+               /*
+                * Set radio capabilities
+                */
+
+               if (AR5K_EEPROM_HDR_11A(ee_header)) {
+                       /* 4920 */
+                       ah->ah_capabilities.cap_range.range_5ghz_min = 5005;
+                       ah->ah_capabilities.cap_range.range_5ghz_max = 6100;
+
+                       /* Set supported modes */
+                       ah->ah_capabilities.cap_mode |= AR5K_MODE_BIT_11A;
+                       ah->ah_capabilities.cap_mode |= AR5K_MODE_BIT_11A_TURBO;
+                       if (ah->ah_version == AR5K_AR5212)
+                               ah->ah_capabilities.cap_mode |=
+                                       AR5K_MODE_BIT_11G_TURBO;
+               }
+
+               /* Enable  802.11b if a 2GHz capable radio (2111/5112) is
+                * connected */
+               if (AR5K_EEPROM_HDR_11B(ee_header) ||
+                   (AR5K_EEPROM_HDR_11G(ee_header) &&
+                    ah->ah_version != AR5K_AR5211)) {
+                       /* 2312 */
+                       ah->ah_capabilities.cap_range.range_2ghz_min = 2412;
+                       ah->ah_capabilities.cap_range.range_2ghz_max = 2732;
+
+                       if (AR5K_EEPROM_HDR_11B(ee_header))
+                               ah->ah_capabilities.cap_mode |=
+                                       AR5K_MODE_BIT_11B;
+
+                       if (AR5K_EEPROM_HDR_11G(ee_header) &&
+                           ah->ah_version != AR5K_AR5211)
+                               ah->ah_capabilities.cap_mode |=
+                                       AR5K_MODE_BIT_11G;
+               }
+       }
+
+       /* GPIO */
+       ah->ah_gpio_npins = AR5K_NUM_GPIO;
+
+       /* Set number of supported TX queues */
+       ah->ah_capabilities.cap_queues.q_tx_num = 1;
+
+       return 0;
+}
+
+/* Main function used by the driver part to check caps */
+int ath5k_hw_get_capability(struct ath5k_hw *ah,
+               enum ath5k_capability_type cap_type,
+               u32 capability __unused, u32 *result)
+{
+       switch (cap_type) {
+       case AR5K_CAP_NUM_TXQUEUES:
+               if (result) {
+                       *result = 1;
+                       goto yes;
+               }
+       case AR5K_CAP_VEOL:
+               goto yes;
+       case AR5K_CAP_COMPRESSION:
+               if (ah->ah_version == AR5K_AR5212)
+                       goto yes;
+               else
+                       goto no;
+       case AR5K_CAP_BURST:
+               goto yes;
+       case AR5K_CAP_TPC:
+               goto yes;
+       case AR5K_CAP_BSSIDMASK:
+               if (ah->ah_version == AR5K_AR5212)
+                       goto yes;
+               else
+                       goto no;
+       case AR5K_CAP_XR:
+               if (ah->ah_version == AR5K_AR5212)
+                       goto yes;
+               else
+                       goto no;
+       default:
+               goto no;
+       }
+
+no:
+       return -EINVAL;
+yes:
+       return 0;
+}
diff --git a/src/drivers/net/ath5k/ath5k_desc.c b/src/drivers/net/ath5k/ath5k_desc.c
new file mode 100644 (file)
index 0000000..c839ec5
--- /dev/null
@@ -0,0 +1,554 @@
+/*
+ * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
+ * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
+ * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
+ *
+ * Lightly modified for gPXE, July 2009, by Joshua Oreman <oremanj@rwcr.net>.
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+FILE_LICENCE ( MIT );
+
+/******************************\
+ Hardware Descriptor Functions
+\******************************/
+
+#include "ath5k.h"
+#include "reg.h"
+#include "base.h"
+
+/*
+ * TX Descriptors
+ */
+
+#define FCS_LEN        4
+
+/*
+ * Initialize the 2-word tx control descriptor on 5210/5211
+ */
+static int
+ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
+       unsigned int pkt_len, unsigned int hdr_len, enum ath5k_pkt_type type,
+       unsigned int tx_power __unused, unsigned int tx_rate0, unsigned int tx_tries0,
+       unsigned int key_index __unused, unsigned int antenna_mode, unsigned int flags,
+       unsigned int rtscts_rate __unused, unsigned int rtscts_duration)
+{
+       u32 frame_type;
+       struct ath5k_hw_2w_tx_ctl *tx_ctl;
+       unsigned int frame_len;
+
+       tx_ctl = &desc->ud.ds_tx5210.tx_ctl;
+
+       /*
+        * Validate input
+        * - Zero retries don't make sense.
+        * - A zero rate will put the HW into a mode where it continously sends
+        *   noise on the channel, so it is important to avoid this.
+        */
+       if (tx_tries0 == 0) {
+               DBG("ath5k: zero retries\n");
+               return -EINVAL;
+       }
+       if (tx_rate0 == 0) {
+               DBG("ath5k: zero rate\n");
+               return -EINVAL;
+       }
+
+       /* Clear descriptor */
+       memset(&desc->ud.ds_tx5210, 0, sizeof(struct ath5k_hw_5210_tx_desc));
+
+       /* Setup control descriptor */
+
+       /* Verify and set frame length */
+
+       frame_len = pkt_len + FCS_LEN;
+
+       if (frame_len & ~AR5K_2W_TX_DESC_CTL0_FRAME_LEN)
+               return -EINVAL;
+
+       tx_ctl->tx_control_0 = frame_len & AR5K_2W_TX_DESC_CTL0_FRAME_LEN;
+
+       /* Verify and set buffer length */
+
+       if (pkt_len & ~AR5K_2W_TX_DESC_CTL1_BUF_LEN)
+               return -EINVAL;
+
+       tx_ctl->tx_control_1 = pkt_len & AR5K_2W_TX_DESC_CTL1_BUF_LEN;
+
+       /*
+        * Verify and set header length
+        * XXX: I only found that on 5210 code, does it work on 5211 ?
+        */
+       if (ah->ah_version == AR5K_AR5210) {
+               if (hdr_len & ~AR5K_2W_TX_DESC_CTL0_HEADER_LEN)
+                       return -EINVAL;
+               tx_ctl->tx_control_0 |=
+                       AR5K_REG_SM(hdr_len, AR5K_2W_TX_DESC_CTL0_HEADER_LEN);
+       }
+
+       /*Diferences between 5210-5211*/
+       if (ah->ah_version == AR5K_AR5210) {
+               switch (type) {
+               case AR5K_PKT_TYPE_BEACON:
+               case AR5K_PKT_TYPE_PROBE_RESP:
+                       frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY;
+               case AR5K_PKT_TYPE_PIFS:
+                       frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS;
+               default:
+                       frame_type = type /*<< 2 ?*/;
+               }
+
+               tx_ctl->tx_control_0 |=
+               AR5K_REG_SM(frame_type, AR5K_2W_TX_DESC_CTL0_FRAME_TYPE) |
+               AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE);
+
+       } else {
+               tx_ctl->tx_control_0 |=
+                       AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE) |
+                       AR5K_REG_SM(antenna_mode,
+                               AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT);
+               tx_ctl->tx_control_1 |=
+                       AR5K_REG_SM(type, AR5K_2W_TX_DESC_CTL1_FRAME_TYPE);
+       }
+#define _TX_FLAGS(_c, _flag)                                   \
+       if (flags & AR5K_TXDESC_##_flag) {                      \
+               tx_ctl->tx_control_##_c |=                      \
+                       AR5K_2W_TX_DESC_CTL##_c##_##_flag;      \
+       }
+
+       _TX_FLAGS(0, CLRDMASK);
+       _TX_FLAGS(0, VEOL);
+       _TX_FLAGS(0, INTREQ);
+       _TX_FLAGS(0, RTSENA);
+       _TX_FLAGS(1, NOACK);
+
+#undef _TX_FLAGS
+
+       /*
+        * RTS/CTS Duration [5210 ?]
+        */
+       if ((ah->ah_version == AR5K_AR5210) &&
+                       (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)))
+               tx_ctl->tx_control_1 |= rtscts_duration &
+                               AR5K_2W_TX_DESC_CTL1_RTS_DURATION;
+
+       return 0;
+}
+
+/*
+ * Initialize the 4-word tx control descriptor on 5212
+ */
+static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah,
+       struct ath5k_desc *desc, unsigned int pkt_len, unsigned int hdr_len __unused,
+       enum ath5k_pkt_type type, unsigned int tx_power, unsigned int tx_rate0,
+       unsigned int tx_tries0, unsigned int key_index __unused,
+       unsigned int antenna_mode, unsigned int flags,
+       unsigned int rtscts_rate,
+       unsigned int rtscts_duration)
+{
+       struct ath5k_hw_4w_tx_ctl *tx_ctl;
+       unsigned int frame_len;
+
+       tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
+
+       /*
+        * Validate input
+        * - Zero retries don't make sense.
+        * - A zero rate will put the HW into a mode where it continously sends
+        *   noise on the channel, so it is important to avoid this.
+        */
+       if (tx_tries0 == 0) {
+               DBG("ath5k: zero retries\n");
+               return -EINVAL;
+       }
+       if (tx_rate0 == 0) {
+               DBG("ath5k: zero rate\n");
+               return -EINVAL;
+       }
+
+       tx_power += ah->ah_txpower.txp_offset;
+       if (tx_power > AR5K_TUNE_MAX_TXPOWER)
+               tx_power = AR5K_TUNE_MAX_TXPOWER;
+
+       /* Clear descriptor */
+       memset(&desc->ud.ds_tx5212, 0, sizeof(struct ath5k_hw_5212_tx_desc));
+
+       /* Setup control descriptor */
+
+       /* Verify and set frame length */
+
+       frame_len = pkt_len + FCS_LEN;
+
+       if (frame_len & ~AR5K_4W_TX_DESC_CTL0_FRAME_LEN)
+               return -EINVAL;
+
+       tx_ctl->tx_control_0 = frame_len & AR5K_4W_TX_DESC_CTL0_FRAME_LEN;
+
+       /* Verify and set buffer length */
+
+       if (pkt_len & ~AR5K_4W_TX_DESC_CTL1_BUF_LEN)
+               return -EINVAL;
+
+       tx_ctl->tx_control_1 = pkt_len & AR5K_4W_TX_DESC_CTL1_BUF_LEN;
+
+       tx_ctl->tx_control_0 |=
+               AR5K_REG_SM(tx_power, AR5K_4W_TX_DESC_CTL0_XMIT_POWER) |
+               AR5K_REG_SM(antenna_mode, AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT);
+       tx_ctl->tx_control_1 |= AR5K_REG_SM(type,
+                                       AR5K_4W_TX_DESC_CTL1_FRAME_TYPE);
+       tx_ctl->tx_control_2 = AR5K_REG_SM(tx_tries0 + AR5K_TUNE_HWTXTRIES,
+                                       AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0);
+       tx_ctl->tx_control_3 = tx_rate0 & AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
+
+#define _TX_FLAGS(_c, _flag)                                   \
+       if (flags & AR5K_TXDESC_##_flag) {                      \
+               tx_ctl->tx_control_##_c |=                      \
+                       AR5K_4W_TX_DESC_CTL##_c##_##_flag;      \
+       }
+
+       _TX_FLAGS(0, CLRDMASK);
+       _TX_FLAGS(0, VEOL);
+       _TX_FLAGS(0, INTREQ);
+       _TX_FLAGS(0, RTSENA);
+       _TX_FLAGS(0, CTSENA);
+       _TX_FLAGS(1, NOACK);
+
+#undef _TX_FLAGS
+
+       /*
+        * RTS/CTS
+        */
+       if (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)) {
+               if ((flags & AR5K_TXDESC_RTSENA) &&
+                               (flags & AR5K_TXDESC_CTSENA))
+                       return -EINVAL;
+               tx_ctl->tx_control_2 |= rtscts_duration &
+                               AR5K_4W_TX_DESC_CTL2_RTS_DURATION;
+               tx_ctl->tx_control_3 |= AR5K_REG_SM(rtscts_rate,
+                               AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE);
+       }
+
+       return 0;
+}
+
+/*
+ * Proccess the tx status descriptor on 5210/5211
+ */
+static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *ah __unused,
+               struct ath5k_desc *desc, struct ath5k_tx_status *ts)
+{
+       struct ath5k_hw_2w_tx_ctl *tx_ctl;
+       struct ath5k_hw_tx_status *tx_status;
+
+       tx_ctl = &desc->ud.ds_tx5210.tx_ctl;
+       tx_status = &desc->ud.ds_tx5210.tx_stat;
+
+       /* No frame has been send or error */
+       if ((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0)
+               return -EINPROGRESS;
+
+       /*
+        * Get descriptor status
+        */
+       ts->ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0,
+               AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP);
+       ts->ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0,
+               AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT);
+       ts->ts_longretry = AR5K_REG_MS(tx_status->tx_status_0,
+               AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT);
+       /*TODO: ts->ts_virtcol + test*/
+       ts->ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1,
+               AR5K_DESC_TX_STATUS1_SEQ_NUM);
+       ts->ts_rssi = AR5K_REG_MS(tx_status->tx_status_1,
+               AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
+       ts->ts_antenna = 1;
+       ts->ts_status = 0;
+       ts->ts_rate[0] = AR5K_REG_MS(tx_ctl->tx_control_0,
+               AR5K_2W_TX_DESC_CTL0_XMIT_RATE);
+       ts->ts_retry[0] = ts->ts_longretry;
+       ts->ts_final_idx = 0;
+
+       if (!(tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK)) {
+               if (tx_status->tx_status_0 &
+                               AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
+                       ts->ts_status |= AR5K_TXERR_XRETRY;
+
+               if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN)
+                       ts->ts_status |= AR5K_TXERR_FIFO;
+
+               if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED)
+                       ts->ts_status |= AR5K_TXERR_FILT;
+       }
+
+       return 0;
+}
+
+/*
+ * Proccess a tx status descriptor on 5212
+ */
+static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *ah __unused,
+               struct ath5k_desc *desc, struct ath5k_tx_status *ts)
+{
+       struct ath5k_hw_4w_tx_ctl *tx_ctl;
+       struct ath5k_hw_tx_status *tx_status;
+
+       tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
+       tx_status = &desc->ud.ds_tx5212.tx_stat;
+
+       /* No frame has been send or error */
+       if (!(tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE))
+               return -EINPROGRESS;
+
+       /*
+        * Get descriptor status
+        */
+       ts->ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0,
+               AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP);
+       ts->ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0,
+               AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT);
+       ts->ts_longretry = AR5K_REG_MS(tx_status->tx_status_0,
+               AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT);
+       ts->ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1,
+               AR5K_DESC_TX_STATUS1_SEQ_NUM);
+       ts->ts_rssi = AR5K_REG_MS(tx_status->tx_status_1,
+               AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
+       ts->ts_antenna = (tx_status->tx_status_1 &
+               AR5K_DESC_TX_STATUS1_XMIT_ANTENNA) ? 2 : 1;
+       ts->ts_status = 0;
+
+       ts->ts_final_idx = AR5K_REG_MS(tx_status->tx_status_1,
+                       AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX);
+
+       ts->ts_retry[0] = ts->ts_longretry;
+       ts->ts_rate[0] = tx_ctl->tx_control_3 &
+               AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
+
+       /* TX error */
+       if (!(tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK)) {
+               if (tx_status->tx_status_0 &
+                               AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
+                       ts->ts_status |= AR5K_TXERR_XRETRY;
+
+               if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN)
+                       ts->ts_status |= AR5K_TXERR_FIFO;
+
+               if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED)
+                       ts->ts_status |= AR5K_TXERR_FILT;
+       }
+
+       return 0;
+}
+
+/*
+ * RX Descriptors
+ */
+
+/*
+ * Initialize an rx control descriptor
+ */
+static int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah __unused,
+                                 struct ath5k_desc *desc,
+                                 u32 size, unsigned int flags)
+{
+       struct ath5k_hw_rx_ctl *rx_ctl;
+
+       rx_ctl = &desc->ud.ds_rx.rx_ctl;
+
+       /*
+        * Clear the descriptor
+        * If we don't clean the status descriptor,
+        * while scanning we get too many results,
+        * most of them virtual, after some secs
+        * of scanning system hangs. M.F.
+       */
+       memset(&desc->ud.ds_rx, 0, sizeof(struct ath5k_hw_all_rx_desc));
+
+       /* Setup descriptor */
+       rx_ctl->rx_control_1 = size & AR5K_DESC_RX_CTL1_BUF_LEN;
+       if (rx_ctl->rx_control_1 != size)
+               return -EINVAL;
+
+       if (flags & AR5K_RXDESC_INTREQ)
+               rx_ctl->rx_control_1 |= AR5K_DESC_RX_CTL1_INTREQ;
+
+       if (desc->ds_link < ah->ah_sc->desc_daddr ||
+           desc->ds_link + sizeof(struct ath5k_desc) > ah->ah_sc->desc_daddr + ah->ah_sc->desc_len ||
+           size != 2400 ||
+           *(void **)bus_to_virt(desc->ds_data + 2408) != bus_to_virt(desc->ds_data)) {
+               DBG("ath5k! set rx desc %p for %d bytes at %p (%08x) link to %p (%08x)\n",
+                   desc, size, bus_to_virt(desc->ds_data), desc->ds_data,
+                   bus_to_virt(desc->ds_link), desc->ds_link);
+               asm("cli;hlt");
+       }
+
+       return 0;
+}
+
+/*
+ * Proccess the rx status descriptor on 5210/5211
+ */
+static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *ah __unused,
+               struct ath5k_desc *desc, struct ath5k_rx_status *rs)
+{
+       struct ath5k_hw_rx_status *rx_status;
+
+       rx_status = &desc->ud.ds_rx.u.rx_stat;
+
+       /* No frame received / not ready */
+       if (!(rx_status->rx_status_1 & AR5K_5210_RX_DESC_STATUS1_DONE))
+               return -EINPROGRESS;
+
+       /*
+        * Frame receive status
+        */
+       rs->rs_datalen = rx_status->rx_status_0 &
+               AR5K_5210_RX_DESC_STATUS0_DATA_LEN;
+       rs->rs_rssi = AR5K_REG_MS(rx_status->rx_status_0,
+               AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL);
+       rs->rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
+               AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE);
+       rs->rs_antenna = AR5K_REG_MS(rx_status->rx_status_0,
+               AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANTENNA);
+       rs->rs_more = !!(rx_status->rx_status_0 &
+               AR5K_5210_RX_DESC_STATUS0_MORE);
+       /* TODO: this timestamp is 13 bit, later on we assume 15 bit */
+       rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
+               AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
+       rs->rs_status = 0;
+       rs->rs_phyerr = 0;
+       rs->rs_keyix = AR5K_RXKEYIX_INVALID;
+
+       /*
+        * Receive/descriptor errors
+        */
+       if (!(rx_status->rx_status_1 &
+             AR5K_5210_RX_DESC_STATUS1_FRAME_RECEIVE_OK)) {
+               if (rx_status->rx_status_1 &
+                               AR5K_5210_RX_DESC_STATUS1_CRC_ERROR)
+                       rs->rs_status |= AR5K_RXERR_CRC;
+
+               if (rx_status->rx_status_1 &
+                               AR5K_5210_RX_DESC_STATUS1_FIFO_OVERRUN)
+                       rs->rs_status |= AR5K_RXERR_FIFO;
+
+               if (rx_status->rx_status_1 &
+                               AR5K_5210_RX_DESC_STATUS1_PHY_ERROR) {
+                       rs->rs_status |= AR5K_RXERR_PHY;
+                       rs->rs_phyerr |= AR5K_REG_MS(rx_status->rx_status_1,
+                               AR5K_5210_RX_DESC_STATUS1_PHY_ERROR);
+               }
+
+               if (rx_status->rx_status_1 &
+                               AR5K_5210_RX_DESC_STATUS1_DECRYPT_CRC_ERROR)
+                       rs->rs_status |= AR5K_RXERR_DECRYPT;
+       }
+
+       return 0;
+}
+
+/*
+ * Proccess the rx status descriptor on 5212
+ */
+static int ath5k_hw_proc_5212_rx_status(struct ath5k_hw *ah __unused,
+               struct ath5k_desc *desc, struct ath5k_rx_status *rs)
+{
+       struct ath5k_hw_rx_status *rx_status;
+       struct ath5k_hw_rx_error *rx_err;
+
+       rx_status = &desc->ud.ds_rx.u.rx_stat;
+
+       /* Overlay on error */
+       rx_err = &desc->ud.ds_rx.u.rx_err;
+
+       /* No frame received / not ready */
+       if (!(rx_status->rx_status_1 & AR5K_5212_RX_DESC_STATUS1_DONE))
+               return -EINPROGRESS;
+
+       /*
+        * Frame receive status
+        */
+       rs->rs_datalen = rx_status->rx_status_0 &
+               AR5K_5212_RX_DESC_STATUS0_DATA_LEN;
+       rs->rs_rssi = AR5K_REG_MS(rx_status->rx_status_0,
+               AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL);
+       rs->rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
+               AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE);
+       rs->rs_antenna = AR5K_REG_MS(rx_status->rx_status_0,
+               AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA);
+       rs->rs_more = !!(rx_status->rx_status_0 &
+               AR5K_5212_RX_DESC_STATUS0_MORE);
+       rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
+               AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
+       rs->rs_status = 0;
+       rs->rs_phyerr = 0;
+       rs->rs_keyix = AR5K_RXKEYIX_INVALID;
+
+       /*
+        * Receive/descriptor errors
+        */
+       if (!(rx_status->rx_status_1 &
+             AR5K_5212_RX_DESC_STATUS1_FRAME_RECEIVE_OK)) {
+               if (rx_status->rx_status_1 &
+                               AR5K_5212_RX_DESC_STATUS1_CRC_ERROR)
+                       rs->rs_status |= AR5K_RXERR_CRC;
+
+               if (rx_status->rx_status_1 &
+                               AR5K_5212_RX_DESC_STATUS1_PHY_ERROR) {
+                       rs->rs_status |= AR5K_RXERR_PHY;
+                       rs->rs_phyerr |= AR5K_REG_MS(rx_err->rx_error_1,
+                                          AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE);
+               }
+
+               if (rx_status->rx_status_1 &
+                               AR5K_5212_RX_DESC_STATUS1_DECRYPT_CRC_ERROR)
+                       rs->rs_status |= AR5K_RXERR_DECRYPT;
+
+               if (rx_status->rx_status_1 &
+                               AR5K_5212_RX_DESC_STATUS1_MIC_ERROR)
+                       rs->rs_status |= AR5K_RXERR_MIC;
+       }
+
+       return 0;
+}
+
+/*
+ * Init function pointers inside ath5k_hw struct
+ */
+int ath5k_hw_init_desc_functions(struct ath5k_hw *ah)
+{
+
+       if (ah->ah_version != AR5K_AR5210 &&
+           ah->ah_version != AR5K_AR5211 &&
+           ah->ah_version != AR5K_AR5212)
+               return -ENOTSUP;
+
+       if (ah->ah_version == AR5K_AR5212) {
+               ah->ah_setup_rx_desc = ath5k_hw_setup_rx_desc;
+               ah->ah_setup_tx_desc = ath5k_hw_setup_4word_tx_desc;
+               ah->ah_proc_tx_desc = ath5k_hw_proc_4word_tx_status;
+       } else {
+               ah->ah_setup_rx_desc = ath5k_hw_setup_rx_desc;
+               ah->ah_setup_tx_desc = ath5k_hw_setup_2word_tx_desc;
+               ah->ah_proc_tx_desc = ath5k_hw_proc_2word_tx_status;
+       }
+
+       if (ah->ah_version == AR5K_AR5212)
+               ah->ah_proc_rx_desc = ath5k_hw_proc_5212_rx_status;
+       else if (ah->ah_version <= AR5K_AR5211)
+               ah->ah_proc_rx_desc = ath5k_hw_proc_5210_rx_status;
+
+       return 0;
+}
+
diff --git a/src/drivers/net/ath5k/ath5k_dma.c b/src/drivers/net/ath5k/ath5k_dma.c
new file mode 100644 (file)
index 0000000..23c4cf9
--- /dev/null
@@ -0,0 +1,631 @@
+/*
+ * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
+ * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
+ *
+ * Lightly modified for gPXE, July 2009, by Joshua Oreman <oremanj@rwcr.net>.
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+FILE_LICENCE ( MIT );
+
+/*************************************\
+* DMA and interrupt masking functions *
+\*************************************/
+
+/*
+ * dma.c - DMA and interrupt masking functions
+ *
+ * Here we setup descriptor pointers (rxdp/txdp) start/stop dma engine and
+ * handle queue setup for 5210 chipset (rest are handled on qcu.c).
+ * Also we setup interrupt mask register (IMR) and read the various iterrupt
+ * status registers (ISR).
+ *
+ * TODO: Handle SISR on 5211+ and introduce a function to return the queue
+ * number that resulted the interrupt.
+ */
+
+#include <unistd.h>
+
+#include "ath5k.h"
+#include "reg.h"
+#include "base.h"
+
+/*********\
+* Receive *
+\*********/
+
+/**
+ * ath5k_hw_start_rx_dma - Start DMA receive
+ *
+ * @ah:        The &struct ath5k_hw
+ */
+void ath5k_hw_start_rx_dma(struct ath5k_hw *ah)
+{
+       ath5k_hw_reg_write(ah, AR5K_CR_RXE, AR5K_CR);
+       ath5k_hw_reg_read(ah, AR5K_CR);
+}
+
+/**
+ * ath5k_hw_stop_rx_dma - Stop DMA receive
+ *
+ * @ah:        The &struct ath5k_hw
+ */
+int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah)
+{
+       unsigned int i;
+
+       ath5k_hw_reg_write(ah, AR5K_CR_RXD, AR5K_CR);
+
+       /*
+        * It may take some time to disable the DMA receive unit
+        */
+       for (i = 1000; i > 0 &&
+                       (ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) != 0;
+                       i--)
+               udelay(10);
+
+       return i ? 0 : -EBUSY;
+}
+
+/**
+ * ath5k_hw_get_rxdp - Get RX Descriptor's address
+ *
+ * @ah: The &struct ath5k_hw
+ *
+ * XXX: Is RXDP read and clear ?
+ */
+u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah)
+{
+       return ath5k_hw_reg_read(ah, AR5K_RXDP);
+}
+
+/**
+ * ath5k_hw_set_rxdp - Set RX Descriptor's address
+ *
+ * @ah: The &struct ath5k_hw
+ * @phys_addr: RX descriptor address
+ *
+ * XXX: Should we check if rx is enabled before setting rxdp ?
+ */
+void ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr)
+{
+       ath5k_hw_reg_write(ah, phys_addr, AR5K_RXDP);
+}
+
+
+/**********\
+* Transmit *
+\**********/
+
+/**
+ * ath5k_hw_start_tx_dma - Start DMA transmit for a specific queue
+ *
+ * @ah: The &struct ath5k_hw
+ * @queue: The hw queue number
+ *
+ * Start DMA transmit for a specific queue and since 5210 doesn't have
+ * QCU/DCU, set up queue parameters for 5210 here based on queue type (one
+ * queue for normal data and one queue for beacons). For queue setup
+ * on newer chips check out qcu.c. Returns -EINVAL if queue number is out
+ * of range or if queue is already disabled.
+ *
+ * NOTE: Must be called after setting up tx control descriptor for that
+ * queue (see below).
+ */
+int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue)
+{
+       u32 tx_queue;
+
+       /* Return if queue is declared inactive */
+       if (ah->ah_txq.tqi_type == AR5K_TX_QUEUE_INACTIVE)
+               return -EIO;
+
+       if (ah->ah_version == AR5K_AR5210) {
+               tx_queue = ath5k_hw_reg_read(ah, AR5K_CR);
+
+               /* Assume always a data queue */
+               tx_queue |= AR5K_CR_TXE0 & ~AR5K_CR_TXD0;
+
+               /* Start queue */
+               ath5k_hw_reg_write(ah, tx_queue, AR5K_CR);
+               ath5k_hw_reg_read(ah, AR5K_CR);
+       } else {
+               /* Return if queue is disabled */
+               if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXD, queue))
+                       return -EIO;
+
+               /* Start queue */
+               AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXE, queue);
+       }
+
+       return 0;
+}
+
+/**
+ * ath5k_hw_stop_tx_dma - Stop DMA transmit on a specific queue
+ *
+ * @ah: The &struct ath5k_hw
+ * @queue: The hw queue number
+ *
+ * Stop DMA transmit on a specific hw queue and drain queue so we don't
+ * have any pending frames. Returns -EBUSY if we still have pending frames,
+ * -EINVAL if queue number is out of range.
+ *
+ */
+int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
+{
+       unsigned int i = 40;
+       u32 tx_queue, pending;
+
+       /* Return if queue is declared inactive */
+       if (ah->ah_txq.tqi_type == AR5K_TX_QUEUE_INACTIVE)
+               return -EIO;
+
+       if (ah->ah_version == AR5K_AR5210) {
+               tx_queue = ath5k_hw_reg_read(ah, AR5K_CR);
+
+               /* Assume a data queue */
+               tx_queue |= AR5K_CR_TXD0 & ~AR5K_CR_TXE0;
+
+               /* Stop queue */
+               ath5k_hw_reg_write(ah, tx_queue, AR5K_CR);
+               ath5k_hw_reg_read(ah, AR5K_CR);
+       } else {
+               /*
+                * Schedule TX disable and wait until queue is empty
+                */
+               AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXD, queue);
+
+               /*Check for pending frames*/
+               do {
+                       pending = ath5k_hw_reg_read(ah,
+                               AR5K_QUEUE_STATUS(queue)) &
+                               AR5K_QCU_STS_FRMPENDCNT;
+                       udelay(100);
+               } while (--i && pending);
+
+               /* For 2413+ order PCU to drop packets using
+                * QUIET mechanism */
+               if (ah->ah_mac_version >= (AR5K_SREV_AR2414 >> 4) && pending) {
+                       /* Set periodicity and duration */
+                       ath5k_hw_reg_write(ah,
+                               AR5K_REG_SM(100, AR5K_QUIET_CTL2_QT_PER)|
+                               AR5K_REG_SM(10, AR5K_QUIET_CTL2_QT_DUR),
+                               AR5K_QUIET_CTL2);
+
+                       /* Enable quiet period for current TSF */
+                       ath5k_hw_reg_write(ah,
+                               AR5K_QUIET_CTL1_QT_EN |
+                               AR5K_REG_SM(ath5k_hw_reg_read(ah,
+                                               AR5K_TSF_L32_5211) >> 10,
+                                               AR5K_QUIET_CTL1_NEXT_QT_TSF),
+                               AR5K_QUIET_CTL1);
+
+                       /* Force channel idle high */
+                       AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211,
+                                       AR5K_DIAG_SW_CHANEL_IDLE_HIGH);
+
+                       /* Wait a while and disable mechanism */
+                       udelay(200);
+                       AR5K_REG_DISABLE_BITS(ah, AR5K_QUIET_CTL1,
+                                               AR5K_QUIET_CTL1_QT_EN);
+
+                       /* Re-check for pending frames */
+                       i = 40;
+                       do {
+                               pending = ath5k_hw_reg_read(ah,
+                                       AR5K_QUEUE_STATUS(queue)) &
+                                       AR5K_QCU_STS_FRMPENDCNT;
+                               udelay(100);
+                       } while (--i && pending);
+
+                       AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5211,
+                                       AR5K_DIAG_SW_CHANEL_IDLE_HIGH);
+               }
+
+               /* Clear register */
+               ath5k_hw_reg_write(ah, 0, AR5K_QCU_TXD);
+               if (pending)
+                       return -EBUSY;
+       }
+
+       /* TODO: Check for success on 5210 else return error */
+       return 0;
+}
+
+/**
+ * ath5k_hw_get_txdp - Get TX Descriptor's address for a specific queue
+ *
+ * @ah: The &struct ath5k_hw
+ * @queue: The hw queue number
+ *
+ * Get TX descriptor's address for a specific queue. For 5210 we ignore
+ * the queue number and use tx queue type since we only have 2 queues.
+ * We use TXDP0 for normal data queue and TXDP1 for beacon queue.
+ * For newer chips with QCU/DCU we just read the corresponding TXDP register.
+ *
+ * XXX: Is TXDP read and clear ?
+ */
+u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue)
+{
+       u16 tx_reg;
+
+       /*
+        * Get the transmit queue descriptor pointer from the selected queue
+        */
+       /*5210 doesn't have QCU*/
+       if (ah->ah_version == AR5K_AR5210) {
+               /* Assume a data queue */
+               tx_reg = AR5K_NOQCU_TXDP0;
+       } else {
+               tx_reg = AR5K_QUEUE_TXDP(queue);
+       }
+
+       return ath5k_hw_reg_read(ah, tx_reg);
+}
+
+/**
+ * ath5k_hw_set_txdp - Set TX Descriptor's address for a specific queue
+ *
+ * @ah: The &struct ath5k_hw
+ * @queue: The hw queue number
+ *
+ * Set TX descriptor's address for a specific queue. For 5210 we ignore
+ * the queue number and we use tx queue type since we only have 2 queues
+ * so as above we use TXDP0 for normal data queue and TXDP1 for beacon queue.
+ * For newer chips with QCU/DCU we just set the corresponding TXDP register.
+ * Returns -EINVAL if queue type is invalid for 5210 and -EIO if queue is still
+ * active.
+ */
+int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue, u32 phys_addr)
+{
+       u16 tx_reg;
+
+       /*
+        * Set the transmit queue descriptor pointer register by type
+        * on 5210
+        */
+       if (ah->ah_version == AR5K_AR5210) {
+               /* Assume a data queue */
+               tx_reg = AR5K_NOQCU_TXDP0;
+       } else {
+               /*
+                * Set the transmit queue descriptor pointer for
+                * the selected queue on QCU for 5211+
+                * (this won't work if the queue is still active)
+                */
+               if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue))
+                       return -EIO;
+
+               tx_reg = AR5K_QUEUE_TXDP(queue);
+       }
+
+       /* Set descriptor pointer */
+       ath5k_hw_reg_write(ah, phys_addr, tx_reg);
+
+       return 0;
+}
+
+/**
+ * ath5k_hw_update_tx_triglevel - Update tx trigger level
+ *
+ * @ah: The &struct ath5k_hw
+ * @increase: Flag to force increase of trigger level
+ *
+ * This function increases/decreases the tx trigger level for the tx fifo
+ * buffer (aka FIFO threshold) that is used to indicate when PCU flushes
+ * the buffer and transmits it's data. Lowering this results sending small
+ * frames more quickly but can lead to tx underruns, raising it a lot can
+ * result other problems (i think bmiss is related). Right now we start with
+ * the lowest possible (64Bytes) and if we get tx underrun we increase it using
+ * the increase flag. Returns -EIO if we have have reached maximum/minimum.
+ *
+ * XXX: Link this with tx DMA size ?
+ * XXX: Use it to save interrupts ?
+ * TODO: Needs testing, i think it's related to bmiss...
+ */
+int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, int increase)
+{
+       u32 trigger_level, imr;
+       int ret = -EIO;
+
+       /*
+        * Disable interrupts by setting the mask
+        */
+       imr = ath5k_hw_set_imr(ah, ah->ah_imr & ~AR5K_INT_GLOBAL);
+
+       trigger_level = AR5K_REG_MS(ath5k_hw_reg_read(ah, AR5K_TXCFG),
+                       AR5K_TXCFG_TXFULL);
+
+       if (!increase) {
+               if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES)
+                       goto done;
+       } else
+               trigger_level +=
+                       ((AR5K_TUNE_MAX_TX_FIFO_THRES - trigger_level) / 2);
+
+       /*
+        * Update trigger level on success
+        */
+       if (ah->ah_version == AR5K_AR5210)
+               ath5k_hw_reg_write(ah, trigger_level, AR5K_TRIG_LVL);
+       else
+               AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG,
+                               AR5K_TXCFG_TXFULL, trigger_level);
+
+       ret = 0;
+
+done:
+       /*
+        * Restore interrupt mask
+        */
+       ath5k_hw_set_imr(ah, imr);
+
+       return ret;
+}
+
+/*******************\
+* Interrupt masking *
+\*******************/
+
+/**
+ * ath5k_hw_is_intr_pending - Check if we have pending interrupts
+ *
+ * @ah: The &struct ath5k_hw
+ *
+ * Check if we have pending interrupts to process. Returns 1 if we
+ * have pending interrupts and 0 if we haven't.
+ */
+int ath5k_hw_is_intr_pending(struct ath5k_hw *ah)
+{
+       return ath5k_hw_reg_read(ah, AR5K_INTPEND) == 1 ? 1 : 0;
+}
+
+/**
+ * ath5k_hw_get_isr - Get interrupt status
+ *
+ * @ah: The @struct ath5k_hw
+ * @interrupt_mask: Driver's interrupt mask used to filter out
+ * interrupts in sw.
+ *
+ * This function is used inside our interrupt handler to determine the reason
+ * for the interrupt by reading Primary Interrupt Status Register. Returns an
+ * abstract interrupt status mask which is mostly ISR with some uncommon bits
+ * being mapped on some standard non hw-specific positions
+ * (check out &ath5k_int).
+ *
+ * NOTE: We use read-and-clear register, so after this function is called ISR
+ * is zeroed.
+ */
+int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask)
+{
+       u32 data;
+
+       /*
+        * Read interrupt status from the Interrupt Status register
+        * on 5210
+        */
+       if (ah->ah_version == AR5K_AR5210) {
+               data = ath5k_hw_reg_read(ah, AR5K_ISR);
+               if (data == AR5K_INT_NOCARD) {
+                       *interrupt_mask = data;
+                       return -ENODEV;
+               }
+       } else {
+               /*
+                * Read interrupt status from Interrupt
+                * Status Register shadow copy (Read And Clear)
+                *
+                * Note: PISR/SISR Not available on 5210
+                */
+               data = ath5k_hw_reg_read(ah, AR5K_RAC_PISR);
+               if (data == AR5K_INT_NOCARD) {
+                       *interrupt_mask = data;
+                       return -ENODEV;
+               }
+       }
+
+       /*
+        * Get abstract interrupt mask (driver-compatible)
+        */
+       *interrupt_mask = (data & AR5K_INT_COMMON) & ah->ah_imr;
+
+       if (ah->ah_version != AR5K_AR5210) {
+               u32 sisr2 = ath5k_hw_reg_read(ah, AR5K_RAC_SISR2);
+
+               /*HIU = Host Interface Unit (PCI etc)*/
+               if (data & (AR5K_ISR_HIUERR))
+                       *interrupt_mask |= AR5K_INT_FATAL;
+
+               /*Beacon Not Ready*/
+               if (data & (AR5K_ISR_BNR))
+                       *interrupt_mask |= AR5K_INT_BNR;
+
+               if (sisr2 & (AR5K_SISR2_SSERR | AR5K_SISR2_DPERR |
+                            AR5K_SISR2_MCABT))
+                       *interrupt_mask |= AR5K_INT_FATAL;
+
+               if (data & AR5K_ISR_TIM)
+                       *interrupt_mask |= AR5K_INT_TIM;
+
+               if (data & AR5K_ISR_BCNMISC) {
+                       if (sisr2 & AR5K_SISR2_TIM)
+                               *interrupt_mask |= AR5K_INT_TIM;
+                       if (sisr2 & AR5K_SISR2_DTIM)
+                               *interrupt_mask |= AR5K_INT_DTIM;
+                       if (sisr2 & AR5K_SISR2_DTIM_SYNC)
+                               *interrupt_mask |= AR5K_INT_DTIM_SYNC;
+                       if (sisr2 & AR5K_SISR2_BCN_TIMEOUT)
+                               *interrupt_mask |= AR5K_INT_BCN_TIMEOUT;
+                       if (sisr2 & AR5K_SISR2_CAB_TIMEOUT)
+                               *interrupt_mask |= AR5K_INT_CAB_TIMEOUT;
+               }
+
+               if (data & AR5K_ISR_RXDOPPLER)
+                       *interrupt_mask |= AR5K_INT_RX_DOPPLER;
+               if (data & AR5K_ISR_QCBRORN) {
+                       *interrupt_mask |= AR5K_INT_QCBRORN;
+                       ah->ah_txq_isr |= AR5K_REG_MS(
+                                       ath5k_hw_reg_read(ah, AR5K_RAC_SISR3),
+                                       AR5K_SISR3_QCBRORN);
+               }
+               if (data & AR5K_ISR_QCBRURN) {
+                       *interrupt_mask |= AR5K_INT_QCBRURN;
+                       ah->ah_txq_isr |= AR5K_REG_MS(
+                                       ath5k_hw_reg_read(ah, AR5K_RAC_SISR3),
+                                       AR5K_SISR3_QCBRURN);
+               }
+               if (data & AR5K_ISR_QTRIG) {
+                       *interrupt_mask |= AR5K_INT_QTRIG;
+                       ah->ah_txq_isr |= AR5K_REG_MS(
+                                       ath5k_hw_reg_read(ah, AR5K_RAC_SISR4),
+                                       AR5K_SISR4_QTRIG);
+               }
+
+               if (data & AR5K_ISR_TXOK)
+                       ah->ah_txq_isr |= AR5K_REG_MS(
+                                       ath5k_hw_reg_read(ah, AR5K_RAC_SISR0),
+                                       AR5K_SISR0_QCU_TXOK);
+
+               if (data & AR5K_ISR_TXDESC)
+                       ah->ah_txq_isr |= AR5K_REG_MS(
+                                       ath5k_hw_reg_read(ah, AR5K_RAC_SISR0),
+                                       AR5K_SISR0_QCU_TXDESC);
+
+               if (data & AR5K_ISR_TXERR)
+                       ah->ah_txq_isr |= AR5K_REG_MS(
+                                       ath5k_hw_reg_read(ah, AR5K_RAC_SISR1),
+                                       AR5K_SISR1_QCU_TXERR);
+
+               if (data & AR5K_ISR_TXEOL)
+                       ah->ah_txq_isr |= AR5K_REG_MS(
+                                       ath5k_hw_reg_read(ah, AR5K_RAC_SISR1),
+                                       AR5K_SISR1_QCU_TXEOL);
+
+               if (data & AR5K_ISR_TXURN)
+                       ah->ah_txq_isr |= AR5K_REG_MS(
+                                       ath5k_hw_reg_read(ah, AR5K_RAC_SISR2),
+                                       AR5K_SISR2_QCU_TXURN);
+       } else {
+               if (data & (AR5K_ISR_SSERR | AR5K_ISR_MCABT |
+                           AR5K_ISR_HIUERR | AR5K_ISR_DPERR))
+                       *interrupt_mask |= AR5K_INT_FATAL;
+
+               /*
+                * XXX: BMISS interrupts may occur after association.
+                * I found this on 5210 code but it needs testing. If this is
+                * true we should disable them before assoc and re-enable them
+                * after a successful assoc + some jiffies.
+                       interrupt_mask &= ~AR5K_INT_BMISS;
+                */
+       }
+
+       return 0;
+}
+
+/**
+ * ath5k_hw_set_imr - Set interrupt mask
+ *
+ * @ah: The &struct ath5k_hw
+ * @new_mask: The new interrupt mask to be set
+ *
+ * Set the interrupt mask in hw to save interrupts. We do that by mapping
+ * ath5k_int bits to hw-specific bits to remove abstraction and writing
+ * Interrupt Mask Register.
+ */
+enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask)
+{
+       enum ath5k_int old_mask, int_mask;
+
+       old_mask = ah->ah_imr;
+
+       /*
+        * Disable card interrupts to prevent any race conditions
+        * (they will be re-enabled afterwards if AR5K_INT GLOBAL
+        * is set again on the new mask).
+        */
+       if (old_mask & AR5K_INT_GLOBAL) {
+               ath5k_hw_reg_write(ah, AR5K_IER_DISABLE, AR5K_IER);
+               ath5k_hw_reg_read(ah, AR5K_IER);
+       }
+
+       /*
+        * Add additional, chipset-dependent interrupt mask flags
+        * and write them to the IMR (interrupt mask register).
+        */
+       int_mask = new_mask & AR5K_INT_COMMON;
+
+       if (ah->ah_version != AR5K_AR5210) {
+               /* Preserve per queue TXURN interrupt mask */
+               u32 simr2 = ath5k_hw_reg_read(ah, AR5K_SIMR2)
+                               & AR5K_SIMR2_QCU_TXURN;
+
+               if (new_mask & AR5K_INT_FATAL) {
+                       int_mask |= AR5K_IMR_HIUERR;
+                       simr2 |= (AR5K_SIMR2_MCABT | AR5K_SIMR2_SSERR
+                               | AR5K_SIMR2_DPERR);
+               }
+
+               /*Beacon Not Ready*/
+               if (new_mask & AR5K_INT_BNR)
+                       int_mask |= AR5K_INT_BNR;
+
+               if (new_mask & AR5K_INT_TIM)
+                       int_mask |= AR5K_IMR_TIM;
+
+               if (new_mask & AR5K_INT_TIM)
+                       simr2 |= AR5K_SISR2_TIM;
+               if (new_mask & AR5K_INT_DTIM)
+                       simr2 |= AR5K_SISR2_DTIM;
+               if (new_mask & AR5K_INT_DTIM_SYNC)
+                       simr2 |= AR5K_SISR2_DTIM_SYNC;
+               if (new_mask & AR5K_INT_BCN_TIMEOUT)
+                       simr2 |= AR5K_SISR2_BCN_TIMEOUT;
+               if (new_mask & AR5K_INT_CAB_TIMEOUT)
+                       simr2 |= AR5K_SISR2_CAB_TIMEOUT;
+
+               if (new_mask & AR5K_INT_RX_DOPPLER)
+                       int_mask |= AR5K_IMR_RXDOPPLER;
+
+               /* Note: Per queue interrupt masks
+                * are set via reset_tx_queue (qcu.c) */
+               ath5k_hw_reg_write(ah, int_mask, AR5K_PIMR);
+               ath5k_hw_reg_write(ah, simr2, AR5K_SIMR2);
+
+       } else {
+               if (new_mask & AR5K_INT_FATAL)
+                       int_mask |= (AR5K_IMR_SSERR | AR5K_IMR_MCABT
+                               | AR5K_IMR_HIUERR | AR5K_IMR_DPERR);
+
+               ath5k_hw_reg_write(ah, int_mask, AR5K_IMR);
+       }
+
+       /* If RXNOFRM interrupt is masked disable it
+        * by setting AR5K_RXNOFRM to zero */
+       if (!(new_mask & AR5K_INT_RXNOFRM))
+               ath5k_hw_reg_write(ah, 0, AR5K_RXNOFRM);
+
+       /* Store new interrupt mask */
+       ah->ah_imr = new_mask;
+
+       /* ..re-enable interrupts if AR5K_INT_GLOBAL is set */
+       if (new_mask & AR5K_INT_GLOBAL) {
+               ath5k_hw_reg_write(ah, ah->ah_ier, AR5K_IER);
+               ath5k_hw_reg_read(ah, AR5K_IER);
+       }
+
+       return old_mask;
+}
+
diff --git a/src/drivers/net/ath5k/ath5k_eeprom.c b/src/drivers/net/ath5k/ath5k_eeprom.c
new file mode 100644 (file)
index 0000000..592714d
--- /dev/null
@@ -0,0 +1,1749 @@
+/*
+ * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
+ * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
+ * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
+ *
+ * Lightly modified for gPXE, July 2009, by Joshua Oreman <oremanj@rwcr.net>.
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+FILE_LICENCE ( MIT );
+
+/*************************************\
+* EEPROM access functions and helpers *
+\*************************************/
+
+#include <unistd.h>
+#include <stdlib.h>
+
+#include "ath5k.h"
+#include "reg.h"
+#include "base.h"
+
+/*
+ * Read from eeprom
+ */
+static int ath5k_hw_eeprom_read(struct ath5k_hw *ah, u32 offset, u16 *data)
+{
+       u32 status, timeout;
+
+       /*
+        * Initialize EEPROM access
+        */
+       if (ah->ah_version == AR5K_AR5210) {
+               AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE);
+               (void)ath5k_hw_reg_read(ah, AR5K_EEPROM_BASE + (4 * offset));
+       } else {
+               ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE);
+               AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
+                               AR5K_EEPROM_CMD_READ);
+       }
+
+       for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) {
+               status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS);
+               if (status & AR5K_EEPROM_STAT_RDDONE) {
+                       if (status & AR5K_EEPROM_STAT_RDERR)
+                               return -EIO;
+                       *data = (u16)(ath5k_hw_reg_read(ah, AR5K_EEPROM_DATA) &
+                                       0xffff);
+                       return 0;
+               }
+               udelay(15);
+       }
+
+       return -ETIMEDOUT;
+}
+
+/*
+ * Translate binary channel representation in EEPROM to frequency
+ */
+static u16 ath5k_eeprom_bin2freq(struct ath5k_eeprom_info *ee, u16 bin,
+                                 unsigned int mode)
+{
+       u16 val;
+
+       if (bin == AR5K_EEPROM_CHANNEL_DIS)
+               return bin;
+
+       if (mode == AR5K_EEPROM_MODE_11A) {
+               if (ee->ee_version > AR5K_EEPROM_VERSION_3_2)
+                       val = (5 * bin) + 4800;
+               else
+                       val = bin > 62 ? (10 * 62) + (5 * (bin - 62)) + 5100 :
+                               (bin * 10) + 5100;
+       } else {
+               if (ee->ee_version > AR5K_EEPROM_VERSION_3_2)
+                       val = bin + 2300;
+               else
+                       val = bin + 2400;
+       }
+
+       return val;
+}
+
+/*
+ * Initialize eeprom & capabilities structs
+ */
+static int
+ath5k_eeprom_init_header(struct ath5k_hw *ah)
+{
+       struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
+       int ret;
+       u16 val;
+
+       /*
+        * Read values from EEPROM and store them in the capability structure
+        */
+       AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MAGIC, ee_magic);
+       AR5K_EEPROM_READ_HDR(AR5K_EEPROM_PROTECT, ee_protect);
+       AR5K_EEPROM_READ_HDR(AR5K_EEPROM_REG_DOMAIN, ee_regdomain);
+       AR5K_EEPROM_READ_HDR(AR5K_EEPROM_VERSION, ee_version);
+       AR5K_EEPROM_READ_HDR(AR5K_EEPROM_HDR, ee_header);
+
+       /* Return if we have an old EEPROM */
+       if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_0)
+               return 0;
+
+       AR5K_EEPROM_READ_HDR(AR5K_EEPROM_ANT_GAIN(ah->ah_ee_version),
+           ee_ant_gain);
+
+       if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
+               AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC0, ee_misc0);
+               AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC1, ee_misc1);
+
+               /* XXX: Don't know which versions include these two */
+               AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC2, ee_misc2);
+
+               if (ee->ee_version >= AR5K_EEPROM_VERSION_4_3)
+                       AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC3, ee_misc3);
+
+               if (ee->ee_version >= AR5K_EEPROM_VERSION_5_0) {
+                       AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC4, ee_misc4);
+                       AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC5, ee_misc5);
+                       AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC6, ee_misc6);
+               }
+       }
+
+       if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_3) {
+               AR5K_EEPROM_READ(AR5K_EEPROM_OBDB0_2GHZ, val);
+               ee->ee_ob[AR5K_EEPROM_MODE_11B][0] = val & 0x7;
+               ee->ee_db[AR5K_EEPROM_MODE_11B][0] = (val >> 3) & 0x7;
+
+               AR5K_EEPROM_READ(AR5K_EEPROM_OBDB1_2GHZ, val);
+               ee->ee_ob[AR5K_EEPROM_MODE_11G][0] = val & 0x7;
+               ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7;
+       }
+
+       return 0;
+}
+
+
+/*
+ * Read antenna infos from eeprom
+ */
+static int ath5k_eeprom_read_ants(struct ath5k_hw *ah, u32 *offset,
+               unsigned int mode)
+{
+       struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
+       u32 o = *offset;
+       u16 val;
+       int ret, i = 0;
+
+       AR5K_EEPROM_READ(o++, val);
+       ee->ee_switch_settling[mode]    = (val >> 8) & 0x7f;
+       ee->ee_atn_tx_rx[mode]          = (val >> 2) & 0x3f;
+       ee->ee_ant_control[mode][i]     = (val << 4) & 0x3f;
+
+       AR5K_EEPROM_READ(o++, val);
+       ee->ee_ant_control[mode][i++]   |= (val >> 12) & 0xf;
+       ee->ee_ant_control[mode][i++]   = (val >> 6) & 0x3f;
+       ee->ee_ant_control[mode][i++]   = val & 0x3f;
+
+       AR5K_EEPROM_READ(o++, val);
+       ee->ee_ant_control[mode][i++]   = (val >> 10) & 0x3f;
+       ee->ee_ant_control[mode][i++]   = (val >> 4) & 0x3f;
+       ee->ee_ant_control[mode][i]     = (val << 2) & 0x3f;
+
+       AR5K_EEPROM_READ(o++, val);
+       ee->ee_ant_control[mode][i++]   |= (val >> 14) & 0x3;
+       ee->ee_ant_control[mode][i++]   = (val >> 8) & 0x3f;
+       ee->ee_ant_control[mode][i++]   = (val >> 2) & 0x3f;
+       ee->ee_ant_control[mode][i]     = (val << 4) & 0x3f;
+
+       AR5K_EEPROM_READ(o++, val);
+       ee->ee_ant_control[mode][i++]   |= (val >> 12) & 0xf;
+       ee->ee_ant_control[mode][i++]   = (val >> 6) & 0x3f;
+       ee->ee_ant_control[mode][i++]   = val & 0x3f;
+
+       /* Get antenna modes */
+       ah->ah_antenna[mode][0] =
+           (ee->ee_ant_control[mode][0] << 4);
+       ah->ah_antenna[mode][AR5K_ANT_FIXED_A] =
+            ee->ee_ant_control[mode][1]        |
+           (ee->ee_ant_control[mode][2] << 6)  |
+           (ee->ee_ant_control[mode][3] << 12) |
+           (ee->ee_ant_control[mode][4] << 18) |
+           (ee->ee_ant_control[mode][5] << 24);
+       ah->ah_antenna[mode][AR5K_ANT_FIXED_B] =
+            ee->ee_ant_control[mode][6]        |
+           (ee->ee_ant_control[mode][7] << 6)  |
+           (ee->ee_ant_control[mode][8] << 12) |
+           (ee->ee_ant_control[mode][9] << 18) |
+           (ee->ee_ant_control[mode][10] << 24);
+
+       /* return new offset */
+       *offset = o;
+
+       return 0;
+}
+
+/*
+ * Read supported modes and some mode-specific calibration data
+ * from eeprom
+ */
+static int ath5k_eeprom_read_modes(struct ath5k_hw *ah, u32 *offset,
+               unsigned int mode)
+{
+       struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
+       u32 o = *offset;
+       u16 val;
+       int ret;
+
+       ee->ee_n_piers[mode] = 0;
+       AR5K_EEPROM_READ(o++, val);
+       ee->ee_adc_desired_size[mode]   = (s8)((val >> 8) & 0xff);
+       switch(mode) {
+       case AR5K_EEPROM_MODE_11A:
+               ee->ee_ob[mode][3]      = (val >> 5) & 0x7;
+               ee->ee_db[mode][3]      = (val >> 2) & 0x7;
+               ee->ee_ob[mode][2]      = (val << 1) & 0x7;
+
+               AR5K_EEPROM_READ(o++, val);
+               ee->ee_ob[mode][2]      |= (val >> 15) & 0x1;
+               ee->ee_db[mode][2]      = (val >> 12) & 0x7;
+               ee->ee_ob[mode][1]      = (val >> 9) & 0x7;
+               ee->ee_db[mode][1]      = (val >> 6) & 0x7;
+               ee->ee_ob[mode][0]      = (val >> 3) & 0x7;
+               ee->ee_db[mode][0]      = val & 0x7;
+               break;
+       case AR5K_EEPROM_MODE_11G:
+       case AR5K_EEPROM_MODE_11B:
+               ee->ee_ob[mode][1]      = (val >> 4) & 0x7;
+               ee->ee_db[mode][1]      = val & 0x7;
+               break;
+       }
+
+       AR5K_EEPROM_READ(o++, val);
+       ee->ee_tx_end2xlna_enable[mode] = (val >> 8) & 0xff;
+       ee->ee_thr_62[mode]             = val & 0xff;
+
+       if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
+               ee->ee_thr_62[mode] = mode == AR5K_EEPROM_MODE_11A ? 15 : 28;
+
+       AR5K_EEPROM_READ(o++, val);
+       ee->ee_tx_end2xpa_disable[mode] = (val >> 8) & 0xff;
+       ee->ee_tx_frm2xpa_enable[mode]  = val & 0xff;
+
+       AR5K_EEPROM_READ(o++, val);
+       ee->ee_pga_desired_size[mode]   = (val >> 8) & 0xff;
+
+       if ((val & 0xff) & 0x80)
+               ee->ee_noise_floor_thr[mode] = -((((val & 0xff) ^ 0xff)) + 1);
+       else
+               ee->ee_noise_floor_thr[mode] = val & 0xff;
+
+       if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
+               ee->ee_noise_floor_thr[mode] =
+                   mode == AR5K_EEPROM_MODE_11A ? -54 : -1;
+
+       AR5K_EEPROM_READ(o++, val);
+       ee->ee_xlna_gain[mode]          = (val >> 5) & 0xff;
+       ee->ee_x_gain[mode]             = (val >> 1) & 0xf;
+       ee->ee_xpd[mode]                = val & 0x1;
+
+       if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0)
+               ee->ee_fixed_bias[mode] = (val >> 13) & 0x1;
+
+       if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_3_3) {
+               AR5K_EEPROM_READ(o++, val);
+               ee->ee_false_detect[mode] = (val >> 6) & 0x7f;
+
+               if (mode == AR5K_EEPROM_MODE_11A)
+                       ee->ee_xr_power[mode] = val & 0x3f;
+               else {
+                       ee->ee_ob[mode][0] = val & 0x7;
+                       ee->ee_db[mode][0] = (val >> 3) & 0x7;
+               }
+       }
+
+       if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_4) {
+               ee->ee_i_gain[mode] = AR5K_EEPROM_I_GAIN;
+               ee->ee_cck_ofdm_power_delta = AR5K_EEPROM_CCK_OFDM_DELTA;
+       } else {
+               ee->ee_i_gain[mode] = (val >> 13) & 0x7;
+
+               AR5K_EEPROM_READ(o++, val);
+               ee->ee_i_gain[mode] |= (val << 3) & 0x38;
+
+               if (mode == AR5K_EEPROM_MODE_11G) {
+                       ee->ee_cck_ofdm_power_delta = (val >> 3) & 0xff;
+                       if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_6)
+                               ee->ee_scaled_cck_delta = (val >> 11) & 0x1f;
+               }
+       }
+
+       if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 &&
+                       mode == AR5K_EEPROM_MODE_11A) {
+               ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
+               ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
+       }
+
+       if (ah->ah_ee_version < AR5K_EEPROM_VERSION_4_0)
+               goto done;
+
+       /* Note: >= v5 have bg freq piers on another location
+        * so these freq piers are ignored for >= v5 (should be 0xff
+        * anyway) */
+       switch(mode) {
+       case AR5K_EEPROM_MODE_11A:
+               if (ah->ah_ee_version < AR5K_EEPROM_VERSION_4_1)
+                       break;
+
+               AR5K_EEPROM_READ(o++, val);
+               ee->ee_margin_tx_rx[mode] = val & 0x3f;
+               break;
+       case AR5K_EEPROM_MODE_11B:
+               AR5K_EEPROM_READ(o++, val);
+
+               ee->ee_pwr_cal_b[0].freq =
+                       ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
+               if (ee->ee_pwr_cal_b[0].freq != AR5K_EEPROM_CHANNEL_DIS)
+                       ee->ee_n_piers[mode]++;
+
+               ee->ee_pwr_cal_b[1].freq =
+                       ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
+               if (ee->ee_pwr_cal_b[1].freq != AR5K_EEPROM_CHANNEL_DIS)
+                       ee->ee_n_piers[mode]++;
+
+               AR5K_EEPROM_READ(o++, val);
+               ee->ee_pwr_cal_b[2].freq =
+                       ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
+               if (ee->ee_pwr_cal_b[2].freq != AR5K_EEPROM_CHANNEL_DIS)
+                       ee->ee_n_piers[mode]++;
+
+               if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
+                       ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
+               break;
+       case AR5K_EEPROM_MODE_11G:
+               AR5K_EEPROM_READ(o++, val);
+
+               ee->ee_pwr_cal_g[0].freq =
+                       ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
+               if (ee->ee_pwr_cal_g[0].freq != AR5K_EEPROM_CHANNEL_DIS)
+                       ee->ee_n_piers[mode]++;
+
+               ee->ee_pwr_cal_g[1].freq =
+                       ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
+               if (ee->ee_pwr_cal_g[1].freq != AR5K_EEPROM_CHANNEL_DIS)
+                       ee->ee_n_piers[mode]++;
+
+               AR5K_EEPROM_READ(o++, val);
+               ee->ee_turbo_max_power[mode] = val & 0x7f;
+               ee->ee_xr_power[mode] = (val >> 7) & 0x3f;
+
+               AR5K_EEPROM_READ(o++, val);
+               ee->ee_pwr_cal_g[2].freq =
+                       ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
+               if (ee->ee_pwr_cal_g[2].freq != AR5K_EEPROM_CHANNEL_DIS)
+                       ee->ee_n_piers[mode]++;
+
+               if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
+                       ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
+
+               AR5K_EEPROM_READ(o++, val);
+               ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
+               ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
+
+               if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_2) {
+                       AR5K_EEPROM_READ(o++, val);
+                       ee->ee_cck_ofdm_gain_delta = val & 0xff;
+               }
+               break;
+       }
+
+done:
+       /* return new offset */
+       *offset = o;
+
+       return 0;
+}
+
+/*
+ * Read turbo mode information on newer EEPROM versions
+ */
+static int
+ath5k_eeprom_read_turbo_modes(struct ath5k_hw *ah,
+                             u32 *offset, unsigned int mode)
+{
+       struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
+       u32 o = *offset;
+       u16 val;
+       int ret;
+
+       if (ee->ee_version < AR5K_EEPROM_VERSION_5_0)
+               return 0;
+
+       switch (mode){
+       case AR5K_EEPROM_MODE_11A:
+               ee->ee_switch_settling_turbo[mode] = (val >> 6) & 0x7f;
+
+               ee->ee_atn_tx_rx_turbo[mode] = (val >> 13) & 0x7;
+               AR5K_EEPROM_READ(o++, val);
+               ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x7) << 3;
+               ee->ee_margin_tx_rx_turbo[mode] = (val >> 3) & 0x3f;
+
+               ee->ee_adc_desired_size_turbo[mode] = (val >> 9) & 0x7f;
+               AR5K_EEPROM_READ(o++, val);
+               ee->ee_adc_desired_size_turbo[mode] |= (val & 0x1) << 7;
+               ee->ee_pga_desired_size_turbo[mode] = (val >> 1) & 0xff;
+
+               if (AR5K_EEPROM_EEMAP(ee->ee_misc0) >=2)
+                       ee->ee_pd_gain_overlap = (val >> 9) & 0xf;
+               break;
+       case AR5K_EEPROM_MODE_11G:
+               ee->ee_switch_settling_turbo[mode] = (val >> 8) & 0x7f;
+
+               ee->ee_atn_tx_rx_turbo[mode] = (val >> 15) & 0x7;
+               AR5K_EEPROM_READ(o++, val);
+               ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x1f) << 1;
+               ee->ee_margin_tx_rx_turbo[mode] = (val >> 5) & 0x3f;
+
+               ee->ee_adc_desired_size_turbo[mode] = (val >> 11) & 0x7f;
+               AR5K_EEPROM_READ(o++, val);
+               ee->ee_adc_desired_size_turbo[mode] |= (val & 0x7) << 5;
+               ee->ee_pga_desired_size_turbo[mode] = (val >> 3) & 0xff;
+               break;
+       }
+
+       /* return new offset */
+       *offset = o;
+
+       return 0;
+}
+
+/* Read mode-specific data (except power calibration data) */
+static int
+ath5k_eeprom_init_modes(struct ath5k_hw *ah)
+{
+       struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
+       u32 mode_offset[3];
+       unsigned int mode;
+       u32 offset;
+       int ret;
+
+       /*
+        * Get values for all modes
+        */
+       mode_offset[AR5K_EEPROM_MODE_11A] = AR5K_EEPROM_MODES_11A(ah->ah_ee_version);
+       mode_offset[AR5K_EEPROM_MODE_11B] = AR5K_EEPROM_MODES_11B(ah->ah_ee_version);
+       mode_offset[AR5K_EEPROM_MODE_11G] = AR5K_EEPROM_MODES_11G(ah->ah_ee_version);
+
+       ee->ee_turbo_max_power[AR5K_EEPROM_MODE_11A] =
+               AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header);
+
+       for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G; mode++) {
+               offset = mode_offset[mode];
+
+               ret = ath5k_eeprom_read_ants(ah, &offset, mode);
+               if (ret)
+                       return ret;
+
+               ret = ath5k_eeprom_read_modes(ah, &offset, mode);
+               if (ret)
+                       return ret;
+
+               ret = ath5k_eeprom_read_turbo_modes(ah, &offset, mode);
+               if (ret)
+                       return ret;
+       }
+
+       /* override for older eeprom versions for better performance */
+       if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2) {
+               ee->ee_thr_62[AR5K_EEPROM_MODE_11A] = 15;
+               ee->ee_thr_62[AR5K_EEPROM_MODE_11B] = 28;
+               ee->ee_thr_62[AR5K_EEPROM_MODE_11G] = 28;
+       }
+
+       return 0;
+}
+
+/* Read the frequency piers for each mode (mostly used on newer eeproms with 0xff
+ * frequency mask) */
+static inline int
+ath5k_eeprom_read_freq_list(struct ath5k_hw *ah, int *offset, int max,
+                       struct ath5k_chan_pcal_info *pc, unsigned int mode)
+{
+       struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
+       int o = *offset;
+       int i = 0;
+       u8 freq1, freq2;
+       int ret;
+       u16 val;
+
+       ee->ee_n_piers[mode] = 0;
+       while(i < max) {
+               AR5K_EEPROM_READ(o++, val);
+
+               freq1 = val & 0xff;
+               if (!freq1)
+                       break;
+
+               pc[i++].freq = ath5k_eeprom_bin2freq(ee,
+                               freq1, mode);
+               ee->ee_n_piers[mode]++;
+
+               freq2 = (val >> 8) & 0xff;
+               if (!freq2)
+                       break;
+
+               pc[i++].freq = ath5k_eeprom_bin2freq(ee,
+                               freq2, mode);
+               ee->ee_n_piers[mode]++;
+       }
+
+       /* return new offset */
+       *offset = o;
+
+       return 0;
+}
+
+/* Read frequency piers for 802.11a */
+static int
+ath5k_eeprom_init_11a_pcal_freq(struct ath5k_hw *ah, int offset)
+{
+       struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
+       struct ath5k_chan_pcal_info *pcal = ee->ee_pwr_cal_a;
+       int i, ret;
+       u16 val;
+       u8 mask;
+
+       if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3) {
+               ath5k_eeprom_read_freq_list(ah, &offset,
+                       AR5K_EEPROM_N_5GHZ_CHAN, pcal,
+                       AR5K_EEPROM_MODE_11A);
+       } else {
+               mask = AR5K_EEPROM_FREQ_M(ah->ah_ee_version);
+
+               AR5K_EEPROM_READ(offset++, val);
+               pcal[0].freq  = (val >> 9) & mask;
+               pcal[1].freq  = (val >> 2) & mask;
+               pcal[2].freq  = (val << 5) & mask;
+
+               AR5K_EEPROM_READ(offset++, val);
+               pcal[2].freq |= (val >> 11) & 0x1f;
+               pcal[3].freq  = (val >> 4) & mask;
+               pcal[4].freq  = (val << 3) & mask;
+
+               AR5K_EEPROM_READ(offset++, val);
+               pcal[4].freq |= (val >> 13) & 0x7;
+               pcal[5].freq  = (val >> 6) & mask;
+               pcal[6].freq  = (val << 1) & mask;
+
+               AR5K_EEPROM_READ(offset++, val);
+               pcal[6].freq |= (val >> 15) & 0x1;
+               pcal[7].freq  = (val >> 8) & mask;
+               pcal[8].freq  = (val >> 1) & mask;
+               pcal[9].freq  = (val << 6) & mask;
+
+               AR5K_EEPROM_READ(offset++, val);
+               pcal[9].freq |= (val >> 10) & 0x3f;
+
+               /* Fixed number of piers */
+               ee->ee_n_piers[AR5K_EEPROM_MODE_11A] = 10;
+
+               for (i = 0; i < AR5K_EEPROM_N_5GHZ_CHAN; i++) {
+                       pcal[i].freq = ath5k_eeprom_bin2freq(ee,
+                               pcal[i].freq, AR5K_EEPROM_MODE_11A);
+               }
+       }
+
+       return 0;
+}
+
+/* Read frequency piers for 802.11bg on eeprom versions >= 5 and eemap >= 2 */
+static inline int
+ath5k_eeprom_init_11bg_2413(struct ath5k_hw *ah, unsigned int mode, int offset)
+{
+       struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
+       struct ath5k_chan_pcal_info *pcal;
+
+       switch(mode) {
+       case AR5K_EEPROM_MODE_11B:
+               pcal = ee->ee_pwr_cal_b;
+               break;
+       case AR5K_EEPROM_MODE_11G:
+               pcal = ee->ee_pwr_cal_g;
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       ath5k_eeprom_read_freq_list(ah, &offset,
+               AR5K_EEPROM_N_2GHZ_CHAN_2413, pcal,
+               mode);
+
+       return 0;
+}
+
+/*
+ * Read power calibration for RF5111 chips
+ *
+ * For RF5111 we have an XPD -eXternal Power Detector- curve
+ * for each calibrated channel. Each curve has 0,5dB Power steps
+ * on x axis and PCDAC steps (offsets) on y axis and looks like an
+ * exponential function. To recreate the curve we read 11 points
+ * here and interpolate later.
+ */
+
+/* Used to match PCDAC steps with power values on RF5111 chips
+ * (eeprom versions < 4). For RF5111 we have 11 pre-defined PCDAC
+ * steps that match with the power values we read from eeprom. On
+ * older eeprom versions (< 3.2) these steps are equaly spaced at
+ * 10% of the pcdac curve -until the curve reaches it's maximum-
+ * (11 steps from 0 to 100%) but on newer eeprom versions (>= 3.2)
+ * these 11 steps are spaced in a different way. This function returns
+ * the pcdac steps based on eeprom version and curve min/max so that we
+ * can have pcdac/pwr points.
+ */
+static inline void
+ath5k_get_pcdac_intercepts(struct ath5k_hw *ah, u8 min, u8 max, u8 *vp)
+{
+       static const u16 intercepts3[] =
+               { 0, 5, 10, 20, 30, 50, 70, 85, 90, 95, 100 };
+       static const u16 intercepts3_2[] =
+               { 0, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100 };
+       const u16 *ip;
+       unsigned i;
+
+       if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_3_2)
+               ip = intercepts3_2;
+       else
+               ip = intercepts3;
+
+       for (i = 0; i < ARRAY_SIZE(intercepts3); i++)
+               vp[i] = (ip[i] * max + (100 - ip[i]) * min) / 100;
+}
+
+/* Convert RF5111 specific data to generic raw data
+ * used by interpolation code */
+static int
+ath5k_eeprom_convert_pcal_info_5111(struct ath5k_hw *ah, int mode,
+                               struct ath5k_chan_pcal_info *chinfo)
+{
+       struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
+       struct ath5k_chan_pcal_info_rf5111 *pcinfo;
+       struct ath5k_pdgain_info *pd;
+       u8 pier, point, idx;
+       u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
+
+       /* Fill raw data for each calibration pier */
+       for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
+
+               pcinfo = &chinfo[pier].rf5111_info;
+
+               /* Allocate pd_curves for this cal pier */
+               chinfo[pier].pd_curves =
+                       calloc(AR5K_EEPROM_N_PD_CURVES,
+                              sizeof(struct ath5k_pdgain_info));
+
+               if (!chinfo[pier].pd_curves)
+                       return -ENOMEM;
+
+               /* Only one curve for RF5111
+                * find out which one and place
+                * in in pd_curves.
+                * Note: ee_x_gain is reversed here */
+               for (idx = 0; idx < AR5K_EEPROM_N_PD_CURVES; idx++) {
+
+                       if (!((ee->ee_x_gain[mode] >> idx) & 0x1)) {
+                               pdgain_idx[0] = idx;
+                               break;
+                       }
+               }
+
+               ee->ee_pd_gains[mode] = 1;
+
+               pd = &chinfo[pier].pd_curves[idx];
+
+               pd->pd_points = AR5K_EEPROM_N_PWR_POINTS_5111;
+
+               /* Allocate pd points for this curve */
+               pd->pd_step = calloc(AR5K_EEPROM_N_PWR_POINTS_5111, sizeof(u8));
+               if (!pd->pd_step)
+                       return -ENOMEM;
+
+               pd->pd_pwr = calloc(AR5K_EEPROM_N_PWR_POINTS_5111, sizeof(s16));
+               if (!pd->pd_pwr)
+                       return -ENOMEM;
+
+               /* Fill raw dataset
+                * (convert power to 0.25dB units
+                * for RF5112 combatibility) */
+               for (point = 0; point < pd->pd_points; point++) {
+
+                       /* Absolute values */
+                       pd->pd_pwr[point] = 2 * pcinfo->pwr[point];
+
+                       /* Already sorted */
+                       pd->pd_step[point] = pcinfo->pcdac[point];
+               }
+
+               /* Set min/max pwr */
+               chinfo[pier].min_pwr = pd->pd_pwr[0];
+               chinfo[pier].max_pwr = pd->pd_pwr[10];
+
+       }
+
+       return 0;
+}
+
+/* Parse EEPROM data */
+static int
+ath5k_eeprom_read_pcal_info_5111(struct ath5k_hw *ah, int mode)
+{
+       struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
+       struct ath5k_chan_pcal_info *pcal;
+       int offset, ret;
+       int i;
+       u16 val;
+
+       offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
+       switch(mode) {
+       case AR5K_EEPROM_MODE_11A:
+               if (!AR5K_EEPROM_HDR_11A(ee->ee_header))
+                       return 0;
+
+               ret = ath5k_eeprom_init_11a_pcal_freq(ah,
+                       offset + AR5K_EEPROM_GROUP1_OFFSET);
+               if (ret < 0)
+                       return ret;
+
+               offset += AR5K_EEPROM_GROUP2_OFFSET;
+               pcal = ee->ee_pwr_cal_a;
+               break;
+       case AR5K_EEPROM_MODE_11B:
+               if (!AR5K_EEPROM_HDR_11B(ee->ee_header) &&
+                   !AR5K_EEPROM_HDR_11G(ee->ee_header))
+                       return 0;
+
+               pcal = ee->ee_pwr_cal_b;
+               offset += AR5K_EEPROM_GROUP3_OFFSET;
+
+               /* fixed piers */
+               pcal[0].freq = 2412;
+               pcal[1].freq = 2447;
+               pcal[2].freq = 2484;
+               ee->ee_n_piers[mode] = 3;
+               break;
+       case AR5K_EEPROM_MODE_11G:
+               if (!AR5K_EEPROM_HDR_11G(ee->ee_header))
+                       return 0;
+
+               pcal = ee->ee_pwr_cal_g;
+               offset += AR5K_EEPROM_GROUP4_OFFSET;
+
+               /* fixed piers */
+               pcal[0].freq = 2312;
+               pcal[1].freq = 2412;
+               pcal[2].freq = 2484;
+               ee->ee_n_piers[mode] = 3;
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       for (i = 0; i < ee->ee_n_piers[mode]; i++) {
+               struct ath5k_chan_pcal_info_rf5111 *cdata =
+                       &pcal[i].rf5111_info;
+
+               AR5K_EEPROM_READ(offset++, val);
+               cdata->pcdac_max = ((val >> 10) & AR5K_EEPROM_PCDAC_M);
+               cdata->pcdac_min = ((val >> 4) & AR5K_EEPROM_PCDAC_M);
+               cdata->pwr[0] = ((val << 2) & AR5K_EEPROM_POWER_M);
+
+               AR5K_EEPROM_READ(offset++, val);
+               cdata->pwr[0] |= ((val >> 14) & 0x3);
+               cdata->pwr[1] = ((val >> 8) & AR5K_EEPROM_POWER_M);
+               cdata->pwr[2] = ((val >> 2) & AR5K_EEPROM_POWER_M);
+               cdata->pwr[3] = ((val << 4) & AR5K_EEPROM_POWER_M);
+
+               AR5K_EEPROM_READ(offset++, val);
+               cdata->pwr[3] |= ((val >> 12) & 0xf);
+               cdata->pwr[4] = ((val >> 6) & AR5K_EEPROM_POWER_M);
+               cdata->pwr[5] = (val  & AR5K_EEPROM_POWER_M);
+
+               AR5K_EEPROM_READ(offset++, val);
+               cdata->pwr[6] = ((val >> 10) & AR5K_EEPROM_POWER_M);
+               cdata->pwr[7] = ((val >> 4) & AR5K_EEPROM_POWER_M);
+               cdata->pwr[8] = ((val << 2) & AR5K_EEPROM_POWER_M);
+
+               AR5K_EEPROM_READ(offset++, val);
+               cdata->pwr[8] |= ((val >> 14) & 0x3);
+               cdata->pwr[9] = ((val >> 8) & AR5K_EEPROM_POWER_M);
+               cdata->pwr[10] = ((val >> 2) & AR5K_EEPROM_POWER_M);
+
+               ath5k_get_pcdac_intercepts(ah, cdata->pcdac_min,
+                       cdata->pcdac_max, cdata->pcdac);
+       }
+
+       return ath5k_eeprom_convert_pcal_info_5111(ah, mode, pcal);
+}
+
+
+/*
+ * Read power calibration for RF5112 chips
+ *
+ * For RF5112 we have 4 XPD -eXternal Power Detector- curves
+ * for each calibrated channel on 0, -6, -12 and -18dbm but we only
+ * use the higher (3) and the lower (0) curves. Each curve has 0.5dB
+ * power steps on x axis and PCDAC steps on y axis and looks like a
+ * linear function. To recreate the curve and pass the power values
+ * on hw, we read 4 points for xpd 0 (lower gain -> max power)
+ * and 3 points for xpd 3 (higher gain -> lower power) here and
+ * interpolate later.
+ *
+ * Note: Many vendors just use xpd 0 so xpd 3 is zeroed.
+ */
+
+/* Convert RF5112 specific data to generic raw data
+ * used by interpolation code */
+static int
+ath5k_eeprom_convert_pcal_info_5112(struct ath5k_hw *ah, int mode,
+                               struct ath5k_chan_pcal_info *chinfo)
+{
+       struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
+       struct ath5k_chan_pcal_info_rf5112 *pcinfo;
+       u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
+       unsigned int pier, pdg, point;
+
+       /* Fill raw data for each calibration pier */
+       for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
+
+               pcinfo = &chinfo[pier].rf5112_info;
+
+               /* Allocate pd_curves for this cal pier */
+               chinfo[pier].pd_curves =
+                               calloc(AR5K_EEPROM_N_PD_CURVES,
+                                      sizeof(struct ath5k_pdgain_info));
+
+               if (!chinfo[pier].pd_curves)
+                       return -ENOMEM;
+
+               /* Fill pd_curves */
+               for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) {
+
+                       u8 idx = pdgain_idx[pdg];
+                       struct ath5k_pdgain_info *pd =
+                                       &chinfo[pier].pd_curves[idx];
+
+                       /* Lowest gain curve (max power) */
+                       if (pdg == 0) {
+                               /* One more point for better accuracy */
+                               pd->pd_points = AR5K_EEPROM_N_XPD0_POINTS;
+
+                               /* Allocate pd points for this curve */
+                               pd->pd_step = calloc(pd->pd_points, sizeof(u8));
+
+                               if (!pd->pd_step)
+                                       return -ENOMEM;
+
+                               pd->pd_pwr = calloc(pd->pd_points, sizeof(s16));
+
+                               if (!pd->pd_pwr)
+                                       return -ENOMEM;
+
+
+                               /* Fill raw dataset
+                                * (all power levels are in 0.25dB units) */
+                               pd->pd_step[0] = pcinfo->pcdac_x0[0];
+                               pd->pd_pwr[0] = pcinfo->pwr_x0[0];
+
+                               for (point = 1; point < pd->pd_points;
+                               point++) {
+                                       /* Absolute values */
+                                       pd->pd_pwr[point] =
+                                               pcinfo->pwr_x0[point];
+
+                                       /* Deltas */
+                                       pd->pd_step[point] =
+                                               pd->pd_step[point - 1] +
+                                               pcinfo->pcdac_x0[point];
+                               }
+
+                               /* Set min power for this frequency */
+                               chinfo[pier].min_pwr = pd->pd_pwr[0];
+
+                       /* Highest gain curve (min power) */
+                       } else if (pdg == 1) {
+
+                               pd->pd_points = AR5K_EEPROM_N_XPD3_POINTS;
+
+                               /* Allocate pd points for this curve */
+                               pd->pd_step = calloc(pd->pd_points, sizeof(u8));
+
+                               if (!pd->pd_step)
+                                       return -ENOMEM;
+
+                               pd->pd_pwr = calloc(pd->pd_points, sizeof(s16));
+
+                               if (!pd->pd_pwr)
+                                       return -ENOMEM;
+
+                               /* Fill raw dataset
+                                * (all power levels are in 0.25dB units) */
+                               for (point = 0; point < pd->pd_points;
+                               point++) {
+                                       /* Absolute values */
+                                       pd->pd_pwr[point] =
+                                               pcinfo->pwr_x3[point];
+
+                                       /* Fixed points */
+                                       pd->pd_step[point] =
+                                               pcinfo->pcdac_x3[point];
+                               }
+
+                               /* Since we have a higher gain curve
+                                * override min power */
+                               chinfo[pier].min_pwr = pd->pd_pwr[0];
+                       }
+               }
+       }
+
+       return 0;
+}
+
+/* Parse EEPROM data */
+static int
+ath5k_eeprom_read_pcal_info_5112(struct ath5k_hw *ah, int mode)
+{
+       struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
+       struct ath5k_chan_pcal_info_rf5112 *chan_pcal_info;
+       struct ath5k_chan_pcal_info *gen_chan_info;
+       u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
+       u32 offset;
+       u8 i, c;
+       u16 val;
+       int ret;
+       u8 pd_gains = 0;
+
+       /* Count how many curves we have and
+        * identify them (which one of the 4
+        * available curves we have on each count).
+        * Curves are stored from lower (x0) to
+        * higher (x3) gain */
+       for (i = 0; i < AR5K_EEPROM_N_PD_CURVES; i++) {
+               /* ee_x_gain[mode] is x gain mask */
+               if ((ee->ee_x_gain[mode] >> i) & 0x1)
+                       pdgain_idx[pd_gains++] = i;
+       }
+       ee->ee_pd_gains[mode] = pd_gains;
+
+       if (pd_gains == 0 || pd_gains > 2)
+               return -EINVAL;
+
+       switch (mode) {
+       case AR5K_EEPROM_MODE_11A:
+               /*
+                * Read 5GHz EEPROM channels
+                */
+               offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
+               ath5k_eeprom_init_11a_pcal_freq(ah, offset);
+
+               offset += AR5K_EEPROM_GROUP2_OFFSET;
+               gen_chan_info = ee->ee_pwr_cal_a;
+               break;
+       case AR5K_EEPROM_MODE_11B:
+               offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
+               if (AR5K_EEPROM_HDR_11A(ee->ee_header))
+                       offset += AR5K_EEPROM_GROUP3_OFFSET;
+
+               /* NB: frequency piers parsed during mode init */
+               gen_chan_info = ee->ee_pwr_cal_b;
+               break;
+       case AR5K_EEPROM_MODE_11G:
+               offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
+               if (AR5K_EEPROM_HDR_11A(ee->ee_header))
+                       offset += AR5K_EEPROM_GROUP4_OFFSET;
+               else if (AR5K_EEPROM_HDR_11B(ee->ee_header))
+                       offset += AR5K_EEPROM_GROUP2_OFFSET;
+
+               /* NB: frequency piers parsed during mode init */
+               gen_chan_info = ee->ee_pwr_cal_g;
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       for (i = 0; i < ee->ee_n_piers[mode]; i++) {
+               chan_pcal_info = &gen_chan_info[i].rf5112_info;
+
+               /* Power values in quarter dB
+                * for the lower xpd gain curve
+                * (0 dBm -> higher output power) */
+               for (c = 0; c < AR5K_EEPROM_N_XPD0_POINTS; c++) {
+                       AR5K_EEPROM_READ(offset++, val);
+                       chan_pcal_info->pwr_x0[c] = (s8) (val & 0xff);
+                       chan_pcal_info->pwr_x0[++c] = (s8) ((val >> 8) & 0xff);
+               }
+
+               /* PCDAC steps
+                * corresponding to the above power
+                * measurements */
+               AR5K_EEPROM_READ(offset++, val);
+               chan_pcal_info->pcdac_x0[1] = (val & 0x1f);
+               chan_pcal_info->pcdac_x0[2] = ((val >> 5) & 0x1f);
+               chan_pcal_info->pcdac_x0[3] = ((val >> 10) & 0x1f);
+
+               /* Power values in quarter dB
+                * for the higher xpd gain curve
+                * (18 dBm -> lower output power) */
+               AR5K_EEPROM_READ(offset++, val);
+               chan_pcal_info->pwr_x3[0] = (s8) (val & 0xff);
+               chan_pcal_info->pwr_x3[1] = (s8) ((val >> 8) & 0xff);
+
+               AR5K_EEPROM_READ(offset++, val);
+               chan_pcal_info->pwr_x3[2] = (val & 0xff);
+
+               /* PCDAC steps
+                * corresponding to the above power
+                * measurements (fixed) */
+               chan_pcal_info->pcdac_x3[0] = 20;
+               chan_pcal_info->pcdac_x3[1] = 35;
+               chan_pcal_info->pcdac_x3[2] = 63;
+
+               if (ee->ee_version >= AR5K_EEPROM_VERSION_4_3) {
+                       chan_pcal_info->pcdac_x0[0] = ((val >> 8) & 0x3f);
+
+                       /* Last xpd0 power level is also channel maximum */
+                       gen_chan_info[i].max_pwr = chan_pcal_info->pwr_x0[3];
+               } else {
+                       chan_pcal_info->pcdac_x0[0] = 1;
+                       gen_chan_info[i].max_pwr = (s8) ((val >> 8) & 0xff);
+               }
+
+       }
+
+       return ath5k_eeprom_convert_pcal_info_5112(ah, mode, gen_chan_info);
+}
+
+
+/*
+ * Read power calibration for RF2413 chips
+ *
+ * For RF2413 we have a Power to PDDAC table (Power Detector)
+ * instead of a PCDAC and 4 pd gain curves for each calibrated channel.
+ * Each curve has power on x axis in 0.5 db steps and PDDADC steps on y
+ * axis and looks like an exponential function like the RF5111 curve.
+ *
+ * To recreate the curves we read here the points and interpolate
+ * later. Note that in most cases only 2 (higher and lower) curves are
+ * used (like RF5112) but vendors have the oportunity to include all
+ * 4 curves on eeprom. The final curve (higher power) has an extra
+ * point for better accuracy like RF5112.
+ */
+
+/* For RF2413 power calibration data doesn't start on a fixed location and
+ * if a mode is not supported, it's section is missing -not zeroed-.
+ * So we need to calculate the starting offset for each section by using
+ * these two functions */
+
+/* Return the size of each section based on the mode and the number of pd
+ * gains available (maximum 4). */
+static inline unsigned int
+ath5k_pdgains_size_2413(struct ath5k_eeprom_info *ee, unsigned int mode)
+{
+       static const unsigned int pdgains_size[] = { 4, 6, 9, 12 };
+       unsigned int sz;
+
+       sz = pdgains_size[ee->ee_pd_gains[mode] - 1];
+       sz *= ee->ee_n_piers[mode];
+
+       return sz;
+}
+
+/* Return the starting offset for a section based on the modes supported
+ * and each section's size. */
+static unsigned int
+ath5k_cal_data_offset_2413(struct ath5k_eeprom_info *ee, int mode)
+{
+       u32 offset = AR5K_EEPROM_CAL_DATA_START(ee->ee_misc4);
+
+       switch(mode) {
+       case AR5K_EEPROM_MODE_11G:
+               if (AR5K_EEPROM_HDR_11B(ee->ee_header))
+                       offset += ath5k_pdgains_size_2413(ee,
+                                       AR5K_EEPROM_MODE_11B) +
+                                       AR5K_EEPROM_N_2GHZ_CHAN_2413 / 2;
+               /* fall through */
+       case AR5K_EEPROM_MODE_11B:
+               if (AR5K_EEPROM_HDR_11A(ee->ee_header))
+                       offset += ath5k_pdgains_size_2413(ee,
+                                       AR5K_EEPROM_MODE_11A) +
+                                       AR5K_EEPROM_N_5GHZ_CHAN / 2;
+               /* fall through */
+       case AR5K_EEPROM_MODE_11A:
+               break;
+       default:
+               break;
+       }
+
+       return offset;
+}
+
+/* Convert RF2413 specific data to generic raw data
+ * used by interpolation code */
+static int
+ath5k_eeprom_convert_pcal_info_2413(struct ath5k_hw *ah, int mode,
+                               struct ath5k_chan_pcal_info *chinfo)
+{
+       struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
+       struct ath5k_chan_pcal_info_rf2413 *pcinfo;
+       u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
+       unsigned int pier, point;
+       int pdg;
+
+       /* Fill raw data for each calibration pier */
+       for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
+
+               pcinfo = &chinfo[pier].rf2413_info;
+
+               /* Allocate pd_curves for this cal pier */
+               chinfo[pier].pd_curves =
+                               calloc(AR5K_EEPROM_N_PD_CURVES,
+                                      sizeof(struct ath5k_pdgain_info));
+
+               if (!chinfo[pier].pd_curves)
+                       return -ENOMEM;
+
+               /* Fill pd_curves */
+               for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) {
+
+                       u8 idx = pdgain_idx[pdg];
+                       struct ath5k_pdgain_info *pd =
+                                       &chinfo[pier].pd_curves[idx];
+
+                       /* One more point for the highest power
+                        * curve (lowest gain) */
+                       if (pdg == ee->ee_pd_gains[mode] - 1)
+                               pd->pd_points = AR5K_EEPROM_N_PD_POINTS;
+                       else
+                               pd->pd_points = AR5K_EEPROM_N_PD_POINTS - 1;
+
+                       /* Allocate pd points for this curve */
+                       pd->pd_step = calloc(pd->pd_points, sizeof(u8));
+
+                       if (!pd->pd_step)
+                               return -ENOMEM;
+
+                       pd->pd_pwr = calloc(pd->pd_points, sizeof(s16));
+
+                       if (!pd->pd_pwr)
+                               return -ENOMEM;
+
+                       /* Fill raw dataset
+                        * convert all pwr levels to
+                        * quarter dB for RF5112 combatibility */
+                       pd->pd_step[0] = pcinfo->pddac_i[pdg];
+                       pd->pd_pwr[0] = 4 * pcinfo->pwr_i[pdg];
+
+                       for (point = 1; point < pd->pd_points; point++) {
+
+                               pd->pd_pwr[point] = pd->pd_pwr[point - 1] +
+                                       2 * pcinfo->pwr[pdg][point - 1];
+
+                               pd->pd_step[point] = pd->pd_step[point - 1] +
+                                               pcinfo->pddac[pdg][point - 1];
+
+                       }
+
+                       /* Highest gain curve -> min power */
+                       if (pdg == 0)
+                               chinfo[pier].min_pwr = pd->pd_pwr[0];
+
+                       /* Lowest gain curve -> max power */
+                       if (pdg == ee->ee_pd_gains[mode] - 1)
+                               chinfo[pier].max_pwr =
+                                       pd->pd_pwr[pd->pd_points - 1];
+               }
+       }
+
+       return 0;
+}
+
+/* Parse EEPROM data */
+static int
+ath5k_eeprom_read_pcal_info_2413(struct ath5k_hw *ah, int mode)
+{
+       struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
+       struct ath5k_chan_pcal_info_rf2413 *pcinfo;
+       struct ath5k_chan_pcal_info *chinfo;
+       u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
+       u32 offset;
+       int idx, i, ret;
+       u16 val;
+       u8 pd_gains = 0;
+
+       /* Count how many curves we have and
+        * identify them (which one of the 4
+        * available curves we have on each count).
+        * Curves are stored from higher to
+        * lower gain so we go backwards */
+       for (idx = AR5K_EEPROM_N_PD_CURVES - 1; idx >= 0; idx--) {
+               /* ee_x_gain[mode] is x gain mask */
+               if ((ee->ee_x_gain[mode] >> idx) & 0x1)
+                       pdgain_idx[pd_gains++] = idx;
+
+       }
+       ee->ee_pd_gains[mode] = pd_gains;
+
+       if (pd_gains == 0)
+               return -EINVAL;
+
+       offset = ath5k_cal_data_offset_2413(ee, mode);
+       switch (mode) {
+       case AR5K_EEPROM_MODE_11A:
+               if (!AR5K_EEPROM_HDR_11A(ee->ee_header))
+                       return 0;
+
+               ath5k_eeprom_init_11a_pcal_freq(ah, offset);
+               offset += AR5K_EEPROM_N_5GHZ_CHAN / 2;
+               chinfo = ee->ee_pwr_cal_a;
+               break;
+       case AR5K_EEPROM_MODE_11B:
+               if (!AR5K_EEPROM_HDR_11B(ee->ee_header))
+                       return 0;
+
+               ath5k_eeprom_init_11bg_2413(ah, mode, offset);
+               offset += AR5K_EEPROM_N_2GHZ_CHAN_2413 / 2;
+               chinfo = ee->ee_pwr_cal_b;
+               break;
+       case AR5K_EEPROM_MODE_11G:
+               if (!AR5K_EEPROM_HDR_11G(ee->ee_header))
+                       return 0;
+
+               ath5k_eeprom_init_11bg_2413(ah, mode, offset);
+               offset += AR5K_EEPROM_N_2GHZ_CHAN_2413 / 2;
+               chinfo = ee->ee_pwr_cal_g;
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       for (i = 0; i < ee->ee_n_piers[mode]; i++) {
+               pcinfo = &chinfo[i].rf2413_info;
+
+               /*
+                * Read pwr_i, pddac_i and the first
+                * 2 pd points (pwr, pddac)
+                */
+               AR5K_EEPROM_READ(offset++, val);
+               pcinfo->pwr_i[0] = val & 0x1f;
+               pcinfo->pddac_i[0] = (val >> 5) & 0x7f;
+               pcinfo->pwr[0][0] = (val >> 12) & 0xf;
+
+               AR5K_EEPROM_READ(offset++, val);
+               pcinfo->pddac[0][0] = val & 0x3f;
+               pcinfo->pwr[0][1] = (val >> 6) & 0xf;
+               pcinfo->pddac[0][1] = (val >> 10) & 0x3f;
+
+               AR5K_EEPROM_READ(offset++, val);
+               pcinfo->pwr[0][2] = val & 0xf;
+               pcinfo->pddac[0][2] = (val >> 4) & 0x3f;
+
+               pcinfo->pwr[0][3] = 0;
+               pcinfo->pddac[0][3] = 0;
+
+               if (pd_gains > 1) {
+                       /*
+                        * Pd gain 0 is not the last pd gain
+                        * so it only has 2 pd points.
+                        * Continue wih pd gain 1.
+                        */
+                       pcinfo->pwr_i[1] = (val >> 10) & 0x1f;
+
+                       pcinfo->pddac_i[1] = (val >> 15) & 0x1;
+                       AR5K_EEPROM_READ(offset++, val);
+                       pcinfo->pddac_i[1] |= (val & 0x3F) << 1;
+
+                       pcinfo->pwr[1][0] = (val >> 6) & 0xf;
+                       pcinfo->pddac[1][0] = (val >> 10) & 0x3f;
+
+                       AR5K_EEPROM_READ(offset++, val);
+                       pcinfo->pwr[1][1] = val & 0xf;
+                       pcinfo->pddac[1][1] = (val >> 4) & 0x3f;
+                       pcinfo->pwr[1][2] = (val >> 10) & 0xf;
+
+                       pcinfo->pddac[1][2] = (val >> 14) & 0x3;
+                       AR5K_EEPROM_READ(offset++, val);
+                       pcinfo->pddac[1][2] |= (val & 0xF) << 2;
+
+                       pcinfo->pwr[1][3] = 0;
+                       pcinfo->pddac[1][3] = 0;
+               } else if (pd_gains == 1) {
+                       /*
+                        * Pd gain 0 is the last one so
+                        * read the extra point.
+                        */
+                       pcinfo->pwr[0][3] = (val >> 10) & 0xf;
+
+                       pcinfo->pddac[0][3] = (val >> 14) & 0x3;
+                       AR5K_EEPROM_READ(offset++, val);
+                       pcinfo->pddac[0][3] |= (val & 0xF) << 2;
+               }
+
+               /*
+                * Proceed with the other pd_gains
+                * as above.
+                */
+               if (pd_gains > 2) {
+                       pcinfo->pwr_i[2] = (val >> 4) & 0x1f;
+                       pcinfo->pddac_i[2] = (val >> 9) & 0x7f;
+
+                       AR5K_EEPROM_READ(offset++, val);
+                       pcinfo->pwr[2][0] = (val >> 0) & 0xf;
+                       pcinfo->pddac[2][0] = (val >> 4) & 0x3f;
+                       pcinfo->pwr[2][1] = (val >> 10) & 0xf;
+
+                       pcinfo->pddac[2][1] = (val >> 14) & 0x3;
+                       AR5K_EEPROM_READ(offset++, val);
+                       pcinfo->pddac[2][1] |= (val & 0xF) << 2;
+
+                       pcinfo->pwr[2][2] = (val >> 4) & 0xf;
+                       pcinfo->pddac[2][2] = (val >> 8) & 0x3f;
+
+                       pcinfo->pwr[2][3] = 0;
+                       pcinfo->pddac[2][3] = 0;
+               } else if (pd_gains == 2) {
+                       pcinfo->pwr[1][3] = (val >> 4) & 0xf;
+                       pcinfo->pddac[1][3] = (val >> 8) & 0x3f;
+               }
+
+               if (pd_gains > 3) {
+                       pcinfo->pwr_i[3] = (val >> 14) & 0x3;
+                       AR5K_EEPROM_READ(offset++, val);
+                       pcinfo->pwr_i[3] |= ((val >> 0) & 0x7) << 2;
+
+                       pcinfo->pddac_i[3] = (val >> 3) & 0x7f;
+                       pcinfo->pwr[3][0] = (val >> 10) & 0xf;
+                       pcinfo->pddac[3][0] = (val >> 14) & 0x3;
+
+                       AR5K_EEPROM_READ(offset++, val);
+                       pcinfo->pddac[3][0] |= (val & 0xF) << 2;
+                       pcinfo->pwr[3][1] = (val >> 4) & 0xf;
+                       pcinfo->pddac[3][1] = (val >> 8) & 0x3f;
+
+                       pcinfo->pwr[3][2] = (val >> 14) & 0x3;
+                       AR5K_EEPROM_READ(offset++, val);
+                       pcinfo->pwr[3][2] |= ((val >> 0) & 0x3) << 2;
+
+                       pcinfo->pddac[3][2] = (val >> 2) & 0x3f;
+                       pcinfo->pwr[3][3] = (val >> 8) & 0xf;
+
+                       pcinfo->pddac[3][3] = (val >> 12) & 0xF;
+                       AR5K_EEPROM_READ(offset++, val);
+                       pcinfo->pddac[3][3] |= ((val >> 0) & 0x3) << 4;
+               } else if (pd_gains == 3) {
+                       pcinfo->pwr[2][3] = (val >> 14) & 0x3;
+                       AR5K_EEPROM_READ(offset++, val);
+                       pcinfo->pwr[2][3] |= ((val >> 0) & 0x3) << 2;
+
+                       pcinfo->pddac[2][3] = (val >> 2) & 0x3f;
+               }
+       }
+
+       return ath5k_eeprom_convert_pcal_info_2413(ah, mode, chinfo);
+}
+
+
+/*
+ * Read per rate target power (this is the maximum tx power
+ * supported by the card). This info is used when setting
+ * tx power, no matter the channel.
+ *
+ * This also works for v5 EEPROMs.
+ */
+static int
+ath5k_eeprom_read_target_rate_pwr_info(struct ath5k_hw *ah, unsigned int mode)
+{
+       struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
+       struct ath5k_rate_pcal_info *rate_pcal_info;
+       u8 *rate_target_pwr_num;
+       u32 offset;
+       u16 val;
+       int ret, i;
+
+       offset = AR5K_EEPROM_TARGET_PWRSTART(ee->ee_misc1);
+       rate_target_pwr_num = &ee->ee_rate_target_pwr_num[mode];
+       switch (mode) {
+       case AR5K_EEPROM_MODE_11A:
+               offset += AR5K_EEPROM_TARGET_PWR_OFF_11A(ee->ee_version);
+               rate_pcal_info = ee->ee_rate_tpwr_a;
+               ee->ee_rate_target_pwr_num[mode] = AR5K_EEPROM_N_5GHZ_CHAN;
+               break;
+       case AR5K_EEPROM_MODE_11B:
+               offset += AR5K_EEPROM_TARGET_PWR_OFF_11B(ee->ee_version);
+               rate_pcal_info = ee->ee_rate_tpwr_b;
+               ee->ee_rate_target_pwr_num[mode] = 2; /* 3rd is g mode's 1st */
+               break;
+       case AR5K_EEPROM_MODE_11G:
+               offset += AR5K_EEPROM_TARGET_PWR_OFF_11G(ee->ee_version);
+               rate_pcal_info = ee->ee_rate_tpwr_g;
+               ee->ee_rate_target_pwr_num[mode] = AR5K_EEPROM_N_2GHZ_CHAN;
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       /* Different freq mask for older eeproms (<= v3.2) */
+       if (ee->ee_version <= AR5K_EEPROM_VERSION_3_2) {
+               for (i = 0; i < (*rate_target_pwr_num); i++) {
+                       AR5K_EEPROM_READ(offset++, val);
+                       rate_pcal_info[i].freq =
+                           ath5k_eeprom_bin2freq(ee, (val >> 9) & 0x7f, mode);
+
+                       rate_pcal_info[i].target_power_6to24 = ((val >> 3) & 0x3f);
+                       rate_pcal_info[i].target_power_36 = (val << 3) & 0x3f;
+
+                       AR5K_EEPROM_READ(offset++, val);
+
+                       if (rate_pcal_info[i].freq == AR5K_EEPROM_CHANNEL_DIS ||
+                           val == 0) {
+                               (*rate_target_pwr_num) = i;
+                               break;
+                       }
+
+                       rate_pcal_info[i].target_power_36 |= ((val >> 13) & 0x7);
+                       rate_pcal_info[i].target_power_48 = ((val >> 7) & 0x3f);
+                       rate_pcal_info[i].target_power_54 = ((val >> 1) & 0x3f);
+               }
+       } else {
+               for (i = 0; i < (*rate_target_pwr_num); i++) {
+                       AR5K_EEPROM_READ(offset++, val);
+                       rate_pcal_info[i].freq =
+                           ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
+
+                       rate_pcal_info[i].target_power_6to24 = ((val >> 2) & 0x3f);
+                       rate_pcal_info[i].target_power_36 = (val << 4) & 0x3f;
+
+                       AR5K_EEPROM_READ(offset++, val);
+
+                       if (rate_pcal_info[i].freq == AR5K_EEPROM_CHANNEL_DIS ||
+                           val == 0) {
+                               (*rate_target_pwr_num) = i;
+                               break;
+                       }
+
+                       rate_pcal_info[i].target_power_36 |= (val >> 12) & 0xf;
+                       rate_pcal_info[i].target_power_48 = ((val >> 6) & 0x3f);
+                       rate_pcal_info[i].target_power_54 = (val & 0x3f);
+               }
+       }
+
+       return 0;
+}
+
+/*
+ * Read per channel calibration info from EEPROM
+ *
+ * This info is used to calibrate the baseband power table. Imagine
+ * that for each channel there is a power curve that's hw specific
+ * (depends on amplifier etc) and we try to "correct" this curve using
+ * offests we pass on to phy chip (baseband -> before amplifier) so that
+ * it can use accurate power values when setting tx power (takes amplifier's
+ * performance on each channel into account).
+ *
+ * EEPROM provides us with the offsets for some pre-calibrated channels
+ * and we have to interpolate to create the full table for these channels and
+ * also the table for any channel.
+ */
+static int
+ath5k_eeprom_read_pcal_info(struct ath5k_hw *ah)
+{
+       struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
+       int (*read_pcal)(struct ath5k_hw *hw, int mode);
+       int mode;
+       int err;
+
+       if ((ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) &&
+                       (AR5K_EEPROM_EEMAP(ee->ee_misc0) == 1))
+               read_pcal = ath5k_eeprom_read_pcal_info_5112;
+       else if ((ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_0) &&
+                       (AR5K_EEPROM_EEMAP(ee->ee_misc0) == 2))
+               read_pcal = ath5k_eeprom_read_pcal_info_2413;
+       else
+               read_pcal = ath5k_eeprom_read_pcal_info_5111;
+
+
+       for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G;
+       mode++) {
+               err = read_pcal(ah, mode);
+               if (err)
+                       return err;
+
+               err = ath5k_eeprom_read_target_rate_pwr_info(ah, mode);
+               if (err < 0)
+                       return err;
+       }
+
+       return 0;
+}
+
+static int
+ath5k_eeprom_free_pcal_info(struct ath5k_hw *ah, int mode)
+{
+       struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
+       struct ath5k_chan_pcal_info *chinfo;
+       u8 pier, pdg;
+
+       switch (mode) {
+       case AR5K_EEPROM_MODE_11A:
+               if (!AR5K_EEPROM_HDR_11A(ee->ee_header))
+                       return 0;
+               chinfo = ee->ee_pwr_cal_a;
+               break;
+       case AR5K_EEPROM_MODE_11B:
+               if (!AR5K_EEPROM_HDR_11B(ee->ee_header))
+                       return 0;
+               chinfo = ee->ee_pwr_cal_b;
+               break;
+       case AR5K_EEPROM_MODE_11G:
+               if (!AR5K_EEPROM_HDR_11G(ee->ee_header))
+                       return 0;
+               chinfo = ee->ee_pwr_cal_g;
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
+               if (!chinfo[pier].pd_curves)
+                       continue;
+
+               for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) {
+                       struct ath5k_pdgain_info *pd =
+                                       &chinfo[pier].pd_curves[pdg];
+
+                       if (pd != NULL) {
+                               free(pd->pd_step);
+                               free(pd->pd_pwr);
+                       }
+               }
+
+               free(chinfo[pier].pd_curves);
+       }
+
+       return 0;
+}
+
+void
+ath5k_eeprom_detach(struct ath5k_hw *ah)
+{
+       u8 mode;
+
+       for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G; mode++)
+               ath5k_eeprom_free_pcal_info(ah, mode);
+}
+
+/* Read conformance test limits used for regulatory control */
+static int
+ath5k_eeprom_read_ctl_info(struct ath5k_hw *ah)
+{
+       struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
+       struct ath5k_edge_power *rep;
+       unsigned int fmask, pmask;
+       unsigned int ctl_mode;
+       int ret, i, j;
+       u32 offset;
+       u16 val;
+
+       pmask = AR5K_EEPROM_POWER_M;
+       fmask = AR5K_EEPROM_FREQ_M(ee->ee_version);
+       offset = AR5K_EEPROM_CTL(ee->ee_version);
+       ee->ee_ctls = AR5K_EEPROM_N_CTLS(ee->ee_version);
+       for (i = 0; i < ee->ee_ctls; i += 2) {
+               AR5K_EEPROM_READ(offset++, val);
+               ee->ee_ctl[i] = (val >> 8) & 0xff;
+               ee->ee_ctl[i + 1] = val & 0xff;
+       }
+
+       offset = AR5K_EEPROM_GROUP8_OFFSET;
+       if (ee->ee_version >= AR5K_EEPROM_VERSION_4_0)
+               offset += AR5K_EEPROM_TARGET_PWRSTART(ee->ee_misc1) -
+                       AR5K_EEPROM_GROUP5_OFFSET;
+       else
+               offset += AR5K_EEPROM_GROUPS_START(ee->ee_version);
+
+       rep = ee->ee_ctl_pwr;
+       for(i = 0; i < ee->ee_ctls; i++) {
+               switch(ee->ee_ctl[i] & AR5K_CTL_MODE_M) {
+               case AR5K_CTL_11A:
+               case AR5K_CTL_TURBO:
+                       ctl_mode = AR5K_EEPROM_MODE_11A;
+                       break;
+               default:
+                       ctl_mode = AR5K_EEPROM_MODE_11G;
+                       break;
+               }
+               if (ee->ee_ctl[i] == 0) {
+                       if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3)
+                               offset += 8;
+                       else
+                               offset += 7;
+                       rep += AR5K_EEPROM_N_EDGES;
+                       continue;
+               }
+               if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3) {
+                       for (j = 0; j < AR5K_EEPROM_N_EDGES; j += 2) {
+                               AR5K_EEPROM_READ(offset++, val);
+                               rep[j].freq = (val >> 8) & fmask;
+                               rep[j + 1].freq = val & fmask;
+                       }
+                       for (j = 0; j < AR5K_EEPROM_N_EDGES; j += 2) {
+                               AR5K_EEPROM_READ(offset++, val);
+                               rep[j].edge = (val >> 8) & pmask;
+                               rep[j].flag = (val >> 14) & 1;
+                               rep[j + 1].edge = val & pmask;
+                               rep[j + 1].flag = (val >> 6) & 1;
+                       }
+               } else {
+                       AR5K_EEPROM_READ(offset++, val);
+                       rep[0].freq = (val >> 9) & fmask;
+                       rep[1].freq = (val >> 2) & fmask;
+                       rep[2].freq = (val << 5) & fmask;
+
+                       AR5K_EEPROM_READ(offset++, val);
+                       rep[2].freq |= (val >> 11) & 0x1f;
+                       rep[3].freq = (val >> 4) & fmask;
+                       rep[4].freq = (val << 3) & fmask;
+
+                       AR5K_EEPROM_READ(offset++, val);
+                       rep[4].freq |= (val >> 13) & 0x7;
+                       rep[5].freq = (val >> 6) & fmask;
+                       rep[6].freq = (val << 1) & fmask;
+
+                       AR5K_EEPROM_READ(offset++, val);
+                       rep[6].freq |= (val >> 15) & 0x1;
+                       rep[7].freq = (val >> 8) & fmask;
+
+                       rep[0].edge = (val >> 2) & pmask;
+                       rep[1].edge = (val << 4) & pmask;
+
+                       AR5K_EEPROM_READ(offset++, val);
+                       rep[1].edge |= (val >> 12) & 0xf;
+                       rep[2].edge = (val >> 6) & pmask;
+                       rep[3].edge = val & pmask;
+
+                       AR5K_EEPROM_READ(offset++, val);
+                       rep[4].edge = (val >> 10) & pmask;
+                       rep[5].edge = (val >> 4) & pmask;
+                       rep[6].edge = (val << 2) & pmask;
+
+                       AR5K_EEPROM_READ(offset++, val);
+                       rep[6].edge |= (val >> 14) & 0x3;
+                       rep[7].edge = (val >> 8) & pmask;
+               }
+               for (j = 0; j < AR5K_EEPROM_N_EDGES; j++) {
+                       rep[j].freq = ath5k_eeprom_bin2freq(ee,
+                               rep[j].freq, ctl_mode);
+               }
+               rep += AR5K_EEPROM_N_EDGES;
+       }
+
+       return 0;
+}
+
+
+/*
+ * Initialize eeprom power tables
+ */
+int
+ath5k_eeprom_init(struct ath5k_hw *ah)
+{
+       int err;
+
+       err = ath5k_eeprom_init_header(ah);
+       if (err < 0)
+               return err;
+
+       err = ath5k_eeprom_init_modes(ah);
+       if (err < 0)
+               return err;
+
+       err = ath5k_eeprom_read_pcal_info(ah);
+       if (err < 0)
+               return err;
+
+       err = ath5k_eeprom_read_ctl_info(ah);
+       if (err < 0)
+               return err;
+
+       return 0;
+}
+
+/*
+ * Read the MAC address from eeprom
+ */
+int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac)
+{
+       u8 mac_d[ETH_ALEN] = {};
+       u32 total, offset;
+       u16 data;
+       int octet, ret;
+
+       ret = ath5k_hw_eeprom_read(ah, 0x20, &data);
+       if (ret)
+               return ret;
+
+       for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) {
+               ret = ath5k_hw_eeprom_read(ah, offset, &data);
+               if (ret)
+                       return ret;
+
+               total += data;
+               mac_d[octet + 1] = data & 0xff;
+               mac_d[octet] = data >> 8;
+               octet += 2;
+       }
+
+       if (!total || total == 3 * 0xffff)
+               return -EINVAL;
+
+       memcpy(mac, mac_d, ETH_ALEN);
+
+       return 0;
+}
+
+int ath5k_eeprom_is_hb63(struct ath5k_hw *ah)
+{
+       u16 data;
+
+       ath5k_hw_eeprom_read(ah, AR5K_EEPROM_IS_HB63, &data);
+
+       if ((ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4)) && data)
+               return 1;
+       else
+               return 0;
+}
+
diff --git a/src/drivers/net/ath5k/ath5k_gpio.c b/src/drivers/net/ath5k/ath5k_gpio.c
new file mode 100644 (file)
index 0000000..0e8a3e6
--- /dev/null
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
+ * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
+ *
+ * Lightly modified for gPXE, July 2009, by Joshua Oreman <oremanj@rwcr.net>.
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+FILE_LICENCE ( MIT );
+
+/****************\
+  GPIO Functions
+\****************/
+
+#include "ath5k.h"
+#include "reg.h"
+#include "base.h"
+
+/*
+ * Set GPIO inputs
+ */
+int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio)
+{
+       if (gpio >= AR5K_NUM_GPIO)
+               return -EINVAL;
+
+       ath5k_hw_reg_write(ah,
+               (ath5k_hw_reg_read(ah, AR5K_GPIOCR) & ~AR5K_GPIOCR_OUT(gpio))
+               | AR5K_GPIOCR_IN(gpio), AR5K_GPIOCR);
+
+       return 0;
+}
+
+/*
+ * Set GPIO outputs
+ */
+int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio)
+{
+       if (gpio >= AR5K_NUM_GPIO)
+               return -EINVAL;
+
+       ath5k_hw_reg_write(ah,
+               (ath5k_hw_reg_read(ah, AR5K_GPIOCR) & ~AR5K_GPIOCR_OUT(gpio))
+               | AR5K_GPIOCR_OUT(gpio), AR5K_GPIOCR);
+
+       return 0;
+}
+
+/*
+ * Get GPIO state
+ */
+u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio)
+{
+       if (gpio >= AR5K_NUM_GPIO)
+               return 0xffffffff;
+
+       /* GPIO input magic */
+       return ((ath5k_hw_reg_read(ah, AR5K_GPIODI) & AR5K_GPIODI_M) >> gpio) &
+               0x1;
+}
+
+/*
+ * Set GPIO state
+ */
+int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val)
+{
+       u32 data;
+
+       if (gpio >= AR5K_NUM_GPIO)
+               return -EINVAL;
+
+       /* GPIO output magic */
+       data = ath5k_hw_reg_read(ah, AR5K_GPIODO);
+
+       data &= ~(1 << gpio);
+       data |= (val & 1) << gpio;
+
+       ath5k_hw_reg_write(ah, data, AR5K_GPIODO);
+
+       return 0;
+}
+
+/*
+ * Initialize the GPIO interrupt (RFKill switch)
+ */
+void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio,
+               u32 interrupt_level)
+{
+       u32 data;
+
+       if (gpio >= AR5K_NUM_GPIO)
+               return;
+
+       /*
+        * Set the GPIO interrupt
+        */
+       data = (ath5k_hw_reg_read(ah, AR5K_GPIOCR) &
+               ~(AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_SELH |
+               AR5K_GPIOCR_INT_ENA | AR5K_GPIOCR_OUT(gpio))) |
+               (AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_ENA);
+
+       ath5k_hw_reg_write(ah, interrupt_level ? data :
+               (data | AR5K_GPIOCR_INT_SELH), AR5K_GPIOCR);
+
+       ah->ah_imr |= AR5K_IMR_GPIO;
+
+       /* Enable GPIO interrupts */
+       AR5K_REG_ENABLE_BITS(ah, AR5K_PIMR, AR5K_IMR_GPIO);
+}
+
diff --git a/src/drivers/net/ath5k/ath5k_initvals.c b/src/drivers/net/ath5k/ath5k_initvals.c
new file mode 100644 (file)
index 0000000..5911be8
--- /dev/null
@@ -0,0 +1,1560 @@
+/*
+ * Initial register settings functions
+ *
+ * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
+ * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
+ * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
+ *
+ * Lightly modified for gPXE, July 2009, by Joshua Oreman <oremanj@rwcr.net>.
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+FILE_LICENCE ( MIT );
+
+#include <unistd.h>
+
+#include "ath5k.h"
+#include "reg.h"
+#include "base.h"
+
+/*
+ * Mode-independent initial register writes
+ */
+
+struct ath5k_ini {
+       u16     ini_register;
+       u32     ini_value;
+
+       enum {
+               AR5K_INI_WRITE = 0,     /* Default */
+               AR5K_INI_READ = 1,      /* Cleared on read */
+       } ini_mode;
+};
+
+/*
+ * Mode specific initial register values
+ */
+
+struct ath5k_ini_mode {
+       u16     mode_register;
+       u32     mode_value[5];
+};
+
+/* Initial register settings for AR5210 */
+static const struct ath5k_ini ar5210_ini[] = {
+       /* PCU and MAC registers */
+       { AR5K_NOQCU_TXDP0,     0, AR5K_INI_WRITE },
+       { AR5K_NOQCU_TXDP1,     0, AR5K_INI_WRITE },
+       { AR5K_RXDP,            0, AR5K_INI_WRITE },
+       { AR5K_CR,              0, AR5K_INI_WRITE },
+       { AR5K_ISR,             0, AR5K_INI_READ },
+       { AR5K_IMR,             0, AR5K_INI_WRITE },
+       { AR5K_IER,             AR5K_IER_DISABLE, AR5K_INI_WRITE },
+       { AR5K_BSR,             0, AR5K_INI_READ },
+       { AR5K_TXCFG,           AR5K_DMASIZE_128B, AR5K_INI_WRITE },
+       { AR5K_RXCFG,           AR5K_DMASIZE_128B, AR5K_INI_WRITE },
+       { AR5K_CFG,             AR5K_INIT_CFG, AR5K_INI_WRITE },
+       { AR5K_TOPS,            8, AR5K_INI_WRITE },
+       { AR5K_RXNOFRM,         8, AR5K_INI_WRITE },
+       { AR5K_RPGTO,           0, AR5K_INI_WRITE },
+       { AR5K_TXNOFRM,         0, AR5K_INI_WRITE },
+       { AR5K_SFR,             0, AR5K_INI_WRITE },
+       { AR5K_MIBC,            0, AR5K_INI_WRITE },
+       { AR5K_MISC,            0, AR5K_INI_WRITE },
+       { AR5K_RX_FILTER_5210,  0, AR5K_INI_WRITE },
+       { AR5K_MCAST_FILTER0_5210, 0, AR5K_INI_WRITE },
+       { AR5K_MCAST_FILTER1_5210, 0, AR5K_INI_WRITE },
+       { AR5K_TX_MASK0,        0, AR5K_INI_WRITE },
+       { AR5K_TX_MASK1,        0, AR5K_INI_WRITE },
+       { AR5K_CLR_TMASK,       0, AR5K_INI_WRITE },
+       { AR5K_TRIG_LVL,        AR5K_TUNE_MIN_TX_FIFO_THRES, AR5K_INI_WRITE },
+       { AR5K_DIAG_SW_5210,    0, AR5K_INI_WRITE },
+       { AR5K_RSSI_THR,        AR5K_TUNE_RSSI_THRES, AR5K_INI_WRITE },
+       { AR5K_TSF_L32_5210,    0, AR5K_INI_WRITE },
+       { AR5K_TIMER0_5210,     0, AR5K_INI_WRITE },
+       { AR5K_TIMER1_5210,     0xffffffff, AR5K_INI_WRITE },
+       { AR5K_TIMER2_5210,     0xffffffff, AR5K_INI_WRITE },
+       { AR5K_TIMER3_5210,     1, AR5K_INI_WRITE },
+       { AR5K_CFP_DUR_5210,    0, AR5K_INI_WRITE },
+       { AR5K_CFP_PERIOD_5210, 0, AR5K_INI_WRITE },
+       /* PHY registers */
+       { AR5K_PHY(0),  0x00000047, AR5K_INI_WRITE },
+       { AR5K_PHY_AGC, 0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHY(3),  0x09848ea6, AR5K_INI_WRITE },
+       { AR5K_PHY(4),  0x3d32e000, AR5K_INI_WRITE },
+       { AR5K_PHY(5),  0x0000076b, AR5K_INI_WRITE },
+       { AR5K_PHY_ACT, AR5K_PHY_ACT_DISABLE, AR5K_INI_WRITE },
+       { AR5K_PHY(8),  0x02020200, AR5K_INI_WRITE },
+       { AR5K_PHY(9),  0x00000e0e, AR5K_INI_WRITE },
+       { AR5K_PHY(10), 0x0a020201, AR5K_INI_WRITE },
+       { AR5K_PHY(11), 0x00036ffc, AR5K_INI_WRITE },
+       { AR5K_PHY(12), 0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHY(13), 0x00000e0e, AR5K_INI_WRITE },
+       { AR5K_PHY(14), 0x00000007, AR5K_INI_WRITE },
+       { AR5K_PHY(15), 0x00020100, AR5K_INI_WRITE },
+       { AR5K_PHY(16), 0x89630000, AR5K_INI_WRITE },
+       { AR5K_PHY(17), 0x1372169c, AR5K_INI_WRITE },
+       { AR5K_PHY(18), 0x0018b633, AR5K_INI_WRITE },
+       { AR5K_PHY(19), 0x1284613c, AR5K_INI_WRITE },
+       { AR5K_PHY(20), 0x0de8b8e0, AR5K_INI_WRITE },
+       { AR5K_PHY(21), 0x00074859, AR5K_INI_WRITE },
+       { AR5K_PHY(22), 0x7e80beba, AR5K_INI_WRITE },
+       { AR5K_PHY(23), 0x313a665e, AR5K_INI_WRITE },
+       { AR5K_PHY_AGCCTL, 0x00001d08, AR5K_INI_WRITE },
+       { AR5K_PHY(25), 0x0001ce00, AR5K_INI_WRITE },
+       { AR5K_PHY(26), 0x409a4190, AR5K_INI_WRITE },
+       { AR5K_PHY(28), 0x0000000f, AR5K_INI_WRITE },
+       { AR5K_PHY(29), 0x00000080, AR5K_INI_WRITE },
+       { AR5K_PHY(30), 0x00000004, AR5K_INI_WRITE },
+       { AR5K_PHY(31), 0x00000018, AR5K_INI_WRITE },   /* 0x987c */
+       { AR5K_PHY(64), 0x00000000, AR5K_INI_WRITE },   /* 0x9900 */
+       { AR5K_PHY(65), 0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHY(66), 0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHY(67), 0x00800000, AR5K_INI_WRITE },
+       { AR5K_PHY(68), 0x00000003, AR5K_INI_WRITE },
+       /* BB gain table (64bytes) */
+       { AR5K_BB_GAIN(0), 0x00000000, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(1), 0x00000020, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(2), 0x00000010, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(3), 0x00000030, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(4), 0x00000008, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(5), 0x00000028, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(6), 0x00000028, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(7), 0x00000004, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(8), 0x00000024, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(9), 0x00000014, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(10), 0x00000034, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(11), 0x0000000c, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(12), 0x0000002c, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(13), 0x00000002, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(14), 0x00000022, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(15), 0x00000012, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(16), 0x00000032, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(17), 0x0000000a, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(18), 0x0000002a, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(19), 0x00000001, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(20), 0x00000021, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(21), 0x00000011, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(22), 0x00000031, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(23), 0x00000009, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(24), 0x00000029, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(25), 0x00000005, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(26), 0x00000025, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(27), 0x00000015, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(28), 0x00000035, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(29), 0x0000000d, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(30), 0x0000002d, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(31), 0x00000003, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(32), 0x00000023, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(33), 0x00000013, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(34), 0x00000033, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(35), 0x0000000b, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(36), 0x0000002b, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(37), 0x00000007, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(38), 0x00000027, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(39), 0x00000017, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(40), 0x00000037, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(41), 0x0000000f, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(42), 0x0000002f, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(43), 0x0000002f, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(44), 0x0000002f, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(45), 0x0000002f, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(46), 0x0000002f, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(47), 0x0000002f, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(48), 0x0000002f, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(49), 0x0000002f, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(50), 0x0000002f, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(51), 0x0000002f, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(52), 0x0000002f, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(53), 0x0000002f, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(54), 0x0000002f, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(55), 0x0000002f, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(56), 0x0000002f, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(57), 0x0000002f, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(58), 0x0000002f, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(59), 0x0000002f, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(60), 0x0000002f, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(61), 0x0000002f, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(62), 0x0000002f, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(63), 0x0000002f, AR5K_INI_WRITE },
+       /* 5110 RF gain table (64btes) */
+       { AR5K_RF_GAIN(0), 0x0000001d, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(1), 0x0000005d, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(2), 0x0000009d, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(3), 0x000000dd, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(4), 0x0000011d, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(5), 0x00000021, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(6), 0x00000061, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(7), 0x000000a1, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(8), 0x000000e1, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(9), 0x00000031, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(10), 0x00000071, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(11), 0x000000b1, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(12), 0x0000001c, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(13), 0x0000005c, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(14), 0x00000029, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(15), 0x00000069, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(16), 0x000000a9, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(17), 0x00000020, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(18), 0x00000019, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(19), 0x00000059, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(20), 0x00000099, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(21), 0x00000030, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(22), 0x00000005, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(23), 0x00000025, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(24), 0x00000065, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(25), 0x000000a5, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(26), 0x00000028, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(27), 0x00000068, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(28), 0x0000001f, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(29), 0x0000001e, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(30), 0x00000018, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(31), 0x00000058, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(32), 0x00000098, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(33), 0x00000003, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(34), 0x00000004, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(35), 0x00000044, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(36), 0x00000084, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(37), 0x00000013, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(38), 0x00000012, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(39), 0x00000052, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(40), 0x00000092, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(41), 0x000000d2, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(42), 0x0000002b, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(43), 0x0000002a, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(44), 0x0000006a, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(45), 0x000000aa, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(46), 0x0000001b, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(47), 0x0000001a, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(48), 0x0000005a, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(49), 0x0000009a, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(50), 0x000000da, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(51), 0x00000006, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(52), 0x00000006, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(53), 0x00000006, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(54), 0x00000006, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(55), 0x00000006, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(56), 0x00000006, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(57), 0x00000006, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(58), 0x00000006, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(59), 0x00000006, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(60), 0x00000006, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(61), 0x00000006, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(62), 0x00000006, AR5K_INI_WRITE },
+       { AR5K_RF_GAIN(63), 0x00000006, AR5K_INI_WRITE },
+       /* PHY activation */
+       { AR5K_PHY(53), 0x00000020, AR5K_INI_WRITE },
+       { AR5K_PHY(51), 0x00000004, AR5K_INI_WRITE },
+       { AR5K_PHY(50), 0x00060106, AR5K_INI_WRITE },
+       { AR5K_PHY(39), 0x0000006d, AR5K_INI_WRITE },
+       { AR5K_PHY(48), 0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHY(52), 0x00000014, AR5K_INI_WRITE },
+       { AR5K_PHY_ACT, AR5K_PHY_ACT_ENABLE, AR5K_INI_WRITE },
+};
+
+/* Initial register settings for AR5211 */
+static const struct ath5k_ini ar5211_ini[] = {
+       { AR5K_RXDP,            0x00000000, AR5K_INI_WRITE },
+       { AR5K_RTSD0,           0x84849c9c, AR5K_INI_WRITE },
+       { AR5K_RTSD1,           0x7c7c7c7c, AR5K_INI_WRITE },
+       { AR5K_RXCFG,           0x00000005, AR5K_INI_WRITE },
+       { AR5K_MIBC,            0x00000000, AR5K_INI_WRITE },
+       { AR5K_TOPS,            0x00000008, AR5K_INI_WRITE },
+       { AR5K_RXNOFRM,         0x00000008, AR5K_INI_WRITE },
+       { AR5K_TXNOFRM,         0x00000010, AR5K_INI_WRITE },
+       { AR5K_RPGTO,           0x00000000, AR5K_INI_WRITE },
+       { AR5K_RFCNT,           0x0000001f, AR5K_INI_WRITE },
+       { AR5K_QUEUE_TXDP(0),   0x00000000, AR5K_INI_WRITE },
+       { AR5K_QUEUE_TXDP(1),   0x00000000, AR5K_INI_WRITE },
+       { AR5K_QUEUE_TXDP(2),   0x00000000, AR5K_INI_WRITE },
+       { AR5K_QUEUE_TXDP(3),   0x00000000, AR5K_INI_WRITE },
+       { AR5K_QUEUE_TXDP(4),   0x00000000, AR5K_INI_WRITE },
+       { AR5K_QUEUE_TXDP(5),   0x00000000, AR5K_INI_WRITE },
+       { AR5K_QUEUE_TXDP(6),   0x00000000, AR5K_INI_WRITE },
+       { AR5K_QUEUE_TXDP(7),   0x00000000, AR5K_INI_WRITE },
+       { AR5K_QUEUE_TXDP(8),   0x00000000, AR5K_INI_WRITE },
+       { AR5K_QUEUE_TXDP(9),   0x00000000, AR5K_INI_WRITE },
+       { AR5K_DCU_FP,          0x00000000, AR5K_INI_WRITE },
+       { AR5K_STA_ID1,         0x00000000, AR5K_INI_WRITE },
+       { AR5K_BSS_ID0,         0x00000000, AR5K_INI_WRITE },
+       { AR5K_BSS_ID1,         0x00000000, AR5K_INI_WRITE },
+       { AR5K_RSSI_THR,        0x00000000, AR5K_INI_WRITE },
+       { AR5K_CFP_PERIOD_5211, 0x00000000, AR5K_INI_WRITE },
+       { AR5K_TIMER0_5211,     0x00000030, AR5K_INI_WRITE },
+       { AR5K_TIMER1_5211,     0x0007ffff, AR5K_INI_WRITE },
+       { AR5K_TIMER2_5211,     0x01ffffff, AR5K_INI_WRITE },
+       { AR5K_TIMER3_5211,     0x00000031, AR5K_INI_WRITE },
+       { AR5K_CFP_DUR_5211,    0x00000000, AR5K_INI_WRITE },
+       { AR5K_RX_FILTER_5211,  0x00000000, AR5K_INI_WRITE },
+       { AR5K_MCAST_FILTER0_5211, 0x00000000, AR5K_INI_WRITE },
+       { AR5K_MCAST_FILTER1_5211, 0x00000002, AR5K_INI_WRITE },
+       { AR5K_DIAG_SW_5211,    0x00000000, AR5K_INI_WRITE },
+       { AR5K_ADDAC_TEST,      0x00000000, AR5K_INI_WRITE },
+       { AR5K_DEFAULT_ANTENNA, 0x00000000, AR5K_INI_WRITE },
+       /* PHY registers */
+       { AR5K_PHY_AGC, 0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHY(3),  0x2d849093, AR5K_INI_WRITE },
+       { AR5K_PHY(4),  0x7d32e000, AR5K_INI_WRITE },
+       { AR5K_PHY(5),  0x00000f6b, AR5K_INI_WRITE },
+       { AR5K_PHY_ACT, 0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHY(11), 0x00026ffe, AR5K_INI_WRITE },
+       { AR5K_PHY(12), 0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHY(15), 0x00020100, AR5K_INI_WRITE },
+       { AR5K_PHY(16), 0x206a017a, AR5K_INI_WRITE },
+       { AR5K_PHY(19), 0x1284613c, AR5K_INI_WRITE },
+       { AR5K_PHY(21), 0x00000859, AR5K_INI_WRITE },
+       { AR5K_PHY(26), 0x409a4190, AR5K_INI_WRITE },   /* 0x9868 */
+       { AR5K_PHY(27), 0x050cb081, AR5K_INI_WRITE },
+       { AR5K_PHY(28), 0x0000000f, AR5K_INI_WRITE },
+       { AR5K_PHY(29), 0x00000080, AR5K_INI_WRITE },
+       { AR5K_PHY(30), 0x0000000c, AR5K_INI_WRITE },
+       { AR5K_PHY(64), 0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHY(65), 0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHY(66), 0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHY(67), 0x00800000, AR5K_INI_WRITE },
+       { AR5K_PHY(68), 0x00000001, AR5K_INI_WRITE },
+       { AR5K_PHY(71), 0x0000092a, AR5K_INI_WRITE },
+       { AR5K_PHY_IQ,  0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHY(73), 0x00058a05, AR5K_INI_WRITE },
+       { AR5K_PHY(74), 0x00000001, AR5K_INI_WRITE },
+       { AR5K_PHY(75), 0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHY_PAPD_PROBE, 0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHY(77), 0x00000000, AR5K_INI_WRITE },   /* 0x9934 */
+       { AR5K_PHY(78), 0x00000000, AR5K_INI_WRITE },   /* 0x9938 */
+       { AR5K_PHY(79), 0x0000003f, AR5K_INI_WRITE },   /* 0x993c */
+       { AR5K_PHY(80), 0x00000004, AR5K_INI_WRITE },
+       { AR5K_PHY(82), 0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHY(83), 0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHY(84), 0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHY_RADAR, 0x5d50f14c, AR5K_INI_WRITE },
+       { AR5K_PHY(86), 0x00000018, AR5K_INI_WRITE },
+       { AR5K_PHY(87), 0x004b6a8e, AR5K_INI_WRITE },
+       /* Initial Power table (32bytes)
+        * common on all cards/modes.
+        * Note: Table is rewritten during
+        * txpower setup later using calibration
+        * data etc. so next write is non-common */
+       { AR5K_PHY_PCDAC_TXPOWER(1), 0x06ff05ff, AR5K_INI_WRITE },
+       { AR5K_PHY_PCDAC_TXPOWER(2), 0x07ff07ff, AR5K_INI_WRITE },
+       { AR5K_PHY_PCDAC_TXPOWER(3), 0x08ff08ff, AR5K_INI_WRITE },
+       { AR5K_PHY_PCDAC_TXPOWER(4), 0x09ff09ff, AR5K_INI_WRITE },
+       { AR5K_PHY_PCDAC_TXPOWER(5), 0x0aff0aff, AR5K_INI_WRITE },
+       { AR5K_PHY_PCDAC_TXPOWER(6), 0x0bff0bff, AR5K_INI_WRITE },
+       { AR5K_PHY_PCDAC_TXPOWER(7), 0x0cff0cff, AR5K_INI_WRITE },
+       { AR5K_PHY_PCDAC_TXPOWER(8), 0x0dff0dff, AR5K_INI_WRITE },
+       { AR5K_PHY_PCDAC_TXPOWER(9), 0x0fff0eff, AR5K_INI_WRITE },
+       { AR5K_PHY_PCDAC_TXPOWER(10), 0x12ff12ff, AR5K_INI_WRITE },
+       { AR5K_PHY_PCDAC_TXPOWER(11), 0x14ff13ff, AR5K_INI_WRITE },
+       { AR5K_PHY_PCDAC_TXPOWER(12), 0x16ff15ff, AR5K_INI_WRITE },
+       { AR5K_PHY_PCDAC_TXPOWER(13), 0x19ff17ff, AR5K_INI_WRITE },
+       { AR5K_PHY_PCDAC_TXPOWER(14), 0x1bff1aff, AR5K_INI_WRITE },
+       { AR5K_PHY_PCDAC_TXPOWER(15), 0x1eff1dff, AR5K_INI_WRITE },
+       { AR5K_PHY_PCDAC_TXPOWER(16), 0x23ff20ff, AR5K_INI_WRITE },
+       { AR5K_PHY_PCDAC_TXPOWER(17), 0x27ff25ff, AR5K_INI_WRITE },
+       { AR5K_PHY_PCDAC_TXPOWER(18), 0x2cff29ff, AR5K_INI_WRITE },
+       { AR5K_PHY_PCDAC_TXPOWER(19), 0x31ff2fff, AR5K_INI_WRITE },
+       { AR5K_PHY_PCDAC_TXPOWER(20), 0x37ff34ff, AR5K_INI_WRITE },
+       { AR5K_PHY_PCDAC_TXPOWER(21), 0x3aff3aff, AR5K_INI_WRITE },
+       { AR5K_PHY_PCDAC_TXPOWER(22), 0x3aff3aff, AR5K_INI_WRITE },
+       { AR5K_PHY_PCDAC_TXPOWER(23), 0x3aff3aff, AR5K_INI_WRITE },
+       { AR5K_PHY_PCDAC_TXPOWER(24), 0x3aff3aff, AR5K_INI_WRITE },
+       { AR5K_PHY_PCDAC_TXPOWER(25), 0x3aff3aff, AR5K_INI_WRITE },
+       { AR5K_PHY_PCDAC_TXPOWER(26), 0x3aff3aff, AR5K_INI_WRITE },
+       { AR5K_PHY_PCDAC_TXPOWER(27), 0x3aff3aff, AR5K_INI_WRITE },
+       { AR5K_PHY_PCDAC_TXPOWER(28), 0x3aff3aff, AR5K_INI_WRITE },
+       { AR5K_PHY_PCDAC_TXPOWER(29), 0x3aff3aff, AR5K_INI_WRITE },
+       { AR5K_PHY_PCDAC_TXPOWER(30), 0x3aff3aff, AR5K_INI_WRITE },
+       { AR5K_PHY_PCDAC_TXPOWER(31), 0x3aff3aff, AR5K_INI_WRITE },
+       { AR5K_PHY_CCKTXCTL, 0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHY(642), 0x503e4646, AR5K_INI_WRITE },
+       { AR5K_PHY_GAIN_2GHZ, 0x6480416c, AR5K_INI_WRITE },
+       { AR5K_PHY(644), 0x0199a003, AR5K_INI_WRITE },
+       { AR5K_PHY(645), 0x044cd610, AR5K_INI_WRITE },
+       { AR5K_PHY(646), 0x13800040, AR5K_INI_WRITE },
+       { AR5K_PHY(647), 0x1be00060, AR5K_INI_WRITE },
+       { AR5K_PHY(648), 0x0c53800a, AR5K_INI_WRITE },
+       { AR5K_PHY(649), 0x0014df3b, AR5K_INI_WRITE },
+       { AR5K_PHY(650), 0x000001b5, AR5K_INI_WRITE },
+       { AR5K_PHY(651), 0x00000020, AR5K_INI_WRITE },
+};
+
+/* Initial mode-specific settings for AR5211
+ * 5211 supports OFDM-only g (draft g) but we
+ * need to test it !
+ */
+static const struct ath5k_ini_mode ar5211_ini_mode[] = {
+       { AR5K_TXCFG,
+       /*        a         aTurbo        b       g (OFDM)    */
+          { 0x00000015, 0x00000015, 0x0000001d, 0x00000015 } },
+       { AR5K_QUEUE_DFS_LOCAL_IFS(0),
+          { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
+       { AR5K_QUEUE_DFS_LOCAL_IFS(1),
+          { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
+       { AR5K_QUEUE_DFS_LOCAL_IFS(2),
+          { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
+       { AR5K_QUEUE_DFS_LOCAL_IFS(3),
+          { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
+       { AR5K_QUEUE_DFS_LOCAL_IFS(4),
+          { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
+       { AR5K_QUEUE_DFS_LOCAL_IFS(5),
+          { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
+       { AR5K_QUEUE_DFS_LOCAL_IFS(6),
+          { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
+       { AR5K_QUEUE_DFS_LOCAL_IFS(7),
+          { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
+       { AR5K_QUEUE_DFS_LOCAL_IFS(8),
+          { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
+       { AR5K_QUEUE_DFS_LOCAL_IFS(9),
+          { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
+       { AR5K_DCU_GBL_IFS_SLOT,
+          { 0x00000168, 0x000001e0, 0x000001b8, 0x00000168 } },
+       { AR5K_DCU_GBL_IFS_SIFS,
+          { 0x00000230, 0x000001e0, 0x000000b0, 0x00000230 } },
+       { AR5K_DCU_GBL_IFS_EIFS,
+          { 0x00000d98, 0x00001180, 0x00001f48, 0x00000d98 } },
+       { AR5K_DCU_GBL_IFS_MISC,
+          { 0x0000a0e0, 0x00014068, 0x00005880, 0x0000a0e0 } },
+       { AR5K_TIME_OUT,
+          { 0x04000400, 0x08000800, 0x20003000, 0x04000400 } },
+       { AR5K_USEC_5211,
+          { 0x0e8d8fa7, 0x0e8d8fcf, 0x01608f95, 0x0e8d8fa7 } },
+       { AR5K_PHY_TURBO,
+          { 0x00000000, 0x00000003, 0x00000000, 0x00000000 } },
+       { AR5K_PHY(8),
+          { 0x02020200, 0x02020200, 0x02010200, 0x02020200 } },
+       { AR5K_PHY(9),
+          { 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e } },
+       { AR5K_PHY(10),
+          { 0x0a020001, 0x0a020001, 0x05010000, 0x0a020001 } },
+       { AR5K_PHY(13),
+          { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
+       { AR5K_PHY(14),
+          { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b } },
+       { AR5K_PHY(17),
+          { 0x1372169c, 0x137216a5, 0x137216a8, 0x1372169c } },
+       { AR5K_PHY(18),
+          { 0x0018ba67, 0x0018ba67, 0x0018ba69, 0x0018ba69 } },
+       { AR5K_PHY(20),
+          { 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0 } },
+       { AR5K_PHY_SIG,
+          { 0x7e800d2e, 0x7e800d2e, 0x7ec00d2e, 0x7e800d2e } },
+       { AR5K_PHY_AGCCOARSE,
+          { 0x31375d5e, 0x31375d5e, 0x313a5d5e, 0x31375d5e } },
+       { AR5K_PHY_AGCCTL,
+          { 0x0000bd10, 0x0000bd10, 0x0000bd38, 0x0000bd10 } },
+       { AR5K_PHY_NF,
+          { 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 } },
+       { AR5K_PHY_RX_DELAY,
+          { 0x00002710, 0x00002710, 0x0000157c, 0x00002710 } },
+       { AR5K_PHY(70),
+          { 0x00000190, 0x00000190, 0x00000084, 0x00000190 } },
+       { AR5K_PHY_FRAME_CTL_5211,
+          { 0x6fe01020, 0x6fe01020, 0x6fe00920, 0x6fe01020 } },
+       { AR5K_PHY_PCDAC_TXPOWER_BASE,
+          { 0x05ff14ff, 0x05ff14ff, 0x05ff14ff, 0x05ff19ff } },
+       { AR5K_RF_BUFFER_CONTROL_4,
+          { 0x00000010, 0x00000014, 0x00000010, 0x00000010 } },
+};
+
+/* Initial register settings for AR5212 */
+static const struct ath5k_ini ar5212_ini_common_start[] = {
+       { AR5K_RXDP,            0x00000000, AR5K_INI_WRITE },
+       { AR5K_RXCFG,           0x00000005, AR5K_INI_WRITE },
+       { AR5K_MIBC,            0x00000000, AR5K_INI_WRITE },
+       { AR5K_TOPS,            0x00000008, AR5K_INI_WRITE },
+       { AR5K_RXNOFRM,         0x00000008, AR5K_INI_WRITE },
+       { AR5K_TXNOFRM,         0x00000010, AR5K_INI_WRITE },
+       { AR5K_RPGTO,           0x00000000, AR5K_INI_WRITE },
+       { AR5K_RFCNT,           0x0000001f, AR5K_INI_WRITE },
+       { AR5K_QUEUE_TXDP(0),   0x00000000, AR5K_INI_WRITE },
+       { AR5K_QUEUE_TXDP(1),   0x00000000, AR5K_INI_WRITE },
+       { AR5K_QUEUE_TXDP(2),   0x00000000, AR5K_INI_WRITE },
+       { AR5K_QUEUE_TXDP(3),   0x00000000, AR5K_INI_WRITE },
+       { AR5K_QUEUE_TXDP(4),   0x00000000, AR5K_INI_WRITE },
+       { AR5K_QUEUE_TXDP(5),   0x00000000, AR5K_INI_WRITE },
+       { AR5K_QUEUE_TXDP(6),   0x00000000, AR5K_INI_WRITE },
+       { AR5K_QUEUE_TXDP(7),   0x00000000, AR5K_INI_WRITE },
+       { AR5K_QUEUE_TXDP(8),   0x00000000, AR5K_INI_WRITE },
+       { AR5K_QUEUE_TXDP(9),   0x00000000, AR5K_INI_WRITE },
+       { AR5K_DCU_FP,          0x00000000, AR5K_INI_WRITE },
+       { AR5K_DCU_TXP,         0x00000000, AR5K_INI_WRITE },
+       /* Tx filter table 0 (32 entries) */
+       { AR5K_DCU_TX_FILTER_0(0),  0x00000000, AR5K_INI_WRITE }, /* DCU 0 */
+       { AR5K_DCU_TX_FILTER_0(1),  0x00000000, AR5K_INI_WRITE },
+       { AR5K_DCU_TX_FILTER_0(2),  0x00000000, AR5K_INI_WRITE },
+       { AR5K_DCU_TX_FILTER_0(3),  0x00000000, AR5K_INI_WRITE },
+       { AR5K_DCU_TX_FILTER_0(4),  0x00000000, AR5K_INI_WRITE }, /* DCU 1 */
+       { AR5K_DCU_TX_FILTER_0(5),  0x00000000, AR5K_INI_WRITE },
+       { AR5K_DCU_TX_FILTER_0(6),  0x00000000, AR5K_INI_WRITE },
+       { AR5K_DCU_TX_FILTER_0(7),  0x00000000, AR5K_INI_WRITE },
+       { AR5K_DCU_TX_FILTER_0(8),  0x00000000, AR5K_INI_WRITE }, /* DCU 2 */
+       { AR5K_DCU_TX_FILTER_0(9),  0x00000000, AR5K_INI_WRITE },
+       { AR5K_DCU_TX_FILTER_0(10), 0x00000000, AR5K_INI_WRITE },
+       { AR5K_DCU_TX_FILTER_0(11), 0x00000000, AR5K_INI_WRITE },
+       { AR5K_DCU_TX_FILTER_0(12), 0x00000000, AR5K_INI_WRITE }, /* DCU 3 */
+       { AR5K_DCU_TX_FILTER_0(13), 0x00000000, AR5K_INI_WRITE },
+       { AR5K_DCU_TX_FILTER_0(14), 0x00000000, AR5K_INI_WRITE },
+       { AR5K_DCU_TX_FILTER_0(15), 0x00000000, AR5K_INI_WRITE },
+       { AR5K_DCU_TX_FILTER_0(16), 0x00000000, AR5K_INI_WRITE }, /* DCU 4 */
+       { AR5K_DCU_TX_FILTER_0(17), 0x00000000, AR5K_INI_WRITE },
+       { AR5K_DCU_TX_FILTER_0(18), 0x00000000, AR5K_INI_WRITE },
+       { AR5K_DCU_TX_FILTER_0(19), 0x00000000, AR5K_INI_WRITE },
+       { AR5K_DCU_TX_FILTER_0(20), 0x00000000, AR5K_INI_WRITE }, /* DCU 5 */
+       { AR5K_DCU_TX_FILTER_0(21), 0x00000000, AR5K_INI_WRITE },
+       { AR5K_DCU_TX_FILTER_0(22), 0x00000000, AR5K_INI_WRITE },
+       { AR5K_DCU_TX_FILTER_0(23), 0x00000000, AR5K_INI_WRITE },
+       { AR5K_DCU_TX_FILTER_0(24), 0x00000000, AR5K_INI_WRITE }, /* DCU 6 */
+       { AR5K_DCU_TX_FILTER_0(25), 0x00000000, AR5K_INI_WRITE },
+       { AR5K_DCU_TX_FILTER_0(26), 0x00000000, AR5K_INI_WRITE },
+       { AR5K_DCU_TX_FILTER_0(27), 0x00000000, AR5K_INI_WRITE },
+       { AR5K_DCU_TX_FILTER_0(28), 0x00000000, AR5K_INI_WRITE }, /* DCU 7 */
+       { AR5K_DCU_TX_FILTER_0(29), 0x00000000, AR5K_INI_WRITE },
+       { AR5K_DCU_TX_FILTER_0(30), 0x00000000, AR5K_INI_WRITE },
+       { AR5K_DCU_TX_FILTER_0(31), 0x00000000, AR5K_INI_WRITE },
+       /* Tx filter table 1 (16 entries) */
+       { AR5K_DCU_TX_FILTER_1(0),  0x00000000, AR5K_INI_WRITE },
+       { AR5K_DCU_TX_FILTER_1(1),  0x00000000, AR5K_INI_WRITE },
+       { AR5K_DCU_TX_FILTER_1(2),  0x00000000, AR5K_INI_WRITE },
+       { AR5K_DCU_TX_FILTER_1(3),  0x00000000, AR5K_INI_WRITE },
+       { AR5K_DCU_TX_FILTER_1(4),  0x00000000, AR5K_INI_WRITE },
+       { AR5K_DCU_TX_FILTER_1(5),  0x00000000, AR5K_INI_WRITE },
+       { AR5K_DCU_TX_FILTER_1(6),  0x00000000, AR5K_INI_WRITE },
+       { AR5K_DCU_TX_FILTER_1(7),  0x00000000, AR5K_INI_WRITE },
+       { AR5K_DCU_TX_FILTER_1(8),  0x00000000, AR5K_INI_WRITE },
+       { AR5K_DCU_TX_FILTER_1(9),  0x00000000, AR5K_INI_WRITE },
+       { AR5K_DCU_TX_FILTER_1(10), 0x00000000, AR5K_INI_WRITE },
+       { AR5K_DCU_TX_FILTER_1(11), 0x00000000, AR5K_INI_WRITE },
+       { AR5K_DCU_TX_FILTER_1(12), 0x00000000, AR5K_INI_WRITE },
+       { AR5K_DCU_TX_FILTER_1(13), 0x00000000, AR5K_INI_WRITE },
+       { AR5K_DCU_TX_FILTER_1(14), 0x00000000, AR5K_INI_WRITE },
+       { AR5K_DCU_TX_FILTER_1(15), 0x00000000, AR5K_INI_WRITE },
+       { AR5K_DCU_TX_FILTER_CLR, 0x00000000, AR5K_INI_WRITE },
+       { AR5K_DCU_TX_FILTER_SET, 0x00000000, AR5K_INI_WRITE },
+       { AR5K_DCU_TX_FILTER_CLR, 0x00000000, AR5K_INI_WRITE },
+       { AR5K_DCU_TX_FILTER_SET, 0x00000000, AR5K_INI_WRITE },
+       { AR5K_STA_ID1,         0x00000000, AR5K_INI_WRITE },
+       { AR5K_BSS_ID0,         0x00000000, AR5K_INI_WRITE },
+       { AR5K_BSS_ID1,         0x00000000, AR5K_INI_WRITE },
+       { AR5K_BEACON_5211,     0x00000000, AR5K_INI_WRITE },
+       { AR5K_CFP_PERIOD_5211, 0x00000000, AR5K_INI_WRITE },
+       { AR5K_TIMER0_5211,     0x00000030, AR5K_INI_WRITE },
+       { AR5K_TIMER1_5211,     0x0007ffff, AR5K_INI_WRITE },
+       { AR5K_TIMER2_5211,     0x01ffffff, AR5K_INI_WRITE },
+       { AR5K_TIMER3_5211,     0x00000031, AR5K_INI_WRITE },
+       { AR5K_CFP_DUR_5211,    0x00000000, AR5K_INI_WRITE },
+       { AR5K_RX_FILTER_5211,  0x00000000, AR5K_INI_WRITE },
+       { AR5K_DIAG_SW_5211,    0x00000000, AR5K_INI_WRITE },
+       { AR5K_ADDAC_TEST,      0x00000000, AR5K_INI_WRITE },
+       { AR5K_DEFAULT_ANTENNA, 0x00000000, AR5K_INI_WRITE },
+       { AR5K_FRAME_CTL_QOSM,  0x000fc78f, AR5K_INI_WRITE },
+       { AR5K_XRMODE,          0x2a82301a, AR5K_INI_WRITE },
+       { AR5K_XRDELAY,         0x05dc01e0, AR5K_INI_WRITE },
+       { AR5K_XRTIMEOUT,       0x1f402710, AR5K_INI_WRITE },
+       { AR5K_XRCHIRP,         0x01f40000, AR5K_INI_WRITE },
+       { AR5K_XRSTOMP,         0x00001e1c, AR5K_INI_WRITE },
+       { AR5K_SLEEP0,          0x0002aaaa, AR5K_INI_WRITE },
+       { AR5K_SLEEP1,          0x02005555, AR5K_INI_WRITE },
+       { AR5K_SLEEP2,          0x00000000, AR5K_INI_WRITE },
+       { AR5K_BSS_IDM0,        0xffffffff, AR5K_INI_WRITE },
+       { AR5K_BSS_IDM1,        0x0000ffff, AR5K_INI_WRITE },
+       { AR5K_TXPC,            0x00000000, AR5K_INI_WRITE },
+       { AR5K_PROFCNT_TX,      0x00000000, AR5K_INI_WRITE },
+       { AR5K_PROFCNT_RX,      0x00000000, AR5K_INI_WRITE },
+       { AR5K_PROFCNT_RXCLR,   0x00000000, AR5K_INI_WRITE },
+       { AR5K_PROFCNT_CYCLE,   0x00000000, AR5K_INI_WRITE },
+       { AR5K_QUIET_CTL1,      0x00000088, AR5K_INI_WRITE },
+       /* Initial rate duration table (32 entries )*/
+       { AR5K_RATE_DUR(0),     0x00000000, AR5K_INI_WRITE },
+       { AR5K_RATE_DUR(1),     0x0000008c, AR5K_INI_WRITE },
+       { AR5K_RATE_DUR(2),     0x000000e4, AR5K_INI_WRITE },
+       { AR5K_RATE_DUR(3),     0x000002d5, AR5K_INI_WRITE },
+       { AR5K_RATE_DUR(4),     0x00000000, AR5K_INI_WRITE },
+       { AR5K_RATE_DUR(5),     0x00000000, AR5K_INI_WRITE },
+       { AR5K_RATE_DUR(6),     0x000000a0, AR5K_INI_WRITE },
+       { AR5K_RATE_DUR(7),     0x000001c9, AR5K_INI_WRITE },
+       { AR5K_RATE_DUR(8),     0x0000002c, AR5K_INI_WRITE },
+       { AR5K_RATE_DUR(9),     0x0000002c, AR5K_INI_WRITE },
+       { AR5K_RATE_DUR(10),    0x00000030, AR5K_INI_WRITE },
+       { AR5K_RATE_DUR(11),    0x0000003c, AR5K_INI_WRITE },
+       { AR5K_RATE_DUR(12),    0x0000002c, AR5K_INI_WRITE },
+       { AR5K_RATE_DUR(13),    0x0000002c, AR5K_INI_WRITE },
+       { AR5K_RATE_DUR(14),    0x00000030, AR5K_INI_WRITE },
+       { AR5K_RATE_DUR(15),    0x0000003c, AR5K_INI_WRITE },
+       { AR5K_RATE_DUR(16),    0x00000000, AR5K_INI_WRITE },
+       { AR5K_RATE_DUR(17),    0x00000000, AR5K_INI_WRITE },
+       { AR5K_RATE_DUR(18),    0x00000000, AR5K_INI_WRITE },
+       { AR5K_RATE_DUR(19),    0x00000000, AR5K_INI_WRITE },
+       { AR5K_RATE_DUR(20),    0x00000000, AR5K_INI_WRITE },
+       { AR5K_RATE_DUR(21),    0x00000000, AR5K_INI_WRITE },
+       { AR5K_RATE_DUR(22),    0x00000000, AR5K_INI_WRITE },
+       { AR5K_RATE_DUR(23),    0x00000000, AR5K_INI_WRITE },
+       { AR5K_RATE_DUR(24),    0x000000d5, AR5K_INI_WRITE },
+       { AR5K_RATE_DUR(25),    0x000000df, AR5K_INI_WRITE },
+       { AR5K_RATE_DUR(26),    0x00000102, AR5K_INI_WRITE },
+       { AR5K_RATE_DUR(27),    0x0000013a, AR5K_INI_WRITE },
+       { AR5K_RATE_DUR(28),    0x00000075, AR5K_INI_WRITE },
+       { AR5K_RATE_DUR(29),    0x0000007f, AR5K_INI_WRITE },
+       { AR5K_RATE_DUR(30),    0x000000a2, AR5K_INI_WRITE },
+       { AR5K_RATE_DUR(31),    0x00000000, AR5K_INI_WRITE },
+       { AR5K_QUIET_CTL2,      0x00010002, AR5K_INI_WRITE },
+       { AR5K_TSF_PARM,        0x00000001, AR5K_INI_WRITE },
+       { AR5K_QOS_NOACK,       0x000000c0, AR5K_INI_WRITE },
+       { AR5K_PHY_ERR_FIL,     0x00000000, AR5K_INI_WRITE },
+       { AR5K_XRLAT_TX,        0x00000168, AR5K_INI_WRITE },
+       { AR5K_ACKSIFS,         0x00000000, AR5K_INI_WRITE },
+       /* Rate -> db table
+        * notice ...03<-02<-01<-00 ! */
+       { AR5K_RATE2DB(0),      0x03020100, AR5K_INI_WRITE },
+       { AR5K_RATE2DB(1),      0x07060504, AR5K_INI_WRITE },
+       { AR5K_RATE2DB(2),      0x0b0a0908, AR5K_INI_WRITE },
+       { AR5K_RATE2DB(3),      0x0f0e0d0c, AR5K_INI_WRITE },
+       { AR5K_RATE2DB(4),      0x13121110, AR5K_INI_WRITE },
+       { AR5K_RATE2DB(5),      0x17161514, AR5K_INI_WRITE },
+       { AR5K_RATE2DB(6),      0x1b1a1918, AR5K_INI_WRITE },
+       { AR5K_RATE2DB(7),      0x1f1e1d1c, AR5K_INI_WRITE },
+       /* Db -> Rate table */
+       { AR5K_DB2RATE(0),      0x03020100, AR5K_INI_WRITE },
+       { AR5K_DB2RATE(1),      0x07060504, AR5K_INI_WRITE },
+       { AR5K_DB2RATE(2),      0x0b0a0908, AR5K_INI_WRITE },
+       { AR5K_DB2RATE(3),      0x0f0e0d0c, AR5K_INI_WRITE },
+       { AR5K_DB2RATE(4),      0x13121110, AR5K_INI_WRITE },
+       { AR5K_DB2RATE(5),      0x17161514, AR5K_INI_WRITE },
+       { AR5K_DB2RATE(6),      0x1b1a1918, AR5K_INI_WRITE },
+       { AR5K_DB2RATE(7),      0x1f1e1d1c, AR5K_INI_WRITE },
+       /* PHY registers (Common settings
+        * for all chips/modes) */
+       { AR5K_PHY(3),          0xad848e19, AR5K_INI_WRITE },
+       { AR5K_PHY(4),          0x7d28e000, AR5K_INI_WRITE },
+       { AR5K_PHY_TIMING_3,    0x9c0a9f6b, AR5K_INI_WRITE },
+       { AR5K_PHY_ACT,         0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHY(16),         0x206a017a, AR5K_INI_WRITE },
+       { AR5K_PHY(21),         0x00000859, AR5K_INI_WRITE },
+       { AR5K_PHY_BIN_MASK_1,  0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHY_BIN_MASK_2,  0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHY_BIN_MASK_3,  0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHY_BIN_MASK_CTL, 0x00800000, AR5K_INI_WRITE },
+       { AR5K_PHY_ANT_CTL,     0x00000001, AR5K_INI_WRITE },
+       /*{ AR5K_PHY(71), 0x0000092a, AR5K_INI_WRITE },*/ /* Old value */
+       { AR5K_PHY_MAX_RX_LEN,  0x00000c80, AR5K_INI_WRITE },
+       { AR5K_PHY_IQ,          0x05100000, AR5K_INI_WRITE },
+       { AR5K_PHY_WARM_RESET,  0x00000001, AR5K_INI_WRITE },
+       { AR5K_PHY_CTL,         0x00000004, AR5K_INI_WRITE },
+       { AR5K_PHY_TXPOWER_RATE1, 0x1e1f2022, AR5K_INI_WRITE },
+       { AR5K_PHY_TXPOWER_RATE2, 0x0a0b0c0d, AR5K_INI_WRITE },
+       { AR5K_PHY_TXPOWER_RATE_MAX, 0x0000003f, AR5K_INI_WRITE },
+       { AR5K_PHY(82),         0x9280b212, AR5K_INI_WRITE },
+       { AR5K_PHY_RADAR,       0x5d50e188, AR5K_INI_WRITE },
+       /*{ AR5K_PHY(86), 0x000000ff, AR5K_INI_WRITE },*/
+       { AR5K_PHY(87),         0x004b6a8e, AR5K_INI_WRITE },
+       { AR5K_PHY_NFTHRES,     0x000003ce, AR5K_INI_WRITE },
+       { AR5K_PHY_RESTART,     0x192fb515, AR5K_INI_WRITE },
+       { AR5K_PHY(94),         0x00000001, AR5K_INI_WRITE },
+       { AR5K_PHY_RFBUS_REQ,   0x00000000, AR5K_INI_WRITE },
+       /*{ AR5K_PHY(644), 0x0080a333, AR5K_INI_WRITE },*/ /* Old value */
+       /*{ AR5K_PHY(645), 0x00206c10, AR5K_INI_WRITE },*/ /* Old value */
+       { AR5K_PHY(644),        0x00806333, AR5K_INI_WRITE },
+       { AR5K_PHY(645),        0x00106c10, AR5K_INI_WRITE },
+       { AR5K_PHY(646),        0x009c4060, AR5K_INI_WRITE },
+       /* { AR5K_PHY(647), 0x1483800a, AR5K_INI_WRITE }, */
+       /* { AR5K_PHY(648), 0x01831061, AR5K_INI_WRITE }, */ /* Old value */
+       { AR5K_PHY(648),        0x018830c6, AR5K_INI_WRITE },
+       { AR5K_PHY(649),        0x00000400, AR5K_INI_WRITE },
+       /*{ AR5K_PHY(650), 0x000001b5, AR5K_INI_WRITE },*/
+       { AR5K_PHY(651),        0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHY_TXPOWER_RATE3, 0x20202020, AR5K_INI_WRITE },
+       { AR5K_PHY_TXPOWER_RATE2, 0x20202020, AR5K_INI_WRITE },
+       /*{ AR5K_PHY(655), 0x13c889af, AR5K_INI_WRITE },*/
+       { AR5K_PHY(656),        0x38490a20, AR5K_INI_WRITE },
+       { AR5K_PHY(657),        0x00007bb6, AR5K_INI_WRITE },
+       { AR5K_PHY(658),        0x0fff3ffc, AR5K_INI_WRITE },
+};
+
+/* Initial mode-specific settings for AR5212 (Written before ar5212_ini) */
+static const struct ath5k_ini_mode ar5212_ini_mode_start[] = {
+       { AR5K_QUEUE_DFS_LOCAL_IFS(0),
+       /*      a/XR       aTurbo         b        g (DYN)     gTurbo     */
+          { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
+       { AR5K_QUEUE_DFS_LOCAL_IFS(1),
+          { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
+       { AR5K_QUEUE_DFS_LOCAL_IFS(2),
+          { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
+       { AR5K_QUEUE_DFS_LOCAL_IFS(3),
+          { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
+       { AR5K_QUEUE_DFS_LOCAL_IFS(4),
+          { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
+       { AR5K_QUEUE_DFS_LOCAL_IFS(5),
+          { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
+       { AR5K_QUEUE_DFS_LOCAL_IFS(6),
+          { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
+       { AR5K_QUEUE_DFS_LOCAL_IFS(7),
+          { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
+       { AR5K_QUEUE_DFS_LOCAL_IFS(8),
+          { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
+       { AR5K_QUEUE_DFS_LOCAL_IFS(9),
+          { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
+       { AR5K_DCU_GBL_IFS_SIFS,
+          { 0x00000230, 0x000001e0, 0x000000b0, 0x00000160, 0x000001e0 } },
+       { AR5K_DCU_GBL_IFS_SLOT,
+          { 0x00000168, 0x000001e0, 0x000001b8, 0x0000018c, 0x000001e0 } },
+       { AR5K_DCU_GBL_IFS_EIFS,
+          { 0x00000e60, 0x00001180, 0x00001f1c, 0x00003e38, 0x00001180 } },
+       { AR5K_DCU_GBL_IFS_MISC,
+          { 0x0000a0e0, 0x00014068, 0x00005880, 0x0000b0e0, 0x00014068 } },
+       { AR5K_TIME_OUT,
+          { 0x03e803e8, 0x06e006e0, 0x04200420, 0x08400840, 0x06e006e0 } },
+       { AR5K_PHY_TURBO,
+          { 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000003 } },
+       { AR5K_PHY(8),
+          { 0x02020200, 0x02020200, 0x02010200, 0x02020200, 0x02020200 } },
+       { AR5K_PHY_RF_CTL2,
+          { 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e, 0x00000e0e } },
+       { AR5K_PHY_SETTLING,
+          { 0x1372161c, 0x13721c25, 0x13721722, 0x137216a2, 0x13721c25 } },
+       { AR5K_PHY_AGCCTL,
+          { 0x00009d10, 0x00009d10, 0x00009d18, 0x00009d18, 0x00009d18 } },
+       { AR5K_PHY_NF,
+          { 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 } },
+       { AR5K_PHY_WEAK_OFDM_HIGH_THR,
+          { 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190 } },
+       { AR5K_PHY(70),
+          { 0x000001b8, 0x000001b8, 0x00000084, 0x00000108, 0x000001b8 } },
+       { AR5K_PHY_OFDM_SELFCORR,
+          { 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05 } },
+       { 0xa230,
+          { 0x00000000, 0x00000000, 0x00000000, 0x00000108, 0x00000000 } },
+};
+
+/* Initial mode-specific settings for AR5212 + RF5111 (Written after ar5212_ini) */
+static const struct ath5k_ini_mode rf5111_ini_mode_end[] = {
+       { AR5K_TXCFG,
+       /*      a/XR       aTurbo         b        g (DYN)     gTurbo     */
+          { 0x00008015, 0x00008015, 0x00008015, 0x00008015, 0x00008015 } },
+       { AR5K_USEC_5211,
+          { 0x128d8fa7, 0x09880fcf, 0x04e00f95, 0x12e00fab, 0x09880fcf } },
+       { AR5K_PHY_RF_CTL3,
+          { 0x0a020001, 0x0a020001, 0x05010100, 0x0a020001, 0x0a020001 } },
+       { AR5K_PHY_RF_CTL4,
+          { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
+       { AR5K_PHY_PA_CTL,
+          { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } },
+       { AR5K_PHY_GAIN,
+          { 0x0018da5a, 0x0018da5a, 0x0018ca69, 0x0018ca69, 0x0018ca69 } },
+       { AR5K_PHY_DESIRED_SIZE,
+          { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } },
+       { AR5K_PHY_SIG,
+          { 0x7e800d2e, 0x7e800d2e, 0x7ee84d2e, 0x7ee84d2e, 0x7e800d2e } },
+       { AR5K_PHY_AGCCOARSE,
+          { 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137615e } },
+       { AR5K_PHY_WEAK_OFDM_LOW_THR,
+          { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb080, 0x050cb080 } },
+       { AR5K_PHY_RX_DELAY,
+          { 0x00002710, 0x00002710, 0x0000157c, 0x00002af8, 0x00002710 } },
+       { AR5K_PHY_FRAME_CTL_5211,
+          { 0xf7b81020, 0xf7b81020, 0xf7b80d20, 0xf7b81020, 0xf7b81020 } },
+       { AR5K_PHY_GAIN_2GHZ,
+          { 0x642c416a, 0x642c416a, 0x6440416a, 0x6440416a, 0x6440416a } },
+       { AR5K_PHY_CCK_RX_CTL_4,
+          { 0x1883800a, 0x1883800a, 0x1873800a, 0x1883800a, 0x1883800a } },
+};
+
+static const struct ath5k_ini rf5111_ini_common_end[] = {
+       { AR5K_DCU_FP,          0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHY_AGC,         0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHY_ADC_CTL,     0x00022ffe, AR5K_INI_WRITE },
+       { 0x983c,               0x00020100, AR5K_INI_WRITE },
+       { AR5K_PHY_GAIN_OFFSET, 0x1284613c, AR5K_INI_WRITE },
+       { AR5K_PHY_PAPD_PROBE,  0x00004883, AR5K_INI_WRITE },
+       { 0x9940,               0x00000004, AR5K_INI_WRITE },
+       { 0x9958,               0x000000ff, AR5K_INI_WRITE },
+       { 0x9974,               0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHY_SPENDING,    0x00000018, AR5K_INI_WRITE },
+       { AR5K_PHY_CCKTXCTL,    0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHY_CCK_CROSSCORR, 0xd03e6788, AR5K_INI_WRITE },
+       { AR5K_PHY_DAG_CCK_CTL, 0x000001b5, AR5K_INI_WRITE },
+       { 0xa23c,               0x13c889af, AR5K_INI_WRITE },
+};
+
+/* Initial mode-specific settings for AR5212 + RF5112 (Written after ar5212_ini) */
+static const struct ath5k_ini_mode rf5112_ini_mode_end[] = {
+       { AR5K_TXCFG,
+       /*      a/XR       aTurbo         b        g (DYN)     gTurbo     */
+          { 0x00008015, 0x00008015, 0x00008015, 0x00008015, 0x00008015 } },
+       { AR5K_USEC_5211,
+          { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
+       { AR5K_PHY_RF_CTL3,
+          { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } },
+       { AR5K_PHY_RF_CTL4,
+          { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
+       { AR5K_PHY_PA_CTL,
+          { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } },
+       { AR5K_PHY_GAIN,
+          { 0x0018da6d, 0x0018da6d, 0x0018ca75, 0x0018ca75, 0x0018ca75 } },
+       { AR5K_PHY_DESIRED_SIZE,
+          { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } },
+       { AR5K_PHY_SIG,
+          { 0x7e800d2e, 0x7e800d2e, 0x7ee80d2e, 0x7ee80d2e, 0x7ee80d2e } },
+       { AR5K_PHY_AGCCOARSE,
+          { 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e } },
+       { AR5K_PHY_WEAK_OFDM_LOW_THR,
+          { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
+       { AR5K_PHY_RX_DELAY,
+          { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
+       { AR5K_PHY_FRAME_CTL_5211,
+          { 0xf7b81020, 0xf7b81020, 0xf7b80d10, 0xf7b81010, 0xf7b81010 } },
+       { AR5K_PHY_CCKTXCTL,
+          { 0x00000000, 0x00000000, 0x00000008, 0x00000008, 0x00000008 } },
+       { AR5K_PHY_CCK_CROSSCORR,
+          { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
+       { AR5K_PHY_GAIN_2GHZ,
+          { 0x642c0140, 0x642c0140, 0x6442c160, 0x6442c160, 0x6442c160 } },
+       { AR5K_PHY_CCK_RX_CTL_4,
+          { 0x1883800a, 0x1883800a, 0x1873800a, 0x1883800a, 0x1883800a } },
+};
+
+static const struct ath5k_ini rf5112_ini_common_end[] = {
+       { AR5K_DCU_FP,          0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHY_AGC,         0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHY_ADC_CTL,     0x00022ffe, AR5K_INI_WRITE },
+       { 0x983c,               0x00020100, AR5K_INI_WRITE },
+       { AR5K_PHY_GAIN_OFFSET, 0x1284613c, AR5K_INI_WRITE },
+       { AR5K_PHY_PAPD_PROBE,  0x00004882, AR5K_INI_WRITE },
+       { 0x9940,               0x00000004, AR5K_INI_WRITE },
+       { 0x9958,               0x000000ff, AR5K_INI_WRITE },
+       { 0x9974,               0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHY_DAG_CCK_CTL, 0x000001b5, AR5K_INI_WRITE },
+       { 0xa23c,               0x13c889af, AR5K_INI_WRITE },
+};
+
+/* Initial mode-specific settings for RF5413/5414 (Written after ar5212_ini) */
+static const struct ath5k_ini_mode rf5413_ini_mode_end[] = {
+       { AR5K_TXCFG,
+       /*      a/XR       aTurbo         b        g (DYN)     gTurbo     */
+          { 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 } },
+       { AR5K_USEC_5211,
+          { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
+       { AR5K_PHY_RF_CTL3,
+          { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } },
+       { AR5K_PHY_RF_CTL4,
+          { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
+       { AR5K_PHY_PA_CTL,
+          { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } },
+       { AR5K_PHY_GAIN,
+          { 0x0018fa61, 0x0018fa61, 0x001a1a63, 0x001a1a63, 0x001a1a63 } },
+       { AR5K_PHY_DESIRED_SIZE,
+          { 0x0c98b4e0, 0x0c98b4e0, 0x0c98b0da, 0x0c98b0da, 0x0c98b0da } },
+       { AR5K_PHY_SIG,
+          { 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e } },
+       { AR5K_PHY_AGCCOARSE,
+          { 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e } },
+       { AR5K_PHY_WEAK_OFDM_LOW_THR,
+          { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
+       { AR5K_PHY_RX_DELAY,
+          { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
+       { AR5K_PHY_FRAME_CTL_5211,
+          { 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 } },
+       { AR5K_PHY_CCKTXCTL,
+          { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
+       { AR5K_PHY_CCK_CROSSCORR,
+          { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
+       { AR5K_PHY_GAIN_2GHZ,
+          { 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 } },
+       { AR5K_PHY_CCK_RX_CTL_4,
+          { 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a } },
+       { 0xa300,
+          { 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 } },
+       { 0xa304,
+          { 0x30032602, 0x30032602, 0x30032602, 0x30032602, 0x30032602 } },
+       { 0xa308,
+          { 0x48073e06, 0x48073e06, 0x48073e06, 0x48073e06, 0x48073e06 } },
+       { 0xa30c,
+          { 0x560b4c0a, 0x560b4c0a, 0x560b4c0a, 0x560b4c0a, 0x560b4c0a } },
+       { 0xa310,
+          { 0x641a600f, 0x641a600f, 0x641a600f, 0x641a600f, 0x641a600f } },
+       { 0xa314,
+          { 0x784f6e1b, 0x784f6e1b, 0x784f6e1b, 0x784f6e1b, 0x784f6e1b } },
+       { 0xa318,
+          { 0x868f7c5a, 0x868f7c5a, 0x868f7c5a, 0x868f7c5a, 0x868f7c5a } },
+       { 0xa31c,
+          { 0x90cf865b, 0x90cf865b, 0x8ecf865b, 0x8ecf865b, 0x8ecf865b } },
+       { 0xa320,
+          { 0x9d4f970f, 0x9d4f970f, 0x9b4f970f, 0x9b4f970f, 0x9b4f970f } },
+       { 0xa324,
+          { 0xa7cfa38f, 0xa7cfa38f, 0xa3cf9f8f, 0xa3cf9f8f, 0xa3cf9f8f } },
+       { 0xa328,
+          { 0xb55faf1f, 0xb55faf1f, 0xb35faf1f, 0xb35faf1f, 0xb35faf1f } },
+       { 0xa32c,
+          { 0xbddfb99f, 0xbddfb99f, 0xbbdfb99f, 0xbbdfb99f, 0xbbdfb99f } },
+       { 0xa330,
+          { 0xcb7fc53f, 0xcb7fc53f, 0xcb7fc73f, 0xcb7fc73f, 0xcb7fc73f } },
+       { 0xa334,
+          { 0xd5ffd1bf, 0xd5ffd1bf, 0xd3ffd1bf, 0xd3ffd1bf, 0xd3ffd1bf } },
+};
+
+static const struct ath5k_ini rf5413_ini_common_end[] = {
+       { AR5K_DCU_FP,          0x000003e0, AR5K_INI_WRITE },
+       { AR5K_5414_CBCFG,      0x00000010, AR5K_INI_WRITE },
+       { AR5K_SEQ_MASK,        0x0000000f, AR5K_INI_WRITE },
+       { 0x809c,               0x00000000, AR5K_INI_WRITE },
+       { 0x80a0,               0x00000000, AR5K_INI_WRITE },
+       { AR5K_MIC_QOS_CTL,     0x00000000, AR5K_INI_WRITE },
+       { AR5K_MIC_QOS_SEL,     0x00000000, AR5K_INI_WRITE },
+       { AR5K_MISC_MODE,       0x00000000, AR5K_INI_WRITE },
+       { AR5K_OFDM_FIL_CNT,    0x00000000, AR5K_INI_WRITE },
+       { AR5K_CCK_FIL_CNT,     0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHYERR_CNT1,     0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHYERR_CNT1_MASK, 0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHYERR_CNT2,     0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHYERR_CNT2_MASK, 0x00000000, AR5K_INI_WRITE },
+       { AR5K_TSF_THRES,       0x00000000, AR5K_INI_WRITE },
+       { 0x8140,               0x800003f9, AR5K_INI_WRITE },
+       { 0x8144,               0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHY_AGC,         0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHY_ADC_CTL,     0x0000a000, AR5K_INI_WRITE },
+       { 0x983c,               0x00200400, AR5K_INI_WRITE },
+       { AR5K_PHY_GAIN_OFFSET, 0x1284233c, AR5K_INI_WRITE },
+       { AR5K_PHY_SCR,         0x0000001f, AR5K_INI_WRITE },
+       { AR5K_PHY_SLMT,        0x00000080, AR5K_INI_WRITE },
+       { AR5K_PHY_SCAL,        0x0000000e, AR5K_INI_WRITE },
+       { 0x9958,               0x00081fff, AR5K_INI_WRITE },
+       { AR5K_PHY_TIMING_7,    0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHY_TIMING_8,    0x02800000, AR5K_INI_WRITE },
+       { AR5K_PHY_TIMING_11,   0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHY_HEAVY_CLIP_ENABLE, 0x00000000, AR5K_INI_WRITE },
+       { 0x99e4,               0xaaaaaaaa, AR5K_INI_WRITE },
+       { 0x99e8,               0x3c466478, AR5K_INI_WRITE },
+       { 0x99ec,               0x000000aa, AR5K_INI_WRITE },
+       { AR5K_PHY_SCLOCK,      0x0000000c, AR5K_INI_WRITE },
+       { AR5K_PHY_SDELAY,      0x000000ff, AR5K_INI_WRITE },
+       { AR5K_PHY_SPENDING,    0x00000014, AR5K_INI_WRITE },
+       { AR5K_PHY_DAG_CCK_CTL, 0x000009b5, AR5K_INI_WRITE },
+       { 0xa23c,               0x93c889af, AR5K_INI_WRITE },
+       { AR5K_PHY_FAST_ADC,    0x00000001, AR5K_INI_WRITE },
+       { 0xa250,               0x0000a000, AR5K_INI_WRITE },
+       { AR5K_PHY_BLUETOOTH,   0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHY_TPC_RG1,     0x0cc75380, AR5K_INI_WRITE },
+       { 0xa25c,               0x0f0f0f01, AR5K_INI_WRITE },
+       { 0xa260,               0x5f690f01, AR5K_INI_WRITE },
+       { 0xa264,               0x00418a11, AR5K_INI_WRITE },
+       { 0xa268,               0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHY_TPC_RG5,     0x0c30c16a, AR5K_INI_WRITE },
+       { 0xa270, 0x00820820, AR5K_INI_WRITE },
+       { 0xa274, 0x081b7caa, AR5K_INI_WRITE },
+       { 0xa278, 0x1ce739ce, AR5K_INI_WRITE },
+       { 0xa27c, 0x051701ce, AR5K_INI_WRITE },
+       { 0xa338, 0x00000000, AR5K_INI_WRITE },
+       { 0xa33c, 0x00000000, AR5K_INI_WRITE },
+       { 0xa340, 0x00000000, AR5K_INI_WRITE },
+       { 0xa344, 0x00000000, AR5K_INI_WRITE },
+       { 0xa348, 0x3fffffff, AR5K_INI_WRITE },
+       { 0xa34c, 0x3fffffff, AR5K_INI_WRITE },
+       { 0xa350, 0x3fffffff, AR5K_INI_WRITE },
+       { 0xa354, 0x0003ffff, AR5K_INI_WRITE },
+       { 0xa358, 0x79a8aa1f, AR5K_INI_WRITE },
+       { 0xa35c, 0x066c420f, AR5K_INI_WRITE },
+       { 0xa360, 0x0f282207, AR5K_INI_WRITE },
+       { 0xa364, 0x17601685, AR5K_INI_WRITE },
+       { 0xa368, 0x1f801104, AR5K_INI_WRITE },
+       { 0xa36c, 0x37a00c03, AR5K_INI_WRITE },
+       { 0xa370, 0x3fc40883, AR5K_INI_WRITE },
+       { 0xa374, 0x57c00803, AR5K_INI_WRITE },
+       { 0xa378, 0x5fd80682, AR5K_INI_WRITE },
+       { 0xa37c, 0x7fe00482, AR5K_INI_WRITE },
+       { 0xa380, 0x7f3c7bba, AR5K_INI_WRITE },
+       { 0xa384, 0xf3307ff0, AR5K_INI_WRITE },
+};
+
+/* Initial mode-specific settings for RF2413/2414 (Written after ar5212_ini) */
+/* XXX: a mode ? */
+static const struct ath5k_ini_mode rf2413_ini_mode_end[] = {
+       { AR5K_TXCFG,
+       /*      a/XR       aTurbo         b        g (DYN)     gTurbo     */
+          { 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 } },
+       { AR5K_USEC_5211,
+          { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
+       { AR5K_PHY_RF_CTL3,
+          { 0x0a020001, 0x0a020001, 0x05020000, 0x0a020001, 0x0a020001 } },
+       { AR5K_PHY_RF_CTL4,
+          { 0x00000e00, 0x00000e00, 0x00000e00, 0x00000e00, 0x00000e00 } },
+       { AR5K_PHY_PA_CTL,
+          { 0x00000002, 0x00000002, 0x0000000a, 0x0000000a, 0x0000000a } },
+       { AR5K_PHY_GAIN,
+          { 0x0018da6d, 0x0018da6d, 0x001a6a64, 0x001a6a64, 0x001a6a64 } },
+       { AR5K_PHY_DESIRED_SIZE,
+          { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b0da, 0x0c98b0da, 0x0de8b0da } },
+       { AR5K_PHY_SIG,
+          { 0x7e800d2e, 0x7e800d2e, 0x7ee80d2e, 0x7ec80d2e, 0x7e800d2e } },
+       { AR5K_PHY_AGCCOARSE,
+          { 0x3137665e, 0x3137665e, 0x3137665e, 0x3139605e, 0x3137665e } },
+       { AR5K_PHY_WEAK_OFDM_LOW_THR,
+          { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
+       { AR5K_PHY_RX_DELAY,
+          { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
+       { AR5K_PHY_FRAME_CTL_5211,
+          { 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 } },
+       { AR5K_PHY_CCKTXCTL,
+          { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
+       { AR5K_PHY_CCK_CROSSCORR,
+          { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
+       { AR5K_PHY_GAIN_2GHZ,
+          { 0x002c0140, 0x002c0140, 0x0042c140, 0x0042c140, 0x0042c140 } },
+       { AR5K_PHY_CCK_RX_CTL_4,
+          { 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a } },
+};
+
+static const struct ath5k_ini rf2413_ini_common_end[] = {
+       { AR5K_DCU_FP,          0x000003e0, AR5K_INI_WRITE },
+       { AR5K_SEQ_MASK,        0x0000000f, AR5K_INI_WRITE },
+       { AR5K_MIC_QOS_CTL,     0x00000000, AR5K_INI_WRITE },
+       { AR5K_MIC_QOS_SEL,     0x00000000, AR5K_INI_WRITE },
+       { AR5K_MISC_MODE,       0x00000000, AR5K_INI_WRITE },
+       { AR5K_OFDM_FIL_CNT,    0x00000000, AR5K_INI_WRITE },
+       { AR5K_CCK_FIL_CNT,     0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHYERR_CNT1,     0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHYERR_CNT1_MASK, 0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHYERR_CNT2,     0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHYERR_CNT2_MASK, 0x00000000, AR5K_INI_WRITE },
+       { AR5K_TSF_THRES,       0x00000000, AR5K_INI_WRITE },
+       { 0x8140,               0x800000a8, AR5K_INI_WRITE },
+       { 0x8144,               0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHY_AGC,         0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHY_ADC_CTL,     0x0000a000, AR5K_INI_WRITE },
+       { 0x983c,               0x00200400, AR5K_INI_WRITE },
+       { AR5K_PHY_GAIN_OFFSET, 0x1284233c, AR5K_INI_WRITE },
+       { AR5K_PHY_SCR,         0x0000001f, AR5K_INI_WRITE },
+       { AR5K_PHY_SLMT,        0x00000080, AR5K_INI_WRITE },
+       { AR5K_PHY_SCAL,        0x0000000e, AR5K_INI_WRITE },
+       { 0x9958,               0x000000ff, AR5K_INI_WRITE },
+       { AR5K_PHY_TIMING_7,    0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHY_TIMING_8,    0x02800000, AR5K_INI_WRITE },
+       { AR5K_PHY_TIMING_11,   0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHY_HEAVY_CLIP_ENABLE, 0x00000000, AR5K_INI_WRITE },
+       { 0x99e4,               0xaaaaaaaa, AR5K_INI_WRITE },
+       { 0x99e8,               0x3c466478, AR5K_INI_WRITE },
+       { 0x99ec,               0x000000aa, AR5K_INI_WRITE },
+       { AR5K_PHY_SCLOCK,      0x0000000c, AR5K_INI_WRITE },
+       { AR5K_PHY_SDELAY,      0x000000ff, AR5K_INI_WRITE },
+       { AR5K_PHY_SPENDING,    0x00000014, AR5K_INI_WRITE },
+       { AR5K_PHY_DAG_CCK_CTL, 0x000009b5, AR5K_INI_WRITE },
+       { 0xa23c,               0x93c889af, AR5K_INI_WRITE },
+       { AR5K_PHY_FAST_ADC,    0x00000001, AR5K_INI_WRITE },
+       { 0xa250,               0x0000a000, AR5K_INI_WRITE },
+       { AR5K_PHY_BLUETOOTH,   0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHY_TPC_RG1,     0x0cc75380, AR5K_INI_WRITE },
+       { 0xa25c,               0x0f0f0f01, AR5K_INI_WRITE },
+       { 0xa260,               0x5f690f01, AR5K_INI_WRITE },
+       { 0xa264,               0x00418a11, AR5K_INI_WRITE },
+       { 0xa268,               0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHY_TPC_RG5,     0x0c30c16a, AR5K_INI_WRITE },
+       { 0xa270, 0x00820820, AR5K_INI_WRITE },
+       { 0xa274, 0x001b7caa, AR5K_INI_WRITE },
+       { 0xa278, 0x1ce739ce, AR5K_INI_WRITE },
+       { 0xa27c, 0x051701ce, AR5K_INI_WRITE },
+       { 0xa300, 0x18010000, AR5K_INI_WRITE },
+       { 0xa304, 0x30032602, AR5K_INI_WRITE },
+       { 0xa308, 0x48073e06, AR5K_INI_WRITE },
+       { 0xa30c, 0x560b4c0a, AR5K_INI_WRITE },
+       { 0xa310, 0x641a600f, AR5K_INI_WRITE },
+       { 0xa314, 0x784f6e1b, AR5K_INI_WRITE },
+       { 0xa318, 0x868f7c5a, AR5K_INI_WRITE },
+       { 0xa31c, 0x8ecf865b, AR5K_INI_WRITE },
+       { 0xa320, 0x9d4f970f, AR5K_INI_WRITE },
+       { 0xa324, 0xa5cfa18f, AR5K_INI_WRITE },
+       { 0xa328, 0xb55faf1f, AR5K_INI_WRITE },
+       { 0xa32c, 0xbddfb99f, AR5K_INI_WRITE },
+       { 0xa330, 0xcd7fc73f, AR5K_INI_WRITE },
+       { 0xa334, 0xd5ffd1bf, AR5K_INI_WRITE },
+       { 0xa338, 0x00000000, AR5K_INI_WRITE },
+       { 0xa33c, 0x00000000, AR5K_INI_WRITE },
+       { 0xa340, 0x00000000, AR5K_INI_WRITE },
+       { 0xa344, 0x00000000, AR5K_INI_WRITE },
+       { 0xa348, 0x3fffffff, AR5K_INI_WRITE },
+       { 0xa34c, 0x3fffffff, AR5K_INI_WRITE },
+       { 0xa350, 0x3fffffff, AR5K_INI_WRITE },
+       { 0xa354, 0x0003ffff, AR5K_INI_WRITE },
+       { 0xa358, 0x79a8aa1f, AR5K_INI_WRITE },
+       { 0xa35c, 0x066c420f, AR5K_INI_WRITE },
+       { 0xa360, 0x0f282207, AR5K_INI_WRITE },
+       { 0xa364, 0x17601685, AR5K_INI_WRITE },
+       { 0xa368, 0x1f801104, AR5K_INI_WRITE },
+       { 0xa36c, 0x37a00c03, AR5K_INI_WRITE },
+       { 0xa370, 0x3fc40883, AR5K_INI_WRITE },
+       { 0xa374, 0x57c00803, AR5K_INI_WRITE },
+       { 0xa378, 0x5fd80682, AR5K_INI_WRITE },
+       { 0xa37c, 0x7fe00482, AR5K_INI_WRITE },
+       { 0xa380, 0x7f3c7bba, AR5K_INI_WRITE },
+       { 0xa384, 0xf3307ff0, AR5K_INI_WRITE },
+};
+
+/* Initial mode-specific settings for RF2425 (Written after ar5212_ini) */
+/* XXX: a mode ? */
+static const struct ath5k_ini_mode rf2425_ini_mode_end[] = {
+       { AR5K_TXCFG,
+       /*      a/XR       aTurbo         b        g (DYN)     gTurbo     */
+          { 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 } },
+       { AR5K_USEC_5211,
+          { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
+       { AR5K_PHY_TURBO,
+          { 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000001 } },
+       { AR5K_PHY_RF_CTL3,
+          { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } },
+       { AR5K_PHY_RF_CTL4,
+          { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
+       { AR5K_PHY_PA_CTL,
+          { 0x00000003, 0x00000003, 0x0000000b, 0x0000000b, 0x0000000b } },
+       { AR5K_PHY_SETTLING,
+          { 0x1372161c, 0x13721c25, 0x13721722, 0x13721422, 0x13721c25 } },
+       { AR5K_PHY_GAIN,
+          { 0x0018fa61, 0x0018fa61, 0x00199a65, 0x00199a65, 0x00199a65 } },
+       { AR5K_PHY_DESIRED_SIZE,
+          { 0x0c98b4e0, 0x0c98b4e0, 0x0c98b0da, 0x0c98b0da, 0x0c98b0da } },
+       { AR5K_PHY_SIG,
+          { 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e } },
+       { AR5K_PHY_AGCCOARSE,
+          { 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e } },
+       { AR5K_PHY_WEAK_OFDM_LOW_THR,
+          { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
+       { AR5K_PHY_RX_DELAY,
+          { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
+       { AR5K_PHY_FRAME_CTL_5211,
+          { 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 } },
+       { AR5K_PHY_CCKTXCTL,
+          { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
+       { AR5K_PHY_CCK_CROSSCORR,
+          { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
+       { AR5K_PHY_GAIN_2GHZ,
+          { 0x00000140, 0x00000140, 0x0052c140, 0x0052c140, 0x0052c140 } },
+       { AR5K_PHY_CCK_RX_CTL_4,
+          { 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a } },
+       { 0xa324,
+          { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
+       { 0xa328,
+          { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
+       { 0xa32c,
+          { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
+       { 0xa330,
+          { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
+       { 0xa334,
+          { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
+};
+
+static const struct ath5k_ini rf2425_ini_common_end[] = {
+       { AR5K_DCU_FP,          0x000003e0, AR5K_INI_WRITE },
+       { AR5K_SEQ_MASK,        0x0000000f, AR5K_INI_WRITE },
+       { 0x809c,               0x00000000, AR5K_INI_WRITE },
+       { 0x80a0,               0x00000000, AR5K_INI_WRITE },
+       { AR5K_MIC_QOS_CTL,     0x00000000, AR5K_INI_WRITE },
+       { AR5K_MIC_QOS_SEL,     0x00000000, AR5K_INI_WRITE },
+       { AR5K_MISC_MODE,       0x00000000, AR5K_INI_WRITE },
+       { AR5K_OFDM_FIL_CNT,    0x00000000, AR5K_INI_WRITE },
+       { AR5K_CCK_FIL_CNT,     0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHYERR_CNT1,     0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHYERR_CNT1_MASK, 0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHYERR_CNT2,     0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHYERR_CNT2_MASK, 0x00000000, AR5K_INI_WRITE },
+       { AR5K_TSF_THRES,       0x00000000, AR5K_INI_WRITE },
+       { 0x8140,               0x800003f9, AR5K_INI_WRITE },
+       { 0x8144,               0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHY_AGC,         0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHY_ADC_CTL,     0x0000a000, AR5K_INI_WRITE },
+       { 0x983c,               0x00200400, AR5K_INI_WRITE },
+       { AR5K_PHY_GAIN_OFFSET, 0x1284233c, AR5K_INI_WRITE },
+       { AR5K_PHY_SCR,         0x0000001f, AR5K_INI_WRITE },
+       { AR5K_PHY_SLMT,        0x00000080, AR5K_INI_WRITE },
+       { AR5K_PHY_SCAL,        0x0000000e, AR5K_INI_WRITE },
+       { 0x9958,               0x00081fff, AR5K_INI_WRITE },
+       { AR5K_PHY_TIMING_7,    0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHY_TIMING_8,    0x02800000, AR5K_INI_WRITE },
+       { AR5K_PHY_TIMING_11,   0x00000000, AR5K_INI_WRITE },
+       { 0x99dc,               0xfebadbe8, AR5K_INI_WRITE },
+       { AR5K_PHY_HEAVY_CLIP_ENABLE, 0x00000000, AR5K_INI_WRITE },
+       { 0x99e4,               0xaaaaaaaa, AR5K_INI_WRITE },
+       { 0x99e8,               0x3c466478, AR5K_INI_WRITE },
+       { 0x99ec,               0x000000aa, AR5K_INI_WRITE },
+       { AR5K_PHY_SCLOCK,      0x0000000c, AR5K_INI_WRITE },
+       { AR5K_PHY_SDELAY,      0x000000ff, AR5K_INI_WRITE },
+       { AR5K_PHY_SPENDING,    0x00000014, AR5K_INI_WRITE },
+       { AR5K_PHY_DAG_CCK_CTL, 0x000009b5, AR5K_INI_WRITE },
+       { AR5K_PHY_TXPOWER_RATE3, 0x20202020, AR5K_INI_WRITE },
+       { AR5K_PHY_TXPOWER_RATE4, 0x20202020, AR5K_INI_WRITE },
+       { 0xa23c,               0x93c889af, AR5K_INI_WRITE },
+       { AR5K_PHY_FAST_ADC,    0x00000001, AR5K_INI_WRITE },
+       { 0xa250,               0x0000a000, AR5K_INI_WRITE },
+       { AR5K_PHY_BLUETOOTH,   0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHY_TPC_RG1,     0x0cc75380, AR5K_INI_WRITE },
+       { 0xa25c,               0x0f0f0f01, AR5K_INI_WRITE },
+       { 0xa260,               0x5f690f01, AR5K_INI_WRITE },
+       { 0xa264,               0x00418a11, AR5K_INI_WRITE },
+       { 0xa268,               0x00000000, AR5K_INI_WRITE },
+       { AR5K_PHY_TPC_RG5,     0x0c30c166, AR5K_INI_WRITE },
+       { 0xa270, 0x00820820, AR5K_INI_WRITE },
+       { 0xa274, 0x081a3caa, AR5K_INI_WRITE },
+       { 0xa278, 0x1ce739ce, AR5K_INI_WRITE },
+       { 0xa27c, 0x051701ce, AR5K_INI_WRITE },
+       { 0xa300, 0x16010000, AR5K_INI_WRITE },
+       { 0xa304, 0x2c032402, AR5K_INI_WRITE },
+       { 0xa308, 0x48433e42, AR5K_INI_WRITE },
+       { 0xa30c, 0x5a0f500b, AR5K_INI_WRITE },
+       { 0xa310, 0x6c4b624a, AR5K_INI_WRITE },
+       { 0xa314, 0x7e8b748a, AR5K_INI_WRITE },
+       { 0xa318, 0x96cf8ccb, AR5K_INI_WRITE },
+       { 0xa31c, 0xa34f9d0f, AR5K_INI_WRITE },
+       { 0xa320, 0xa7cfa58f, AR5K_INI_WRITE },
+       { 0xa348, 0x3fffffff, AR5K_INI_WRITE },
+       { 0xa34c, 0x3fffffff, AR5K_INI_WRITE },
+       { 0xa350, 0x3fffffff, AR5K_INI_WRITE },
+       { 0xa354, 0x0003ffff, AR5K_INI_WRITE },
+       { 0xa358, 0x79a8aa1f, AR5K_INI_WRITE },
+       { 0xa35c, 0x066c420f, AR5K_INI_WRITE },
+       { 0xa360, 0x0f282207, AR5K_INI_WRITE },
+       { 0xa364, 0x17601685, AR5K_INI_WRITE },
+       { 0xa368, 0x1f801104, AR5K_INI_WRITE },
+       { 0xa36c, 0x37a00c03, AR5K_INI_WRITE },
+       { 0xa370, 0x3fc40883, AR5K_INI_WRITE },
+       { 0xa374, 0x57c00803, AR5K_INI_WRITE },
+       { 0xa378, 0x5fd80682, AR5K_INI_WRITE },
+       { 0xa37c, 0x7fe00482, AR5K_INI_WRITE },
+       { 0xa380, 0x7f3c7bba, AR5K_INI_WRITE },
+       { 0xa384, 0xf3307ff0, AR5K_INI_WRITE },
+};
+
+/*
+ * Initial BaseBand Gain settings for RF5111/5112 (AR5210 comes with
+ * RF5110 only so initial BB Gain settings are included in AR5K_AR5210_INI)
+ */
+
+/* RF5111 Initial BaseBand Gain settings */
+static const struct ath5k_ini rf5111_ini_bbgain[] = {
+       { AR5K_BB_GAIN(0), 0x00000000, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(1), 0x00000020, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(2), 0x00000010, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(3), 0x00000030, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(4), 0x00000008, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(5), 0x00000028, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(6), 0x00000004, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(7), 0x00000024, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(8), 0x00000014, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(9), 0x00000034, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(10), 0x0000000c, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(11), 0x0000002c, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(12), 0x00000002, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(13), 0x00000022, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(14), 0x00000012, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(15), 0x00000032, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(16), 0x0000000a, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(17), 0x0000002a, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(18), 0x00000006, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(19), 0x00000026, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(20), 0x00000016, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(21), 0x00000036, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(22), 0x0000000e, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(23), 0x0000002e, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(24), 0x00000001, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(25), 0x00000021, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(26), 0x00000011, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(27), 0x00000031, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(28), 0x00000009, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(29), 0x00000029, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(30), 0x00000005, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(31), 0x00000025, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(32), 0x00000015, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(33), 0x00000035, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(34), 0x0000000d, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(35), 0x0000002d, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(36), 0x00000003, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(37), 0x00000023, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(38), 0x00000013, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(39), 0x00000033, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(40), 0x0000000b, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(41), 0x0000002b, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(42), 0x0000002b, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(43), 0x0000002b, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(44), 0x0000002b, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(45), 0x0000002b, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(46), 0x0000002b, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(47), 0x0000002b, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(48), 0x0000002b, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(49), 0x0000002b, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(50), 0x0000002b, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(51), 0x0000002b, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(52), 0x0000002b, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(53), 0x0000002b, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(54), 0x0000002b, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(55), 0x0000002b, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(56), 0x0000002b, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(57), 0x0000002b, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(58), 0x0000002b, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(59), 0x0000002b, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(60), 0x0000002b, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(61), 0x0000002b, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(62), 0x00000002, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(63), 0x00000016, AR5K_INI_WRITE },
+};
+
+/* RF5112 Initial BaseBand Gain settings (Same for RF5413/5414+) */
+static const struct ath5k_ini rf5112_ini_bbgain[] = {
+       { AR5K_BB_GAIN(0), 0x00000000, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(1), 0x00000001, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(2), 0x00000002, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(3), 0x00000003, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(4), 0x00000004, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(5), 0x00000005, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(6), 0x00000008, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(7), 0x00000009, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(8), 0x0000000a, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(9), 0x0000000b, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(10), 0x0000000c, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(11), 0x0000000d, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(12), 0x00000010, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(13), 0x00000011, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(14), 0x00000012, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(15), 0x00000013, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(16), 0x00000014, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(17), 0x00000015, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(18), 0x00000018, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(19), 0x00000019, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(20), 0x0000001a, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(21), 0x0000001b, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(22), 0x0000001c, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(23), 0x0000001d, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(24), 0x00000020, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(25), 0x00000021, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(26), 0x00000022, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(27), 0x00000023, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(28), 0x00000024, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(29), 0x00000025, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(30), 0x00000028, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(31), 0x00000029, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(32), 0x0000002a, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(33), 0x0000002b, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(34), 0x0000002c, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(35), 0x0000002d, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(36), 0x00000030, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(37), 0x00000031, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(38), 0x00000032, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(39), 0x00000033, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(40), 0x00000034, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(41), 0x00000035, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(42), 0x00000035, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(43), 0x00000035, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(44), 0x00000035, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(45), 0x00000035, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(46), 0x00000035, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(47), 0x00000035, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(48), 0x00000035, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(49), 0x00000035, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(50), 0x00000035, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(51), 0x00000035, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(52), 0x00000035, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(53), 0x00000035, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(54), 0x00000035, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(55), 0x00000035, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(56), 0x00000035, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(57), 0x00000035, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(58), 0x00000035, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(59), 0x00000035, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(60), 0x00000035, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(61), 0x00000035, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(62), 0x00000010, AR5K_INI_WRITE },
+       { AR5K_BB_GAIN(63), 0x0000001a, AR5K_INI_WRITE },
+};
+
+
+/*
+ * Write initial register dump
+ */
+static void ath5k_hw_ini_registers(struct ath5k_hw *ah, unsigned int size,
+               const struct ath5k_ini *ini_regs, int change_channel)
+{
+       unsigned int i;
+
+       /* Write initial registers */
+       for (i = 0; i < size; i++) {
+               /* On channel change there is
+                * no need to mess with PCU */
+               if (change_channel &&
+                               ini_regs[i].ini_register >= AR5K_PCU_MIN &&
+                               ini_regs[i].ini_register <= AR5K_PCU_MAX)
+                       continue;
+
+               switch (ini_regs[i].ini_mode) {
+               case AR5K_INI_READ:
+                       /* Cleared on read */
+                       ath5k_hw_reg_read(ah, ini_regs[i].ini_register);
+                       break;
+               case AR5K_INI_WRITE:
+               default:
+                       AR5K_REG_WAIT(i);
+                       ath5k_hw_reg_write(ah, ini_regs[i].ini_value,
+                                       ini_regs[i].ini_register);
+               }
+       }
+}
+
+static void ath5k_hw_ini_mode_registers(struct ath5k_hw *ah,
+               unsigned int size, const struct ath5k_ini_mode *ini_mode,
+               u8 mode)
+{
+       unsigned int i;
+
+       for (i = 0; i < size; i++) {
+               AR5K_REG_WAIT(i);
+               ath5k_hw_reg_write(ah, ini_mode[i].mode_value[mode],
+                       (u32)ini_mode[i].mode_register);
+       }
+}
+
+int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, int change_channel)
+{
+       /*
+        * Write initial register settings
+        */
+
+       /* For AR5212 and combatible */
+       if (ah->ah_version == AR5K_AR5212) {
+
+               /* First set of mode-specific settings */
+               ath5k_hw_ini_mode_registers(ah,
+                       ARRAY_SIZE(ar5212_ini_mode_start),
+                       ar5212_ini_mode_start, mode);
+
+               /*
+                * Write initial settings common for all modes
+                */
+               ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5212_ini_common_start),
+                               ar5212_ini_common_start, change_channel);
+
+               /* Second set of mode-specific settings */
+               switch (ah->ah_radio) {
+               case AR5K_RF5111: