src/drivers/net/tg3.c

   1 /* $Id$
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002 Jeff Garzik (jgarzik@mandrakesoft.com)
   6  * Copyright (C) 2003 Eric Biederman (ebiederman@lnxi.com)  [etherboot port]
   7  */
   8
   9 /* 11-13-2003   timlegge        Fix Issue with NetGear GA302T
  10  * 11-18-2003   ebiederm        Generalize NetGear Fix to what the code was supposed to be.
  11  * 01-06-2005   Alf (Frederic Olivie) Add Dell bcm 5751 (0x1677) support
  12  * 04-15-2005   Martin Vogt Add Fujitsu Siemens Computer (FSC) 0x1734 bcm 5751 0x105d support
  13  */
  14
  15 #include "etherboot.h"
  16 #include "nic.h"
  17 #include <errno.h>
  18 #include <gpxe/pci.h>
  19 #include <gpxe/ethernet.h>
  20 #include "string.h"
  21 #include "tg3.h"
  22
  23 #define SUPPORT_COPPER_PHY  1
  24 #define SUPPORT_FIBER_PHY   1
  25 #define SUPPORT_LINK_REPORT 1
  26 #define SUPPORT_PARTNO_STR  1
  27 #define SUPPORT_PHY_STR     1
  28
  29 static struct tg3 tg3;
  30
  31 /* These numbers seem to be hard coded in the NIC firmware somehow.
  32  * You can't change the ring sizes, but you can change where you place
  33  * them in the NIC onboard memory.
  34  */
  35 #define TG3_RX_RING_SIZE                512
  36 #define TG3_DEF_RX_RING_PENDING         20      /* RX_RING_PENDING seems to be o.k. at 20 and 200 */
  37 #define TG3_RX_RCB_RING_SIZE    1024
  38
  39 /*      (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ? \
  40          512 : 1024) */
  41 #define TG3_TX_RING_SIZE                512
  42 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
  43
  44 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_RING_SIZE)
  45 #define TG3_RX_RCB_RING_BYTES   (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_RCB_RING_SIZE)
  46
  47 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * TG3_TX_RING_SIZE)
  48 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
  49 #define PREV_TX(N)              (((N) - 1) & (TG3_TX_RING_SIZE - 1))
  50
  51 #define RX_PKT_BUF_SZ           (1536 + 2 + 64)
  52
  53 struct eth_frame {
  54         uint8_t  dst_addr[ETH_ALEN];
  55         uint8_t  src_addr[ETH_ALEN];
  56         uint16_t type;
  57         uint8_t  data [ETH_FRAME_LEN - ETH_HLEN];
  58 };
  59
  60 struct bss {
  61         struct tg3_rx_buffer_desc rx_std[TG3_RX_RING_SIZE];
  62         struct tg3_rx_buffer_desc rx_rcb[TG3_RX_RCB_RING_SIZE];
  63         struct tg3_tx_buffer_desc tx_ring[TG3_TX_RING_SIZE];
  64         struct tg3_hw_status      hw_status;
  65         struct tg3_hw_stats       hw_stats;
  66         unsigned char             rx_bufs[TG3_DEF_RX_RING_PENDING][RX_PKT_BUF_SZ];
  67         struct eth_frame          tx_frame[2];
  68 } tg3_bss __shared;
  69
  70 /**
  71  * pci_save_state - save the PCI configuration space of a device before suspending
  72  * @dev: - PCI device that we're dealing with
  73  * @buffer: - buffer to hold config space context
  74  *
  75  * @buffer must be large enough to hold the entire PCI 2.2 config space
  76  * (>= 64 bytes).
  77  */
  78 static int pci_save_state(struct pci_device *dev, uint32_t *buffer)
  79 {
  80         int i;
  81         for (i = 0; i < 16; i++)
  82                 pci_read_config_dword(dev, i * 4,&buffer[i]);
  83         return 0;
  84 }
  85
  86 /**
  87  * pci_restore_state - Restore the saved state of a PCI device
  88  * @dev: - PCI device that we're dealing with
  89  * @buffer: - saved PCI config space
  90  *
  91  */
  92 static int pci_restore_state(struct pci_device *dev, uint32_t *buffer)
  93 {
  94         int i;
  95
  96         for (i = 0; i < 16; i++)
  97                 pci_write_config_dword(dev,i * 4, buffer[i]);
  98         return 0;
  99 }
 100
 101 static void tg3_write_indirect_reg32(uint32_t off, uint32_t val)
 102 {
 103         pci_write_config_dword(tg3.pdev, TG3PCI_REG_BASE_ADDR, off);
 104         pci_write_config_dword(tg3.pdev, TG3PCI_REG_DATA, val);
 105 }
 106
 107 #define tw32(reg,val)           tg3_write_indirect_reg32((reg),(val))
 108 #define tw32_mailbox(reg, val)  writel(((val) & 0xffffffff), tg3.regs + (reg))
 109 #define tw16(reg,val)           writew(((val) & 0xffff), tg3.regs + (reg))
 110 #define tw8(reg,val)            writeb(((val) & 0xff), tg3.regs + (reg))
 111 #define tr32(reg)               readl(tg3.regs + (reg))
 112 #define tr16(reg)               readw(tg3.regs + (reg))
 113 #define tr8(reg)                readb(tg3.regs + (reg))
 114
 115 static void tw32_carefully(uint32_t reg, uint32_t val)
 116 {
 117         tw32(reg, val);
 118         tr32(reg);
 119         udelay(100);
 120 }
 121
 122 static void tw32_mailbox2(uint32_t reg, uint32_t val)
 123 {
 124         tw32_mailbox(reg, val);
 125         tr32(reg);
 126 }
 127
 128 static void tg3_write_mem(uint32_t off, uint32_t val)
 129 {
 130         pci_write_config_dword(tg3.pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 131         pci_write_config_dword(tg3.pdev, TG3PCI_MEM_WIN_DATA, val);
 132
 133         /* Always leave this as zero. */
 134         pci_write_config_dword(tg3.pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 135 }
 136
 137 static void tg3_read_mem(uint32_t off, uint32_t *val)
 138 {
 139         pci_write_config_dword(tg3.pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 140         pci_read_config_dword(tg3.pdev, TG3PCI_MEM_WIN_DATA, val);
 141
 142         /* Always leave this as zero. */
 143         pci_write_config_dword(tg3.pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 144 }
 145
 146 static void tg3_disable_ints(struct tg3 *tp)
 147 {
 148         tw32(TG3PCI_MISC_HOST_CTRL,
 149              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 150         tw32_mailbox2(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
 151 }
 152
 153 static void tg3_switch_clocks(struct tg3 *tp)
 154 {
 155         uint32_t orig_clock_ctrl, clock_ctrl;
 156
 157         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 158
 159         orig_clock_ctrl = clock_ctrl;
 160         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN | CLOCK_CTRL_CLKRUN_OENABLE | 0x1f);
 161         tp->pci_clock_ctrl = clock_ctrl;
 162
 163         if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) &&
 164             (!((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
 165                && (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) &&
 166                 (orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE)!=0) {
 167                 tw32_carefully(TG3PCI_CLOCK_CTRL,
 168                         clock_ctrl | (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK));
 169                 tw32_carefully(TG3PCI_CLOCK_CTRL,
 170                         clock_ctrl | (CLOCK_CTRL_ALTCLK));
 171         }
 172         tw32_carefully(TG3PCI_CLOCK_CTRL, clock_ctrl);
 173 }
 174
 175 #define PHY_BUSY_LOOPS  5000
 176
 177 static int tg3_readphy(struct tg3 *tp, int reg, uint32_t *val)
 178 {
 179         uint32_t frame_val;
 180         int loops, ret;
 181
 182         tw32_carefully(MAC_MI_MODE, tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL);
 183
 184         *val = 0xffffffff;
 185
 186         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 187                       MI_COM_PHY_ADDR_MASK);
 188         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 189                       MI_COM_REG_ADDR_MASK);
 190         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 191
 192         tw32_carefully(MAC_MI_COM, frame_val);
 193
 194         loops = PHY_BUSY_LOOPS;
 195         while (loops-- > 0) {
 196                 udelay(10);
 197                 frame_val = tr32(MAC_MI_COM);
 198
 199                 if ((frame_val & MI_COM_BUSY) == 0) {
 200                         udelay(5);
 201                         frame_val = tr32(MAC_MI_COM);
 202                         break;
 203                 }
 204         }
 205
 206         ret = -EBUSY;
 207         if (loops > 0) {
 208                 *val = frame_val & MI_COM_DATA_MASK;
 209                 ret = 0;
 210         }
 211
 212         tw32_carefully(MAC_MI_MODE, tp->mi_mode);
 213
 214         return ret;
 215 }
 216
 217 static int tg3_writephy(struct tg3 *tp, int reg, uint32_t val)
 218 {
 219         uint32_t frame_val;
 220         int loops, ret;
 221
 222         tw32_carefully(MAC_MI_MODE, tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL);
 223
 224         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 225                       MI_COM_PHY_ADDR_MASK);
 226         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 227                       MI_COM_REG_ADDR_MASK);
 228         frame_val |= (val & MI_COM_DATA_MASK);
 229         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 230
 231         tw32_carefully(MAC_MI_COM, frame_val);
 232
 233         loops = PHY_BUSY_LOOPS;
 234         while (loops-- > 0) {
 235                 udelay(10);
 236                 frame_val = tr32(MAC_MI_COM);
 237                 if ((frame_val & MI_COM_BUSY) == 0) {
 238                         udelay(5);
 239                         frame_val = tr32(MAC_MI_COM);
 240                         break;
 241                 }
 242         }
 243
 244         ret = -EBUSY;
 245         if (loops > 0)
 246                 ret = 0;
 247
 248         tw32_carefully(MAC_MI_MODE, tp->mi_mode);
 249
 250         return ret;
 251 }
 252
 253 static int tg3_writedsp(struct tg3 *tp, uint16_t addr, uint16_t val)
 254 {
 255         int err;
 256         err  = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, addr);
 257         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
 258         return err;
 259 }
 260
 261
 262 static void tg3_phy_set_wirespeed(struct tg3 *tp)
 263 {
 264         uint32_t val;
 265
 266         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
 267                 return;
 268
 269         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007);
 270         tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
 271         tg3_writephy(tp, MII_TG3_AUX_CTRL, (val | (1 << 15) | (1 << 4)));
 272 }
 273
 274 static int tg3_bmcr_reset(struct tg3 *tp)
 275 {
 276         uint32_t phy_control;
 277         int limit, err;
 278
 279         /* OK, reset it, and poll the BMCR_RESET bit until it
 280          * clears or we time out.
 281          */
 282         phy_control = BMCR_RESET;
 283         err = tg3_writephy(tp, MII_BMCR, phy_control);
 284         if (err != 0)
 285                 return -EBUSY;
 286
 287         limit = 5000;
 288         while (limit--) {
 289                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 290                 if (err != 0)
 291                         return -EBUSY;
 292
 293                 if ((phy_control & BMCR_RESET) == 0) {
 294                         udelay(40);
 295                         break;
 296                 }
 297                 udelay(10);
 298         }
 299         if (limit <= 0)
 300                 return -EBUSY;
 301
 302         return 0;
 303 }
 304
 305 static int tg3_wait_macro_done(struct tg3 *tp)
 306 {
 307         int limit = 100;
 308
 309         while (limit--) {
 310                 uint32_t tmp32;
 311
 312                 tg3_readphy(tp, 0x16, &tmp32);
 313                 if ((tmp32 & 0x1000) == 0)
 314                         break;
 315         }
 316         if (limit <= 0)
 317                 return -EBUSY;
 318
 319         return 0;
 320 }
 321
 322 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
 323 {
 324         static const uint32_t test_pat[4][6] = {
 325         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
 326         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
 327         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
 328         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
 329         };
 330         int chan;
 331
 332         for (chan = 0; chan < 4; chan++) {
 333                 int i;
 334
 335                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 336                         (chan * 0x2000) | 0x0200);
 337                 tg3_writephy(tp, 0x16, 0x0002);
 338
 339                 for (i = 0; i < 6; i++)
 340                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
 341                                 test_pat[chan][i]);
 342
 343                 tg3_writephy(tp, 0x16, 0x0202);
 344                 if (tg3_wait_macro_done(tp)) {
 345                         *resetp = 1;
 346                         return -EBUSY;
 347                 }
 348
 349                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 350                              (chan * 0x2000) | 0x0200);
 351                 tg3_writephy(tp, 0x16, 0x0082);
 352                 if (tg3_wait_macro_done(tp)) {
 353                         *resetp = 1;
 354                         return -EBUSY;
 355                 }
 356
 357                 tg3_writephy(tp, 0x16, 0x0802);
 358                 if (tg3_wait_macro_done(tp)) {
 359                         *resetp = 1;
 360                         return -EBUSY;
 361                 }
 362
 363                 for (i = 0; i < 6; i += 2) {
 364                         uint32_t low, high;
 365
 366                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low);
 367                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high);
 368                         if (tg3_wait_macro_done(tp)) {
 369                                 *resetp = 1;
 370                                 return -EBUSY;
 371                         }
 372                         low &= 0x7fff;
 373                         high &= 0x000f;
 374                         if (low != test_pat[chan][i] ||
 375                             high != test_pat[chan][i+1]) {
 376                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
 377                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
 378                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
 379
 380                                 return -EBUSY;
 381                         }
 382                 }
 383         }
 384
 385         return 0;
 386 }
 387
 388 static int tg3_phy_reset_chanpat(struct tg3 *tp)
 389 {
 390         int chan;
 391
 392         for (chan = 0; chan < 4; chan++) {
 393                 int i;
 394
 395                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 396                              (chan * 0x2000) | 0x0200);
 397                 tg3_writephy(tp, 0x16, 0x0002);
 398                 for (i = 0; i < 6; i++)
 399                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
 400                 tg3_writephy(tp, 0x16, 0x0202);
 401                 if (tg3_wait_macro_done(tp))
 402                         return -EBUSY;
 403         }
 404
 405         return 0;
 406 }
 407
 408 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
 409 {
 410         uint32_t reg32, phy9_orig;
 411         int retries, do_phy_reset, err;
 412
 413         retries = 10;
 414         do_phy_reset = 1;
 415         do {
 416                 if (do_phy_reset) {
 417                         err = tg3_bmcr_reset(tp);
 418                         if (err)
 419                                 return err;
 420                         do_phy_reset = 0;
 421                 }
 422
 423                 /* Disable transmitter and interrupt.  */
 424                 tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32);
 425                 reg32 |= 0x3000;
 426                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 427
 428                 /* Set full-duplex, 1000 mbps.  */
 429                 tg3_writephy(tp, MII_BMCR,
 430                         BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
 431
 432                 /* Set to master mode.  */
 433                 tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig);
 434                 tg3_writephy(tp, MII_TG3_CTRL,
 435                         (MII_TG3_CTRL_AS_MASTER |
 436                                 MII_TG3_CTRL_ENABLE_AS_MASTER));
 437
 438                 /* Enable SM_DSP_CLOCK and 6dB.  */
 439                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 440
 441                 /* Block the PHY control access.  */
 442                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 443                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
 444
 445                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
 446                 if (!err)
 447                         break;
 448         } while (--retries);
 449
 450         err = tg3_phy_reset_chanpat(tp);
 451         if (err)
 452                 return err;
 453
 454         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 455         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
 456
 457         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
 458         tg3_writephy(tp, 0x16, 0x0000);
 459
 460         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 461
 462         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
 463
 464         tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32);
 465         reg32 &= ~0x3000;
 466         tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 467
 468         return err;
 469 }
 470
 471 /* This will reset the tigon3 PHY if there is no valid
 472  * link.
 473  */
 474 static int tg3_phy_reset(struct tg3 *tp)
 475 {
 476         uint32_t phy_status;
 477         int err;
 478
 479         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
 480         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
 481         if (err != 0)
 482                 return -EBUSY;
 483
 484         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) ||
 485                 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
 486                 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
 487                 err = tg3_phy_reset_5703_4_5(tp);
 488                 if (err)
 489                         return err;
 490                 goto out;
 491         }
 492         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
 493           // Taken from Broadcom's source code
 494           tg3_writephy(tp, 0x18, 0x0c00);
 495           tg3_writephy(tp, 0x17, 0x000a);
 496           tg3_writephy(tp, 0x15, 0x310b);
 497           tg3_writephy(tp, 0x17, 0x201f);
 498           tg3_writephy(tp, 0x15, 0x9506);
 499           tg3_writephy(tp, 0x17, 0x401f);
 500           tg3_writephy(tp, 0x15, 0x14e2);
 501           tg3_writephy(tp, 0x18, 0x0400);
 502         }
 503         err = tg3_bmcr_reset(tp);
 504         if (err)
 505                 return err;
 506  out:
 507         tg3_phy_set_wirespeed(tp);
 508         return 0;
 509 }
 510
 511 static void tg3_set_power_state_0(struct tg3 *tp)
 512 {
 513         uint16_t power_control;
 514         int pm = tp->pm_cap;
 515
 516         /* Make sure register accesses (indirect or otherwise)
 517          * will function correctly.
 518          */
 519         pci_write_config_dword(tp->pdev,  TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
 520
 521         pci_read_config_word(tp->pdev, pm + PCI_PM_CTRL, &power_control);
 522
 523         power_control |= PCI_PM_CTRL_PME_STATUS;
 524         power_control &= ~(PCI_PM_CTRL_STATE_MASK);
 525         power_control |= 0;
 526         pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
 527
 528         tw32_carefully(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
 529
 530         return;
 531 }
 532
 533
 534 #if SUPPORT_LINK_REPORT
 535 static void tg3_link_report(struct tg3 *tp)
 536 {
 537         if (!tp->carrier_ok) {
 538                 printf("Link is down.\n");
 539         } else {
 540                 printf("Link is up at %d Mbps, %s duplex. %s %s %s\n",
 541                         (tp->link_config.active_speed == SPEED_1000 ?
 542                                1000 :
 543                         (tp->link_config.active_speed == SPEED_100 ?
 544                                 100 : 10)),
 545                         (tp->link_config.active_duplex == DUPLEX_FULL ?
 546                                 "full" : "half"),
 547                         (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "TX" : "",
 548                         (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "RX" : "",
 549                         (tp->tg3_flags & (TG3_FLAG_TX_PAUSE |TG3_FLAG_RX_PAUSE)) ? "flow control" : "");
 550         }
 551 }
 552 #else
 553 #define tg3_link_report(tp)
 554 #endif
 555
 556 static void tg3_setup_flow_control(struct tg3 *tp, uint32_t local_adv, uint32_t remote_adv)
 557 {
 558         uint32_t new_tg3_flags = 0;
 559
 560         if (local_adv & ADVERTISE_PAUSE_CAP) {
 561                 if (local_adv & ADVERTISE_PAUSE_ASYM) {
 562                         if (remote_adv & LPA_PAUSE_CAP)
 563                                 new_tg3_flags |=
 564                                         (TG3_FLAG_RX_PAUSE |
 565                                          TG3_FLAG_TX_PAUSE);
 566                         else if (remote_adv & LPA_PAUSE_ASYM)
 567                                 new_tg3_flags |=
 568                                         (TG3_FLAG_RX_PAUSE);
 569                 } else {
 570                         if (remote_adv & LPA_PAUSE_CAP)
 571                                 new_tg3_flags |=
 572                                         (TG3_FLAG_RX_PAUSE |
 573                                          TG3_FLAG_TX_PAUSE);
 574                 }
 575         } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
 576                 if ((remote_adv & LPA_PAUSE_CAP) &&
 577                     (remote_adv & LPA_PAUSE_ASYM))
 578                         new_tg3_flags |= TG3_FLAG_TX_PAUSE;
 579         }
 580
 581         tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
 582         tp->tg3_flags |= new_tg3_flags;
 583
 584         if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
 585                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
 586         else
 587                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
 588
 589         if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
 590                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
 591         else
 592                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
 593 }
 594
 595 #if SUPPORT_COPPER_PHY
 596 static void tg3_aux_stat_to_speed_duplex(
 597         struct tg3 *tp __unused, uint32_t val, uint8_t *speed, uint8_t *duplex)
 598 {
 599         static const uint8_t map[] = {
 600                 [0] = (SPEED_INVALID << 2) | DUPLEX_INVALID,
 601                 [MII_TG3_AUX_STAT_10HALF >> 8]   = (SPEED_10 << 2) | DUPLEX_HALF,
 602                 [MII_TG3_AUX_STAT_10FULL >> 8]   = (SPEED_10 << 2) | DUPLEX_FULL,
 603                 [MII_TG3_AUX_STAT_100HALF >> 8]  = (SPEED_100 << 2) | DUPLEX_HALF,
 604                 [MII_TG3_AUX_STAT_100_4 >> 8] = (SPEED_INVALID << 2) | DUPLEX_INVALID,
 605                 [MII_TG3_AUX_STAT_100FULL >> 8]  = (SPEED_100 << 2) | DUPLEX_FULL,
 606                 [MII_TG3_AUX_STAT_1000HALF >> 8] = (SPEED_1000 << 2) | DUPLEX_HALF,
 607                 [MII_TG3_AUX_STAT_1000FULL >> 8] = (SPEED_1000 << 2) | DUPLEX_FULL,
 608         };
 609         uint8_t result;
 610         result = map[(val & MII_TG3_AUX_STAT_SPDMASK) >> 8];
 611         *speed = result >> 2;
 612         *duplex = result & 3;
 613 }
 614
 615 static int tg3_phy_copper_begin(struct tg3 *tp)
 616 {
 617         uint32_t new_adv;
 618
 619         tp->link_config.advertising =
 620                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
 621                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
 622                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
 623                         ADVERTISED_Autoneg | ADVERTISED_MII);
 624
 625         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY) {
 626                 tp->link_config.advertising &=
 627                         ~(ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
 628         }
 629
 630         new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
 631         if (tp->link_config.advertising & ADVERTISED_10baseT_Half) {
 632                 new_adv |= ADVERTISE_10HALF;
 633         }
 634         if (tp->link_config.advertising & ADVERTISED_10baseT_Full) {
 635                 new_adv |= ADVERTISE_10FULL;
 636         }
 637         if (tp->link_config.advertising & ADVERTISED_100baseT_Half) {
 638                 new_adv |= ADVERTISE_100HALF;
 639         }
 640         if (tp->link_config.advertising & ADVERTISED_100baseT_Full) {
 641                 new_adv |= ADVERTISE_100FULL;
 642         }
 643         tg3_writephy(tp, MII_ADVERTISE, new_adv);
 644
 645         if (tp->link_config.advertising &
 646                 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
 647                 new_adv = 0;
 648                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half) {
 649                         new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
 650                 }
 651                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full) {
 652                         new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
 653                 }
 654                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
 655                         (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
 656                                 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)) {
 657                         new_adv |= (MII_TG3_CTRL_AS_MASTER |
 658                                 MII_TG3_CTRL_ENABLE_AS_MASTER);
 659                 }
 660                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
 661         } else {
 662                 tg3_writephy(tp, MII_TG3_CTRL, 0);
 663         }
 664
 665         tg3_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
 666
 667         return 0;
 668 }
 669
 670 static int tg3_init_5401phy_dsp(struct tg3 *tp)
 671 {
 672         int err;
 673
 674         /* Turn off tap power management. */
 675         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c20);
 676
 677         err |= tg3_writedsp(tp, 0x0012, 0x1804);
 678         err |= tg3_writedsp(tp, 0x0013, 0x1204);
 679         err |= tg3_writedsp(tp, 0x8006, 0x0132);
 680         err |= tg3_writedsp(tp, 0x8006, 0x0232);
 681         err |= tg3_writedsp(tp, 0x201f, 0x0a20);
 682
 683         udelay(40);
 684
 685         return err;
 686 }
 687
 688 static int tg3_setup_copper_phy(struct tg3 *tp)
 689 {
 690         int current_link_up;
 691         uint32_t bmsr, dummy;
 692         int i, err;
 693
 694         tw32_carefully(MAC_STATUS,
 695                 (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED
 696                  | MAC_STATUS_LNKSTATE_CHANGED));
 697
 698         tp->mi_mode = MAC_MI_MODE_BASE;
 699         tw32_carefully(MAC_MI_MODE, tp->mi_mode);
 700
 701         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
 702
 703         /* Some third-party PHYs need to be reset on link going
 704          * down.
 705          */
 706         if (    (       (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) ||
 707                         (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
 708                         (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)) &&
 709                 (tp->carrier_ok)) {
 710                 tg3_readphy(tp, MII_BMSR, &bmsr);
 711                 tg3_readphy(tp, MII_BMSR, &bmsr);
 712                 if (!(bmsr & BMSR_LSTATUS))
 713                         tg3_phy_reset(tp);
 714         }
 715
 716         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
 717                 tg3_readphy(tp, MII_BMSR, &bmsr);
 718                 tg3_readphy(tp, MII_BMSR, &bmsr);
 719
 720                 if (!(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
 721                         bmsr = 0;
 722
 723                 if (!(bmsr & BMSR_LSTATUS)) {
 724                         err = tg3_init_5401phy_dsp(tp);
 725                         if (err)
 726                                 return err;
 727
 728                         tg3_readphy(tp, MII_BMSR, &bmsr);
 729                         for (i = 0; i < 1000; i++) {
 730                                 udelay(10);
 731                                 tg3_readphy(tp, MII_BMSR, &bmsr);
 732                                 if (bmsr & BMSR_LSTATUS) {
 733                                         udelay(40);
 734                                         break;
 735                                 }
 736                         }
 737
 738                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
 739                             !(bmsr & BMSR_LSTATUS) &&
 740                             tp->link_config.active_speed == SPEED_1000) {
 741                                 err = tg3_phy_reset(tp);
 742                                 if (!err)
 743                                         err = tg3_init_5401phy_dsp(tp);
 744                                 if (err)
 745                                         return err;
 746                         }
 747                 }
 748         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
 749                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
 750                 /* 5701 {A0,B0} CRC bug workaround */
 751                 tg3_writephy(tp, 0x15, 0x0a75);
 752                 tg3_writephy(tp, 0x1c, 0x8c68);
 753                 tg3_writephy(tp, 0x1c, 0x8d68);
 754                 tg3_writephy(tp, 0x1c, 0x8c68);
 755         }
 756
 757         /* Clear pending interrupts... */
 758         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
 759         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
 760
 761         tg3_writephy(tp, MII_TG3_IMASK, ~0);
 762
 763         if (tp->led_mode == led_mode_three_link)
 764                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
 765                              MII_TG3_EXT_CTRL_LNK3_LED_MODE);
 766         else
 767                 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
 768
 769         current_link_up = 0;
 770
 771         tg3_readphy(tp, MII_BMSR, &bmsr);
 772         tg3_readphy(tp, MII_BMSR, &bmsr);
 773
 774         if (bmsr & BMSR_LSTATUS) {
 775                 uint32_t aux_stat, bmcr;
 776
 777                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
 778                 for (i = 0; i < 2000; i++) {
 779                         udelay(10);
 780                         tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
 781                         if (aux_stat)
 782                                 break;
 783                 }
 784
 785                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
 786                         &tp->link_config.active_speed,
 787                         &tp->link_config.active_duplex);
 788                 tg3_readphy(tp, MII_BMCR, &bmcr);
 789                 tg3_readphy(tp, MII_BMCR, &bmcr);
 790                 if (bmcr & BMCR_ANENABLE) {
 791                         uint32_t gig_ctrl;
 792
 793                         current_link_up = 1;
 794
 795                         /* Force autoneg restart if we are exiting
 796                          * low power mode.
 797                          */
 798                         tg3_readphy(tp, MII_TG3_CTRL, &gig_ctrl);
 799                         if (!(gig_ctrl & (MII_TG3_CTRL_ADV_1000_HALF |
 800                                       MII_TG3_CTRL_ADV_1000_FULL))) {
 801                                 current_link_up = 0;
 802                         }
 803                 } else {
 804                         current_link_up = 0;
 805                 }
 806         }
 807
 808         if (current_link_up == 1 &&
 809                 (tp->link_config.active_duplex == DUPLEX_FULL)) {
 810                 uint32_t local_adv, remote_adv;
 811
 812                 tg3_readphy(tp, MII_ADVERTISE, &local_adv);
 813                 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
 814
 815                 tg3_readphy(tp, MII_LPA, &remote_adv);
 816                 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
 817
 818                 /* If we are not advertising full pause capability,
 819                  * something is wrong.  Bring the link down and reconfigure.
 820                  */
 821                 if (local_adv != ADVERTISE_PAUSE_CAP) {
 822                         current_link_up = 0;
 823                 } else {
 824                         tg3_setup_flow_control(tp, local_adv, remote_adv);
 825                 }
 826         }
 827
 828         if (current_link_up == 0) {
 829                 uint32_t tmp;
 830
 831                 tg3_phy_copper_begin(tp);
 832
 833                 tg3_readphy(tp, MII_BMSR, &tmp);
 834                 tg3_readphy(tp, MII_BMSR, &tmp);
 835                 if (tmp & BMSR_LSTATUS)
 836                         current_link_up = 1;
 837         }
 838
 839         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
 840         if (current_link_up == 1) {
 841                 if (tp->link_config.active_speed == SPEED_100 ||
 842                     tp->link_config.active_speed == SPEED_10)
 843                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
 844                 else
 845                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
 846         } else
 847                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
 848
 849         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
 850         if (tp->link_config.active_duplex == DUPLEX_HALF)
 851                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
 852
 853         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
 854         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
 855                 if ((tp->led_mode == led_mode_link10) ||
 856                     (current_link_up == 1 &&
 857                      tp->link_config.active_speed == SPEED_10))
 858                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
 859         } else {
 860                 if (current_link_up == 1)
 861                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
 862                 tw32(MAC_LED_CTRL, LED_CTRL_PHY_MODE_1);
 863         }
 864
 865         /* ??? Without this setting Netgear GA302T PHY does not
 866          * ??? send/receive packets...
 867          * With this other PHYs cannot bring up the link
 868          */
 869         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
 870                 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
 871                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
 872                 tw32_carefully(MAC_MI_MODE, tp->mi_mode);
 873         }
 874
 875         tw32_carefully(MAC_MODE, tp->mac_mode);
 876
 877         /* Link change polled. */
 878         tw32_carefully(MAC_EVENT, 0);
 879
 880         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
 881             current_link_up == 1 &&
 882             tp->link_config.active_speed == SPEED_1000 &&
 883             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
 884              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
 885                 udelay(120);
 886                 tw32_carefully(MAC_STATUS,
 887                         (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED));
 888                 tg3_write_mem(
 889                               NIC_SRAM_FIRMWARE_MBOX,
 890                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
 891         }
 892
 893         if (current_link_up != tp->carrier_ok) {
 894                 tp->carrier_ok = current_link_up;
 895                 tg3_link_report(tp);
 896         }
 897
 898         return 0;
 899 }
 900 #else
 901 #define tg3_setup_copper_phy(TP) (-EINVAL)
 902 #endif /* SUPPORT_COPPER_PHY */
 903
 904 #if SUPPORT_FIBER_PHY
 905 struct tg3_fiber_aneginfo {
 906         int state;
 907 #define ANEG_STATE_UNKNOWN              0
 908 #define ANEG_STATE_AN_ENABLE            1
 909 #define ANEG_STATE_RESTART_INIT         2
 910 #define ANEG_STATE_RESTART              3
 911 #define ANEG_STATE_DISABLE_LINK_OK      4
 912 #define ANEG_STATE_ABILITY_DETECT_INIT  5
 913 #define ANEG_STATE_ABILITY_DETECT       6
 914 #define ANEG_STATE_ACK_DETECT_INIT      7
 915 #define ANEG_STATE_ACK_DETECT           8
 916 #define ANEG_STATE_COMPLETE_ACK_INIT    9
 917 #define ANEG_STATE_COMPLETE_ACK         10
 918 #define ANEG_STATE_IDLE_DETECT_INIT     11
 919 #define ANEG_STATE_IDLE_DETECT          12
 920 #define ANEG_STATE_LINK_OK              13
 921 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
 922 #define ANEG_STATE_NEXT_PAGE_WAIT       15
 923
 924         uint32_t flags;
 925 #define MR_AN_ENABLE            0x00000001
 926 #define MR_RESTART_AN           0x00000002
 927 #define MR_AN_COMPLETE          0x00000004
 928 #define MR_PAGE_RX              0x00000008
 929 #define MR_NP_LOADED            0x00000010
 930 #define MR_TOGGLE_TX            0x00000020
 931 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
 932 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
 933 #define MR_LP_ADV_SYM_PAUSE     0x00000100
 934 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
 935 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
 936 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
 937 #define MR_LP_ADV_NEXT_PAGE     0x00001000
 938 #define MR_TOGGLE_RX            0x00002000
 939 #define MR_NP_RX                0x00004000
 940
 941 #define MR_LINK_OK              0x80000000
 942
 943         unsigned long link_time, cur_time;
 944
 945         uint32_t ability_match_cfg;
 946         int ability_match_count;
 947
 948         char ability_match, idle_match, ack_match;
 949
 950         uint32_t txconfig, rxconfig;
 951 #define ANEG_CFG_NP             0x00000080
 952 #define ANEG_CFG_ACK            0x00000040
 953 #define ANEG_CFG_RF2            0x00000020
 954 #define ANEG_CFG_RF1            0x00000010
 955 #define ANEG_CFG_PS2            0x00000001
 956 #define ANEG_CFG_PS1            0x00008000
 957 #define ANEG_CFG_HD             0x00004000
 958 #define ANEG_CFG_FD             0x00002000
 959 #define ANEG_CFG_INVAL          0x00001f06
 960
 961 };
 962 #define ANEG_OK         0
 963 #define ANEG_DONE       1
 964 #define ANEG_TIMER_ENAB 2
 965 #define ANEG_FAILED     -1
 966
 967 #define ANEG_STATE_SETTLE_TIME  10000
 968
 969 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
 970                                    struct tg3_fiber_aneginfo *ap)
 971 {
 972         unsigned long delta;
 973         uint32_t rx_cfg_reg;
 974         int ret;
 975
 976         if (ap->state == ANEG_STATE_UNKNOWN) {
 977                 ap->rxconfig = 0;
 978                 ap->link_time = 0;
 979                 ap->cur_time = 0;
 980                 ap->ability_match_cfg = 0;
 981                 ap->ability_match_count = 0;
 982                 ap->ability_match = 0;
 983                 ap->idle_match = 0;
 984                 ap->ack_match = 0;
 985         }
 986         ap->cur_time++;
 987
 988         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
 989                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
 990
 991                 if (rx_cfg_reg != ap->ability_match_cfg) {
 992                         ap->ability_match_cfg = rx_cfg_reg;
 993                         ap->ability_match = 0;
 994                         ap->ability_match_count = 0;
 995                 } else {
 996                         if (++ap->ability_match_count > 1) {
 997                                 ap->ability_match = 1;
 998                                 ap->ability_match_cfg = rx_cfg_reg;
 999                         }
1000                 }
1001                 if (rx_cfg_reg & ANEG_CFG_ACK)
1002                         ap->ack_match = 1;
1003                 else
1004                         ap->ack_match = 0;
1005
1006                 ap->idle_match = 0;
1007         } else {
1008                 ap->idle_match = 1;
1009                 ap->ability_match_cfg = 0;
1010                 ap->ability_match_count = 0;
1011                 ap->ability_match = 0;
1012                 ap->ack_match = 0;
1013
1014                 rx_cfg_reg = 0;
1015         }
1016
1017         ap->rxconfig = rx_cfg_reg;
1018         ret = ANEG_OK;
1019
1020         switch(ap->state) {
1021         case ANEG_STATE_UNKNOWN:
1022                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
1023                         ap->state = ANEG_STATE_AN_ENABLE;
1024
1025                 /* fallthru */
1026         case ANEG_STATE_AN_ENABLE:
1027                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
1028                 if (ap->flags & MR_AN_ENABLE) {
1029                         ap->link_time = 0;
1030                         ap->cur_time = 0;
1031                         ap->ability_match_cfg = 0;
1032                         ap->ability_match_count = 0;
1033                         ap->ability_match = 0;
1034                         ap->idle_match = 0;
1035                         ap->ack_match = 0;
1036
1037                         ap->state = ANEG_STATE_RESTART_INIT;
1038                 } else {
1039                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
1040                 }
1041                 break;
1042
1043         case ANEG_STATE_RESTART_INIT:
1044                 ap->link_time = ap->cur_time;
1045                 ap->flags &= ~(MR_NP_LOADED);
1046                 ap->txconfig = 0;
1047                 tw32(MAC_TX_AUTO_NEG, 0);
1048                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1049                 tw32_carefully(MAC_MODE, tp->mac_mode);
1050
1051                 ret = ANEG_TIMER_ENAB;
1052                 ap->state = ANEG_STATE_RESTART;
1053
1054                 /* fallthru */
1055         case ANEG_STATE_RESTART:
1056                 delta = ap->cur_time - ap->link_time;
1057                 if (delta > ANEG_STATE_SETTLE_TIME) {
1058                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
1059                 } else {
1060                         ret = ANEG_TIMER_ENAB;
1061                 }
1062                 break;
1063
1064         case ANEG_STATE_DISABLE_LINK_OK:
1065                 ret = ANEG_DONE;
1066                 break;
1067
1068         case ANEG_STATE_ABILITY_DETECT_INIT:
1069                 ap->flags &= ~(MR_TOGGLE_TX);
1070                 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
1071                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
1072                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1073                 tw32_carefully(MAC_MODE, tp->mac_mode);
1074
1075                 ap->state = ANEG_STATE_ABILITY_DETECT;
1076                 break;
1077
1078         case ANEG_STATE_ABILITY_DETECT:
1079                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
1080                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
1081                 }
1082                 break;
1083
1084         case ANEG_STATE_ACK_DETECT_INIT:
1085                 ap->txconfig |= ANEG_CFG_ACK;
1086                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
1087                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1088                 tw32_carefully(MAC_MODE, tp->mac_mode);
1089
1090                 ap->state = ANEG_STATE_ACK_DETECT;
1091
1092                 /* fallthru */
1093         case ANEG_STATE_ACK_DETECT:
1094                 if (ap->ack_match != 0) {
1095                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
1096                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
1097                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
1098                         } else {
1099                                 ap->state = ANEG_STATE_AN_ENABLE;
1100                         }
1101                 } else if (ap->ability_match != 0 &&
1102                            ap->rxconfig == 0) {
1103                         ap->state = ANEG_STATE_AN_ENABLE;
1104                 }
1105                 break;
1106
1107         case ANEG_STATE_COMPLETE_ACK_INIT:
1108                 if (ap->rxconfig & ANEG_CFG_INVAL) {
1109                         ret = ANEG_FAILED;
1110                         break;
1111                 }
1112                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
1113                                MR_LP_ADV_HALF_DUPLEX |
1114                                MR_LP_ADV_SYM_PAUSE |
1115                                MR_LP_ADV_ASYM_PAUSE |
1116                                MR_LP_ADV_REMOTE_FAULT1 |
1117                                MR_LP_ADV_REMOTE_FAULT2 |
1118                                MR_LP_ADV_NEXT_PAGE |
1119                                MR_TOGGLE_RX |
1120                                MR_NP_RX);
1121                 if (ap->rxconfig & ANEG_CFG_FD)
1122                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
1123                 if (ap->rxconfig & ANEG_CFG_HD)
1124                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
1125                 if (ap->rxconfig & ANEG_CFG_PS1)
1126                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
1127                 if (ap->rxconfig & ANEG_CFG_PS2)
1128                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
1129                 if (ap->rxconfig & ANEG_CFG_RF1)
1130                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
1131                 if (ap->rxconfig & ANEG_CFG_RF2)
1132                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
1133                 if (ap->rxconfig & ANEG_CFG_NP)
1134                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
1135
1136                 ap->link_time = ap->cur_time;
1137
1138                 ap->flags ^= (MR_TOGGLE_TX);
1139                 if (ap->rxconfig & 0x0008)
1140                         ap->flags |= MR_TOGGLE_RX;
1141                 if (ap->rxconfig & ANEG_CFG_NP)
1142                         ap->flags |= MR_NP_RX;
1143                 ap->flags |= MR_PAGE_RX;
1144
1145                 ap->state = ANEG_STATE_COMPLETE_ACK;
1146                 ret = ANEG_TIMER_ENAB;
1147                 break;
1148
1149         case ANEG_STATE_COMPLETE_ACK:
1150                 if (ap->ability_match != 0 &&
1151                     ap->rxconfig == 0) {
1152                         ap->state = ANEG_STATE_AN_ENABLE;
1153                         break;
1154                 }
1155                 delta = ap->cur_time - ap->link_time;
1156                 if (delta > ANEG_STATE_SETTLE_TIME) {
1157                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
1158                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
1159                         } else {
1160                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
1161                                     !(ap->flags & MR_NP_RX)) {
1162                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
1163                                 } else {
1164                                         ret = ANEG_FAILED;
1165                                 }
1166                         }
1167                 }
1168                 break;
1169
1170         case ANEG_STATE_IDLE_DETECT_INIT:
1171                 ap->link_time = ap->cur_time;
1172                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
1173                 tw32_carefully(MAC_MODE, tp->mac_mode);
1174
1175                 ap->state = ANEG_STATE_IDLE_DETECT;
1176                 ret = ANEG_TIMER_ENAB;
1177                 break;
1178
1179         case ANEG_STATE_IDLE_DETECT:
1180                 if (ap->ability_match != 0 &&
1181                     ap->rxconfig == 0) {
1182                         ap->state = ANEG_STATE_AN_ENABLE;
1183                         break;
1184                 }
1185                 delta = ap->cur_time - ap->link_time;
1186                 if (delta > ANEG_STATE_SETTLE_TIME) {
1187                         /* XXX another gem from the Broadcom driver :( */
1188                         ap->state = ANEG_STATE_LINK_OK;
1189                 }
1190                 break;
1191
1192         case ANEG_STATE_LINK_OK:
1193                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
1194                 ret = ANEG_DONE;
1195                 break;
1196
1197         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
1198                 /* ??? unimplemented */
1199                 break;
1200
1201         case ANEG_STATE_NEXT_PAGE_WAIT:
1202                 /* ??? unimplemented */
1203                 break;
1204
1205         default:
1206                 ret = ANEG_FAILED;
1207                 break;
1208         };
1209
1210         return ret;
1211 }
1212
1213 static int tg3_setup_fiber_phy(struct tg3 *tp)
1214 {
1215         uint32_t orig_pause_cfg;
1216         uint16_t orig_active_speed;
1217         uint8_t orig_active_duplex;
1218         int current_link_up;
1219         int i;
1220
1221         orig_pause_cfg =
1222                 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
1223                                   TG3_FLAG_TX_PAUSE));
1224         orig_active_speed = tp->link_config.active_speed;
1225         orig_active_duplex = tp->link_config.active_duplex;
1226
1227         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
1228         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
1229         tw32_carefully(MAC_MODE, tp->mac_mode);
1230
1231         /* Reset when initting first time or we have a link. */
1232         if (!(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) ||
1233             (tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED)) {
1234                 /* Set PLL lock range. */
1235                 tg3_writephy(tp, 0x16, 0x8007);
1236
1237                 /* SW reset */
1238                 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
1239
1240                 /* Wait for reset to complete. */
1241                 mdelay(5);
1242
1243                 /* Config mode; select PMA/Ch 1 regs. */
1244                 tg3_writephy(tp, 0x10, 0x8411);
1245
1246                 /* Enable auto-lock and comdet, select txclk for tx. */
1247                 tg3_writephy(tp, 0x11, 0x0a10);
1248
1249                 tg3_writephy(tp, 0x18, 0x00a0);
1250                 tg3_writephy(tp, 0x16, 0x41ff);
1251
1252                 /* Assert and deassert POR. */
1253                 tg3_writephy(tp, 0x13, 0x0400);
1254                 udelay(40);
1255                 tg3_writephy(tp, 0x13, 0x0000);
1256
1257                 tg3_writephy(tp, 0x11, 0x0a50);
1258                 udelay(40);
1259                 tg3_writephy(tp, 0x11, 0x0a10);
1260
1261                 /* Wait for signal to stabilize */
1262                 mdelay(150);
1263
1264                 /* Deselect the channel register so we can read the PHYID
1265                  * later.
1266                  */
1267                 tg3_writephy(tp, 0x10, 0x8011);
1268         }
1269
1270         /* Disable link change interrupt.  */
1271         tw32_carefully(MAC_EVENT, 0);
1272
1273         current_link_up = 0;
1274         if (tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED) {
1275                 if (!(tp->tg3_flags & TG3_FLAG_GOT_SERDES_FLOWCTL)) {
1276                         struct tg3_fiber_aneginfo aninfo;
1277                         int status = ANEG_FAILED;
1278                         unsigned int tick;
1279                         uint32_t tmp;
1280
1281                         memset(&aninfo, 0, sizeof(aninfo));
1282                         aninfo.flags |= (MR_AN_ENABLE);
1283
1284                         tw32(MAC_TX_AUTO_NEG, 0);
1285
1286                         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
1287                         tw32_carefully(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
1288
1289                         tw32_carefully(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
1290
1291                         aninfo.state = ANEG_STATE_UNKNOWN;
1292                         aninfo.cur_time = 0;
1293                         tick = 0;
1294                         while (++tick < 195000) {
1295                                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
1296                                 if (status == ANEG_DONE ||
1297                                     status == ANEG_FAILED)
1298                                         break;
1299
1300                                 udelay(1);
1301                         }
1302
1303                         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
1304                         tw32_carefully(MAC_MODE, tp->mac_mode);
1305
1306                         if (status == ANEG_DONE &&
1307                             (aninfo.flags &
1308                              (MR_AN_COMPLETE | MR_LINK_OK |
1309                               MR_LP_ADV_FULL_DUPLEX))) {
1310                                 uint32_t local_adv, remote_adv;
1311
1312                                 local_adv = ADVERTISE_PAUSE_CAP;
1313                                 remote_adv = 0;
1314                                 if (aninfo.flags & MR_LP_ADV_SYM_PAUSE)
1315                                         remote_adv |= LPA_PAUSE_CAP;
1316                                 if (aninfo.flags & MR_LP_ADV_ASYM_PAUSE)
1317                                         remote_adv |= LPA_PAUSE_ASYM;
1318
1319                                 tg3_setup_flow_control(tp, local_adv, remote_adv);
1320
1321                                 tp->tg3_flags |=
1322                                         TG3_FLAG_GOT_SERDES_FLOWCTL;
1323                                 current_link_up = 1;
1324                         }
1325                         for (i = 0; i < 60; i++) {
1326                                 udelay(20);
1327                                 tw32_carefully(MAC_STATUS,
1328                                         (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED));
1329                                 if ((tr32(MAC_STATUS) &
1330                                      (MAC_STATUS_SYNC_CHANGED |
1331                                       MAC_STATUS_CFG_CHANGED)) == 0)
1332                                         break;
1333                         }
1334                         if (current_link_up == 0 &&
1335                             (tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED)) {
1336                                 current_link_up = 1;
1337                         }
1338                 } else {
1339                         /* Forcing 1000FD link up. */
1340                         current_link_up = 1;
1341                 }
1342         }
1343
1344         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1345         tw32_carefully(MAC_MODE, tp->mac_mode);
1346
1347         tp->hw_status->status =
1348                 (SD_STATUS_UPDATED |
1349                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
1350
1351         for (i = 0; i < 100; i++) {
1352                 udelay(20);
1353                 tw32_carefully(MAC_STATUS,
1354                         (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED));
1355                 if ((tr32(MAC_STATUS) &
1356                      (MAC_STATUS_SYNC_CHANGED |
1357                       MAC_STATUS_CFG_CHANGED)) == 0)
1358                         break;
1359         }
1360
1361         if ((tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED) == 0)
1362                 current_link_up = 0;
1363
1364         if (current_link_up == 1) {
1365                 tp->link_config.active_speed = SPEED_1000;
1366                 tp->link_config.active_duplex = DUPLEX_FULL;
1367         } else {
1368                 tp->link_config.active_speed = SPEED_INVALID;
1369                 tp->link_config.active_duplex = DUPLEX_INVALID;
1370         }
1371
1372         if (current_link_up != tp->carrier_ok) {
1373                 tp->carrier_ok = current_link_up;
1374                 tg3_link_report(tp);
1375         } else {
1376                 uint32_t now_pause_cfg =
1377                         tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
1378                                          TG3_FLAG_TX_PAUSE);
1379                 if (orig_pause_cfg != now_pause_cfg ||
1380                     orig_active_speed != tp->link_config.active_speed ||
1381                     orig_active_duplex != tp->link_config.active_duplex)
1382                         tg3_link_report(tp);
1383         }
1384
1385         if ((tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED) == 0) {
1386                 tw32_carefully(MAC_MODE, tp->mac_mode | MAC_MODE_LINK_POLARITY);
1387                 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
1388                         tw32_carefully(MAC_MODE, tp->mac_mode);
1389                 }
1390         }
1391
1392         return 0;
1393 }
1394 #else
1395 #define tg3_setup_fiber_phy(TP) (-EINVAL)
1396 #endif /* SUPPORT_FIBER_PHY */
1397
1398 static int tg3_setup_phy(struct tg3 *tp)
1399 {
1400         int err;
1401
1402         if (tp->phy_id == PHY_ID_SERDES) {
1403                 err = tg3_setup_fiber_phy(tp);
1404         } else {
1405                 err = tg3_setup_copper_phy(tp);
1406         }
1407
1408         if (tp->link_config.active_speed == SPEED_1000 &&
1409             tp->link_config.active_duplex == DUPLEX_HALF)
1410                 tw32(MAC_TX_LENGTHS,
1411                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1412                       (6 << TX_LENGTHS_IPG_SHIFT) |
1413                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1414         else
1415                 tw32(MAC_TX_LENGTHS,
1416                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1417                       (6 << TX_LENGTHS_IPG_SHIFT) |
1418                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1419
1420         return err;
1421 }
1422
1423
1424 #define MAX_WAIT_CNT 1000
1425
1426 /* To stop a block, clear the enable bit and poll till it
1427  * clears.
1428  */
1429 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, uint32_t enable_bit)
1430 {
1431         unsigned int i;
1432         uint32_t val;
1433
1434         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
1435             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
1436                 switch(ofs) {
1437                 case RCVLSC_MODE:
1438                 case DMAC_MODE:
1439                 case MBFREE_MODE:
1440                 case BUFMGR_MODE:
1441                 case MEMARB_MODE:
1442                         /* We can't enable/disable these bits of the
1443                          * 5705 or 5787, just say success.
1444                          */
1445                         return 0;
1446                 default:
1447                         break;
1448                 }
1449         }
1450         val = tr32(ofs);
1451         val &= ~enable_bit;
1452         tw32(ofs, val);
1453         tr32(ofs);
1454
1455         for (i = 0; i < MAX_WAIT_CNT; i++) {
1456                 udelay(100);
1457                 val = tr32(ofs);
1458                 if ((val & enable_bit) == 0)
1459                         break;
1460         }
1461
1462         if (i == MAX_WAIT_CNT) {
1463                 printf( "tg3_stop_block timed out, ofs=%#lx enable_bit=%3lx\n",
1464                        ofs, enable_bit );
1465                 return -ENODEV;
1466         }
1467
1468         return 0;
1469 }
1470
1471 static int tg3_abort_hw(struct tg3 *tp)
1472 {
1473         int i, err;
1474         uint32_t val;
1475
1476         tg3_disable_ints(tp);
1477
1478         tp->rx_mode &= ~RX_MODE_ENABLE;
1479         tw32_carefully(MAC_RX_MODE, tp->rx_mode);
1480
1481         err  = tg3_stop_block(tp, RCVBDI_MODE,   RCVBDI_MODE_ENABLE);
1482         err |= tg3_stop_block(tp, RCVLPC_MODE,   RCVLPC_MODE_ENABLE);
1483         err |= tg3_stop_block(tp, RCVLSC_MODE,   RCVLSC_MODE_ENABLE);
1484         err |= tg3_stop_block(tp, RCVDBDI_MODE,  RCVDBDI_MODE_ENABLE);
1485         err |= tg3_stop_block(tp, RCVDCC_MODE,   RCVDCC_MODE_ENABLE);
1486         err |= tg3_stop_block(tp, RCVCC_MODE,    RCVCC_MODE_ENABLE);
1487
1488         err |= tg3_stop_block(tp, SNDBDS_MODE,   SNDBDS_MODE_ENABLE);
1489         err |= tg3_stop_block(tp, SNDBDI_MODE,   SNDBDI_MODE_ENABLE);
1490         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1491         err |= tg3_stop_block(tp, RDMAC_MODE,    RDMAC_MODE_ENABLE);
1492         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
1493         err |= tg3_stop_block(tp, SNDBDC_MODE,   SNDBDC_MODE_ENABLE);
1494         if (err)
1495                 goto out;
1496
1497         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
1498         tw32_carefully(MAC_MODE, tp->mac_mode);
1499
1500         tp->tx_mode &= ~TX_MODE_ENABLE;
1501         tw32_carefully(MAC_TX_MODE, tp->tx_mode);
1502
1503         for (i = 0; i < MAX_WAIT_CNT; i++) {
1504                 udelay(100);
1505                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
1506                         break;
1507         }
1508         if (i >= MAX_WAIT_CNT) {
1509                 printf("tg3_abort_hw timed out TX_MODE_ENABLE will not clear MAC_TX_MODE=%x\n",
1510                        (unsigned int) tr32(MAC_TX_MODE));
1511                 return -ENODEV;
1512         }
1513
1514         err  = tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE);
1515         err |= tg3_stop_block(tp, WDMAC_MODE,  WDMAC_MODE_ENABLE);
1516         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE);
1517
1518         val = tr32(FTQ_RESET);
1519         val |= FTQ_RESET_DMA_READ_QUEUE | FTQ_RESET_DMA_HIGH_PRI_READ |
1520                FTQ_RESET_SEND_BD_COMPLETION | FTQ_RESET_DMA_WRITE |
1521                FTQ_RESET_DMA_HIGH_PRI_WRITE | FTQ_RESET_SEND_DATA_COMPLETION |
1522                FTQ_RESET_HOST_COALESCING | FTQ_RESET_MAC_TX |
1523                FTQ_RESET_RX_BD_COMPLETE | FTQ_RESET_RX_LIST_PLCMT |
1524                FTQ_RESET_RX_DATA_COMPLETION;
1525         tw32(FTQ_RESET, val);
1526
1527         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE);
1528         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE);
1529         if (err)
1530                 goto out;
1531
1532         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
1533
1534 out:
1535         return err;
1536 }
1537
1538 static void tg3_chip_reset(struct tg3 *tp)
1539 {
1540         uint32_t val;
1541
1542         if (!(tp->tg3_flags2 & TG3_FLG2_SUN_5704)) {
1543                 /* Force NVRAM to settle.
1544                  * This deals with a chip bug which can result in EEPROM
1545                  * corruption.
1546                  */
1547                 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
1548                         int i;
1549
1550                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
1551                         for (i = 0; i < 100000; i++) {
1552                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
1553                                         break;
1554                                 udelay(10);
1555                         }
1556                 }
1557         }
1558         /* In Etherboot we don't need to worry about the 5701
1559          * REG_WRITE_BUG because we do all register writes indirectly.
1560          */
1561
1562         // Alf: here patched
1563         /* do the reset */
1564         val = GRC_MISC_CFG_CORECLK_RESET;
1565         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
1566                 if (tr32(0x7e2c) == 0x60) {
1567                         tw32(0x7e2c, 0x20);
1568                 }
1569                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
1570                         tw32(GRC_MISC_CFG, (1 << 29));
1571                         val |= (1 << 29);
1572                 }
1573         }
1574
1575         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
1576             || (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1577             || (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)) {
1578                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
1579         }
1580
1581         // Alf : Please VALIDATE THIS.
1582         // It is necessary in my case (5751) to prevent a reboot, but
1583         // I have no idea about a side effect on any other version.
1584         // It appears to be what's done in tigon3.c from Broadcom
1585         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
1586           tw32(GRC_MISC_CFG, 0x20000000) ;
1587           val |= 0x20000000 ;
1588         }
1589
1590         tw32(GRC_MISC_CFG, val);
1591
1592         /* Flush PCI posted writes.  The normal MMIO registers
1593          * are inaccessible at this time so this is the only
1594          * way to make this reliably.  I tried to use indirect
1595          * register read/write but this upset some 5701 variants.
1596          */
1597         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
1598
1599         udelay(120);
1600
1601         /* Re-enable indirect register accesses. */
1602         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
1603                                tp->misc_host_ctrl);
1604
1605         /* Set MAX PCI retry to zero. */
1606         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
1607         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
1608             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
1609                 val |= PCISTATE_RETRY_SAME_DMA;
1610         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
1611
1612         pci_restore_state(tp->pdev, tp->pci_cfg_state);
1613
1614         /* Make sure PCI-X relaxed ordering bit is clear. */
1615         pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
1616         val &= ~PCIX_CAPS_RELAXED_ORDERING;
1617         pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
1618
1619         tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
1620
1621         if (((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0) &&
1622                 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
1623                 tp->pci_clock_ctrl |=
1624                         (CLOCK_CTRL_FORCE_CLKRUN | CLOCK_CTRL_CLKRUN_OENABLE);
1625                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
1626         }
1627
1628         tw32(TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
1629 }
1630
1631 static void tg3_stop_fw(struct tg3 *tp)
1632 {
1633         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
1634                 uint32_t val;
1635                 int i;
1636
1637                 tg3_write_mem(NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1638                 val = tr32(GRC_RX_CPU_EVENT);
1639                 val |= (1 << 14);
1640                 tw32(GRC_RX_CPU_EVENT, val);
1641
1642                 /* Wait for RX cpu to ACK the event.  */
1643                 for (i = 0; i < 100; i++) {
1644                         if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
1645                                 break;
1646                         udelay(1);
1647                 }
1648         }
1649 }
1650
1651 static int tg3_restart_fw(struct tg3 *tp, uint32_t state)
1652 {
1653         uint32_t val;
1654         int i;
1655
1656         tg3_write_mem(NIC_SRAM_FIRMWARE_MBOX,
1657                 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1658         /* Wait for firmware initialization to complete. */
1659         for (i = 0; i < 100000; i++) {
1660                 tg3_read_mem(NIC_SRAM_FIRMWARE_MBOX, &val);
1661                 if (val == (uint32_t) ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1662                         break;
1663                 udelay(10);
1664         }
1665         if (i >= 100000 &&
1666                     !(tp->tg3_flags2 & TG3_FLG2_SUN_5704) &&
1667                     !(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)) {
1668                 printf ( "Firmware will not restart magic=%#lx\n",
1669                         val );
1670                 return -ENODEV;
1671         }
1672         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1673           state = DRV_STATE_SUSPEND;
1674         }
1675
1676         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
1677             (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)) {
1678           // Enable PCIE bug fix
1679           tg3_read_mem(0x7c00, &val);
1680           tg3_write_mem(0x7c00, val | 0x02000000);
1681         }
1682         tg3_write_mem(NIC_SRAM_FW_DRV_STATE_MBOX, state);
1683         return 0;
1684 }
1685
1686 static int tg3_halt(struct tg3 *tp)
1687 {
1688         tg3_stop_fw(tp);
1689         tg3_abort_hw(tp);
1690         tg3_chip_reset(tp);
1691         return tg3_restart_fw(tp, DRV_STATE_UNLOAD);
1692 }
1693
1694 static void __tg3_set_mac_addr(struct tg3 *tp)
1695 {
1696         uint32_t addr_high, addr_low;
1697         int i;
1698
1699         addr_high = ((tp->nic->node_addr[0] << 8) |
1700                      tp->nic->node_addr[1]);
1701         addr_low = ((tp->nic->node_addr[2] << 24) |
1702                     (tp->nic->node_addr[3] << 16) |
1703                     (tp->nic->node_addr[4] <<  8) |
1704                     (tp->nic->node_addr[5] <<  0));
1705         for (i = 0; i < 4; i++) {
1706                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
1707                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
1708         }
1709
1710         if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
1711                 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
1712                 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705)) {
1713                 for(i = 0; i < 12; i++) {
1714                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
1715                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
1716                 }
1717         }
1718         addr_high = (tp->nic->node_addr[0] +
1719                      tp->nic->node_addr[1] +
1720                      tp->nic->node_addr[2] +
1721                      tp->nic->node_addr[3] +
1722                      tp->nic->node_addr[4] +
1723                      tp->nic->node_addr[5]) &
1724                 TX_BACKOFF_SEED_MASK;
1725         tw32(MAC_TX_BACKOFF_SEED, addr_high);
1726 }
1727
1728 static void tg3_set_bdinfo(struct tg3 *tp, uint32_t bdinfo_addr,
1729                            dma_addr_t mapping, uint32_t maxlen_flags,
1730                            uint32_t nic_addr)
1731 {
1732         tg3_write_mem((bdinfo_addr +
1733                        TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
1734                       ((uint64_t) mapping >> 32));
1735         tg3_write_mem((bdinfo_addr +
1736                        TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
1737                       ((uint64_t) mapping & 0xffffffff));
1738         tg3_write_mem((bdinfo_addr +
1739                        TG3_BDINFO_MAXLEN_FLAGS),
1740                        maxlen_flags);
1741         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
1742                 tg3_write_mem((bdinfo_addr + TG3_BDINFO_NIC_ADDR), nic_addr);
1743         }
1744 }
1745
1746
1747 static void tg3_init_rings(struct tg3 *tp)
1748 {
1749         unsigned i;
1750
1751         /* Zero out the tg3 variables */
1752         memset(&tg3_bss, 0, sizeof(tg3_bss));
1753         tp->rx_std    = &tg3_bss.rx_std[0];
1754         tp->rx_rcb    = &tg3_bss.rx_rcb[0];
1755         tp->tx_ring   = &tg3_bss.tx_ring[0];
1756         tp->hw_status = &tg3_bss.hw_status;
1757         tp->hw_stats  = &tg3_bss.hw_stats;
1758         tp->mac_mode  = 0;
1759
1760
1761         /* Initialize tx/rx rings for packet processing.
1762          *
1763          * The chip has been shut down and the driver detached from
1764          * the networking, so no interrupts or new tx packets will
1765          * end up in the driver.
1766          */
1767
1768         /* Initialize invariants of the rings, we only set this
1769          * stuff once.  This works because the card does not
1770          * write into the rx buffer posting rings.
1771          */
1772         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
1773                 struct tg3_rx_buffer_desc *rxd;
1774
1775                 rxd = &tp->rx_std[i];
1776                 rxd->idx_len = (RX_PKT_BUF_SZ - 2 - 64) << RXD_LEN_SHIFT;
1777                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
1778                 rxd->opaque = (RXD_OPAQUE_RING_STD | (i << RXD_OPAQUE_INDEX_SHIFT));
1779
1780                 /* Note where the receive buffer for the ring is placed */
1781                 rxd->addr_hi = 0;
1782                 rxd->addr_lo = virt_to_bus(
1783                         &tg3_bss.rx_bufs[i%TG3_DEF_RX_RING_PENDING][2]);
1784         }
1785 }
1786
1787 #define TG3_WRITE_SETTINGS(TABLE) \
1788 do { \
1789         const uint32_t *_table, *_end; \
1790         _table = TABLE; \
1791         _end = _table + sizeof(TABLE)/sizeof(TABLE[0]);  \
1792         for(; _table < _end; _table += 2) { \
1793                 tw32(_table[0], _table[1]); \
1794         } \
1795 } while(0)
1796
1797
1798 /* initialize/reset the tg3 */
1799 static int tg3_setup_hw(struct tg3 *tp)
1800 {
1801         uint32_t val, rdmac_mode;
1802         int i, err, limit;
1803
1804         /* Simply don't support setups with extremly buggy firmware in etherboot */
1805         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
1806                 printf("Error 5701_A0 firmware bug detected\n");
1807                 return -EINVAL;
1808         }
1809
1810         tg3_disable_ints(tp);
1811
1812         /* Originally this was all in tg3_init_hw */
1813
1814         /* Force the chip into D0. */
1815         tg3_set_power_state_0(tp);
1816
1817         tg3_switch_clocks(tp);
1818
1819         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
1820
1821         // This should go somewhere else
1822 #define T3_PCIE_CAPABILITY_ID_REG           0xD0
1823 #define T3_PCIE_CAPABILITY_ID               0x10
1824 #define T3_PCIE_CAPABILITY_REG              0xD2
1825
1826         /* Originally this was all in tg3_reset_hw */
1827
1828         tg3_stop_fw(tp);
1829
1830         /* No need to call tg3_abort_hw here, it is called before tg3_setup_hw. */
1831
1832         tg3_chip_reset(tp);
1833
1834         tw32(GRC_MODE, tp->grc_mode);  /* Redundant? */
1835
1836         err = tg3_restart_fw(tp, DRV_STATE_START);
1837         if (err)
1838                 return err;
1839
1840         if (tp->phy_id == PHY_ID_SERDES) {
1841                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
1842         }
1843         tw32_carefully(MAC_MODE, tp->mac_mode);
1844
1845
1846         /* This works around an issue with Athlon chipsets on
1847          * B3 tigon3 silicon.  This bit has no effect on any
1848          * other revision.
1849          * Alf: Except 5750 ! (which reboots)
1850          */
1851
1852         if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
1853           tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
1854         tw32_carefully(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
1855
1856         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
1857             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
1858                 val = tr32(TG3PCI_PCISTATE);
1859                 val |= PCISTATE_RETRY_SAME_DMA;
1860                 tw32(TG3PCI_PCISTATE, val);
1861         }
1862
1863         /* Descriptor ring init may make accesses to the
1864          * NIC SRAM area to setup the TX descriptors, so we
1865          * can only do this after the hardware has been
1866          * successfully reset.
1867          */
1868         tg3_init_rings(tp);
1869
1870         /* Clear statistics/status block in chip */
1871         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
1872                 for (i = NIC_SRAM_STATS_BLK;
1873                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
1874                      i += sizeof(uint32_t)) {
1875                         tg3_write_mem(i, 0);
1876                         udelay(40);
1877                 }
1878         }
1879
1880         /* This value is determined during the probe time DMA
1881          * engine test, tg3_setup_dma.
1882          */
1883         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
1884
1885         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
1886                           GRC_MODE_4X_NIC_SEND_RINGS |
1887                           GRC_MODE_NO_TX_PHDR_CSUM |
1888                           GRC_MODE_NO_RX_PHDR_CSUM);
1889         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
1890         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1891         tp->grc_mode |= GRC_MODE_NO_RX_PHDR_CSUM;
1892
1893         tw32(GRC_MODE,
1894                 tp->grc_mode |
1895                 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
1896
1897         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
1898         tw32(GRC_MISC_CFG,
1899              (65 << GRC_MISC_CFG_PRESCALAR_SHIFT));
1900
1901         /* Initialize MBUF/DESC pool. */
1902         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
1903                 /* Do nothing. */
1904         } else if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) &&
1905                 (tp->pci_chip_rev_id != CHIPREV_ID_5721)) {
1906                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
1907                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
1908                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
1909                 else
1910                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
1911                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
1912                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
1913         }
1914         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE)) {
1915                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
1916                      tp->bufmgr_config.mbuf_read_dma_low_water);
1917                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
1918                      tp->bufmgr_config.mbuf_mac_rx_low_water);
1919                 tw32(BUFMGR_MB_HIGH_WATER,
1920                      tp->bufmgr_config.mbuf_high_water);
1921         } else {
1922                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
1923                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
1924                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
1925                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
1926                 tw32(BUFMGR_MB_HIGH_WATER,
1927                      tp->bufmgr_config.mbuf_high_water_jumbo);
1928         }
1929         tw32(BUFMGR_DMA_LOW_WATER,
1930              tp->bufmgr_config.dma_low_water);
1931         tw32(BUFMGR_DMA_HIGH_WATER,
1932              tp->bufmgr_config.dma_high_water);
1933
1934         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
1935         for (i = 0; i < 2000; i++) {
1936                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
1937                         break;
1938                 udelay(10);
1939         }
1940         if (i >= 2000) {
1941                 printf("tg3_setup_hw cannot enable BUFMGR\n");
1942                 return -ENODEV;
1943         }
1944
1945         tw32(FTQ_RESET, 0xffffffff);
1946         tw32(FTQ_RESET, 0x00000000);
1947         for (i = 0; i < 2000; i++) {
1948                 if (tr32(FTQ_RESET) == 0x00000000)
1949                         break;
1950                 udelay(10);
1951         }
1952         if (i >= 2000) {
1953                 printf("tg3_setup_hw cannot reset FTQ\n");
1954                 return -ENODEV;
1955         }
1956
1957         /* Initialize TG3_BDINFO's at:
1958          *  RCVDBDI_STD_BD:     standard eth size rx ring
1959          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
1960          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
1961          *
1962          * like so:
1963          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
1964          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
1965          *                              ring attribute flags
1966          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
1967          *
1968          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
1969          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
1970          *
1971          * ??? No space allocated for mini receive ring? :(
1972          *
1973          * The size of each ring is fixed in the firmware, but the location is
1974          * configurable.
1975          */
1976         {
1977                 static const uint32_t table_all[] = {
1978                         /* Setup replenish thresholds. */
1979                         RCVBDI_STD_THRESH, TG3_DEF_RX_RING_PENDING / 8,
1980
1981                         /* Etherboot lives below 4GB */
1982                         RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, 0,
1983                         RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR, NIC_SRAM_RX_BUFFER_DESC,
1984                 };
1985                 static const uint32_t table_not_5705[] = {
1986                         /* Buffer maximum length */
1987                         RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT,
1988
1989                         /* Disable the mini frame rx ring */
1990                         RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,      BDINFO_FLAGS_DISABLED,
1991
1992                         /* Disable the jumbo frame rx ring */
1993                         RCVBDI_JUMBO_THRESH, 0,
1994                         RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, BDINFO_FLAGS_DISABLED,
1995
1996
1997                 };
1998                 TG3_WRITE_SETTINGS(table_all);
1999                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
2000                         virt_to_bus(tp->rx_std));
2001                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
2002                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
2003                         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
2004                                 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
2005                 } else {
2006                         TG3_WRITE_SETTINGS(table_not_5705);
2007                 }
2008         }
2009
2010
2011         /* There is only one send ring on 5705 and 5787, no need to explicitly
2012          * disable the others.
2013          */
2014         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
2015             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) {
2016                 /* Clear out send RCB ring in SRAM. */
2017                 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
2018                         tg3_write_mem(i + TG3_BDINFO_MAXLEN_FLAGS, BDINFO_FLAGS_DISABLED);
2019         }
2020
2021         tp->tx_prod = 0;
2022         tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
2023         tw32_mailbox2(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
2024
2025         tg3_set_bdinfo(tp,
2026                 NIC_SRAM_SEND_RCB,
2027                 virt_to_bus(tp->tx_ring),
2028                 (TG3_TX_RING_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT),
2029                 NIC_SRAM_TX_BUFFER_DESC);
2030
2031         /* There is only one receive return ring on 5705 and 5787, no need to
2032          * explicitly disable the others.
2033          */
2034         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
2035             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) {
2036                 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK; i += TG3_BDINFO_SIZE) {
2037                         tg3_write_mem(i + TG3_BDINFO_MAXLEN_FLAGS,
2038                                 BDINFO_FLAGS_DISABLED);
2039                 }
2040         }
2041
2042         tp->rx_rcb_ptr = 0;
2043         tw32_mailbox2(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
2044
2045         tg3_set_bdinfo(tp,
2046                 NIC_SRAM_RCV_RET_RCB,
2047                 virt_to_bus(tp->rx_rcb),
2048                 (TG3_RX_RCB_RING_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT),
2049                 0);
2050
2051         tp->rx_std_ptr = TG3_DEF_RX_RING_PENDING;
2052         tw32_mailbox2(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
2053                      tp->rx_std_ptr);
2054
2055         tw32_mailbox2(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW, 0);
2056
2057         /* Initialize MAC address and backoff seed. */
2058         __tg3_set_mac_addr(tp);
2059
2060         /* Calculate RDMAC_MODE setting early, we need it to determine
2061          * the RCVLPC_STATE_ENABLE mask.
2062          */
2063         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
2064                 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
2065                 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
2066                 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
2067                 RDMAC_MODE_LNGREAD_ENAB);
2068         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
2069                 rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
2070         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2071                 if (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
2072                         if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
2073                                 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
2074                                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
2075                         }
2076                 }
2077         }
2078
2079         /* Setup host coalescing engine. */
2080         tw32(HOSTCC_MODE, 0);
2081         for (i = 0; i < 2000; i++) {
2082                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
2083                         break;
2084                 udelay(10);
2085         }
2086
2087         tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
2088                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
2089         tw32_carefully(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
2090
2091         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
2092         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
2093                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
2094                                        GRC_LCLCTRL_GPIO_OUTPUT1);
2095         tw32_carefully(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
2096
2097         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
2098         tr32(MAILBOX_INTERRUPT_0);
2099
2100         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
2101                 tw32_carefully(DMAC_MODE, DMAC_MODE_ENABLE);
2102         }
2103
2104         val = ( WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
2105                 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
2106                 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
2107                 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
2108                 WDMAC_MODE_LNGREAD_ENAB);
2109         if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) &&
2110                 ((tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) != 0) &&
2111                 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
2112                 val |= WDMAC_MODE_RX_ACCEL;
2113         }
2114
2115         /* Host coalescing bug fix */
2116         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
2117                 val |= (1 << 29);
2118
2119         tw32_carefully(WDMAC_MODE, val);
2120
2121         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
2122                 val = tr32(TG3PCI_X_CAPS);
2123                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
2124                         val &= PCIX_CAPS_BURST_MASK;
2125                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
2126                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2127                         val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
2128                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
2129                         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
2130                                 val |= (tp->split_mode_max_reqs <<
2131                                         PCIX_CAPS_SPLIT_SHIFT);
2132                 }
2133                 tw32(TG3PCI_X_CAPS, val);
2134         }
2135
2136         tw32_carefully(RDMAC_MODE, rdmac_mode);
2137         {
2138                 static const uint32_t table_all[] = {
2139                         /* MTU + ethernet header + FCS + optional VLAN tag */
2140                         MAC_RX_MTU_SIZE, ETH_MAX_MTU + ETH_HLEN + 8,
2141
2142                         /* The slot time is changed by tg3_setup_phy if we
2143                          * run at gigabit with half duplex.
2144                          */
2145                         MAC_TX_LENGTHS,
2146                         (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2147                         (6 << TX_LENGTHS_IPG_SHIFT) |
2148                         (32 << TX_LENGTHS_SLOT_TIME_SHIFT),
2149
2150                         /* Receive rules. */
2151                         MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS,
2152                         RCVLPC_CONFIG, 0x0181,
2153
2154                         /* Receive/send statistics. */
2155                         RCVLPC_STATS_ENABLE, 0xffffff,
2156                         RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE,
2157                         SNDDATAI_STATSENAB, 0xffffff,
2158                         SNDDATAI_STATSCTRL, (SNDDATAI_SCTRL_ENABLE |SNDDATAI_SCTRL_FASTUPD),
2159
2160                         /* Host coalescing engine */
2161                         HOSTCC_RXCOL_TICKS, 0,
2162                         HOSTCC_TXCOL_TICKS, LOW_TXCOL_TICKS,
2163                         HOSTCC_RXMAX_FRAMES, 1,
2164                         HOSTCC_TXMAX_FRAMES, LOW_RXMAX_FRAMES,
2165                         HOSTCC_RXCOAL_MAXF_INT, 1,
2166                         HOSTCC_TXCOAL_MAXF_INT, 0,
2167
2168                         /* Status/statistics block address. */
2169                         /* Etherboot lives below 4GB, so HIGH == 0 */
2170                         HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, 0,
2171
2172                         /* No need to enable 32byte coalesce mode. */
2173                         HOSTCC_MODE, HOSTCC_MODE_ENABLE | 0,
2174
2175                         RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE,
2176                         RCVLPC_MODE, RCVLPC_MODE_ENABLE,
2177
2178                         RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE,
2179
2180                         SNDDATAC_MODE, SNDDATAC_MODE_ENABLE,
2181                         SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE,
2182                         RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB,
2183                         RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ,
2184                         SNDDATAI_MODE, SNDDATAI_MODE_ENABLE,
2185                         SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE,
2186                         SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE,
2187
2188                         /* Accept all multicast frames. */
2189                         MAC_HASH_REG_0, 0xffffffff,
2190                         MAC_HASH_REG_1, 0xffffffff,
2191                         MAC_HASH_REG_2, 0xffffffff,
2192                         MAC_HASH_REG_3, 0xffffffff,
2193                 };
2194                 static const uint32_t table_not_5705[] = {
2195                         /* Host coalescing engine */
2196                         HOSTCC_RXCOAL_TICK_INT, 0,
2197                         HOSTCC_TXCOAL_TICK_INT, 0,
2198
2199                         /* Status/statistics block address. */
2200                         /* Etherboot lives below 4GB, so HIGH == 0 */
2201                         HOSTCC_STAT_COAL_TICKS, DEFAULT_STAT_COAL_TICKS,
2202                         HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, 0,
2203                         HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK,
2204                         HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK,
2205
2206                         RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE,
2207
2208                         MBFREE_MODE, MBFREE_MODE_ENABLE,
2209                 };
2210                 TG3_WRITE_SETTINGS(table_all);
2211                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
2212                         virt_to_bus(tp->hw_stats));
2213                 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
2214                         virt_to_bus(tp->hw_status));
2215                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
2216                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) {
2217                         TG3_WRITE_SETTINGS(table_not_5705);
2218                 }
2219         }
2220
2221         tp->tx_mode = TX_MODE_ENABLE;
2222         tw32_carefully(MAC_TX_MODE, tp->tx_mode);
2223
2224         tp->rx_mode = RX_MODE_ENABLE;
2225         tw32_carefully(MAC_RX_MODE, tp->rx_mode);
2226
2227         tp->mi_mode = MAC_MI_MODE_BASE;
2228         tw32_carefully(MAC_MI_MODE, tp->mi_mode);
2229
2230         tw32(MAC_LED_CTRL, 0);
2231         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2232         if (tp->phy_id == PHY_ID_SERDES) {
2233                 tw32_carefully(MAC_RX_MODE, RX_MODE_RESET);
2234         }
2235         tp->rx_mode |= RX_MODE_KEEP_VLAN_TAG; /* drop tagged vlan packets */
2236         tw32_carefully(MAC_RX_MODE, tp->rx_mode);
2237
2238         if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
2239                 tw32(MAC_SERDES_CFG, 0x616000);
2240
2241         /* Prevent chip from dropping frames when flow control
2242          * is enabled.
2243          */
2244         tw32(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
2245         tr32(MAC_LOW_WMARK_MAX_RX_FRAME);
2246
2247         err = tg3_setup_phy(tp);
2248
2249         /* Ignore CRC stats */
2250
2251         /* Initialize receive rules. */
2252         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
2253         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
2254         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
2255         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
2256
2257         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
2258             || (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750))
2259                 limit = 8;
2260         else
2261                 limit = 16;
2262         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
2263                 limit -= 4;
2264         switch (limit) {
2265         case 16:        tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
2266         case 15:        tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
2267         case 14:        tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
2268         case 13:        tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
2269         case 12:        tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
2270         case 11:        tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
2271         case 10:        tw32(MAC_RCV_RULE_9,  0);  tw32(MAC_RCV_VALUE_9,  0);
2272         case 9:         tw32(MAC_RCV_RULE_8,  0);  tw32(MAC_RCV_VALUE_8,  0);
2273         case 8:         tw32(MAC_RCV_RULE_7,  0);  tw32(MAC_RCV_VALUE_7,  0);
2274         case 7:         tw32(MAC_RCV_RULE_6,  0);  tw32(MAC_RCV_VALUE_6,  0);
2275         case 6:         tw32(MAC_RCV_RULE_5,  0);  tw32(MAC_RCV_VALUE_5,  0);
2276         case 5:         tw32(MAC_RCV_RULE_4,  0);  tw32(MAC_RCV_VALUE_4,  0);
2277         case 4:         /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
2278         case 3:         /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
2279         case 2:
2280         case 1:
2281         default:
2282                 break;
2283         };
2284
2285         return err;
2286 }
2287
2288
2289
2290 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
2291 static void tg3_nvram_init(struct tg3 *tp)
2292 {
2293         tw32(GRC_EEPROM_ADDR,
2294              (EEPROM_ADDR_FSM_RESET |
2295               (EEPROM_DEFAULT_CLOCK_PERIOD <<
2296                EEPROM_ADDR_CLKPERD_SHIFT)));
2297
2298         mdelay(1);
2299
2300         /* Enable seeprom accesses. */
2301         tw32_carefully(GRC_LOCAL_CTRL,
2302                 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
2303
2304         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2305             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2306                 uint32_t nvcfg1 = tr32(NVRAM_CFG1);
2307
2308                 tp->tg3_flags |= TG3_FLAG_NVRAM;
2309                 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
2310                         if (nvcfg1 & NVRAM_CFG1_BUFFERED_MODE)
2311                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
2312                 } else {
2313                         nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
2314                         tw32(NVRAM_CFG1, nvcfg1);
2315                 }
2316
2317         } else {
2318                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
2319         }
2320 }
2321
2322
2323 static int tg3_nvram_read_using_eeprom(
2324         struct tg3 *tp __unused, uint32_t offset, uint32_t *val)
2325 {
2326         uint32_t tmp;
2327         int i;
2328
2329         if (offset > EEPROM_ADDR_ADDR_MASK ||
2330                 (offset % 4) != 0) {
2331                 return -EINVAL;
2332         }
2333
2334         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2335                                         EEPROM_ADDR_DEVID_MASK |
2336                                         EEPROM_ADDR_READ);
2337         tw32(GRC_EEPROM_ADDR,
2338              tmp |
2339              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2340              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2341               EEPROM_ADDR_ADDR_MASK) |
2342              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2343
2344         for (i = 0; i < 10000; i++) {
2345                 tmp = tr32(GRC_EEPROM_ADDR);
2346
2347                 if (tmp & EEPROM_ADDR_COMPLETE)
2348                         break;
2349                 udelay(100);
2350         }
2351         if (!(tmp & EEPROM_ADDR_COMPLETE)) {
2352                 return -EBUSY;
2353         }
2354
2355         *val = tr32(GRC_EEPROM_DATA);
2356         return 0;
2357 }
2358
2359 static int tg3_nvram_read(struct tg3 *tp, uint32_t offset, uint32_t *val)
2360 {
2361         int i, saw_done_clear;
2362
2363         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2364                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2365
2366         if (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED)
2367                 offset = ((offset / NVRAM_BUFFERED_PAGE_SIZE) <<
2368                           NVRAM_BUFFERED_PAGE_POS) +
2369                         (offset % NVRAM_BUFFERED_PAGE_SIZE);
2370
2371         if (offset > NVRAM_ADDR_MSK)
2372                 return -EINVAL;
2373
2374         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2375         for (i = 0; i < 1000; i++) {
2376                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2377                         break;
2378                 udelay(20);
2379         }
2380
2381         tw32(NVRAM_ADDR, offset);
2382         tw32(NVRAM_CMD,
2383              NVRAM_CMD_RD | NVRAM_CMD_GO |
2384              NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2385
2386         /* Wait for done bit to clear then set again. */
2387         saw_done_clear = 0;
2388         for (i = 0; i < 1000; i++) {
2389                 udelay(10);
2390                 if (!saw_done_clear &&
2391                     !(tr32(NVRAM_CMD) & NVRAM_CMD_DONE))
2392                         saw_done_clear = 1;
2393                 else if (saw_done_clear &&
2394                          (tr32(NVRAM_CMD) & NVRAM_CMD_DONE))
2395                         break;
2396         }
2397         if (i >= 1000) {
2398                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2399                 return -EBUSY;
2400         }
2401
2402         *val = bswap_32(tr32(NVRAM_RDDATA));
2403         tw32(NVRAM_SWARB, 0x20);
2404
2405         return 0;
2406 }
2407
2408 struct subsys_tbl_ent {
2409         uint16_t subsys_vendor, subsys_devid;
2410         uint32_t phy_id;
2411 };
2412
2413 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
2414         /* Broadcom boards. */
2415         { 0x14e4, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
2416         { 0x14e4, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
2417         { 0x14e4, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
2418         { 0x14e4, 0x0003, PHY_ID_SERDES  }, /* BCM95700A9 */
2419         { 0x14e4, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
2420         { 0x14e4, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
2421         { 0x14e4, 0x0007, PHY_ID_SERDES  }, /* BCM95701A7 */
2422         { 0x14e4, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
2423         { 0x14e4, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
2424         { 0x14e4, 0x0009, PHY_ID_BCM5701 }, /* BCM95703Ax1 */
2425         { 0x14e4, 0x8009, PHY_ID_BCM5701 }, /* BCM95703Ax2 */
2426
2427         /* 3com boards. */
2428         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
2429         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
2430         /* { PCI_VENDOR_ID_3COM, 0x1002, PHY_ID_XXX },     3C996CT */
2431         /* { PCI_VENDOR_ID_3COM, 0x1003, PHY_ID_XXX },     3C997T */
2432         { PCI_VENDOR_ID_3COM, 0x1004, PHY_ID_SERDES  }, /* 3C996SX */
2433         /* { PCI_VENDOR_ID_3COM, 0x1005, PHY_ID_XXX },     3C997SZ */
2434         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
2435         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
2436
2437         /* DELL boards. */
2438         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
2439         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
2440         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
2441         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
2442         { PCI_VENDOR_ID_DELL, 0x0179, PHY_ID_BCM5751 }, /* EtherXpress */
2443
2444         /* Fujitsu Siemens Computer */
2445         { PCI_VENDOR_ID_FSC, 0x105d, PHY_ID_BCM5751 }, /* Futro C200 */
2446
2447         /* Compaq boards. */
2448         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
2449         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
2450         { PCI_VENDOR_ID_COMPAQ, 0x007d, PHY_ID_SERDES  }, /* CHANGELING */
2451         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
2452         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }  /* NC7780_2 */
2453 };
2454
2455 static int tg3_phy_probe(struct tg3 *tp)
2456 {
2457         uint32_t eeprom_phy_id, hw_phy_id_1, hw_phy_id_2;
2458         uint32_t hw_phy_id, hw_phy_id_masked;
2459         enum phy_led_mode eeprom_led_mode;
2460         uint32_t val;
2461         unsigned i;
2462         int eeprom_signature_found, err;
2463
2464         tp->phy_id = PHY_ID_INVALID;
2465
2466         for (i = 0; i < sizeof(subsys_id_to_phy_id)/sizeof(subsys_id_to_phy_id[0]); i++) {
2467                 if ((subsys_id_to_phy_id[i].subsys_vendor == tp->subsystem_vendor) &&
2468                         (subsys_id_to_phy_id[i].subsys_devid == tp->subsystem_device)) {
2469                         tp->phy_id = subsys_id_to_phy_id[i].phy_id;
2470                         break;
2471                 }
2472         }
2473
2474         eeprom_phy_id = PHY_ID_INVALID;
2475         eeprom_led_mode = led_mode_auto;
2476         eeprom_signature_found = 0;
2477         tg3_read_mem(NIC_SRAM_DATA_SIG, &val);
2478         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
2479                 uint32_t nic_cfg;
2480
2481                 tg3_read_mem(NIC_SRAM_DATA_CFG, &nic_cfg);
2482                 tp->nic_sram_data_cfg = nic_cfg;
2483
2484                 eeprom_signature_found = 1;
2485
2486                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
2487                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER) {
2488                         eeprom_phy_id = PHY_ID_SERDES;
2489                 } else {
2490                         uint32_t nic_phy_id;
2491
2492                         tg3_read_mem(NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
2493                         if (nic_phy_id != 0) {
2494                                 uint32_t id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
2495                                 uint32_t id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
2496
2497                                 eeprom_phy_id  = (id1 >> 16) << 10;
2498                                 eeprom_phy_id |= (id2 & 0xfc00) << 16;
2499                                 eeprom_phy_id |= (id2 & 0x03ff) <<  0;
2500                         }
2501                 }
2502
2503                 switch (nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK) {
2504                 case NIC_SRAM_DATA_CFG_LED_TRIPLE_SPD:
2505                         eeprom_led_mode = led_mode_three_link;
2506                         break;
2507
2508                 case NIC_SRAM_DATA_CFG_LED_LINK_SPD:
2509                         eeprom_led_mode = led_mode_link10;
2510                         break;
2511
2512                 default:
2513                         eeprom_led_mode = led_mode_auto;
2514                         break;
2515                 };
2516                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) ||
2517                         (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
2518                         (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) &&
2519                         (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP)) {
2520                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
2521                 }
2522
2523                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE)
2524                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
2525                 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
2526                         tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
2527         }
2528
2529         /* Now read the physical PHY_ID from the chip and verify
2530          * that it is sane.  If it doesn't look good, we fall back
2531          * to either the hard-coded table based PHY_ID and failing
2532          * that the value found in the eeprom area.
2533          */
2534         err  = tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
2535         err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
2536
2537         hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
2538         hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
2539         hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
2540
2541         hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
2542
2543         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
2544                 tp->phy_id = hw_phy_id;
2545         } else {
2546                 /* phy_id currently holds the value found in the
2547                  * subsys_id_to_phy_id[] table or PHY_ID_INVALID
2548                  * if a match was not found there.
2549                  */
2550                 if (tp->phy_id == PHY_ID_INVALID) {
2551                         if (!eeprom_signature_found ||
2552                             !KNOWN_PHY_ID(eeprom_phy_id & PHY_ID_MASK))
2553                                 return -ENODEV;
2554                         tp->phy_id = eeprom_phy_id;
2555                 }
2556         }
2557
2558         err = tg3_phy_reset(tp);
2559         if (err)
2560                 return err;
2561
2562         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2563             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
2564                 uint32_t mii_tg3_ctrl;
2565
2566                 /* These chips, when reset, only advertise 10Mb
2567                  * capabilities.  Fix that.
2568                  */
2569                 err  = tg3_writephy(tp, MII_ADVERTISE,
2570                                     (ADVERTISE_CSMA |
2571                                      ADVERTISE_PAUSE_CAP |
2572                                      ADVERTISE_10HALF |
2573                                      ADVERTISE_10FULL |
2574                                      ADVERTISE_100HALF |
2575                                      ADVERTISE_100FULL));
2576                 mii_tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
2577                                 MII_TG3_CTRL_ADV_1000_FULL |
2578                                 MII_TG3_CTRL_AS_MASTER |
2579                                 MII_TG3_CTRL_ENABLE_AS_MASTER);
2580                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2581                         mii_tg3_ctrl = 0;
2582
2583                 err |= tg3_writephy(tp, MII_TG3_CTRL, mii_tg3_ctrl);
2584                 err |= tg3_writephy(tp, MII_BMCR,
2585                                     (BMCR_ANRESTART | BMCR_ANENABLE));
2586         }
2587
2588         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
2589                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2590                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2591                 tg3_writedsp(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
2592         }
2593
2594         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2595                 tg3_writephy(tp, 0x1c, 0x8d68);
2596                 tg3_writephy(tp, 0x1c, 0x8d68);
2597         }
2598
2599         /* Enable Ethernet@WireSpeed */
2600         tg3_phy_set_wirespeed(tp);
2601
2602         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
2603                 err = tg3_init_5401phy_dsp(tp);
2604         }
2605
2606         /* Determine the PHY led mode.
2607          * Be careful if this gets set wrong it can result in an inability to
2608          * establish a link.
2609          */
2610         if (tp->phy_id == PHY_ID_SERDES) {
2611                 tp->led_mode = led_mode_three_link;
2612         }
2613         else if (tp->subsystem_vendor == PCI_VENDOR_ID_DELL) {
2614                 tp->led_mode = led_mode_link10;
2615         } else {
2616                 tp->led_mode = led_mode_three_link;
2617                 if (eeprom_signature_found &&
2618                     eeprom_led_mode != led_mode_auto)
2619                         tp->led_mode = eeprom_led_mode;
2620         }
2621
2622         if (tp->phy_id == PHY_ID_SERDES)
2623                 tp->link_config.advertising =
2624                         (ADVERTISED_1000baseT_Half |
2625                          ADVERTISED_1000baseT_Full |
2626                          ADVERTISED_Autoneg |
2627                          ADVERTISED_FIBRE);
2628         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2629                 tp->link_config.advertising &=
2630                         ~(ADVERTISED_1000baseT_Half |
2631                           ADVERTISED_1000baseT_Full);
2632
2633         return err;
2634 }
2635
2636 #if SUPPORT_PARTNO_STR
2637 static void tg3_read_partno(struct tg3 *tp)
2638 {
2639         unsigned char vpd_data[256];
2640         int i;
2641
2642         for (i = 0; i < 256; i += 4) {
2643                 uint32_t tmp;
2644
2645                 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
2646                         goto out_not_found;
2647
2648                 vpd_data[i + 0] = ((tmp >>  0) & 0xff);
2649                 vpd_data[i + 1] = ((tmp >>  8) & 0xff);
2650                 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
2651                 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
2652         }
2653
2654         /* Now parse and find the part number. */
2655         for (i = 0; i < 256; ) {
2656                 unsigned char val = vpd_data[i];
2657                 int block_end;
2658
2659                 if (val == 0x82 || val == 0x91) {
2660                         i = (i + 3 +
2661                              (vpd_data[i + 1] +
2662                               (vpd_data[i + 2] << 8)));
2663                         continue;
2664                 }
2665
2666                 if (val != 0x90)
2667                         goto out_not_found;
2668
2669                 block_end = (i + 3 +
2670                              (vpd_data[i + 1] +
2671                               (vpd_data[i + 2] << 8)));
2672                 i += 3;
2673                 while (i < block_end) {
2674                         if (vpd_data[i + 0] == 'P' &&
2675                             vpd_data[i + 1] == 'N') {
2676                                 int partno_len = vpd_data[i + 2];
2677
2678                                 if (partno_len > 24)
2679                                         goto out_not_found;
2680
2681                                 memcpy(tp->board_part_number,
2682                                        &vpd_data[i + 3],
2683                                        partno_len);
2684
2685                                 /* Success. */
2686                                 return;
2687                         }
2688                 }
2689
2690                 /* Part number not found. */
2691                 goto out_not_found;
2692         }
2693
2694 out_not_found:
2695         memcpy(tp->board_part_number, "none", sizeof("none"));
2696 }
2697 #else
2698 #define tg3_read_partno(TP) ((TP)->board_part_number[0] = '\0')
2699 #endif
2700
2701 static int tg3_get_invariants(struct tg3 *tp)
2702 {
2703         uint32_t misc_ctrl_reg;
2704         uint32_t pci_state_reg, grc_misc_cfg;
2705         uint16_t pci_cmd;
2706         uint8_t  pci_latency;
2707         uint32_t val ;
2708         int err;
2709
2710         /* Read the subsystem vendor and device ids */
2711         pci_read_config_word(tp->pdev, PCI_SUBSYSTEM_VENDOR_ID, &tp->subsystem_vendor);
2712         pci_read_config_word(tp->pdev, PCI_SUBSYSTEM_ID, &tp->subsystem_device);
2713
2714         /* The sun_5704 code needs infrastructure etherboot does have
2715          * ignore it for now.
2716          */
2717
2718         /* If we have an AMD 762 or Intel ICH/ICH0 chipset, write
2719          * reordering to the mailbox registers done by the host
2720          * controller can cause major troubles.  We read back from
2721          * every mailbox register write to force the writes to be
2722          * posted to the chip in order.
2723          *
2724          * TG3_FLAG_MBOX_WRITE_REORDER has been forced on.
2725          */
2726
2727         /* Force memory write invalidate off.  If we leave it on,
2728          * then on 5700_BX chips we have to enable a workaround.
2729          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundry
2730          * to match the cacheline size.  The Broadcom driver have this
2731          * workaround but turns MWI off all the times so never uses
2732          * it.  This seems to suggest that the workaround is insufficient.
2733          */
2734         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
2735         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
2736         /* Also, force SERR#/PERR# in PCI command. */
2737         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
2738         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
2739
2740         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
2741          * has the register indirect write enable bit set before
2742          * we try to access any of the MMIO registers.  It is also
2743          * critical that the PCI-X hw workaround situation is decided
2744          * before that as well.
2745          */
2746         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, &misc_ctrl_reg);
2747
2748         tp->pci_chip_rev_id = (misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT);
2749
2750         /* Initialize misc host control in PCI block. */
2751         tp->misc_host_ctrl |= (misc_ctrl_reg &
2752                                MISC_HOST_CTRL_CHIPREV);
2753         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
2754                                tp->misc_host_ctrl);
2755
2756         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, &pci_latency);
2757         if (pci_latency < 64) {
2758                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, 64);
2759         }
2760
2761         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &pci_state_reg);
2762
2763         /* If this is a 5700 BX chipset, and we are in PCI-X
2764          * mode, enable register write workaround.
2765          *
2766          * The workaround is to use indirect register accesses
2767          * for all chip writes not to mailbox registers.
2768          *
2769          * In etherboot to simplify things we just always use this work around.
2770          */
2771         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
2772                 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
2773         }
2774         /* Back to back register writes can cause problems on the 5701,
2775          * the workaround is to read back all reg writes except those to
2776          * mailbox regs.
2777          * In etherboot we always use indirect register accesses so
2778          * we don't see this.
2779          */
2780
2781         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
2782                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
2783         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
2784                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
2785
2786         /* Chip-specific fixup from Broadcom driver */
2787         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
2788             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
2789                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
2790                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
2791         }
2792
2793         /* determine if it is PCIE system */
2794         // Alf : I have no idea what this is about...
2795         // But it's definitely usefull
2796         val = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
2797         if (val)
2798                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
2799
2800         /* Force the chip into D0. */
2801         tg3_set_power_state_0(tp);
2802
2803         /* Etherboot does not ask the tg3 to do checksums */
2804         /* Etherboot does not ask the tg3 to do jumbo frames */
2805         /* Ehterboot does not ask the tg3 to use WakeOnLan. */
2806
2807         /* A few boards don't want Ethernet@WireSpeed phy feature */
2808         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
2809             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
2810                 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2811                         (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
2812                         (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1))) {
2813                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
2814         }
2815
2816         /* Avoid tagged irq status etherboot does not use irqs */
2817
2818         /* Only 5701 and later support tagged irq status mode.
2819          * Also, 5788 chips cannot use tagged irq status.
2820          *
2821          * However, since etherboot does not use irqs avoid tagged irqs
2822          * status  because the interrupt condition is more difficult to
2823          * fully clear in that mode.
2824          */
2825
2826         /* Since some 5700_AX && 5700_BX have problems with 32BYTE
2827          * coalesce_mode, and the rest work fine anything set.
2828          * Don't enable HOST_CC_MODE_32BYTE in etherboot.
2829          */
2830
2831         /* Initialize MAC MI mode, polling disabled. */
2832         tw32_carefully(MAC_MI_MODE, tp->mi_mode);
2833
2834         /* Initialize data/descriptor byte/word swapping. */
2835         tw32(GRC_MODE, tp->grc_mode);
2836
2837         tg3_switch_clocks(tp);
2838
2839         /* Clear this out for sanity. */
2840         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
2841
2842         /* Etherboot does not need to check if the PCIX_TARGET_HWBUG
2843          * is needed.  It always uses it.
2844          */
2845
2846         udelay(50);
2847         tg3_nvram_init(tp);
2848
2849         /* The TX descriptors will reside in main memory.
2850          */
2851
2852         /* See which board we are using.
2853          */
2854         grc_misc_cfg = tr32(GRC_MISC_CFG);
2855         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
2856
2857         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
2858             grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5704CIOBE) {
2859                 tp->tg3_flags |= TG3_FLAG_SPLIT_MODE;
2860                 tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ;
2861         }
2862
2863         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
2864             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
2865              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
2866                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
2867
2868 #define PCI_DEVICE_ID_TIGON3_5901       0x170d
2869 #define PCI_DEVICE_ID_TIGON3_5901_2     0x170e
2870
2871         /* these are limited to 10/100 only */
2872         if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) &&
2873                     ((grc_misc_cfg == 0x8000) || (grc_misc_cfg == 0x4000))) ||
2874                 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2875                         (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM) &&
2876                         ((tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901) ||
2877                                 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2)))) {
2878                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
2879         }
2880
2881         err = tg3_phy_probe(tp);
2882         if (err) {
2883                 printf("phy probe failed, err %d\n", err);
2884         }
2885
2886         tg3_read_partno(tp);
2887
2888
2889         /* 5700 BX chips need to have their TX producer index mailboxes
2890          * written twice to workaround a bug.
2891          * In etherboot we do this unconditionally to simplify things.
2892          */
2893
2894         /* 5700 chips can get confused if TX buffers straddle the
2895          * 4GB address boundary in some cases.
2896          *
2897          * In etherboot we can ignore the problem as etherboot lives below 4GB.
2898          */
2899
2900         /* In etherboot wake-on-lan is unconditionally disabled */
2901         return err;
2902 }
2903
2904 static int  tg3_get_device_address(struct tg3 *tp)
2905 {
2906         struct nic *nic = tp->nic;
2907         uint32_t hi, lo, mac_offset;
2908
2909         if (PCI_FUNC(tp->pdev->devfn) == 0)
2910                 mac_offset = 0x7c;
2911         else
2912                 mac_offset = 0xcc;
2913
2914         /* First try to get it from MAC address mailbox. */
2915         tg3_read_mem(NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
2916         if ((hi >> 16) == 0x484b) {
2917                 nic->node_addr[0] = (hi >>  8) & 0xff;
2918                 nic->node_addr[1] = (hi >>  0) & 0xff;
2919
2920                 tg3_read_mem(NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
2921                 nic->node_addr[2] = (lo >> 24) & 0xff;
2922                 nic->node_addr[3] = (lo >> 16) & 0xff;
2923                 nic->node_addr[4] = (lo >>  8) & 0xff;
2924                 nic->node_addr[5] = (lo >>  0) & 0xff;
2925         }
2926         /* Next, try NVRAM. */
2927         else if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
2928                  !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
2929                 nic->node_addr[0] = ((hi >> 16) & 0xff);
2930                 nic->node_addr[1] = ((hi >> 24) & 0xff);
2931                 nic->node_addr[2] = ((lo >>  0) & 0xff);
2932                 nic->node_addr[3] = ((lo >>  8) & 0xff);
2933                 nic->node_addr[4] = ((lo >> 16) & 0xff);
2934                 nic->node_addr[5] = ((lo >> 24) & 0xff);
2935         }
2936         /* Finally just fetch it out of the MAC control regs. */
2937         else {
2938                 hi = tr32(MAC_ADDR_0_HIGH);
2939                 lo = tr32(MAC_ADDR_0_LOW);
2940
2941                 nic->node_addr[5] = lo & 0xff;
2942                 nic->node_addr[4] = (lo >> 8) & 0xff;
2943                 nic->node_addr[3] = (lo >> 16) & 0xff;
2944                 nic->node_addr[2] = (lo >> 24) & 0xff;
2945                 nic->node_addr[1] = hi & 0xff;
2946                 nic->node_addr[0] = (hi >> 8) & 0xff;
2947         }
2948
2949         return 0;
2950 }
2951
2952
2953 static int tg3_setup_dma(struct tg3 *tp)
2954 {
2955         tw32(TG3PCI_CLOCK_CTRL, 0);
2956
2957         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) == 0) {
2958                 tp->dma_rwctrl =
2959                         (0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
2960                         (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT) |
2961                         (0x7 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
2962                         (0x7 << DMA_RWCTRL_READ_WATER_SHIFT) |
2963                         (0x0f << DMA_RWCTRL_MIN_DMA_SHIFT);
2964                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2965                         tp->dma_rwctrl &= ~(DMA_RWCTRL_MIN_DMA << DMA_RWCTRL_MIN_DMA_SHIFT);
2966                 }
2967         } else {
2968                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
2969                         tp->dma_rwctrl =
2970                                 (0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
2971                                 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT) |
2972                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
2973                                 (0x7 << DMA_RWCTRL_READ_WATER_SHIFT) |
2974                                 (0x00 << DMA_RWCTRL_MIN_DMA_SHIFT);
2975                 else
2976                         tp->dma_rwctrl =
2977                                 (0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
2978                                 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT) |
2979                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
2980                                 (0x3 << DMA_RWCTRL_READ_WATER_SHIFT) |
2981                                 (0x0f << DMA_RWCTRL_MIN_DMA_SHIFT);
2982
2983                 /* Wheee, some more chip bugs... */
2984                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) ||
2985                         (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)) {
2986                         uint32_t ccval = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
2987
2988                         if ((ccval == 0x6) || (ccval == 0x7)) {
2989                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
2990                         }
2991                 }
2992         }
2993
2994         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) ||
2995                 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)) {
2996                 tp->dma_rwctrl &= ~(DMA_RWCTRL_MIN_DMA << DMA_RWCTRL_MIN_DMA_SHIFT);
2997         }
2998
2999         /*
3000           Alf : Tried that, but it does not work. Should be this way though :-(
3001         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
3002           tp->dma_rwctrl |= 0x001f0000;
3003         }
3004         */
3005         tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
3006
3007         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
3008
3009         return 0;
3010 }
3011
3012 static void tg3_init_link_config(struct tg3 *tp)
3013 {
3014         tp->link_config.advertising =
3015                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3016                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3017                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
3018                  ADVERTISED_Autoneg | ADVERTISED_MII);
3019         tp->carrier_ok = 0;
3020         tp->link_config.active_speed = SPEED_INVALID;
3021         tp->link_config.active_duplex = DUPLEX_INVALID;
3022 }
3023
3024
3025 #if SUPPORT_PHY_STR
3026 static const char * tg3_phy_string(struct tg3 *tp)
3027 {
3028         switch (tp->phy_id & PHY_ID_MASK) {
3029         case PHY_ID_BCM5400:    return "5400";
3030         case PHY_ID_BCM5401:    return "5401";
3031         case PHY_ID_BCM5411:    return "5411";
3032         case PHY_ID_BCM5701:    return "5701";
3033         case PHY_ID_BCM5703:    return "5703";
3034         case PHY_ID_BCM5704:    return "5704";
3035         case PHY_ID_BCM5705:    return "5705";
3036         case PHY_ID_BCM5750:    return "5750";
3037         case PHY_ID_BCM5751:    return "5751";
3038         case PHY_ID_BCM5787:    return "5787";
3039         case PHY_ID_BCM8002:    return "8002/serdes";
3040         case PHY_ID_SERDES:     return "serdes";
3041         default:                return "unknown";
3042         };
3043 }
3044 #else
3045 #define tg3_phy_string(TP) "?"
3046 #endif
3047
3048
3049 static void tg3_poll_link(struct tg3 *tp)
3050 {
3051         uint32_t mac_stat;
3052
3053         mac_stat = tr32(MAC_STATUS);
3054         if (tp->phy_id == PHY_ID_SERDES) {
3055                 if (tp->carrier_ok?
3056                         (mac_stat & MAC_STATUS_LNKSTATE_CHANGED):
3057                         (mac_stat & MAC_STATUS_PCS_SYNCED)) {
3058                         tw32_carefully(MAC_MODE, tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK);
3059                         tw32_carefully(MAC_MODE, tp->mac_mode);
3060
3061                         tg3_setup_phy(tp);
3062                 }
3063         }
3064         else {
3065                 if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED) {
3066                         tg3_setup_phy(tp);
3067                 }
3068         }
3069 }
3070
3071 /**************************************************************************
3072 POLL - Wait for a frame
3073 ***************************************************************************/
3074 static void tg3_ack_irqs(struct tg3 *tp)
3075 {
3076         if (tp->hw_status->status & SD_STATUS_UPDATED) {
3077                 /*
3078                  * writing any value to intr-mbox-0 clears PCI INTA# and
3079                  * chip-internal interrupt pending events.
3080                  * writing non-zero to intr-mbox-0 additional tells the
3081                  * NIC to stop sending us irqs, engaging "in-intr-handler"
3082                  * event coalescing.
3083                  */
3084                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3085                         0x00000001);
3086                 /*
3087                  * Flush PCI write.  This also guarantees that our
3088                  * status block has been flushed to host memory.
3089                  */
3090                 tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
3091                 tp->hw_status->status &= ~SD_STATUS_UPDATED;
3092         }
3093 }
3094
3095 static int tg3_poll(struct nic *nic, int retrieve)
3096 {
3097         /* return true if there's an ethernet packet ready to read */
3098         /* nic->packet should contain data on return */
3099         /* nic->packetlen should contain length of data */
3100
3101         struct tg3 *tp = &tg3;
3102         int result;
3103
3104         result = 0;
3105
3106         if ( (tp->hw_status->idx[0].rx_producer != tp->rx_rcb_ptr) && !retrieve )
3107           return 1;
3108
3109         tg3_ack_irqs(tp);
3110
3111         if (tp->hw_status->idx[0].rx_producer != tp->rx_rcb_ptr) {
3112                 struct tg3_rx_buffer_desc *desc;
3113                 unsigned int len;
3114                 desc = &tp->rx_rcb[tp->rx_rcb_ptr];
3115                 if ((desc->opaque & RXD_OPAQUE_RING_MASK) == RXD_OPAQUE_RING_STD) {
3116                         len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3117
3118                         nic->packetlen = len;
3119                         memcpy(nic->packet, bus_to_virt(desc->addr_lo), len);
3120                         result = 1;
3121                 }
3122                 tp->rx_rcb_ptr = (tp->rx_rcb_ptr + 1) % TG3_RX_RCB_RING_SIZE;
3123
3124                 /* ACK the status ring */
3125                 tw32_mailbox2(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, tp->rx_rcb_ptr);
3126
3127                 /* Refill RX ring. */
3128                 if (result) {
3129                         tp->rx_std_ptr = (tp->rx_std_ptr + 1) % TG3_RX_RING_SIZE;
3130                         tw32_mailbox2(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW, tp->rx_std_ptr);
3131                 }
3132         }
3133         tg3_poll_link(tp);
3134         return result;
3135 }
3136
3137 /**************************************************************************
3138 TRANSMIT - Transmit a frame
3139 ***************************************************************************/
3140 #if 0
3141 static void tg3_set_txd(struct tg3 *tp, int entry,
3142         dma_addr_t mapping, int len, uint32_t flags,
3143         uint32_t mss_and_is_end)
3144 {
3145         struct tg3_tx_buffer_desc *txd =  &tp->tx_ring[entry];
3146         int is_end = (mss_and_is_end & 0x1);
3147         if (is_end) {
3148                 flags |= TXD_FLAG_END;
3149         }
3150
3151         txd->addr_hi   = 0;
3152         txd->addr_lo   = mapping & 0xffffffff;
3153         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3154         txd->vlan_tag  = 0 << TXD_VLAN_TAG_SHIFT;
3155 }
3156 #endif
3157
3158 static void tg3_transmit(struct nic *nic, const char *dst_addr,
3159         unsigned int type, unsigned int size, const char *packet)
3160 {
3161         static int frame_idx;
3162         struct eth_frame *frame;
3163
3164         /* send the packet to destination */
3165         struct tg3_tx_buffer_desc *txd;
3166         struct tg3 *tp;
3167         uint32_t entry;
3168         int i;
3169
3170         /* Wait until there is a free packet frame */
3171         tp = &tg3;
3172         i = 0;
3173         entry = tp->tx_prod;
3174         while((tp->hw_status->idx[0].tx_consumer != entry) &&
3175                 (tp->hw_status->idx[0].tx_consumer != PREV_TX(entry))) {
3176                 mdelay(10);     /* give the nick a chance */
3177                 if (++i > 500) { /* timeout 5s for transmit */
3178                         printf("transmit timed out\n");
3179                         tg3_halt(tp);
3180                         tg3_setup_hw(tp);
3181                         return;
3182                 }
3183         }
3184         if (i != 0) {
3185                 printf("#");
3186         }
3187
3188         /* Copy the packet to the our local buffer */
3189         frame = &tg3_bss.tx_frame[frame_idx];
3190         memcpy(frame->dst_addr, dst_addr, ETH_ALEN);
3191         memcpy(frame->src_addr, nic->node_addr, ETH_ALEN);
3192         frame->type = htons(type);
3193         memset(frame->data, 0, sizeof(frame->data));
3194         memcpy(frame->data, packet, size);
3195
3196         /* Setup the ring buffer entry to transmit */
3197         txd            = &tp->tx_ring[entry];
3198         txd->addr_hi   = 0; /* Etherboot runs under 4GB */
3199         txd->addr_lo   = virt_to_bus(frame);
3200         txd->len_flags = ((size + ETH_HLEN) << TXD_LEN_SHIFT) | TXD_FLAG_END;
3201         txd->vlan_tag  = 0 << TXD_VLAN_TAG_SHIFT;
3202
3203         /* Advance to the next entry */
3204         entry = NEXT_TX(entry);
3205         frame_idx ^= 1;
3206
3207         /* Packets are ready, update Tx producer idx local and on card */
3208         tw32_mailbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3209         tw32_mailbox2((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3210         tp->tx_prod = entry;
3211 }
3212
3213 /**************************************************************************
3214 DISABLE - Turn off ethernet interface
3215 ***************************************************************************/
3216 static void tg3_disable ( struct nic *nic __unused ) {
3217         struct tg3 *tp = &tg3;
3218         /* put the card in its initial state */
3219         /* This function serves 3 purposes.
3220          * This disables DMA and interrupts so we don't receive
3221          *  unexpected packets or interrupts from the card after
3222          *  etherboot has finished.
3223          * This frees resources so etherboot may use
3224          *  this driver on another interface
3225          * This allows etherboot to reinitialize the interface
3226          *  if something is something goes wrong.
3227          */
3228         tg3_halt(tp);
3229         tp->tg3_flags &= ~(TG3_FLAG_INIT_COMPLETE|TG3_FLAG_GOT_SERDES_FLOWCTL);
3230         tp->carrier_ok = 0;
3231         iounmap((void *)tp->regs);
3232 }
3233
3234 /**************************************************************************
3235 IRQ - Enable, Disable, or Force interrupts
3236 ***************************************************************************/
3237 static void tg3_irq(struct nic *nic __unused, irq_action_t action __unused)
3238 {
3239   switch ( action ) {
3240   case DISABLE :
3241     break;
3242   case ENABLE :
3243     break;
3244   case FORCE :
3245     break;
3246   }
3247 }
3248
3249 static struct nic_operations tg3_operations = {
3250         .connect        = dummy_connect,
3251         .poll           = tg3_poll,
3252         .transmit       = tg3_transmit,
3253         .irq            = tg3_irq,
3254
3255 };
3256
3257 /**************************************************************************
3258 PROBE - Look for an adapter, this routine's visible to the outside
3259 You should omit the last argument struct pci_device * for a non-PCI NIC
3260 ***************************************************************************/
3261 static int tg3_probe ( struct nic *nic, struct pci_device *pdev ) {
3262
3263         struct tg3 *tp = &tg3;
3264         unsigned long tg3reg_base, tg3reg_len;
3265         int i, err, pm_cap;
3266
3267         memset(tp, 0, sizeof(*tp));
3268
3269         adjust_pci_device(pdev);
3270
3271         nic->irqno  = 0;
3272         nic->ioaddr = pdev->ioaddr;
3273
3274         /* Find power-management capability. */
3275         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3276         if (pm_cap == 0) {
3277                 printf("Cannot find PowerManagement capability, aborting.\n");
3278                 return 0;
3279         }
3280         tg3reg_base = pci_bar_start(pdev, PCI_BASE_ADDRESS_0);
3281         if (tg3reg_base == -1UL) {
3282                 printf("Unuseable bar\n");
3283                 return 0;
3284         }
3285         tg3reg_len  = pci_bar_size(pdev,  PCI_BASE_ADDRESS_0);
3286
3287         tp->pdev       = pdev;
3288         tp->nic        = nic;
3289         tp->pm_cap     = pm_cap;
3290         tp->rx_mode    = 0;
3291         tp->tx_mode    = 0;
3292         tp->mi_mode    = MAC_MI_MODE_BASE;
3293         tp->tg3_flags  = 0 & ~TG3_FLAG_INIT_COMPLETE;
3294
3295         /* The word/byte swap controls here control register access byte
3296          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
3297          * setting below.
3298          */
3299         tp->misc_host_ctrl =
3300                 MISC_HOST_CTRL_MASK_PCI_INT |
3301                 MISC_HOST_CTRL_WORD_SWAP |
3302                 MISC_HOST_CTRL_INDIR_ACCESS |
3303                 MISC_HOST_CTRL_PCISTATE_RW;
3304
3305         /* The NONFRM (non-frame) byte/word swap controls take effect
3306          * on descriptor entries, anything which isn't packet data.
3307          *
3308          * The StrongARM chips on the board (one for tx, one for rx)
3309          * are running in big-endian mode.
3310          */
3311         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
3312                         GRC_MODE_WSWAP_NONFRM_DATA);
3313 #if __BYTE_ORDER == __BIG_ENDIAN
3314         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
3315 #endif
3316         tp->regs = (unsigned long) ioremap(tg3reg_base, tg3reg_len);
3317         if (tp->regs == 0UL) {
3318                 printf("Cannot map device registers, aborting\n");
3319                 return 0;
3320         }
3321
3322         tg3_init_link_config(tp);
3323
3324         err = tg3_get_invariants(tp);
3325         if (err) {
3326                 printf("Problem fetching invariants of chip, aborting.\n");
3327                 goto err_out_iounmap;
3328         }
3329
3330         err = tg3_get_device_address(tp);
3331         if (err) {
3332                 printf("Could not obtain valid ethernet address, aborting.\n");
3333                 goto err_out_iounmap;
3334         }
3335
3336         DBG ( "Ethernet addr: %s\n", eth_ntoa ( nic->node_addr ) );
3337
3338         tg3_setup_dma(tp);
3339
3340         /* Now that we have fully setup the chip, save away a snapshot
3341          * of the PCI config space.  We need to restore this after
3342          * GRC_MISC_CFG core clock resets and some resume events.
3343          */
3344         pci_save_state(tp->pdev, tp->pci_cfg_state);
3345
3346         printf("Tigon3 [partno(%s) rev %hx PHY(%s)] (PCI%s:%s:%s)\n",
3347                 tp->board_part_number,
3348                 tp->pci_chip_rev_id,
3349                 tg3_phy_string(tp),
3350                 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "X" : ""),
3351                 ((tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED) ?
3352                         ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "133MHz" : "66MHz") :
3353                         ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "100MHz" : "33MHz")),
3354                 ((tp->tg3_flags & TG3_FLAG_PCI_32BIT) ? "32-bit" : "64-bit"));
3355
3356
3357         err = tg3_setup_hw(tp);
3358         if (err) {
3359                 goto err_out_disable;
3360         }
3361         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
3362
3363         /* Wait for a reasonable time for the link to come up */
3364         tg3_poll_link(tp);
3365         for(i = 0; !tp->carrier_ok && (i < VALID_LINK_TIMEOUT*100); i++) {
3366                 mdelay(1);
3367                 tg3_poll_link(tp);
3368         }
3369         if (!tp->carrier_ok){
3370                 printf("Valid link not established\n");
3371                 goto err_out_disable;
3372         }
3373
3374         nic->nic_op     = &tg3_operations;
3375         return 1;
3376
3377  err_out_iounmap:
3378         iounmap((void *)tp->regs);
3379         return 0;
3380  err_out_disable:
3381         tg3_disable(nic);
3382         return 0;
3383 }
3384
3385
3386 static struct pci_device_id tg3_nics[] = {
3387 PCI_ROM(0x14e4, 0x1644, "tg3-5700",        "Broadcom Tigon 3 5700"),
3388 PCI_ROM(0x14e4, 0x1645, "tg3-5701",        "Broadcom Tigon 3 5701"),
3389 PCI_ROM(0x14e4, 0x1646, "tg3-5702",        "Broadcom Tigon 3 5702"),
3390 PCI_ROM(0x14e4, 0x1647, "tg3-5703",        "Broadcom Tigon 3 5703"),
3391 PCI_ROM(0x14e4, 0x1648, "tg3-5704",        "Broadcom Tigon 3 5704"),
3392 PCI_ROM(0x14e4, 0x164d, "tg3-5702FE",      "Broadcom Tigon 3 5702FE"),
3393 PCI_ROM(0x14e4, 0x1653, "tg3-5705",        "Broadcom Tigon 3 5705"),
3394 PCI_ROM(0x14e4, 0x1654, "tg3-5705_2",      "Broadcom Tigon 3 5705_2"),
3395 PCI_ROM(0x14e4, 0x1659, "tg3-5721",        "Broadcom Tigon 3 5721"),
3396 PCI_ROM(0x14e4, 0x165d, "tg3-5705M",       "Broadcom Tigon 3 5705M"),
3397 PCI_ROM(0x14e4, 0x165e, "tg3-5705M_2",     "Broadcom Tigon 3 5705M_2"),
3398 PCI_ROM(0x14e4, 0x1677, "tg3-5751",        "Broadcom Tigon 3 5751"),
3399 PCI_ROM(0x14e4, 0x167a, "tg3-5754",        "Broadcom Tigon 3 5754"),
3400 PCI_ROM(0x14e4, 0x1693, "tg3-5787",        "Broadcom Tigon 3 5787"),
3401 PCI_ROM(0x14e4, 0x1696, "tg3-5782",        "Broadcom Tigon 3 5782"),
3402 PCI_ROM(0x14e4, 0x169a, "tg3-5786",        "Broadcom Tigon 3 5786"),
3403 PCI_ROM(0x14e4, 0x169c, "tg3-5788",        "Broadcom Tigon 3 5788"),
3404 PCI_ROM(0x14e4, 0x169d, "tg3-5789",        "Broadcom Tigon 3 5789"),
3405 PCI_ROM(0x14e4, 0x16a6, "tg3-5702X",       "Broadcom Tigon 3 5702X"),
3406 PCI_ROM(0x14e4, 0x16a7, "tg3-5703X",       "Broadcom Tigon 3 5703X"),
3407 PCI_ROM(0x14e4, 0x16a8, "tg3-5704S",       "Broadcom Tigon 3 5704S"),
3408 PCI_ROM(0x14e4, 0x16c6, "tg3-5702A3",      "Broadcom Tigon 3 5702A3"),
3409 PCI_ROM(0x14e4, 0x16c7, "tg3-5703A3",      "Broadcom Tigon 3 5703A3"),
3410 PCI_ROM(0x14e4, 0x170d, "tg3-5901",        "Broadcom Tigon 3 5901"),
3411 PCI_ROM(0x14e4, 0x170e, "tg3-5901_2",      "Broadcom Tigon 3 5901_2"),
3412 PCI_ROM(0x1148, 0x4400, "tg3-9DXX",        "Syskonnect 9DXX"),
3413 PCI_ROM(0x1148, 0x4500, "tg3-9MXX",        "Syskonnect 9MXX"),
3414 PCI_ROM(0x173b, 0x03e8, "tg3-ac1000",      "Altima AC1000"),
3415 PCI_ROM(0x173b, 0x03e9, "tg3-ac1001",      "Altima AC1001"),
3416 PCI_ROM(0x173b, 0x03ea, "tg3-ac9100",      "Altima AC9100"),
3417 PCI_ROM(0x173b, 0x03eb, "tg3-ac1003",      "Altima AC1003"),
3418 PCI_ROM(0x0e11, 0x00ca, "tg3-hp",          "HP Tigon 3"),
3419 };
3420
3421 PCI_DRIVER ( tg3_driver, tg3_nics, PCI_NO_CLASS );
3422
3423 DRIVER ( "TG3", nic_driver, pci_driver, tg3_driver,
3424          tg3_probe, tg3_disable );
3425
3426 /*
3427  * Local variables:
3428  *  c-basic-offset: 8
3429  *  c-indent-level: 8
3430  *  tab-width: 8
3431  * End:
3432  */