13 /* Drag in hardware definitions */
14 #include "nx_bitops.h"
15 #include "phantom_hw.h"
16 struct phantom_rds { NX_PSEUDO_BIT_STRUCT ( struct phantom_rds_pb ) };
17 struct phantom_sds { NX_PSEUDO_BIT_STRUCT ( struct phantom_sds_pb ) };
18 union phantom_cds { NX_PSEUDO_BIT_STRUCT ( union phantom_cds_pb ) };
20 /* Drag in firmware interface definitions */
25 typedef uint32_t nx_rcode_t;
26 #define NXHAL_VERSION 1
27 #include "nxhal_nic_interface.h"
29 /** SPI controller maximum block size */
30 #define UNM_SPI_BLKSIZE 4
32 /** DMA buffer alignment */
33 #define UNM_DMA_BUFFER_ALIGN 16
35 /** Mark structure as DMA-aligned */
36 #define __unm_dma_aligned __attribute__ (( aligned ( UNM_DMA_BUFFER_ALIGN ) ))
38 /** Dummy DMA buffer size */
39 #define UNM_DUMMY_DMA_SIZE 1024
41 /******************************************************************************
43 * Register definitions
47 #define UNM_128M_CRB_WINDOW 0x6110210UL
48 #define UNM_32M_CRB_WINDOW 0x0110210UL
49 #define UNM_2M_CRB_WINDOW 0x0130060UL
52 * Phantom register blocks
54 * The upper address bits vary between cards. We define an abstract
55 * address space in which the upper 8 bits of the 32-bit register
56 * address encode the register block. This gets translated to a bus
57 * address by the phantom_crb_access_xxx() methods.
65 #define UNM_CRB_BASE(blk) ( (blk) << 24 )
66 #define UNM_CRB_BLK(reg) ( (reg) >> 24 )
67 #define UNM_CRB_OFFSET(reg) ( (reg) & 0x00ffffff )
69 #define UNM_CRB_PCIE UNM_CRB_BASE ( UNM_CRB_BLK_PCIE )
70 #define UNM_PCIE_SEM2_LOCK ( UNM_CRB_PCIE + 0x1c010 )
71 #define UNM_PCIE_SEM2_UNLOCK ( UNM_CRB_PCIE + 0x1c014 )
73 #define UNM_CRB_CAM UNM_CRB_BASE ( UNM_CRB_BLK_CAM )
75 #define UNM_CAM_RAM ( UNM_CRB_CAM + 0x02000 )
76 #define UNM_CAM_RAM_PORT_MODE ( UNM_CAM_RAM + 0x00024 )
77 #define UNM_CAM_RAM_PORT_MODE_AUTO_NEG 4
78 #define UNM_CAM_RAM_PORT_MODE_AUTO_NEG_1G 5
79 #define UNM_CAM_RAM_DMESG_HEAD(n) ( UNM_CAM_RAM + 0x00030 + (n) * 0x10 )
80 #define UNM_CAM_RAM_DMESG_LEN(n) ( UNM_CAM_RAM + 0x00034 + (n) * 0x10 )
81 #define UNM_CAM_RAM_DMESG_TAIL(n) ( UNM_CAM_RAM + 0x00038 + (n) * 0x10 )
82 #define UNM_CAM_RAM_DMESG_SIG(n) ( UNM_CAM_RAM + 0x0003c + (n) * 0x10 )
83 #define UNM_CAM_RAM_DMESG_SIG_MAGIC 0xcafebabeUL
84 #define UNM_CAM_RAM_NUM_DMESG_BUFFERS 5
85 #define UNM_CAM_RAM_WOL_PORT_MODE ( UNM_CAM_RAM + 0x00198 )
86 #define UNM_CAM_RAM_MAC_ADDRS ( UNM_CAM_RAM + 0x001c0 )
87 #define UNM_CAM_RAM_COLD_BOOT ( UNM_CAM_RAM + 0x001fc )
88 #define UNM_CAM_RAM_COLD_BOOT_MAGIC 0x55555555UL
90 #define UNM_NIC_REG ( UNM_CRB_CAM + 0x02200 )
91 #define UNM_NIC_REG_NX_CDRP ( UNM_NIC_REG + 0x00018 )
92 #define UNM_NIC_REG_NX_ARG1 ( UNM_NIC_REG + 0x0001c )
93 #define UNM_NIC_REG_NX_ARG2 ( UNM_NIC_REG + 0x00020 )
94 #define UNM_NIC_REG_NX_ARG3 ( UNM_NIC_REG + 0x00024 )
95 #define UNM_NIC_REG_NX_SIGN ( UNM_NIC_REG + 0x00028 )
96 #define UNM_NIC_REG_DUMMY_BUF_ADDR_HI ( UNM_NIC_REG + 0x0003c )
97 #define UNM_NIC_REG_DUMMY_BUF_ADDR_LO ( UNM_NIC_REG + 0x00040 )
98 #define UNM_NIC_REG_CMDPEG_STATE ( UNM_NIC_REG + 0x00050 )
99 #define UNM_NIC_REG_CMDPEG_STATE_INITIALIZED 0xff01
100 #define UNM_NIC_REG_CMDPEG_STATE_INITIALIZE_ACK 0xf00f
101 #define UNM_NIC_REG_DUMMY_BUF ( UNM_NIC_REG + 0x000fc )
102 #define UNM_NIC_REG_DUMMY_BUF_INIT 0
103 #define UNM_NIC_REG_XG_STATE_P3 ( UNM_NIC_REG + 0x00098 )
104 #define UNM_NIC_REG_XG_STATE_P3_LINK( port, state_p3 ) \
105 ( ( (state_p3) >> ( (port) * 4 ) ) & 0x0f )
106 #define UNM_NIC_REG_XG_STATE_P3_LINK_UP 0x01
107 #define UNM_NIC_REG_XG_STATE_P3_LINK_DOWN 0x02
108 #define UNM_NIC_REG_RCVPEG_STATE ( UNM_NIC_REG + 0x0013c )
109 #define UNM_NIC_REG_RCVPEG_STATE_INITIALIZED 0xff01
110 #define UNM_NIC_REG_SW_INT_MASK_0 ( UNM_NIC_REG + 0x001d8 )
111 #define UNM_NIC_REG_SW_INT_MASK_1 ( UNM_NIC_REG + 0x001e0 )
112 #define UNM_NIC_REG_SW_INT_MASK_2 ( UNM_NIC_REG + 0x001e4 )
113 #define UNM_NIC_REG_SW_INT_MASK_3 ( UNM_NIC_REG + 0x001e8 )
115 #define UNM_CRB_ROMUSB UNM_CRB_BASE ( UNM_CRB_BLK_ROMUSB )
117 #define UNM_ROMUSB_GLB ( UNM_CRB_ROMUSB + 0x00000 )
118 #define UNM_ROMUSB_GLB_STATUS ( UNM_ROMUSB_GLB + 0x00004 )
119 #define UNM_ROMUSB_GLB_STATUS_ROM_DONE ( 1 << 1 )
120 #define UNM_ROMUSB_GLB_SW_RESET ( UNM_ROMUSB_GLB + 0x00008 )
121 #define UNM_ROMUSB_GLB_SW_RESET_MAGIC 0x0080000fUL
122 #define UNM_ROMUSB_GLB_PEGTUNE_DONE ( UNM_ROMUSB_GLB + 0x0005c )
124 #define UNM_ROMUSB_ROM ( UNM_CRB_ROMUSB + 0x10000 )
125 #define UNM_ROMUSB_ROM_INSTR_OPCODE ( UNM_ROMUSB_ROM + 0x00004 )
126 #define UNM_ROMUSB_ROM_ADDRESS ( UNM_ROMUSB_ROM + 0x00008 )
127 #define UNM_ROMUSB_ROM_WDATA ( UNM_ROMUSB_ROM + 0x0000c )
128 #define UNM_ROMUSB_ROM_ABYTE_CNT ( UNM_ROMUSB_ROM + 0x00010 )
129 #define UNM_ROMUSB_ROM_DUMMY_BYTE_CNT ( UNM_ROMUSB_ROM + 0x00014 )
130 #define UNM_ROMUSB_ROM_RDATA ( UNM_ROMUSB_ROM + 0x00018 )
132 #define UNM_CRB_TEST UNM_CRB_BASE ( UNM_CRB_BLK_TEST )
134 #define UNM_TEST_CONTROL ( UNM_CRB_TEST + 0x00090 )
135 #define UNM_TEST_CONTROL_START 0x01
136 #define UNM_TEST_CONTROL_ENABLE 0x02
137 #define UNM_TEST_CONTROL_BUSY 0x08
138 #define UNM_TEST_ADDR_LO ( UNM_CRB_TEST + 0x00094 )
139 #define UNM_TEST_ADDR_HI ( UNM_CRB_TEST + 0x00098 )
140 #define UNM_TEST_RDDATA_LO ( UNM_CRB_TEST + 0x000a8 )
141 #define UNM_TEST_RDDATA_HI ( UNM_CRB_TEST + 0x000ac )
143 /******************************************************************************
149 /* Board configuration */
151 #define UNM_BRDCFG_START 0x4000
153 struct unm_board_info {
154 uint32_t header_version;
168 uint32_t mac_addr_lo_0;
169 uint32_t mac_addr_lo_1;
170 uint32_t mac_addr_lo_2;
171 uint32_t mac_addr_lo_3;
172 uint32_t mn_sync_mode;
173 uint32_t mn_sync_shift_cclk;
174 uint32_t mn_sync_shift_mclk;
176 uint32_t mn_crystal_freq;
182 uint32_t mn_rd_latency_0;
183 uint32_t mn_rd_latency_1;
184 uint32_t mn_rd_latency_2;
185 uint32_t mn_rd_latency_3;
186 uint32_t mn_rd_latency_4;
187 uint32_t mn_rd_latency_5;
188 uint32_t mn_rd_latency_6;
189 uint32_t mn_rd_latency_7;
190 uint32_t mn_rd_latency_8;
191 uint32_t mn_dll_val[18];
192 uint32_t mn_mode_reg;
193 uint32_t mn_ext_mode_reg;
194 uint32_t mn_timing_0;
195 uint32_t mn_timing_1;
196 uint32_t mn_timing_2;
197 uint32_t sn_sync_mode;
201 uint32_t sn_crystal_freq;
206 uint32_t sn_rd_latency;
207 uint32_t mac_addr_hi_0;
208 uint32_t mac_addr_hi_1;
209 uint32_t mac_addr_hi_2;
210 uint32_t mac_addr_hi_3;
213 uint32_t mn_dll_override;
216 #define UNM_BDINFO_VERSION 1
217 #define UNM_BRDTYPE_P3_HMEZ 0x0022
218 #define UNM_BRDTYPE_P3_10G_CX4_LP 0x0023
219 #define UNM_BRDTYPE_P3_4_GB 0x0024
220 #define UNM_BRDTYPE_P3_IMEZ 0x0025
221 #define UNM_BRDTYPE_P3_10G_SFP_PLUS 0x0026
222 #define UNM_BRDTYPE_P3_10000_BASE_T 0x0027
223 #define UNM_BRDTYPE_P3_XG_LOM 0x0028
224 #define UNM_BRDTYPE_P3_10G_CX4 0x0031
225 #define UNM_BRDTYPE_P3_10G_XFP 0x0032
226 #define UNM_BDINFO_MAGIC 0x12345678
228 /* User defined region */
230 #define UNM_USER_START 0x3e8000
232 #define UNM_FLASH_NUM_PORTS 4
233 #define UNM_FLASH_NUM_MAC_PER_PORT 32
235 struct unm_user_info {
236 uint8_t flash_md5[16 * 64];
237 uint32_t bootld_version;
238 uint32_t bootld_size;
239 uint32_t image_version;
241 uint32_t primary_status;
242 uint32_t secondary_present;
243 /* MAC address , 4 ports, 32 address per port */
244 uint64_t mac_addr[UNM_FLASH_NUM_PORTS * UNM_FLASH_NUM_MAC_PER_PORT];
246 uint8_t serial_num[32];
247 uint32_t bios_version;
249 uint32_t vlan_tag[UNM_FLASH_NUM_PORTS];
252 #endif /* _PHANTOM_H */