2 * Copyright (C) 2008 Michael Brown <mbrown@fensystems.co.uk>.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of the
7 * License, or any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
27 #include <gpxe/malloc.h>
28 #include <gpxe/iobuf.h>
29 #include <gpxe/netdevice.h>
30 #include <gpxe/if_ether.h>
31 #include <gpxe/ethernet.h>
42 /** Maximum time to wait for SPI lock */
43 #define PHN_SPI_LOCK_TIMEOUT_MS 100
45 /** Maximum time to wait for SPI command to be issued */
46 #define PHN_SPI_CMD_TIMEOUT_MS 100
48 /** Maximum time to wait for command PEG to initialise
52 * The command PEG will currently report initialisation complete only
53 * when at least one PHY has detected a link (so that the global PHY
54 * clock can be set to 10G/1G as appropriate). This can take a very,
57 * A future firmware revision should decouple PHY initialisation from
58 * firmware initialisation, at which point the command PEG will report
59 * initialisation complete much earlier, and this timeout can be
62 #define PHN_CMDPEG_INIT_TIMEOUT_SEC 50
64 /** Maximum time to wait for receive PEG to initialise */
65 #define PHN_RCVPEG_INIT_TIMEOUT_SEC 2
67 /** Maximum time to wait for firmware to accept a command */
68 #define PHN_ISSUE_CMD_TIMEOUT_MS 2000
70 /** Maximum time to wait for test memory */
71 #define PHN_TEST_MEM_TIMEOUT_MS 100
73 /** Link state poll frequency
75 * The link state will be checked once in every N calls to poll().
77 #define PHN_LINK_POLL_FREQUENCY 4096
79 /** Number of RX descriptors */
80 #define PHN_NUM_RDS 32
82 /** RX maximum fill level. Must be strictly less than PHN_NUM_RDS. */
83 #define PHN_RDS_MAX_FILL 16
86 #define PHN_RX_BUFSIZE ( 32 /* max LL padding added by card */ + \
89 /** Number of RX status descriptors */
90 #define PHN_NUM_SDS 32
92 /** Number of TX descriptors */
95 /** A Phantom descriptor ring set */
96 struct phantom_descriptor_rings {
98 struct phantom_rds rds[PHN_NUM_RDS];
99 /** RX status descriptors */
100 struct phantom_sds sds[PHN_NUM_SDS];
101 /** TX descriptors */
102 union phantom_cds cds[PHN_NUM_CDS];
103 /** TX consumer index */
104 volatile uint32_t cmd_cons;
107 /** A Phantom NIC port */
108 struct phantom_nic_port {
109 /** Phantom NIC containing this port */
110 struct phantom_nic *phantom;
116 uint16_t rx_context_id;
117 /** RX descriptor producer CRB offset */
118 unsigned long rds_producer_crb;
119 /** RX status descriptor consumer CRB offset */
120 unsigned long sds_consumer_crb;
122 /** RX producer index */
123 unsigned int rds_producer_idx;
124 /** RX consumer index */
125 unsigned int rds_consumer_idx;
126 /** RX status consumer index */
127 unsigned int sds_consumer_idx;
128 /** RX I/O buffers */
129 struct io_buffer *rds_iobuf[PHN_RDS_MAX_FILL];
133 uint16_t tx_context_id;
134 /** TX descriptor producer CRB offset */
135 unsigned long cds_producer_crb;
137 /** TX producer index */
138 unsigned int cds_producer_idx;
139 /** TX consumer index */
140 unsigned int cds_consumer_idx;
141 /** TX I/O buffers */
142 struct io_buffer *cds_iobuf[PHN_NUM_CDS];
145 /** Link state poll timer */
146 unsigned long link_poll_timer;
149 /** Descriptor rings */
150 struct phantom_descriptor_rings *desc;
153 /** RX context creation request and response buffers */
154 struct phantom_create_rx_ctx_rqrsp {
156 struct nx_hostrq_rx_ctx_s rx_ctx;
157 struct nx_hostrq_rds_ring_s rds;
158 struct nx_hostrq_sds_ring_s sds;
159 } __unm_dma_aligned hostrq;
161 struct nx_cardrsp_rx_ctx_s rx_ctx;
162 struct nx_cardrsp_rds_ring_s rds;
163 struct nx_cardrsp_sds_ring_s sds;
164 } __unm_dma_aligned cardrsp;
167 /** TX context creation request and response buffers */
168 struct phantom_create_tx_ctx_rqrsp {
170 struct nx_hostrq_tx_ctx_s tx_ctx;
171 } __unm_dma_aligned hostrq;
173 struct nx_cardrsp_tx_ctx_s tx_ctx;
174 } __unm_dma_aligned cardrsp;
177 /** A Phantom DMA buffer area */
178 union phantom_dma_buffer {
179 /** Dummy area required for (read-only) self-tests */
180 uint8_t dummy_dma[UNM_DUMMY_DMA_SIZE];
181 /** RX context creation request and response buffers */
182 struct phantom_create_rx_ctx_rqrsp create_rx_ctx;
183 /** TX context creation request and response buffers */
184 struct phantom_create_tx_ctx_rqrsp create_tx_ctx;
191 /** Current CRB window */
192 unsigned long crb_window;
193 /** CRB window access method */
194 unsigned long ( *crb_access ) ( struct phantom_nic *phantom,
197 /** Number of ports */
199 /** Per-port network devices */
200 struct net_device *netdev[UNM_FLASH_NUM_PORTS];
203 union phantom_dma_buffer *dma_buf;
205 /** Flash memory SPI bus */
206 struct spi_bus spi_bus;
207 /** Flash memory SPI device */
208 struct spi_device flash;
210 /** Last known link state */
214 /***************************************************************************
216 * CRB register access
221 * Prepare for access to CRB register via 128MB BAR
223 * @v phantom Phantom NIC
224 * @v reg Register offset within abstract address space
225 * @ret offset Register offset within PCI BAR0
227 static unsigned long phantom_crb_access_128m ( struct phantom_nic *phantom,
228 unsigned long reg ) {
229 static const uint32_t reg_window[] = {
230 [UNM_CRB_BLK_PCIE] = 0x0000000,
231 [UNM_CRB_BLK_CAM] = 0x2000000,
232 [UNM_CRB_BLK_ROMUSB] = 0x2000000,
233 [UNM_CRB_BLK_TEST] = 0x0000000,
235 static const uint32_t reg_bases[] = {
236 [UNM_CRB_BLK_PCIE] = 0x6100000,
237 [UNM_CRB_BLK_CAM] = 0x6200000,
238 [UNM_CRB_BLK_ROMUSB] = 0x7300000,
239 [UNM_CRB_BLK_TEST] = 0x6200000,
241 unsigned int block = UNM_CRB_BLK ( reg );
242 unsigned long offset = UNM_CRB_OFFSET ( reg );
243 uint32_t window = reg_window[block];
244 uint32_t verify_window;
246 if ( phantom->crb_window != window ) {
248 /* Write to the CRB window register */
249 writel ( window, phantom->bar0 + UNM_128M_CRB_WINDOW );
251 /* Ensure that the write has reached the card */
252 verify_window = readl ( phantom->bar0 + UNM_128M_CRB_WINDOW );
253 assert ( verify_window == window );
255 /* Record new window */
256 phantom->crb_window = window;
259 return ( reg_bases[block] + offset );
263 * Prepare for access to CRB register via 32MB BAR
265 * @v phantom Phantom NIC
266 * @v reg Register offset within abstract address space
267 * @ret offset Register offset within PCI BAR0
269 static unsigned long phantom_crb_access_32m ( struct phantom_nic *phantom,
270 unsigned long reg ) {
271 static const uint32_t reg_window[] = {
272 [UNM_CRB_BLK_PCIE] = 0x0000000,
273 [UNM_CRB_BLK_CAM] = 0x2000000,
274 [UNM_CRB_BLK_ROMUSB] = 0x2000000,
275 [UNM_CRB_BLK_TEST] = 0x0000000,
277 static const uint32_t reg_bases[] = {
278 [UNM_CRB_BLK_PCIE] = 0x0100000,
279 [UNM_CRB_BLK_CAM] = 0x0200000,
280 [UNM_CRB_BLK_ROMUSB] = 0x1300000,
281 [UNM_CRB_BLK_TEST] = 0x0200000,
283 unsigned int block = UNM_CRB_BLK ( reg );
284 unsigned long offset = UNM_CRB_OFFSET ( reg );
285 uint32_t window = reg_window[block];
286 uint32_t verify_window;
288 if ( phantom->crb_window != window ) {
290 /* Write to the CRB window register */
291 writel ( window, phantom->bar0 + UNM_32M_CRB_WINDOW );
293 /* Ensure that the write has reached the card */
294 verify_window = readl ( phantom->bar0 + UNM_32M_CRB_WINDOW );
295 assert ( verify_window == window );
297 /* Record new window */
298 phantom->crb_window = window;
301 return ( reg_bases[block] + offset );
305 * Prepare for access to CRB register via 2MB BAR
307 * @v phantom Phantom NIC
308 * @v reg Register offset within abstract address space
309 * @ret offset Register offset within PCI BAR0
311 static unsigned long phantom_crb_access_2m ( struct phantom_nic *phantom,
312 unsigned long reg ) {
313 static const uint32_t reg_window_hi[] = {
314 [UNM_CRB_BLK_PCIE] = 0x77300000,
315 [UNM_CRB_BLK_CAM] = 0x41600000,
316 [UNM_CRB_BLK_ROMUSB] = 0x42100000,
317 [UNM_CRB_BLK_TEST] = 0x29500000,
319 unsigned int block = UNM_CRB_BLK ( reg );
320 unsigned long offset = UNM_CRB_OFFSET ( reg );
321 uint32_t window = ( reg_window_hi[block] | ( offset & 0x000f0000 ) );
322 uint32_t verify_window;
324 if ( phantom->crb_window != window ) {
326 /* Write to the CRB window register */
327 writel ( window, phantom->bar0 + UNM_2M_CRB_WINDOW );
329 /* Ensure that the write has reached the card */
330 verify_window = readl ( phantom->bar0 + UNM_2M_CRB_WINDOW );
331 assert ( verify_window == window );
333 /* Record new window */
334 phantom->crb_window = window;
337 return ( 0x1e0000 + ( offset & 0xffff ) );
341 * Read from Phantom CRB register
343 * @v phantom Phantom NIC
344 * @v reg Register offset within abstract address space
345 * @ret value Register value
347 static uint32_t phantom_readl ( struct phantom_nic *phantom,
348 unsigned long reg ) {
349 unsigned long offset;
351 offset = phantom->crb_access ( phantom, reg );
352 return readl ( phantom->bar0 + offset );
356 * Write to Phantom CRB register
358 * @v phantom Phantom NIC
359 * @v value Register value
360 * @v reg Register offset within abstract address space
362 static void phantom_writel ( struct phantom_nic *phantom, uint32_t value,
363 unsigned long reg ) {
364 unsigned long offset;
366 offset = phantom->crb_access ( phantom, reg );
367 writel ( value, phantom->bar0 + offset );
371 * Write to Phantom CRB HI/LO register pair
373 * @v phantom Phantom NIC
374 * @v value Register value
375 * @v lo_offset LO register offset within CRB
376 * @v hi_offset HI register offset within CRB
378 static inline void phantom_write_hilo ( struct phantom_nic *phantom,
380 unsigned long lo_offset,
381 unsigned long hi_offset ) {
382 uint32_t lo = ( value & 0xffffffffUL );
383 uint32_t hi = ( value >> 32 );
385 phantom_writel ( phantom, lo, lo_offset );
386 phantom_writel ( phantom, hi, hi_offset );
389 /***************************************************************************
391 * Firmware message buffer access (for debug)
396 * Read from Phantom test memory
398 * @v phantom Phantom NIC
399 * @v offset Offset within test memory
400 * @v buf 8-byte buffer to fill
401 * @ret rc Return status code
403 static int phantom_read_test_mem ( struct phantom_nic *phantom,
404 uint64_t offset, uint32_t buf[2] ) {
405 unsigned int retries;
406 uint32_t test_control;
408 phantom_write_hilo ( phantom, offset, UNM_TEST_ADDR_LO,
410 phantom_writel ( phantom, UNM_TEST_CONTROL_ENABLE, UNM_TEST_CONTROL );
411 phantom_writel ( phantom,
412 ( UNM_TEST_CONTROL_ENABLE | UNM_TEST_CONTROL_START ),
415 for ( retries = 0 ; retries < PHN_TEST_MEM_TIMEOUT_MS ; retries++ ) {
416 test_control = phantom_readl ( phantom, UNM_TEST_CONTROL );
417 if ( ( test_control & UNM_TEST_CONTROL_BUSY ) == 0 ) {
418 buf[0] = phantom_readl ( phantom, UNM_TEST_RDDATA_LO );
419 buf[1] = phantom_readl ( phantom, UNM_TEST_RDDATA_HI );
425 DBGC ( phantom, "Phantom %p timed out waiting for test memory\n",
431 * Dump Phantom firmware dmesg log
433 * @v phantom Phantom NIC
436 static void phantom_dmesg ( struct phantom_nic *phantom, unsigned int log ) {
449 /* Optimise out for non-debug builds */
453 head = phantom_readl ( phantom, UNM_CAM_RAM_DMESG_HEAD ( log ) );
454 len = phantom_readl ( phantom, UNM_CAM_RAM_DMESG_LEN ( log ) );
455 tail = phantom_readl ( phantom, UNM_CAM_RAM_DMESG_TAIL ( log ) );
456 sig = phantom_readl ( phantom, UNM_CAM_RAM_DMESG_SIG ( log ) );
457 DBGC ( phantom, "Phantom %p firmware dmesg buffer %d (%08lx-%08lx)\n",
458 phantom, log, head, tail );
459 assert ( ( head & 0x07 ) == 0 );
460 if ( sig != UNM_CAM_RAM_DMESG_SIG_MAGIC ) {
461 DBGC ( phantom, "Warning: bad signature %08lx (want %08lx)\n",
462 sig, UNM_CAM_RAM_DMESG_SIG_MAGIC );
465 for ( offset = head ; offset < tail ; offset += 8 ) {
466 if ( ( rc = phantom_read_test_mem ( phantom, offset,
467 buf.dwords ) ) != 0 ) {
468 DBGC ( phantom, "Phantom %p could not read from test "
469 "memory: %s\n", phantom, strerror ( rc ) );
472 for ( i = 0 ; ( ( i < sizeof ( buf ) ) &&
473 ( offset + i ) < tail ) ; i++ ) {
474 DBG ( "%c", buf.bytes[i] );
481 * Dump Phantom firmware dmesg logs
483 * @v phantom Phantom NIC
485 static void __attribute__ (( unused ))
486 phantom_dmesg_all ( struct phantom_nic *phantom ) {
489 for ( i = 0 ; i < UNM_CAM_RAM_NUM_DMESG_BUFFERS ; i++ )
490 phantom_dmesg ( phantom, i );
493 /***************************************************************************
495 * SPI bus access (for flash memory)
500 * Acquire Phantom SPI lock
502 * @v phantom Phantom NIC
503 * @ret rc Return status code
505 static int phantom_spi_lock ( struct phantom_nic *phantom ) {
506 unsigned int retries;
507 uint32_t pcie_sem2_lock;
509 for ( retries = 0 ; retries < PHN_SPI_LOCK_TIMEOUT_MS ; retries++ ) {
510 pcie_sem2_lock = phantom_readl ( phantom, UNM_PCIE_SEM2_LOCK );
511 if ( pcie_sem2_lock != 0 )
516 DBGC ( phantom, "Phantom %p timed out waiting for SPI lock\n",
522 * Wait for Phantom SPI command to complete
524 * @v phantom Phantom NIC
525 * @ret rc Return status code
527 static int phantom_spi_wait ( struct phantom_nic *phantom ) {
528 unsigned int retries;
531 for ( retries = 0 ; retries < PHN_SPI_CMD_TIMEOUT_MS ; retries++ ) {
532 glb_status = phantom_readl ( phantom, UNM_ROMUSB_GLB_STATUS );
533 if ( glb_status & UNM_ROMUSB_GLB_STATUS_ROM_DONE )
538 DBGC ( phantom, "Phantom %p timed out waiting for SPI command\n",
544 * Release Phantom SPI lock
546 * @v phantom Phantom NIC
548 static void phantom_spi_unlock ( struct phantom_nic *phantom ) {
549 phantom_readl ( phantom, UNM_PCIE_SEM2_UNLOCK );
553 * Read/write data via Phantom SPI bus
556 * @v device SPI device
558 * @v address Address to read/write (<0 for no address)
559 * @v data_out TX data buffer (or NULL)
560 * @v data_in RX data buffer (or NULL)
561 * @v len Length of data buffer(s)
562 * @ret rc Return status code
564 static int phantom_spi_rw ( struct spi_bus *bus,
565 struct spi_device *device,
566 unsigned int command, int address,
567 const void *data_out, void *data_in,
569 struct phantom_nic *phantom =
570 container_of ( bus, struct phantom_nic, spi_bus );
574 DBGCP ( phantom, "Phantom %p SPI command %x at %x+%zx\n",
575 phantom, command, address, len );
577 DBGCP_HDA ( phantom, address, data_out, len );
579 /* We support only exactly 4-byte reads */
580 if ( len != UNM_SPI_BLKSIZE ) {
581 DBGC ( phantom, "Phantom %p invalid SPI length %zx\n",
586 /* Acquire SPI lock */
587 if ( ( rc = phantom_spi_lock ( phantom ) ) != 0 )
590 /* Issue SPI command as per the PRM */
592 memcpy ( &data, data_out, sizeof ( data ) );
593 phantom_writel ( phantom, data, UNM_ROMUSB_ROM_WDATA );
595 phantom_writel ( phantom, address, UNM_ROMUSB_ROM_ADDRESS );
596 phantom_writel ( phantom, ( device->address_len / 8 ),
597 UNM_ROMUSB_ROM_ABYTE_CNT );
598 udelay ( 100 ); /* according to PRM */
599 phantom_writel ( phantom, 0, UNM_ROMUSB_ROM_DUMMY_BYTE_CNT );
600 phantom_writel ( phantom, command, UNM_ROMUSB_ROM_INSTR_OPCODE );
602 /* Wait for SPI command to complete */
603 if ( ( rc = phantom_spi_wait ( phantom ) ) != 0 )
606 /* Reset address byte count and dummy byte count, because the
609 phantom_writel ( phantom, 0, UNM_ROMUSB_ROM_ABYTE_CNT );
610 udelay ( 100 ); /* according to PRM */
611 phantom_writel ( phantom, 0, UNM_ROMUSB_ROM_DUMMY_BYTE_CNT );
613 /* Read data, if applicable */
615 data = phantom_readl ( phantom, UNM_ROMUSB_ROM_RDATA );
616 memcpy ( data_in, &data, sizeof ( data ) );
617 DBGCP_HDA ( phantom, address, data_in, len );
621 phantom_spi_unlock ( phantom );
626 /***************************************************************************
633 * Wait for firmware to accept command
635 * @v phantom Phantom NIC
636 * @ret rc Return status code
638 static int phantom_wait_for_cmd ( struct phantom_nic *phantom ) {
639 unsigned int retries;
642 for ( retries = 0 ; retries < PHN_ISSUE_CMD_TIMEOUT_MS ; retries++ ) {
644 cdrp = phantom_readl ( phantom, UNM_NIC_REG_NX_CDRP );
645 if ( NX_CDRP_IS_RSP ( cdrp ) ) {
646 switch ( NX_CDRP_FORM_RSP ( cdrp ) ) {
649 case NX_CDRP_RSP_FAIL:
651 case NX_CDRP_RSP_TIMEOUT:
659 DBGC ( phantom, "Phantom %p timed out waiting for firmware to accept "
660 "command\n", phantom );
665 * Issue command to firmware
667 * @v phantom_port Phantom NIC port
668 * @v command Firmware command
672 * @ret rc Return status code
674 static int phantom_issue_cmd ( struct phantom_nic_port *phantom_port,
675 uint32_t command, uint32_t arg1, uint32_t arg2,
677 struct phantom_nic *phantom = phantom_port->phantom;
682 signature = NX_CDRP_SIGNATURE_MAKE ( phantom_port->port,
684 DBGC2 ( phantom, "Phantom %p port %d issuing command %08lx (%08lx, "
685 "%08lx, %08lx)\n", phantom, phantom_port->port,
686 command, arg1, arg2, arg3 );
687 phantom_writel ( phantom, signature, UNM_NIC_REG_NX_SIGN );
688 phantom_writel ( phantom, arg1, UNM_NIC_REG_NX_ARG1 );
689 phantom_writel ( phantom, arg2, UNM_NIC_REG_NX_ARG2 );
690 phantom_writel ( phantom, arg3, UNM_NIC_REG_NX_ARG3 );
691 phantom_writel ( phantom, NX_CDRP_FORM_CMD ( command ),
692 UNM_NIC_REG_NX_CDRP );
694 /* Wait for command to be accepted */
695 if ( ( rc = phantom_wait_for_cmd ( phantom ) ) != 0 ) {
696 DBGC ( phantom, "Phantom %p could not issue command: %s\n",
697 phantom, strerror ( rc ) );
705 * Issue buffer-format command to firmware
707 * @v phantom_port Phantom NIC port
708 * @v command Firmware command
709 * @v buffer Buffer to pass to firmware
710 * @v len Length of buffer
711 * @ret rc Return status code
713 static int phantom_issue_buf_cmd ( struct phantom_nic_port *phantom_port,
714 uint32_t command, void *buffer,
718 physaddr = virt_to_bus ( buffer );
719 return phantom_issue_cmd ( phantom_port, command, ( physaddr >> 32 ),
720 ( physaddr & 0xffffffffUL ), len );
724 * Create Phantom RX context
726 * @v phantom_port Phantom NIC port
727 * @ret rc Return status code
729 static int phantom_create_rx_ctx ( struct phantom_nic_port *phantom_port ) {
730 struct phantom_nic *phantom = phantom_port->phantom;
731 struct phantom_create_rx_ctx_rqrsp *buf;
734 /* Prepare request */
735 buf = &phantom->dma_buf->create_rx_ctx;
736 memset ( buf, 0, sizeof ( *buf ) );
737 buf->hostrq.rx_ctx.host_rsp_dma_addr =
738 cpu_to_le64 ( virt_to_bus ( &buf->cardrsp ) );
739 buf->hostrq.rx_ctx.capabilities[0] =
740 cpu_to_le32 ( NX_CAP0_LEGACY_CONTEXT | NX_CAP0_LEGACY_MN );
741 buf->hostrq.rx_ctx.host_int_crb_mode =
742 cpu_to_le32 ( NX_HOST_INT_CRB_MODE_SHARED );
743 buf->hostrq.rx_ctx.host_rds_crb_mode =
744 cpu_to_le32 ( NX_HOST_RDS_CRB_MODE_UNIQUE );
745 buf->hostrq.rx_ctx.rds_ring_offset = cpu_to_le32 ( 0 );
746 buf->hostrq.rx_ctx.sds_ring_offset =
747 cpu_to_le32 ( sizeof ( buf->hostrq.rds ) );
748 buf->hostrq.rx_ctx.num_rds_rings = cpu_to_le16 ( 1 );
749 buf->hostrq.rx_ctx.num_sds_rings = cpu_to_le16 ( 1 );
750 buf->hostrq.rds.host_phys_addr =
751 cpu_to_le64 ( virt_to_bus ( phantom_port->desc->rds ) );
752 buf->hostrq.rds.buff_size = cpu_to_le64 ( PHN_RX_BUFSIZE );
753 buf->hostrq.rds.ring_size = cpu_to_le32 ( PHN_NUM_RDS );
754 buf->hostrq.rds.ring_kind = cpu_to_le32 ( NX_RDS_RING_TYPE_NORMAL );
755 buf->hostrq.sds.host_phys_addr =
756 cpu_to_le64 ( virt_to_bus ( phantom_port->desc->sds ) );
757 buf->hostrq.sds.ring_size = cpu_to_le32 ( PHN_NUM_SDS );
759 DBGC ( phantom, "Phantom %p port %d creating RX context\n",
760 phantom, phantom_port->port );
761 DBGC2_HDA ( phantom, virt_to_bus ( &buf->hostrq ),
762 &buf->hostrq, sizeof ( buf->hostrq ) );
765 if ( ( rc = phantom_issue_buf_cmd ( phantom_port,
766 NX_CDRP_CMD_CREATE_RX_CTX,
768 sizeof ( buf->hostrq ) ) ) != 0 ) {
769 DBGC ( phantom, "Phantom %p port %d could not create RX "
771 phantom, phantom_port->port, strerror ( rc ) );
772 DBGC ( phantom, "Request:\n" );
773 DBGC_HDA ( phantom, virt_to_bus ( &buf->hostrq ),
774 &buf->hostrq, sizeof ( buf->hostrq ) );
775 DBGC ( phantom, "Response:\n" );
776 DBGC_HDA ( phantom, virt_to_bus ( &buf->cardrsp ),
777 &buf->cardrsp, sizeof ( buf->cardrsp ) );
781 /* Retrieve context parameters */
782 phantom_port->rx_context_id =
783 le16_to_cpu ( buf->cardrsp.rx_ctx.context_id );
784 phantom_port->rds_producer_crb =
786 le32_to_cpu ( buf->cardrsp.rds.host_producer_crb ));
787 phantom_port->sds_consumer_crb =
789 le32_to_cpu ( buf->cardrsp.sds.host_consumer_crb ));
791 DBGC ( phantom, "Phantom %p port %d created RX context (id %04x, "
792 "port phys %02x virt %02x)\n", phantom, phantom_port->port,
793 phantom_port->rx_context_id, buf->cardrsp.rx_ctx.phys_port,
794 buf->cardrsp.rx_ctx.virt_port );
795 DBGC2_HDA ( phantom, virt_to_bus ( &buf->cardrsp ),
796 &buf->cardrsp, sizeof ( buf->cardrsp ) );
797 DBGC ( phantom, "Phantom %p port %d RDS producer CRB is %08lx\n",
798 phantom, phantom_port->port, phantom_port->rds_producer_crb );
799 DBGC ( phantom, "Phantom %p port %d SDS consumer CRB is %08lx\n",
800 phantom, phantom_port->port, phantom_port->sds_consumer_crb );
806 * Destroy Phantom RX context
808 * @v phantom_port Phantom NIC port
809 * @ret rc Return status code
811 static void phantom_destroy_rx_ctx ( struct phantom_nic_port *phantom_port ) {
812 struct phantom_nic *phantom = phantom_port->phantom;
815 DBGC ( phantom, "Phantom %p port %d destroying RX context (id %04x)\n",
816 phantom, phantom_port->port, phantom_port->rx_context_id );
819 if ( ( rc = phantom_issue_cmd ( phantom_port,
820 NX_CDRP_CMD_DESTROY_RX_CTX,
821 phantom_port->rx_context_id,
822 NX_DESTROY_CTX_RESET, 0 ) ) != 0 ) {
823 DBGC ( phantom, "Phantom %p port %d could not destroy RX "
825 phantom, phantom_port->port, strerror ( rc ) );
826 /* We're probably screwed */
830 /* Clear context parameters */
831 phantom_port->rx_context_id = 0;
832 phantom_port->rds_producer_crb = 0;
833 phantom_port->sds_consumer_crb = 0;
835 /* Reset software counters */
836 phantom_port->rds_producer_idx = 0;
837 phantom_port->rds_consumer_idx = 0;
838 phantom_port->sds_consumer_idx = 0;
842 * Create Phantom TX context
844 * @v phantom_port Phantom NIC port
845 * @ret rc Return status code
847 static int phantom_create_tx_ctx ( struct phantom_nic_port *phantom_port ) {
848 struct phantom_nic *phantom = phantom_port->phantom;
849 struct phantom_create_tx_ctx_rqrsp *buf;
852 /* Prepare request */
853 buf = &phantom->dma_buf->create_tx_ctx;
854 memset ( buf, 0, sizeof ( *buf ) );
855 buf->hostrq.tx_ctx.host_rsp_dma_addr =
856 cpu_to_le64 ( virt_to_bus ( &buf->cardrsp ) );
857 buf->hostrq.tx_ctx.cmd_cons_dma_addr =
858 cpu_to_le64 ( virt_to_bus ( &phantom_port->desc->cmd_cons ) );
859 buf->hostrq.tx_ctx.dummy_dma_addr =
860 cpu_to_le64 ( virt_to_bus ( phantom->dma_buf->dummy_dma ) );
861 buf->hostrq.tx_ctx.capabilities[0] =
862 cpu_to_le32 ( NX_CAP0_LEGACY_CONTEXT | NX_CAP0_LEGACY_MN );
863 buf->hostrq.tx_ctx.host_int_crb_mode =
864 cpu_to_le32 ( NX_HOST_INT_CRB_MODE_SHARED );
865 buf->hostrq.tx_ctx.cds_ring.host_phys_addr =
866 cpu_to_le64 ( virt_to_bus ( phantom_port->desc->cds ) );
867 buf->hostrq.tx_ctx.cds_ring.ring_size = cpu_to_le32 ( PHN_NUM_CDS );
869 DBGC ( phantom, "Phantom %p port %d creating TX context\n",
870 phantom, phantom_port->port );
871 DBGC2_HDA ( phantom, virt_to_bus ( &buf->hostrq ),
872 &buf->hostrq, sizeof ( buf->hostrq ) );
875 if ( ( rc = phantom_issue_buf_cmd ( phantom_port,
876 NX_CDRP_CMD_CREATE_TX_CTX,
878 sizeof ( buf->hostrq ) ) ) != 0 ) {
879 DBGC ( phantom, "Phantom %p port %d could not create TX "
881 phantom, phantom_port->port, strerror ( rc ) );
882 DBGC ( phantom, "Request:\n" );
883 DBGC_HDA ( phantom, virt_to_bus ( &buf->hostrq ),
884 &buf->hostrq, sizeof ( buf->hostrq ) );
885 DBGC ( phantom, "Response:\n" );
886 DBGC_HDA ( phantom, virt_to_bus ( &buf->cardrsp ),
887 &buf->cardrsp, sizeof ( buf->cardrsp ) );
891 /* Retrieve context parameters */
892 phantom_port->tx_context_id =
893 le16_to_cpu ( buf->cardrsp.tx_ctx.context_id );
894 phantom_port->cds_producer_crb =
896 le32_to_cpu(buf->cardrsp.tx_ctx.cds_ring.host_producer_crb));
898 DBGC ( phantom, "Phantom %p port %d created TX context (id %04x, "
899 "port phys %02x virt %02x)\n", phantom, phantom_port->port,
900 phantom_port->tx_context_id, buf->cardrsp.tx_ctx.phys_port,
901 buf->cardrsp.tx_ctx.virt_port );
902 DBGC2_HDA ( phantom, virt_to_bus ( &buf->cardrsp ),
903 &buf->cardrsp, sizeof ( buf->cardrsp ) );
904 DBGC ( phantom, "Phantom %p port %d CDS producer CRB is %08lx\n",
905 phantom, phantom_port->port, phantom_port->cds_producer_crb );
911 * Destroy Phantom TX context
913 * @v phantom_port Phantom NIC port
914 * @ret rc Return status code
916 static void phantom_destroy_tx_ctx ( struct phantom_nic_port *phantom_port ) {
917 struct phantom_nic *phantom = phantom_port->phantom;
920 DBGC ( phantom, "Phantom %p port %d destroying TX context (id %04x)\n",
921 phantom, phantom_port->port, phantom_port->tx_context_id );
924 if ( ( rc = phantom_issue_cmd ( phantom_port,
925 NX_CDRP_CMD_DESTROY_TX_CTX,
926 phantom_port->tx_context_id,
927 NX_DESTROY_CTX_RESET, 0 ) ) != 0 ) {
928 DBGC ( phantom, "Phantom %p port %d could not destroy TX "
930 phantom, phantom_port->port, strerror ( rc ) );
931 /* We're probably screwed */
935 /* Clear context parameters */
936 phantom_port->tx_context_id = 0;
937 phantom_port->cds_producer_crb = 0;
939 /* Reset software counters */
940 phantom_port->cds_producer_idx = 0;
941 phantom_port->cds_consumer_idx = 0;
944 /***************************************************************************
946 * Descriptor ring management
951 * Allocate Phantom RX descriptor
953 * @v phantom_port Phantom NIC port
954 * @ret index RX descriptor index, or negative error
956 static int phantom_alloc_rds ( struct phantom_nic_port *phantom_port ) {
957 struct phantom_nic *phantom = phantom_port->phantom;
958 unsigned int rds_producer_idx;
959 unsigned int next_rds_producer_idx;
961 /* Check for space in the ring. RX descriptors are consumed
962 * out of order, but they are *read* by the hardware in strict
963 * order. We maintain a pessimistic consumer index, which is
964 * guaranteed never to be an overestimate of the number of
965 * descriptors read by the hardware.
967 rds_producer_idx = phantom_port->rds_producer_idx;
968 next_rds_producer_idx = ( ( rds_producer_idx + 1 ) % PHN_NUM_RDS );
969 if ( next_rds_producer_idx == phantom_port->rds_consumer_idx ) {
970 DBGC ( phantom, "Phantom %p port %d RDS ring full (index %d "
971 "not consumed)\n", phantom, phantom_port->port,
972 next_rds_producer_idx );
976 return rds_producer_idx;
980 * Post Phantom RX descriptor
982 * @v phantom_port Phantom NIC port
983 * @v rds RX descriptor
985 static void phantom_post_rds ( struct phantom_nic_port *phantom_port,
986 struct phantom_rds *rds ) {
987 struct phantom_nic *phantom = phantom_port->phantom;
988 unsigned int rds_producer_idx;
989 unsigned int next_rds_producer_idx;
990 struct phantom_rds *entry;
992 /* Copy descriptor to ring */
993 rds_producer_idx = phantom_port->rds_producer_idx;
994 entry = &phantom_port->desc->rds[rds_producer_idx];
995 memcpy ( entry, rds, sizeof ( *entry ) );
996 DBGC2 ( phantom, "Phantom %p port %d posting RDS %ld (slot %d):\n",
997 phantom, phantom_port->port, NX_GET ( rds, handle ),
999 DBGC2_HDA ( phantom, virt_to_bus ( entry ), entry, sizeof ( *entry ) );
1001 /* Update producer index */
1002 next_rds_producer_idx = ( ( rds_producer_idx + 1 ) % PHN_NUM_RDS );
1003 phantom_port->rds_producer_idx = next_rds_producer_idx;
1005 phantom_writel ( phantom, phantom_port->rds_producer_idx,
1006 phantom_port->rds_producer_crb );
1010 * Allocate Phantom TX descriptor
1012 * @v phantom_port Phantom NIC port
1013 * @ret index TX descriptor index, or negative error
1015 static int phantom_alloc_cds ( struct phantom_nic_port *phantom_port ) {
1016 struct phantom_nic *phantom = phantom_port->phantom;
1017 unsigned int cds_producer_idx;
1018 unsigned int next_cds_producer_idx;
1020 /* Check for space in the ring. TX descriptors are consumed
1021 * in strict order, so we just check for a collision against
1022 * the consumer index.
1024 cds_producer_idx = phantom_port->cds_producer_idx;
1025 next_cds_producer_idx = ( ( cds_producer_idx + 1 ) % PHN_NUM_CDS );
1026 if ( next_cds_producer_idx == phantom_port->cds_consumer_idx ) {
1027 DBGC ( phantom, "Phantom %p port %d CDS ring full (index %d "
1028 "not consumed)\n", phantom, phantom_port->port,
1029 next_cds_producer_idx );
1033 return cds_producer_idx;
1037 * Post Phantom TX descriptor
1039 * @v phantom_port Phantom NIC port
1040 * @v cds TX descriptor
1042 static void phantom_post_cds ( struct phantom_nic_port *phantom_port,
1043 union phantom_cds *cds ) {
1044 struct phantom_nic *phantom = phantom_port->phantom;
1045 unsigned int cds_producer_idx;
1046 unsigned int next_cds_producer_idx;
1047 union phantom_cds *entry;
1049 /* Copy descriptor to ring */
1050 cds_producer_idx = phantom_port->cds_producer_idx;
1051 entry = &phantom_port->desc->cds[cds_producer_idx];
1052 memcpy ( entry, cds, sizeof ( *entry ) );
1053 DBGC2 ( phantom, "Phantom %p port %d posting CDS %d:\n",
1054 phantom, phantom_port->port, cds_producer_idx );
1055 DBGC2_HDA ( phantom, virt_to_bus ( entry ), entry, sizeof ( *entry ) );
1057 /* Update producer index */
1058 next_cds_producer_idx = ( ( cds_producer_idx + 1 ) % PHN_NUM_CDS );
1059 phantom_port->cds_producer_idx = next_cds_producer_idx;
1061 phantom_writel ( phantom, phantom_port->cds_producer_idx,
1062 phantom_port->cds_producer_crb );
1065 /***************************************************************************
1067 * MAC address management
1072 * Add/remove MAC address
1074 * @v phantom_port Phantom NIC port
1075 * @v ll_addr MAC address to add or remove
1076 * @v opcode MAC request opcode
1077 * @ret rc Return status code
1079 static int phantom_update_macaddr ( struct phantom_nic_port *phantom_port,
1080 const uint8_t *ll_addr,
1081 unsigned int opcode ) {
1082 union phantom_cds cds;
1085 /* Get descriptor ring entry */
1086 index = phantom_alloc_cds ( phantom_port );
1090 /* Fill descriptor ring entry */
1091 memset ( &cds, 0, sizeof ( cds ) );
1092 NX_FILL_1 ( &cds, 0,
1093 nic_request.common.opcode, UNM_NIC_REQUEST );
1094 NX_FILL_2 ( &cds, 1,
1095 nic_request.header.opcode, UNM_MAC_EVENT,
1096 nic_request.header.context_id, phantom_port->port );
1097 NX_FILL_7 ( &cds, 2,
1098 nic_request.body.mac_request.opcode, opcode,
1099 nic_request.body.mac_request.mac_addr_0, ll_addr[0],
1100 nic_request.body.mac_request.mac_addr_1, ll_addr[1],
1101 nic_request.body.mac_request.mac_addr_2, ll_addr[2],
1102 nic_request.body.mac_request.mac_addr_3, ll_addr[3],
1103 nic_request.body.mac_request.mac_addr_4, ll_addr[4],
1104 nic_request.body.mac_request.mac_addr_5, ll_addr[5] );
1106 /* Post descriptor */
1107 phantom_post_cds ( phantom_port, &cds );
1115 * @v phantom_port Phantom NIC port
1116 * @v ll_addr MAC address to add or remove
1117 * @ret rc Return status code
1119 static inline int phantom_add_macaddr ( struct phantom_nic_port *phantom_port,
1120 const uint8_t *ll_addr ) {
1121 struct phantom_nic *phantom = phantom_port->phantom;
1123 DBGC ( phantom, "Phantom %p port %d adding MAC address %s\n",
1124 phantom, phantom_port->port, eth_ntoa ( ll_addr ) );
1126 return phantom_update_macaddr ( phantom_port, ll_addr, UNM_MAC_ADD );
1130 * Remove MAC address
1132 * @v phantom_port Phantom NIC port
1133 * @v ll_addr MAC address to add or remove
1134 * @ret rc Return status code
1136 static inline int phantom_del_macaddr ( struct phantom_nic_port *phantom_port,
1137 const uint8_t *ll_addr ) {
1138 struct phantom_nic *phantom = phantom_port->phantom;
1140 DBGC ( phantom, "Phantom %p port %d removing MAC address %s\n",
1141 phantom, phantom_port->port, eth_ntoa ( ll_addr ) );
1143 return phantom_update_macaddr ( phantom_port, ll_addr, UNM_MAC_DEL );
1146 /***************************************************************************
1148 * Link state detection
1155 * @v phantom Phantom NIC
1157 static void phantom_poll_link_state ( struct phantom_nic *phantom ) {
1158 struct net_device *netdev;
1159 struct phantom_nic_port *phantom_port;
1160 uint32_t xg_state_p3;
1164 /* Read link state */
1165 xg_state_p3 = phantom_readl ( phantom, UNM_NIC_REG_XG_STATE_P3 );
1167 /* If there is no change, do nothing */
1168 if ( phantom->link_state == xg_state_p3 )
1171 /* Record new link state */
1172 DBGC ( phantom, "Phantom %p new link state %08lx (was %08lx)\n",
1173 phantom, xg_state_p3, phantom->link_state );
1174 phantom->link_state = xg_state_p3;
1176 /* Indicate per-port link state to gPXE */
1177 for ( i = 0 ; i < phantom->num_ports ; i++ ) {
1178 netdev = phantom->netdev[i];
1179 phantom_port = netdev_priv ( netdev );
1180 link = UNM_NIC_REG_XG_STATE_P3_LINK ( phantom_port->port,
1181 phantom->link_state );
1183 case UNM_NIC_REG_XG_STATE_P3_LINK_UP:
1184 DBGC ( phantom, "Phantom %p port %d link is up\n",
1185 phantom, phantom_port->port );
1186 netdev_link_up ( netdev );
1188 case UNM_NIC_REG_XG_STATE_P3_LINK_DOWN:
1189 DBGC ( phantom, "Phantom %p port %d link is down\n",
1190 phantom, phantom_port->port );
1191 netdev_link_down ( netdev );
1194 DBGC ( phantom, "Phantom %p port %d bad link state "
1195 "%d\n", phantom, phantom_port->port, link );
1201 /***************************************************************************
1208 * Refill descriptor ring
1210 * @v netdev Net device
1212 static void phantom_refill_rx_ring ( struct net_device *netdev ) {
1213 struct phantom_nic_port *phantom_port = netdev_priv ( netdev );
1214 struct io_buffer *iobuf;
1215 struct phantom_rds rds;
1216 unsigned int handle;
1219 for ( handle = 0 ; handle < PHN_RDS_MAX_FILL ; handle++ ) {
1221 /* Skip this index if the descriptor has not yet been
1224 if ( phantom_port->rds_iobuf[handle] != NULL )
1227 /* Allocate descriptor ring entry */
1228 index = phantom_alloc_rds ( phantom_port );
1229 assert ( PHN_RDS_MAX_FILL < PHN_NUM_RDS );
1230 assert ( index >= 0 ); /* Guaranteed by MAX_FILL < NUM_RDS ) */
1232 /* Try to allocate an I/O buffer */
1233 iobuf = alloc_iob ( PHN_RX_BUFSIZE );
1235 /* Failure is non-fatal; we will retry later */
1236 netdev_rx_err ( netdev, NULL, -ENOMEM );
1240 /* Fill descriptor ring entry */
1241 memset ( &rds, 0, sizeof ( rds ) );
1242 NX_FILL_2 ( &rds, 0,
1244 length, iob_len ( iobuf ) );
1245 NX_FILL_1 ( &rds, 1,
1246 dma_addr, virt_to_bus ( iobuf->data ) );
1248 /* Record I/O buffer */
1249 assert ( phantom_port->rds_iobuf[handle] == NULL );
1250 phantom_port->rds_iobuf[handle] = iobuf;
1252 /* Post descriptor */
1253 phantom_post_rds ( phantom_port, &rds );
1260 * @v netdev Net device
1261 * @ret rc Return status code
1263 static int phantom_open ( struct net_device *netdev ) {
1264 struct phantom_nic_port *phantom_port = netdev_priv ( netdev );
1267 /* Allocate and zero descriptor rings */
1268 phantom_port->desc = malloc_dma ( sizeof ( *(phantom_port->desc) ),
1269 UNM_DMA_BUFFER_ALIGN );
1270 if ( ! phantom_port->desc ) {
1272 goto err_alloc_desc;
1274 memset ( phantom_port->desc, 0, sizeof ( *(phantom_port->desc) ) );
1276 /* Create RX context */
1277 if ( ( rc = phantom_create_rx_ctx ( phantom_port ) ) != 0 )
1278 goto err_create_rx_ctx;
1280 /* Create TX context */
1281 if ( ( rc = phantom_create_tx_ctx ( phantom_port ) ) != 0 )
1282 goto err_create_tx_ctx;
1284 /* Fill the RX descriptor ring */
1285 phantom_refill_rx_ring ( netdev );
1287 /* Add MAC addresses
1291 * We would like to be able to enable receiving all multicast
1292 * packets (or, failing that, promiscuous mode), but the
1293 * firmware doesn't currently support this.
1295 if ( ( rc = phantom_add_macaddr ( phantom_port,
1296 netdev->ll_protocol->ll_broadcast ) ) != 0 )
1297 goto err_add_macaddr_broadcast;
1298 if ( ( rc = phantom_add_macaddr ( phantom_port,
1299 netdev->ll_addr ) ) != 0 )
1300 goto err_add_macaddr_unicast;
1304 phantom_del_macaddr ( phantom_port, netdev->ll_addr );
1305 err_add_macaddr_unicast:
1306 phantom_del_macaddr ( phantom_port,
1307 netdev->ll_protocol->ll_broadcast );
1308 err_add_macaddr_broadcast:
1309 phantom_destroy_tx_ctx ( phantom_port );
1311 phantom_destroy_rx_ctx ( phantom_port );
1313 free_dma ( phantom_port->desc, sizeof ( *(phantom_port->desc) ) );
1314 phantom_port->desc = NULL;
1322 * @v netdev Net device
1324 static void phantom_close ( struct net_device *netdev ) {
1325 struct phantom_nic_port *phantom_port = netdev_priv ( netdev );
1326 struct io_buffer *iobuf;
1331 * When the last TX context is destroyed, the firmware will
1332 * pause the Egress Packet Generator (EPG). The corresponding
1333 * code that is supposed to unpause the EPG when the first TX
1334 * context is created is #if 0'd out (with a comment saying
1335 * FIXME). The net result of this is that if you close and
1336 * then reopen the interface, you will no longer be able to
1340 /* Shut down the port */
1341 phantom_del_macaddr ( phantom_port, netdev->ll_addr );
1342 phantom_del_macaddr ( phantom_port,
1343 netdev->ll_protocol->ll_broadcast );
1344 phantom_destroy_tx_ctx ( phantom_port );
1345 phantom_destroy_rx_ctx ( phantom_port );
1346 free_dma ( phantom_port->desc, sizeof ( *(phantom_port->desc) ) );
1347 phantom_port->desc = NULL;
1349 /* Flush any uncompleted descriptors */
1350 for ( i = 0 ; i < PHN_RDS_MAX_FILL ; i++ ) {
1351 iobuf = phantom_port->rds_iobuf[i];
1354 phantom_port->rds_iobuf[i] = NULL;
1357 for ( i = 0 ; i < PHN_NUM_CDS ; i++ ) {
1358 iobuf = phantom_port->cds_iobuf[i];
1360 netdev_tx_complete_err ( netdev, iobuf, -ECANCELED );
1361 phantom_port->cds_iobuf[i] = NULL;
1369 * @v netdev Network device
1370 * @v iobuf I/O buffer
1371 * @ret rc Return status code
1373 static int phantom_transmit ( struct net_device *netdev,
1374 struct io_buffer *iobuf ) {
1375 struct phantom_nic_port *phantom_port = netdev_priv ( netdev );
1376 union phantom_cds cds;
1379 /* Get descriptor ring entry */
1380 index = phantom_alloc_cds ( phantom_port );
1384 /* Fill descriptor ring entry */
1385 memset ( &cds, 0, sizeof ( cds ) );
1386 NX_FILL_3 ( &cds, 0,
1387 tx.opcode, UNM_TX_ETHER_PKT,
1389 tx.length, iob_len ( iobuf ) );
1390 NX_FILL_2 ( &cds, 2,
1391 tx.port, phantom_port->port,
1392 tx.context_id, phantom_port->port );
1393 NX_FILL_1 ( &cds, 4,
1394 tx.buffer1_dma_addr, virt_to_bus ( iobuf->data ) );
1395 NX_FILL_1 ( &cds, 5,
1396 tx.buffer1_length, iob_len ( iobuf ) );
1398 /* Record I/O buffer */
1399 assert ( phantom_port->cds_iobuf[index] == NULL );
1400 phantom_port->cds_iobuf[index] = iobuf;
1402 /* Post descriptor */
1403 phantom_post_cds ( phantom_port, &cds );
1409 * Poll for received packets
1411 * @v netdev Network device
1413 static void phantom_poll ( struct net_device *netdev ) {
1414 struct phantom_nic_port *phantom_port = netdev_priv ( netdev );
1415 struct phantom_nic *phantom = phantom_port->phantom;
1416 struct io_buffer *iobuf;
1417 unsigned int cds_consumer_idx;
1418 unsigned int raw_new_cds_consumer_idx;
1419 unsigned int new_cds_consumer_idx;
1420 unsigned int rds_consumer_idx;
1421 unsigned int sds_consumer_idx;
1422 struct phantom_sds *sds;
1423 unsigned int sds_handle;
1424 unsigned int sds_opcode;
1426 /* Check for TX completions */
1427 cds_consumer_idx = phantom_port->cds_consumer_idx;
1428 raw_new_cds_consumer_idx = phantom_port->desc->cmd_cons;
1429 new_cds_consumer_idx = le32_to_cpu ( raw_new_cds_consumer_idx );
1430 while ( cds_consumer_idx != new_cds_consumer_idx ) {
1431 DBGC2 ( phantom, "Phantom %p port %d CDS %d complete\n",
1432 phantom, phantom_port->port, cds_consumer_idx );
1433 /* Completions may be for commands other than TX, so
1434 * there may not always be an associated I/O buffer.
1436 if ( ( iobuf = phantom_port->cds_iobuf[cds_consumer_idx] ) ) {
1437 netdev_tx_complete ( netdev, iobuf );
1438 phantom_port->cds_iobuf[cds_consumer_idx] = NULL;
1440 cds_consumer_idx = ( ( cds_consumer_idx + 1 ) % PHN_NUM_CDS );
1441 phantom_port->cds_consumer_idx = cds_consumer_idx;
1444 /* Check for received packets */
1445 rds_consumer_idx = phantom_port->rds_consumer_idx;
1446 sds_consumer_idx = phantom_port->sds_consumer_idx;
1448 sds = &phantom_port->desc->sds[sds_consumer_idx];
1449 if ( NX_GET ( sds, owner ) == 0 )
1452 DBGC2 ( phantom, "Phantom %p port %d SDS %d status:\n",
1453 phantom, phantom_port->port, sds_consumer_idx );
1454 DBGC2_HDA ( phantom, virt_to_bus ( sds ), sds, sizeof (*sds) );
1456 /* Check received opcode */
1457 sds_opcode = NX_GET ( sds, opcode );
1458 switch ( sds_opcode ) {
1459 case UNM_RXPKT_DESC:
1460 case UNM_SYN_OFFLOAD:
1461 /* Process received packet */
1462 sds_handle = NX_GET ( sds, handle );
1463 iobuf = phantom_port->rds_iobuf[sds_handle];
1464 assert ( iobuf != NULL );
1465 iob_put ( iobuf, NX_GET ( sds, total_length ) );
1466 iob_pull ( iobuf, NX_GET ( sds, pkt_offset ) );
1467 DBGC2 ( phantom, "Phantom %p port %d RDS %d "
1469 phantom, phantom_port->port, sds_handle );
1470 netdev_rx ( netdev, iobuf );
1471 phantom_port->rds_iobuf[sds_handle] = NULL;
1474 DBGC ( phantom, "Phantom %p port %d unexpected SDS "
1476 phantom, phantom_port->port, sds_opcode );
1477 DBGC_HDA ( phantom, virt_to_bus ( sds ),
1478 sds, sizeof ( *sds ) );
1482 /* Update RDS consumer counter. This is a lower bound
1483 * for the number of descriptors that have been read
1484 * by the hardware, since the hardware must have read
1485 * at least one descriptor for each completion that we
1488 rds_consumer_idx = ( ( rds_consumer_idx + 1 ) % PHN_NUM_RDS );
1489 phantom_port->rds_consumer_idx = rds_consumer_idx;
1491 /* Clear status descriptor */
1492 memset ( sds, 0, sizeof ( *sds ) );
1494 /* Update SDS consumer index */
1495 sds_consumer_idx = ( ( sds_consumer_idx + 1 ) % PHN_NUM_SDS );
1496 phantom_port->sds_consumer_idx = sds_consumer_idx;
1498 phantom_writel ( phantom, phantom_port->sds_consumer_idx,
1499 phantom_port->sds_consumer_crb );
1502 /* Refill the RX descriptor ring */
1503 phantom_refill_rx_ring ( netdev );
1505 /* Occasionally poll the link state */
1506 if ( phantom_port->link_poll_timer-- == 0 ) {
1507 phantom_poll_link_state ( phantom );
1508 /* Reset the link poll timer */
1509 phantom_port->link_poll_timer = PHN_LINK_POLL_FREQUENCY;
1514 * Enable/disable interrupts
1516 * @v netdev Network device
1517 * @v enable Interrupts should be enabled
1519 static void phantom_irq ( struct net_device *netdev, int enable ) {
1520 struct phantom_nic_port *phantom_port = netdev_priv ( netdev );
1521 struct phantom_nic *phantom = phantom_port->phantom;
1522 static const unsigned long sw_int_mask_reg[UNM_FLASH_NUM_PORTS] = {
1523 UNM_NIC_REG_SW_INT_MASK_0,
1524 UNM_NIC_REG_SW_INT_MASK_1,
1525 UNM_NIC_REG_SW_INT_MASK_2,
1526 UNM_NIC_REG_SW_INT_MASK_3
1529 phantom_writel ( phantom,
1531 sw_int_mask_reg[phantom_port->port] );
1534 /** Phantom net device operations */
1535 static struct net_device_operations phantom_operations = {
1536 .open = phantom_open,
1537 .close = phantom_close,
1538 .transmit = phantom_transmit,
1539 .poll = phantom_poll,
1544 * Map Phantom CRB window
1546 * @v phantom Phantom NIC
1547 * @ret rc Return status code
1549 static int phantom_map_crb ( struct phantom_nic *phantom,
1550 struct pci_device *pci ) {
1551 unsigned long bar0_start;
1552 unsigned long bar0_size;
1554 /* CRB window is always in the last 32MB of BAR0 (which may be
1555 * a 32MB or a 128MB BAR).
1557 bar0_start = pci_bar_start ( pci, PCI_BASE_ADDRESS_0 );
1558 bar0_size = pci_bar_size ( pci, PCI_BASE_ADDRESS_0 );
1559 DBGC ( phantom, "Phantom %p BAR0 is %08lx+%lx\n",
1560 phantom, bar0_start, bar0_size );
1562 switch ( bar0_size ) {
1563 case ( 128 * 1024 * 1024 ) :
1564 DBGC ( phantom, "Phantom %p has 128MB BAR\n", phantom );
1565 phantom->crb_access = phantom_crb_access_128m;
1567 case ( 32 * 1024 * 1024 ) :
1568 DBGC ( phantom, "Phantom %p has 32MB BAR\n", phantom );
1569 phantom->crb_access = phantom_crb_access_32m;
1571 case ( 2 * 1024 * 1024 ) :
1572 DBGC ( phantom, "Phantom %p has 2MB BAR\n", phantom );
1573 phantom->crb_access = phantom_crb_access_2m;
1576 DBGC ( phantom, "Phantom %p has bad BAR size\n", phantom );
1580 phantom->bar0 = ioremap ( bar0_start, bar0_size );
1581 if ( ! phantom->bar0 ) {
1582 DBGC ( phantom, "Phantom %p could not map BAR0\n", phantom );
1586 /* Mark current CRB window as invalid, so that the first
1587 * read/write will set the current window.
1589 phantom->crb_window = -1UL;
1595 * Read Phantom flash contents
1597 * @v phantom Phantom NIC
1598 * @ret rc Return status code
1600 static int phantom_read_flash ( struct phantom_nic *phantom ) {
1601 struct unm_board_info board_info;
1604 /* Initialise flash access */
1605 phantom->spi_bus.rw = phantom_spi_rw;
1606 phantom->flash.bus = &phantom->spi_bus;
1607 init_m25p32 ( &phantom->flash );
1608 /* Phantom doesn't support greater than 4-byte block sizes */
1609 phantom->flash.nvs.block_size = UNM_SPI_BLKSIZE;
1611 /* Read and verify board information */
1612 if ( ( rc = nvs_read ( &phantom->flash.nvs, UNM_BRDCFG_START,
1613 &board_info, sizeof ( board_info ) ) ) != 0 ) {
1614 DBGC ( phantom, "Phantom %p could not read board info: %s\n",
1615 phantom, strerror ( rc ) );
1618 if ( board_info.magic != UNM_BDINFO_MAGIC ) {
1619 DBGC ( phantom, "Phantom %p has bad board info magic %lx\n",
1620 phantom, board_info.magic );
1621 DBGC_HD ( phantom, &board_info, sizeof ( board_info ) );
1624 if ( board_info.header_version != UNM_BDINFO_VERSION ) {
1625 DBGC ( phantom, "Phantom %p has bad board info version %lx\n",
1626 phantom, board_info.header_version );
1627 DBGC_HD ( phantom, &board_info, sizeof ( board_info ) );
1631 /* Identify board type and number of ports */
1632 switch ( board_info.board_type ) {
1633 case UNM_BRDTYPE_P3_4_GB:
1634 phantom->num_ports = 4;
1636 case UNM_BRDTYPE_P3_HMEZ:
1637 case UNM_BRDTYPE_P3_IMEZ:
1638 case UNM_BRDTYPE_P3_10G_CX4:
1639 case UNM_BRDTYPE_P3_10G_CX4_LP:
1640 case UNM_BRDTYPE_P3_10G_SFP_PLUS:
1641 case UNM_BRDTYPE_P3_XG_LOM:
1642 phantom->num_ports = 2;
1644 case UNM_BRDTYPE_P3_10000_BASE_T:
1645 case UNM_BRDTYPE_P3_10G_XFP:
1646 phantom->num_ports = 1;
1649 DBGC ( phantom, "Phantom %p unrecognised board type %#lx; "
1650 "assuming single-port\n",
1651 phantom, board_info.board_type );
1652 phantom->num_ports = 1;
1655 DBGC ( phantom, "Phantom %p board type is %#lx (%d ports)\n",
1656 phantom, board_info.board_type, phantom->num_ports );
1662 * Initialise the Phantom command PEG
1664 * @v phantom Phantom NIC
1665 * @ret rc Return status code
1667 static int phantom_init_cmdpeg ( struct phantom_nic *phantom ) {
1670 physaddr_t dummy_dma_phys;
1671 unsigned int retries;
1672 uint32_t cmdpeg_state;
1673 uint32_t last_cmdpeg_state = 0;
1675 /* If this was a cold boot, check that the hardware came up ok */
1676 cold_boot = phantom_readl ( phantom, UNM_CAM_RAM_COLD_BOOT );
1677 if ( cold_boot == UNM_CAM_RAM_COLD_BOOT_MAGIC ) {
1678 DBGC ( phantom, "Phantom %p coming up from cold boot\n",
1680 sw_reset = phantom_readl ( phantom, UNM_ROMUSB_GLB_SW_RESET );
1681 if ( sw_reset != UNM_ROMUSB_GLB_SW_RESET_MAGIC ) {
1682 DBGC ( phantom, "Phantom %p reset failed: %08lx\n",
1683 phantom, sw_reset );
1687 DBGC ( phantom, "Phantom %p coming up from warm boot "
1688 "(%08lx)\n", phantom, cold_boot );
1690 /* Clear cold-boot flag */
1691 phantom_writel ( phantom, 0, UNM_CAM_RAM_COLD_BOOT );
1693 /* Set port modes */
1694 phantom_writel ( phantom, UNM_CAM_RAM_PORT_MODE_AUTO_NEG,
1695 UNM_CAM_RAM_PORT_MODE );
1696 phantom_writel ( phantom, UNM_CAM_RAM_PORT_MODE_AUTO_NEG_1G,
1697 UNM_CAM_RAM_WOL_PORT_MODE );
1699 /* Pass dummy DMA area to card */
1700 dummy_dma_phys = virt_to_bus ( phantom->dma_buf->dummy_dma );
1701 DBGC ( phantom, "Phantom %p dummy DMA at %08lx\n",
1702 phantom, dummy_dma_phys );
1703 phantom_write_hilo ( phantom, dummy_dma_phys,
1704 UNM_NIC_REG_DUMMY_BUF_ADDR_LO,
1705 UNM_NIC_REG_DUMMY_BUF_ADDR_HI );
1706 phantom_writel ( phantom, UNM_NIC_REG_DUMMY_BUF_INIT,
1707 UNM_NIC_REG_DUMMY_BUF );
1709 /* Tell the hardware that tuning is complete */
1710 phantom_writel ( phantom, 1, UNM_ROMUSB_GLB_PEGTUNE_DONE );
1712 /* Wait for command PEG to finish initialising */
1713 DBGC ( phantom, "Phantom %p initialising command PEG (will take up to "
1714 "%d seconds)...\n", phantom, PHN_CMDPEG_INIT_TIMEOUT_SEC );
1715 for ( retries = 0; retries < PHN_CMDPEG_INIT_TIMEOUT_SEC; retries++ ) {
1716 cmdpeg_state = phantom_readl ( phantom,
1717 UNM_NIC_REG_CMDPEG_STATE );
1718 if ( cmdpeg_state != last_cmdpeg_state ) {
1719 DBGC ( phantom, "Phantom %p command PEG state is "
1720 "%08lx after %d seconds...\n",
1721 phantom, cmdpeg_state, retries );
1722 last_cmdpeg_state = cmdpeg_state;
1724 if ( cmdpeg_state == UNM_NIC_REG_CMDPEG_STATE_INITIALIZED ) {
1725 /* Acknowledge the PEG initialisation */
1726 phantom_writel ( phantom,
1727 UNM_NIC_REG_CMDPEG_STATE_INITIALIZE_ACK,
1728 UNM_NIC_REG_CMDPEG_STATE );
1734 DBGC ( phantom, "Phantom %p timed out waiting for command PEG to "
1735 "initialise (status %08lx)\n", phantom, cmdpeg_state );
1740 * Read Phantom MAC address
1742 * @v phanton_port Phantom NIC port
1743 * @v ll_addr Buffer to fill with MAC address
1745 static void phantom_get_macaddr ( struct phantom_nic_port *phantom_port,
1746 uint8_t *ll_addr ) {
1747 struct phantom_nic *phantom = phantom_port->phantom;
1749 uint8_t mac_addr[2][ETH_ALEN];
1752 unsigned long offset;
1755 /* Read the three dwords that include this MAC address and one other */
1756 offset = ( UNM_CAM_RAM_MAC_ADDRS +
1757 ( 12 * ( phantom_port->port / 2 ) ) );
1758 for ( i = 0 ; i < 3 ; i++, offset += 4 ) {
1759 u.dwords[i] = phantom_readl ( phantom, offset );
1762 /* Copy out the relevant MAC address */
1763 for ( i = 0 ; i < ETH_ALEN ; i++ ) {
1764 ll_addr[ ETH_ALEN - i - 1 ] =
1765 u.mac_addr[ phantom_port->port & 1 ][i];
1767 DBGC ( phantom, "Phantom %p port %d MAC address is %s\n",
1768 phantom, phantom_port->port, eth_ntoa ( ll_addr ) );
1772 * Initialise Phantom receive PEG
1774 * @v phantom Phantom NIC
1775 * @ret rc Return status code
1777 static int phantom_init_rcvpeg ( struct phantom_nic *phantom ) {
1778 unsigned int retries;
1779 uint32_t rcvpeg_state;
1780 uint32_t last_rcvpeg_state = 0;
1782 DBGC ( phantom, "Phantom %p initialising receive PEG (will take up to "
1783 "%d seconds)...\n", phantom, PHN_RCVPEG_INIT_TIMEOUT_SEC );
1784 for ( retries = 0; retries < PHN_RCVPEG_INIT_TIMEOUT_SEC; retries++ ) {
1785 rcvpeg_state = phantom_readl ( phantom,
1786 UNM_NIC_REG_RCVPEG_STATE );
1787 if ( rcvpeg_state != last_rcvpeg_state ) {
1788 DBGC ( phantom, "Phantom %p receive PEG state is "
1789 "%08lx after %d seconds...\n",
1790 phantom, rcvpeg_state, retries );
1791 last_rcvpeg_state = rcvpeg_state;
1793 if ( rcvpeg_state == UNM_NIC_REG_RCVPEG_STATE_INITIALIZED )
1798 DBGC ( phantom, "Phantom %p timed out waiting for receive PEG to "
1799 "initialise (status %08lx)\n", phantom, rcvpeg_state );
1808 * @ret rc Return status code
1810 static int phantom_probe ( struct pci_device *pci,
1811 const struct pci_device_id *id __unused ) {
1812 struct phantom_nic *phantom;
1813 struct net_device *netdev;
1814 struct phantom_nic_port *phantom_port;
1818 /* Phantom NICs expose multiple PCI functions, used for
1819 * virtualisation. Ignore everything except function 0.
1821 if ( PCI_FUNC ( pci->devfn ) != 0 )
1824 /* Allocate Phantom device */
1825 phantom = zalloc ( sizeof ( *phantom ) );
1828 goto err_alloc_phantom;
1830 pci_set_drvdata ( pci, phantom );
1832 /* Fix up PCI device */
1833 adjust_pci_device ( pci );
1836 if ( ( rc = phantom_map_crb ( phantom, pci ) ) != 0 )
1839 /* Read flash information */
1840 if ( ( rc = phantom_read_flash ( phantom ) ) != 0 )
1841 goto err_read_flash;
1843 /* Allocate net devices for each port */
1844 for ( i = 0 ; i < phantom->num_ports ; i++ ) {
1845 netdev = alloc_etherdev ( sizeof ( *phantom_port ) );
1848 goto err_alloc_etherdev;
1850 phantom->netdev[i] = netdev;
1851 netdev_init ( netdev, &phantom_operations );
1852 phantom_port = netdev_priv ( netdev );
1853 netdev->dev = &pci->dev;
1854 phantom_port->phantom = phantom;
1855 phantom_port->port = i;
1858 /* Allocate dummy DMA buffer and perform initial hardware handshake */
1859 phantom->dma_buf = malloc_dma ( sizeof ( *(phantom->dma_buf) ),
1860 UNM_DMA_BUFFER_ALIGN );
1861 if ( ! phantom->dma_buf )
1863 if ( ( rc = phantom_init_cmdpeg ( phantom ) ) != 0 )
1864 goto err_init_cmdpeg;
1866 /* Read MAC addresses */
1867 for ( i = 0 ; i < phantom->num_ports ; i++ ) {
1868 phantom_port = netdev_priv ( phantom->netdev[i] );
1869 phantom_get_macaddr ( phantom_port,
1870 phantom->netdev[i]->ll_addr );
1873 /* Initialise the receive firmware */
1874 if ( ( rc = phantom_init_rcvpeg ( phantom ) ) != 0 )
1875 goto err_init_rcvpeg;
1877 /* Register network devices */
1878 for ( i = 0 ; i < phantom->num_ports ; i++ ) {
1879 if ( ( rc = register_netdev ( phantom->netdev[i] ) ) != 0 ) {
1880 DBGC ( phantom, "Phantom %p could not register port "
1881 "%d: %s\n", phantom, i, strerror ( rc ) );
1882 goto err_register_netdev;
1888 i = ( phantom->num_ports - 1 );
1889 err_register_netdev:
1890 for ( ; i >= 0 ; i-- )
1891 unregister_netdev ( phantom->netdev[i] );
1894 free_dma ( phantom->dma_buf, sizeof ( *(phantom->dma_buf) ) );
1895 phantom->dma_buf = NULL;
1897 i = ( phantom->num_ports - 1 );
1899 for ( ; i >= 0 ; i-- ) {
1900 netdev_nullify ( phantom->netdev[i] );
1901 netdev_put ( phantom->netdev[i] );
1915 static void phantom_remove ( struct pci_device *pci ) {
1916 struct phantom_nic *phantom = pci_get_drvdata ( pci );
1919 for ( i = ( phantom->num_ports - 1 ) ; i >= 0 ; i-- )
1920 unregister_netdev ( phantom->netdev[i] );
1921 free_dma ( phantom->dma_buf, sizeof ( *(phantom->dma_buf) ) );
1922 phantom->dma_buf = NULL;
1923 for ( i = ( phantom->num_ports - 1 ) ; i >= 0 ; i-- ) {
1924 netdev_nullify ( phantom->netdev[i] );
1925 netdev_put ( phantom->netdev[i] );
1930 /** Phantom PCI IDs */
1931 static struct pci_device_id phantom_nics[] = {
1932 PCI_ROM ( 0x4040, 0x0100, "nx", "NX" ),
1935 /** Phantom PCI driver */
1936 struct pci_driver phantom_driver __pci_driver = {
1937 .ids = phantom_nics,
1938 .id_count = ( sizeof ( phantom_nics ) / sizeof ( phantom_nics[0] ) ),
1939 .probe = phantom_probe,
1940 .remove = phantom_remove,