Import from Etherboot 5.4
[people/peper/gpxe.git] / src / drivers / net / e1000.c
1 /**************************************************************************
2 Etherboot -  BOOTP/TFTP Bootstrap Program
3 Inter Pro 1000 for Etherboot
4 Drivers are port from Intel's Linux driver e1000-4.3.15
5
6 ***************************************************************************/
7 /*******************************************************************************
8
9   
10   Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
11   
12   This program is free software; you can redistribute it and/or modify it 
13   under the terms of the GNU General Public License as published by the Free 
14   Software Foundation; either version 2 of the License, or (at your option) 
15   any later version.
16   
17   This program is distributed in the hope that it will be useful, but WITHOUT 
18   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
19   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for 
20   more details.
21   
22   You should have received a copy of the GNU General Public License along with
23   this program; if not, write to the Free Software Foundation, Inc., 59 
24   Temple Place - Suite 330, Boston, MA  02111-1307, USA.
25   
26   The full GNU General Public License is included in this distribution in the
27   file called LICENSE.
28   
29   Contact Information:
30   Linux NICS <linux.nics@intel.com>
31   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
32
33 *******************************************************************************/
34 /*
35  *  Copyright (C) Archway Digital Solutions.
36  *
37  *  written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
38  *  2/9/2002
39  *
40  *  Copyright (C) Linux Networx.
41  *  Massive upgrade to work with the new intel gigabit NICs.
42  *  <ebiederman at lnxi dot com>
43  *
44  *  Support for 82541ei & 82547ei chips from Intel's Linux driver 5.1.13 added by
45  *  Georg Baum <gbaum@users.sf.net>, sponsored by PetaMem GmbH and linkLINE Communications, Inc.
46  *
47  *  01/2004: Updated to Linux driver 5.2.22 by Georg Baum <gbaum@users.sf.net>
48  */
49
50 /* to get some global routines like printf */
51 #include "etherboot.h"
52 /* to get the interface to the body of the program */
53 #include "nic.h"
54 /* to get the PCI support functions, if this is a PCI NIC */
55 #include "pci.h"
56 #include "timer.h"
57
58 typedef unsigned char *dma_addr_t;
59
60 typedef enum {
61         FALSE = 0,
62         TRUE = 1
63 } boolean_t;
64
65 #define DEBUG 0
66
67
68 /* Some pieces of code are disabled with #if 0 ... #endif.
69  * They are not deleted to show where the etherboot driver differs
70  * from the linux driver below the function level.
71  * Some member variables of the hw struct have been eliminated
72  * and the corresponding inplace checks inserted instead.
73  * Pieces such as LED handling that we definitely don't need are deleted.
74  *
75  * The following defines should not be needed normally,
76  * but may be helpful for debugging purposes. */
77
78 /* Define this if you want to program the transmission control register
79  * the way the Linux driver does it. */
80 #undef LINUX_DRIVER_TCTL
81
82 /* Define this to behave more like the Linux driver. */
83 #undef LINUX_DRIVER
84
85 #include "e1000_hw.h"
86
87 /* NIC specific static variables go here */
88 static struct nic_operations e1000_operations;
89 static struct pci_driver e1000_driver;
90
91 static struct e1000_hw hw;
92
93 struct {
94         char tx_pool[128 + 16];
95         char rx_pool[128 + 16];
96         char packet[2096];
97 } e1000_bufs __shared;
98
99 static struct e1000_tx_desc *tx_base;
100 static struct e1000_rx_desc *rx_base;
101
102 static int tx_tail;
103 static int rx_tail, rx_last;
104
105 /* Function forward declarations */
106 static int e1000_setup_link(struct e1000_hw *hw);
107 static int e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
108 static int e1000_setup_copper_link(struct e1000_hw *hw);
109 static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
110 static void e1000_config_collision_dist(struct e1000_hw *hw);
111 static int e1000_config_mac_to_phy(struct e1000_hw *hw);
112 static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
113 static int e1000_check_for_link(struct e1000_hw *hw);
114 static int e1000_wait_autoneg(struct e1000_hw *hw);
115 static void e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed, uint16_t *duplex);
116 static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
117 static int e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
118 static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data);
119 static int e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data);
120 static void e1000_phy_hw_reset(struct e1000_hw *hw);
121 static int e1000_phy_reset(struct e1000_hw *hw);
122 static int e1000_detect_gig_phy(struct e1000_hw *hw);
123 static void e1000_irq(struct nic *nic, irq_action_t action);
124
125 /* Printing macros... */
126
127 #define E1000_ERR(args...) printf("e1000: " args)
128
129 #if DEBUG >= 3
130 #define E1000_DBG(args...) printf("e1000: " args)
131 #else
132 #define E1000_DBG(args...)
133 #endif
134
135 #define MSGOUT(S, A, B)     printk(S "\n", A, B)
136 #if DEBUG >= 2
137 #define DEBUGFUNC(F)        DEBUGOUT(F "\n");
138 #else
139 #define DEBUGFUNC(F)
140 #endif
141 #if DEBUG >= 1
142 #define DEBUGOUT(S) printf(S)
143 #define DEBUGOUT1(S,A) printf(S,A)
144 #define DEBUGOUT2(S,A,B) printf(S,A,B)
145 #define DEBUGOUT3(S,A,B,C) printf(S,A,B,C)
146 #define DEBUGOUT7(S,A,B,C,D,E,F,G) printf(S,A,B,C,D,E,F,G)
147 #else
148 #define DEBUGOUT(S)
149 #define DEBUGOUT1(S,A)
150 #define DEBUGOUT2(S,A,B)
151 #define DEBUGOUT3(S,A,B,C)
152 #define DEBUGOUT7(S,A,B,C,D,E,F,G)
153 #endif
154
155 #define E1000_WRITE_REG(a, reg, value) ( \
156     ((a)->mac_type >= e1000_82543) ? \
157         (writel((value), ((a)->hw_addr + E1000_##reg))) : \
158         (writel((value), ((a)->hw_addr + E1000_82542_##reg))))
159
160 #define E1000_READ_REG(a, reg) ( \
161     ((a)->mac_type >= e1000_82543) ? \
162         readl((a)->hw_addr + E1000_##reg) : \
163         readl((a)->hw_addr + E1000_82542_##reg))
164
165 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \
166     ((a)->mac_type >= e1000_82543) ? \
167         writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2))) : \
168         writel((value), ((a)->hw_addr + E1000_82542_##reg + ((offset) << 2))))
169
170 #define E1000_READ_REG_ARRAY(a, reg, offset) ( \
171     ((a)->mac_type >= e1000_82543) ? \
172         readl((a)->hw_addr + E1000_##reg + ((offset) << 2)) : \
173         readl((a)->hw_addr + E1000_82542_##reg + ((offset) << 2)))
174
175 #define E1000_WRITE_FLUSH(a) {uint32_t x; x = E1000_READ_REG(a, STATUS);}
176
177 static inline uint32_t
178 e1000_io_read(struct e1000_hw *hw __unused, uint32_t port)
179 {
180         return inl(port);
181 }
182
183 static inline void
184 e1000_io_write(struct e1000_hw *hw __unused, uint32_t port, uint32_t value)
185 {
186         outl(value, port);
187 }
188
189 static inline void e1000_pci_set_mwi(struct e1000_hw *hw)
190 {
191         pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
192 }
193
194 static inline void e1000_pci_clear_mwi(struct e1000_hw *hw)
195 {
196         pci_write_config_word(hw->pdev, PCI_COMMAND,
197                               hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
198 }
199
200 /******************************************************************************
201  * Raises the EEPROM's clock input.
202  *
203  * hw - Struct containing variables accessed by shared code
204  * eecd - EECD's current value
205  *****************************************************************************/
206 static void
207 e1000_raise_ee_clk(struct e1000_hw *hw,
208                    uint32_t *eecd)
209 {
210         /* Raise the clock input to the EEPROM (by setting the SK bit), and then
211          * wait <delay> microseconds.
212          */
213         *eecd = *eecd | E1000_EECD_SK;
214         E1000_WRITE_REG(hw, EECD, *eecd);
215         E1000_WRITE_FLUSH(hw);
216         udelay(hw->eeprom.delay_usec);
217 }
218
219 /******************************************************************************
220  * Lowers the EEPROM's clock input.
221  *
222  * hw - Struct containing variables accessed by shared code 
223  * eecd - EECD's current value
224  *****************************************************************************/
225 static void
226 e1000_lower_ee_clk(struct e1000_hw *hw,
227                    uint32_t *eecd)
228 {
229         /* Lower the clock input to the EEPROM (by clearing the SK bit), and then 
230          * wait 50 microseconds. 
231          */
232         *eecd = *eecd & ~E1000_EECD_SK;
233         E1000_WRITE_REG(hw, EECD, *eecd);
234         E1000_WRITE_FLUSH(hw);
235         udelay(hw->eeprom.delay_usec);
236 }
237
238 /******************************************************************************
239  * Shift data bits out to the EEPROM.
240  *
241  * hw - Struct containing variables accessed by shared code
242  * data - data to send to the EEPROM
243  * count - number of bits to shift out
244  *****************************************************************************/
245 static void
246 e1000_shift_out_ee_bits(struct e1000_hw *hw,
247                         uint16_t data,
248                         uint16_t count)
249 {
250         struct e1000_eeprom_info *eeprom = &hw->eeprom;
251         uint32_t eecd;
252         uint32_t mask;
253         
254         /* We need to shift "count" bits out to the EEPROM. So, value in the
255          * "data" parameter will be shifted out to the EEPROM one bit at a time.
256          * In order to do this, "data" must be broken down into bits. 
257          */
258         mask = 0x01 << (count - 1);
259         eecd = E1000_READ_REG(hw, EECD);
260         if (eeprom->type == e1000_eeprom_microwire) {
261                 eecd &= ~E1000_EECD_DO;
262         } else if (eeprom->type == e1000_eeprom_spi) {
263                 eecd |= E1000_EECD_DO;
264         }
265         do {
266                 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
267                  * and then raising and then lowering the clock (the SK bit controls
268                  * the clock input to the EEPROM).  A "0" is shifted out to the EEPROM
269                  * by setting "DI" to "0" and then raising and then lowering the clock.
270                  */
271                 eecd &= ~E1000_EECD_DI;
272                 
273                 if(data & mask)
274                         eecd |= E1000_EECD_DI;
275                 
276                 E1000_WRITE_REG(hw, EECD, eecd);
277                 E1000_WRITE_FLUSH(hw);
278                 
279                 udelay(eeprom->delay_usec);
280                 
281                 e1000_raise_ee_clk(hw, &eecd);
282                 e1000_lower_ee_clk(hw, &eecd);
283                 
284                 mask = mask >> 1;
285                 
286         } while(mask);
287
288         /* We leave the "DI" bit set to "0" when we leave this routine. */
289         eecd &= ~E1000_EECD_DI;
290         E1000_WRITE_REG(hw, EECD, eecd);
291 }
292
293 /******************************************************************************
294  * Shift data bits in from the EEPROM
295  *
296  * hw - Struct containing variables accessed by shared code
297  *****************************************************************************/
298 static uint16_t
299 e1000_shift_in_ee_bits(struct e1000_hw *hw,
300                        uint16_t count)
301 {
302         uint32_t eecd;
303         uint32_t i;
304         uint16_t data;
305         
306         /* In order to read a register from the EEPROM, we need to shift 'count' 
307          * bits in from the EEPROM. Bits are "shifted in" by raising the clock
308          * input to the EEPROM (setting the SK bit), and then reading the value of
309          * the "DO" bit.  During this "shifting in" process the "DI" bit should
310          * always be clear.
311          */
312         
313         eecd = E1000_READ_REG(hw, EECD);
314         
315         eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
316         data = 0;
317         
318         for(i = 0; i < count; i++) {
319                 data = data << 1;
320                 e1000_raise_ee_clk(hw, &eecd);
321                 
322                 eecd = E1000_READ_REG(hw, EECD);
323                 
324                 eecd &= ~(E1000_EECD_DI);
325                 if(eecd & E1000_EECD_DO)
326                         data |= 1;
327                 
328                 e1000_lower_ee_clk(hw, &eecd);
329         }
330         
331         return data;
332 }
333
334 /******************************************************************************
335  * Prepares EEPROM for access
336  *
337  * hw - Struct containing variables accessed by shared code
338  *
339  * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 
340  * function should be called before issuing a command to the EEPROM.
341  *****************************************************************************/
342 static int32_t
343 e1000_acquire_eeprom(struct e1000_hw *hw)
344 {
345         struct e1000_eeprom_info *eeprom = &hw->eeprom;
346         uint32_t eecd, i=0;
347
348         eecd = E1000_READ_REG(hw, EECD);
349
350         /* Request EEPROM Access */
351         if(hw->mac_type > e1000_82544) {
352                 eecd |= E1000_EECD_REQ;
353                 E1000_WRITE_REG(hw, EECD, eecd);
354                 eecd = E1000_READ_REG(hw, EECD);
355                 while((!(eecd & E1000_EECD_GNT)) &&
356                       (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
357                         i++;
358                         udelay(5);
359                         eecd = E1000_READ_REG(hw, EECD);
360                 }
361                 if(!(eecd & E1000_EECD_GNT)) {
362                         eecd &= ~E1000_EECD_REQ;
363                         E1000_WRITE_REG(hw, EECD, eecd);
364                         DEBUGOUT("Could not acquire EEPROM grant\n");
365                         return -E1000_ERR_EEPROM;
366                 }
367         }
368
369         /* Setup EEPROM for Read/Write */
370
371         if (eeprom->type == e1000_eeprom_microwire) {
372                 /* Clear SK and DI */
373                 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
374                 E1000_WRITE_REG(hw, EECD, eecd);
375
376                 /* Set CS */
377                 eecd |= E1000_EECD_CS;
378                 E1000_WRITE_REG(hw, EECD, eecd);
379         } else if (eeprom->type == e1000_eeprom_spi) {
380                 /* Clear SK and CS */
381                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
382                 E1000_WRITE_REG(hw, EECD, eecd);
383                 udelay(1);
384         }
385
386         return E1000_SUCCESS;
387 }
388
389 /******************************************************************************
390  * Returns EEPROM to a "standby" state
391  * 
392  * hw - Struct containing variables accessed by shared code
393  *****************************************************************************/
394 static void
395 e1000_standby_eeprom(struct e1000_hw *hw)
396 {
397         struct e1000_eeprom_info *eeprom = &hw->eeprom;
398         uint32_t eecd;
399         
400         eecd = E1000_READ_REG(hw, EECD);
401
402         if(eeprom->type == e1000_eeprom_microwire) {
403
404                 /* Deselect EEPROM */
405                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
406                 E1000_WRITE_REG(hw, EECD, eecd);
407                 E1000_WRITE_FLUSH(hw);
408                 udelay(eeprom->delay_usec);
409         
410                 /* Clock high */
411                 eecd |= E1000_EECD_SK;
412                 E1000_WRITE_REG(hw, EECD, eecd);
413                 E1000_WRITE_FLUSH(hw);
414                 udelay(eeprom->delay_usec);
415         
416                 /* Select EEPROM */
417                 eecd |= E1000_EECD_CS;
418                 E1000_WRITE_REG(hw, EECD, eecd);
419                 E1000_WRITE_FLUSH(hw);
420                 udelay(eeprom->delay_usec);
421
422                 /* Clock low */
423                 eecd &= ~E1000_EECD_SK;
424                 E1000_WRITE_REG(hw, EECD, eecd);
425                 E1000_WRITE_FLUSH(hw);
426                 udelay(eeprom->delay_usec);
427         } else if(eeprom->type == e1000_eeprom_spi) {
428                 /* Toggle CS to flush commands */
429                 eecd |= E1000_EECD_CS;
430                 E1000_WRITE_REG(hw, EECD, eecd);
431                 E1000_WRITE_FLUSH(hw);
432                 udelay(eeprom->delay_usec);
433                 eecd &= ~E1000_EECD_CS;
434                 E1000_WRITE_REG(hw, EECD, eecd);
435                 E1000_WRITE_FLUSH(hw);
436                 udelay(eeprom->delay_usec);
437         }
438 }
439
440 /******************************************************************************
441  * Terminates a command by inverting the EEPROM's chip select pin
442  *
443  * hw - Struct containing variables accessed by shared code
444  *****************************************************************************/
445 static void
446 e1000_release_eeprom(struct e1000_hw *hw)
447 {
448         uint32_t eecd;
449
450         eecd = E1000_READ_REG(hw, EECD);
451
452         if (hw->eeprom.type == e1000_eeprom_spi) {
453                 eecd |= E1000_EECD_CS;  /* Pull CS high */
454                 eecd &= ~E1000_EECD_SK; /* Lower SCK */
455
456                 E1000_WRITE_REG(hw, EECD, eecd);
457
458                 udelay(hw->eeprom.delay_usec);
459         } else if(hw->eeprom.type == e1000_eeprom_microwire) {
460                 /* cleanup eeprom */
461
462                 /* CS on Microwire is active-high */
463                 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
464
465                 E1000_WRITE_REG(hw, EECD, eecd);
466
467                 /* Rising edge of clock */
468                 eecd |= E1000_EECD_SK;
469                 E1000_WRITE_REG(hw, EECD, eecd);
470                 E1000_WRITE_FLUSH(hw);
471                 udelay(hw->eeprom.delay_usec);
472
473                 /* Falling edge of clock */
474                 eecd &= ~E1000_EECD_SK;
475                 E1000_WRITE_REG(hw, EECD, eecd);
476                 E1000_WRITE_FLUSH(hw);
477                 udelay(hw->eeprom.delay_usec);
478         }
479
480         /* Stop requesting EEPROM access */
481         if(hw->mac_type > e1000_82544) {
482                 eecd &= ~E1000_EECD_REQ;
483                 E1000_WRITE_REG(hw, EECD, eecd);
484         }
485 }
486
487 /******************************************************************************
488  * Reads a 16 bit word from the EEPROM.
489  *
490  * hw - Struct containing variables accessed by shared code
491  *****************************************************************************/
492 static int32_t
493 e1000_spi_eeprom_ready(struct e1000_hw *hw)
494 {
495         uint16_t retry_count = 0;
496         uint8_t spi_stat_reg;
497
498         /* Read "Status Register" repeatedly until the LSB is cleared.  The
499          * EEPROM will signal that the command has been completed by clearing
500          * bit 0 of the internal status register.  If it's not cleared within
501          * 5 milliseconds, then error out.
502          */
503         retry_count = 0;
504         do {
505                 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
506                 hw->eeprom.opcode_bits);
507                 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
508                 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
509                         break;
510
511                 udelay(5);
512                 retry_count += 5;
513
514         } while(retry_count < EEPROM_MAX_RETRY_SPI);
515
516         /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
517          * only 0-5mSec on 5V devices)
518          */
519         if(retry_count >= EEPROM_MAX_RETRY_SPI) {
520                 DEBUGOUT("SPI EEPROM Status error\n");
521                 return -E1000_ERR_EEPROM;
522         }
523
524         return E1000_SUCCESS;
525 }
526
527 /******************************************************************************
528  * Reads a 16 bit word from the EEPROM.
529  *
530  * hw - Struct containing variables accessed by shared code
531  * offset - offset of  word in the EEPROM to read
532  * data - word read from the EEPROM
533  * words - number of words to read
534  *****************************************************************************/
535 static int
536 e1000_read_eeprom(struct e1000_hw *hw,
537                   uint16_t offset,
538                   uint16_t words,
539                   uint16_t *data)
540 {
541         struct e1000_eeprom_info *eeprom = &hw->eeprom;
542         uint32_t i = 0;
543         
544         DEBUGFUNC("e1000_read_eeprom");
545
546         /* A check for invalid values:  offset too large, too many words, and not
547          * enough words.
548          */
549         if((offset > eeprom->word_size) || (words > eeprom->word_size - offset) ||
550            (words == 0)) {
551                 DEBUGOUT("\"words\" parameter out of bounds\n");
552                 return -E1000_ERR_EEPROM;
553         }
554
555         /*  Prepare the EEPROM for reading  */
556         if(e1000_acquire_eeprom(hw) != E1000_SUCCESS)
557                 return -E1000_ERR_EEPROM;
558
559         if(eeprom->type == e1000_eeprom_spi) {
560                 uint16_t word_in;
561                 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
562
563                 if(e1000_spi_eeprom_ready(hw)) {
564                         e1000_release_eeprom(hw);
565                         return -E1000_ERR_EEPROM;
566                 }
567
568                 e1000_standby_eeprom(hw);
569
570                 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
571                 if((eeprom->address_bits == 8) && (offset >= 128))
572                         read_opcode |= EEPROM_A8_OPCODE_SPI;
573
574                 /* Send the READ command (opcode + addr)  */
575                 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
576                 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
577
578                 /* Read the data.  The address of the eeprom internally increments with
579                  * each byte (spi) being read, saving on the overhead of eeprom setup
580                  * and tear-down.  The address counter will roll over if reading beyond
581                  * the size of the eeprom, thus allowing the entire memory to be read
582                  * starting from any offset. */
583                 for (i = 0; i < words; i++) {
584                         word_in = e1000_shift_in_ee_bits(hw, 16);
585                         data[i] = (word_in >> 8) | (word_in << 8);
586                 }
587         } else if(eeprom->type == e1000_eeprom_microwire) {
588                 for (i = 0; i < words; i++) {
589                         /*  Send the READ command (opcode + addr)  */
590                         e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
591                                                 eeprom->opcode_bits);
592                         e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
593                                                 eeprom->address_bits);
594
595                         /* Read the data.  For microwire, each word requires the overhead
596                          * of eeprom setup and tear-down. */
597                         data[i] = e1000_shift_in_ee_bits(hw, 16);
598                         e1000_standby_eeprom(hw);
599                 }
600         }
601
602         /* End this read operation */
603         e1000_release_eeprom(hw);
604
605         return E1000_SUCCESS;
606 }
607
608 /******************************************************************************
609  * Verifies that the EEPROM has a valid checksum
610  * 
611  * hw - Struct containing variables accessed by shared code
612  *
613  * Reads the first 64 16 bit words of the EEPROM and sums the values read.
614  * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
615  * valid.
616  *****************************************************************************/
617 static int
618 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
619 {
620         uint16_t checksum = 0;
621         uint16_t i, eeprom_data;
622
623         DEBUGFUNC("e1000_validate_eeprom_checksum");
624
625         for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
626                 if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
627                         DEBUGOUT("EEPROM Read Error\n");
628                         return -E1000_ERR_EEPROM;
629                 }
630                 checksum += eeprom_data;
631         }
632         
633         if(checksum == (uint16_t) EEPROM_SUM)
634                 return E1000_SUCCESS;
635         else {
636                 DEBUGOUT("EEPROM Checksum Invalid\n");    
637                 return -E1000_ERR_EEPROM;
638         }
639 }
640
641 /******************************************************************************
642  * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
643  * second function of dual function devices
644  *
645  * hw - Struct containing variables accessed by shared code
646  *****************************************************************************/
647 static int 
648 e1000_read_mac_addr(struct e1000_hw *hw)
649 {
650         uint16_t offset;
651         uint16_t eeprom_data;
652         int i;
653
654         DEBUGFUNC("e1000_read_mac_addr");
655
656         for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
657                 offset = i >> 1;
658                 if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
659                         DEBUGOUT("EEPROM Read Error\n");
660                         return -E1000_ERR_EEPROM;
661                 }
662                 hw->mac_addr[i] = eeprom_data & 0xff;
663                 hw->mac_addr[i+1] = (eeprom_data >> 8) & 0xff;
664         }
665         if(((hw->mac_type == e1000_82546) || (hw->mac_type == e1000_82546_rev_3)) &&
666                 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1))
667                 /* Invert the last bit if this is the second device */
668                 hw->mac_addr[5] ^= 1;
669         return E1000_SUCCESS;
670 }
671
672 /******************************************************************************
673  * Initializes receive address filters.
674  *
675  * hw - Struct containing variables accessed by shared code 
676  *
677  * Places the MAC address in receive address register 0 and clears the rest
678  * of the receive addresss registers. Clears the multicast table. Assumes
679  * the receiver is in reset when the routine is called.
680  *****************************************************************************/
681 static void
682 e1000_init_rx_addrs(struct e1000_hw *hw)
683 {
684         uint32_t i;
685         uint32_t addr_low;
686         uint32_t addr_high;
687         
688         DEBUGFUNC("e1000_init_rx_addrs");
689         
690         /* Setup the receive address. */
691         DEBUGOUT("Programming MAC Address into RAR[0]\n");
692         addr_low = (hw->mac_addr[0] |
693                 (hw->mac_addr[1] << 8) |
694                 (hw->mac_addr[2] << 16) | (hw->mac_addr[3] << 24));
695         
696         addr_high = (hw->mac_addr[4] |
697                 (hw->mac_addr[5] << 8) | E1000_RAH_AV);
698         
699         E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
700         E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
701         
702         /* Zero out the other 15 receive addresses. */
703         DEBUGOUT("Clearing RAR[1-15]\n");
704         for(i = 1; i < E1000_RAR_ENTRIES; i++) {
705                 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
706                 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
707         }
708 }
709
710 /******************************************************************************
711  * Clears the VLAN filer table
712  *
713  * hw - Struct containing variables accessed by shared code
714  *****************************************************************************/
715 static void
716 e1000_clear_vfta(struct e1000_hw *hw)
717 {
718         uint32_t offset;
719     
720         for(offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
721                 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
722 }
723
724 /******************************************************************************
725 * Writes a value to one of the devices registers using port I/O (as opposed to
726 * memory mapped I/O). Only 82544 and newer devices support port I/O. *
727 * hw - Struct containing variables accessed by shared code
728 * offset - offset to write to * value - value to write
729 *****************************************************************************/
730 static inline void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset,
731                                       uint32_t value){
732         e1000_io_write(hw, hw->io_base, offset);
733         e1000_io_write(hw, hw->io_base + 4, value);
734 }
735
736 /******************************************************************************
737  * Set the phy type member in the hw struct.
738  *
739  * hw - Struct containing variables accessed by shared code
740  *****************************************************************************/
741 static int32_t
742 e1000_set_phy_type(struct e1000_hw *hw)
743 {
744         DEBUGFUNC("e1000_set_phy_type");
745
746         switch(hw->phy_id) {
747         case M88E1000_E_PHY_ID:
748         case M88E1000_I_PHY_ID:
749         case M88E1011_I_PHY_ID:
750                 hw->phy_type = e1000_phy_m88;
751                 break;
752         case IGP01E1000_I_PHY_ID:
753                 hw->phy_type = e1000_phy_igp;
754                 break;
755         default:
756                 /* Should never have loaded on this device */
757                 hw->phy_type = e1000_phy_undefined;
758                 return -E1000_ERR_PHY_TYPE;
759         }
760
761         return E1000_SUCCESS;
762 }
763
764 /******************************************************************************
765  * IGP phy init script - initializes the GbE PHY
766  *
767  * hw - Struct containing variables accessed by shared code
768  *****************************************************************************/
769 static void
770 e1000_phy_init_script(struct e1000_hw *hw)
771 {
772         DEBUGFUNC("e1000_phy_init_script");
773
774 #if 0
775         /* See e1000_sw_init() of the Linux driver */
776         if(hw->phy_init_script) {
777 #else
778         if((hw->mac_type == e1000_82541) ||
779            (hw->mac_type == e1000_82547) ||
780            (hw->mac_type == e1000_82541_rev_2) ||
781            (hw->mac_type == e1000_82547_rev_2)) {
782 #endif
783                 mdelay(20);
784
785                 e1000_write_phy_reg(hw,0x0000,0x0140);
786
787                 mdelay(5);
788
789                 if(hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547) {
790                         e1000_write_phy_reg(hw, 0x1F95, 0x0001);
791
792                         e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
793
794                         e1000_write_phy_reg(hw, 0x1F79, 0x0018);
795
796                         e1000_write_phy_reg(hw, 0x1F30, 0x1600);
797
798                         e1000_write_phy_reg(hw, 0x1F31, 0x0014);
799
800                         e1000_write_phy_reg(hw, 0x1F32, 0x161C);
801
802                         e1000_write_phy_reg(hw, 0x1F94, 0x0003);
803
804                         e1000_write_phy_reg(hw, 0x1F96, 0x003F);
805
806                         e1000_write_phy_reg(hw, 0x2010, 0x0008);
807                 } else {
808                         e1000_write_phy_reg(hw, 0x1F73, 0x0099);
809                 }
810
811                 e1000_write_phy_reg(hw, 0x0000, 0x3300);
812
813
814                 if(hw->mac_type == e1000_82547) {
815                         uint16_t fused, fine, coarse;
816
817                         /* Move to analog registers page */
818                         e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
819
820                         if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
821                                 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
822
823                                 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
824                                 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
825
826                                 if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
827                                         coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
828                                         fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
829                                 } else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
830                                         fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
831
832                                 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
833                                         (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
834                                         (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
835
836                                 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
837                                 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
838                                                 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
839                         }
840                 }
841         }
842 }
843
844 /******************************************************************************
845  * Set the mac type member in the hw struct.
846  * 
847  * hw - Struct containing variables accessed by shared code
848  *****************************************************************************/
849 static int
850 e1000_set_mac_type(struct e1000_hw *hw)
851 {
852         DEBUGFUNC("e1000_set_mac_type");
853
854         switch (hw->device_id) {
855         case E1000_DEV_ID_82542:
856                 switch (hw->revision_id) {
857                 case E1000_82542_2_0_REV_ID:
858                         hw->mac_type = e1000_82542_rev2_0;
859                         break;
860                 case E1000_82542_2_1_REV_ID:
861                         hw->mac_type = e1000_82542_rev2_1;
862                         break;
863                 default:
864                         /* Invalid 82542 revision ID */
865                         return -E1000_ERR_MAC_TYPE;
866                 }
867                 break;
868         case E1000_DEV_ID_82543GC_FIBER:
869         case E1000_DEV_ID_82543GC_COPPER:
870                 hw->mac_type = e1000_82543;
871                 break;
872         case E1000_DEV_ID_82544EI_COPPER:
873         case E1000_DEV_ID_82544EI_FIBER:
874         case E1000_DEV_ID_82544GC_COPPER:
875         case E1000_DEV_ID_82544GC_LOM:
876                 hw->mac_type = e1000_82544;
877                 break;
878         case E1000_DEV_ID_82540EM:
879         case E1000_DEV_ID_82540EM_LOM:
880         case E1000_DEV_ID_82540EP:
881         case E1000_DEV_ID_82540EP_LOM:
882         case E1000_DEV_ID_82540EP_LP:
883                 hw->mac_type = e1000_82540;
884                 break;
885         case E1000_DEV_ID_82545EM_COPPER:
886         case E1000_DEV_ID_82545EM_FIBER:
887                 hw->mac_type = e1000_82545;
888                 break;
889         case E1000_DEV_ID_82545GM_COPPER:
890         case E1000_DEV_ID_82545GM_FIBER:
891         case E1000_DEV_ID_82545GM_SERDES:
892                 hw->mac_type = e1000_82545_rev_3;
893                 break;
894         case E1000_DEV_ID_82546EB_COPPER:
895         case E1000_DEV_ID_82546EB_FIBER:
896         case E1000_DEV_ID_82546EB_QUAD_COPPER:
897                 hw->mac_type = e1000_82546;
898                 break;
899         case E1000_DEV_ID_82546GB_COPPER:
900         case E1000_DEV_ID_82546GB_FIBER:
901         case E1000_DEV_ID_82546GB_SERDES:
902                 hw->mac_type = e1000_82546_rev_3;
903                 break;
904         case E1000_DEV_ID_82541EI:
905         case E1000_DEV_ID_82541EI_MOBILE:
906                 hw->mac_type = e1000_82541;
907                 break;
908         case E1000_DEV_ID_82541ER:
909         case E1000_DEV_ID_82541GI:
910         case E1000_DEV_ID_82541GI_MOBILE:
911                 hw->mac_type = e1000_82541_rev_2;
912                 break;
913         case E1000_DEV_ID_82547EI:
914                 hw->mac_type = e1000_82547;
915                 break;
916         case E1000_DEV_ID_82547GI:
917                 hw->mac_type = e1000_82547_rev_2;
918                 break;
919         default:
920                 /* Should never have loaded on this device */
921                 return -E1000_ERR_MAC_TYPE;
922         }
923
924         return E1000_SUCCESS;
925 }
926
927 /*****************************************************************************
928  * Set media type and TBI compatibility.
929  *
930  * hw - Struct containing variables accessed by shared code
931  * **************************************************************************/
932 static void
933 e1000_set_media_type(struct e1000_hw *hw)
934 {
935         uint32_t status;
936
937         DEBUGFUNC("e1000_set_media_type");
938         
939         if(hw->mac_type != e1000_82543) {
940                 /* tbi_compatibility is only valid on 82543 */
941                 hw->tbi_compatibility_en = FALSE;
942         }
943
944         switch (hw->device_id) {
945                 case E1000_DEV_ID_82545GM_SERDES:
946                 case E1000_DEV_ID_82546GB_SERDES:
947                         hw->media_type = e1000_media_type_internal_serdes;
948                         break;
949                 default:
950                         if(hw->mac_type >= e1000_82543) {
951                                 status = E1000_READ_REG(hw, STATUS);
952                                 if(status & E1000_STATUS_TBIMODE) {
953                                         hw->media_type = e1000_media_type_fiber;
954                                         /* tbi_compatibility not valid on fiber */
955                                         hw->tbi_compatibility_en = FALSE;
956                                 } else {
957                                         hw->media_type = e1000_media_type_copper;
958                                 }
959                         } else {
960                                 /* This is an 82542 (fiber only) */
961                                 hw->media_type = e1000_media_type_fiber;
962                         }
963         }
964 }
965
966 /******************************************************************************
967  * Reset the transmit and receive units; mask and clear all interrupts.
968  *
969  * hw - Struct containing variables accessed by shared code
970  *****************************************************************************/
971 static void
972 e1000_reset_hw(struct e1000_hw *hw)
973 {
974         uint32_t ctrl;
975         uint32_t ctrl_ext;
976         uint32_t icr;
977         uint32_t manc;
978         
979         DEBUGFUNC("e1000_reset_hw");
980         
981         /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
982         if(hw->mac_type == e1000_82542_rev2_0) {
983                 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
984                 e1000_pci_clear_mwi(hw);
985         }
986
987         /* Clear interrupt mask to stop board from generating interrupts */
988         DEBUGOUT("Masking off all interrupts\n");
989         E1000_WRITE_REG(hw, IMC, 0xffffffff);
990         
991         /* Disable the Transmit and Receive units.  Then delay to allow
992          * any pending transactions to complete before we hit the MAC with
993          * the global reset.
994          */
995         E1000_WRITE_REG(hw, RCTL, 0);
996         E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
997         E1000_WRITE_FLUSH(hw);
998
999         /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
1000         hw->tbi_compatibility_on = FALSE;
1001
1002         /* Delay to allow any outstanding PCI transactions to complete before
1003          * resetting the device
1004          */ 
1005         mdelay(10);
1006
1007         ctrl = E1000_READ_REG(hw, CTRL);
1008
1009         /* Must reset the PHY before resetting the MAC */
1010         if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1011                 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
1012                 mdelay(5);
1013         }
1014
1015         /* Issue a global reset to the MAC.  This will reset the chip's
1016          * transmit, receive, DMA, and link units.  It will not effect
1017          * the current PCI configuration.  The global reset bit is self-
1018          * clearing, and should clear within a microsecond.
1019          */
1020         DEBUGOUT("Issuing a global reset to MAC\n");
1021
1022         switch(hw->mac_type) {
1023                 case e1000_82544:
1024                 case e1000_82540:
1025                 case e1000_82545:
1026                 case e1000_82546:
1027                 case e1000_82541:
1028                 case e1000_82541_rev_2:
1029                         /* These controllers can't ack the 64-bit write when issuing the
1030                          * reset, so use IO-mapping as a workaround to issue the reset */
1031                         E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
1032                         break;
1033                 case e1000_82545_rev_3:
1034                 case e1000_82546_rev_3:
1035                         /* Reset is performed on a shadow of the control register */
1036                         E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
1037                         break;
1038                 default:
1039                         E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
1040                         break;
1041         }
1042
1043         /* After MAC reset, force reload of EEPROM to restore power-on settings to
1044          * device.  Later controllers reload the EEPROM automatically, so just wait
1045          * for reload to complete.
1046          */
1047         switch(hw->mac_type) {
1048                 case e1000_82542_rev2_0:
1049                 case e1000_82542_rev2_1:
1050                 case e1000_82543:
1051                 case e1000_82544:
1052                         /* Wait for reset to complete */
1053                         udelay(10);
1054                         ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1055                         ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1056                         E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1057                         E1000_WRITE_FLUSH(hw);
1058                         /* Wait for EEPROM reload */
1059                         mdelay(2);
1060                         break;
1061                 case e1000_82541:
1062                 case e1000_82541_rev_2:
1063                 case e1000_82547:
1064                 case e1000_82547_rev_2:
1065                         /* Wait for EEPROM reload */
1066                         mdelay(20);
1067                         break;
1068                 default:
1069                         /* Wait for EEPROM reload (it happens automatically) */
1070                         mdelay(5);
1071                         break;
1072         }
1073
1074         /* Disable HW ARPs on ASF enabled adapters */
1075         if(hw->mac_type >= e1000_82540) {
1076                 manc = E1000_READ_REG(hw, MANC);
1077                 manc &= ~(E1000_MANC_ARP_EN);
1078                 E1000_WRITE_REG(hw, MANC, manc);
1079         }
1080
1081         if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1082                 e1000_phy_init_script(hw);
1083         }
1084
1085         /* Clear interrupt mask to stop board from generating interrupts */
1086         DEBUGOUT("Masking off all interrupts\n");
1087         E1000_WRITE_REG(hw, IMC, 0xffffffff);
1088         
1089         /* Clear any pending interrupt events. */
1090         icr = E1000_READ_REG(hw, ICR);
1091
1092         /* If MWI was previously enabled, reenable it. */
1093         if(hw->mac_type == e1000_82542_rev2_0) {
1094 #ifdef LINUX_DRIVER
1095                 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1096 #endif
1097                         e1000_pci_set_mwi(hw);
1098         }
1099 }
1100
1101 /******************************************************************************
1102  * Performs basic configuration of the adapter.
1103  *
1104  * hw - Struct containing variables accessed by shared code
1105  * 
1106  * Assumes that the controller has previously been reset and is in a 
1107  * post-reset uninitialized state. Initializes the receive address registers,
1108  * multicast table, and VLAN filter table. Calls routines to setup link
1109  * configuration and flow control settings. Clears all on-chip counters. Leaves
1110  * the transmit and receive units disabled and uninitialized.
1111  *****************************************************************************/
1112 static int
1113 e1000_init_hw(struct e1000_hw *hw)
1114 {
1115         uint32_t ctrl, status;
1116         uint32_t i;
1117         int32_t ret_val;
1118         uint16_t pcix_cmd_word;
1119         uint16_t pcix_stat_hi_word;
1120         uint16_t cmd_mmrbc;
1121         uint16_t stat_mmrbc;
1122         e1000_bus_type bus_type = e1000_bus_type_unknown;
1123
1124         DEBUGFUNC("e1000_init_hw");
1125
1126         /* Set the media type and TBI compatibility */
1127         e1000_set_media_type(hw);
1128
1129         /* Disabling VLAN filtering. */
1130         DEBUGOUT("Initializing the IEEE VLAN\n");
1131         E1000_WRITE_REG(hw, VET, 0);
1132         
1133         e1000_clear_vfta(hw);
1134         
1135         /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
1136         if(hw->mac_type == e1000_82542_rev2_0) {
1137                 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1138                 e1000_pci_clear_mwi(hw);
1139                 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
1140                 E1000_WRITE_FLUSH(hw);
1141                 mdelay(5);
1142         }
1143         
1144         /* Setup the receive address. This involves initializing all of the Receive
1145          * Address Registers (RARs 0 - 15).
1146          */
1147         e1000_init_rx_addrs(hw);
1148         
1149         /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
1150         if(hw->mac_type == e1000_82542_rev2_0) {
1151                 E1000_WRITE_REG(hw, RCTL, 0);
1152                 E1000_WRITE_FLUSH(hw);
1153                 mdelay(1);
1154 #ifdef LINUX_DRIVER
1155                 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1156 #endif
1157                         e1000_pci_set_mwi(hw);
1158         }
1159         
1160         /* Zero out the Multicast HASH table */
1161         DEBUGOUT("Zeroing the MTA\n");
1162         for(i = 0; i < E1000_MC_TBL_SIZE; i++)
1163                 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
1164         
1165 #if 0
1166         /* Set the PCI priority bit correctly in the CTRL register.  This
1167          * determines if the adapter gives priority to receives, or if it
1168          * gives equal priority to transmits and receives.
1169          */
1170         if(hw->dma_fairness) {
1171                 ctrl = E1000_READ_REG(hw, CTRL);
1172                 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
1173         }
1174 #endif
1175
1176         switch(hw->mac_type) {
1177                 case e1000_82545_rev_3:
1178                 case e1000_82546_rev_3:
1179                         break;
1180                 default:
1181                         if (hw->mac_type >= e1000_82543) {
1182                                 /* See e1000_get_bus_info() of the Linux driver */
1183                                 status = E1000_READ_REG(hw, STATUS);
1184                                 bus_type = (status & E1000_STATUS_PCIX_MODE) ?
1185                                         e1000_bus_type_pcix : e1000_bus_type_pci;
1186                         }
1187
1188                         /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
1189                         if(bus_type == e1000_bus_type_pcix) {
1190                                 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
1191                                 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
1192                                 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
1193                                         PCIX_COMMAND_MMRBC_SHIFT;
1194                                 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
1195                                         PCIX_STATUS_HI_MMRBC_SHIFT;
1196                                 if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
1197                                         stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
1198                                 if(cmd_mmrbc > stat_mmrbc) {
1199                                         pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
1200                                         pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
1201                                         pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER, pcix_cmd_word);
1202                                 }
1203                         }
1204                         break;
1205         }
1206
1207         /* Call a subroutine to configure the link and setup flow control. */
1208         ret_val = e1000_setup_link(hw);
1209         
1210         /* Set the transmit descriptor write-back policy */
1211         if(hw->mac_type > e1000_82544) {
1212                 ctrl = E1000_READ_REG(hw, TXDCTL);
1213                 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
1214                 E1000_WRITE_REG(hw, TXDCTL, ctrl);
1215         }
1216
1217 #if 0
1218         /* Clear all of the statistics registers (clear on read).  It is
1219          * important that we do this after we have tried to establish link
1220          * because the symbol error count will increment wildly if there
1221          * is no link.
1222          */
1223         e1000_clear_hw_cntrs(hw);
1224 #endif
1225
1226         return ret_val;
1227 }
1228
1229 /******************************************************************************
1230  * Adjust SERDES output amplitude based on EEPROM setting.
1231  *
1232  * hw - Struct containing variables accessed by shared code.
1233  *****************************************************************************/
1234 static int32_t
1235 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
1236 {
1237         uint16_t eeprom_data;
1238         int32_t  ret_val;
1239
1240         DEBUGFUNC("e1000_adjust_serdes_amplitude");
1241
1242         if(hw->media_type != e1000_media_type_internal_serdes)
1243                 return E1000_SUCCESS;
1244
1245         switch(hw->mac_type) {
1246                 case e1000_82545_rev_3:
1247                 case e1000_82546_rev_3:
1248                         break;
1249                 default:
1250                         return E1000_SUCCESS;
1251         }
1252
1253         if ((ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,
1254                                         &eeprom_data))) {
1255                 return ret_val;
1256         }
1257
1258         if(eeprom_data != EEPROM_RESERVED_WORD) {
1259                 /* Adjust SERDES output amplitude only. */
1260                 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
1261                 if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL,
1262                                                   eeprom_data)))
1263                         return ret_val;
1264         }
1265
1266         return E1000_SUCCESS;
1267 }
1268                                                                    
1269 /******************************************************************************
1270  * Configures flow control and link settings.
1271  * 
1272  * hw - Struct containing variables accessed by shared code
1273  * 
1274  * Determines which flow control settings to use. Calls the apropriate media-
1275  * specific link configuration function. Configures the flow control settings.
1276  * Assuming the adapter has a valid link partner, a valid link should be
1277  * established. Assumes the hardware has previously been reset and the 
1278  * transmitter and receiver are not enabled.
1279  *****************************************************************************/
1280 static int
1281 e1000_setup_link(struct e1000_hw *hw)
1282 {
1283         uint32_t ctrl_ext;
1284         int32_t ret_val;
1285         uint16_t eeprom_data;
1286
1287         DEBUGFUNC("e1000_setup_link");
1288         
1289         /* Read and store word 0x0F of the EEPROM. This word contains bits
1290          * that determine the hardware's default PAUSE (flow control) mode,
1291          * a bit that determines whether the HW defaults to enabling or
1292          * disabling auto-negotiation, and the direction of the
1293          * SW defined pins. If there is no SW over-ride of the flow
1294          * control setting, then the variable hw->fc will
1295          * be initialized based on a value in the EEPROM.
1296          */
1297         if(e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data) < 0) {
1298                 DEBUGOUT("EEPROM Read Error\n");
1299                 return -E1000_ERR_EEPROM;
1300         }
1301         
1302         if(hw->fc == e1000_fc_default) {
1303                 if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
1304                         hw->fc = e1000_fc_none;
1305                 else if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 
1306                         EEPROM_WORD0F_ASM_DIR)
1307                         hw->fc = e1000_fc_tx_pause;
1308                 else
1309                         hw->fc = e1000_fc_full;
1310         }
1311         
1312         /* We want to save off the original Flow Control configuration just
1313          * in case we get disconnected and then reconnected into a different
1314          * hub or switch with different Flow Control capabilities.
1315          */
1316         if(hw->mac_type == e1000_82542_rev2_0)
1317                 hw->fc &= (~e1000_fc_tx_pause);
1318
1319 #if 0
1320         /* See e1000_sw_init() of the Linux driver */
1321         if((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
1322 #else
1323         if((hw->mac_type < e1000_82543) && (hw->mac_type >= e1000_82543))
1324 #endif
1325                 hw->fc &= (~e1000_fc_rx_pause);
1326         
1327 #if 0
1328         hw->original_fc = hw->fc;
1329 #endif
1330
1331         DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
1332         
1333         /* Take the 4 bits from EEPROM word 0x0F that determine the initial
1334          * polarity value for the SW controlled pins, and setup the
1335          * Extended Device Control reg with that info.
1336          * This is needed because one of the SW controlled pins is used for
1337          * signal detection.  So this should be done before e1000_setup_pcs_link()
1338          * or e1000_phy_setup() is called.
1339          */
1340         if(hw->mac_type == e1000_82543) {
1341                 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 
1342                         SWDPIO__EXT_SHIFT);
1343                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1344         }
1345         
1346         /* Call the necessary subroutine to configure the link. */
1347         ret_val = (hw->media_type == e1000_media_type_copper) ?
1348                 e1000_setup_copper_link(hw) :
1349                 e1000_setup_fiber_serdes_link(hw);
1350         if (ret_val < 0) {
1351                 return ret_val;
1352         }
1353         
1354         /* Initialize the flow control address, type, and PAUSE timer
1355          * registers to their default values.  This is done even if flow
1356          * control is disabled, because it does not hurt anything to
1357          * initialize these registers.
1358          */
1359         DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
1360         
1361         E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1362         E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1363         E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1364 #if 0
1365         E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
1366 #else
1367         E1000_WRITE_REG(hw, FCTTV, FC_DEFAULT_TX_TIMER);
1368 #endif
1369         
1370         /* Set the flow control receive threshold registers.  Normally,
1371          * these registers will be set to a default threshold that may be
1372          * adjusted later by the driver's runtime code.  However, if the
1373          * ability to transmit pause frames in not enabled, then these
1374          * registers will be set to 0. 
1375          */
1376         if(!(hw->fc & e1000_fc_tx_pause)) {
1377                 E1000_WRITE_REG(hw, FCRTL, 0);
1378                 E1000_WRITE_REG(hw, FCRTH, 0);
1379         } else {
1380                 /* We need to set up the Receive Threshold high and low water marks
1381                  * as well as (optionally) enabling the transmission of XON frames.
1382                  */
1383 #if 0
1384                 if(hw->fc_send_xon) {
1385                         E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
1386                         E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1387                 } else {
1388                         E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
1389                         E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1390                 }
1391 #else
1392                 E1000_WRITE_REG(hw, FCRTL, (FC_DEFAULT_LO_THRESH | E1000_FCRTL_XONE));
1393                 E1000_WRITE_REG(hw, FCRTH, FC_DEFAULT_HI_THRESH);
1394 #endif
1395         }
1396         return ret_val;
1397 }
1398
1399 /******************************************************************************
1400  * Sets up link for a fiber based or serdes based adapter
1401  *
1402  * hw - Struct containing variables accessed by shared code
1403  *
1404  * Manipulates Physical Coding Sublayer functions in order to configure
1405  * link. Assumes the hardware has been previously reset and the transmitter
1406  * and receiver are not enabled.
1407  *****************************************************************************/
1408 static int
1409 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1410 {
1411         uint32_t ctrl;
1412         uint32_t status;
1413         uint32_t txcw = 0;
1414         uint32_t i;
1415         uint32_t signal = 0;
1416         int32_t ret_val;
1417
1418         DEBUGFUNC("e1000_setup_fiber_serdes_link");
1419
1420         /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be 
1421          * set when the optics detect a signal. On older adapters, it will be 
1422          * cleared when there is a signal.  This applies to fiber media only.
1423          * If we're on serdes media, adjust the output amplitude to value set in
1424          * the EEPROM.
1425          */
1426         ctrl = E1000_READ_REG(hw, CTRL);
1427         if(hw->media_type == e1000_media_type_fiber)
1428                 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
1429
1430         if((ret_val = e1000_adjust_serdes_amplitude(hw)))
1431                 return ret_val;
1432
1433         /* Take the link out of reset */
1434         ctrl &= ~(E1000_CTRL_LRST);
1435
1436 #if 0
1437         /* Adjust VCO speed to improve BER performance */
1438         if((ret_val = e1000_set_vco_speed(hw)))
1439                 return ret_val;
1440 #endif
1441
1442         e1000_config_collision_dist(hw);
1443         
1444         /* Check for a software override of the flow control settings, and setup
1445          * the device accordingly.  If auto-negotiation is enabled, then software
1446          * will have to set the "PAUSE" bits to the correct value in the Tranmsit
1447          * Config Word Register (TXCW) and re-start auto-negotiation.  However, if
1448          * auto-negotiation is disabled, then software will have to manually 
1449          * configure the two flow control enable bits in the CTRL register.
1450          *
1451          * The possible values of the "fc" parameter are:
1452          *      0:  Flow control is completely disabled
1453          *      1:  Rx flow control is enabled (we can receive pause frames, but 
1454          *          not send pause frames).
1455          *      2:  Tx flow control is enabled (we can send pause frames but we do
1456          *          not support receiving pause frames).
1457          *      3:  Both Rx and TX flow control (symmetric) are enabled.
1458          */
1459         switch (hw->fc) {
1460         case e1000_fc_none:
1461                 /* Flow control is completely disabled by a software over-ride. */
1462                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1463                 break;
1464         case e1000_fc_rx_pause:
1465                 /* RX Flow control is enabled and TX Flow control is disabled by a 
1466                  * software over-ride. Since there really isn't a way to advertise 
1467                  * that we are capable of RX Pause ONLY, we will advertise that we
1468                  * support both symmetric and asymmetric RX PAUSE. Later, we will
1469                  *  disable the adapter's ability to send PAUSE frames.
1470                  */
1471                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1472                 break;
1473         case e1000_fc_tx_pause:
1474                 /* TX Flow control is enabled, and RX Flow control is disabled, by a 
1475                  * software over-ride.
1476                  */
1477                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1478                 break;
1479         case e1000_fc_full:
1480                 /* Flow control (both RX and TX) is enabled by a software over-ride. */
1481                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1482                 break;
1483         default:
1484                 DEBUGOUT("Flow control param set incorrectly\n");
1485                 return -E1000_ERR_CONFIG;
1486                 break;
1487         }
1488         
1489         /* Since auto-negotiation is enabled, take the link out of reset (the link
1490          * will be in reset, because we previously reset the chip). This will
1491          * restart auto-negotiation.  If auto-neogtiation is successful then the
1492          * link-up status bit will be set and the flow control enable bits (RFCE
1493          * and TFCE) will be set according to their negotiated value.
1494          */
1495         DEBUGOUT("Auto-negotiation enabled\n");
1496         
1497         E1000_WRITE_REG(hw, TXCW, txcw);
1498         E1000_WRITE_REG(hw, CTRL, ctrl);
1499         E1000_WRITE_FLUSH(hw);
1500         
1501         hw->txcw = txcw;
1502         mdelay(1);
1503         
1504         /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
1505          * indication in the Device Status Register.  Time-out if a link isn't 
1506          * seen in 500 milliseconds seconds (Auto-negotiation should complete in 
1507          * less than 500 milliseconds even if the other end is doing it in SW).
1508          * For internal serdes, we just assume a signal is present, then poll.
1509          */
1510         if(hw->media_type == e1000_media_type_internal_serdes ||
1511            (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
1512                 DEBUGOUT("Looking for Link\n");
1513                 for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
1514                         mdelay(10);
1515                         status = E1000_READ_REG(hw, STATUS);
1516                         if(status & E1000_STATUS_LU) break;
1517                 }
1518                 if(i == (LINK_UP_TIMEOUT / 10)) {
1519                         DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1520                         hw->autoneg_failed = 1;
1521                         /* AutoNeg failed to achieve a link, so we'll call 
1522                          * e1000_check_for_link. This routine will force the link up if
1523                          * we detect a signal. This will allow us to communicate with
1524                          * non-autonegotiating link partners.
1525                          */
1526                         if((ret_val = e1000_check_for_link(hw))) {
1527                                 DEBUGOUT("Error while checking for link\n");
1528                                 return ret_val;
1529                         }
1530                         hw->autoneg_failed = 0;
1531                 } else {
1532                         hw->autoneg_failed = 0;
1533                         DEBUGOUT("Valid Link Found\n");
1534                 }
1535         } else {
1536                 DEBUGOUT("No Signal Detected\n");
1537         }
1538         return E1000_SUCCESS;
1539 }
1540
1541 /******************************************************************************
1542 * Detects which PHY is present and the speed and duplex
1543 *
1544 * hw - Struct containing variables accessed by shared code
1545 ******************************************************************************/
1546 static int
1547 e1000_setup_copper_link(struct e1000_hw *hw)
1548 {
1549         uint32_t ctrl;
1550         int32_t ret_val;
1551         uint16_t i;
1552         uint16_t phy_data;
1553         
1554         DEBUGFUNC("e1000_setup_copper_link");
1555         
1556         ctrl = E1000_READ_REG(hw, CTRL);
1557         /* With 82543, we need to force speed and duplex on the MAC equal to what
1558          * the PHY speed and duplex configuration is. In addition, we need to
1559          * perform a hardware reset on the PHY to take it out of reset.
1560          */
1561         if(hw->mac_type > e1000_82543) {
1562                 ctrl |= E1000_CTRL_SLU;
1563                 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1564                 E1000_WRITE_REG(hw, CTRL, ctrl);
1565         } else {
1566                 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1567                 E1000_WRITE_REG(hw, CTRL, ctrl);
1568                 e1000_phy_hw_reset(hw);
1569         }
1570         
1571         /* Make sure we have a valid PHY */
1572         if((ret_val = e1000_detect_gig_phy(hw))) {
1573                 DEBUGOUT("Error, did not detect valid phy.\n");
1574                 return ret_val;
1575         }
1576         DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
1577
1578         if(hw->mac_type <= e1000_82543 ||
1579            hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1580 #if 0
1581            hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
1582                 hw->phy_reset_disable = FALSE;
1583
1584         if(!hw->phy_reset_disable) {
1585 #else
1586            hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) {
1587 #endif
1588         if (hw->phy_type == e1000_phy_igp) {
1589
1590                 if((ret_val = e1000_phy_reset(hw))) {
1591                         DEBUGOUT("Error Resetting the PHY\n");
1592                         return ret_val;
1593                 }
1594
1595                 /* Wait 10ms for MAC to configure PHY from eeprom settings */
1596                 mdelay(15);
1597
1598 #if 0
1599                 /* disable lplu d3 during driver init */
1600                 if((ret_val = e1000_set_d3_lplu_state(hw, FALSE))) {
1601                         DEBUGOUT("Error Disabling LPLU D3\n");
1602                         return ret_val;
1603                 }
1604
1605                 /* Configure mdi-mdix settings */
1606                 if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
1607                                                  &phy_data)))
1608                         return ret_val;
1609
1610                 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1611                         hw->dsp_config_state = e1000_dsp_config_disabled;
1612                         /* Force MDI for IGP B-0 PHY */
1613                         phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX |
1614                                       IGP01E1000_PSCR_FORCE_MDI_MDIX);
1615                         hw->mdix = 1;
1616
1617                 } else {
1618                         hw->dsp_config_state = e1000_dsp_config_enabled;
1619                         phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1620
1621                         switch (hw->mdix) {
1622                         case 1:
1623                                 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1624                                 break;
1625                         case 2:
1626                                 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1627                                 break;
1628                         case 0:
1629                         default:
1630                                 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1631                                 break;
1632                         }
1633                 }
1634                 if((ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
1635                                                   phy_data)))
1636                         return ret_val;
1637
1638                 /* set auto-master slave resolution settings */
1639                 e1000_ms_type phy_ms_setting = hw->master_slave;
1640
1641                 if(hw->ffe_config_state == e1000_ffe_config_active)
1642                         hw->ffe_config_state = e1000_ffe_config_enabled;
1643
1644                 if(hw->dsp_config_state == e1000_dsp_config_activated)
1645                         hw->dsp_config_state = e1000_dsp_config_enabled;
1646 #endif
1647
1648                 /* when autonegotiation advertisment is only 1000Mbps then we
1649                  * should disable SmartSpeed and enable Auto MasterSlave
1650                  * resolution as hardware default. */
1651                 if(hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1652                         /* Disable SmartSpeed */
1653                         if((ret_val = e1000_read_phy_reg(hw,
1654                                                          IGP01E1000_PHY_PORT_CONFIG,
1655                                                          &phy_data)))
1656                                 return ret_val;
1657                         phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1658                         if((ret_val = e1000_write_phy_reg(hw,
1659                                                           IGP01E1000_PHY_PORT_CONFIG,
1660                                                           phy_data)))
1661                                 return ret_val;
1662                         /* Set auto Master/Slave resolution process */
1663                         if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
1664                                                          &phy_data)))
1665                                 return ret_val;
1666                         phy_data &= ~CR_1000T_MS_ENABLE;
1667                         if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
1668                                                           phy_data)))
1669                                 return ret_val;
1670                 }
1671
1672                 if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
1673                                                  &phy_data)))
1674                         return ret_val;
1675
1676 #if 0
1677                 /* load defaults for future use */
1678                 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1679                                             ((phy_data & CR_1000T_MS_VALUE) ?
1680                                              e1000_ms_force_master :
1681                                              e1000_ms_force_slave) :
1682                                              e1000_ms_auto;
1683
1684                 switch (phy_ms_setting) {
1685                 case e1000_ms_force_master:
1686                         phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1687                         break;
1688                 case e1000_ms_force_slave:
1689                         phy_data |= CR_1000T_MS_ENABLE;
1690                         phy_data &= ~(CR_1000T_MS_VALUE);
1691                         break;
1692                 case e1000_ms_auto:
1693                         phy_data &= ~CR_1000T_MS_ENABLE;
1694                 default:
1695                         break;
1696                 }
1697 #endif
1698
1699                 if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
1700                                                   phy_data)))
1701                         return ret_val;
1702         } else {
1703                 /* Enable CRS on TX. This must be set for half-duplex operation. */
1704                 if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1705                                                  &phy_data)))
1706                         return ret_val;
1707
1708                 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1709
1710                 /* Options:
1711                  *   MDI/MDI-X = 0 (default)
1712                  *   0 - Auto for all speeds
1713                  *   1 - MDI mode
1714                  *   2 - MDI-X mode
1715                  *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1716                  */
1717 #if 0
1718                 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1719
1720                 switch (hw->mdix) {
1721                 case 1:
1722                         phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1723                         break;
1724                 case 2:
1725                         phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1726                         break;
1727                 case 3:
1728                         phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1729                         break;
1730                 case 0:
1731                 default:
1732 #endif
1733                         phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1734 #if 0
1735                         break;
1736                 }
1737 #endif
1738
1739                 /* Options:
1740                  *   disable_polarity_correction = 0 (default)
1741                  *       Automatic Correction for Reversed Cable Polarity
1742                  *   0 - Disabled
1743                  *   1 - Enabled
1744                  */
1745                 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1746                 if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1747                                                   phy_data)))
1748                         return ret_val;
1749
1750                 /* Force TX_CLK in the Extended PHY Specific Control Register
1751                  * to 25MHz clock.
1752                  */
1753                 if((ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1754                                                  &phy_data)))
1755                         return ret_val;
1756
1757                 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1758
1759 #ifdef LINUX_DRIVER
1760                 if (hw->phy_revision < M88E1011_I_REV_4) {
1761 #endif
1762                         /* Configure Master and Slave downshift values */
1763                         phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1764                                 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1765                         phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1766                                 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1767                         if((ret_val = e1000_write_phy_reg(hw,
1768                                                           M88E1000_EXT_PHY_SPEC_CTRL,
1769                                                           phy_data)))
1770                                 return ret_val;
1771                 }
1772         
1773                 /* SW Reset the PHY so all changes take effect */
1774                 if((ret_val = e1000_phy_reset(hw))) {
1775                         DEBUGOUT("Error Resetting the PHY\n");
1776                         return ret_val;
1777 #ifdef LINUX_DRIVER
1778                 }
1779 #endif
1780         }
1781         
1782         /* Options:
1783          *   autoneg = 1 (default)
1784          *      PHY will advertise value(s) parsed from
1785          *      autoneg_advertised and fc
1786          *   autoneg = 0
1787          *      PHY will be set to 10H, 10F, 100H, or 100F
1788          *      depending on value parsed from forced_speed_duplex.
1789          */
1790         
1791         /* Is autoneg enabled?  This is enabled by default or by software
1792          * override.  If so, call e1000_phy_setup_autoneg routine to parse the
1793          * autoneg_advertised and fc options. If autoneg is NOT enabled, then
1794          * the user should have provided a speed/duplex override.  If so, then
1795          * call e1000_phy_force_speed_duplex to parse and set this up.
1796          */
1797         /* Perform some bounds checking on the hw->autoneg_advertised
1798          * parameter.  If this variable is zero, then set it to the default.
1799          */
1800         hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1801         
1802         /* If autoneg_advertised is zero, we assume it was not defaulted
1803          * by the calling code so we set to advertise full capability.
1804          */
1805         if(hw->autoneg_advertised == 0)
1806                 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1807         
1808         DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1809         if((ret_val = e1000_phy_setup_autoneg(hw))) {
1810                 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1811                 return ret_val;
1812         }
1813         DEBUGOUT("Restarting Auto-Neg\n");
1814         
1815         /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1816          * the Auto Neg Restart bit in the PHY control register.
1817          */
1818         if((ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data)))
1819                 return ret_val;
1820
1821         phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1822         if((ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data)))
1823                 return ret_val;
1824
1825 #if 0   
1826         /* Does the user want to wait for Auto-Neg to complete here, or
1827          * check at a later time (for example, callback routine).
1828          */
1829         if(hw->wait_autoneg_complete) {
1830                 if((ret_val = e1000_wait_autoneg(hw))) {
1831                         DEBUGOUT("Error while waiting for autoneg to complete\n");
1832                         return ret_val;
1833                 }
1834         }
1835 #else
1836         /* If we do not wait for autonegotiation to complete I 
1837          * do not see a valid link status.
1838          */
1839         if((ret_val = e1000_wait_autoneg(hw))) {
1840                 DEBUGOUT("Error while waiting for autoneg to complete\n");
1841                 return ret_val;
1842         }
1843 #endif
1844         } /* !hw->phy_reset_disable */
1845         
1846         /* Check link status. Wait up to 100 microseconds for link to become
1847          * valid.
1848          */
1849         for(i = 0; i < 10; i++) {
1850                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
1851                         return ret_val;
1852                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
1853                         return ret_val;
1854
1855                 if(phy_data & MII_SR_LINK_STATUS) {
1856                         /* We have link, so we need to finish the config process:
1857                          *   1) Set up the MAC to the current PHY speed/duplex
1858                          *      if we are on 82543.  If we
1859                          *      are on newer silicon, we only need to configure
1860                          *      collision distance in the Transmit Control Register.
1861                          *   2) Set up flow control on the MAC to that established with
1862                          *      the link partner.
1863                          */
1864                         if(hw->mac_type >= e1000_82544) {
1865                                 e1000_config_collision_dist(hw);
1866                         } else {
1867                                 if((ret_val = e1000_config_mac_to_phy(hw))) {
1868                                         DEBUGOUT("Error configuring MAC to PHY settings\n");
1869                                         return ret_val;
1870                                 }
1871                         }
1872                         if((ret_val = e1000_config_fc_after_link_up(hw))) {
1873                                 DEBUGOUT("Error Configuring Flow Control\n");
1874                                 return ret_val;
1875                         }
1876 #if 0
1877                         if(hw->phy_type == e1000_phy_igp) {
1878                                 if((ret_val = e1000_config_dsp_after_link_change(hw, TRUE))) {
1879                                         DEBUGOUT("Error Configuring DSP after link up\n");
1880                                         return ret_val;
1881                                 }
1882                         }
1883 #endif
1884                         DEBUGOUT("Valid link established!!!\n");
1885                         return E1000_SUCCESS;
1886                 }
1887                 udelay(10);
1888         }
1889         
1890         DEBUGOUT("Unable to establish link!!!\n");
1891         return -E1000_ERR_NOLINK;
1892 }
1893
1894 /******************************************************************************
1895 * Configures PHY autoneg and flow control advertisement settings
1896 *
1897 * hw - Struct containing variables accessed by shared code
1898 ******************************************************************************/
1899 static int
1900 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1901 {
1902         int32_t ret_val;
1903         uint16_t mii_autoneg_adv_reg;
1904         uint16_t mii_1000t_ctrl_reg;
1905
1906         DEBUGFUNC("e1000_phy_setup_autoneg");
1907         
1908         /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1909         if((ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
1910                                          &mii_autoneg_adv_reg)))
1911                 return ret_val;
1912
1913         /* Read the MII 1000Base-T Control Register (Address 9). */
1914         if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg)))
1915                 return ret_val;
1916
1917         /* Need to parse both autoneg_advertised and fc and set up
1918          * the appropriate PHY registers.  First we will parse for
1919          * autoneg_advertised software override.  Since we can advertise
1920          * a plethora of combinations, we need to check each bit
1921          * individually.
1922          */
1923         
1924         /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1925          * Advertisement Register (Address 4) and the 1000 mb speed bits in
1926          * the  1000Base-T Control Register (Address 9).
1927          */
1928         mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
1929         mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1930
1931         DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
1932
1933         /* Do we want to advertise 10 Mb Half Duplex? */
1934         if(hw->autoneg_advertised & ADVERTISE_10_HALF) {
1935                 DEBUGOUT("Advertise 10mb Half duplex\n");
1936                 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1937         }
1938
1939         /* Do we want to advertise 10 Mb Full Duplex? */
1940         if(hw->autoneg_advertised & ADVERTISE_10_FULL) {
1941                 DEBUGOUT("Advertise 10mb Full duplex\n");
1942                 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1943         }
1944
1945         /* Do we want to advertise 100 Mb Half Duplex? */
1946         if(hw->autoneg_advertised & ADVERTISE_100_HALF) {
1947                 DEBUGOUT("Advertise 100mb Half duplex\n");
1948                 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1949         }
1950
1951         /* Do we want to advertise 100 Mb Full Duplex? */
1952         if(hw->autoneg_advertised & ADVERTISE_100_FULL) {
1953                 DEBUGOUT("Advertise 100mb Full duplex\n");
1954                 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1955         }
1956
1957         /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1958         if(hw->autoneg_advertised & ADVERTISE_1000_HALF) {
1959                 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
1960         }
1961
1962         /* Do we want to advertise 1000 Mb Full Duplex? */
1963         if(hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1964                 DEBUGOUT("Advertise 1000mb Full duplex\n");
1965                 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1966         }
1967
1968         /* Check for a software override of the flow control settings, and
1969          * setup the PHY advertisement registers accordingly.  If
1970          * auto-negotiation is enabled, then software will have to set the
1971          * "PAUSE" bits to the correct value in the Auto-Negotiation
1972          * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
1973          *
1974          * The possible values of the "fc" parameter are:
1975          *      0:  Flow control is completely disabled
1976          *      1:  Rx flow control is enabled (we can receive pause frames
1977          *          but not send pause frames).
1978          *      2:  Tx flow control is enabled (we can send pause frames
1979          *          but we do not support receiving pause frames).
1980          *      3:  Both Rx and TX flow control (symmetric) are enabled.
1981          *  other:  No software override.  The flow control configuration
1982          *          in the EEPROM is used.
1983          */
1984         switch (hw->fc) {
1985         case e1000_fc_none: /* 0 */
1986                 /* Flow control (RX & TX) is completely disabled by a
1987                  * software over-ride.
1988                  */
1989                 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1990                 break;
1991         case e1000_fc_rx_pause: /* 1 */
1992                 /* RX Flow control is enabled, and TX Flow control is
1993                  * disabled, by a software over-ride.
1994                  */
1995                 /* Since there really isn't a way to advertise that we are
1996                  * capable of RX Pause ONLY, we will advertise that we
1997                  * support both symmetric and asymmetric RX PAUSE.  Later
1998                  * (in e1000_config_fc_after_link_up) we will disable the
1999                  *hw's ability to send PAUSE frames.
2000                  */
2001                 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2002                 break;
2003         case e1000_fc_tx_pause: /* 2 */
2004                 /* TX Flow control is enabled, and RX Flow control is
2005                  * disabled, by a software over-ride.
2006                  */
2007                 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
2008                 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
2009                 break;
2010         case e1000_fc_full: /* 3 */
2011                 /* Flow control (both RX and TX) is enabled by a software
2012                  * over-ride.
2013                  */
2014                 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2015                 break;
2016         default:
2017                 DEBUGOUT("Flow control param set incorrectly\n");
2018                 return -E1000_ERR_CONFIG;
2019         }
2020
2021         if((ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV,
2022                                mii_autoneg_adv_reg)))
2023                 return ret_val;
2024
2025         DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
2026
2027         if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg)))
2028                 return ret_val;
2029
2030         return E1000_SUCCESS;
2031 }
2032
2033 /******************************************************************************
2034 * Sets the collision distance in the Transmit Control register
2035 *
2036 * hw - Struct containing variables accessed by shared code
2037 *
2038 * Link should have been established previously. Reads the speed and duplex
2039 * information from the Device Status register.
2040 ******************************************************************************/
2041 static void
2042 e1000_config_collision_dist(struct e1000_hw *hw)
2043 {
2044         uint32_t tctl;
2045
2046         tctl = E1000_READ_REG(hw, TCTL);
2047         
2048         tctl &= ~E1000_TCTL_COLD;
2049         tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
2050         
2051         E1000_WRITE_REG(hw, TCTL, tctl);
2052         E1000_WRITE_FLUSH(hw);
2053 }
2054
2055 /******************************************************************************
2056 * Sets MAC speed and duplex settings to reflect the those in the PHY
2057 *
2058 * hw - Struct containing variables accessed by shared code
2059 * mii_reg - data to write to the MII control register
2060 *
2061 * The contents of the PHY register containing the needed information need to
2062 * be passed in.
2063 ******************************************************************************/
2064 static int
2065 e1000_config_mac_to_phy(struct e1000_hw *hw)
2066 {
2067         uint32_t ctrl;
2068         int32_t ret_val;
2069         uint16_t phy_data;
2070
2071         DEBUGFUNC("e1000_config_mac_to_phy");
2072
2073         /* Read the Device Control Register and set the bits to Force Speed
2074          * and Duplex.
2075          */
2076         ctrl = E1000_READ_REG(hw, CTRL);
2077         ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2078         ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
2079
2080         /* Set up duplex in the Device Control and Transmit Control
2081          * registers depending on negotiated values.
2082          */
2083         if (hw->phy_type == e1000_phy_igp) {
2084                 if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
2085                                                  &phy_data)))
2086                         return ret_val;
2087
2088                 if(phy_data & IGP01E1000_PSSR_FULL_DUPLEX) ctrl |= E1000_CTRL_FD;
2089                 else ctrl &= ~E1000_CTRL_FD;
2090
2091                 e1000_config_collision_dist(hw);
2092
2093                 /* Set up speed in the Device Control register depending on
2094                  * negotiated values.
2095                  */
2096                 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
2097                    IGP01E1000_PSSR_SPEED_1000MBPS)
2098                         ctrl |= E1000_CTRL_SPD_1000;
2099                 else if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
2100                         IGP01E1000_PSSR_SPEED_100MBPS)
2101                         ctrl |= E1000_CTRL_SPD_100;
2102         } else {
2103                 if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
2104                                                  &phy_data)))
2105                         return ret_val;
2106                 
2107                 if(phy_data & M88E1000_PSSR_DPLX) ctrl |= E1000_CTRL_FD;
2108                 else ctrl &= ~E1000_CTRL_FD;
2109
2110                 e1000_config_collision_dist(hw);
2111
2112                 /* Set up speed in the Device Control register depending on
2113                  * negotiated values.
2114                  */
2115                 if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
2116                         ctrl |= E1000_CTRL_SPD_1000;
2117                 else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
2118                         ctrl |= E1000_CTRL_SPD_100;
2119         }
2120         /* Write the configured values back to the Device Control Reg. */
2121         E1000_WRITE_REG(hw, CTRL, ctrl);
2122         return E1000_SUCCESS;
2123 }
2124
2125 /******************************************************************************
2126  * Forces the MAC's flow control settings.
2127  * 
2128  * hw - Struct containing variables accessed by shared code
2129  *
2130  * Sets the TFCE and RFCE bits in the device control register to reflect
2131  * the adapter settings. TFCE and RFCE need to be explicitly set by
2132  * software when a Copper PHY is used because autonegotiation is managed
2133  * by the PHY rather than the MAC. Software must also configure these
2134  * bits when link is forced on a fiber connection.
2135  *****************************************************************************/
2136 static int
2137 e1000_force_mac_fc(struct e1000_hw *hw)
2138 {
2139         uint32_t ctrl;
2140         
2141         DEBUGFUNC("e1000_force_mac_fc");
2142         
2143         /* Get the current configuration of the Device Control Register */
2144         ctrl = E1000_READ_REG(hw, CTRL);
2145         
2146         /* Because we didn't get link via the internal auto-negotiation
2147          * mechanism (we either forced link or we got link via PHY
2148          * auto-neg), we have to manually enable/disable transmit an
2149          * receive flow control.
2150          *
2151          * The "Case" statement below enables/disable flow control
2152          * according to the "hw->fc" parameter.
2153          *
2154          * The possible values of the "fc" parameter are:
2155          *      0:  Flow control is completely disabled
2156          *      1:  Rx flow control is enabled (we can receive pause
2157          *          frames but not send pause frames).
2158          *      2:  Tx flow control is enabled (we can send pause frames
2159          *          frames but we do not receive pause frames).
2160          *      3:  Both Rx and TX flow control (symmetric) is enabled.
2161          *  other:  No other values should be possible at this point.
2162          */
2163         
2164         switch (hw->fc) {
2165         case e1000_fc_none:
2166                 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
2167                 break;
2168         case e1000_fc_rx_pause:
2169                 ctrl &= (~E1000_CTRL_TFCE);
2170                 ctrl |= E1000_CTRL_RFCE;
2171                 break;
2172         case e1000_fc_tx_pause:
2173                 ctrl &= (~E1000_CTRL_RFCE);
2174                 ctrl |= E1000_CTRL_TFCE;
2175                 break;
2176         case e1000_fc_full:
2177                 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
2178                 break;
2179         default:
2180                 DEBUGOUT("Flow control param set incorrectly\n");
2181                 return -E1000_ERR_CONFIG;
2182         }
2183         
2184         /* Disable TX Flow Control for 82542 (rev 2.0) */
2185         if(hw->mac_type == e1000_82542_rev2_0)
2186                 ctrl &= (~E1000_CTRL_TFCE);
2187         
2188         E1000_WRITE_REG(hw, CTRL, ctrl);
2189         return E1000_SUCCESS;
2190 }
2191
2192 /******************************************************************************
2193  * Configures flow control settings after link is established
2194  * 
2195  * hw - Struct containing variables accessed by shared code
2196  *
2197  * Should be called immediately after a valid link has been established.
2198  * Forces MAC flow control settings if link was forced. When in MII/GMII mode
2199  * and autonegotiation is enabled, the MAC flow control settings will be set
2200  * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
2201  * and RFCE bits will be automaticaly set to the negotiated flow control mode.
2202  *****************************************************************************/
2203 static int
2204 e1000_config_fc_after_link_up(struct e1000_hw *hw)
2205 {
2206         int32_t ret_val;
2207         uint16_t mii_status_reg;
2208         uint16_t mii_nway_adv_reg;
2209         uint16_t mii_nway_lp_ability_reg;
2210         uint16_t speed;
2211         uint16_t duplex;
2212         
2213         DEBUGFUNC("e1000_config_fc_after_link_up");
2214         
2215         /* Check for the case where we have fiber media and auto-neg failed
2216          * so we had to force link.  In this case, we need to force the
2217          * configuration of the MAC to match the "fc" parameter.
2218          */
2219         if(((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
2220            ((hw->media_type == e1000_media_type_internal_serdes) && (hw->autoneg_failed))) { 
2221                 if((ret_val = e1000_force_mac_fc(hw))) {
2222                         DEBUGOUT("Error forcing flow control settings\n");
2223                         return ret_val;
2224                 }
2225         }
2226         
2227         /* Check for the case where we have copper media and auto-neg is
2228          * enabled.  In this case, we need to check and see if Auto-Neg
2229          * has completed, and if so, how the PHY and link partner has
2230          * flow control configured.
2231          */
2232         if(hw->media_type == e1000_media_type_copper) {
2233                 /* Read the MII Status Register and check to see if AutoNeg
2234                  * has completed.  We read this twice because this reg has
2235                  * some "sticky" (latched) bits.
2236                  */
2237                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
2238                         return ret_val;
2239                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
2240                         return ret_val;
2241                 
2242                 if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
2243                         /* The AutoNeg process has completed, so we now need to
2244                          * read both the Auto Negotiation Advertisement Register
2245                          * (Address 4) and the Auto_Negotiation Base Page Ability
2246                          * Register (Address 5) to determine how flow control was
2247                          * negotiated.
2248                          */
2249                         if((ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
2250                                                          &mii_nway_adv_reg)))
2251                                 return ret_val;
2252                         if((ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2253                                                          &mii_nway_lp_ability_reg)))
2254                                 return ret_val;
2255
2256                         /* Two bits in the Auto Negotiation Advertisement Register
2257                          * (Address 4) and two bits in the Auto Negotiation Base
2258                          * Page Ability Register (Address 5) determine flow control
2259                          * for both the PHY and the link partner.  The following
2260                          * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
2261                          * 1999, describes these PAUSE resolution bits and how flow
2262                          * control is determined based upon these settings.
2263                          * NOTE:  DC = Don't Care
2264                          *
2265                          *   LOCAL DEVICE  |   LINK PARTNER
2266                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
2267                          *-------|---------|-------|---------|--------------------
2268                          *   0   |    0    |  DC   |   DC    | e1000_fc_none
2269                          *   0   |    1    |   0   |   DC    | e1000_fc_none
2270                          *   0   |    1    |   1   |    0    | e1000_fc_none
2271                          *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
2272                          *   1   |    0    |   0   |   DC    | e1000_fc_none
2273                          *   1   |   DC    |   1   |   DC    | e1000_fc_full
2274                          *   1   |    1    |   0   |    0    | e1000_fc_none
2275                          *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
2276                          *
2277                          */
2278                         /* Are both PAUSE bits set to 1?  If so, this implies
2279                          * Symmetric Flow Control is enabled at both ends.  The
2280                          * ASM_DIR bits are irrelevant per the spec.
2281                          *
2282                          * For Symmetric Flow Control:
2283                          *
2284                          *   LOCAL DEVICE  |   LINK PARTNER
2285                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2286                          *-------|---------|-------|---------|--------------------
2287                          *   1   |   DC    |   1   |   DC    | e1000_fc_full
2288                          *
2289                          */
2290                         if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2291                                 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
2292                                 /* Now we need to check if the user selected RX ONLY
2293                                  * of pause frames.  In this case, we had to advertise
2294                                  * FULL flow control because we could not advertise RX
2295                                  * ONLY. Hence, we must now check to see if we need to
2296                                  * turn OFF  the TRANSMISSION of PAUSE frames.
2297                                  */
2298 #if 0
2299                                 if(hw->original_fc == e1000_fc_full) {
2300                                         hw->fc = e1000_fc_full;
2301 #else
2302                                 if(hw->fc == e1000_fc_full) {
2303 #endif
2304                                         DEBUGOUT("Flow Control = FULL.\r\n");
2305                                 } else {
2306                                         hw->fc = e1000_fc_rx_pause;
2307                                         DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
2308                                 }
2309                         }
2310                         /* For receiving PAUSE frames ONLY.
2311                          *
2312                          *   LOCAL DEVICE  |   LINK PARTNER
2313                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2314                          *-------|---------|-------|---------|--------------------
2315                          *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
2316                          *
2317                          */
2318                         else if(!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2319                                 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2320                                 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2321                                 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2322                                 hw->fc = e1000_fc_tx_pause;
2323                                 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n");
2324                         }
2325                         /* For transmitting PAUSE frames ONLY.
2326                          *
2327                          *   LOCAL DEVICE  |   LINK PARTNER
2328                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2329                          *-------|---------|-------|---------|--------------------
2330                          *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
2331                          *
2332                          */
2333                         else if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2334                                 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2335                                 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2336                                 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2337                                 hw->fc = e1000_fc_rx_pause;
2338                                 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
2339                         }
2340                         /* Per the IEEE spec, at this point flow control should be
2341                          * disabled.  However, we want to consider that we could
2342                          * be connected to a legacy switch that doesn't advertise
2343                          * desired flow control, but can be forced on the link
2344                          * partner.  So if we advertised no flow control, that is
2345                          * what we will resolve to.  If we advertised some kind of
2346                          * receive capability (Rx Pause Only or Full Flow Control)
2347                          * and the link partner advertised none, we will configure
2348                          * ourselves to enable Rx Flow Control only.  We can do
2349                          * this safely for two reasons:  If the link partner really
2350                          * didn't want flow control enabled, and we enable Rx, no
2351                          * harm done since we won't be receiving any PAUSE frames
2352                          * anyway.  If the intent on the link partner was to have
2353                          * flow control enabled, then by us enabling RX only, we
2354                          * can at least receive pause frames and process them.
2355                          * This is a good idea because in most cases, since we are
2356                          * predominantly a server NIC, more times than not we will
2357                          * be asked to delay transmission of packets than asking
2358                          * our link partner to pause transmission of frames.
2359                          */
2360 #if 0
2361                         else if(hw->original_fc == e1000_fc_none ||
2362                                 hw->original_fc == e1000_fc_tx_pause) {
2363 #else
2364                         else if(hw->fc == e1000_fc_none)
2365                                 DEBUGOUT("Flow Control = NONE.\r\n");
2366                         else if(hw->fc == e1000_fc_tx_pause) {
2367 #endif
2368                                 hw->fc = e1000_fc_none;
2369                                 DEBUGOUT("Flow Control = NONE.\r\n");
2370                         } else {
2371                                 hw->fc = e1000_fc_rx_pause;
2372                                 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
2373                         }
2374                         
2375                         /* Now we need to do one last check...  If we auto-
2376                          * negotiated to HALF DUPLEX, flow control should not be
2377                          * enabled per IEEE 802.3 spec.
2378                          */
2379                         e1000_get_speed_and_duplex(hw, &speed, &duplex);
2380                         
2381                         if(duplex == HALF_DUPLEX)
2382                                 hw->fc = e1000_fc_none;
2383                         
2384                         /* Now we call a subroutine to actually force the MAC
2385                          * controller to use the correct flow control settings.
2386                          */
2387                         if((ret_val = e1000_force_mac_fc(hw))) {
2388                                 DEBUGOUT("Error forcing flow control settings\n");
2389                                 return ret_val;
2390                         }
2391                 } else {
2392                         DEBUGOUT("Copper PHY and Auto Neg has not completed.\r\n");
2393                 }
2394         }
2395         return E1000_SUCCESS;
2396 }
2397
2398 /******************************************************************************
2399  * Checks to see if the link status of the hardware has changed.
2400  *
2401  * hw - Struct containing variables accessed by shared code
2402  *
2403  * Called by any function that needs to check the link status of the adapter.
2404  *****************************************************************************/
2405 static int
2406 e1000_check_for_link(struct e1000_hw *hw)
2407 {
2408         uint32_t rxcw;
2409         uint32_t ctrl;
2410         uint32_t status;
2411         uint32_t rctl;
2412         uint32_t signal = 0;
2413         int32_t ret_val;
2414         uint16_t phy_data;
2415         uint16_t lp_capability;
2416         
2417         DEBUGFUNC("e1000_check_for_link");
2418         
2419         /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be 
2420          * set when the optics detect a signal. On older adapters, it will be 
2421          * cleared when there is a signal.  This applies to fiber media only.
2422          */
2423         if(hw->media_type == e1000_media_type_fiber)
2424                 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
2425
2426         ctrl = E1000_READ_REG(hw, CTRL);
2427         status = E1000_READ_REG(hw, STATUS);
2428         rxcw = E1000_READ_REG(hw, RXCW);
2429         
2430         /* If we have a copper PHY then we only want to go out to the PHY
2431          * registers to see if Auto-Neg has completed and/or if our link
2432          * status has changed.  The get_link_status flag will be set if we
2433          * receive a Link Status Change interrupt or we have Rx Sequence
2434          * Errors.
2435          */
2436 #if 0
2437         if((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
2438 #else
2439         if(hw->media_type == e1000_media_type_copper) {
2440 #endif
2441                 /* First we want to see if the MII Status Register reports
2442                  * link.  If so, then we want to get the current speed/duplex
2443                  * of the PHY.
2444                  * Read the register twice since the link bit is sticky.
2445                  */
2446                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2447                         return ret_val;
2448                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2449                         return ret_val;
2450                 
2451                 if(phy_data & MII_SR_LINK_STATUS) {
2452 #if 0
2453                         hw->get_link_status = FALSE;
2454 #endif
2455                 } else {
2456                         /* No link detected */
2457                         return -E1000_ERR_NOLINK;
2458                 }
2459
2460                 /* We have a M88E1000 PHY and Auto-Neg is enabled.  If we
2461                  * have Si on board that is 82544 or newer, Auto
2462                  * Speed Detection takes care of MAC speed/duplex
2463                  * configuration.  So we only need to configure Collision
2464                  * Distance in the MAC.  Otherwise, we need to force
2465                  * speed/duplex on the MAC to the current PHY speed/duplex
2466                  * settings.
2467                  */
2468                 if(hw->mac_type >= e1000_82544)
2469                         e1000_config_collision_dist(hw);
2470                 else {
2471                         if((ret_val = e1000_config_mac_to_phy(hw))) {
2472                                 DEBUGOUT("Error configuring MAC to PHY settings\n");
2473                                 return ret_val;
2474                         }
2475                 }
2476                 
2477                 /* Configure Flow Control now that Auto-Neg has completed. First, we 
2478                  * need to restore the desired flow control settings because we may
2479                  * have had to re-autoneg with a different link partner.
2480                  */
2481                 if((ret_val = e1000_config_fc_after_link_up(hw))) {
2482                         DEBUGOUT("Error configuring flow control\n");
2483                         return ret_val;
2484                 }
2485                 
2486                 /* At this point we know that we are on copper and we have
2487                  * auto-negotiated link.  These are conditions for checking the link
2488                  * parter capability register.  We use the link partner capability to
2489                  * determine if TBI Compatibility needs to be turned on or off.  If
2490                  * the link partner advertises any speed in addition to Gigabit, then
2491                  * we assume that they are GMII-based, and TBI compatibility is not
2492                  * needed. If no other speeds are advertised, we assume the link
2493                  * partner is TBI-based, and we turn on TBI Compatibility.
2494                  */
2495                 if(hw->tbi_compatibility_en) {
2496                         if((ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2497                                                          &lp_capability)))
2498                                 return ret_val;
2499                         if(lp_capability & (NWAY_LPAR_10T_HD_CAPS |
2500                                 NWAY_LPAR_10T_FD_CAPS |
2501                                 NWAY_LPAR_100TX_HD_CAPS |
2502                                 NWAY_LPAR_100TX_FD_CAPS |
2503                                 NWAY_LPAR_100T4_CAPS)) {
2504                                 /* If our link partner advertises anything in addition to 
2505                                  * gigabit, we do not need to enable TBI compatibility.
2506                                  */
2507                                 if(hw->tbi_compatibility_on) {
2508                                         /* If we previously were in the mode, turn it off. */
2509                                         rctl = E1000_READ_REG(hw, RCTL);
2510                                         rctl &= ~E1000_RCTL_SBP;
2511                                         E1000_WRITE_REG(hw, RCTL, rctl);
2512                                         hw->tbi_compatibility_on = FALSE;
2513                                 }
2514                         } else {
2515                                 /* If TBI compatibility is was previously off, turn it on. For
2516                                  * compatibility with a TBI link partner, we will store bad
2517                                  * packets. Some frames have an additional byte on the end and
2518                                  * will look like CRC errors to to the hardware.
2519                                  */
2520                                 if(!hw->tbi_compatibility_on) {
2521                                         hw->tbi_compatibility_on = TRUE;
2522                                         rctl = E1000_READ_REG(hw, RCTL);
2523                                         rctl |= E1000_RCTL_SBP;
2524                                         E1000_WRITE_REG(hw, RCTL, rctl);
2525                                 }
2526                         }
2527                 }
2528         }
2529         /* If we don't have link (auto-negotiation failed or link partner cannot
2530          * auto-negotiate), the cable is plugged in (we have signal), and our
2531          * link partner is not trying to auto-negotiate with us (we are receiving
2532          * idles or data), we need to force link up. We also need to give
2533          * auto-negotiation time to complete, in case the cable was just plugged
2534          * in. The autoneg_failed flag does this.
2535          */
2536         else if((((hw->media_type == e1000_media_type_fiber) &&
2537                 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
2538                 (hw->media_type == e1000_media_type_internal_serdes)) &&
2539                 (!(status & E1000_STATUS_LU)) &&
2540                 (!(rxcw & E1000_RXCW_C))) {
2541                 if(hw->autoneg_failed == 0) {
2542                         hw->autoneg_failed = 1;
2543                         return 0;
2544                 }
2545                 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
2546                 
2547                 /* Disable auto-negotiation in the TXCW register */
2548                 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
2549                 
2550                 /* Force link-up and also force full-duplex. */
2551                 ctrl = E1000_READ_REG(hw, CTRL);
2552                 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
2553                 E1000_WRITE_REG(hw, CTRL, ctrl);
2554                 
2555                 /* Configure Flow Control after forcing link up. */
2556                 if((ret_val = e1000_config_fc_after_link_up(hw))) {
2557                         DEBUGOUT("Error configuring flow control\n");
2558                         return ret_val;
2559                 }
2560         }
2561         /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
2562          * auto-negotiation in the TXCW register and disable forced link in the
2563          * Device Control register in an attempt to auto-negotiate with our link
2564          * partner.
2565          */
2566         else if(((hw->media_type == e1000_media_type_fiber)  ||
2567                  (hw->media_type == e1000_media_type_internal_serdes)) &&
2568                 (ctrl & E1000_CTRL_SLU) &&
2569                 (rxcw & E1000_RXCW_C)) {
2570                 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
2571                 E1000_WRITE_REG(hw, TXCW, hw->txcw);
2572                 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
2573         }
2574 #if 0
2575         /* If we force link for non-auto-negotiation switch, check link status
2576          * based on MAC synchronization for internal serdes media type.
2577          */
2578         else if((hw->media_type == e1000_media_type_internal_serdes) &&
2579                         !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
2580                 /* SYNCH bit and IV bit are sticky. */
2581                 udelay(10);
2582                 if(E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
2583                         if(!(rxcw & E1000_RXCW_IV)) {
2584                                 hw->serdes_link_down = FALSE;
2585                                 DEBUGOUT("SERDES: Link is up.\n");
2586                         }
2587                 } else {
2588                         hw->serdes_link_down = TRUE;
2589                         DEBUGOUT("SERDES: Link is down.\n");
2590                 }
2591         }
2592 #endif
2593         return E1000_SUCCESS;
2594 }
2595
2596 /******************************************************************************
2597  * Detects the current speed and duplex settings of the hardware.
2598  *
2599  * hw - Struct containing variables accessed by shared code
2600  * speed - Speed of the connection
2601  * duplex - Duplex setting of the connection
2602  *****************************************************************************/
2603 static void 
2604 e1000_get_speed_and_duplex(struct e1000_hw *hw,
2605                            uint16_t *speed,
2606                            uint16_t *duplex)
2607 {
2608         uint32_t status;
2609         
2610         DEBUGFUNC("e1000_get_speed_and_duplex");
2611         
2612         if(hw->mac_type >= e1000_82543) {
2613                 status = E1000_READ_REG(hw, STATUS);
2614                 if(status & E1000_STATUS_SPEED_1000) {
2615                         *speed = SPEED_1000;
2616                         DEBUGOUT("1000 Mbs, ");
2617                 } else if(status & E1000_STATUS_SPEED_100) {
2618                         *speed = SPEED_100;
2619                         DEBUGOUT("100 Mbs, ");
2620                 } else {
2621                         *speed = SPEED_10;
2622                         DEBUGOUT("10 Mbs, ");
2623                 }
2624                 
2625                 if(status & E1000_STATUS_FD) {
2626                         *duplex = FULL_DUPLEX;
2627                         DEBUGOUT("Full Duplex\r\n");
2628                 } else {
2629                         *duplex = HALF_DUPLEX;
2630                         DEBUGOUT(" Half Duplex\r\n");
2631                 }
2632         } else {
2633                 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
2634                 *speed = SPEED_1000;
2635                 *duplex = FULL_DUPLEX;
2636         }
2637 }
2638
2639 /******************************************************************************
2640 * Blocks until autoneg completes or times out (~4.5 seconds)
2641 *
2642 * hw - Struct containing variables accessed by shared code
2643 ******************************************************************************/
2644 static int
2645 e1000_wait_autoneg(struct e1000_hw *hw)
2646 {
2647         int32_t ret_val;
2648         uint16_t i;
2649         uint16_t phy_data;
2650         
2651         DEBUGFUNC("e1000_wait_autoneg");
2652         DEBUGOUT("Waiting for Auto-Neg to complete.\n");
2653         
2654         /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2655         for(i = PHY_AUTO_NEG_TIME; i > 0; i--) {
2656                 /* Read the MII Status Register and wait for Auto-Neg
2657                  * Complete bit to be set.
2658                  */
2659                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2660                         return ret_val;
2661                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2662                         return ret_val;
2663                 if(phy_data & MII_SR_AUTONEG_COMPLETE) {
2664                         DEBUGOUT("Auto-Neg complete.\n");
2665                         return E1000_SUCCESS;
2666                 }
2667                 mdelay(100);
2668         }
2669         DEBUGOUT("Auto-Neg timedout.\n");
2670         return -E1000_ERR_TIMEOUT;
2671 }
2672
2673 /******************************************************************************
2674 * Raises the Management Data Clock
2675 *
2676 * hw - Struct containing variables accessed by shared code
2677 * ctrl - Device control register's current value
2678 ******************************************************************************/
2679 static void
2680 e1000_raise_mdi_clk(struct e1000_hw *hw,
2681                     uint32_t *ctrl)
2682 {
2683         /* Raise the clock input to the Management Data Clock (by setting the MDC
2684          * bit), and then delay 10 microseconds.
2685          */
2686         E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
2687         E1000_WRITE_FLUSH(hw);
2688         udelay(10);
2689 }
2690
2691 /******************************************************************************
2692 * Lowers the Management Data Clock
2693 *
2694 * hw - Struct containing variables accessed by shared code
2695 * ctrl - Device control register's current value
2696 ******************************************************************************/
2697 static void
2698 e1000_lower_mdi_clk(struct e1000_hw *hw,
2699                     uint32_t *ctrl)
2700 {
2701         /* Lower the clock input to the Management Data Clock (by clearing the MDC
2702          * bit), and then delay 10 microseconds.
2703          */
2704         E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
2705         E1000_WRITE_FLUSH(hw);
2706         udelay(10);
2707 }
2708
2709 /******************************************************************************
2710 * Shifts data bits out to the PHY
2711 *
2712 * hw - Struct containing variables accessed by shared code
2713 * data - Data to send out to the PHY
2714 * count - Number of bits to shift out
2715 *
2716 * Bits are shifted out in MSB to LSB order.
2717 ******************************************************************************/
2718 static void
2719 e1000_shift_out_mdi_bits(struct e1000_hw *hw,
2720                          uint32_t data,
2721                          uint16_t count)
2722 {
2723         uint32_t ctrl;
2724         uint32_t mask;
2725
2726         /* We need to shift "count" number of bits out to the PHY. So, the value
2727          * in the "data" parameter will be shifted out to the PHY one bit at a 
2728          * time. In order to do this, "data" must be broken down into bits.
2729          */
2730         mask = 0x01;
2731         mask <<= (count - 1);
2732         
2733         ctrl = E1000_READ_REG(hw, CTRL);
2734         
2735         /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
2736         ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
2737         
2738         while(mask) {
2739                 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
2740                  * then raising and lowering the Management Data Clock. A "0" is
2741                  * shifted out to the PHY by setting the MDIO bit to "0" and then
2742                  * raising and lowering the clock.
2743                  */
2744                 if(data & mask) ctrl |= E1000_CTRL_MDIO;
2745                 else ctrl &= ~E1000_CTRL_MDIO;
2746                 
2747                 E1000_WRITE_REG(hw, CTRL, ctrl);
2748                 E1000_WRITE_FLUSH(hw);
2749                 
2750                 udelay(10);
2751
2752                 e1000_raise_mdi_clk(hw, &ctrl);
2753                 e1000_lower_mdi_clk(hw, &ctrl);
2754
2755                 mask = mask >> 1;
2756         }
2757 }
2758
2759 /******************************************************************************
2760 * Shifts data bits in from the PHY
2761 *
2762 * hw - Struct containing variables accessed by shared code
2763 *
2764 * Bits are shifted in in MSB to LSB order. 
2765 ******************************************************************************/
2766 static uint16_t
2767 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
2768 {
2769         uint32_t ctrl;
2770         uint16_t data = 0;
2771         uint8_t i;
2772
2773         /* In order to read a register from the PHY, we need to shift in a total
2774          * of 18 bits from the PHY. The first two bit (turnaround) times are used
2775          * to avoid contention on the MDIO pin when a read operation is performed.
2776          * These two bits are ignored by us and thrown away. Bits are "shifted in"
2777          * by raising the input to the Management Data Clock (setting the MDC bit),
2778          * and then reading the value of the MDIO bit.
2779          */ 
2780         ctrl = E1000_READ_REG(hw, CTRL);
2781         
2782         /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
2783         ctrl &= ~E1000_CTRL_MDIO_DIR;
2784         ctrl &= ~E1000_CTRL_MDIO;
2785         
2786         E1000_WRITE_REG(hw, CTRL, ctrl);
2787         E1000_WRITE_FLUSH(hw);
2788         
2789         /* Raise and Lower the clock before reading in the data. This accounts for
2790          * the turnaround bits. The first clock occurred when we clocked out the
2791          * last bit of the Register Address.
2792          */
2793         e1000_raise_mdi_clk(hw, &ctrl);
2794         e1000_lower_mdi_clk(hw, &ctrl);
2795         
2796         for(data = 0, i = 0; i < 16; i++) {
2797                 data = data << 1;
2798                 e1000_raise_mdi_clk(hw, &ctrl);
2799                 ctrl = E1000_READ_REG(hw, CTRL);
2800                 /* Check to see if we shifted in a "1". */
2801                 if(ctrl & E1000_CTRL_MDIO) data |= 1;
2802                 e1000_lower_mdi_clk(hw, &ctrl);
2803         }
2804         
2805         e1000_raise_mdi_clk(hw, &ctrl);
2806         e1000_lower_mdi_clk(hw, &ctrl);
2807         
2808         return data;
2809 }
2810
2811 /*****************************************************************************
2812 * Reads the value from a PHY register, if the value is on a specific non zero
2813 * page, sets the page first.
2814 *
2815 * hw - Struct containing variables accessed by shared code
2816 * reg_addr - address of the PHY register to read
2817 ******************************************************************************/
2818 static int
2819 e1000_read_phy_reg(struct e1000_hw *hw,
2820                    uint32_t reg_addr,
2821                    uint16_t *phy_data)
2822 {
2823         uint32_t ret_val;
2824
2825         DEBUGFUNC("e1000_read_phy_reg");
2826
2827         if(hw->phy_type == e1000_phy_igp &&
2828            (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2829                 if((ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2830                                                      (uint16_t)reg_addr)))
2831                         return ret_val;
2832         }
2833
2834         ret_val = e1000_read_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr,
2835                                         phy_data);
2836
2837         return ret_val;
2838 }
2839
2840 static int
2841 e1000_read_phy_reg_ex(struct e1000_hw *hw,
2842                       uint32_t reg_addr,
2843                       uint16_t *phy_data)
2844 {
2845         uint32_t i;
2846         uint32_t mdic = 0;
2847         const uint32_t phy_addr = 1;
2848
2849         DEBUGFUNC("e1000_read_phy_reg_ex");
2850         
2851         if(reg_addr > MAX_PHY_REG_ADDRESS) {
2852                 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2853                 return -E1000_ERR_PARAM;
2854         }
2855         
2856         if(hw->mac_type > e1000_82543) {
2857                 /* Set up Op-code, Phy Address, and register address in the MDI
2858                  * Control register.  The MAC will take care of interfacing with the
2859                  * PHY to retrieve the desired data.
2860                  */
2861                 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
2862                         (phy_addr << E1000_MDIC_PHY_SHIFT) | 
2863                         (E1000_MDIC_OP_READ));
2864                 
2865                 E1000_WRITE_REG(hw, MDIC, mdic);
2866
2867                 /* Poll the ready bit to see if the MDI read completed */
2868                 for(i = 0; i < 64; i++) {
2869                         udelay(50);
2870                         mdic = E1000_READ_REG(hw, MDIC);
2871                         if(mdic & E1000_MDIC_READY) break;
2872                 }
2873                 if(!(mdic & E1000_MDIC_READY)) {
2874                         DEBUGOUT("MDI Read did not complete\n");
2875                         return -E1000_ERR_PHY;
2876                 }
2877                 if(mdic & E1000_MDIC_ERROR) {
2878                         DEBUGOUT("MDI Error\n");
2879                         return -E1000_ERR_PHY;
2880                 }
2881                 *phy_data = (uint16_t) mdic;
2882         } else {
2883                 /* We must first send a preamble through the MDIO pin to signal the
2884                  * beginning of an MII instruction.  This is done by sending 32
2885                  * consecutive "1" bits.
2886                  */
2887                 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2888                 
2889                 /* Now combine the next few fields that are required for a read
2890                  * operation.  We use this method instead of calling the
2891                  * e1000_shift_out_mdi_bits routine five different times. The format of
2892                  * a MII read instruction consists of a shift out of 14 bits and is
2893                  * defined as follows:
2894                  *    <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
2895                  * followed by a shift in of 18 bits.  This first two bits shifted in
2896                  * are TurnAround bits used to avoid contention on the MDIO pin when a
2897                  * READ operation is performed.  These two bits are thrown away
2898                  * followed by a shift in of 16 bits which contains the desired data.
2899                  */
2900                 mdic = ((reg_addr) | (phy_addr << 5) | 
2901                         (PHY_OP_READ << 10) | (PHY_SOF << 12));
2902                 
2903                 e1000_shift_out_mdi_bits(hw, mdic, 14);
2904                 
2905                 /* Now that we've shifted out the read command to the MII, we need to
2906                  * "shift in" the 16-bit value (18 total bits) of the requested PHY
2907                  * register address.
2908                  */
2909                 *phy_data = e1000_shift_in_mdi_bits(hw);
2910         }
2911         return E1000_SUCCESS;
2912 }
2913
2914 /******************************************************************************
2915 * Writes a value to a PHY register
2916 *
2917 * hw - Struct containing variables accessed by shared code
2918 * reg_addr - address of the PHY register to write
2919 * data - data to write to the PHY
2920 ******************************************************************************/
2921 static int 
2922 e1000_write_phy_reg(struct e1000_hw *hw,
2923                     uint32_t reg_addr,
2924                     uint16_t phy_data)
2925 {
2926         uint32_t ret_val;
2927
2928         DEBUGFUNC("e1000_write_phy_reg");
2929
2930         if(hw->phy_type == e1000_phy_igp &&
2931            (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2932                 if((ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2933                                                      (uint16_t)reg_addr)))
2934                         return ret_val;
2935         }
2936
2937         ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr,
2938                                          phy_data);
2939
2940         return ret_val;
2941 }
2942
2943 static int
2944 e1000_write_phy_reg_ex(struct e1000_hw *hw,
2945                        uint32_t reg_addr,
2946                        uint16_t phy_data)
2947 {
2948         uint32_t i;
2949         uint32_t mdic = 0;
2950         const uint32_t phy_addr = 1;
2951         
2952         DEBUGFUNC("e1000_write_phy_reg_ex");
2953         
2954         if(reg_addr > MAX_PHY_REG_ADDRESS) {
2955                 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2956                 return -E1000_ERR_PARAM;
2957         }
2958         
2959         if(hw->mac_type > e1000_82543) {
2960                 /* Set up Op-code, Phy Address, register address, and data intended
2961                  * for the PHY register in the MDI Control register.  The MAC will take
2962                  * care of interfacing with the PHY to send the desired data.
2963                  */
2964                 mdic = (((uint32_t) phy_data) |
2965                         (reg_addr << E1000_MDIC_REG_SHIFT) |
2966                         (phy_addr << E1000_MDIC_PHY_SHIFT) | 
2967                         (E1000_MDIC_OP_WRITE));
2968                 
2969                 E1000_WRITE_REG(hw, MDIC, mdic);
2970                 
2971                 /* Poll the ready bit to see if the MDI read completed */
2972                 for(i = 0; i < 640; i++) {
2973                         udelay(5);
2974                         mdic = E1000_READ_REG(hw, MDIC);
2975                         if(mdic & E1000_MDIC_READY) break;
2976                 }
2977                 if(!(mdic & E1000_MDIC_READY)) {
2978                         DEBUGOUT("MDI Write did not complete\n");
2979                         return -E1000_ERR_PHY;
2980                 }
2981         } else {
2982                 /* We'll need to use the SW defined pins to shift the write command
2983                  * out to the PHY. We first send a preamble to the PHY to signal the
2984                  * beginning of the MII instruction.  This is done by sending 32 
2985                  * consecutive "1" bits.
2986                  */
2987                 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2988                 
2989                 /* Now combine the remaining required fields that will indicate a 
2990                  * write operation. We use this method instead of calling the
2991                  * e1000_shift_out_mdi_bits routine for each field in the command. The
2992                  * format of a MII write instruction is as follows:
2993                  * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
2994                  */
2995                 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
2996                         (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
2997                 mdic <<= 16;
2998                 mdic |= (uint32_t) phy_data;
2999                 
3000                 e1000_shift_out_mdi_bits(hw, mdic, 32);
3001         }
3002
3003         return E1000_SUCCESS;
3004 }
3005
3006 /******************************************************************************
3007 * Returns the PHY to the power-on reset state
3008 *
3009 * hw - Struct containing variables accessed by shared code
3010 ******************************************************************************/
3011 static void
3012 e1000_phy_hw_reset(struct e1000_hw *hw)
3013 {
3014         uint32_t ctrl, ctrl_ext;
3015
3016         DEBUGFUNC("e1000_phy_hw_reset");
3017         
3018         DEBUGOUT("Resetting Phy...\n");
3019         
3020         if(hw->mac_type > e1000_82543) {
3021                 /* Read the device control register and assert the E1000_CTRL_PHY_RST
3022                  * bit. Then, take it out of reset.
3023                  */
3024                 ctrl = E1000_READ_REG(hw, CTRL);
3025                 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
3026                 E1000_WRITE_FLUSH(hw);
3027                 mdelay(10);
3028                 E1000_WRITE_REG(hw, CTRL, ctrl);
3029                 E1000_WRITE_FLUSH(hw);
3030         } else {
3031                 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
3032                  * bit to put the PHY into reset. Then, take it out of reset.
3033                  */
3034                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
3035                 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
3036                 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
3037                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3038                 E1000_WRITE_FLUSH(hw);
3039                 mdelay(10);
3040                 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
3041                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3042                 E1000_WRITE_FLUSH(hw);
3043         }
3044         udelay(150);
3045 }
3046
3047 /******************************************************************************
3048 * Resets the PHY
3049 *
3050 * hw - Struct containing variables accessed by shared code
3051 *
3052 * Sets bit 15 of the MII Control regiser
3053 ******************************************************************************/
3054 static int 
3055 e1000_phy_reset(struct e1000_hw *hw)
3056 {
3057         int32_t ret_val;
3058         uint16_t phy_data;
3059
3060         DEBUGFUNC("e1000_phy_reset");
3061
3062         if(hw->mac_type != e1000_82541_rev_2) {
3063                 if((ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data)))
3064                         return ret_val;
3065                 
3066                 phy_data |= MII_CR_RESET;
3067                 if((ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data)))
3068                         return ret_val;
3069                 
3070                 udelay(1);
3071         } else e1000_phy_hw_reset(hw);
3072
3073         if(hw->phy_type == e1000_phy_igp)
3074                 e1000_phy_init_script(hw);
3075
3076         return E1000_SUCCESS;
3077 }
3078
3079 /******************************************************************************
3080 * Probes the expected PHY address for known PHY IDs
3081 *
3082 * hw - Struct containing variables accessed by shared code
3083 ******************************************************************************/
3084 static int
3085 e1000_detect_gig_phy(struct e1000_hw *hw)
3086 {
3087         int32_t phy_init_status, ret_val;
3088         uint16_t phy_id_high, phy_id_low;
3089         boolean_t match = FALSE;
3090
3091         DEBUGFUNC("e1000_detect_gig_phy");
3092         
3093         /* Read the PHY ID Registers to identify which PHY is onboard. */
3094         if((ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high)))
3095                 return ret_val;
3096
3097         hw->phy_id = (uint32_t) (phy_id_high << 16);
3098         udelay(20);
3099         if((ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low)))
3100                 return ret_val;
3101         
3102         hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
3103 #ifdef LINUX_DRIVER
3104         hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
3105 #endif
3106         
3107         switch(hw->mac_type) {
3108         case e1000_82543:
3109                 if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
3110                 break;
3111         case e1000_82544:
3112                 if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
3113                 break;
3114         case e1000_82540:
3115         case e1000_82545:
3116         case e1000_82545_rev_3:
3117         case e1000_82546:
3118         case e1000_82546_rev_3:
3119                 if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
3120                 break;
3121         case e1000_82541:
3122         case e1000_82541_rev_2:
3123         case e1000_82547:
3124         case e1000_82547_rev_2:
3125                 if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
3126                 break;
3127         default:
3128                 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
3129                 return -E1000_ERR_CONFIG;
3130         }
3131         phy_init_status = e1000_set_phy_type(hw);
3132
3133         if ((match) && (phy_init_status == E1000_SUCCESS)) {
3134                 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
3135                 return E1000_SUCCESS;
3136         }
3137         DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
3138         return -E1000_ERR_PHY;
3139 }
3140
3141 /******************************************************************************
3142  * Sets up eeprom variables in the hw struct.  Must be called after mac_type
3143  * is configured.
3144  *
3145  * hw - Struct containing variables accessed by shared code
3146  *****************************************************************************/
3147 static void
3148 e1000_init_eeprom_params(struct e1000_hw *hw)
3149 {
3150         struct e1000_eeprom_info *eeprom = &hw->eeprom;
3151         uint32_t eecd = E1000_READ_REG(hw, EECD);
3152         uint16_t eeprom_size;
3153
3154         DEBUGFUNC("e1000_init_eeprom_params");
3155
3156         switch (hw->mac_type) {
3157         case e1000_82542_rev2_0:
3158         case e1000_82542_rev2_1:
3159         case e1000_82543:
3160         case e1000_82544:
3161                 eeprom->type = e1000_eeprom_microwire;
3162                 eeprom->word_size = 64;
3163                 eeprom->opcode_bits = 3;
3164                 eeprom->address_bits = 6;
3165                 eeprom->delay_usec = 50;
3166                 break;
3167         case e1000_82540:
3168         case e1000_82545:
3169         case e1000_82545_rev_3:
3170         case e1000_82546:
3171         case e1000_82546_rev_3:
3172                 eeprom->type = e1000_eeprom_microwire;
3173                 eeprom->opcode_bits = 3;
3174                 eeprom->delay_usec = 50;
3175                 if(eecd & E1000_EECD_SIZE) {
3176                         eeprom->word_size = 256;
3177                         eeprom->address_bits = 8;
3178                 } else {
3179                         eeprom->word_size = 64;
3180                         eeprom->address_bits = 6;
3181                 }
3182                 break;
3183         case e1000_82541:
3184         case e1000_82541_rev_2:
3185         case e1000_82547:
3186         case e1000_82547_rev_2:
3187                 if (eecd & E1000_EECD_TYPE) {
3188                         eeprom->type = e1000_eeprom_spi;
3189                         if (eecd & E1000_EECD_ADDR_BITS) {
3190                                 eeprom->page_size = 32;
3191                                 eeprom->address_bits = 16;
3192                         } else {
3193                                 eeprom->page_size = 8;
3194                                 eeprom->address_bits = 8;
3195                         }
3196                 } else {
3197                         eeprom->type = e1000_eeprom_microwire;
3198                         eeprom->opcode_bits = 3;
3199                         eeprom->delay_usec = 50;
3200                         if (eecd & E1000_EECD_ADDR_BITS) {
3201                                 eeprom->word_size = 256;
3202                                 eeprom->address_bits = 8;
3203                         } else {
3204                                 eeprom->word_size = 64;
3205                                 eeprom->address_bits = 6;
3206                         }
3207                 }
3208                 break;
3209         default:
3210                 eeprom->type = e1000_eeprom_spi;
3211                 if (eecd & E1000_EECD_ADDR_BITS) {
3212                         eeprom->page_size = 32;
3213                         eeprom->address_bits = 16;
3214                 } else {
3215                         eeprom->page_size = 8;
3216                         eeprom->address_bits = 8;
3217                 }
3218                 break;
3219         }
3220
3221         if (eeprom->type == e1000_eeprom_spi) {
3222                 eeprom->opcode_bits = 8;
3223                 eeprom->delay_usec = 1;
3224                 eeprom->word_size = 64;
3225                 if (e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size) == 0) {
3226                         eeprom_size &= EEPROM_SIZE_MASK;
3227
3228                         switch (eeprom_size) {
3229                         case EEPROM_SIZE_16KB:
3230                                 eeprom->word_size = 8192;
3231                                 break;
3232                         case EEPROM_SIZE_8KB:
3233                                 eeprom->word_size = 4096;
3234                                 break;
3235                         case EEPROM_SIZE_4KB:
3236                                 eeprom->word_size = 2048;
3237                                 break;
3238                         case EEPROM_SIZE_2KB:
3239                                 eeprom->word_size = 1024;
3240                                 break;
3241                         case EEPROM_SIZE_1KB:
3242                                 eeprom->word_size = 512;
3243                                 break;
3244                         case EEPROM_SIZE_512B:
3245                                 eeprom->word_size = 256;
3246                                 break;
3247                         case EEPROM_SIZE_128B:
3248                         default:
3249                                 break;
3250                         }
3251                 }
3252         }
3253 }
3254
3255 /**
3256  * e1000_reset - Reset the adapter
3257  */
3258
3259 static int
3260 e1000_reset(struct e1000_hw *hw)
3261 {
3262         uint32_t pba;
3263         /* Repartition Pba for greater than 9k mtu
3264          * To take effect CTRL.RST is required.
3265          */
3266
3267         if(hw->mac_type < e1000_82547) {
3268                 pba = E1000_PBA_48K;
3269         } else {
3270                 pba = E1000_PBA_30K;
3271         }
3272         E1000_WRITE_REG(hw, PBA, pba);
3273
3274         /* flow control settings */
3275 #if 0
3276         hw->fc_high_water = FC_DEFAULT_HI_THRESH;
3277         hw->fc_low_water = FC_DEFAULT_LO_THRESH;
3278         hw->fc_pause_time = FC_DEFAULT_TX_TIMER;
3279         hw->fc_send_xon = 1;
3280         hw->fc = hw->original_fc;
3281 #endif
3282         
3283         e1000_reset_hw(hw);
3284         if(hw->mac_type >= e1000_82544)
3285                 E1000_WRITE_REG(hw, WUC, 0);
3286         return e1000_init_hw(hw);
3287 }
3288
3289 /**
3290  * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
3291  * @adapter: board private structure to initialize
3292  *
3293  * e1000_sw_init initializes the Adapter private data structure.
3294  * Fields are initialized based on PCI device information and
3295  * OS network device settings (MTU size).
3296  **/
3297
3298 static int 
3299 e1000_sw_init(struct pci_device *pdev, struct e1000_hw *hw)
3300 {
3301         int result;
3302
3303         /* PCI config space info */
3304         pci_read_config_word(pdev, PCI_VENDOR_ID, &hw->vendor_id);
3305         pci_read_config_word(pdev, PCI_DEVICE_ID, &hw->device_id);
3306         pci_read_config_byte(pdev, PCI_REVISION, &hw->revision_id);
3307 #if 0
3308         pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID,
3309                              &hw->subsystem_vendor_id);
3310         pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
3311 #endif
3312
3313         pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
3314
3315         /* identify the MAC */
3316
3317         result = e1000_set_mac_type(hw);
3318         if (result) {
3319                 E1000_ERR("Unknown MAC Type\n");
3320                 return result;
3321         }
3322
3323         /* initialize eeprom parameters */
3324
3325         e1000_init_eeprom_params(hw);
3326
3327 #if 0
3328         if((hw->mac_type == e1000_82541) ||
3329            (hw->mac_type == e1000_82547) ||
3330            (hw->mac_type == e1000_82541_rev_2) ||
3331            (hw->mac_type == e1000_82547_rev_2))
3332                 hw->phy_init_script = 1;
3333 #endif
3334
3335         e1000_set_media_type(hw);
3336
3337 #if 0
3338         if(hw->mac_type < e1000_82543)
3339                 hw->report_tx_early = 0;
3340         else
3341                 hw->report_tx_early = 1;
3342
3343         hw->wait_autoneg_complete = FALSE;
3344 #endif
3345         hw->tbi_compatibility_en = TRUE;
3346 #if 0
3347         hw->adaptive_ifs = TRUE;
3348
3349         /* Copper options */
3350
3351         if(hw->media_type == e1000_media_type_copper) {
3352                 hw->mdix = AUTO_ALL_MODES;
3353                 hw->disable_polarity_correction = FALSE;
3354                 hw->master_slave = E1000_MASTER_SLAVE;
3355         }
3356 #endif
3357         return E1000_SUCCESS;
3358 }
3359
3360 static void fill_rx (void)
3361 {
3362         struct e1000_rx_desc *rd;
3363         rx_last = rx_tail;
3364         rd = rx_base + rx_tail;
3365         rx_tail = (rx_tail + 1) % 8;
3366         memset (rd, 0, 16);
3367         rd->buffer_addr = virt_to_bus(&e1000_bufs.packet);
3368         E1000_WRITE_REG (&hw, RDT, rx_tail);
3369 }
3370
3371 static void init_descriptor (void)
3372 {
3373         unsigned long ptr;
3374         unsigned long tctl;
3375
3376         ptr = virt_to_phys(e1000_bufs.tx_pool);
3377         if (ptr & 0xf)
3378                 ptr = (ptr + 0x10) & (~0xf);
3379
3380         tx_base = phys_to_virt(ptr);
3381
3382         E1000_WRITE_REG (&hw, TDBAL, virt_to_bus(tx_base));
3383         E1000_WRITE_REG (&hw, TDBAH, 0);
3384         E1000_WRITE_REG (&hw, TDLEN, 128);
3385
3386         /* Setup the HW Tx Head and Tail descriptor pointers */
3387
3388         E1000_WRITE_REG (&hw, TDH, 0);
3389         E1000_WRITE_REG (&hw, TDT, 0);
3390         tx_tail = 0;
3391
3392         /* Program the Transmit Control Register */
3393
3394 #ifdef LINUX_DRIVER_TCTL
3395         tctl = E1000_READ_REG(&hw, TCTL);
3396
3397         tctl &= ~E1000_TCTL_CT;
3398         tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
3399                 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
3400 #else
3401         tctl = E1000_TCTL_PSP | E1000_TCTL_EN |
3402                 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT) | 
3403                 (E1000_HDX_COLLISION_DISTANCE << E1000_COLD_SHIFT);
3404 #endif
3405
3406         E1000_WRITE_REG (&hw, TCTL, tctl);
3407
3408         e1000_config_collision_dist(&hw);
3409
3410
3411         rx_tail = 0;
3412         /* disable receive */
3413         E1000_WRITE_REG (&hw, RCTL, 0);
3414         ptr = virt_to_phys(e1000_bufs.rx_pool);
3415         if (ptr & 0xf)
3416                 ptr = (ptr + 0x10) & (~0xf);
3417         rx_base = phys_to_virt(ptr);
3418
3419         /* Setup the Base and Length of the Rx Descriptor Ring */
3420
3421         E1000_WRITE_REG (&hw, RDBAL, virt_to_bus(rx_base));
3422         E1000_WRITE_REG (&hw, RDBAH, 0);
3423
3424         E1000_WRITE_REG (&hw, RDLEN, 128);
3425
3426         /* Setup the HW Rx Head and Tail Descriptor Pointers */