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inline | side by side (from parent 1:
bea8787)
e1000 should now work in VMware.
rctl = E1000_READ_REG ( hw, RCTL );
E1000_WRITE_REG ( hw, RCTL, rctl & ~E1000_RCTL_EN );
rctl = E1000_READ_REG ( hw, RCTL );
E1000_WRITE_REG ( hw, RCTL, rctl & ~E1000_RCTL_EN );
/* Setup the HW Rx Head and Tail Descriptor Pointers and
* the Base and Length of the Rx Descriptor Ring */
/* Setup the HW Rx Head and Tail Descriptor Pointers and
* the Base and Length of the Rx Descriptor Ring */
E1000_WRITE_REG ( hw, RDLEN, adapter->rx_ring_size );
E1000_WRITE_REG ( hw, RDH, 0 );
E1000_WRITE_REG ( hw, RDLEN, adapter->rx_ring_size );
E1000_WRITE_REG ( hw, RDH, 0 );
- E1000_WRITE_REG ( hw, RDT, NUM_TX_DESC );
+ E1000_WRITE_REG ( hw, RDT, NUM_RX_DESC - 1 );
/* Enable Receives */
rctl = ( E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_SZ_2048 |
/* Enable Receives */
rctl = ( E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_SZ_2048 |
rx_curr_desc = ( void * ) ( adapter->rx_base ) +
( i * sizeof ( *adapter->rx_base ) );
rx_curr_desc = ( void * ) ( adapter->rx_base ) +
( i * sizeof ( *adapter->rx_base ) );
rx_len = rx_curr_desc->length;
rx_len = rx_curr_desc->length;
- DBG ( "Received packet, rx_tail: %ld rx_status: %#08lx rx_len: %ld\n",
+ DBG ( "Received packet, rx_curr: %ld rx_status: %#08lx rx_len: %ld\n",
i, rx_status, rx_len );
rx_err = rx_curr_desc->errors;
i, rx_status, rx_len );
rx_err = rx_curr_desc->errors;
memset ( rx_curr_desc, 0, sizeof ( *rx_curr_desc ) );
rx_curr_desc->buffer_addr = tmp_buffer_addr;
memset ( rx_curr_desc, 0, sizeof ( *rx_curr_desc ) );
rx_curr_desc->buffer_addr = tmp_buffer_addr;
- E1000_WRITE_REG ( hw, RDT, adapter->rx_tail );
+ E1000_WRITE_REG ( hw, RDT, adapter->rx_curr );
- adapter->rx_tail = ( adapter->rx_tail + 1 ) % NUM_RX_DESC;
+ adapter->rx_curr = ( adapter->rx_curr + 1 ) % NUM_RX_DESC;
uint32_t tx_tail;
uint32_t tx_fill_ctr;
uint32_t tx_tail;
uint32_t tx_fill_ctr;
uint32_t ioaddr;
uint32_t irqno;
uint32_t ioaddr;
uint32_t irqno;