[e1000e] Add e1000e driver
[people/pcmattman/gpxe.git] / src / drivers / net / e1000e / e1000e_ich8lan.c
1 /*******************************************************************************
2
3   Intel PRO/1000 Linux driver
4   Copyright(c) 1999 - 2009 Intel Corporation.
5
6   This program is free software; you can redistribute it and/or modify it
7   under the terms and conditions of the GNU General Public License,
8   version 2, as published by the Free Software Foundation.
9
10   This program is distributed in the hope it will be useful, but WITHOUT
11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13   more details.
14
15   You should have received a copy of the GNU General Public License along with
16   this program; if not, write to the Free Software Foundation, Inc.,
17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19   The full GNU General Public License is included in this distribution in
20   the file called "COPYING".
21
22   Contact Information:
23   Linux NICS <linux.nics@intel.com>
24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 FILE_LICENCE ( GPL2_OR_LATER );
30
31 /*
32  * 82562G 10/100 Network Connection
33  * 82562G-2 10/100 Network Connection
34  * 82562GT 10/100 Network Connection
35  * 82562GT-2 10/100 Network Connection
36  * 82562V 10/100 Network Connection
37  * 82562V-2 10/100 Network Connection
38  * 82566DC-2 Gigabit Network Connection
39  * 82566DC Gigabit Network Connection
40  * 82566DM-2 Gigabit Network Connection
41  * 82566DM Gigabit Network Connection
42  * 82566MC Gigabit Network Connection
43  * 82566MM Gigabit Network Connection
44  * 82567LM Gigabit Network Connection
45  * 82567LF Gigabit Network Connection
46  * 82567V Gigabit Network Connection
47  * 82567LM-2 Gigabit Network Connection
48  * 82567LF-2 Gigabit Network Connection
49  * 82567V-2 Gigabit Network Connection
50  * 82567LF-3 Gigabit Network Connection
51  * 82567LM-3 Gigabit Network Connection
52  * 82567LM-4 Gigabit Network Connection
53  * 82577LM Gigabit Network Connection
54  * 82577LC Gigabit Network Connection
55  * 82578DM Gigabit Network Connection
56  * 82578DC Gigabit Network Connection
57  */
58
59 #include "e1000e.h"
60
61 static s32  e1000e_init_phy_params_ich8lan(struct e1000_hw *hw);
62 static s32  e1000e_init_phy_params_pchlan(struct e1000_hw *hw);
63 static s32  e1000e_init_nvm_params_ich8lan(struct e1000_hw *hw);
64 static s32  e1000e_init_mac_params_ich8lan(struct e1000_hw *hw);
65 static s32  e1000e_acquire_swflag_ich8lan(struct e1000_hw *hw);
66 static void e1000e_release_swflag_ich8lan(struct e1000_hw *hw);
67 static s32  e1000e_acquire_nvm_ich8lan(struct e1000_hw *hw);
68 static void e1000e_release_nvm_ich8lan(struct e1000_hw *hw);
69 static bool e1000e_check_mng_mode_ich8lan(struct e1000_hw *hw);
70 static s32  e1000e_check_reset_block_ich8lan(struct e1000_hw *hw);
71 static s32  e1000e_phy_hw_reset_ich8lan(struct e1000_hw *hw);
72 static s32  e1000e_get_phy_info_ich8lan(struct e1000_hw *hw);
73 static s32  e1000e_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
74 static s32  e1000e_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
75                                             bool active);
76 static s32  e1000e_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
77                                             bool active);
78 static s32  e1000e_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
79                                    u16 words, u16 *data);
80 static s32  e1000e_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
81                                     u16 words, u16 *data);
82 static s32  e1000e_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
83 static s32  e1000e_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
84 static s32  e1000e_valid_led_default_ich8lan(struct e1000_hw *hw,
85                                             u16 *data);
86 static s32  e1000e_id_led_init_pchlan(struct e1000_hw *hw);
87 static s32  e1000e_get_bus_info_ich8lan(struct e1000_hw *hw);
88 static s32  e1000e_reset_hw_ich8lan(struct e1000_hw *hw);
89 static s32  e1000e_init_hw_ich8lan(struct e1000_hw *hw);
90 static s32  e1000e_setup_link_ich8lan(struct e1000_hw *hw);
91 static s32  e1000e_setup_copper_link_ich8lan(struct e1000_hw *hw);
92 static s32  e1000e_get_link_up_info_ich8lan(struct e1000_hw *hw,
93                                            u16 *speed, u16 *duplex);
94 static s32  e1000e_cleanup_led_ich8lan(struct e1000_hw *hw);
95 static s32  e1000e_led_on_ich8lan(struct e1000_hw *hw);
96 static s32  e1000e_led_off_ich8lan(struct e1000_hw *hw);
97 static s32  e1000e_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
98 static s32  e1000e_setup_led_pchlan(struct e1000_hw *hw);
99 static s32  e1000e_cleanup_led_pchlan(struct e1000_hw *hw);
100 static s32  e1000e_led_on_pchlan(struct e1000_hw *hw);
101 static s32  e1000e_led_off_pchlan(struct e1000_hw *hw);
102 static void e1000e_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
103 static s32  e1000e_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
104 static s32  e1000e_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout);
105 static s32  e1000e_flash_cycle_init_ich8lan(struct e1000_hw *hw);
106 static s32  e1000e_get_phy_info_ife_ich8lan(struct e1000_hw *hw);
107 static void e1000e_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
108 static s32  e1000e_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
109 static s32  e1000e_read_flash_byte_ich8lan(struct e1000_hw *hw,
110                                           u32 offset, u8 *data);
111 static s32  e1000e_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
112                                           u8 size, u16 *data);
113 static s32  e1000e_read_flash_word_ich8lan(struct e1000_hw *hw,
114                                           u32 offset, u16 *data);
115 static s32  e1000e_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
116                                                  u32 offset, u8 byte);
117 static s32  e1000e_write_flash_byte_ich8lan(struct e1000_hw *hw,
118                                            u32 offset, u8 data);
119 static s32  e1000e_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
120                                            u8 size, u16 data);
121 static s32  e1000e_get_cfg_done_ich8lan(struct e1000_hw *hw);
122 static void e1000e_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
123 static s32  e1000e_check_for_copper_link_ich8lan(struct e1000_hw *hw);
124 static void e1000e_lan_init_done_ich8lan(struct e1000_hw *hw);
125 static s32  e1000e_sw_lcd_config_ich8lan(struct e1000_hw *hw);
126
127 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
128 /* Offset 04h HSFSTS */
129 union ich8_hws_flash_status {
130         struct ich8_hsfsts {
131                 u16 flcdone    :1; /* bit 0 Flash Cycle Done */
132                 u16 flcerr     :1; /* bit 1 Flash Cycle Error */
133                 u16 dael       :1; /* bit 2 Direct Access error Log */
134                 u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
135                 u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
136                 u16 reserved1  :2; /* bit 13:6 Reserved */
137                 u16 reserved2  :6; /* bit 13:6 Reserved */
138                 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
139                 u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
140         } hsf_status;
141         u16 regval;
142 };
143
144 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
145 /* Offset 06h FLCTL */
146 union ich8_hws_flash_ctrl {
147         struct ich8_hsflctl {
148                 u16 flcgo      :1;   /* 0 Flash Cycle Go */
149                 u16 flcycle    :2;   /* 2:1 Flash Cycle */
150                 u16 reserved   :5;   /* 7:3 Reserved  */
151                 u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
152                 u16 flockdn    :6;   /* 15:10 Reserved */
153         } hsf_ctrl;
154         u16 regval;
155 };
156
157 /* ICH Flash Region Access Permissions */
158 union ich8_hws_flash_regacc {
159         struct ich8_flracc {
160                 u32 grra      :8; /* 0:7 GbE region Read Access */
161                 u32 grwa      :8; /* 8:15 GbE region Write Access */
162                 u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
163                 u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
164         } hsf_flregacc;
165         u16 regval;
166 };
167
168 /**
169  *  e1000e_init_phy_params_pchlan - Initialize PHY function pointers
170  *  @hw: pointer to the HW structure
171  *
172  *  Initialize family-specific PHY parameters and function pointers.
173  **/
174 static s32 e1000e_init_phy_params_pchlan(struct e1000_hw *hw)
175 {
176         struct e1000_phy_info *phy = &hw->phy;
177         s32 ret_val = E1000_SUCCESS;
178
179         phy->addr                     = 1;
180         phy->reset_delay_us           = 100;
181
182         phy->ops.acquire              = e1000e_acquire_swflag_ich8lan;
183         phy->ops.check_polarity       = e1000e_check_polarity_ife;
184         phy->ops.check_reset_block    = e1000e_check_reset_block_ich8lan;
185 #if 0
186         phy->ops.force_speed_duplex   = e1000e_phy_force_speed_duplex_ife;
187 #endif
188 #if 0
189         phy->ops.get_cable_length     = e1000e_get_cable_length_igp_2;
190 #endif
191         phy->ops.get_cfg_done         = e1000e_get_cfg_done_ich8lan;
192         phy->ops.get_info             = e1000e_get_phy_info_ich8lan;
193         phy->ops.read_reg             = e1000e_read_phy_reg_hv;
194         phy->ops.read_reg_locked      = e1000e_read_phy_reg_hv_locked;
195         phy->ops.release              = e1000e_release_swflag_ich8lan;
196         phy->ops.reset                = e1000e_phy_hw_reset_ich8lan;
197         phy->ops.set_d0_lplu_state    = e1000e_set_lplu_state_pchlan;
198         phy->ops.set_d3_lplu_state    = e1000e_set_lplu_state_pchlan;
199         phy->ops.write_reg            = e1000e_write_phy_reg_hv;
200         phy->ops.write_reg_locked     = e1000e_write_phy_reg_hv_locked;
201         phy->ops.power_up             = e1000e_power_up_phy_copper;
202         phy->ops.power_down           = e1000e_power_down_phy_copper_ich8lan;
203         phy->autoneg_mask             = AUTONEG_ADVERTISE_SPEED_DEFAULT;
204
205         phy->id = e1000_phy_unknown;
206         e1000e_get_phy_id(hw);
207         phy->type = e1000e_get_phy_type_from_id(phy->id);
208
209         if (phy->type == e1000_phy_82577) {
210                 phy->ops.check_polarity = e1000e_check_polarity_82577;
211 #if 0
212                 phy->ops.force_speed_duplex =
213                         e1000e_phy_force_speed_duplex_82577;
214 #endif
215 #if 0
216                 phy->ops.get_cable_length   = e1000e_get_cable_length_82577;
217 #endif
218                 phy->ops.get_info = e1000e_get_phy_info_82577;
219                 phy->ops.commit = e1000e_phy_sw_reset;
220         }
221
222         return ret_val;
223 }
224
225 /**
226  *  e1000e_init_phy_params_ich8lan - Initialize PHY function pointers
227  *  @hw: pointer to the HW structure
228  *
229  *  Initialize family-specific PHY parameters and function pointers.
230  **/
231 static s32 e1000e_init_phy_params_ich8lan(struct e1000_hw *hw)
232 {
233         struct e1000_phy_info *phy = &hw->phy;
234         s32 ret_val = E1000_SUCCESS;
235         u16 i = 0;
236
237         phy->addr                     = 1;
238         phy->reset_delay_us           = 100;
239
240         phy->ops.acquire              = e1000e_acquire_swflag_ich8lan;
241         phy->ops.check_polarity       = e1000e_check_polarity_ife;
242         phy->ops.check_reset_block    = e1000e_check_reset_block_ich8lan;
243 #if 0
244         phy->ops.force_speed_duplex   = e1000e_phy_force_speed_duplex_ife;
245 #endif
246 #if 0
247         phy->ops.get_cable_length     = e1000e_get_cable_length_igp_2;
248 #endif
249         phy->ops.get_cfg_done         = e1000e_get_cfg_done_ich8lan;
250         phy->ops.get_info             = e1000e_get_phy_info_ich8lan;
251         phy->ops.read_reg             = e1000e_read_phy_reg_igp;
252         phy->ops.release              = e1000e_release_swflag_ich8lan;
253         phy->ops.reset                = e1000e_phy_hw_reset_ich8lan;
254         phy->ops.set_d0_lplu_state    = e1000e_set_d0_lplu_state_ich8lan;
255         phy->ops.set_d3_lplu_state    = e1000e_set_d3_lplu_state_ich8lan;
256         phy->ops.write_reg            = e1000e_write_phy_reg_igp;
257         phy->ops.power_up             = e1000e_power_up_phy_copper;
258         phy->ops.power_down           = e1000e_power_down_phy_copper_ich8lan;
259
260         /*
261          * We may need to do this twice - once for IGP and if that fails,
262          * we'll set BM func pointers and try again
263          */
264         ret_val = e1000e_determine_phy_address(hw);
265         if (ret_val) {
266                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
267                 phy->ops.read_reg  = e1000e_read_phy_reg_bm;
268                 ret_val = e1000e_determine_phy_address(hw);
269                 if (ret_val) {
270                         DBG("Cannot determine PHY addr. Erroring out\n");
271                         goto out;
272                 }
273         }
274
275         phy->id = 0;
276         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
277                (i++ < 100)) {
278                 msleep(1);
279                 ret_val = e1000e_get_phy_id(hw);
280                 if (ret_val)
281                         goto out;
282         }
283
284         /* Verify phy id */
285         switch (phy->id) {
286         case IGP03E1000_E_PHY_ID:
287                 phy->type = e1000_phy_igp_3;
288                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
289                 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
290                 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
291                 break;
292         case IFE_E_PHY_ID:
293         case IFE_PLUS_E_PHY_ID:
294         case IFE_C_E_PHY_ID:
295                 phy->type = e1000_phy_ife;
296                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
297                 break;
298         case BME1000_E_PHY_ID:
299                 phy->type = e1000_phy_bm;
300                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
301                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
302                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
303                 phy->ops.commit = e1000e_phy_sw_reset;
304                 break;
305         default:
306                 ret_val = -E1000_ERR_PHY;
307                 goto out;
308         }
309
310 out:
311         return ret_val;
312 }
313
314 /**
315  *  e1000e_init_nvm_params_ich8lan - Initialize NVM function pointers
316  *  @hw: pointer to the HW structure
317  *
318  *  Initialize family-specific NVM parameters and function
319  *  pointers.
320  **/
321 static s32 e1000e_init_nvm_params_ich8lan(struct e1000_hw *hw)
322 {
323         struct e1000_nvm_info *nvm = &hw->nvm;
324         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
325         u32 gfpreg, sector_base_addr, sector_end_addr;
326         s32 ret_val = E1000_SUCCESS;
327         u16 i;
328
329         /* Can't read flash registers if the register set isn't mapped. */
330         if (!hw->flash_address) {
331                 e_dbg("ERROR: Flash registers not mapped\n");
332                 ret_val = -E1000_ERR_CONFIG;
333                 goto out;
334         }
335
336         nvm->type = e1000_nvm_flash_sw;
337
338         gfpreg = er32flash(ICH_FLASH_GFPREG);
339
340         /*
341          * sector_X_addr is a "sector"-aligned address (4096 bytes)
342          * Add 1 to sector_end_addr since this sector is included in
343          * the overall size.
344          */
345         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
346         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
347
348         /* flash_base_addr is byte-aligned */
349         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
350
351         /*
352          * find total size of the NVM, then cut in half since the total
353          * size represents two separate NVM banks.
354          */
355         nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
356                                   << FLASH_SECTOR_ADDR_SHIFT;
357         nvm->flash_bank_size /= 2;
358         /* Adjust to word count */
359         nvm->flash_bank_size /= sizeof(u16);
360
361         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
362
363         /* Clear shadow ram */
364         for (i = 0; i < nvm->word_size; i++) {
365                 dev_spec->shadow_ram[i].modified = false;
366                 dev_spec->shadow_ram[i].value    = 0xFFFF;
367         }
368
369         /* Function Pointers */
370         nvm->ops.acquire       = e1000e_acquire_nvm_ich8lan;
371         nvm->ops.release       = e1000e_release_nvm_ich8lan;
372         nvm->ops.read          = e1000e_read_nvm_ich8lan;
373         nvm->ops.update        = e1000e_update_nvm_checksum_ich8lan;
374         nvm->ops.valid_led_default = e1000e_valid_led_default_ich8lan;
375         nvm->ops.validate      = e1000e_validate_nvm_checksum_ich8lan;
376         nvm->ops.write         = e1000e_write_nvm_ich8lan;
377
378 out:
379         return ret_val;
380 }
381
382 /**
383  *  e1000e_init_mac_params_ich8lan - Initialize MAC function pointers
384  *  @hw: pointer to the HW structure
385  *
386  *  Initialize family-specific MAC parameters and function
387  *  pointers.
388  **/
389 static s32 e1000e_init_mac_params_ich8lan(struct e1000_hw *hw)
390 {
391         struct e1000_mac_info *mac = &hw->mac;
392
393         /* Set media type function pointer */
394         hw->phy.media_type = e1000_media_type_copper;
395
396         /* Set mta register count */
397         mac->mta_reg_count = 32;
398         /* Set rar entry count */
399         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
400         if (mac->type == e1000_ich8lan)
401                 mac->rar_entry_count--;
402         /* Set if part includes ASF firmware */
403         mac->asf_firmware_present = true;
404         /* Set if manageability features are enabled. */
405         mac->arc_subsystem_valid = true;
406
407         /* Function pointers */
408
409         /* bus type/speed/width */
410         mac->ops.get_bus_info = e1000e_get_bus_info_ich8lan;
411         /* function id */
412         mac->ops.set_lan_id = e1000e_set_lan_id_single_port;
413         /* reset */
414         mac->ops.reset_hw = e1000e_reset_hw_ich8lan;
415         /* hw initialization */
416         mac->ops.init_hw = e1000e_init_hw_ich8lan;
417         /* link setup */
418         mac->ops.setup_link = e1000e_setup_link_ich8lan;
419         /* physical interface setup */
420         mac->ops.setup_physical_interface = e1000e_setup_copper_link_ich8lan;
421         /* check for link */
422         mac->ops.check_for_link = e1000e_check_for_copper_link_ich8lan;
423         /* check management mode */
424         mac->ops.check_mng_mode = e1000e_check_mng_mode_ich8lan;
425         /* link info */
426         mac->ops.get_link_up_info = e1000e_get_link_up_info_ich8lan;
427         /* multicast address update */
428         mac->ops.update_mc_addr_list = e1000e_update_mc_addr_list_generic;
429         /* setting MTA */
430         mac->ops.mta_set = e1000e_mta_set_generic;
431         /* clear hardware counters */
432         mac->ops.clear_hw_cntrs = e1000e_clear_hw_cntrs_ich8lan;
433
434         /* LED operations */
435         switch (mac->type) {
436         case e1000_ich8lan:
437         case e1000_ich9lan:
438         case e1000_ich10lan:
439                 /* ID LED init */
440                 mac->ops.id_led_init = e1000e_id_led_init;
441                 /* blink LED */
442                 mac->ops.blink_led = e1000e_blink_led;
443                 /* setup LED */
444                 mac->ops.setup_led = e1000e_setup_led_generic;
445                 /* cleanup LED */
446                 mac->ops.cleanup_led = e1000e_cleanup_led_ich8lan;
447                 /* turn on/off LED */
448                 mac->ops.led_on = e1000e_led_on_ich8lan;
449                 mac->ops.led_off = e1000e_led_off_ich8lan;
450                 break;
451         case e1000_pchlan:
452                 /* ID LED init */
453                 mac->ops.id_led_init = e1000e_id_led_init_pchlan;
454                 /* setup LED */
455                 mac->ops.setup_led = e1000e_setup_led_pchlan;
456                 /* cleanup LED */
457                 mac->ops.cleanup_led = e1000e_cleanup_led_pchlan;
458                 /* turn on/off LED */
459                 mac->ops.led_on = e1000e_led_on_pchlan;
460                 mac->ops.led_off = e1000e_led_off_pchlan;
461                 break;
462         default:
463                 break;
464         }
465
466         /* Enable PCS Lock-loss workaround for ICH8 */
467         if (mac->type == e1000_ich8lan)
468                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
469
470
471         return E1000_SUCCESS;
472 }
473
474 /**
475  *  e1000e_check_for_copper_link_ich8lan - Check for link (Copper)
476  *  @hw: pointer to the HW structure
477  *
478  *  Checks to see of the link status of the hardware has changed.  If a
479  *  change in link status has been detected, then we read the PHY registers
480  *  to get the current speed/duplex if link exists.
481  **/
482 static s32 e1000e_check_for_copper_link_ich8lan(struct e1000_hw *hw)
483 {
484         struct e1000_mac_info *mac = &hw->mac;
485         s32 ret_val;
486         bool link;
487
488         /*
489          * We only want to go out to the PHY registers to see if Auto-Neg
490          * has completed and/or if our link status has changed.  The
491          * get_link_status flag is set upon receiving a Link Status
492          * Change or Rx Sequence Error interrupt.
493          */
494         if (!mac->get_link_status) {
495                 ret_val = E1000_SUCCESS;
496                 goto out;
497         }
498
499         /*
500          * First we want to see if the MII Status Register reports
501          * link.  If so, then we want to get the current speed/duplex
502          * of the PHY.
503          */
504         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
505         if (ret_val)
506                 goto out;
507
508         if (hw->mac.type == e1000_pchlan) {
509                 ret_val = e1000e_k1_gig_workaround_hv(hw, link);
510                 if (ret_val)
511                         goto out;
512         }
513
514         if (!link)
515                 goto out; /* No link detected */
516
517         mac->get_link_status = false;
518
519         if (hw->phy.type == e1000_phy_82578) {
520                 ret_val = e1000e_link_stall_workaround_hv(hw);
521                 if (ret_val)
522                         goto out;
523         }
524
525         /*
526          * Check if there was DownShift, must be checked
527          * immediately after link-up
528          */
529         e1000e_check_downshift(hw);
530
531         /*
532          * If we are forcing speed/duplex, then we simply return since
533          * we have already determined whether we have link or not.
534          */
535         if (!mac->autoneg) {
536                 ret_val = -E1000_ERR_CONFIG;
537                 goto out;
538         }
539
540         /*
541          * Auto-Neg is enabled.  Auto Speed Detection takes care
542          * of MAC speed/duplex configuration.  So we only need to
543          * configure Collision Distance in the MAC.
544          */
545         e1000e_config_collision_dist(hw);
546
547         /*
548          * Configure Flow Control now that Auto-Neg has completed.
549          * First, we need to restore the desired flow control
550          * settings because we may have had to re-autoneg with a
551          * different link partner.
552          */
553         ret_val = e1000e_config_fc_after_link_up(hw);
554         if (ret_val)
555                 e_dbg("Error configuring flow control\n");
556
557 out:
558         return ret_val;
559 }
560
561 /**
562  *  e1000e_init_function_pointers_ich8lan - Initialize ICH8 function pointers
563  *  @hw: pointer to the HW structure
564  *
565  *  Initialize family-specific function pointers for PHY, MAC, and NVM.
566  **/
567 void e1000e_init_function_pointers_ich8lan(struct e1000_hw *hw)
568 {
569         e1000e_init_mac_ops_generic(hw);
570         e1000e_init_nvm_ops_generic(hw);
571         hw->mac.ops.init_params = e1000e_init_mac_params_ich8lan;
572         hw->nvm.ops.init_params = e1000e_init_nvm_params_ich8lan;
573         switch (hw->mac.type) {
574         case e1000_ich8lan:
575         case e1000_ich9lan:
576         case e1000_ich10lan:
577                 hw->phy.ops.init_params = e1000e_init_phy_params_ich8lan;
578                 break;
579         case e1000_pchlan:
580                 hw->phy.ops.init_params = e1000e_init_phy_params_pchlan;
581                 break;
582         default:
583                 break;
584         }
585 }
586
587 #if 0
588 static DEFINE_MUTEX(nvm_mutex);
589 #endif
590
591 /**
592  *  e1000e_acquire_nvm_ich8lan - Acquire NVM mutex
593  *  @hw: pointer to the HW structure
594  *
595  *  Acquires the mutex for performing NVM operations.
596  **/
597 static s32 e1000e_acquire_nvm_ich8lan(struct e1000_hw *hw __unused)
598 {
599 #if 0
600         mutex_lock(&nvm_mutex);
601 #endif
602         return E1000_SUCCESS;
603 }
604
605 /**
606  *  e1000e_release_nvm_ich8lan - Release NVM mutex
607  *  @hw: pointer to the HW structure
608  *
609  *  Releases the mutex used while performing NVM operations.
610  **/
611 static void e1000e_release_nvm_ich8lan(struct e1000_hw *hw __unused)
612 {
613 #if 0
614         mutex_unlock(&nvm_mutex);
615 #endif
616         return;
617 }
618
619 #if 0
620 static DEFINE_MUTEX(swflag_mutex);
621 #endif
622
623 /**
624  *  e1000e_acquire_swflag_ich8lan - Acquire software control flag
625  *  @hw: pointer to the HW structure
626  *
627  *  Acquires the software control flag for performing PHY and select
628  *  MAC CSR accesses.
629  **/
630 static s32 e1000e_acquire_swflag_ich8lan(struct e1000_hw *hw)
631 {
632         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
633         s32 ret_val = E1000_SUCCESS;
634
635 #if 0
636         mutex_lock(&swflag_mutex);
637 #endif
638
639         while (timeout) {
640                 extcnf_ctrl = er32(EXTCNF_CTRL);
641                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
642                         break;
643
644                 mdelay(1);
645                 timeout--;
646         }
647
648         if (!timeout) {
649                 e_dbg("SW/FW/HW has locked the resource for too long.\n");
650                 ret_val = -E1000_ERR_CONFIG;
651                 goto out;
652         }
653
654         timeout = SW_FLAG_TIMEOUT;
655
656         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
657         ew32(EXTCNF_CTRL, extcnf_ctrl);
658
659         while (timeout) {
660                 extcnf_ctrl = er32(EXTCNF_CTRL);
661                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
662                         break;
663
664                 mdelay(1);
665                 timeout--;
666         }
667
668         if (!timeout) {
669                 e_dbg("Failed to acquire the semaphore.\n");
670                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
671                 ew32(EXTCNF_CTRL, extcnf_ctrl);
672                 ret_val = -E1000_ERR_CONFIG;
673                 goto out;
674         }
675
676 out:
677 #if 0
678         if (ret_val)
679                 mutex_unlock(&swflag_mutex);
680 #endif
681         return ret_val;
682 }
683
684 /**
685  *  e1000e_release_swflag_ich8lan - Release software control flag
686  *  @hw: pointer to the HW structure
687  *
688  *  Releases the software control flag for performing PHY and select
689  *  MAC CSR accesses.
690  **/
691 static void e1000e_release_swflag_ich8lan(struct e1000_hw *hw)
692 {
693         u32 extcnf_ctrl;
694
695         extcnf_ctrl = er32(EXTCNF_CTRL);
696         extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
697         ew32(EXTCNF_CTRL, extcnf_ctrl);
698
699 #if 0
700         mutex_unlock(&swflag_mutex);
701 #endif
702         return;
703 }
704
705 /**
706  *  e1000e_check_mng_mode_ich8lan - Checks management mode
707  *  @hw: pointer to the HW structure
708  *
709  *  This checks if the adapter has manageability enabled.
710  *  This is a function pointer entry point only called by read/write
711  *  routines for the PHY and NVM parts.
712  **/
713 static bool e1000e_check_mng_mode_ich8lan(struct e1000_hw *hw)
714 {
715         u32 fwsm;
716
717         fwsm = er32(FWSM);
718         return (fwsm & E1000_FWSM_MODE_MASK) ==
719                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
720 }
721 /**
722  *  e1000e_check_reset_block_ich8lan - Check if PHY reset is blocked
723  *  @hw: pointer to the HW structure
724  *
725  *  Checks if firmware is blocking the reset of the PHY.
726  *  This is a function pointer entry point only called by
727  *  reset routines.
728  **/
729 static s32 e1000e_check_reset_block_ich8lan(struct e1000_hw *hw)
730 {
731         u32 fwsm;
732
733         fwsm = er32(FWSM);
734         return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? E1000_SUCCESS
735                                                 : E1000_BLK_PHY_RESET;
736 }
737
738 /**
739  *  e1000e_sw_lcd_config_ich8lan - SW-based LCD Configuration
740  *  @hw:   pointer to the HW structure
741  *
742  *  SW should configure the LCD from the NVM extended configuration region
743  *  as a workaround for certain parts.
744  **/
745 static s32 e1000e_sw_lcd_config_ich8lan(struct e1000_hw *hw)
746 {
747         struct e1000_phy_info *phy = &hw->phy;
748         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
749         s32 ret_val;
750         u16 word_addr, reg_data, reg_addr, phy_page = 0;
751
752         ret_val = hw->phy.ops.acquire(hw);
753         if (ret_val)
754                 return ret_val;
755
756         /*
757          * Initialize the PHY from the NVM on ICH platforms.  This
758          * is needed due to an issue where the NVM configuration is
759          * not properly autoloaded after power transitions.
760          * Therefore, after each PHY reset, we will load the
761          * configuration data out of the NVM manually.
762          */
763         if ((hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) ||
764                 (hw->mac.type == e1000_pchlan)) {
765                 /* Check if SW needs to configure the PHY */
766                 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
767                     (hw->device_id == E1000_DEV_ID_ICH8_IGP_M) ||
768                     (hw->mac.type == e1000_pchlan))
769                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
770                 else
771                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
772
773                 data = er32(FEXTNVM);
774                 if (!(data & sw_cfg_mask))
775                         goto out;
776
777                 /* Wait for basic configuration completes before proceeding */
778                 e1000e_lan_init_done_ich8lan(hw);
779
780                 /*
781                  * Make sure HW does not configure LCD from PHY
782                  * extended configuration before SW configuration
783                  */
784                 data = er32(EXTCNF_CTRL);
785                 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
786                         goto out;
787
788                 cnf_size = er32(EXTCNF_SIZE);
789                 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
790                 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
791                 if (!cnf_size)
792                         goto out;
793
794                 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
795                 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
796
797                 if (!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
798                     (hw->mac.type == e1000_pchlan)) {
799                         /*
800                          * HW configures the SMBus address and LEDs when the
801                          * OEM and LCD Write Enable bits are set in the NVM.
802                          * When both NVM bits are cleared, SW will configure
803                          * them instead.
804                          */
805                         data = er32(STRAP);
806                         data &= E1000_STRAP_SMBUS_ADDRESS_MASK;
807                         reg_data = data >> E1000_STRAP_SMBUS_ADDRESS_SHIFT;
808                         reg_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
809                         ret_val = e1000e_write_phy_reg_hv_locked(hw, HV_SMB_ADDR,
810                                                                 reg_data);
811                         if (ret_val)
812                                 goto out;
813
814                         data = er32(LEDCTL);
815                         ret_val = e1000e_write_phy_reg_hv_locked(hw,
816                                                                 HV_LED_CONFIG,
817                                                                 (u16)data);
818                         if (ret_val)
819                                 goto out;
820                 }
821
822                 /* Configure LCD from extended configuration region. */
823
824                 /* cnf_base_addr is in DWORD */
825                 word_addr = (u16)(cnf_base_addr << 1);
826
827                 for (i = 0; i < cnf_size; i++) {
828                         ret_val = e1000e_read_nvm(hw, (word_addr + i * 2), 1,
829                                                    &reg_data);
830                         if (ret_val)
831                                 goto out;
832
833                         ret_val = e1000e_read_nvm(hw, (word_addr + i * 2 + 1),
834                                                    1, &reg_addr);
835                         if (ret_val)
836                                 goto out;
837
838                         /* Save off the PHY page for future writes. */
839                         if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
840                                 phy_page = reg_data;
841                                 continue;
842                         }
843
844                         reg_addr &= PHY_REG_MASK;
845                         reg_addr |= phy_page;
846
847                         ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
848                                                             reg_data);
849                         if (ret_val)
850                                 goto out;
851                 }
852         }
853
854 out:
855         hw->phy.ops.release(hw);
856         return ret_val;
857 }
858
859 /**
860  *  e1000e_k1_gig_workaround_hv - K1 Si workaround
861  *  @hw:   pointer to the HW structure
862  *  @link: link up bool flag
863  *
864  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
865  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
866  *  If link is down, the function will restore the default K1 setting located
867  *  in the NVM.
868  **/
869 static s32 e1000e_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
870 {
871         s32 ret_val = E1000_SUCCESS;
872         u16 status_reg = 0;
873         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
874
875         if (hw->mac.type != e1000_pchlan)
876                 goto out;
877
878         /* Wrap the whole flow with the sw flag */
879         ret_val = hw->phy.ops.acquire(hw);
880         if (ret_val)
881                 goto out;
882
883         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
884         if (link) {
885                 if (hw->phy.type == e1000_phy_82578) {
886                         ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
887                                                               &status_reg);
888                         if (ret_val)
889                                 goto release;
890
891                         status_reg &= BM_CS_STATUS_LINK_UP |
892                                       BM_CS_STATUS_RESOLVED |
893                                       BM_CS_STATUS_SPEED_MASK;
894
895                         if (status_reg == (BM_CS_STATUS_LINK_UP |
896                                            BM_CS_STATUS_RESOLVED |
897                                            BM_CS_STATUS_SPEED_1000))
898                                 k1_enable = false;
899                 }
900
901                 if (hw->phy.type == e1000_phy_82577) {
902                         ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
903                                                               &status_reg);
904                         if (ret_val)
905                                 goto release;
906
907                         status_reg &= HV_M_STATUS_LINK_UP |
908                                       HV_M_STATUS_AUTONEG_COMPLETE |
909                                       HV_M_STATUS_SPEED_MASK;
910
911                         if (status_reg == (HV_M_STATUS_LINK_UP |
912                                            HV_M_STATUS_AUTONEG_COMPLETE |
913                                            HV_M_STATUS_SPEED_1000))
914                                 k1_enable = false;
915                 }
916
917                 /* Link stall fix for link up */
918                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
919                                                        0x0100);
920                 if (ret_val)
921                         goto release;
922
923         } else {
924                 /* Link stall fix for link down */
925                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
926                                                        0x4100);
927                 if (ret_val)
928                         goto release;
929         }
930
931         ret_val = e1000e_configure_k1_ich8lan(hw, k1_enable);
932
933 release:
934         hw->phy.ops.release(hw);
935 out:
936         return ret_val;
937 }
938
939 /**
940  *  e1000e_configure_k1_ich8lan - Configure K1 power state
941  *  @hw: pointer to the HW structure
942  *  @enable: K1 state to configure
943  *
944  *  Configure the K1 power state based on the provided parameter.
945  *  Assumes semaphore already acquired.
946  *
947  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
948  **/
949 s32 e1000e_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
950 {
951         s32 ret_val = E1000_SUCCESS;
952         u32 ctrl_reg = 0;
953         u32 ctrl_ext = 0;
954         u32 reg = 0;
955         u16 kmrn_reg = 0;
956
957         ret_val = e1000e_read_kmrn_reg_locked(hw,
958                                              E1000_KMRNCTRLSTA_K1_CONFIG,
959                                              &kmrn_reg);
960         if (ret_val)
961                 goto out;
962
963         if (k1_enable)
964                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
965         else
966                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
967
968         ret_val = e1000e_write_kmrn_reg_locked(hw,
969                                               E1000_KMRNCTRLSTA_K1_CONFIG,
970                                               kmrn_reg);
971         if (ret_val)
972                 goto out;
973
974         udelay(20);
975         ctrl_ext = er32(CTRL_EXT);
976         ctrl_reg = er32(CTRL);
977
978         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
979         reg |= E1000_CTRL_FRCSPD;
980         ew32(CTRL, reg);
981
982         E1000_WRITE_REG(hw,
983                         E1000_CTRL_EXT,
984                         ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
985         udelay(20);
986         ew32(CTRL, ctrl_reg);
987         ew32(CTRL_EXT, ctrl_ext);
988         udelay(20);
989
990 out:
991         return ret_val;
992 }
993
994 /**
995  *  e1000e_oem_bits_config_ich8lan - SW-based LCD Configuration
996  *  @hw:       pointer to the HW structure
997  *  @d0_state: boolean if entering d0 or d3 device state
998  *
999  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1000  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
1001  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
1002  **/
1003 s32 e1000e_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1004 {
1005         s32 ret_val = 0;
1006         u32 mac_reg;
1007         u16 oem_reg;
1008
1009         if (hw->mac.type != e1000_pchlan)
1010                 return ret_val;
1011
1012         ret_val = hw->phy.ops.acquire(hw);
1013         if (ret_val)
1014                 return ret_val;
1015
1016         mac_reg = er32(EXTCNF_CTRL);
1017         if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1018                 goto out;
1019
1020         mac_reg = er32(FEXTNVM);
1021         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1022                 goto out;
1023
1024         mac_reg = er32(PHY_CTRL);
1025
1026         ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1027         if (ret_val)
1028                 goto out;
1029
1030         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1031
1032         if (d0_state) {
1033                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1034                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1035
1036                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1037                         oem_reg |= HV_OEM_BITS_LPLU;
1038         } else {
1039                 if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE)
1040                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1041
1042                 if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU)
1043                         oem_reg |= HV_OEM_BITS_LPLU;
1044         }
1045         /* Restart auto-neg to activate the bits */
1046         if (!e1000e_check_reset_block(hw))
1047                 oem_reg |= HV_OEM_BITS_RESTART_AN;
1048         ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
1049
1050 out:
1051         hw->phy.ops.release(hw);
1052
1053         return ret_val;
1054 }
1055
1056 /**
1057  *  e1000e_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1058  *  done after every PHY reset.
1059  **/
1060 static s32 e1000e_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1061 {
1062         s32 ret_val = E1000_SUCCESS;
1063
1064         if (hw->mac.type != e1000_pchlan)
1065                 goto out;
1066
1067         if (((hw->phy.type == e1000_phy_82577) &&
1068              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1069             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1070                 /* Disable generation of early preamble */
1071                 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1072                 if (ret_val)
1073                         goto out;
1074
1075                 /* Preamble tuning for SSC */
1076                 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
1077                 if (ret_val)
1078                         goto out;
1079         }
1080
1081         if (hw->phy.type == e1000_phy_82578) {
1082                 /*
1083                  * Return registers to default by doing a soft reset then
1084                  * writing 0x3140 to the control register.
1085                  */
1086                 if (hw->phy.revision < 2) {
1087                         e1000e_phy_sw_reset(hw);
1088                         ret_val = e1e_wphy(hw, PHY_CONTROL,
1089                                                         0x3140);
1090                 }
1091         }
1092
1093         /* Select page 0 */
1094         ret_val = hw->phy.ops.acquire(hw);
1095         if (ret_val)
1096                 goto out;
1097
1098         hw->phy.addr = 1;
1099         ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1100         if (ret_val)
1101                 goto out;
1102         hw->phy.ops.release(hw);
1103
1104         /*
1105          * Configure the K1 Si workaround during phy reset assuming there is
1106          * link so that it disables K1 if link is in 1Gbps.
1107          */
1108         ret_val = e1000e_k1_gig_workaround_hv(hw, true);
1109
1110 out:
1111         return ret_val;
1112 }
1113
1114 /**
1115  *  e1000e_lan_init_done_ich8lan - Check for PHY config completion
1116  *  @hw: pointer to the HW structure
1117  *
1118  *  Check the appropriate indication the MAC has finished configuring the
1119  *  PHY after a software reset.
1120  **/
1121 static void e1000e_lan_init_done_ich8lan(struct e1000_hw *hw)
1122 {
1123         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
1124
1125         /* Wait for basic configuration completes before proceeding */
1126         do {
1127                 data = er32(STATUS);
1128                 data &= E1000_STATUS_LAN_INIT_DONE;
1129                 udelay(100);
1130         } while ((!data) && --loop);
1131
1132         /*
1133          * If basic configuration is incomplete before the above loop
1134          * count reaches 0, loading the configuration from NVM will
1135          * leave the PHY in a bad state possibly resulting in no link.
1136          */
1137         if (loop == 0)
1138                 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
1139
1140         /* Clear the Init Done bit for the next init event */
1141         data = er32(STATUS);
1142         data &= ~E1000_STATUS_LAN_INIT_DONE;
1143         ew32(STATUS, data);
1144 }
1145
1146 /**
1147  *  e1000e_phy_hw_reset_ich8lan - Performs a PHY reset
1148  *  @hw: pointer to the HW structure
1149  *
1150  *  Resets the PHY
1151  *  This is a function pointer entry point called by drivers
1152  *  or other shared routines.
1153  **/
1154 static s32 e1000e_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1155 {
1156         s32 ret_val = E1000_SUCCESS;
1157         u16 reg;
1158
1159         ret_val = e1000e_phy_hw_reset_generic(hw);
1160         if (ret_val)
1161                 goto out;
1162
1163         /* Allow time for h/w to get to a quiescent state after reset */
1164         msleep(10);
1165
1166         if (hw->mac.type == e1000_pchlan) {
1167                 ret_val = e1000e_hv_phy_workarounds_ich8lan(hw);
1168                 if (ret_val)
1169                         goto out;
1170         }
1171
1172         /* Dummy read to clear the phy wakeup bit after lcd reset */
1173         if (hw->mac.type == e1000_pchlan)
1174                 e1e_rphy(hw, BM_WUC, &reg);
1175
1176         /* Configure the LCD with the extended configuration region in NVM */
1177         ret_val = e1000e_sw_lcd_config_ich8lan(hw);
1178         if (ret_val)
1179                 goto out;
1180
1181         /* Configure the LCD with the OEM bits in NVM */
1182         if (hw->mac.type == e1000_pchlan)
1183                 ret_val = e1000e_oem_bits_config_ich8lan(hw, true);
1184
1185 out:
1186         return ret_val;
1187 }
1188
1189 /**
1190  *  e1000e_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
1191  *  @hw: pointer to the HW structure
1192  *
1193  *  Wrapper for calling the get_phy_info routines for the appropriate phy type.
1194  **/
1195 static s32 e1000e_get_phy_info_ich8lan(struct e1000_hw *hw)
1196 {
1197         s32 ret_val = -E1000_ERR_PHY_TYPE;
1198
1199         switch (hw->phy.type) {
1200         case e1000_phy_ife:
1201                 ret_val = e1000e_get_phy_info_ife_ich8lan(hw);
1202                 break;
1203         case e1000_phy_igp_3:
1204         case e1000_phy_bm:
1205         case e1000_phy_82578:
1206         case e1000_phy_82577:
1207                 ret_val = e1000e_get_phy_info_igp(hw);
1208                 break;
1209         default:
1210                 break;
1211         }
1212
1213         return ret_val;
1214 }
1215
1216 /**
1217  *  e1000e_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states
1218  *  @hw: pointer to the HW structure
1219  *
1220  *  Populates "phy" structure with various feature states.
1221  *  This function is only called by other family-specific
1222  *  routines.
1223  **/
1224 static s32 e1000e_get_phy_info_ife_ich8lan(struct e1000_hw *hw)
1225 {
1226         struct e1000_phy_info *phy = &hw->phy;
1227         s32 ret_val;
1228         u16 data;
1229         bool link;
1230
1231         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1232         if (ret_val)
1233                 goto out;
1234
1235         if (!link) {
1236                 e_dbg("Phy info is only valid if link is up\n");
1237                 ret_val = -E1000_ERR_CONFIG;
1238                 goto out;
1239         }
1240
1241         ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
1242         if (ret_val)
1243                 goto out;
1244         phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE)
1245                                    ? false : true;
1246
1247         if (phy->polarity_correction) {
1248                 ret_val = e1000e_check_polarity_ife(hw);
1249                 if (ret_val)
1250                         goto out;
1251         } else {
1252                 /* Polarity is forced */
1253                 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
1254                                       ? e1000_rev_polarity_reversed
1255                                       : e1000_rev_polarity_normal;
1256         }
1257
1258         ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
1259         if (ret_val)
1260                 goto out;
1261
1262         phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? true : false;
1263
1264         /* The following parameters are undefined for 10/100 operation. */
1265         phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1266         phy->local_rx = e1000_1000t_rx_status_undefined;
1267         phy->remote_rx = e1000_1000t_rx_status_undefined;
1268
1269 out:
1270         return ret_val;
1271 }
1272
1273 /**
1274  *  e1000e_set_lplu_state_pchlan - Set Low Power Link Up state
1275  *  @hw: pointer to the HW structure
1276  *  @active: true to enable LPLU, false to disable
1277  *
1278  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
1279  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1280  *  the phy speed. This function will manually set the LPLU bit and restart
1281  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
1282  *  since it configures the same bit.
1283  **/
1284 static s32 e1000e_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1285 {
1286         s32 ret_val = E1000_SUCCESS;
1287         u16 oem_reg;
1288
1289         ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1290         if (ret_val)
1291                 goto out;
1292
1293         if (active)
1294                 oem_reg |= HV_OEM_BITS_LPLU;
1295         else
1296                 oem_reg &= ~HV_OEM_BITS_LPLU;
1297
1298         oem_reg |= HV_OEM_BITS_RESTART_AN;
1299         ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1300
1301 out:
1302         return ret_val;
1303 }
1304
1305 /**
1306  *  e1000e_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1307  *  @hw: pointer to the HW structure
1308  *  @active: true to enable LPLU, false to disable
1309  *
1310  *  Sets the LPLU D0 state according to the active flag.  When
1311  *  activating LPLU this function also disables smart speed
1312  *  and vice versa.  LPLU will not be activated unless the
1313  *  device autonegotiation advertisement meets standards of
1314  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1315  *  This is a function pointer entry point only called by
1316  *  PHY setup routines.
1317  **/
1318 static s32 e1000e_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1319 {
1320         struct e1000_phy_info *phy = &hw->phy;
1321         u32 phy_ctrl;
1322         s32 ret_val = E1000_SUCCESS;
1323         u16 data;
1324
1325         if (phy->type == e1000_phy_ife)
1326                 goto out;
1327
1328         phy_ctrl = er32(PHY_CTRL);
1329
1330         if (active) {
1331                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1332                 ew32(PHY_CTRL, phy_ctrl);
1333
1334                 if (phy->type != e1000_phy_igp_3)
1335                         goto out;
1336
1337                 /*
1338                  * Call gig speed drop workaround on LPLU before accessing
1339                  * any PHY registers
1340                  */
1341                 if (hw->mac.type == e1000_ich8lan)
1342                         e1000e_gig_downshift_workaround_ich8lan(hw);
1343
1344                 /* When LPLU is enabled, we should disable SmartSpeed */
1345                 ret_val = e1e_rphy(hw,
1346                                             IGP01E1000_PHY_PORT_CONFIG,
1347                                             &data);
1348                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1349                 ret_val = e1e_wphy(hw,
1350                                              IGP01E1000_PHY_PORT_CONFIG,
1351                                              data);
1352                 if (ret_val)
1353                         goto out;
1354         } else {
1355                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1356                 ew32(PHY_CTRL, phy_ctrl);
1357
1358                 if (phy->type != e1000_phy_igp_3)
1359                         goto out;
1360
1361                 /*
1362                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1363                  * during Dx states where the power conservation is most
1364                  * important.  During driver activity we should enable
1365                  * SmartSpeed, so performance is maintained.
1366                  */
1367                 if (phy->smart_speed == e1000_smart_speed_on) {
1368                         ret_val = e1e_rphy(hw,
1369                                                     IGP01E1000_PHY_PORT_CONFIG,
1370                                                     &data);
1371                         if (ret_val)
1372                                 goto out;
1373
1374                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1375                         ret_val = e1e_wphy(hw,
1376                                                      IGP01E1000_PHY_PORT_CONFIG,
1377                                                      data);
1378                         if (ret_val)
1379                                 goto out;
1380                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1381                         ret_val = e1e_rphy(hw,
1382                                                     IGP01E1000_PHY_PORT_CONFIG,
1383                                                     &data);
1384                         if (ret_val)
1385                                 goto out;
1386
1387                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1388                         ret_val = e1e_wphy(hw,
1389                                                      IGP01E1000_PHY_PORT_CONFIG,
1390                                                      data);
1391                         if (ret_val)
1392                                 goto out;
1393                 }
1394         }
1395
1396 out:
1397         return ret_val;
1398 }
1399
1400 /**
1401  *  e1000e_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1402  *  @hw: pointer to the HW structure
1403  *  @active: true to enable LPLU, false to disable
1404  *
1405  *  Sets the LPLU D3 state according to the active flag.  When
1406  *  activating LPLU this function also disables smart speed
1407  *  and vice versa.  LPLU will not be activated unless the
1408  *  device autonegotiation advertisement meets standards of
1409  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1410  *  This is a function pointer entry point only called by
1411  *  PHY setup routines.
1412  **/
1413 static s32 e1000e_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1414 {
1415         struct e1000_phy_info *phy = &hw->phy;
1416         u32 phy_ctrl;
1417         s32 ret_val = E1000_SUCCESS;
1418         u16 data;
1419
1420         phy_ctrl = er32(PHY_CTRL);
1421
1422         if (!active) {
1423                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
1424                 ew32(PHY_CTRL, phy_ctrl);
1425
1426                 if (phy->type != e1000_phy_igp_3)
1427                         goto out;
1428
1429                 /*
1430                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1431                  * during Dx states where the power conservation is most
1432                  * important.  During driver activity we should enable
1433                  * SmartSpeed, so performance is maintained.
1434                  */
1435                 if (phy->smart_speed == e1000_smart_speed_on) {
1436                         ret_val = e1e_rphy(hw,
1437                                                     IGP01E1000_PHY_PORT_CONFIG,
1438                                                     &data);
1439                         if (ret_val)
1440                                 goto out;
1441
1442                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1443                         ret_val = e1e_wphy(hw,
1444                                                      IGP01E1000_PHY_PORT_CONFIG,
1445                                                      data);
1446                         if (ret_val)
1447                                 goto out;
1448                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1449                         ret_val = e1e_rphy(hw,
1450                                                     IGP01E1000_PHY_PORT_CONFIG,
1451                                                     &data);
1452                         if (ret_val)
1453                                 goto out;
1454
1455                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1456                         ret_val = e1e_wphy(hw,
1457                                                      IGP01E1000_PHY_PORT_CONFIG,
1458                                                      data);
1459                         if (ret_val)
1460                                 goto out;
1461                 }
1462         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1463                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1464                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1465                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
1466                 ew32(PHY_CTRL, phy_ctrl);
1467
1468                 if (phy->type != e1000_phy_igp_3)
1469                         goto out;
1470
1471                 /*
1472                  * Call gig speed drop workaround on LPLU before accessing
1473                  * any PHY registers
1474                  */
1475                 if (hw->mac.type == e1000_ich8lan)
1476                         e1000e_gig_downshift_workaround_ich8lan(hw);
1477
1478                 /* When LPLU is enabled, we should disable SmartSpeed */
1479                 ret_val = e1e_rphy(hw,
1480                                             IGP01E1000_PHY_PORT_CONFIG,
1481                                             &data);
1482                 if (ret_val)
1483                         goto out;
1484
1485                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1486                 ret_val = e1e_wphy(hw,
1487                                              IGP01E1000_PHY_PORT_CONFIG,
1488                                              data);
1489         }
1490
1491 out:
1492         return ret_val;
1493 }
1494
1495 /**
1496  *  e1000e_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
1497  *  @hw: pointer to the HW structure
1498  *  @bank:  pointer to the variable that returns the active bank
1499  *
1500  *  Reads signature byte from the NVM using the flash access registers.
1501  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
1502  **/
1503 static s32 e1000e_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
1504 {
1505         u32 eecd;
1506         struct e1000_nvm_info *nvm = &hw->nvm;
1507         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
1508         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
1509         u8 sig_byte = 0;
1510         s32 ret_val = E1000_SUCCESS;
1511
1512         switch (hw->mac.type) {
1513         case e1000_ich8lan:
1514         case e1000_ich9lan:
1515                 eecd = er32(EECD);
1516                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
1517                     E1000_EECD_SEC1VAL_VALID_MASK) {
1518                         if (eecd & E1000_EECD_SEC1VAL)
1519                                 *bank = 1;
1520                         else
1521                                 *bank = 0;
1522
1523                         goto out;
1524                 }
1525                 e_dbg("Unable to determine valid NVM bank via EEC - "
1526                          "reading flash signature\n");
1527                 /* fall-thru */
1528         default:
1529                 /* set bank to 0 in case flash read fails */
1530                 *bank = 0;
1531
1532                 /* Check bank 0 */
1533                 ret_val = e1000e_read_flash_byte_ich8lan(hw, act_offset,
1534                                                         &sig_byte);
1535                 if (ret_val)
1536                         goto out;
1537                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1538                     E1000_ICH_NVM_SIG_VALUE) {
1539                         *bank = 0;
1540                         goto out;
1541                 }
1542
1543                 /* Check bank 1 */
1544                 ret_val = e1000e_read_flash_byte_ich8lan(hw, act_offset +
1545                                                         bank1_offset,
1546                                                         &sig_byte);
1547                 if (ret_val)
1548                         goto out;
1549                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1550                     E1000_ICH_NVM_SIG_VALUE) {
1551                         *bank = 1;
1552                         goto out;
1553                 }
1554
1555                 e_dbg("ERROR: No valid NVM bank present\n");
1556                 ret_val = -E1000_ERR_NVM;
1557                 break;
1558         }
1559 out:
1560         return ret_val;
1561 }
1562
1563 /**
1564  *  e1000e_read_nvm_ich8lan - Read word(s) from the NVM
1565  *  @hw: pointer to the HW structure
1566  *  @offset: The offset (in bytes) of the word(s) to read.
1567  *  @words: Size of data to read in words
1568  *  @data: Pointer to the word(s) to read at offset.
1569  *
1570  *  Reads a word(s) from the NVM using the flash access registers.
1571  **/
1572 static s32 e1000e_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1573                                   u16 *data)
1574 {
1575         struct e1000_nvm_info *nvm = &hw->nvm;
1576         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1577         u32 act_offset;
1578         s32 ret_val = E1000_SUCCESS;
1579         u32 bank = 0;
1580         u16 i, word;
1581
1582         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1583             (words == 0)) {
1584                 e_dbg("nvm parameter(s) out of bounds\n");
1585                 ret_val = -E1000_ERR_NVM;
1586                 goto out;
1587         }
1588
1589         nvm->ops.acquire(hw);
1590
1591         ret_val = e1000e_valid_nvm_bank_detect_ich8lan(hw, &bank);
1592         if (ret_val != E1000_SUCCESS) {
1593                 e_dbg("Could not detect valid bank, assuming bank 0\n");
1594                 bank = 0;
1595         }
1596
1597         act_offset = (bank) ? nvm->flash_bank_size : 0;
1598         act_offset += offset;
1599
1600         ret_val = E1000_SUCCESS;
1601         for (i = 0; i < words; i++) {
1602                 if ((dev_spec->shadow_ram) &&
1603                     (dev_spec->shadow_ram[offset+i].modified)) {
1604                         data[i] = dev_spec->shadow_ram[offset+i].value;
1605                 } else {
1606                         ret_val = e1000e_read_flash_word_ich8lan(hw,
1607                                                                 act_offset + i,
1608                                                                 &word);
1609                         if (ret_val)
1610                                 break;
1611                         data[i] = word;
1612                 }
1613         }
1614
1615         nvm->ops.release(hw);
1616
1617 out:
1618         if (ret_val)
1619                 e_dbg("NVM read error: %d\n", ret_val);
1620
1621         return ret_val;
1622 }
1623
1624 /**
1625  *  e1000e_flash_cycle_init_ich8lan - Initialize flash
1626  *  @hw: pointer to the HW structure
1627  *
1628  *  This function does initial flash setup so that a new read/write/erase cycle
1629  *  can be started.
1630  **/
1631 static s32 e1000e_flash_cycle_init_ich8lan(struct e1000_hw *hw)
1632 {
1633         union ich8_hws_flash_status hsfsts;
1634         s32 ret_val = -E1000_ERR_NVM;
1635         s32 i = 0;
1636
1637         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1638
1639         /* Check if the flash descriptor is valid */
1640         if (hsfsts.hsf_status.fldesvalid == 0) {
1641                 e_dbg("Flash descriptor invalid.  "
1642                          "SW Sequencing must be used.");
1643                 goto out;
1644         }
1645
1646         /* Clear FCERR and DAEL in hw status by writing 1 */
1647         hsfsts.hsf_status.flcerr = 1;
1648         hsfsts.hsf_status.dael = 1;
1649
1650         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1651
1652         /*
1653          * Either we should have a hardware SPI cycle in progress
1654          * bit to check against, in order to start a new cycle or
1655          * FDONE bit should be changed in the hardware so that it
1656          * is 1 after hardware reset, which can then be used as an
1657          * indication whether a cycle is in progress or has been
1658          * completed.
1659          */
1660
1661         if (hsfsts.hsf_status.flcinprog == 0) {
1662                 /*
1663                  * There is no cycle running at present,
1664                  * so we can start a cycle.
1665                  * Begin by setting Flash Cycle Done.
1666                  */
1667                 hsfsts.hsf_status.flcdone = 1;
1668                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1669                 ret_val = E1000_SUCCESS;
1670         } else {
1671                 /*
1672                  * Otherwise poll for sometime so the current
1673                  * cycle has a chance to end before giving up.
1674                  */
1675                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
1676                         hsfsts.regval = er16flash(
1677                                                               ICH_FLASH_HSFSTS);
1678                         if (hsfsts.hsf_status.flcinprog == 0) {
1679                                 ret_val = E1000_SUCCESS;
1680                                 break;
1681                         }
1682                         udelay(1);
1683                 }
1684                 if (ret_val == E1000_SUCCESS) {
1685                         /*
1686                          * Successful in waiting for previous cycle to timeout,
1687                          * now set the Flash Cycle Done.
1688                          */
1689                         hsfsts.hsf_status.flcdone = 1;
1690                         ew16flash(ICH_FLASH_HSFSTS,
1691                                                 hsfsts.regval);
1692                 } else {
1693                         e_dbg("Flash controller busy, cannot get access");
1694                 }
1695         }
1696
1697 out:
1698         return ret_val;
1699 }
1700
1701 /**
1702  *  e1000e_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1703  *  @hw: pointer to the HW structure
1704  *  @timeout: maximum time to wait for completion
1705  *
1706  *  This function starts a flash cycle and waits for its completion.
1707  **/
1708 static s32 e1000e_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
1709 {
1710         union ich8_hws_flash_ctrl hsflctl;
1711         union ich8_hws_flash_status hsfsts;
1712         s32 ret_val = -E1000_ERR_NVM;
1713         u32 i = 0;
1714
1715         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
1716         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1717         hsflctl.hsf_ctrl.flcgo = 1;
1718         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1719
1720         /* wait till FDONE bit is set to 1 */
1721         do {
1722                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1723                 if (hsfsts.hsf_status.flcdone == 1)
1724                         break;
1725                 udelay(1);
1726         } while (i++ < timeout);
1727
1728         if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
1729                 ret_val = E1000_SUCCESS;
1730
1731         return ret_val;
1732 }
1733
1734 /**
1735  *  e1000e_read_flash_word_ich8lan - Read word from flash
1736  *  @hw: pointer to the HW structure
1737  *  @offset: offset to data location
1738  *  @data: pointer to the location for storing the data
1739  *
1740  *  Reads the flash word at offset into data.  Offset is converted
1741  *  to bytes before read.
1742  **/
1743 static s32 e1000e_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
1744                                          u16 *data)
1745 {
1746         s32 ret_val;
1747
1748         if (!data) {
1749                 ret_val = -E1000_ERR_NVM;
1750                 goto out;
1751         }
1752
1753         /* Must convert offset into bytes. */
1754         offset <<= 1;
1755
1756         ret_val = e1000e_read_flash_data_ich8lan(hw, offset, 2, data);
1757
1758 out:
1759         return ret_val;
1760 }
1761
1762 /**
1763  *  e1000e_read_flash_byte_ich8lan - Read byte from flash
1764  *  @hw: pointer to the HW structure
1765  *  @offset: The offset of the byte to read.
1766  *  @data: Pointer to a byte to store the value read.
1767  *
1768  *  Reads a single byte from the NVM using the flash access registers.
1769  **/
1770 static s32 e1000e_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1771                                          u8 *data)
1772 {
1773         s32 ret_val = E1000_SUCCESS;
1774         u16 word = 0;
1775
1776         ret_val = e1000e_read_flash_data_ich8lan(hw, offset, 1, &word);
1777         if (ret_val)
1778                 goto out;
1779
1780         *data = (u8)word;
1781
1782 out:
1783         return ret_val;
1784 }
1785
1786 /**
1787  *  e1000e_read_flash_data_ich8lan - Read byte or word from NVM
1788  *  @hw: pointer to the HW structure
1789  *  @offset: The offset (in bytes) of the byte or word to read.
1790  *  @size: Size of data to read, 1=byte 2=word
1791  *  @data: Pointer to the word to store the value read.
1792  *
1793  *  Reads a byte or word from the NVM using the flash access registers.
1794  **/
1795 static s32 e1000e_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1796                                          u8 size, u16 *data)
1797 {
1798         union ich8_hws_flash_status hsfsts;
1799         union ich8_hws_flash_ctrl hsflctl;
1800         u32 flash_linear_addr;
1801         u32 flash_data = 0;
1802         s32 ret_val = -E1000_ERR_NVM;
1803         u8 count = 0;
1804
1805         if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
1806                 goto out;
1807         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1808                             hw->nvm.flash_base_addr;
1809
1810         do {
1811                 udelay(1);
1812                 /* Steps */
1813                 ret_val = e1000e_flash_cycle_init_ich8lan(hw);
1814                 if (ret_val != E1000_SUCCESS)
1815                         break;
1816
1817                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1818                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1819                 hsflctl.hsf_ctrl.fldbcount = size - 1;
1820                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
1821                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1822
1823                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1824
1825                 ret_val = e1000e_flash_cycle_ich8lan(hw,
1826                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
1827
1828                 /*
1829                  * Check if FCERR is set to 1, if set to 1, clear it
1830                  * and try the whole sequence a few more times, else
1831                  * read in (shift in) the Flash Data0, the order is
1832                  * least significant byte first msb to lsb
1833                  */
1834                 if (ret_val == E1000_SUCCESS) {
1835                         flash_data = er32flash(ICH_FLASH_FDATA0);
1836                         if (size == 1)
1837                                 *data = (u8)(flash_data & 0x000000FF);
1838                         else if (size == 2)
1839                                 *data = (u16)(flash_data & 0x0000FFFF);
1840                         break;
1841                 } else {
1842                         /*
1843                          * If we've gotten here, then things are probably
1844                          * completely hosed, but if the error condition is
1845                          * detected, it won't hurt to give it another try...
1846                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1847                          */
1848                         hsfsts.regval = er16flash(
1849                                                               ICH_FLASH_HSFSTS);
1850                         if (hsfsts.hsf_status.flcerr == 1) {
1851                                 /* Repeat for some time before giving up. */
1852                                 continue;
1853                         } else if (hsfsts.hsf_status.flcdone == 0) {
1854                                 e_dbg("Timeout error - flash cycle "
1855                                          "did not complete.");
1856                                 break;
1857                         }
1858                 }
1859         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1860
1861 out:
1862         return ret_val;
1863 }
1864
1865 /**
1866  *  e1000e_write_nvm_ich8lan - Write word(s) to the NVM
1867  *  @hw: pointer to the HW structure
1868  *  @offset: The offset (in bytes) of the word(s) to write.
1869  *  @words: Size of data to write in words
1870  *  @data: Pointer to the word(s) to write at offset.
1871  *
1872  *  Writes a byte or word to the NVM using the flash access registers.
1873  **/
1874 static s32 e1000e_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1875                                    u16 *data)
1876 {
1877         struct e1000_nvm_info *nvm = &hw->nvm;
1878         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1879         s32 ret_val = E1000_SUCCESS;
1880         u16 i;
1881
1882         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1883             (words == 0)) {
1884                 e_dbg("nvm parameter(s) out of bounds\n");
1885                 ret_val = -E1000_ERR_NVM;
1886                 goto out;
1887         }
1888
1889         nvm->ops.acquire(hw);
1890
1891         for (i = 0; i < words; i++) {
1892                 dev_spec->shadow_ram[offset+i].modified = true;
1893                 dev_spec->shadow_ram[offset+i].value = data[i];
1894         }
1895
1896         nvm->ops.release(hw);
1897
1898 out:
1899         return ret_val;
1900 }
1901
1902 /**
1903  *  e1000e_update_nvm_checksum_ich8lan - Update the checksum for NVM
1904  *  @hw: pointer to the HW structure
1905  *
1906  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
1907  *  which writes the checksum to the shadow ram.  The changes in the shadow
1908  *  ram are then committed to the EEPROM by processing each bank at a time
1909  *  checking for the modified bit and writing only the pending changes.
1910  *  After a successful commit, the shadow ram is cleared and is ready for
1911  *  future writes.
1912  **/
1913 static s32 e1000e_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
1914 {
1915         struct e1000_nvm_info *nvm = &hw->nvm;
1916         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1917         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
1918         s32 ret_val;
1919         u16 data;
1920
1921         ret_val = e1000e_update_nvm_checksum_generic(hw);
1922         if (ret_val)
1923                 goto out;
1924
1925         if (nvm->type != e1000_nvm_flash_sw)
1926                 goto out;
1927
1928         nvm->ops.acquire(hw);
1929
1930         /*
1931          * We're writing to the opposite bank so if we're on bank 1,
1932          * write to bank 0 etc.  We also need to erase the segment that
1933          * is going to be written
1934          */
1935         ret_val =  e1000e_valid_nvm_bank_detect_ich8lan(hw, &bank);
1936         if (ret_val != E1000_SUCCESS) {
1937                 e_dbg("Could not detect valid bank, assuming bank 0\n");
1938                 bank = 0;
1939         }
1940
1941         if (bank == 0) {
1942                 new_bank_offset = nvm->flash_bank_size;
1943                 old_bank_offset = 0;
1944                 ret_val = e1000e_erase_flash_bank_ich8lan(hw, 1);
1945                 if (ret_val) {
1946                         nvm->ops.release(hw);
1947                         goto out;
1948                 }
1949         } else {
1950                 old_bank_offset = nvm->flash_bank_size;
1951                 new_bank_offset = 0;
1952                 ret_val = e1000e_erase_flash_bank_ich8lan(hw, 0);
1953                 if (ret_val) {
1954                         nvm->ops.release(hw);
1955                         goto out;
1956                 }
1957         }
1958
1959         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
1960                 /*
1961                  * Determine whether to write the value stored
1962                  * in the other NVM bank or a modified value stored
1963                  * in the shadow RAM
1964                  */
1965                 if (dev_spec->shadow_ram[i].modified) {
1966                         data = dev_spec->shadow_ram[i].value;
1967                 } else {
1968                         ret_val = e1000e_read_flash_word_ich8lan(hw, i +
1969                                                                 old_bank_offset,
1970                                                                 &data);
1971                         if (ret_val)
1972                                 break;
1973                 }
1974
1975                 /*
1976                  * If the word is 0x13, then make sure the signature bits
1977                  * (15:14) are 11b until the commit has completed.
1978                  * This will allow us to write 10b which indicates the
1979                  * signature is valid.  We want to do this after the write
1980                  * has completed so that we don't mark the segment valid
1981                  * while the write is still in progress
1982                  */
1983                 if (i == E1000_ICH_NVM_SIG_WORD)
1984                         data |= E1000_ICH_NVM_SIG_MASK;
1985
1986                 /* Convert offset to bytes. */
1987                 act_offset = (i + new_bank_offset) << 1;
1988
1989                 udelay(100);
1990                 /* Write the bytes to the new bank. */
1991                 ret_val = e1000e_retry_write_flash_byte_ich8lan(hw,
1992                                                                act_offset,
1993                                                                (u8)data);
1994                 if (ret_val)
1995                         break;
1996
1997                 udelay(100);
1998                 ret_val = e1000e_retry_write_flash_byte_ich8lan(hw,
1999                                                           act_offset + 1,
2000                                                           (u8)(data >> 8));
2001                 if (ret_val)
2002                         break;
2003         }
2004
2005         /*
2006          * Don't bother writing the segment valid bits if sector
2007          * programming failed.
2008          */
2009         if (ret_val) {
2010                 e_dbg("Flash commit failed.\n");
2011                 nvm->ops.release(hw);
2012                 goto out;
2013         }
2014
2015         /*
2016          * Finally validate the new segment by setting bit 15:14
2017          * to 10b in word 0x13 , this can be done without an
2018          * erase as well since these bits are 11 to start with
2019          * and we need to change bit 14 to 0b
2020          */
2021         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2022         ret_val = e1000e_read_flash_word_ich8lan(hw, act_offset, &data);
2023         if (ret_val) {
2024                 nvm->ops.release(hw);
2025                 goto out;
2026         }
2027
2028         data &= 0xBFFF;
2029         ret_val = e1000e_retry_write_flash_byte_ich8lan(hw,
2030                                                        act_offset * 2 + 1,
2031                                                        (u8)(data >> 8));
2032         if (ret_val) {
2033                 nvm->ops.release(hw);
2034                 goto out;
2035         }
2036
2037         /*
2038          * And invalidate the previously valid segment by setting
2039          * its signature word (0x13) high_byte to 0b. This can be
2040          * done without an erase because flash erase sets all bits
2041          * to 1's. We can write 1's to 0's without an erase
2042          */
2043         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2044         ret_val = e1000e_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2045         if (ret_val) {
2046                 nvm->ops.release(hw);
2047                 goto out;
2048         }
2049
2050         /* Great!  Everything worked, we can now clear the cached entries. */
2051         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2052                 dev_spec->shadow_ram[i].modified = false;
2053                 dev_spec->shadow_ram[i].value = 0xFFFF;
2054         }
2055
2056         nvm->ops.release(hw);
2057
2058         /*
2059          * Reload the EEPROM, or else modifications will not appear
2060          * until after the next adapter reset.
2061          */
2062         nvm->ops.reload(hw);
2063         msleep(10);
2064
2065 out:
2066         if (ret_val)
2067                 e_dbg("NVM update error: %d\n", ret_val);
2068
2069         return ret_val;
2070 }
2071
2072 /**
2073  *  e1000e_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2074  *  @hw: pointer to the HW structure
2075  *
2076  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2077  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
2078  *  calculated, in which case we need to calculate the checksum and set bit 6.
2079  **/
2080 static s32 e1000e_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2081 {
2082         s32 ret_val = E1000_SUCCESS;
2083         u16 data;
2084
2085         /*
2086          * Read 0x19 and check bit 6.  If this bit is 0, the checksum
2087          * needs to be fixed.  This bit is an indication that the NVM
2088          * was prepared by OEM software and did not calculate the
2089          * checksum...a likely scenario.
2090          */
2091         ret_val = e1000e_read_nvm(hw, 0x19, 1, &data);
2092         if (ret_val)
2093                 goto out;
2094
2095         if ((data & 0x40) == 0) {
2096                 data |= 0x40;
2097                 ret_val = e1000e_write_nvm(hw, 0x19, 1, &data);
2098                 if (ret_val)
2099                         goto out;
2100                 ret_val = e1000e_update_nvm_checksum(hw);
2101                 if (ret_val)
2102                         goto out;
2103         }
2104
2105         ret_val = e1000e_validate_nvm_checksum_generic(hw);
2106
2107 out:
2108         return ret_val;
2109 }
2110
2111 /**
2112  *  e1000e_write_flash_data_ich8lan - Writes bytes to the NVM
2113  *  @hw: pointer to the HW structure
2114  *  @offset: The offset (in bytes) of the byte/word to read.
2115  *  @size: Size of data to read, 1=byte 2=word
2116  *  @data: The byte(s) to write to the NVM.
2117  *
2118  *  Writes one/two bytes to the NVM using the flash access registers.
2119  **/
2120 static s32 e1000e_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2121                                           u8 size, u16 data)
2122 {
2123         union ich8_hws_flash_status hsfsts;
2124         union ich8_hws_flash_ctrl hsflctl;
2125         u32 flash_linear_addr;
2126         u32 flash_data = 0;
2127         s32 ret_val = -E1000_ERR_NVM;
2128         u8 count = 0;
2129
2130         if (size < 1 || size > 2 || data > size * 0xff ||
2131             offset > ICH_FLASH_LINEAR_ADDR_MASK)
2132                 goto out;
2133
2134         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2135                             hw->nvm.flash_base_addr;
2136
2137         do {
2138                 udelay(1);
2139                 /* Steps */
2140                 ret_val = e1000e_flash_cycle_init_ich8lan(hw);
2141                 if (ret_val != E1000_SUCCESS)
2142                         break;
2143
2144                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2145                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2146                 hsflctl.hsf_ctrl.fldbcount = size - 1;
2147                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
2148                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2149
2150                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2151
2152                 if (size == 1)
2153                         flash_data = (u32)data & 0x00FF;
2154                 else
2155                         flash_data = (u32)data;
2156
2157                 ew32flash(ICH_FLASH_FDATA0, flash_data);
2158
2159                 /*
2160                  * check if FCERR is set to 1 , if set to 1, clear it
2161                  * and try the whole sequence a few more times else done
2162                  */
2163                 ret_val = e1000e_flash_cycle_ich8lan(hw,
2164                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2165                 if (ret_val == E1000_SUCCESS)
2166                         break;
2167
2168                 /*
2169                  * If we're here, then things are most likely
2170                  * completely hosed, but if the error condition
2171                  * is detected, it won't hurt to give it another
2172                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2173                  */
2174                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2175                 if (hsfsts.hsf_status.flcerr == 1) {
2176                         /* Repeat for some time before giving up. */
2177                         continue;
2178                 } else if (hsfsts.hsf_status.flcdone == 0) {
2179                         e_dbg("Timeout error - flash cycle "
2180                                  "did not complete.");
2181                         break;
2182                 }
2183         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2184
2185 out:
2186         return ret_val;
2187 }
2188
2189 /**
2190  *  e1000e_write_flash_byte_ich8lan - Write a single byte to NVM
2191  *  @hw: pointer to the HW structure
2192  *  @offset: The index of the byte to read.
2193  *  @data: The byte to write to the NVM.
2194  *
2195  *  Writes a single byte to the NVM using the flash access registers.
2196  **/
2197 static s32 e1000e_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2198                                           u8 data)
2199 {
2200         u16 word = (u16)data;
2201
2202         return e1000e_write_flash_data_ich8lan(hw, offset, 1, word);
2203 }
2204
2205 /**
2206  *  e1000e_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2207  *  @hw: pointer to the HW structure
2208  *  @offset: The offset of the byte to write.
2209  *  @byte: The byte to write to the NVM.
2210  *
2211  *  Writes a single byte to the NVM using the flash access registers.
2212  *  Goes through a retry algorithm before giving up.
2213  **/
2214 static s32 e1000e_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2215                                                 u32 offset, u8 byte)
2216 {
2217         s32 ret_val;
2218         u16 program_retries;
2219
2220         ret_val = e1000e_write_flash_byte_ich8lan(hw, offset, byte);
2221         if (ret_val == E1000_SUCCESS)
2222                 goto out;
2223
2224         for (program_retries = 0; program_retries < 100; program_retries++) {
2225                 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
2226                 udelay(100);
2227                 ret_val = e1000e_write_flash_byte_ich8lan(hw, offset, byte);
2228                 if (ret_val == E1000_SUCCESS)
2229                         break;
2230         }
2231         if (program_retries == 100) {
2232                 ret_val = -E1000_ERR_NVM;
2233                 goto out;
2234         }
2235
2236 out:
2237         return ret_val;
2238 }
2239
2240 /**
2241  *  e1000e_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2242  *  @hw: pointer to the HW structure
2243  *  @bank: 0 for first bank, 1 for second bank, etc.
2244  *
2245  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2246  *  bank N is 4096 * N + flash_reg_addr.
2247  **/
2248 static s32 e1000e_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2249 {
2250         struct e1000_nvm_info *nvm = &hw->nvm;
2251         union ich8_hws_flash_status hsfsts;
2252         union ich8_hws_flash_ctrl hsflctl;
2253         u32 flash_linear_addr;
2254         /* bank size is in 16bit words - adjust to bytes */
2255         u32 flash_bank_size = nvm->flash_bank_size * 2;
2256         s32 ret_val = E1000_SUCCESS;
2257         s32 count = 0;
2258         s32 j, iteration, sector_size;
2259
2260         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2261
2262         /*
2263          * Determine HW Sector size: Read BERASE bits of hw flash status
2264          * register
2265          * 00: The Hw sector is 256 bytes, hence we need to erase 16
2266          *     consecutive sectors.  The start index for the nth Hw sector
2267          *     can be calculated as = bank * 4096 + n * 256
2268          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2269          *     The start index for the nth Hw sector can be calculated
2270          *     as = bank * 4096
2271          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2272          *     (ich9 only, otherwise error condition)
2273          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2274          */
2275         switch (hsfsts.hsf_status.berasesz) {
2276         case 0:
2277                 /* Hw sector size 256 */
2278                 sector_size = ICH_FLASH_SEG_SIZE_256;
2279                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2280                 break;
2281         case 1:
2282                 sector_size = ICH_FLASH_SEG_SIZE_4K;
2283                 iteration = 1;
2284                 break;
2285         case 2:
2286                 sector_size = ICH_FLASH_SEG_SIZE_8K;
2287                 iteration = 1;
2288                 break;
2289         case 3:
2290                 sector_size = ICH_FLASH_SEG_SIZE_64K;
2291                 iteration = 1;
2292                 break;
2293         default:
2294                 ret_val = -E1000_ERR_NVM;
2295                 goto out;
2296         }
2297
2298         /* Start with the base address, then add the sector offset. */
2299         flash_linear_addr = hw->nvm.flash_base_addr;
2300         flash_linear_addr += (bank) ? flash_bank_size : 0;
2301
2302         for (j = 0; j < iteration ; j++) {
2303                 do {
2304                         /* Steps */
2305                         ret_val = e1000e_flash_cycle_init_ich8lan(hw);
2306                         if (ret_val)
2307                                 goto out;
2308
2309                         /*
2310                          * Write a value 11 (block Erase) in Flash
2311                          * Cycle field in hw flash control
2312                          */
2313                         hsflctl.regval = er16flash(
2314                                                               ICH_FLASH_HSFCTL);
2315                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2316                         ew16flash(ICH_FLASH_HSFCTL,
2317                                                 hsflctl.regval);
2318
2319                         /*
2320                          * Write the last 24 bits of an index within the
2321                          * block into Flash Linear address field in Flash
2322                          * Address.
2323                          */
2324                         flash_linear_addr += (j * sector_size);
2325                         ew32flash(ICH_FLASH_FADDR,
2326                                               flash_linear_addr);
2327
2328                         ret_val = e1000e_flash_cycle_ich8lan(hw,
2329                                                ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2330                         if (ret_val == E1000_SUCCESS)
2331                                 break;
2332
2333                         /*
2334                          * Check if FCERR is set to 1.  If 1,
2335                          * clear it and try the whole sequence
2336                          * a few more times else Done
2337                          */
2338                         hsfsts.regval = er16flash(
2339                                                       ICH_FLASH_HSFSTS);
2340                         if (hsfsts.hsf_status.flcerr == 1)
2341                                 /* repeat for some time before giving up */
2342                                 continue;
2343                         else if (hsfsts.hsf_status.flcdone == 0)
2344                                 goto out;
2345                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2346         }
2347
2348 out:
2349         return ret_val;
2350 }
2351
2352 /**
2353  *  e1000e_valid_led_default_ich8lan - Set the default LED settings
2354  *  @hw: pointer to the HW structure
2355  *  @data: Pointer to the LED settings
2356  *
2357  *  Reads the LED default settings from the NVM to data.  If the NVM LED
2358  *  settings is all 0's or F's, set the LED default to a valid LED default
2359  *  setting.
2360  **/
2361 static s32 e1000e_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2362 {
2363         s32 ret_val;
2364
2365         ret_val = e1000e_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2366         if (ret_val) {
2367                 e_dbg("NVM Read Error\n");
2368                 goto out;
2369         }
2370
2371         if (*data == ID_LED_RESERVED_0000 ||
2372             *data == ID_LED_RESERVED_FFFF)
2373                 *data = ID_LED_DEFAULT_ICH8LAN;
2374
2375 out:
2376         return ret_val;
2377 }
2378
2379 /**
2380  *  e1000e_id_led_init_pchlan - store LED configurations
2381  *  @hw: pointer to the HW structure
2382  *
2383  *  PCH does not control LEDs via the LEDCTL register, rather it uses
2384  *  the PHY LED configuration register.
2385  *
2386  *  PCH also does not have an "always on" or "always off" mode which
2387  *  complicates the ID feature.  Instead of using the "on" mode to indicate
2388  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2389  *  use "link_up" mode.  The LEDs will still ID on request if there is no
2390  *  link based on logic in e1000e_led_[on|off]_pchlan().
2391  **/
2392 static s32 e1000e_id_led_init_pchlan(struct e1000_hw *hw)
2393 {
2394         struct e1000_mac_info *mac = &hw->mac;
2395         s32 ret_val;
2396         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2397         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2398         u16 data, i, temp, shift;
2399
2400         /* Get default ID LED modes */
2401         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2402         if (ret_val)
2403                 goto out;
2404
2405         mac->ledctl_default = er32(LEDCTL);
2406         mac->ledctl_mode1 = mac->ledctl_default;
2407         mac->ledctl_mode2 = mac->ledctl_default;
2408
2409         for (i = 0; i < 4; i++) {
2410                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2411                 shift = (i * 5);
2412                 switch (temp) {
2413                 case ID_LED_ON1_DEF2:
2414                 case ID_LED_ON1_ON2:
2415                 case ID_LED_ON1_OFF2:
2416                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2417                         mac->ledctl_mode1 |= (ledctl_on << shift);
2418                         break;
2419                 case ID_LED_OFF1_DEF2:
2420                 case ID_LED_OFF1_ON2:
2421                 case ID_LED_OFF1_OFF2:
2422                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2423                         mac->ledctl_mode1 |= (ledctl_off << shift);
2424                         break;
2425                 default:
2426                         /* Do nothing */
2427                         break;
2428                 }
2429                 switch (temp) {
2430                 case ID_LED_DEF1_ON2:
2431                 case ID_LED_ON1_ON2:
2432                 case ID_LED_OFF1_ON2:
2433                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2434                         mac->ledctl_mode2 |= (ledctl_on << shift);
2435                         break;
2436                 case ID_LED_DEF1_OFF2:
2437                 case ID_LED_ON1_OFF2:
2438                 case ID_LED_OFF1_OFF2:
2439                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2440                         mac->ledctl_mode2 |= (ledctl_off << shift);
2441                         break;
2442                 default:
2443                         /* Do nothing */
2444                         break;
2445                 }
2446         }
2447
2448 out:
2449         return ret_val;
2450 }
2451
2452 /**
2453  *  e1000e_get_bus_info_ich8lan - Get/Set the bus type and width
2454  *  @hw: pointer to the HW structure
2455  *
2456  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2457  *  register, so the the bus width is hard coded.
2458  **/
2459 static s32 e1000e_get_bus_info_ich8lan(struct e1000_hw *hw)
2460 {
2461         struct e1000_bus_info *bus = &hw->bus;
2462         s32 ret_val;
2463
2464         ret_val = e1000e_get_bus_info_pcie(hw);
2465
2466         /*
2467          * ICH devices are "PCI Express"-ish.  They have
2468          * a configuration space, but do not contain
2469          * PCI Express Capability registers, so bus width
2470          * must be hardcoded.
2471          */
2472         if (bus->width == e1000_bus_width_unknown)
2473                 bus->width = e1000_bus_width_pcie_x1;
2474
2475         return ret_val;
2476 }
2477
2478 /**
2479  *  e1000e_reset_hw_ich8lan - Reset the hardware
2480  *  @hw: pointer to the HW structure
2481  *
2482  *  Does a full reset of the hardware which includes a reset of the PHY and
2483  *  MAC.
2484  **/
2485 static s32 e1000e_reset_hw_ich8lan(struct e1000_hw *hw)
2486 {
2487         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2488         u16 reg;
2489         u32 ctrl, icr, kab;
2490         s32 ret_val;
2491
2492         /*
2493          * Prevent the PCI-E bus from sticking if there is no TLP connection
2494          * on the last TLP read/write transaction when MAC is reset.
2495          */
2496         ret_val = e1000e_disable_pcie_master(hw);
2497         if (ret_val)
2498                 e_dbg("PCI-E Master disable polling has failed.\n");
2499
2500         e_dbg("Masking off all interrupts\n");
2501         ew32(IMC, 0xffffffff);
2502
2503         /*
2504          * Disable the Transmit and Receive units.  Then delay to allow
2505          * any pending transactions to complete before we hit the MAC
2506          * with the global reset.
2507          */
2508         ew32(RCTL, 0);
2509         ew32(TCTL, E1000_TCTL_PSP);
2510         e1e_flush();
2511
2512         msleep(10);
2513
2514         /* Workaround for ICH8 bit corruption issue in FIFO memory */
2515         if (hw->mac.type == e1000_ich8lan) {
2516                 /* Set Tx and Rx buffer allocation to 8k apiece. */
2517                 ew32(PBA, E1000_PBA_8K);
2518                 /* Set Packet Buffer Size to 16k. */
2519                 ew32(PBS, E1000_PBS_16K);
2520         }
2521
2522         if (hw->mac.type == e1000_pchlan) {
2523                 /* Save the NVM K1 bit setting*/
2524                 ret_val = e1000e_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &reg);
2525                 if (ret_val)
2526                         return ret_val;
2527
2528                 if (reg & E1000_NVM_K1_ENABLE)
2529                         dev_spec->nvm_k1_enabled = true;
2530                 else
2531                         dev_spec->nvm_k1_enabled = false;
2532         }
2533
2534         ctrl = er32(CTRL);
2535
2536         if (!e1000e_check_reset_block(hw) && !hw->phy.reset_disable) {
2537                 /* Clear PHY Reset Asserted bit */
2538                 if (hw->mac.type >= e1000_pchlan) {
2539                         u32 status = er32(STATUS);
2540                         ew32(STATUS, status &
2541                                         ~E1000_STATUS_PHYRA);
2542                 }
2543
2544                 /*
2545                  * PHY HW reset requires MAC CORE reset at the same
2546                  * time to make sure the interface between MAC and the
2547                  * external PHY is reset.
2548                  */
2549                 ctrl |= E1000_CTRL_PHY_RST;
2550         }
2551         ret_val = e1000e_acquire_swflag_ich8lan(hw);
2552         e_dbg("Issuing a global reset to ich8lan\n");
2553         ew32(CTRL, (ctrl | E1000_CTRL_RST));
2554         msleep(20);
2555
2556         if (!ret_val)
2557                 e1000e_release_swflag_ich8lan(hw);
2558
2559         if (ctrl & E1000_CTRL_PHY_RST)
2560                 ret_val = hw->phy.ops.get_cfg_done(hw);
2561
2562         if (hw->mac.type >= e1000_ich10lan) {
2563                 e1000e_lan_init_done_ich8lan(hw);
2564         } else {
2565                 ret_val = e1000e_get_auto_rd_done(hw);
2566                 if (ret_val) {
2567                         /*
2568                          * When auto config read does not complete, do not
2569                          * return with an error. This can happen in situations
2570                          * where there is no eeprom and prevents getting link.
2571                          */
2572                         e_dbg("Auto Read Done did not complete\n");
2573                 }
2574         }
2575         /* Dummy read to clear the phy wakeup bit after lcd reset */
2576         if (hw->mac.type == e1000_pchlan)
2577                 e1e_rphy(hw, BM_WUC, &reg);
2578
2579         ret_val = e1000e_sw_lcd_config_ich8lan(hw);
2580         if (ret_val)
2581                 goto out;
2582
2583         if (hw->mac.type == e1000_pchlan) {
2584                 ret_val = e1000e_oem_bits_config_ich8lan(hw, true);
2585                 if (ret_val)
2586                         goto out;
2587         }
2588         /*
2589          * For PCH, this write will make sure that any noise
2590          * will be detected as a CRC error and be dropped rather than show up
2591          * as a bad packet to the DMA engine.
2592          */
2593         if (hw->mac.type == e1000_pchlan)
2594                 ew32(CRC_OFFSET, 0x65656565);
2595
2596         ew32(IMC, 0xffffffff);
2597         icr = er32(ICR);
2598
2599         kab = er32(KABGTXD);
2600         kab |= E1000_KABGTXD_BGSQLBIAS;
2601         ew32(KABGTXD, kab);
2602
2603         if (hw->mac.type == e1000_pchlan)
2604                 ret_val = e1000e_hv_phy_workarounds_ich8lan(hw);
2605
2606 out:
2607         return ret_val;
2608 }
2609
2610 /**
2611  *  e1000e_init_hw_ich8lan - Initialize the hardware
2612  *  @hw: pointer to the HW structure
2613  *
2614  *  Prepares the hardware for transmit and receive by doing the following:
2615  *   - initialize hardware bits
2616  *   - initialize LED identification
2617  *   - setup receive address registers
2618  *   - setup flow control
2619  *   - setup transmit descriptors
2620  *   - clear statistics
2621  **/
2622 static s32 e1000e_init_hw_ich8lan(struct e1000_hw *hw)
2623 {
2624         struct e1000_mac_info *mac = &hw->mac;
2625         u32 ctrl_ext, txdctl, snoop;
2626         s32 ret_val;
2627         u16 i;
2628
2629         e1000e_initialize_hw_bits_ich8lan(hw);
2630
2631         /* Initialize identification LED */
2632         ret_val = mac->ops.id_led_init(hw);
2633         if (ret_val)
2634                 /* This is not fatal and we should not stop init due to this */
2635                 e_dbg("Error initializing identification LED\n");
2636
2637         /* Setup the receive address. */
2638         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
2639
2640         /* Zero out the Multicast HASH table */
2641         e_dbg("Zeroing the MTA\n");
2642         for (i = 0; i < mac->mta_reg_count; i++)
2643                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
2644
2645         /*
2646          * The 82578 Rx buffer will stall if wakeup is enabled in host and
2647          * the ME.  Reading the BM_WUC register will clear the host wakeup bit.
2648          * Reset the phy after disabling host wakeup to reset the Rx buffer.
2649          */
2650         if (hw->phy.type == e1000_phy_82578) {
2651                 e1e_rphy(hw, BM_WUC, &i);
2652                 ret_val = e1000e_phy_hw_reset_ich8lan(hw);
2653                 if (ret_val)
2654                         return ret_val;
2655         }
2656
2657         /* Setup link and flow control */
2658         ret_val = mac->ops.setup_link(hw);
2659
2660         /* Set the transmit descriptor write-back policy for both queues */
2661         txdctl = er32(TXDCTL(0));
2662         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2663                  E1000_TXDCTL_FULL_TX_DESC_WB;
2664         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2665                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2666         ew32(TXDCTL(0), txdctl);
2667         txdctl = er32(TXDCTL(1));
2668         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2669                  E1000_TXDCTL_FULL_TX_DESC_WB;
2670         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2671                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2672         ew32(TXDCTL(1), txdctl);
2673
2674         /*
2675          * ICH8 has opposite polarity of no_snoop bits.
2676          * By default, we should use snoop behavior.
2677          */
2678         if (mac->type == e1000_ich8lan)
2679                 snoop = PCIE_ICH8_SNOOP_ALL;
2680         else
2681                 snoop = (u32)~(PCIE_NO_SNOOP_ALL);
2682         e1000e_set_pcie_no_snoop(hw, snoop);
2683
2684         ctrl_ext = er32(CTRL_EXT);
2685         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
2686         ew32(CTRL_EXT, ctrl_ext);
2687
2688         /*
2689          * Clear all of the statistics registers (clear on read).  It is
2690          * important that we do this after we have tried to establish link
2691          * because the symbol error count will increment wildly if there
2692          * is no link.
2693          */
2694         e1000e_clear_hw_cntrs_ich8lan(hw);
2695
2696         return ret_val;
2697 }
2698 /**
2699  *  e1000e_initialize_hw_bits_ich8lan - Initialize required hardware bits
2700  *  @hw: pointer to the HW structure
2701  *
2702  *  Sets/Clears required hardware bits necessary for correctly setting up the
2703  *  hardware for transmit and receive.
2704  **/
2705 static void e1000e_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
2706 {
2707         u32 reg;
2708
2709         /* Extended Device Control */
2710         reg = er32(CTRL_EXT);
2711         reg |= (1 << 22);
2712         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
2713         if (hw->mac.type >= e1000_pchlan)
2714                 reg |= E1000_CTRL_EXT_PHYPDEN;
2715         ew32(CTRL_EXT, reg);
2716
2717         /* Transmit Descriptor Control 0 */
2718         reg = er32(TXDCTL(0));
2719         reg |= (1 << 22);
2720         ew32(TXDCTL(0), reg);
2721
2722         /* Transmit Descriptor Control 1 */
2723         reg = er32(TXDCTL(1));
2724         reg |= (1 << 22);
2725         ew32(TXDCTL(1), reg);
2726
2727         /* Transmit Arbitration Control 0 */
2728         reg = er32(TARC(0));
2729         if (hw->mac.type == e1000_ich8lan)
2730                 reg |= (1 << 28) | (1 << 29);
2731         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
2732         ew32(TARC(0), reg);
2733
2734         /* Transmit Arbitration Control 1 */
2735         reg = er32(TARC(1));
2736         if (er32(TCTL) & E1000_TCTL_MULR)
2737                 reg &= ~(1 << 28);
2738         else
2739                 reg |= (1 << 28);
2740         reg |= (1 << 24) | (1 << 26) | (1 << 30);
2741         ew32(TARC(1), reg);
2742
2743         /* Device Status */
2744         if (hw->mac.type == e1000_ich8lan) {
2745                 reg = er32(STATUS);
2746                 reg &= ~(1 << 31);
2747                 ew32(STATUS, reg);
2748         }
2749
2750         return;
2751 }
2752
2753 /**
2754  *  e1000e_setup_link_ich8lan - Setup flow control and link settings
2755  *  @hw: pointer to the HW structure
2756  *
2757  *  Determines which flow control settings to use, then configures flow
2758  *  control.  Calls the appropriate media-specific link configuration
2759  *  function.  Assuming the adapter has a valid link partner, a valid link
2760  *  should be established.  Assumes the hardware has previously been reset
2761  *  and the transmitter and receiver are not enabled.
2762  **/
2763 static s32 e1000e_setup_link_ich8lan(struct e1000_hw *hw)
2764 {
2765         s32 ret_val = E1000_SUCCESS;
2766
2767         if (e1000e_check_reset_block(hw))
2768                 goto out;
2769
2770         /*
2771          * ICH parts do not have a word in the NVM to determine
2772          * the default flow control setting, so we explicitly
2773          * set it to full.
2774          */
2775         if (hw->fc.requested_mode == e1000_fc_default)
2776                 hw->fc.requested_mode = e1000_fc_full;
2777
2778         /*
2779          * Save off the requested flow control mode for use later.  Depending
2780          * on the link partner's capabilities, we may or may not use this mode.
2781          */
2782         hw->fc.current_mode = hw->fc.requested_mode;
2783
2784         e_dbg("After fix-ups FlowControl is now = %x\n",
2785                 hw->fc.current_mode);
2786
2787         /* Continue to configure the copper link. */
2788         ret_val = hw->mac.ops.setup_physical_interface(hw);
2789         if (ret_val)
2790                 goto out;
2791
2792         ew32(FCTTV, hw->fc.pause_time);
2793         if ((hw->phy.type == e1000_phy_82578) ||
2794             (hw->phy.type == e1000_phy_82577)) {
2795                 ret_val = e1e_wphy(hw,
2796                                              PHY_REG(BM_PORT_CTRL_PAGE, 27),
2797                                              hw->fc.pause_time);
2798                 if (ret_val)
2799                         goto out;
2800         }
2801
2802         ret_val = e1000e_set_fc_watermarks(hw);
2803
2804 out:
2805         return ret_val;
2806 }
2807
2808 /**
2809  *  e1000e_setup_copper_link_ich8lan - Configure MAC/PHY interface
2810  *  @hw: pointer to the HW structure
2811  *
2812  *  Configures the kumeran interface to the PHY to wait the appropriate time
2813  *  when polling the PHY, then call the generic setup_copper_link to finish
2814  *  configuring the copper link.
2815  **/
2816 static s32 e1000e_setup_copper_link_ich8lan(struct e1000_hw *hw)
2817 {
2818         u32 ctrl;
2819         s32 ret_val;
2820         u16 reg_data;
2821
2822         ctrl = er32(CTRL);
2823         ctrl |= E1000_CTRL_SLU;
2824         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2825         ew32(CTRL, ctrl);
2826
2827         /*
2828          * Set the mac to wait the maximum time between each iteration
2829          * and increase the max iterations when polling the phy;
2830          * this fixes erroneous timeouts at 10Mbps.
2831          */
2832         ret_val = e1000e_write_kmrn_reg(hw,
2833                                                E1000_KMRNCTRLSTA_TIMEOUTS,
2834                                                0xFFFF);
2835         if (ret_val)
2836                 goto out;
2837         ret_val = e1000e_read_kmrn_reg(hw,
2838                                               E1000_KMRNCTRLSTA_INBAND_PARAM,
2839                                               &reg_data);
2840         if (ret_val)
2841                 goto out;
2842         reg_data |= 0x3F;
2843         ret_val = e1000e_write_kmrn_reg(hw,
2844                                                E1000_KMRNCTRLSTA_INBAND_PARAM,
2845                                                reg_data);
2846         if (ret_val)
2847                 goto out;
2848
2849         switch (hw->phy.type) {
2850         case e1000_phy_igp_3:
2851                 ret_val = e1000e_copper_link_setup_igp(hw);
2852                 if (ret_val)
2853                         goto out;
2854                 break;
2855         case e1000_phy_bm:
2856         case e1000_phy_82578:
2857                 ret_val = e1000e_copper_link_setup_m88(hw);
2858                 if (ret_val)
2859                         goto out;
2860                 break;
2861         case e1000_phy_82577:
2862                 ret_val = e1000e_copper_link_setup_82577(hw);
2863                 if (ret_val)
2864                         goto out;
2865                 break;
2866         case e1000_phy_ife:
2867                 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL,
2868                                                &reg_data);
2869                 if (ret_val)
2870                         goto out;
2871
2872                 reg_data &= ~IFE_PMC_AUTO_MDIX;
2873
2874                 switch (hw->phy.mdix) {
2875                 case 1:
2876                         reg_data &= ~IFE_PMC_FORCE_MDIX;
2877                         break;
2878                 case 2:
2879                         reg_data |= IFE_PMC_FORCE_MDIX;
2880                         break;
2881                 case 0:
2882                 default:
2883                         reg_data |= IFE_PMC_AUTO_MDIX;
2884                         break;
2885                 }
2886                 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL,
2887                                                 reg_data);
2888                 if (ret_val)
2889                         goto out;
2890                 break;
2891         default:
2892                 break;
2893         }
2894         ret_val = e1000e_setup_copper_link(hw);
2895
2896 out:
2897         return ret_val;
2898 }
2899
2900 /**
2901  *  e1000e_get_link_up_info_ich8lan - Get current link speed and duplex
2902  *  @hw: pointer to the HW structure
2903  *  @speed: pointer to store current link speed
2904  *  @duplex: pointer to store the current link duplex
2905  *
2906  *  Calls the generic get_speed_and_duplex to retrieve the current link
2907  *  information and then calls the Kumeran lock loss workaround for links at
2908  *  gigabit speeds.
2909  **/
2910 static s32 e1000e_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
2911                                           u16 *duplex)
2912 {
2913         s32 ret_val;
2914
2915         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
2916         if (ret_val)
2917                 goto out;
2918
2919         if ((hw->mac.type == e1000_ich8lan) &&
2920             (hw->phy.type == e1000_phy_igp_3) &&
2921             (*speed == SPEED_1000)) {
2922                 ret_val = e1000e_kmrn_lock_loss_workaround_ich8lan(hw);
2923         }
2924
2925 out:
2926         return ret_val;
2927 }
2928
2929 /**
2930  *  e1000e_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
2931  *  @hw: pointer to the HW structure
2932  *
2933  *  Work-around for 82566 Kumeran PCS lock loss:
2934  *  On link status change (i.e. PCI reset, speed change) and link is up and
2935  *  speed is gigabit-
2936  *    0) if workaround is optionally disabled do nothing
2937  *    1) wait 1ms for Kumeran link to come up
2938  *    2) check Kumeran Diagnostic register PCS lock loss bit
2939  *    3) if not set the link is locked (all is good), otherwise...
2940  *    4) reset the PHY
2941  *    5) repeat up to 10 times
2942  *  Note: this is only called for IGP3 copper when speed is 1gb.
2943  **/
2944 static s32 e1000e_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
2945 {
2946         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2947         u32 phy_ctrl;
2948         s32 ret_val = E1000_SUCCESS;
2949         u16 i, data;
2950         bool link;
2951
2952         if (!(dev_spec->kmrn_lock_loss_workaround_enabled))
2953                 goto out;
2954
2955         /*
2956          * Make sure link is up before proceeding.  If not just return.
2957          * Attempting this while link is negotiating fouled up link
2958          * stability
2959          */
2960         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2961         if (!link) {
2962                 ret_val = E1000_SUCCESS;
2963                 goto out;
2964         }
2965
2966         for (i = 0; i < 10; i++) {
2967                 /* read once to clear */
2968                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2969                 if (ret_val)
2970                         goto out;
2971                 /* and again to get new status */
2972                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2973                 if (ret_val)
2974                         goto out;
2975
2976                 /* check for PCS lock */
2977                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) {
2978                         ret_val = E1000_SUCCESS;
2979                         goto out;
2980                 }
2981
2982                 /* Issue PHY reset */
2983                 e1000e_phy_hw_reset(hw);
2984                 mdelay(5);
2985         }
2986         /* Disable GigE link negotiation */
2987         phy_ctrl = er32(PHY_CTRL);
2988         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
2989                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2990         ew32(PHY_CTRL, phy_ctrl);
2991
2992         /*
2993          * Call gig speed drop workaround on Gig disable before accessing
2994          * any PHY registers
2995          */
2996         e1000e_gig_downshift_workaround_ich8lan(hw);
2997
2998         /* unable to acquire PCS lock */
2999         ret_val = -E1000_ERR_PHY;
3000
3001 out:
3002         return ret_val;
3003 }
3004
3005 /**
3006  *  e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
3007  *  @hw: pointer to the HW structure
3008  *  @state: boolean value used to set the current Kumeran workaround state
3009  *
3010  *  If ICH8, set the current Kumeran workaround state (enabled - true
3011  *  /disabled - false).
3012  **/
3013 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3014                                                  bool state)
3015 {
3016         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3017
3018         if (hw->mac.type != e1000_ich8lan) {
3019                 e_dbg("Workaround applies to ICH8 only.\n");
3020                 return;
3021         }
3022
3023         dev_spec->kmrn_lock_loss_workaround_enabled = state;
3024
3025         return;
3026 }
3027
3028 /**
3029  *  e1000e_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3030  *  @hw: pointer to the HW structure
3031  *
3032  *  Workaround for 82566 power-down on D3 entry:
3033  *    1) disable gigabit link
3034  *    2) write VR power-down enable
3035  *    3) read it back
3036  *  Continue if successful, else issue LCD reset and repeat
3037  **/
3038 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3039 {
3040         u32 reg;
3041         u16 data;
3042         u8  retry = 0;
3043
3044         if (hw->phy.type != e1000_phy_igp_3)
3045                 goto out;
3046
3047         /* Try the workaround twice (if needed) */
3048         do {
3049                 /* Disable link */
3050                 reg = er32(PHY_CTRL);
3051                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3052                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3053                 ew32(PHY_CTRL, reg);
3054
3055                 /*
3056                  * Call gig speed drop workaround on Gig disable before
3057                  * accessing any PHY registers
3058                  */
3059                 if (hw->mac.type == e1000_ich8lan)
3060                         e1000e_gig_downshift_workaround_ich8lan(hw);
3061
3062                 /* Write VR power-down enable */
3063                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3064                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3065                 e1e_wphy(hw, IGP3_VR_CTRL,
3066                                    data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3067
3068                 /* Read it back and test */
3069                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3070                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3071                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3072                         break;
3073
3074                 /* Issue PHY reset and repeat at most one more time */
3075                 reg = er32(CTRL);
3076                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3077                 retry++;
3078         } while (retry);
3079
3080 out:
3081         return;
3082 }
3083
3084 /**
3085  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3086  *  @hw: pointer to the HW structure
3087  *
3088  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
3089  *  LPLU, Gig disable, MDIC PHY reset):
3090  *    1) Set Kumeran Near-end loopback
3091  *    2) Clear Kumeran Near-end loopback
3092  *  Should only be called for ICH8[m] devices with IGP_3 Phy.
3093  **/
3094 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3095 {
3096         s32 ret_val = E1000_SUCCESS;
3097         u16 reg_data;
3098
3099         if ((hw->mac.type != e1000_ich8lan) ||
3100             (hw->phy.type != e1000_phy_igp_3))
3101                 goto out;
3102
3103         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3104                                               &reg_data);
3105         if (ret_val)
3106                 goto out;
3107         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3108         ret_val = e1000e_write_kmrn_reg(hw,
3109                                                E1000_KMRNCTRLSTA_DIAG_OFFSET,
3110                                                reg_data);
3111         if (ret_val)
3112                 goto out;
3113         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3114         ret_val = e1000e_write_kmrn_reg(hw,
3115                                                E1000_KMRNCTRLSTA_DIAG_OFFSET,
3116                                                reg_data);
3117 out:
3118         return;
3119 }
3120
3121 /**
3122  *  e1000e_disable_gig_wol_ich8lan - disable gig during WoL
3123  *  @hw: pointer to the HW structure
3124  *
3125  *  During S0 to Sx transition, it is possible the link remains at gig
3126  *  instead of negotiating to a lower speed.  Before going to Sx, set
3127  *  'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
3128  *  to a lower speed.
3129  *
3130  *  Should only be called for applicable parts.
3131  **/
3132 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
3133 {
3134         u32 phy_ctrl;
3135
3136         switch (hw->mac.type) {
3137         case e1000_ich8lan:
3138         case e1000_ich9lan:
3139         case e1000_ich10lan:
3140         case e1000_pchlan:
3141                 phy_ctrl = er32(PHY_CTRL);
3142                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
3143                             E1000_PHY_CTRL_GBE_DISABLE;
3144                 ew32(PHY_CTRL, phy_ctrl);
3145
3146                 if (hw->mac.type == e1000_pchlan)
3147                         e1000e_phy_hw_reset_ich8lan(hw);
3148         default:
3149                 break;
3150         }
3151
3152         return;
3153 }
3154
3155 /**
3156  *  e1000e_cleanup_led_ich8lan - Restore the default LED operation
3157  *  @hw: pointer to the HW structure
3158  *
3159  *  Return the LED back to the default configuration.
3160  **/
3161 static s32 e1000e_cleanup_led_ich8lan(struct e1000_hw *hw)
3162 {
3163         s32 ret_val = E1000_SUCCESS;
3164
3165         if (hw->phy.type == e1000_phy_ife)
3166                 ret_val = e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3167                                               0);
3168         else
3169                 ew32(LEDCTL, hw->mac.ledctl_default);
3170
3171         return ret_val;
3172 }
3173
3174 /**
3175  *  e1000e_led_on_ich8lan - Turn LEDs on
3176  *  @hw: pointer to the HW structure
3177  *
3178  *  Turn on the LEDs.
3179  **/
3180 static s32 e1000e_led_on_ich8lan(struct e1000_hw *hw)
3181 {
3182         s32 ret_val = E1000_SUCCESS;
3183
3184         if (hw->phy.type == e1000_phy_ife)
3185                 ret_val = e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3186                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3187         else
3188                 ew32(LEDCTL, hw->mac.ledctl_mode2);
3189
3190         return ret_val;
3191 }
3192
3193 /**
3194  *  e1000e_led_off_ich8lan - Turn LEDs off
3195  *  @hw: pointer to the HW structure
3196  *
3197  *  Turn off the LEDs.
3198  **/
3199 static s32 e1000e_led_off_ich8lan(struct e1000_hw *hw)
3200 {
3201         s32 ret_val = E1000_SUCCESS;
3202
3203         if (hw->phy.type == e1000_phy_ife)
3204                 ret_val = e1e_wphy(hw,
3205                                IFE_PHY_SPECIAL_CONTROL_LED,
3206                                (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
3207         else
3208                 ew32(LEDCTL, hw->mac.ledctl_mode1);
3209
3210         return ret_val;
3211 }
3212
3213 /**
3214  *  e1000e_setup_led_pchlan - Configures SW controllable LED
3215  *  @hw: pointer to the HW structure
3216  *
3217  *  This prepares the SW controllable LED for use.
3218  **/
3219 static s32 e1000e_setup_led_pchlan(struct e1000_hw *hw)
3220 {
3221         return e1e_wphy(hw, HV_LED_CONFIG,
3222                                         (u16)hw->mac.ledctl_mode1);
3223 }
3224
3225 /**
3226  *  e1000e_cleanup_led_pchlan - Restore the default LED operation
3227  *  @hw: pointer to the HW structure
3228  *
3229  *  Return the LED back to the default configuration.
3230  **/
3231 static s32 e1000e_cleanup_led_pchlan(struct e1000_hw *hw)
3232 {
3233         return e1e_wphy(hw, HV_LED_CONFIG,
3234                                         (u16)hw->mac.ledctl_default);
3235 }
3236
3237 /**
3238  *  e1000e_led_on_pchlan - Turn LEDs on
3239  *  @hw: pointer to the HW structure
3240  *
3241  *  Turn on the LEDs.
3242  **/
3243 static s32 e1000e_led_on_pchlan(struct e1000_hw *hw)
3244 {
3245         u16 data = (u16)hw->mac.ledctl_mode2;
3246         u32 i, led;
3247
3248         /*
3249          * If no link, then turn LED on by setting the invert bit
3250          * for each LED that's mode is "link_up" in ledctl_mode2.
3251          */
3252         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3253                 for (i = 0; i < 3; i++) {
3254                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3255                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3256                             E1000_LEDCTL_MODE_LINK_UP)
3257                                 continue;
3258                         if (led & E1000_PHY_LED0_IVRT)
3259                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3260                         else
3261                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3262                 }
3263         }
3264
3265         return e1e_wphy(hw, HV_LED_CONFIG, data);
3266 }
3267
3268 /**
3269  *  e1000e_led_off_pchlan - Turn LEDs off
3270  *  @hw: pointer to the HW structure
3271  *
3272  *  Turn off the LEDs.
3273  **/
3274 static s32 e1000e_led_off_pchlan(struct e1000_hw *hw)
3275 {
3276         u16 data = (u16)hw->mac.ledctl_mode1;
3277         u32 i, led;
3278
3279         /*
3280          * If no link, then turn LED off by clearing the invert bit
3281          * for each LED that's mode is "link_up" in ledctl_mode1.
3282          */
3283         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3284                 for (i = 0; i < 3; i++) {
3285                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3286                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3287                             E1000_LEDCTL_MODE_LINK_UP)
3288                                 continue;
3289                         if (led & E1000_PHY_LED0_IVRT)
3290                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3291                         else
3292                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3293                 }
3294         }
3295
3296         return e1e_wphy(hw, HV_LED_CONFIG, data);
3297 }
3298
3299 /**
3300  *  e1000e_get_cfg_done_ich8lan - Read config done bit
3301  *  @hw: pointer to the HW structure
3302  *
3303  *  Read the management control register for the config done bit for
3304  *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
3305  *  to read the config done bit, so an error is *ONLY* logged and returns
3306  *  E1000_SUCCESS.  If we were to return with error, EEPROM-less silicon
3307  *  would not be able to be reset or change link.
3308  **/
3309 static s32 e1000e_get_cfg_done_ich8lan(struct e1000_hw *hw)
3310 {
3311         s32 ret_val = E1000_SUCCESS;
3312         u32 bank = 0;
3313
3314         if (hw->mac.type >= e1000_pchlan) {
3315                 u32 status = er32(STATUS);
3316
3317                 if (status & E1000_STATUS_PHYRA) {
3318                         ew32(STATUS, status &
3319                                         ~E1000_STATUS_PHYRA);
3320                 } else
3321                         e_dbg("PHY Reset Asserted not set - needs delay\n");
3322         }
3323
3324         e1000e_get_cfg_done(hw);
3325
3326         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3327         if ((hw->mac.type != e1000_ich10lan) &&
3328             (hw->mac.type != e1000_pchlan)) {
3329                 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3330                     (hw->phy.type == e1000_phy_igp_3)) {
3331                         e1000e_phy_init_script_igp3(hw);
3332                 }
3333         } else {
3334                 if (e1000e_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3335                         /* Maybe we should do a basic PHY config */
3336                         e_dbg("EEPROM not present\n");
3337                         ret_val = -E1000_ERR_CONFIG;
3338                 }
3339         }
3340
3341         return ret_val;
3342 }
3343
3344 /**
3345  * e1000e_power_down_phy_copper_ich8lan - Remove link during PHY power down
3346  * @hw: pointer to the HW structure
3347  *
3348  * In the case of a PHY power down to save power, or to turn off link during a
3349  * driver unload, or wake on lan is not enabled, remove the link.
3350  **/
3351 static void e1000e_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
3352 {
3353         /* If the management interface is not enabled, then power down */
3354         if (!(hw->mac.ops.check_mng_mode(hw) ||
3355               e1000e_check_reset_block(hw)))
3356                 e1000e_power_down_phy_copper(hw);
3357
3358         return;
3359 }
3360
3361 /**
3362  *  e1000e_clear_hw_cntrs_ich8lan - Clear statistical counters
3363  *  @hw: pointer to the HW structure
3364  *
3365  *  Clears hardware counters specific to the silicon family and calls