[e1000e] Add e1000e driver
[people/pcmattman/gpxe.git] / src / drivers / net / e1000e / e1000e_82571.c
1 /*******************************************************************************
2
3   Intel PRO/1000 Linux driver
4   Copyright(c) 1999 - 2009 Intel Corporation.
5
6   This program is free software; you can redistribute it and/or modify it
7   under the terms and conditions of the GNU General Public License,
8   version 2, as published by the Free Software Foundation.
9
10   This program is distributed in the hope it will be useful, but WITHOUT
11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13   more details.
14
15   You should have received a copy of the GNU General Public License along with
16   this program; if not, write to the Free Software Foundation, Inc.,
17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19   The full GNU General Public License is included in this distribution in
20   the file called "COPYING".
21
22   Contact Information:
23   Linux NICS <linux.nics@intel.com>
24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 FILE_LICENCE ( GPL2_OR_LATER );
30
31 /*
32  * 82571EB Gigabit Ethernet Controller
33  * 82571EB Gigabit Ethernet Controller (Copper)
34  * 82571EB Gigabit Ethernet Controller (Fiber)
35  * 82571EB Dual Port Gigabit Mezzanine Adapter
36  * 82571EB Quad Port Gigabit Mezzanine Adapter
37  * 82571PT Gigabit PT Quad Port Server ExpressModule
38  * 82572EI Gigabit Ethernet Controller (Copper)
39  * 82572EI Gigabit Ethernet Controller (Fiber)
40  * 82572EI Gigabit Ethernet Controller
41  * 82573V Gigabit Ethernet Controller (Copper)
42  * 82573E Gigabit Ethernet Controller (Copper)
43  * 82573L Gigabit Ethernet Controller
44  * 82574L Gigabit Network Connection
45  * 82574L Gigabit Network Connection
46  * 82583V Gigabit Network Connection
47  */
48
49 #include "e1000e.h"
50
51 static s32  e1000e_init_phy_params_82571(struct e1000_hw *hw);
52 static s32  e1000e_init_nvm_params_82571(struct e1000_hw *hw);
53 static s32  e1000e_init_mac_params_82571(struct e1000_hw *hw);
54 static s32  e1000e_acquire_nvm_82571(struct e1000_hw *hw);
55 static void e1000e_release_nvm_82571(struct e1000_hw *hw);
56 static s32  e1000e_write_nvm_82571(struct e1000_hw *hw, u16 offset,
57                                   u16 words, u16 *data);
58 static s32  e1000e_update_nvm_checksum_82571(struct e1000_hw *hw);
59 static s32  e1000e_validate_nvm_checksum_82571(struct e1000_hw *hw);
60 static s32  e1000e_get_cfg_done_82571(struct e1000_hw *hw);
61 static s32  e1000e_set_d0_lplu_state_82571(struct e1000_hw *hw,
62                                           bool active);
63 static s32  e1000e_reset_hw_82571(struct e1000_hw *hw);
64 static s32  e1000e_init_hw_82571(struct e1000_hw *hw);
65 static void e1000e_clear_vfta_82571(struct e1000_hw *hw);
66 #if 0
67 static bool e1000e_check_mng_mode_82574(struct e1000_hw *hw);
68 #endif
69 static s32  e1000e_led_on_82574(struct e1000_hw *hw);
70 static s32  e1000e_setup_link_82571(struct e1000_hw *hw);
71 static s32  e1000e_setup_copper_link_82571(struct e1000_hw *hw);
72 static s32  e1000e_check_for_serdes_link_82571(struct e1000_hw *hw);
73 static s32  e1000e_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
74 static s32  e1000e_valid_led_default_82571(struct e1000_hw *hw, u16 *data);
75 static void e1000e_clear_hw_cntrs_82571(struct e1000_hw *hw);
76 static s32  e1000e_get_hw_semaphore_82571(struct e1000_hw *hw);
77 static s32  e1000e_fix_nvm_checksum_82571(struct e1000_hw *hw);
78 static s32  e1000e_get_phy_id_82571(struct e1000_hw *hw);
79 static void e1000e_put_hw_semaphore_82571(struct e1000_hw *hw);
80 static void e1000e_initialize_hw_bits_82571(struct e1000_hw *hw);
81 static s32  e1000e_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
82                                        u16 words, u16 *data);
83 static s32  e1000e_read_mac_addr_82571(struct e1000_hw *hw);
84 static void e1000e_power_down_phy_copper_82571(struct e1000_hw *hw);
85
86 /**
87  *  e1000e_init_phy_params_82571 - Init PHY func ptrs.
88  *  @hw: pointer to the HW structure
89  **/
90 static s32 e1000e_init_phy_params_82571(struct e1000_hw *hw)
91 {
92         struct e1000_phy_info *phy = &hw->phy;
93         s32 ret_val = E1000_SUCCESS;
94
95         if (hw->phy.media_type != e1000_media_type_copper) {
96                 phy->type = e1000_phy_none;
97                 goto out;
98         }
99
100         phy->addr                        = 1;
101         phy->autoneg_mask                = AUTONEG_ADVERTISE_SPEED_DEFAULT;
102         phy->reset_delay_us              = 100;
103
104         phy->ops.acquire                 = e1000e_get_hw_semaphore_82571;
105         phy->ops.check_polarity          = e1000e_check_polarity_igp;
106         phy->ops.check_reset_block       = e1000e_check_reset_block_generic;
107         phy->ops.release                 = e1000e_put_hw_semaphore_82571;
108         phy->ops.reset                   = e1000e_phy_hw_reset_generic;
109         phy->ops.set_d0_lplu_state       = e1000e_set_d0_lplu_state_82571;
110         phy->ops.set_d3_lplu_state       = e1000e_set_d3_lplu_state;
111         phy->ops.power_up                = e1000e_power_up_phy_copper;
112         phy->ops.power_down              = e1000e_power_down_phy_copper_82571;
113
114         switch (hw->mac.type) {
115         case e1000_82571:
116         case e1000_82572:
117                 phy->type                   = e1000_phy_igp_2;
118                 phy->ops.get_cfg_done       = e1000e_get_cfg_done_82571;
119                 phy->ops.get_info           = e1000e_get_phy_info_igp;
120 #if 0
121                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
122 #endif
123 #if 0
124                 phy->ops.get_cable_length   = e1000e_get_cable_length_igp_2;
125 #endif
126                 phy->ops.read_reg           = e1000e_read_phy_reg_igp;
127                 phy->ops.write_reg          = e1000e_write_phy_reg_igp;
128
129                 /* This uses above function pointers */
130                 ret_val = e1000e_get_phy_id_82571(hw);
131
132                 /* Verify PHY ID */
133                 if (phy->id != IGP01E1000_I_PHY_ID) {
134                         ret_val = -E1000_ERR_PHY;
135                         goto out;
136                 }
137                 break;
138         case e1000_82573:
139                 phy->type                   = e1000_phy_m88;
140                 phy->ops.get_cfg_done       = e1000e_get_cfg_done;
141                 phy->ops.get_info           = e1000e_get_phy_info_m88;
142                 phy->ops.commit             = e1000e_phy_sw_reset;
143 #if 0
144                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
145 #endif
146 #if 0
147                 phy->ops.get_cable_length   = e1000e_get_cable_length_m88;
148 #endif
149                 phy->ops.read_reg           = e1000e_read_phy_reg_m88;
150                 phy->ops.write_reg          = e1000e_write_phy_reg_m88;
151
152                 /* This uses above function pointers */
153                 ret_val = e1000e_get_phy_id_82571(hw);
154
155                 /* Verify PHY ID */
156                 if (phy->id != M88E1111_I_PHY_ID) {
157                         ret_val = -E1000_ERR_PHY;
158                         e_dbg("PHY ID unknown: type = 0x%08x\n", phy->id);
159                         goto out;
160                 }
161                 break;
162         case e1000_82583:
163         case e1000_82574:
164                 phy->type                   = e1000_phy_bm;
165                 phy->ops.get_cfg_done       = e1000e_get_cfg_done;
166                 phy->ops.get_info           = e1000e_get_phy_info_m88;
167                 phy->ops.commit             = e1000e_phy_sw_reset;
168 #if 0
169                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
170 #endif
171 #if 0
172                 phy->ops.get_cable_length   = e1000e_get_cable_length_m88;
173 #endif
174                 phy->ops.read_reg           = e1000e_read_phy_reg_bm2;
175                 phy->ops.write_reg          = e1000e_write_phy_reg_bm2;
176
177                 /* This uses above function pointers */
178                 ret_val = e1000e_get_phy_id_82571(hw);
179                 /* Verify PHY ID */
180                 if (phy->id != BME1000_E_PHY_ID_R2) {
181                         ret_val = -E1000_ERR_PHY;
182                         e_dbg("PHY ID unknown: type = 0x%08x\n", phy->id);
183                         goto out;
184                 }
185                 break;
186         default:
187                 ret_val = -E1000_ERR_PHY;
188                 goto out;
189                 break;
190         }
191
192 out:
193         return ret_val;
194 }
195
196 /**
197  *  e1000e_init_nvm_params_82571 - Init NVM func ptrs.
198  *  @hw: pointer to the HW structure
199  **/
200 static s32 e1000e_init_nvm_params_82571(struct e1000_hw *hw)
201 {
202         struct e1000_nvm_info *nvm = &hw->nvm;
203         u32 eecd = er32(EECD);
204         u16 size;
205
206         nvm->opcode_bits = 8;
207         nvm->delay_usec = 1;
208         switch (nvm->override) {
209         case e1000_nvm_override_spi_large:
210                 nvm->page_size = 32;
211                 nvm->address_bits = 16;
212                 break;
213         case e1000_nvm_override_spi_small:
214                 nvm->page_size = 8;
215                 nvm->address_bits = 8;
216                 break;
217         default:
218                 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
219                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
220                 break;
221         }
222
223         switch (hw->mac.type) {
224         case e1000_82573:
225         case e1000_82574:
226         case e1000_82583:
227                 if (((eecd >> 15) & 0x3) == 0x3) {
228                         nvm->type = e1000_nvm_flash_hw;
229                         nvm->word_size = 2048;
230                         /*
231                          * Autonomous Flash update bit must be cleared due
232                          * to Flash update issue.
233                          */
234                         eecd &= ~E1000_EECD_AUPDEN;
235                         ew32(EECD, eecd);
236                         break;
237                 }
238                 /* Fall Through */
239         default:
240                 nvm->type = e1000_nvm_eeprom_spi;
241                 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
242                                   E1000_EECD_SIZE_EX_SHIFT);
243                 /*
244                  * Added to a constant, "size" becomes the left-shift value
245                  * for setting word_size.
246                  */
247                 size += NVM_WORD_SIZE_BASE_SHIFT;
248
249                 /* EEPROM access above 16k is unsupported */
250                 if (size > 14)
251                         size = 14;
252                 nvm->word_size  = 1 << size;
253                 break;
254         }
255
256         /* Function Pointers */
257         nvm->ops.acquire       = e1000e_acquire_nvm_82571;
258         nvm->ops.read          = e1000e_read_nvm_eerd;
259         nvm->ops.release       = e1000e_release_nvm_82571;
260         nvm->ops.update        = e1000e_update_nvm_checksum_82571;
261         nvm->ops.validate      = e1000e_validate_nvm_checksum_82571;
262         nvm->ops.valid_led_default = e1000e_valid_led_default_82571;
263         nvm->ops.write         = e1000e_write_nvm_82571;
264
265         return E1000_SUCCESS;
266 }
267
268 /**
269  *  e1000e_init_mac_params_82571 - Init MAC func ptrs.
270  *  @hw: pointer to the HW structure
271  **/
272 static s32 e1000e_init_mac_params_82571(struct e1000_hw *hw)
273 {
274         struct e1000_mac_info *mac = &hw->mac;
275         s32 ret_val = E1000_SUCCESS;
276         u32 swsm = 0;
277         u32 swsm2 = 0;
278         bool force_clear_smbi = false;
279
280         /* Set media type */
281         switch (hw->device_id) {
282         case E1000_DEV_ID_82571EB_FIBER:
283         case E1000_DEV_ID_82572EI_FIBER:
284         case E1000_DEV_ID_82571EB_QUAD_FIBER:
285                 hw->phy.media_type = e1000_media_type_fiber;
286                 break;
287         case E1000_DEV_ID_82571EB_SERDES:
288         case E1000_DEV_ID_82571EB_SERDES_DUAL:
289         case E1000_DEV_ID_82571EB_SERDES_QUAD:
290         case E1000_DEV_ID_82572EI_SERDES:
291                 hw->phy.media_type = e1000_media_type_internal_serdes;
292                 break;
293         default:
294                 hw->phy.media_type = e1000_media_type_copper;
295                 break;
296         }
297
298         /* Set mta register count */
299         mac->mta_reg_count = 128;
300         /* Set rar entry count */
301         mac->rar_entry_count = E1000_RAR_ENTRIES;
302         /* Set if part includes ASF firmware */
303         mac->asf_firmware_present = true;
304         /* Set if manageability features are enabled. */
305         mac->arc_subsystem_valid =
306                 (er32(FWSM) & E1000_FWSM_MODE_MASK)
307                         ? true : false;
308
309         /* Function pointers */
310
311         /* bus type/speed/width */
312         mac->ops.get_bus_info = e1000e_get_bus_info_pcie;
313         /* function id */
314         switch (hw->mac.type) {
315         case e1000_82573:
316         case e1000_82574:
317         case e1000_82583:
318                 mac->ops.set_lan_id = e1000e_set_lan_id_single_port;
319                 break;
320         default:
321                 break;
322         }
323         /* reset */
324         mac->ops.reset_hw = e1000e_reset_hw_82571;
325         /* hw initialization */
326         mac->ops.init_hw = e1000e_init_hw_82571;
327         /* link setup */
328         mac->ops.setup_link = e1000e_setup_link_82571;
329         /* physical interface link setup */
330         mac->ops.setup_physical_interface =
331                 (hw->phy.media_type == e1000_media_type_copper)
332                         ? e1000e_setup_copper_link_82571
333                         : e1000e_setup_fiber_serdes_link_82571;
334         /* check for link */
335         switch (hw->phy.media_type) {
336         case e1000_media_type_copper:
337                 mac->ops.check_for_link = e1000e_check_for_copper_link;
338                 break;
339         case e1000_media_type_fiber:
340                 mac->ops.check_for_link = e1000e_check_for_fiber_link;
341                 break;
342         case e1000_media_type_internal_serdes:
343                 mac->ops.check_for_link = e1000e_check_for_serdes_link_82571;
344                 break;
345         default:
346                 ret_val = -E1000_ERR_CONFIG;
347                 goto out;
348                 break;
349         }
350         /* check management mode */
351 #if 0
352         switch (hw->mac.type) {
353         case e1000_82574:
354         case e1000_82583:
355                 mac->ops.check_mng_mode = e1000e_check_mng_mode_82574;
356                 break;
357         default:
358                 mac->ops.check_mng_mode = e1000e_check_mng_mode_generic;
359                 break;
360         }
361 #endif
362         /* multicast address update */
363         mac->ops.update_mc_addr_list = e1000e_update_mc_addr_list_generic;
364         /* writing VFTA */
365         mac->ops.write_vfta = e1000e_write_vfta_generic;
366         /* clearing VFTA */
367         mac->ops.clear_vfta = e1000e_clear_vfta_82571;
368         /* setting MTA */
369         mac->ops.mta_set = e1000e_mta_set_generic;
370         /* read mac address */
371         mac->ops.read_mac_addr = e1000e_read_mac_addr_82571;
372         /* ID LED init */
373         mac->ops.id_led_init = e1000e_id_led_init;
374         /* blink LED */
375         mac->ops.blink_led = e1000e_blink_led;
376         /* setup LED */
377         mac->ops.setup_led = e1000e_setup_led_generic;
378         /* cleanup LED */
379         mac->ops.cleanup_led = e1000e_cleanup_led_generic;
380         /* turn on/off LED */
381         switch (hw->mac.type) {
382         case e1000_82574:
383         case e1000_82583:
384                 mac->ops.led_on = e1000e_led_on_82574;
385                 break;
386         default:
387                 mac->ops.led_on = e1000e_led_on_generic;
388                 break;
389         }
390         mac->ops.led_off = e1000e_led_off_generic;
391         /* clear hardware counters */
392         mac->ops.clear_hw_cntrs = e1000e_clear_hw_cntrs_82571;
393         /* link info */
394         mac->ops.get_link_up_info =
395                 (hw->phy.media_type == e1000_media_type_copper)
396                         ? e1000e_get_speed_and_duplex_copper
397                         : e1000e_get_speed_and_duplex_fiber_serdes;
398
399         /*
400          * Ensure that the inter-port SWSM.SMBI lock bit is clear before
401          * first NVM or PHY acess. This should be done for single-port
402          * devices, and for one port only on dual-port devices so that
403          * for those devices we can still use the SMBI lock to synchronize
404          * inter-port accesses to the PHY & NVM.
405          */
406         switch (hw->mac.type) {
407         case e1000_82571:
408         case e1000_82572:
409                 swsm2 = er32(SWSM2);
410
411                 if (!(swsm2 & E1000_SWSM2_LOCK)) {
412                         /* Only do this for the first interface on this card */
413                         ew32(SWSM2,
414                             swsm2 | E1000_SWSM2_LOCK);
415                         force_clear_smbi = true;
416                 } else
417                         force_clear_smbi = false;
418                 break;
419         default:
420                 force_clear_smbi = true;
421                 break;
422         }
423
424         if (force_clear_smbi) {
425                 /* Make sure SWSM.SMBI is clear */
426                 swsm = er32(SWSM);
427                 if (swsm & E1000_SWSM_SMBI) {
428                         /* This bit should not be set on a first interface, and
429                          * indicates that the bootagent or EFI code has
430                          * improperly left this bit enabled
431                          */
432                         e_dbg("Please update your 82571 Bootagent\n");
433                 }
434                 ew32(SWSM, swsm & ~E1000_SWSM_SMBI);
435         }
436
437         /*
438          * Initialze device specific counter of SMBI acquisition
439          * timeouts.
440          */
441          hw->dev_spec._82571.smb_counter = 0;
442
443 out:
444         return ret_val;
445 }
446
447 /**
448  *  e1000e_init_function_pointers_82571 - Init func ptrs.
449  *  @hw: pointer to the HW structure
450  *
451  *  Called to initialize all function pointers and parameters.
452  **/
453 void e1000e_init_function_pointers_82571(struct e1000_hw *hw)
454 {
455         e1000e_init_mac_ops_generic(hw);
456         e1000e_init_nvm_ops_generic(hw);
457         hw->mac.ops.init_params = e1000e_init_mac_params_82571;
458         hw->nvm.ops.init_params = e1000e_init_nvm_params_82571;
459         hw->phy.ops.init_params = e1000e_init_phy_params_82571;
460 }
461
462 /**
463  *  e1000e_get_phy_id_82571 - Retrieve the PHY ID and revision
464  *  @hw: pointer to the HW structure
465  *
466  *  Reads the PHY registers and stores the PHY ID and possibly the PHY
467  *  revision in the hardware structure.
468  **/
469 static s32 e1000e_get_phy_id_82571(struct e1000_hw *hw)
470 {
471         struct e1000_phy_info *phy = &hw->phy;
472         s32 ret_val = E1000_SUCCESS;
473         u16 phy_id = 0;
474
475         switch (hw->mac.type) {
476         case e1000_82571:
477         case e1000_82572:
478                 /*
479                  * The 82571 firmware may still be configuring the PHY.
480                  * In this case, we cannot access the PHY until the
481                  * configuration is done.  So we explicitly set the
482                  * PHY ID.
483                  */
484                 phy->id = IGP01E1000_I_PHY_ID;
485                 break;
486         case e1000_82573:
487                 ret_val = e1000e_get_phy_id(hw);
488                 break;
489         case e1000_82574:
490         case e1000_82583:
491                 ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);
492                 if (ret_val)
493                         goto out;
494
495                 phy->id = (u32)(phy_id << 16);
496                 udelay(20);
497                 ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);
498                 if (ret_val)
499                         goto out;
500
501                 phy->id |= (u32)(phy_id);
502                 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
503                 break;
504         default:
505                 ret_val = -E1000_ERR_PHY;
506                 break;
507         }
508 out:
509         return ret_val;
510 }
511
512 /**
513  *  e1000e_get_hw_semaphore_82571 - Acquire hardware semaphore
514  *  @hw: pointer to the HW structure
515  *
516  *  Acquire the HW semaphore to access the PHY or NVM
517  **/
518 s32 e1000e_get_hw_semaphore_82571(struct e1000_hw *hw)
519 {
520         u32 swsm;
521         s32 ret_val = E1000_SUCCESS;
522         s32 sw_timeout = hw->nvm.word_size + 1;
523         s32 fw_timeout = hw->nvm.word_size + 1;
524         s32 i = 0;
525
526         /*
527          * If we have timedout 3 times on trying to acquire
528          * the inter-port SMBI semaphore, there is old code
529          * operating on the other port, and it is not
530          * releasing SMBI. Modify the number of times that
531          * we try for the semaphore to interwork with this
532          * older code.
533          */
534         if (hw->dev_spec._82571.smb_counter > 2)
535                 sw_timeout = 1;
536
537         /* Get the SW semaphore */
538         while (i < sw_timeout) {
539                 swsm = er32(SWSM);
540                 if (!(swsm & E1000_SWSM_SMBI))
541                         break;
542
543                 udelay(50);
544                 i++;
545         }
546
547         if (i == sw_timeout) {
548                 e_dbg("Driver can't access device - SMBI bit is set.\n");
549                 hw->dev_spec._82571.smb_counter++;
550         }
551         /* Get the FW semaphore. */
552         for (i = 0; i < fw_timeout; i++) {
553                 swsm = er32(SWSM);
554                 ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
555
556                 /* Semaphore acquired if bit latched */
557                 if (er32(SWSM) & E1000_SWSM_SWESMBI)
558                         break;
559
560                 udelay(50);
561         }
562
563         if (i == fw_timeout) {
564                 /* Release semaphores */
565                 e1000e_put_hw_semaphore_82571(hw);
566                 e_dbg("Driver can't access the NVM\n");
567                 ret_val = -E1000_ERR_NVM;
568                 goto out;
569         }
570
571 out:
572         return ret_val;
573 }
574
575 /**
576  *  e1000e_put_hw_semaphore_82571 - Release hardware semaphore
577  *  @hw: pointer to the HW structure
578  *
579  *  Release hardware semaphore used to access the PHY or NVM
580  **/
581 void e1000e_put_hw_semaphore_82571(struct e1000_hw *hw)
582 {
583         u32 swsm;
584
585         swsm = er32(SWSM);
586         swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
587         ew32(SWSM, swsm);
588 }
589
590 /**
591  *  e1000e_acquire_nvm_82571 - Request for access to the EEPROM
592  *  @hw: pointer to the HW structure
593  *
594  *  To gain access to the EEPROM, first we must obtain a hardware semaphore.
595  *  Then for non-82573 hardware, set the EEPROM access request bit and wait
596  *  for EEPROM access grant bit.  If the access grant bit is not set, release
597  *  hardware semaphore.
598  **/
599 static s32 e1000e_acquire_nvm_82571(struct e1000_hw *hw)
600 {
601         s32 ret_val;
602
603         ret_val = e1000e_get_hw_semaphore_82571(hw);
604         if (ret_val)
605                 goto out;
606
607         switch (hw->mac.type) {
608         case e1000_82574:
609         case e1000_82583:
610         case e1000_82573:
611                 break;
612         default:
613                 ret_val = e1000e_acquire_nvm(hw);
614                 break;
615         }
616
617         if (ret_val)
618                 e1000e_put_hw_semaphore_82571(hw);
619
620 out:
621         return ret_val;
622 }
623
624 /**
625  *  e1000e_release_nvm_82571 - Release exclusive access to EEPROM
626  *  @hw: pointer to the HW structure
627  *
628  *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
629  **/
630 static void e1000e_release_nvm_82571(struct e1000_hw *hw)
631 {
632         e1000e_release_nvm(hw);
633         e1000e_put_hw_semaphore_82571(hw);
634 }
635
636 /**
637  *  e1000e_write_nvm_82571 - Write to EEPROM using appropriate interface
638  *  @hw: pointer to the HW structure
639  *  @offset: offset within the EEPROM to be written to
640  *  @words: number of words to write
641  *  @data: 16 bit word(s) to be written to the EEPROM
642  *
643  *  For non-82573 silicon, write data to EEPROM at offset using SPI interface.
644  *
645  *  If e1000e_update_nvm_checksum is not called after this function, the
646  *  EEPROM will most likely contain an invalid checksum.
647  **/
648 static s32 e1000e_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
649                                  u16 *data)
650 {
651         s32 ret_val = E1000_SUCCESS;
652
653         switch (hw->mac.type) {
654         case e1000_82573:
655         case e1000_82574:
656         case e1000_82583:
657                 ret_val = e1000e_write_nvm_eewr_82571(hw, offset, words, data);
658                 break;
659         case e1000_82571:
660         case e1000_82572:
661                 ret_val = e1000e_write_nvm_spi(hw, offset, words, data);
662                 break;
663         default:
664                 ret_val = -E1000_ERR_NVM;
665                 break;
666         }
667
668         return ret_val;
669 }
670
671 /**
672  *  e1000e_update_nvm_checksum_82571 - Update EEPROM checksum
673  *  @hw: pointer to the HW structure
674  *
675  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
676  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
677  *  value to the EEPROM.
678  **/
679 static s32 e1000e_update_nvm_checksum_82571(struct e1000_hw *hw)
680 {
681         u32 eecd;
682         s32 ret_val;
683         u16 i;
684
685         ret_val = e1000e_update_nvm_checksum_generic(hw);
686         if (ret_val)
687                 goto out;
688
689         /*
690          * If our nvm is an EEPROM, then we're done
691          * otherwise, commit the checksum to the flash NVM.
692          */
693         if (hw->nvm.type != e1000_nvm_flash_hw)
694                 goto out;
695
696         /* Check for pending operations. */
697         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
698                 msleep(1);
699                 if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
700                         break;
701         }
702
703         if (i == E1000_FLASH_UPDATES) {
704                 ret_val = -E1000_ERR_NVM;
705                 goto out;
706         }
707
708         /* Reset the firmware if using STM opcode. */
709         if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) {
710                 /*
711                  * The enabling of and the actual reset must be done
712                  * in two write cycles.
713                  */
714                 ew32(HICR, E1000_HICR_FW_RESET_ENABLE);
715                 e1e_flush();
716                 ew32(HICR, E1000_HICR_FW_RESET);
717         }
718
719         /* Commit the write to flash */
720         eecd = er32(EECD) | E1000_EECD_FLUPD;
721         ew32(EECD, eecd);
722
723         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
724                 msleep(1);
725                 if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
726                         break;
727         }
728
729         if (i == E1000_FLASH_UPDATES) {
730                 ret_val = -E1000_ERR_NVM;
731                 goto out;
732         }
733
734 out:
735         return ret_val;
736 }
737
738 /**
739  *  e1000e_validate_nvm_checksum_82571 - Validate EEPROM checksum
740  *  @hw: pointer to the HW structure
741  *
742  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
743  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
744  **/
745 static s32 e1000e_validate_nvm_checksum_82571(struct e1000_hw *hw)
746 {
747         if (hw->nvm.type == e1000_nvm_flash_hw)
748                 e1000e_fix_nvm_checksum_82571(hw);
749
750         return e1000e_validate_nvm_checksum_generic(hw);
751 }
752
753 /**
754  *  e1000e_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
755  *  @hw: pointer to the HW structure
756  *  @offset: offset within the EEPROM to be written to
757  *  @words: number of words to write
758  *  @data: 16 bit word(s) to be written to the EEPROM
759  *
760  *  After checking for invalid values, poll the EEPROM to ensure the previous
761  *  command has completed before trying to write the next word.  After write
762  *  poll for completion.
763  *
764  *  If e1000e_update_nvm_checksum is not called after this function, the
765  *  EEPROM will most likely contain an invalid checksum.
766  **/
767 static s32 e1000e_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
768                                       u16 words, u16 *data)
769 {
770         struct e1000_nvm_info *nvm = &hw->nvm;
771         u32 i, eewr = 0;
772         s32 ret_val = 0;
773
774         /*
775          * A check for invalid values:  offset too large, too many words,
776          * and not enough words.
777          */
778         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
779             (words == 0)) {
780                 e_dbg("nvm parameter(s) out of bounds\n");
781                 ret_val = -E1000_ERR_NVM;
782                 goto out;
783         }
784
785         for (i = 0; i < words; i++) {
786                 eewr = (data[i] << E1000_NVM_RW_REG_DATA) |
787                        ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |
788                        E1000_NVM_RW_REG_START;
789
790                 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
791                 if (ret_val)
792                         break;
793
794                 ew32(EEWR, eewr);
795
796                 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
797                 if (ret_val)
798                         break;
799         }
800
801 out:
802         return ret_val;
803 }
804
805 /**
806  *  e1000e_get_cfg_done_82571 - Poll for configuration done
807  *  @hw: pointer to the HW structure
808  *
809  *  Reads the management control register for the config done bit to be set.
810  **/
811 static s32 e1000e_get_cfg_done_82571(struct e1000_hw *hw)
812 {
813         s32 timeout = PHY_CFG_TIMEOUT;
814         s32 ret_val = E1000_SUCCESS;
815
816         while (timeout) {
817                 if (er32(EEMNGCTL) & E1000_NVM_CFG_DONE_PORT_0)
818                         break;
819                 msleep(1);
820                 timeout--;
821         }
822         if (!timeout) {
823                 e_dbg("MNG configuration cycle has not completed.\n");
824                 ret_val = -E1000_ERR_RESET;
825                 goto out;
826         }
827
828 out:
829         return ret_val;
830 }
831
832 /**
833  *  e1000e_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
834  *  @hw: pointer to the HW structure
835  *  @active: true to enable LPLU, false to disable
836  *
837  *  Sets the LPLU D0 state according to the active flag.  When activating LPLU
838  *  this function also disables smart speed and vice versa.  LPLU will not be
839  *  activated unless the device autonegotiation advertisement meets standards
840  *  of either 10 or 10/100 or 10/100/1000 at all duplexes.  This is a function
841  *  pointer entry point only called by PHY setup routines.
842  **/
843 static s32 e1000e_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
844 {
845         struct e1000_phy_info *phy = &hw->phy;
846         s32 ret_val = E1000_SUCCESS;
847         u16 data;
848
849         if (!(phy->ops.read_reg))
850                 goto out;
851
852         ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
853         if (ret_val)
854                 goto out;
855
856         if (active) {
857                 data |= IGP02E1000_PM_D0_LPLU;
858                 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT,
859                                              data);
860                 if (ret_val)
861                         goto out;
862
863                 /* When LPLU is enabled, we should disable SmartSpeed */
864                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
865                                             &data);
866                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
867                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
868                                              data);
869                 if (ret_val)
870                         goto out;
871         } else {
872                 data &= ~IGP02E1000_PM_D0_LPLU;
873                 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT,
874                                              data);
875                 /*
876                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
877                  * during Dx states where the power conservation is most
878                  * important.  During driver activity we should enable
879                  * SmartSpeed, so performance is maintained.
880                  */
881                 if (phy->smart_speed == e1000_smart_speed_on) {
882                         ret_val = e1e_rphy(hw,
883                                                     IGP01E1000_PHY_PORT_CONFIG,
884                                                     &data);
885                         if (ret_val)
886                                 goto out;
887
888                         data |= IGP01E1000_PSCFR_SMART_SPEED;
889                         ret_val = e1e_wphy(hw,
890                                                      IGP01E1000_PHY_PORT_CONFIG,
891                                                      data);
892                         if (ret_val)
893                                 goto out;
894                 } else if (phy->smart_speed == e1000_smart_speed_off) {
895                         ret_val = e1e_rphy(hw,
896                                                     IGP01E1000_PHY_PORT_CONFIG,
897                                                     &data);
898                         if (ret_val)
899                                 goto out;
900
901                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
902                         ret_val = e1e_wphy(hw,
903                                                      IGP01E1000_PHY_PORT_CONFIG,
904                                                      data);
905                         if (ret_val)
906                                 goto out;
907                 }
908         }
909
910 out:
911         return ret_val;
912 }
913
914 /**
915  *  e1000e_reset_hw_82571 - Reset hardware
916  *  @hw: pointer to the HW structure
917  *
918  *  This resets the hardware into a known state.
919  **/
920 static s32 e1000e_reset_hw_82571(struct e1000_hw *hw)
921 {
922         u32 ctrl, extcnf_ctrl, ctrl_ext, icr;
923         s32 ret_val;
924         u16 i = 0;
925
926         /*
927          * Prevent the PCI-E bus from sticking if there is no TLP connection
928          * on the last TLP read/write transaction when MAC is reset.
929          */
930         ret_val = e1000e_disable_pcie_master(hw);
931         if (ret_val)
932                 e_dbg("PCI-E Master disable polling has failed.\n");
933
934         e_dbg("Masking off all interrupts\n");
935         ew32(IMC, 0xffffffff);
936
937         ew32(RCTL, 0);
938         ew32(TCTL, E1000_TCTL_PSP);
939         e1e_flush();
940
941         msleep(10);
942
943         /*
944          * Must acquire the MDIO ownership before MAC reset.
945          * Ownership defaults to firmware after a reset.
946          */
947         switch (hw->mac.type) {
948         case e1000_82574:
949         case e1000_82583:
950         case e1000_82573:
951                 extcnf_ctrl = er32(EXTCNF_CTRL);
952                 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
953
954                 do {
955                         ew32(EXTCNF_CTRL, extcnf_ctrl);
956                         extcnf_ctrl = er32(EXTCNF_CTRL);
957
958                         if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
959                                 break;
960
961                         extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
962
963                         msleep(2);
964                         i++;
965                 } while (i < MDIO_OWNERSHIP_TIMEOUT);
966                 break;
967         default:
968                 break;
969         }
970
971         ctrl = er32(CTRL);
972
973         e_dbg("Issuing a global reset to MAC\n");
974         ew32(CTRL, ctrl | E1000_CTRL_RST);
975
976         if (hw->nvm.type == e1000_nvm_flash_hw) {
977                 udelay(10);
978                 ctrl_ext = er32(CTRL_EXT);
979                 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
980                 ew32(CTRL_EXT, ctrl_ext);
981                 e1e_flush();
982         }
983
984         ret_val = e1000e_get_auto_rd_done(hw);
985         if (ret_val)
986                 /* We don't want to continue accessing MAC registers. */
987                 goto out;
988
989         /*
990          * Phy configuration from NVM just starts after EECD_AUTO_RD is set.
991          * Need to wait for Phy configuration completion before accessing
992          * NVM and Phy.
993          */
994
995         switch (hw->mac.type) {
996         case e1000_82574:
997         case e1000_82583:
998         case e1000_82573:
999                 msleep(25);
1000                 break;
1001         default:
1002                 break;
1003         }
1004
1005         /* Clear any pending interrupt events. */
1006         ew32(IMC, 0xffffffff);
1007         icr = er32(ICR);
1008
1009         /* Install any alternate MAC address into RAR0 */
1010         ret_val = e1000e_check_alt_mac_addr_generic(hw);
1011         if (ret_val)
1012                 goto out;
1013
1014         e1000e_set_laa_state_82571(hw, true);
1015
1016         /* Reinitialize the 82571 serdes link state machine */
1017         if (hw->phy.media_type == e1000_media_type_internal_serdes)
1018                 hw->mac.serdes_link_state = e1000_serdes_link_down;
1019
1020 out:
1021         return ret_val;
1022 }
1023
1024 /**
1025  *  e1000e_init_hw_82571 - Initialize hardware
1026  *  @hw: pointer to the HW structure
1027  *
1028  *  This inits the hardware readying it for operation.
1029  **/
1030 static s32 e1000e_init_hw_82571(struct e1000_hw *hw)
1031 {
1032         struct e1000_mac_info *mac = &hw->mac;
1033         u32 reg_data;
1034         s32 ret_val;
1035         u16 i, rar_count = mac->rar_entry_count;
1036
1037         e1000e_initialize_hw_bits_82571(hw);
1038
1039         /* Initialize identification LED */
1040         ret_val = mac->ops.id_led_init(hw);
1041         if (ret_val) {
1042                 e_dbg("Error initializing identification LED\n");
1043                 /* This is not fatal and we should not stop init due to this */
1044         }
1045
1046         /* Disabling VLAN filtering */
1047         e_dbg("Initializing the IEEE VLAN\n");
1048         e1000e_clear_vfta(hw);
1049
1050         /* Setup the receive address. */
1051         /*
1052          * If, however, a locally administered address was assigned to the
1053          * 82571, we must reserve a RAR for it to work around an issue where
1054          * resetting one port will reload the MAC on the other port.
1055          */
1056         if (e1000e_get_laa_state_82571(hw))
1057                 rar_count--;
1058         e1000e_init_rx_addrs(hw, rar_count);
1059
1060         /* Zero out the Multicast HASH table */
1061         e_dbg("Zeroing the MTA\n");
1062         for (i = 0; i < mac->mta_reg_count; i++)
1063                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1064
1065         /* Setup link and flow control */
1066         ret_val = mac->ops.setup_link(hw);
1067
1068         /* Set the transmit descriptor write-back policy */
1069         reg_data = er32(TXDCTL(0));
1070         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1071                    E1000_TXDCTL_FULL_TX_DESC_WB |
1072                    E1000_TXDCTL_COUNT_DESC;
1073         ew32(TXDCTL(0), reg_data);
1074
1075         /* ...for both queues. */
1076         switch (mac->type) {
1077         case e1000_82574:
1078         case e1000_82583:
1079         case e1000_82573:
1080 #if 0
1081                 e1000e_enable_tx_pkt_filtering(hw);
1082 #endif
1083                 reg_data = er32(GCR);
1084                 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1085                 ew32(GCR, reg_data);
1086                 break;
1087         default:
1088                 reg_data = er32(TXDCTL(1));
1089                 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1090                                         E1000_TXDCTL_FULL_TX_DESC_WB |
1091                                         E1000_TXDCTL_COUNT_DESC;
1092                 ew32(TXDCTL(1), reg_data);
1093                 break;
1094         }
1095
1096         /*
1097          * Clear all of the statistics registers (clear on read).  It is
1098          * important that we do this after we have tried to establish link
1099          * because the symbol error count will increment wildly if there
1100          * is no link.
1101          */
1102         e1000e_clear_hw_cntrs_82571(hw);
1103
1104         return ret_val;
1105 }
1106
1107 /**
1108  *  e1000e_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1109  *  @hw: pointer to the HW structure
1110  *
1111  *  Initializes required hardware-dependent bits needed for normal operation.
1112  **/
1113 static void e1000e_initialize_hw_bits_82571(struct e1000_hw *hw)
1114 {
1115         u32 reg;
1116
1117         /* Transmit Descriptor Control 0 */
1118         reg = er32(TXDCTL(0));
1119         reg |= (1 << 22);
1120         ew32(TXDCTL(0), reg);
1121
1122         /* Transmit Descriptor Control 1 */
1123         reg = er32(TXDCTL(1));
1124         reg |= (1 << 22);
1125         ew32(TXDCTL(1), reg);
1126
1127         /* Transmit Arbitration Control 0 */
1128         reg = er32(TARC(0));
1129         reg &= ~(0xF << 27); /* 30:27 */
1130         switch (hw->mac.type) {
1131         case e1000_82571:
1132         case e1000_82572:
1133                 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
1134                 break;
1135         default:
1136                 break;
1137         }
1138         ew32(TARC(0), reg);
1139
1140         /* Transmit Arbitration Control 1 */
1141         reg = er32(TARC(1));
1142         switch (hw->mac.type) {
1143         case e1000_82571:
1144         case e1000_82572:
1145                 reg &= ~((1 << 29) | (1 << 30));
1146                 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
1147                 if (er32(TCTL) & E1000_TCTL_MULR)
1148                         reg &= ~(1 << 28);
1149                 else
1150                         reg |= (1 << 28);
1151                 ew32(TARC(1), reg);
1152                 break;
1153         default:
1154                 break;
1155         }
1156
1157         /* Device Control */
1158
1159         switch (hw->mac.type) {
1160         case e1000_82574:
1161         case e1000_82583:
1162         case e1000_82573:
1163                 reg = er32(CTRL);
1164                 reg &= ~(1 << 29);
1165                 ew32(CTRL, reg);
1166                 break;
1167         default:
1168                 break;
1169         }
1170
1171         /* Extended Device Control */
1172         switch (hw->mac.type) {
1173         case e1000_82574:
1174         case e1000_82583:
1175         case e1000_82573:
1176                 reg = er32(CTRL_EXT);
1177                 reg &= ~(1 << 23);
1178                 reg |= (1 << 22);
1179                 ew32(CTRL_EXT, reg);
1180                 break;
1181         default:
1182                 break;
1183         }
1184
1185
1186         if (hw->mac.type == e1000_82571) {
1187                 reg = er32(PBA_ECC);
1188                 reg |= E1000_PBA_ECC_CORR_EN;
1189                 ew32(PBA_ECC, reg);
1190         }
1191
1192         /*
1193          * Workaround for hardware errata.
1194          * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1195          */
1196
1197         if ((hw->mac.type == e1000_82571) ||
1198            (hw->mac.type == e1000_82572)) {
1199                 reg = er32(CTRL_EXT);
1200                 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1201                 ew32(CTRL_EXT, reg);
1202         }
1203
1204         /* PCI-Ex Control Registers */
1205
1206         switch (hw->mac.type) {
1207         case e1000_82574:
1208         case e1000_82583:
1209                 reg = er32(GCR);
1210                 reg |= (1 << 22);
1211                 ew32(GCR, reg);
1212                 /*
1213                  * Workaround for hardware errata.
1214                  * apply workaround for hardware errata documented in errata
1215                  * docs Fixes issue where some error prone or unreliable PCIe
1216                  * completions are occurring, particularly with ASPM enabled.
1217                  * Without fix, issue can cause tx timeouts.
1218                  */
1219                 reg = er32(GCR2);
1220                 reg |= 1;
1221                 ew32(GCR2, reg);
1222                 break;
1223         default:
1224                 break;
1225         }
1226         return;
1227 }
1228
1229 /**
1230  *  e1000e_clear_vfta_82571 - Clear VLAN filter table
1231  *  @hw: pointer to the HW structure
1232  *
1233  *  Clears the register array which contains the VLAN filter table by
1234  *  setting all the values to 0.
1235  **/
1236 static void e1000e_clear_vfta_82571(struct e1000_hw *hw)
1237 {
1238         u32 offset;
1239         u32 vfta_value = 0;
1240         u32 vfta_offset = 0;
1241         u32 vfta_bit_in_reg = 0;
1242
1243         switch (hw->mac.type) {
1244         case e1000_82574:
1245         case e1000_82583:
1246         case e1000_82573:
1247                 if (hw->mng_cookie.vlan_id != 0) {
1248                         /*
1249                         *The VFTA is a 4096b bit-field, each identifying
1250                         *a single VLAN ID.  The following operations
1251                         *determine which 32b entry (i.e. offset) into the
1252                         *array we want to set the VLAN ID (i.e. bit) of
1253                         *the manageability unit.
1254                         */
1255                         vfta_offset = (hw->mng_cookie.vlan_id >>
1256                                 E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK;
1257                         vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
1258                                 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1259                 }
1260
1261                 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1262                         /*
1263                         *If the offset we want to clear is the same offset of
1264                         *the manageability VLAN ID, then clear all bits except
1265                         *that of the manageability unit
1266                         */
1267                         vfta_value = (offset == vfta_offset) ?
1268                                                         vfta_bit_in_reg : 0;
1269                         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset,
1270                                 vfta_value);
1271                         e1e_flush();
1272                 }
1273                 break;
1274         default:
1275                 break;
1276         }
1277 }
1278
1279 #if 0
1280 /**
1281  *  e1000e_check_mng_mode_82574 - Check manageability is enabled
1282  *  @hw: pointer to the HW structure
1283  *
1284  *  Reads the NVM Initialization Control Word 2 and returns true
1285  *  (>0) if any manageability is enabled, else false (0).
1286  **/
1287 static bool e1000e_check_mng_mode_82574(struct e1000_hw *hw)
1288 {
1289         u16 data;
1290
1291         e1000e_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1292         return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1293 }
1294 #endif
1295
1296 /**
1297  *  e1000e_led_on_82574 - Turn LED on
1298  *  @hw: pointer to the HW structure
1299  *
1300  *  Turn LED on.
1301  **/
1302 static s32 e1000e_led_on_82574(struct e1000_hw *hw __unused)
1303 {
1304 #if 0
1305         u32 ctrl;
1306         u32 i;
1307
1308         ctrl = hw->mac.ledctl_mode2;
1309         if (!(E1000_STATUS_LU & er32(STATUS))) {
1310                 /*
1311                  * If no link, then turn LED on by setting the invert bit
1312                  * for each LED that's "on" (0x0E) in ledctl_mode2.
1313                  */
1314                 for (i = 0; i < 4; i++)
1315                         if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1316                             E1000_LEDCTL_MODE_LED_ON)
1317                                 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1318         }
1319         ew32(LEDCTL, ctrl);
1320 #endif
1321         return E1000_SUCCESS;
1322 }
1323
1324 /**
1325  *  e1000e_setup_link_82571 - Setup flow control and link settings
1326  *  @hw: pointer to the HW structure
1327  *
1328  *  Determines which flow control settings to use, then configures flow
1329  *  control.  Calls the appropriate media-specific link configuration
1330  *  function.  Assuming the adapter has a valid link partner, a valid link
1331  *  should be established.  Assumes the hardware has previously been reset
1332  *  and the transmitter and receiver are not enabled.
1333  **/
1334 static s32 e1000e_setup_link_82571(struct e1000_hw *hw)
1335 {
1336         /*
1337          * 82573 does not have a word in the NVM to determine
1338          * the default flow control setting, so we explicitly
1339          * set it to full.
1340          */
1341         switch (hw->mac.type) {
1342         case e1000_82574:
1343         case e1000_82583:
1344         case e1000_82573:
1345                 if (hw->fc.requested_mode == e1000_fc_default)
1346                         hw->fc.requested_mode = e1000_fc_full;
1347                 break;
1348         default:
1349                 break;
1350         }
1351         return e1000e_setup_link(hw);
1352 }
1353
1354 /**
1355  *  e1000e_setup_copper_link_82571 - Configure copper link settings
1356  *  @hw: pointer to the HW structure
1357  *
1358  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1359  *  for link, once link is established calls to configure collision distance
1360  *  and flow control are called.
1361  **/
1362 static s32 e1000e_setup_copper_link_82571(struct e1000_hw *hw)
1363 {
1364         u32 ctrl;
1365         s32  ret_val;
1366
1367         ctrl = er32(CTRL);
1368         ctrl |= E1000_CTRL_SLU;
1369         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1370         ew32(CTRL, ctrl);
1371
1372         switch (hw->phy.type) {
1373         case e1000_phy_m88:
1374         case e1000_phy_bm:
1375                 ret_val = e1000e_copper_link_setup_m88(hw);
1376                 break;
1377         case e1000_phy_igp_2:
1378                 ret_val = e1000e_copper_link_setup_igp(hw);
1379                 break;
1380         default:
1381                 ret_val = -E1000_ERR_PHY;
1382                 break;
1383         }
1384
1385         if (ret_val)
1386                 goto out;
1387
1388         ret_val = e1000e_setup_copper_link(hw);
1389
1390 out:
1391         return ret_val;
1392 }
1393
1394 /**
1395  *  e1000e_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1396  *  @hw: pointer to the HW structure
1397  *
1398  *  Configures collision distance and flow control for fiber and serdes links.
1399  *  Upon successful setup, poll for link.
1400  **/
1401 static s32 e1000e_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1402 {
1403         switch (hw->mac.type) {
1404         case e1000_82571:
1405         case e1000_82572:
1406                 /*
1407                  * If SerDes loopback mode is entered, there is no form
1408                  * of reset to take the adapter out of that mode.  So we
1409                  * have to explicitly take the adapter out of loopback
1410                  * mode.  This prevents drivers from twiddling their thumbs
1411                  * if another tool failed to take it out of loopback mode.
1412                  */
1413                 ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1414                 break;
1415         default:
1416                 break;
1417         }
1418
1419         return e1000e_setup_fiber_serdes_link(hw);
1420 }
1421
1422 /**
1423  *  e1000e_check_for_serdes_link_82571 - Check for link (Serdes)
1424  *  @hw: pointer to the HW structure
1425  *
1426  *  Reports the link state as up or down.
1427  *
1428  *  If autonegotiation is supported by the link partner, the link state is
1429  *  determined by the result of autongotiation. This is the most likely case.
1430  *  If autonegotiation is not supported by the link partner, and the link
1431  *  has a valid signal, force the link up.
1432  *
1433  *  The link state is represented internally here by 4 states:
1434  *
1435  *  1) down
1436  *  2) autoneg_progress
1437  *  3) autoneg_complete (the link sucessfully autonegotiated)
1438  *  4) forced_up (the link has been forced up, it did not autonegotiate)
1439  *
1440  **/
1441 s32 e1000e_check_for_serdes_link_82571(struct e1000_hw *hw)
1442 {
1443         struct e1000_mac_info *mac = &hw->mac;
1444         u32 rxcw;
1445         u32 ctrl;
1446         u32 status;
1447         s32 ret_val = E1000_SUCCESS;
1448
1449         ctrl = er32(CTRL);
1450         status = er32(STATUS);
1451         rxcw = er32(RXCW);
1452
1453         if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1454
1455                 /* Receiver is synchronized with no invalid bits.  */
1456                 switch (mac->serdes_link_state) {
1457                 case e1000_serdes_link_autoneg_complete:
1458                         if (!(status & E1000_STATUS_LU)) {
1459                                 /*
1460                                  * We have lost link, retry autoneg before
1461                                  * reporting link failure
1462                                  */
1463                                 mac->serdes_link_state =
1464                                     e1000_serdes_link_autoneg_progress;
1465                                 mac->serdes_has_link = false;
1466                                 e_dbg("AN_UP     -> AN_PROG\n");
1467                         }
1468                 break;
1469
1470                 case e1000_serdes_link_forced_up:
1471                         /*
1472                          * If we are receiving /C/ ordered sets, re-enable
1473                          * auto-negotiation in the TXCW register and disable
1474                          * forced link in the Device Control register in an
1475                          * attempt to auto-negotiate with our link partner.
1476                          */
1477                         if (rxcw & E1000_RXCW_C) {
1478                                 /* Enable autoneg, and unforce link up */
1479                                 ew32(TXCW, mac->txcw);
1480                                 ew32(CTRL,
1481                                     (ctrl & ~E1000_CTRL_SLU));
1482                                 mac->serdes_link_state =
1483                                     e1000_serdes_link_autoneg_progress;
1484                                 mac->serdes_has_link = false;
1485                                 e_dbg("FORCED_UP -> AN_PROG\n");
1486                         }
1487                         break;
1488
1489                 case e1000_serdes_link_autoneg_progress:
1490                         if (rxcw & E1000_RXCW_C) {
1491                                 /* We received /C/ ordered sets, meaning the
1492                                  * link partner has autonegotiated, and we can
1493                                  * trust the Link Up (LU) status bit
1494                                  */
1495                                 if (status & E1000_STATUS_LU) {
1496                                         mac->serdes_link_state =
1497                                             e1000_serdes_link_autoneg_complete;
1498                                         e_dbg("AN_PROG   -> AN_UP\n");
1499                                         mac->serdes_has_link = true;
1500                                 } else {
1501                                         /* Autoneg completed, but failed */
1502                                         mac->serdes_link_state =
1503                                             e1000_serdes_link_down;
1504                                         e_dbg("AN_PROG   -> DOWN\n");
1505                                 }
1506                         } else {
1507                                 /* The link partner did not autoneg.
1508                                  * Force link up and full duplex, and change
1509                                  * state to forced.
1510                                  */
1511                                 ew32(TXCW,
1512                                 (mac->txcw & ~E1000_TXCW_ANE));
1513                                 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1514                                 ew32(CTRL, ctrl);
1515
1516                                 /* Configure Flow Control after link up. */
1517                                 ret_val =
1518                                     e1000e_config_fc_after_link_up(hw);
1519                                 if (ret_val) {
1520                                         e_dbg("Error config flow control\n");
1521                                         break;
1522                                 }
1523                                 mac->serdes_link_state =
1524                                 e1000_serdes_link_forced_up;
1525                                 mac->serdes_has_link = true;
1526                                 e_dbg("AN_PROG   -> FORCED_UP\n");
1527                         }
1528                         break;
1529
1530                 case e1000_serdes_link_down:
1531                 default:
1532                         /* The link was down but the receiver has now gained
1533                          * valid sync, so lets see if we can bring the link
1534                          * up. */
1535                         ew32(TXCW, mac->txcw);
1536                         ew32(CTRL,
1537                             (ctrl & ~E1000_CTRL_SLU));
1538                         mac->serdes_link_state =
1539                             e1000_serdes_link_autoneg_progress;
1540                         e_dbg("DOWN      -> AN_PROG\n");
1541                         break;
1542                 }
1543         } else {
1544                 if (!(rxcw & E1000_RXCW_SYNCH)) {
1545                         mac->serdes_has_link = false;
1546                         mac->serdes_link_state = e1000_serdes_link_down;
1547                         e_dbg("ANYSTATE  -> DOWN\n");
1548                 } else {
1549                         /*
1550                          * We have sync, and can tolerate one
1551                          * invalid (IV) codeword before declaring
1552                          * link down, so reread to look again
1553                          */
1554                         udelay(10);
1555                         rxcw = er32(RXCW);
1556                         if (rxcw & E1000_RXCW_IV) {
1557                                 mac->serdes_link_state = e1000_serdes_link_down;
1558                                 mac->serdes_has_link = false;
1559                                 e_dbg("ANYSTATE  -> DOWN\n");
1560                         }
1561                 }
1562         }
1563
1564         return ret_val;
1565 }
1566
1567 /**
1568  *  e1000e_valid_led_default_82571 - Verify a valid default LED config
1569  *  @hw: pointer to the HW structure
1570  *  @data: pointer to the NVM (EEPROM)
1571  *
1572  *  Read the EEPROM for the current default LED configuration.  If the
1573  *  LED configuration is not valid, set to a valid LED configuration.
1574  **/
1575 static s32 e1000e_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1576 {
1577         s32 ret_val;
1578
1579         ret_val = e1000e_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1580         if (ret_val) {
1581                 e_dbg("NVM Read Error\n");
1582                 goto out;
1583         }
1584
1585         switch (hw->mac.type) {
1586         case e1000_82574:
1587         case e1000_82583:
1588         case e1000_82573:
1589                 if(*data == ID_LED_RESERVED_F746)
1590                         *data = ID_LED_DEFAULT_82573;
1591                 break;
1592         default:
1593                 if (*data == ID_LED_RESERVED_0000 ||
1594                         *data == ID_LED_RESERVED_FFFF)
1595                         *data = ID_LED_DEFAULT;
1596                 break;
1597         }
1598
1599 out:
1600         return ret_val;
1601 }
1602
1603 /**
1604  *  e1000e_get_laa_state_82571 - Get locally administered address state
1605  *  @hw: pointer to the HW structure
1606  *
1607  *  Retrieve and return the current locally administered address state.
1608  **/
1609 bool e1000e_get_laa_state_82571(struct e1000_hw *hw)
1610 {
1611         if (hw->mac.type != e1000_82571)
1612                 return false;
1613
1614         return hw->dev_spec._82571.laa_is_present;
1615 }
1616
1617 /**
1618  *  e1000e_set_laa_state_82571 - Set locally administered address state
1619  *  @hw: pointer to the HW structure
1620  *  @state: enable/disable locally administered address
1621  *
1622  *  Enable/Disable the current locally administered address state.
1623  **/
1624 void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state)
1625 {
1626         if (hw->mac.type != e1000_82571)
1627                 return;
1628
1629         hw->dev_spec._82571.laa_is_present = state;
1630
1631         /* If workaround is activated... */
1632         if (state)
1633                 /*
1634                  * Hold a copy of the LAA in RAR[14] This is done so that
1635                  * between the time RAR[0] gets clobbered and the time it
1636                  * gets fixed, the actual LAA is in one of the RARs and no
1637                  * incoming packets directed to this port are dropped.
1638                  * Eventually the LAA will be in RAR[0] and RAR[14].
1639                  */
1640                 e1000e_rar_set(hw, hw->mac.addr,
1641                                       hw->mac.rar_entry_count - 1);
1642         return;
1643 }
1644
1645 /**
1646  *  e1000e_fix_nvm_checksum_82571 - Fix EEPROM checksum
1647  *  @hw: pointer to the HW structure
1648  *
1649  *  Verifies that the EEPROM has completed the update.  After updating the
1650  *  EEPROM, we need to check bit 15 in work 0x23 for the checksum fix.  If
1651  *  the checksum fix is not implemented, we need to set the bit and update
1652  *  the checksum.  Otherwise, if bit 15 is set and the checksum is incorrect,
1653  *  we need to return bad checksum.
1654  **/
1655 static s32 e1000e_fix_nvm_checksum_82571(struct e1000_hw *hw)
1656 {
1657         struct e1000_nvm_info *nvm = &hw->nvm;
1658         s32 ret_val = E1000_SUCCESS;
1659         u16 data;
1660
1661         if (nvm->type != e1000_nvm_flash_hw)
1662                 goto out;
1663
1664         /*
1665          * Check bit 4 of word 10h.  If it is 0, firmware is done updating
1666          * 10h-12h.  Checksum may need to be fixed.
1667          */
1668         ret_val = e1000e_read_nvm(hw, 0x10, 1, &data);
1669         if (ret_val)
1670                 goto out;
1671
1672         if (!(data & 0x10)) {
1673                 /*
1674                  * Read 0x23 and check bit 15.  This bit is a 1
1675                  * when the checksum has already been fixed.  If
1676                  * the checksum is still wrong and this bit is a
1677                  * 1, we need to return bad checksum.  Otherwise,
1678                  * we need to set this bit to a 1 and update the
1679                  * checksum.
1680                  */
1681                 ret_val = e1000e_read_nvm(hw, 0x23, 1, &data);
1682                 if (ret_val)
1683                         goto out;
1684
1685                 if (!(data & 0x8000)) {
1686                         data |= 0x8000;
1687                         ret_val = e1000e_write_nvm(hw, 0x23, 1, &data);
1688                         if (ret_val)
1689                                 goto out;
1690                         ret_val = e1000e_update_nvm_checksum(hw);
1691                 }
1692         }
1693
1694 out:
1695         return ret_val;
1696 }
1697
1698 /**
1699  *  e1000e_read_mac_addr_82571 - Read device MAC address
1700  *  @hw: pointer to the HW structure
1701  **/
1702 static s32 e1000e_read_mac_addr_82571(struct e1000_hw *hw)
1703 {
1704         s32 ret_val = E1000_SUCCESS;
1705
1706         /*
1707          * If there's an alternate MAC address place it in RAR0
1708          * so that it will override the Si installed default perm
1709          * address.
1710          */
1711         ret_val = e1000e_check_alt_mac_addr_generic(hw);
1712         if (ret_val)
1713                 goto out;
1714
1715         ret_val = e1000e_read_mac_addr_generic(hw);
1716
1717 out:
1718         return ret_val;
1719 }
1720
1721 /**
1722  * e1000e_power_down_phy_copper_82571 - Remove link during PHY power down
1723  * @hw: pointer to the HW structure
1724  *
1725  * In the case of a PHY power down to save power, or to turn off link during a
1726  * driver unload, or wake on lan is not enabled, remove the link.
1727  **/
1728 static void e1000e_power_down_phy_copper_82571(struct e1000_hw *hw)
1729 {
1730         struct e1000_phy_info *phy = &hw->phy;
1731         struct e1000_mac_info *mac = &hw->mac;
1732
1733         if (!(phy->ops.check_reset_block))
1734                 return;
1735
1736         /* If the management interface is not enabled, then power down */
1737         if (!(mac->ops.check_mng_mode(hw) || e1000e_check_reset_block(hw)))
1738                 e1000e_power_down_phy_copper(hw);
1739
1740         return;
1741 }
1742
1743 /**
1744  *  e1000e_clear_hw_cntrs_82571 - Clear device specific hardware counters
1745  *  @hw: pointer to the HW structure
1746  *
1747  *  Clears the hardware counters by reading the counter registers.
1748  **/
1749 static void e1000e_clear_hw_cntrs_82571(struct e1000_hw *hw __unused)
1750 {
1751 #if 0
1752         e1000e_clear_hw_cntrs_base(hw);
1753
1754         er32(PRC64);
1755         er32(PRC127);
1756         er32(PRC255);
1757         er32(PRC511);
1758         er32(PRC1023);
1759         er32(PRC1522);
1760         er32(PTC64);
1761         er32(PTC127);
1762         er32(PTC255);
1763         er32(PTC511);
1764         er32(PTC1023);
1765         er32(PTC1522);
1766
1767         er32(ALGNERRC);
1768         er32(RXERRC);
1769         er32(TNCRS);
1770         er32(CEXTERR);
1771         er32(TSCTC);
1772         er32(TSCTFC);
1773
1774         er32(MGTPRC);
1775         er32(MGTPDC);
1776         er32(MGTPTC);
1777
1778         er32(IAC);
1779         er32(ICRXOC);
1780
1781         er32(ICRXPTC);
1782         er32(ICRXATC);
1783         er32(ICTXPTC);
1784         er32(ICTXATC);
1785         er32(ICTXQEC);
1786         er32(ICTXQMTC);
1787         er32(ICRXDMTC);
1788 #endif
1789 }
1790
1791 static struct pci_device_id e1000e_82571_nics[] = {
1792      PCI_ROM(0x8086, 0x105E, "E1000_DEV_ID_82571EB_COPPER", "E1000_DEV_ID_82571EB_COPPER", board_82571),
1793      PCI_ROM(0x8086, 0x105F, "E1000_DEV_ID_82571EB_FIBER", "E1000_DEV_ID_82571EB_FIBER", board_82571),
1794      PCI_ROM(0x8086, 0x10A4, "E1000_DEV_ID_82571EB_QUAD_COPPER", "E1000_DEV_ID_82571EB_QUAD_COPPER", board_82571),
1795      PCI_ROM(0x8086, 0x10BC, "E1000_DEV_ID_82571EB_QUAD_COPPER_LP", "E1000_DEV_ID_82571EB_QUAD_COPPER_LP", board_82571),
1796      PCI_ROM(0x8086, 0x10A5, "E1000_DEV_ID_82571EB_QUAD_FIBER", "E1000_DEV_ID_82571EB_QUAD_FIBER", board_82571),
1797      PCI_ROM(0x8086, 0x1060, "E1000_DEV_ID_82571EB_SERDES", "E1000_DEV_ID_82571EB_SERDES", board_82571),
1798      PCI_ROM(0x8086, 0x10D9, "E1000_DEV_ID_82571EB_SERDES_DUAL", "E1000_DEV_ID_82571EB_SERDES_DUAL", board_82571),
1799      PCI_ROM(0x8086, 0x10DA, "E1000_DEV_ID_82571EB_SERDES_QUAD", "E1000_DEV_ID_82571EB_SERDES_QUAD", board_82571),
1800      PCI_ROM(0x8086, 0x10D5, "E1000_DEV_ID_82571PT_QUAD_COPPER", "E1000_DEV_ID_82571PT_QUAD_COPPER", board_82571),
1801      PCI_ROM(0x8086, 0x10B9, "E1000_DEV_ID_82572EI", "E1000_DEV_ID_82572EI", board_82572),
1802      PCI_ROM(0x8086, 0x107D, "E1000_DEV_ID_82572EI_COPPER", "E1000_DEV_ID_82572EI_COPPER", board_82572),
1803      PCI_ROM(0x8086, 0x107E, "E1000_DEV_ID_82572EI_FIBER", "E1000_DEV_ID_82572EI_FIBER", board_82572),
1804      PCI_ROM(0x8086, 0x107F, "E1000_DEV_ID_82572EI_SERDES", "E1000_DEV_ID_82572EI_SERDES", board_82572),
1805      PCI_ROM(0x8086, 0x108B, "E1000_DEV_ID_82573E", "E1000_DEV_ID_82573E", board_82573),
1806      PCI_ROM(0x8086, 0x108C, "E1000_DEV_ID_82573E_IAMT", "E1000_DEV_ID_82573E_IAMT", board_82573),
1807      PCI_ROM(0x8086, 0x109A, "E1000_DEV_ID_82573L", "E1000_DEV_ID_82573L", board_82573),
1808      PCI_ROM(0x8086, 0x10D3, "E1000_DEV_ID_82574L", "E1000_DEV_ID_82574L", board_82574),
1809      PCI_ROM(0x8086, 0x10F6, "E1000_DEV_ID_82574LA", "E1000_DEV_ID_82574LA", board_82574),
1810      PCI_ROM(0x8086, 0x150C, "E1000_DEV_ID_82583V", "E1000_DEV_ID_82583V", board_82583),
1811 };
1812
1813 struct pci_driver e1000e_82571_driver __pci_driver = {
1814         .ids = e1000e_82571_nics,
1815         .id_count = (sizeof (e1000e_82571_nics) / sizeof (e1000e_82571_nics[0])),
1816         .probe = e1000e_probe,
1817         .remove = e1000e_remove,
1818 };