[e1000e] Add e1000e driver
[people/pcmattman/gpxe.git] / src / drivers / net / e1000e / e1000e_80003es2lan.c
1 /*******************************************************************************
2
3   Intel PRO/1000 Linux driver
4   Copyright(c) 1999 - 2009 Intel Corporation.
5
6   This program is free software; you can redistribute it and/or modify it
7   under the terms and conditions of the GNU General Public License,
8   version 2, as published by the Free Software Foundation.
9
10   This program is distributed in the hope it will be useful, but WITHOUT
11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13   more details.
14
15   You should have received a copy of the GNU General Public License along with
16   this program; if not, write to the Free Software Foundation, Inc.,
17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19   The full GNU General Public License is included in this distribution in
20   the file called "COPYING".
21
22   Contact Information:
23   Linux NICS <linux.nics@intel.com>
24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 FILE_LICENCE ( GPL2_OR_LATER );
30
31 /*
32  * 80003ES2LAN Gigabit Ethernet Controller (Copper)
33  * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
34  */
35
36 #include "e1000e.h"
37
38 static s32  e1000e_init_phy_params_80003es2lan(struct e1000_hw *hw);
39 static s32  e1000e_init_nvm_params_80003es2lan(struct e1000_hw *hw);
40 static s32  e1000e_init_mac_params_80003es2lan(struct e1000_hw *hw);
41 static s32  e1000e_acquire_phy_80003es2lan(struct e1000_hw *hw);
42 static void e1000e_release_phy_80003es2lan(struct e1000_hw *hw);
43 static s32  e1000e_acquire_nvm_80003es2lan(struct e1000_hw *hw);
44 static void e1000e_release_nvm_80003es2lan(struct e1000_hw *hw);
45 static s32  e1000e_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
46                                                    u32 offset,
47                                                    u16 *data);
48 static s32  e1000e_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
49                                                     u32 offset,
50                                                     u16 data);
51 static s32  e1000e_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
52                                         u16 words, u16 *data);
53 static s32  e1000e_get_cfg_done_80003es2lan(struct e1000_hw *hw);
54 #if 0
55 static s32  e1000e_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw);
56 #endif
57 #if 0
58 static s32  e1000e_get_cable_length_80003es2lan(struct e1000_hw *hw);
59 #endif
60 static s32  e1000e_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
61                                                u16 *duplex);
62 static s32  e1000e_reset_hw_80003es2lan(struct e1000_hw *hw);
63 static s32  e1000e_init_hw_80003es2lan(struct e1000_hw *hw);
64 static s32  e1000e_setup_copper_link_80003es2lan(struct e1000_hw *hw);
65 static void e1000e_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
66 static s32  e1000e_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
67 static s32  e1000e_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
68 static s32  e1000e_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
69 static s32  e1000e_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);
70 static s32  e1000e_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
71                                             u16 *data);
72 static s32  e1000e_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
73                                              u16 data);
74 static s32  e1000e_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw);
75 static void e1000e_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
76 static void e1000e_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
77 static s32  e1000e_read_mac_addr_80003es2lan(struct e1000_hw *hw);
78 static void e1000e_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
79
80 #if 0
81 /*
82  * A table for the GG82563 cable length where the range is defined
83  * with a lower bound at "index" and the upper bound at
84  * "index + 5".
85  */
86 static const u16 e1000_gg82563_cable_length_table[] =
87          { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
88 #define GG82563_CABLE_LENGTH_TABLE_SIZE \
89                 (sizeof(e1000_gg82563_cable_length_table) / \
90                  sizeof(e1000_gg82563_cable_length_table[0]))
91 #endif
92
93 /**
94  *  e1000e_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
95  *  @hw: pointer to the HW structure
96  **/
97 static s32 e1000e_init_phy_params_80003es2lan(struct e1000_hw *hw)
98 {
99         struct e1000_phy_info *phy = &hw->phy;
100         s32 ret_val = E1000_SUCCESS;
101
102         if (hw->phy.media_type != e1000_media_type_copper) {
103                 phy->type        = e1000_phy_none;
104                 goto out;
105         } else {
106                 phy->ops.power_up = e1000e_power_up_phy_copper;
107                 phy->ops.power_down = e1000e_power_down_phy_copper_80003es2lan;
108         }
109
110         phy->addr                = 1;
111         phy->autoneg_mask        = AUTONEG_ADVERTISE_SPEED_DEFAULT;
112         phy->reset_delay_us      = 100;
113         phy->type                = e1000_phy_gg82563;
114
115         phy->ops.acquire            = e1000e_acquire_phy_80003es2lan;
116         phy->ops.check_polarity     = e1000e_check_polarity_m88;
117         phy->ops.check_reset_block  = e1000e_check_reset_block_generic;
118         phy->ops.commit             = e1000e_phy_sw_reset;
119         phy->ops.get_cfg_done       = e1000e_get_cfg_done_80003es2lan;
120         phy->ops.get_info           = e1000e_get_phy_info_m88;
121         phy->ops.release            = e1000e_release_phy_80003es2lan;
122         phy->ops.reset              = e1000e_phy_hw_reset_generic;
123         phy->ops.set_d3_lplu_state  = e1000e_set_d3_lplu_state;
124 #if 0
125         phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_80003es2lan;
126 #endif
127 #if 0
128         phy->ops.get_cable_length   = e1000e_get_cable_length_80003es2lan;
129 #endif
130         phy->ops.read_reg           = e1000e_read_phy_reg_gg82563_80003es2lan;
131         phy->ops.write_reg          = e1000e_write_phy_reg_gg82563_80003es2lan;
132
133         phy->ops.cfg_on_link_up    = e1000e_cfg_on_link_up_80003es2lan;
134
135         /* This can only be done after all function pointers are setup. */
136         ret_val = e1000e_get_phy_id(hw);
137
138         /* Verify phy id */
139         if (phy->id != GG82563_E_PHY_ID) {
140                 ret_val = -E1000_ERR_PHY;
141                 goto out;
142         }
143
144 out:
145         return ret_val;
146 }
147
148 /**
149  *  e1000e_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
150  *  @hw: pointer to the HW structure
151  **/
152 static s32 e1000e_init_nvm_params_80003es2lan(struct e1000_hw *hw)
153 {
154         struct e1000_nvm_info *nvm = &hw->nvm;
155         u32 eecd = er32(EECD);
156         u16 size;
157
158         nvm->opcode_bits        = 8;
159         nvm->delay_usec         = 1;
160         switch (nvm->override) {
161         case e1000_nvm_override_spi_large:
162                 nvm->page_size    = 32;
163                 nvm->address_bits = 16;
164                 break;
165         case e1000_nvm_override_spi_small:
166                 nvm->page_size    = 8;
167                 nvm->address_bits = 8;
168                 break;
169         default:
170                 nvm->page_size    = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
171                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
172                 break;
173         }
174
175         nvm->type               = e1000_nvm_eeprom_spi;
176
177         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
178                           E1000_EECD_SIZE_EX_SHIFT);
179
180         /*
181          * Added to a constant, "size" becomes the left-shift value
182          * for setting word_size.
183          */
184         size += NVM_WORD_SIZE_BASE_SHIFT;
185
186         /* EEPROM access above 16k is unsupported */
187         if (size > 14)
188                 size = 14;
189         nvm->word_size  = 1 << size;
190
191         /* Function Pointers */
192         nvm->ops.acquire           = e1000e_acquire_nvm_80003es2lan;
193         nvm->ops.read              = e1000e_read_nvm_eerd;
194         nvm->ops.release           = e1000e_release_nvm_80003es2lan;
195         nvm->ops.update            = e1000e_update_nvm_checksum_generic;
196         nvm->ops.valid_led_default = e1000e_valid_led_default;
197         nvm->ops.validate          = e1000e_validate_nvm_checksum_generic;
198         nvm->ops.write             = e1000e_write_nvm_80003es2lan;
199
200         return E1000_SUCCESS;
201 }
202
203 /**
204  *  e1000e_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
205  *  @hw: pointer to the HW structure
206  **/
207 static s32 e1000e_init_mac_params_80003es2lan(struct e1000_hw *hw)
208 {
209         struct e1000_mac_info *mac = &hw->mac;
210         s32 ret_val = E1000_SUCCESS;
211
212         /* Set media type */
213         switch (hw->device_id) {
214         case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
215                 hw->phy.media_type = e1000_media_type_internal_serdes;
216                 break;
217         default:
218                 hw->phy.media_type = e1000_media_type_copper;
219                 break;
220         }
221
222         /* Set mta register count */
223         mac->mta_reg_count = 128;
224         /* Set rar entry count */
225         mac->rar_entry_count = E1000_RAR_ENTRIES;
226         /* Set if part includes ASF firmware */
227         mac->asf_firmware_present = true;
228         /* Set if manageability features are enabled. */
229         mac->arc_subsystem_valid =
230                 (er32(FWSM) & E1000_FWSM_MODE_MASK)
231                         ? true : false;
232
233         /* Function pointers */
234
235         /* bus type/speed/width */
236         mac->ops.get_bus_info = e1000e_get_bus_info_pcie;
237         /* reset */
238         mac->ops.reset_hw = e1000e_reset_hw_80003es2lan;
239         /* hw initialization */
240         mac->ops.init_hw = e1000e_init_hw_80003es2lan;
241         /* link setup */
242         mac->ops.setup_link = e1000e_setup_link;
243         /* physical interface link setup */
244         mac->ops.setup_physical_interface =
245                 (hw->phy.media_type == e1000_media_type_copper)
246                         ? e1000e_setup_copper_link_80003es2lan
247                         : e1000e_setup_fiber_serdes_link;
248         /* check for link */
249         switch (hw->phy.media_type) {
250         case e1000_media_type_copper:
251                 mac->ops.check_for_link = e1000e_check_for_copper_link;
252                 break;
253         case e1000_media_type_fiber:
254                 mac->ops.check_for_link = e1000e_check_for_fiber_link;
255                 break;
256         case e1000_media_type_internal_serdes:
257                 mac->ops.check_for_link = e1000e_check_for_serdes_link;
258                 break;
259         default:
260                 ret_val = -E1000_ERR_CONFIG;
261                 goto out;
262                 break;
263         }
264         /* check management mode */
265 #if 0
266         mac->ops.check_mng_mode = e1000e_check_mng_mode_generic;
267 #endif
268         /* multicast address update */
269         mac->ops.update_mc_addr_list = e1000e_update_mc_addr_list_generic;
270         /* writing VFTA */
271         mac->ops.write_vfta = e1000e_write_vfta_generic;
272         /* clearing VFTA */
273         mac->ops.clear_vfta = e1000e_clear_vfta_generic;
274         /* setting MTA */
275         mac->ops.mta_set = e1000e_mta_set_generic;
276         /* read mac address */
277         mac->ops.read_mac_addr = e1000e_read_mac_addr_80003es2lan;
278         /* ID LED init */
279         mac->ops.id_led_init = e1000e_id_led_init;
280         /* blink LED */
281         mac->ops.blink_led = e1000e_blink_led;
282         /* setup LED */
283         mac->ops.setup_led = e1000e_setup_led_generic;
284         /* cleanup LED */
285         mac->ops.cleanup_led = e1000e_cleanup_led_generic;
286         /* turn on/off LED */
287         mac->ops.led_on = e1000e_led_on_generic;
288         mac->ops.led_off = e1000e_led_off_generic;
289         /* clear hardware counters */
290         mac->ops.clear_hw_cntrs = e1000e_clear_hw_cntrs_80003es2lan;
291         /* link info */
292         mac->ops.get_link_up_info = e1000e_get_link_up_info_80003es2lan;
293
294         /* set lan id for port to determine which phy lock to use */
295         hw->mac.ops.set_lan_id(hw);
296
297 out:
298         return ret_val;
299 }
300
301 /**
302  *  e1000e_init_function_pointers_80003es2lan - Init ESB2 func ptrs.
303  *  @hw: pointer to the HW structure
304  *
305  *  Called to initialize all function pointers and parameters.
306  **/
307 void e1000e_init_function_pointers_80003es2lan(struct e1000_hw *hw)
308 {
309         e1000e_init_mac_ops_generic(hw);
310         e1000e_init_nvm_ops_generic(hw);
311         hw->mac.ops.init_params = e1000e_init_mac_params_80003es2lan;
312         hw->nvm.ops.init_params = e1000e_init_nvm_params_80003es2lan;
313         hw->phy.ops.init_params = e1000e_init_phy_params_80003es2lan;
314 }
315
316 /**
317  *  e1000e_acquire_phy_80003es2lan - Acquire rights to access PHY
318  *  @hw: pointer to the HW structure
319  *
320  *  A wrapper to acquire access rights to the correct PHY.
321  **/
322 static s32 e1000e_acquire_phy_80003es2lan(struct e1000_hw *hw)
323 {
324         u16 mask;
325
326         mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
327         return e1000e_acquire_swfw_sync_80003es2lan(hw, mask);
328 }
329
330 /**
331  *  e1000e_release_phy_80003es2lan - Release rights to access PHY
332  *  @hw: pointer to the HW structure
333  *
334  *  A wrapper to release access rights to the correct PHY.
335  **/
336 static void e1000e_release_phy_80003es2lan(struct e1000_hw *hw)
337 {
338         u16 mask;
339
340         mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
341         e1000e_release_swfw_sync_80003es2lan(hw, mask);
342 }
343
344 /**
345  *  e1000e_acquire_mac_csr_80003es2lan - Acquire rights to access Kumeran register
346  *  @hw: pointer to the HW structure
347  *
348  *  Acquire the semaphore to access the Kumeran interface.
349  *
350  **/
351 static s32 e1000e_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
352 {
353         u16 mask;
354
355         mask = E1000_SWFW_CSR_SM;
356
357         return e1000e_acquire_swfw_sync_80003es2lan(hw, mask);
358 }
359
360 /**
361  *  e1000e_release_mac_csr_80003es2lan - Release rights to access Kumeran Register
362  *  @hw: pointer to the HW structure
363  *
364  *  Release the semaphore used to access the Kumeran interface
365  **/
366 static void e1000e_release_mac_csr_80003es2lan(struct e1000_hw *hw)
367 {
368         u16 mask;
369
370         mask = E1000_SWFW_CSR_SM;
371
372         e1000e_release_swfw_sync_80003es2lan(hw, mask);
373 }
374
375 /**
376  *  e1000e_acquire_nvm_80003es2lan - Acquire rights to access NVM
377  *  @hw: pointer to the HW structure
378  *
379  *  Acquire the semaphore to access the EEPROM.
380  **/
381 static s32 e1000e_acquire_nvm_80003es2lan(struct e1000_hw *hw)
382 {
383         s32 ret_val;
384
385         ret_val = e1000e_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
386         if (ret_val)
387                 goto out;
388
389         ret_val = e1000e_acquire_nvm(hw);
390
391         if (ret_val)
392                 e1000e_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
393
394 out:
395         return ret_val;
396 }
397
398 /**
399  *  e1000e_release_nvm_80003es2lan - Relinquish rights to access NVM
400  *  @hw: pointer to the HW structure
401  *
402  *  Release the semaphore used to access the EEPROM.
403  **/
404 static void e1000e_release_nvm_80003es2lan(struct e1000_hw *hw)
405 {
406         e1000e_release_nvm(hw);
407         e1000e_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
408 }
409
410 /**
411  *  e1000e_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
412  *  @hw: pointer to the HW structure
413  *  @mask: specifies which semaphore to acquire
414  *
415  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
416  *  will also specify which port we're acquiring the lock for.
417  **/
418 static s32 e1000e_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
419 {
420         u32 swfw_sync;
421         u32 swmask = mask;
422         u32 fwmask = mask << 16;
423         s32 ret_val = E1000_SUCCESS;
424         s32 i = 0, timeout = 50;
425
426         while (i < timeout) {
427                 if (e1000e_get_hw_semaphore(hw)) {
428                         ret_val = -E1000_ERR_SWFW_SYNC;
429                         goto out;
430                 }
431
432                 swfw_sync = er32(SW_FW_SYNC);
433                 if (!(swfw_sync & (fwmask | swmask)))
434                         break;
435
436                 /*
437                  * Firmware currently using resource (fwmask)
438                  * or other software thread using resource (swmask)
439                  */
440                 e1000e_put_hw_semaphore(hw);
441                 mdelay(5);
442                 i++;
443         }
444
445         if (i == timeout) {
446                 e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
447                 ret_val = -E1000_ERR_SWFW_SYNC;
448                 goto out;
449         }
450
451         swfw_sync |= swmask;
452         ew32(SW_FW_SYNC, swfw_sync);
453
454         e1000e_put_hw_semaphore(hw);
455
456 out:
457         return ret_val;
458 }
459
460 /**
461  *  e1000e_release_swfw_sync_80003es2lan - Release SW/FW semaphore
462  *  @hw: pointer to the HW structure
463  *  @mask: specifies which semaphore to acquire
464  *
465  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
466  *  will also specify which port we're releasing the lock for.
467  **/
468 static void e1000e_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
469 {
470         u32 swfw_sync;
471
472         while (e1000e_get_hw_semaphore(hw) != E1000_SUCCESS)
473                 ; /* Empty */
474
475         swfw_sync = er32(SW_FW_SYNC);
476         swfw_sync &= ~mask;
477         ew32(SW_FW_SYNC, swfw_sync);
478
479         e1000e_put_hw_semaphore(hw);
480 }
481
482 /**
483  *  e1000e_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
484  *  @hw: pointer to the HW structure
485  *  @offset: offset of the register to read
486  *  @data: pointer to the data returned from the operation
487  *
488  *  Read the GG82563 PHY register.
489  **/
490 static s32 e1000e_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
491                                                   u32 offset, u16 *data)
492 {
493         s32 ret_val;
494         u32 page_select;
495         u16 temp;
496
497         ret_val = e1000e_acquire_phy_80003es2lan(hw);
498         if (ret_val)
499                 goto out;
500
501         /* Select Configuration Page */
502         if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
503                 page_select = GG82563_PHY_PAGE_SELECT;
504         } else {
505                 /*
506                  * Use Alternative Page Select register to access
507                  * registers 30 and 31
508                  */
509                 page_select = GG82563_PHY_PAGE_SELECT_ALT;
510         }
511
512         temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
513         ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
514         if (ret_val) {
515                 e1000e_release_phy_80003es2lan(hw);
516                 goto out;
517         }
518
519         if (hw->dev_spec._80003es2lan.mdic_wa_enable == true) {
520                 /*
521                  * The "ready" bit in the MDIC register may be incorrectly set
522                  * before the device has completed the "Page Select" MDI
523                  * transaction.  So we wait 200us after each MDI command...
524                  */
525                 udelay(200);
526
527                 /* ...and verify the command was successful. */
528                 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
529
530                 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
531                         ret_val = -E1000_ERR_PHY;
532                         e1000e_release_phy_80003es2lan(hw);
533                         goto out;
534                 }
535
536                 udelay(200);
537
538                 ret_val = e1000e_read_phy_reg_mdic(hw,
539                                                   MAX_PHY_REG_ADDRESS & offset,
540                                                   data);
541
542                 udelay(200);
543         } else
544                 ret_val = e1000e_read_phy_reg_mdic(hw,
545                                                   MAX_PHY_REG_ADDRESS & offset,
546                                                   data);
547
548         e1000e_release_phy_80003es2lan(hw);
549
550 out:
551         return ret_val;
552 }
553
554 /**
555  *  e1000e_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
556  *  @hw: pointer to the HW structure
557  *  @offset: offset of the register to read
558  *  @data: value to write to the register
559  *
560  *  Write to the GG82563 PHY register.
561  **/
562 static s32 e1000e_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
563                                                    u32 offset, u16 data)
564 {
565         s32 ret_val;
566         u32 page_select;
567         u16 temp;
568
569         ret_val = e1000e_acquire_phy_80003es2lan(hw);
570         if (ret_val)
571                 goto out;
572
573         /* Select Configuration Page */
574         if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
575                 page_select = GG82563_PHY_PAGE_SELECT;
576         } else {
577                 /*
578                  * Use Alternative Page Select register to access
579                  * registers 30 and 31
580                  */
581                 page_select = GG82563_PHY_PAGE_SELECT_ALT;
582         }
583
584         temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
585         ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
586         if (ret_val) {
587                 e1000e_release_phy_80003es2lan(hw);
588                 goto out;
589         }
590
591         if (hw->dev_spec._80003es2lan.mdic_wa_enable == true) {
592                 /*
593                  * The "ready" bit in the MDIC register may be incorrectly set
594                  * before the device has completed the "Page Select" MDI
595                  * transaction.  So we wait 200us after each MDI command...
596                  */
597                 udelay(200);
598
599                 /* ...and verify the command was successful. */
600                 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
601
602                 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
603                         ret_val = -E1000_ERR_PHY;
604                         e1000e_release_phy_80003es2lan(hw);
605                         goto out;
606                 }
607
608                 udelay(200);
609
610                 ret_val = e1000e_write_phy_reg_mdic(hw,
611                                                   MAX_PHY_REG_ADDRESS & offset,
612                                                   data);
613
614                 udelay(200);
615         } else
616                 ret_val = e1000e_write_phy_reg_mdic(hw,
617                                                   MAX_PHY_REG_ADDRESS & offset,
618                 data);
619
620         e1000e_release_phy_80003es2lan(hw);
621
622 out:
623         return ret_val;
624 }
625
626 /**
627  *  e1000e_write_nvm_80003es2lan - Write to ESB2 NVM
628  *  @hw: pointer to the HW structure
629  *  @offset: offset of the register to read
630  *  @words: number of words to write
631  *  @data: buffer of data to write to the NVM
632  *
633  *  Write "words" of data to the ESB2 NVM.
634  **/
635 static s32 e1000e_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
636                             u16 words, u16 *data)
637 {
638         return e1000e_write_nvm_spi(hw, offset, words, data);
639 }
640
641 /**
642  *  e1000e_get_cfg_done_80003es2lan - Wait for configuration to complete
643  *  @hw: pointer to the HW structure
644  *
645  *  Wait a specific amount of time for manageability processes to complete.
646  *  This is a function pointer entry point called by the phy module.
647  **/
648 static s32 e1000e_get_cfg_done_80003es2lan(struct e1000_hw *hw)
649 {
650         s32 timeout = PHY_CFG_TIMEOUT;
651         s32 ret_val = E1000_SUCCESS;
652         u32 mask = E1000_NVM_CFG_DONE_PORT_0;
653
654         if (hw->bus.func == 1)
655                 mask = E1000_NVM_CFG_DONE_PORT_1;
656
657         while (timeout) {
658                 if (er32(EEMNGCTL) & mask)
659                         break;
660                 msleep(1);
661                 timeout--;
662         }
663         if (!timeout) {
664                 e_dbg("MNG configuration cycle has not completed.\n");
665                 ret_val = -E1000_ERR_RESET;
666                 goto out;
667         }
668
669 out:
670         return ret_val;
671 }
672 #if 0
673 /**
674  *  e1000e_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
675  *  @hw: pointer to the HW structure
676  *
677  *  Force the speed and duplex settings onto the PHY.  This is a
678  *  function pointer entry point called by the phy module.
679  **/
680 static s32 e1000e_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
681 {
682         s32 ret_val = E1000_SUCCESS;
683         u16 phy_data;
684         bool link;
685
686         if (!(hw->phy.ops.read_reg))
687                 goto out;
688
689         /*
690          * Clear Auto-Crossover to force MDI manually.  M88E1000 requires MDI
691          * forced whenever speed and duplex are forced.
692          */
693         ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
694         if (ret_val)
695                 goto out;
696
697         phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
698         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data);
699         if (ret_val)
700                 goto out;
701
702         e_dbg("GG82563 PSCR: %X\n", phy_data);
703
704         ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
705         if (ret_val)
706                 goto out;
707
708         e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
709
710         /* Reset the phy to commit changes. */
711         phy_data |= MII_CR_RESET;
712
713         ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
714         if (ret_val)
715                 goto out;
716
717         udelay(1);
718
719         if (hw->phy.autoneg_wait_to_complete) {
720                 e_dbg("Waiting for forced speed/duplex link "
721                          "on GG82563 phy.\n");
722
723                 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
724                                                      100000, &link);
725                 if (ret_val)
726                         goto out;
727
728                 if (!link) {
729                         /*
730                          * We didn't get link.
731                          * Reset the DSP and cross our fingers.
732                          */
733                         ret_val = e1000e_phy_reset_dsp(hw);
734                         if (ret_val)
735                                 goto out;
736                 }
737
738                 /* Try once more */
739                 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
740                                                      100000, &link);
741                 if (ret_val)
742                         goto out;
743         }
744
745         ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
746         if (ret_val)
747                 goto out;
748
749         /*
750          * Resetting the phy means we need to verify the TX_CLK corresponds
751          * to the link speed.  10Mbps -> 2.5MHz, else 25MHz.
752          */
753         phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
754         if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
755                 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
756         else
757                 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
758
759         /*
760          * In addition, we must re-enable CRS on Tx for both half and full
761          * duplex.
762          */
763         phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
764         ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
765
766 out:
767         return ret_val;
768 }
769 #endif
770
771 #if 0
772 /**
773  *  e1000e_get_cable_length_80003es2lan - Set approximate cable length
774  *  @hw: pointer to the HW structure
775  *
776  *  Find the approximate cable length as measured by the GG82563 PHY.
777  *  This is a function pointer entry point called by the phy module.
778  **/
779 static s32 e1000e_get_cable_length_80003es2lan(struct e1000_hw *hw)
780 {
781         struct e1000_phy_info *phy = &hw->phy;
782         s32 ret_val = E1000_SUCCESS;
783         u16 phy_data, index;
784
785         if (!(hw->phy.ops.read_reg))
786                 goto out;
787
788         ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
789         if (ret_val)
790                 goto out;
791
792         index = phy_data & GG82563_DSPD_CABLE_LENGTH;
793
794         if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5) {
795                 ret_val = -E1000_ERR_PHY;
796                 goto out;
797         }
798
799         phy->min_cable_length = e1000_gg82563_cable_length_table[index];
800         phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];
801
802         phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
803
804 out:
805         return ret_val;
806 }
807 #endif
808
809 /**
810  *  e1000e_get_link_up_info_80003es2lan - Report speed and duplex
811  *  @hw: pointer to the HW structure
812  *  @speed: pointer to speed buffer
813  *  @duplex: pointer to duplex buffer
814  *
815  *  Retrieve the current speed and duplex configuration.
816  **/
817 static s32 e1000e_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
818                                               u16 *duplex)
819 {
820         s32 ret_val;
821
822         if (hw->phy.media_type == e1000_media_type_copper) {
823                 ret_val = e1000e_get_speed_and_duplex_copper(hw,
824                                                                     speed,
825                                                                     duplex);
826                 hw->phy.ops.cfg_on_link_up(hw);
827         } else {
828                 ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw,
829                                                                   speed,
830                                                                   duplex);
831         }
832
833         return ret_val;
834 }
835
836 /**
837  *  e1000e_reset_hw_80003es2lan - Reset the ESB2 controller
838  *  @hw: pointer to the HW structure
839  *
840  *  Perform a global reset to the ESB2 controller.
841  **/
842 static s32 e1000e_reset_hw_80003es2lan(struct e1000_hw *hw)
843 {
844         u32 ctrl, icr;
845         s32 ret_val;
846
847         /*
848          * Prevent the PCI-E bus from sticking if there is no TLP connection
849          * on the last TLP read/write transaction when MAC is reset.
850          */
851         ret_val = e1000e_disable_pcie_master(hw);
852         if (ret_val)
853                 e_dbg("PCI-E Master disable polling has failed.\n");
854
855         e_dbg("Masking off all interrupts\n");
856         ew32(IMC, 0xffffffff);
857
858         ew32(RCTL, 0);
859         ew32(TCTL, E1000_TCTL_PSP);
860         e1e_flush();
861
862         msleep(10);
863
864         ctrl = er32(CTRL);
865
866         ret_val = e1000e_acquire_phy_80003es2lan(hw);
867         e_dbg("Issuing a global reset to MAC\n");
868         ew32(CTRL, ctrl | E1000_CTRL_RST);
869         e1000e_release_phy_80003es2lan(hw);
870
871         ret_val = e1000e_get_auto_rd_done(hw);
872         if (ret_val)
873                 /* We don't want to continue accessing MAC registers. */
874                 goto out;
875
876         /* Clear any pending interrupt events. */
877         ew32(IMC, 0xffffffff);
878         icr = er32(ICR);
879
880         ret_val = e1000e_check_alt_mac_addr_generic(hw);
881
882 out:
883         return ret_val;
884 }
885
886 /**
887  *  e1000e_init_hw_80003es2lan - Initialize the ESB2 controller
888  *  @hw: pointer to the HW structure
889  *
890  *  Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
891  **/
892 static s32 e1000e_init_hw_80003es2lan(struct e1000_hw *hw)
893 {
894         struct e1000_mac_info *mac = &hw->mac;
895         u32 reg_data;
896         s32 ret_val;
897         u16 i;
898
899         e1000e_initialize_hw_bits_80003es2lan(hw);
900
901         /* Initialize identification LED */
902         ret_val = mac->ops.id_led_init(hw);
903         if (ret_val) {
904                 e_dbg("Error initializing identification LED\n");
905                 /* This is not fatal and we should not stop init due to this */
906         }
907
908         /* Disabling VLAN filtering */
909         e_dbg("Initializing the IEEE VLAN\n");
910         e1000e_clear_vfta(hw);
911
912         /* Setup the receive address. */
913         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
914
915         /* Zero out the Multicast HASH table */
916         e_dbg("Zeroing the MTA\n");
917         for (i = 0; i < mac->mta_reg_count; i++)
918                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
919
920         /* Setup link and flow control */
921         ret_val = mac->ops.setup_link(hw);
922
923         /* Set the transmit descriptor write-back policy */
924         reg_data = er32(TXDCTL(0));
925         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
926                    E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
927         ew32(TXDCTL(0), reg_data);
928
929         /* ...for both queues. */
930         reg_data = er32(TXDCTL(1));
931         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
932                    E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
933         ew32(TXDCTL(1), reg_data);
934
935         /* Enable retransmit on late collisions */
936         reg_data = er32(TCTL);
937         reg_data |= E1000_TCTL_RTLC;
938         ew32(TCTL, reg_data);
939
940         /* Configure Gigabit Carry Extend Padding */
941         reg_data = er32(TCTL_EXT);
942         reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
943         reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
944         ew32(TCTL_EXT, reg_data);
945
946         /* Configure Transmit Inter-Packet Gap */
947         reg_data = er32(TIPG);
948         reg_data &= ~E1000_TIPG_IPGT_MASK;
949         reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
950         ew32(TIPG, reg_data);
951
952         reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
953         reg_data &= ~0x00100000;
954         E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
955
956         /* default to true to enable the MDIC W/A */
957         hw->dev_spec._80003es2lan.mdic_wa_enable = true;
958
959         ret_val = e1000e_read_kmrn_reg_80003es2lan(hw,
960                                       E1000_KMRNCTRLSTA_OFFSET >>
961                                       E1000_KMRNCTRLSTA_OFFSET_SHIFT,
962                                       &i);
963         if (!ret_val) {
964                 if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
965                      E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
966                         hw->dev_spec._80003es2lan.mdic_wa_enable = false;
967         }
968
969         /*
970          * Clear all of the statistics registers (clear on read).  It is
971          * important that we do this after we have tried to establish link
972          * because the symbol error count will increment wildly if there
973          * is no link.
974          */
975         e1000e_clear_hw_cntrs_80003es2lan(hw);
976
977         return ret_val;
978 }
979
980 /**
981  *  e1000e_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
982  *  @hw: pointer to the HW structure
983  *
984  *  Initializes required hardware-dependent bits needed for normal operation.
985  **/
986 static void e1000e_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
987 {
988         u32 reg;
989
990         /* Transmit Descriptor Control 0 */
991         reg = er32(TXDCTL(0));
992         reg |= (1 << 22);
993         ew32(TXDCTL(0), reg);
994
995         /* Transmit Descriptor Control 1 */
996         reg = er32(TXDCTL(1));
997         reg |= (1 << 22);
998         ew32(TXDCTL(1), reg);
999
1000         /* Transmit Arbitration Control 0 */
1001         reg = er32(TARC(0));
1002         reg &= ~(0xF << 27); /* 30:27 */
1003         if (hw->phy.media_type != e1000_media_type_copper)
1004                 reg &= ~(1 << 20);
1005         ew32(TARC(0), reg);
1006
1007         /* Transmit Arbitration Control 1 */
1008         reg = er32(TARC(1));
1009         if (er32(TCTL) & E1000_TCTL_MULR)
1010                 reg &= ~(1 << 28);
1011         else
1012                 reg |= (1 << 28);
1013         ew32(TARC(1), reg);
1014
1015         return;
1016 }
1017
1018 /**
1019  *  e1000e_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
1020  *  @hw: pointer to the HW structure
1021  *
1022  *  Setup some GG82563 PHY registers for obtaining link
1023  **/
1024 static s32 e1000e_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
1025 {
1026         struct e1000_phy_info *phy = &hw->phy;
1027         s32 ret_val;
1028         u32 ctrl_ext;
1029         u16 data;
1030
1031         if (!phy->reset_disable) {
1032                 ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL,
1033                                              &data);
1034                 if (ret_val)
1035                         goto out;
1036
1037                 data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
1038                 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
1039                 data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
1040
1041                 ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL,
1042                                               data);
1043                 if (ret_val)
1044                         goto out;
1045
1046                 /*
1047                  * Options:
1048                  *   MDI/MDI-X = 0 (default)
1049                  *   0 - Auto for all speeds
1050                  *   1 - MDI mode
1051                  *   2 - MDI-X mode
1052                  *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1053                  */
1054                 ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data);
1055                 if (ret_val)
1056                         goto out;
1057
1058                 data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
1059
1060                 switch (phy->mdix) {
1061                 case 1:
1062                         data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
1063                         break;
1064                 case 2:
1065                         data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
1066                         break;
1067                 case 0:
1068                 default:
1069                         data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1070                         break;
1071                 }
1072
1073                 /*
1074                  * Options:
1075                  *   disable_polarity_correction = 0 (default)
1076                  *       Automatic Correction for Reversed Cable Polarity
1077                  *   0 - Disabled
1078                  *   1 - Enabled
1079                  */
1080                 data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1081                 if (phy->disable_polarity_correction)
1082                         data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1083
1084                 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data);
1085                 if (ret_val)
1086                         goto out;
1087
1088                 /* SW Reset the PHY so all changes take effect */
1089                 ret_val = e1000e_commit_phy(hw);
1090                 if (ret_val) {
1091                         e_dbg("Error Resetting the PHY\n");
1092                         goto out;
1093                 }
1094
1095         }
1096
1097         /* Bypass Rx and Tx FIFO's */
1098         ret_val = e1000e_write_kmrn_reg_80003es2lan(hw,
1099                                         E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
1100                                         E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
1101                                         E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
1102         if (ret_val)
1103                 goto out;
1104
1105         ret_val = e1000e_read_kmrn_reg_80003es2lan(hw,
1106                                       E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1107                                       &data);
1108         if (ret_val)
1109                 goto out;
1110         data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
1111         ret_val = e1000e_write_kmrn_reg_80003es2lan(hw,
1112                                        E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1113                                        data);
1114         if (ret_val)
1115                 goto out;
1116
1117         ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data);
1118         if (ret_val)
1119                 goto out;
1120
1121         data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1122         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data);
1123         if (ret_val)
1124                 goto out;
1125
1126         ctrl_ext = er32(CTRL_EXT);
1127         ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1128         ew32(CTRL_EXT, ctrl_ext);
1129
1130         ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
1131         if (ret_val)
1132                 goto out;
1133
1134         /*
1135          * Do not init these registers when the HW is in IAMT mode, since the
1136          * firmware will have already initialized them.  We only initialize
1137          * them if the HW is not in IAMT mode.
1138          */
1139         if (!(hw->mac.ops.check_mng_mode(hw))) {
1140                 /* Enable Electrical Idle on the PHY */
1141                 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1142                 ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL,
1143                                                 data);
1144                 if (ret_val)
1145                         goto out;
1146
1147                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL,
1148                                                &data);
1149                 if (ret_val)
1150                         goto out;
1151
1152                 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1153                 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL,
1154                                                 data);
1155                 if (ret_val)
1156                         goto out;
1157         }
1158
1159         /*
1160          * Workaround: Disable padding in Kumeran interface in the MAC
1161          * and in the PHY to avoid CRC errors.
1162          */
1163         ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);
1164         if (ret_val)
1165                 goto out;
1166
1167         data |= GG82563_ICR_DIS_PADDING;
1168         ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data);
1169         if (ret_val)
1170                 goto out;
1171
1172 out:
1173         return ret_val;
1174 }
1175
1176 /**
1177  *  e1000e_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1178  *  @hw: pointer to the HW structure
1179  *
1180  *  Essentially a wrapper for setting up all things "copper" related.
1181  *  This is a function pointer entry point called by the mac module.
1182  **/
1183 static s32 e1000e_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1184 {
1185         u32 ctrl;
1186         s32 ret_val;
1187         u16 reg_data;
1188
1189         ctrl = er32(CTRL);
1190         ctrl |= E1000_CTRL_SLU;
1191         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1192         ew32(CTRL, ctrl);
1193
1194         /*
1195          * Set the mac to wait the maximum time between each
1196          * iteration and increase the max iterations when
1197          * polling the phy; this fixes erroneous timeouts at 10Mbps.
1198          */
1199         ret_val = e1000e_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1200                                                    0xFFFF);
1201         if (ret_val)
1202                 goto out;
1203         ret_val = e1000e_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1204                                                   &reg_data);
1205         if (ret_val)
1206                 goto out;
1207         reg_data |= 0x3F;
1208         ret_val = e1000e_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1209                                                    reg_data);
1210         if (ret_val)
1211                 goto out;
1212         ret_val = e1000e_read_kmrn_reg_80003es2lan(hw,
1213                                       E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1214                                       &reg_data);
1215         if (ret_val)
1216                 goto out;
1217         reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1218         ret_val = e1000e_write_kmrn_reg_80003es2lan(hw,
1219                                        E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1220                                        reg_data);
1221         if (ret_val)
1222                 goto out;
1223
1224         ret_val = e1000e_copper_link_setup_gg82563_80003es2lan(hw);
1225         if (ret_val)
1226                 goto out;
1227
1228         ret_val = e1000e_setup_copper_link(hw);
1229
1230 out:
1231         return ret_val;
1232 }
1233
1234 /**
1235  *  e1000e_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
1236  *  @hw: pointer to the HW structure
1237  *  @duplex: current duplex setting
1238  *
1239  *  Configure the KMRN interface by applying last minute quirks for
1240  *  10/100 operation.
1241  **/
1242 static s32 e1000e_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
1243 {
1244         s32 ret_val = E1000_SUCCESS;
1245         u16 speed;
1246         u16 duplex;
1247
1248         if (hw->phy.media_type == e1000_media_type_copper) {
1249                 ret_val = e1000e_get_speed_and_duplex_copper(hw,
1250                                                                     &speed,
1251                                                                     &duplex);
1252                 if (ret_val)
1253                         goto out;
1254
1255                 if (speed == SPEED_1000)
1256                         ret_val = e1000e_cfg_kmrn_1000_80003es2lan(hw);
1257                 else
1258                         ret_val = e1000e_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1259         }
1260
1261 out:
1262         return ret_val;
1263 }
1264
1265 /**
1266  *  e1000e_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1267  *  @hw: pointer to the HW structure
1268  *  @duplex: current duplex setting
1269  *
1270  *  Configure the KMRN interface by applying last minute quirks for
1271  *  10/100 operation.
1272  **/
1273 static s32 e1000e_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1274 {
1275         s32 ret_val = E1000_SUCCESS;
1276         u32 tipg;
1277         u32 i = 0;
1278         u16 reg_data, reg_data2;
1279
1280         reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1281         ret_val = e1000e_write_kmrn_reg_80003es2lan(hw,
1282                                        E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1283                                        reg_data);
1284         if (ret_val)
1285                 goto out;
1286
1287         /* Configure Transmit Inter-Packet Gap */
1288         tipg = er32(TIPG);
1289         tipg &= ~E1000_TIPG_IPGT_MASK;
1290         tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1291         ew32(TIPG, tipg);
1292
1293
1294         do {
1295                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL,
1296                                                &reg_data);
1297                 if (ret_val)
1298                         goto out;
1299
1300                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL,
1301                                                &reg_data2);
1302                 if (ret_val)
1303                         goto out;
1304                 i++;
1305         } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1306
1307         if (duplex == HALF_DUPLEX)
1308                 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1309         else
1310                 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1311
1312         ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1313
1314 out:
1315         return ret_val;
1316 }
1317
1318 /**
1319  *  e1000e_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1320  *  @hw: pointer to the HW structure
1321  *
1322  *  Configure the KMRN interface by applying last minute quirks for
1323  *  gigabit operation.
1324  **/
1325 static s32 e1000e_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1326 {
1327         s32 ret_val = E1000_SUCCESS;
1328         u16 reg_data, reg_data2;
1329         u32 tipg;
1330         u32 i = 0;
1331
1332         reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1333         ret_val = e1000e_write_kmrn_reg_80003es2lan(hw,
1334                                        E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1335                                        reg_data);
1336         if (ret_val)
1337                 goto out;
1338
1339         /* Configure Transmit Inter-Packet Gap */
1340         tipg = er32(TIPG);
1341         tipg &= ~E1000_TIPG_IPGT_MASK;
1342         tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1343         ew32(TIPG, tipg);
1344
1345
1346         do {
1347                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL,
1348                                                &reg_data);
1349                 if (ret_val)
1350                         goto out;
1351
1352                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL,
1353                                                &reg_data2);
1354                 if (ret_val)
1355                         goto out;
1356                 i++;
1357         } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1358
1359         reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1360         ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1361
1362 out:
1363         return ret_val;
1364 }
1365
1366 /**
1367  *  e1000e_read_kmrn_reg_80003es2lan - Read kumeran register
1368  *  @hw: pointer to the HW structure
1369  *  @offset: register offset to be read
1370  *  @data: pointer to the read data
1371  *
1372  *  Acquire semaphore, then read the PHY register at offset
1373  *  using the kumeran interface.  The information retrieved is stored in data.
1374  *  Release the semaphore before exiting.
1375  **/
1376 static s32 e1000e_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1377                                            u16 *data)
1378 {
1379         u32 kmrnctrlsta;
1380         s32 ret_val = E1000_SUCCESS;
1381
1382         ret_val = e1000e_acquire_mac_csr_80003es2lan(hw);
1383         if (ret_val)
1384                 goto out;
1385
1386         kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1387                        E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
1388         ew32(KMRNCTRLSTA, kmrnctrlsta);
1389
1390         udelay(2);
1391
1392         kmrnctrlsta = er32(KMRNCTRLSTA);
1393         *data = (u16)kmrnctrlsta;
1394
1395         e1000e_release_mac_csr_80003es2lan(hw);
1396
1397 out:
1398         return ret_val;
1399 }
1400
1401 /**
1402  *  e1000e_write_kmrn_reg_80003es2lan - Write kumeran register
1403  *  @hw: pointer to the HW structure
1404  *  @offset: register offset to write to
1405  *  @data: data to write at register offset
1406  *
1407  *  Acquire semaphore, then write the data to PHY register
1408  *  at the offset using the kumeran interface.  Release semaphore
1409  *  before exiting.
1410  **/
1411 static s32 e1000e_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1412                                             u16 data)
1413 {
1414         u32 kmrnctrlsta;
1415         s32 ret_val = E1000_SUCCESS;
1416
1417         ret_val = e1000e_acquire_mac_csr_80003es2lan(hw);
1418         if (ret_val)
1419                 goto out;
1420
1421         kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1422                        E1000_KMRNCTRLSTA_OFFSET) | data;
1423         ew32(KMRNCTRLSTA, kmrnctrlsta);
1424
1425         udelay(2);
1426
1427         e1000e_release_mac_csr_80003es2lan(hw);
1428
1429 out:
1430         return ret_val;
1431 }
1432
1433 /**
1434  *  e1000e_read_mac_addr_80003es2lan - Read device MAC address
1435  *  @hw: pointer to the HW structure
1436  **/
1437 static s32 e1000e_read_mac_addr_80003es2lan(struct e1000_hw *hw)
1438 {
1439         s32 ret_val = E1000_SUCCESS;
1440
1441         /*
1442          * If there's an alternate MAC address place it in RAR0
1443          * so that it will override the Si installed default perm
1444          * address.
1445          */
1446         ret_val = e1000e_check_alt_mac_addr_generic(hw);
1447         if (ret_val)
1448                 goto out;
1449
1450         ret_val = e1000e_read_mac_addr_generic(hw);
1451
1452 out:
1453         return ret_val;
1454 }
1455
1456 /**
1457  * e1000e_power_down_phy_copper_80003es2lan - Remove link during PHY power down
1458  * @hw: pointer to the HW structure
1459  *
1460  * In the case of a PHY power down to save power, or to turn off link during a
1461  * driver unload, or wake on lan is not enabled, remove the link.
1462  **/
1463 static void e1000e_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
1464 {
1465         /* If the management interface is not enabled, then power down */
1466         if (!(hw->mac.ops.check_mng_mode(hw) ||
1467               e1000e_check_reset_block(hw)))
1468              e1000e_power_down_phy_copper(hw);
1469
1470         return;
1471 }
1472
1473 /**
1474  *  e1000e_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1475  *  @hw: pointer to the HW structure
1476  *
1477  *  Clears the hardware counters by reading the counter registers.
1478  **/
1479 static void e1000e_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw __unused)
1480 {
1481 #if 0
1482         e1000e_clear_hw_cntrs_base(hw);
1483
1484         er32(PRC64);
1485         er32(PRC127);
1486         er32(PRC255);
1487         er32(PRC511);
1488         er32(PRC1023);
1489         er32(PRC1522);
1490         er32(PTC64);
1491         er32(PTC127);
1492         er32(PTC255);
1493         er32(PTC511);
1494         er32(PTC1023);
1495         er32(PTC1522);
1496
1497         er32(ALGNERRC);
1498         er32(RXERRC);
1499         er32(TNCRS);
1500         er32(CEXTERR);
1501         er32(TSCTC);
1502         er32(TSCTFC);
1503
1504         er32(MGTPRC);
1505         er32(MGTPDC);
1506         er32(MGTPTC);
1507
1508         er32(IAC);
1509         er32(ICRXOC);
1510
1511         er32(ICRXPTC);
1512         er32(ICRXATC);
1513         er32(ICTXPTC);
1514         er32(ICTXATC);
1515         er32(ICTXQEC);
1516         er32(ICTXQMTC);
1517         er32(ICRXDMTC);
1518 #endif
1519 }
1520
1521 static struct pci_device_id e1000e_80003es2lan_nics[] = {
1522      PCI_ROM(0x8086, 0x1096, "E1000_DEV_ID_80003ES2LAN_COPPER_DPT", "E1000_DEV_ID_80003ES2LAN_COPPER_DPT", board_80003es2lan),
1523      PCI_ROM(0x8086, 0x10BA, "E1000_DEV_ID_80003ES2LAN_COPPER_SPT", "E1000_DEV_ID_80003ES2LAN_COPPER_SPT", board_80003es2lan),
1524      PCI_ROM(0x8086, 0x1098, "E1000_DEV_ID_80003ES2LAN_SERDES_DPT", "E1000_DEV_ID_80003ES2LAN_SERDES_DPT", board_80003es2lan),
1525      PCI_ROM(0x8086, 0x10BB, "E1000_DEV_ID_80003ES2LAN_SERDES_SPT", "E1000_DEV_ID_80003ES2LAN_SERDES_SPT", board_80003es2lan),
1526 };
1527
1528 struct pci_driver e1000e_80003es2lan_driver __pci_driver = {
1529         .ids = e1000e_80003es2lan_nics,
1530         .id_count = (sizeof (e1000e_80003es2lan_nics) / sizeof (e1000e_80003es2lan_nics[0])),
1531         .probe = e1000e_probe,
1532         .remove = e1000e_remove,
1533 };