[igb] Add igb driver
[people/pcmattman/gpxe.git] / src / drivers / net / igb / igb_manage.c
1 /*******************************************************************************
2
3   Intel(R) Gigabit Ethernet Linux driver
4   Copyright(c) 2007-2009 Intel Corporation.
5
6   This program is free software; you can redistribute it and/or modify it
7   under the terms and conditions of the GNU General Public License,
8   version 2, as published by the Free Software Foundation.
9
10   This program is distributed in the hope it will be useful, but WITHOUT
11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13   more details.
14
15   You should have received a copy of the GNU General Public License along with
16   this program; if not, write to the Free Software Foundation, Inc.,
17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19   The full GNU General Public License is included in this distribution in
20   the file called "COPYING".
21
22   Contact Information:
23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 FILE_LICENCE ( GPL2_ONLY );
29
30 #include "igb.h"
31
32 #if 0
33
34 static u8 e1000_calculate_checksum(u8 *buffer, u32 length);
35
36 /**
37  *  e1000_calculate_checksum - Calculate checksum for buffer
38  *  @buffer: pointer to EEPROM
39  *  @length: size of EEPROM to calculate a checksum for
40  *
41  *  Calculates the checksum for some buffer on a specified length.  The
42  *  checksum calculated is returned.
43  **/
44 static u8 e1000_calculate_checksum(u8 *buffer, u32 length)
45 {
46         u32 i;
47         u8  sum = 0;
48
49         DEBUGFUNC("igb_calculate_checksum");
50
51         if (!buffer)
52                 return 0;
53
54         for (i = 0; i < length; i++)
55                 sum += buffer[i];
56
57         return (u8) (0 - sum);
58 }
59
60 /**
61  *  e1000_mng_enable_host_if_generic - Checks host interface is enabled
62  *  @hw: pointer to the HW structure
63  *
64  *  Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND
65  *
66  *  This function checks whether the HOST IF is enabled for command operation
67  *  and also checks whether the previous command is completed.  It busy waits
68  *  in case of previous command is not completed.
69  **/
70 s32 e1000_mng_enable_host_if_generic(struct e1000_hw *hw)
71 {
72         u32 hicr;
73         s32 ret_val = E1000_SUCCESS;
74         u8  i;
75
76         DEBUGFUNC("igb_mng_enable_host_if_generic");
77
78         /* Check that the host interface is enabled. */
79         hicr = E1000_READ_REG(hw, E1000_HICR);
80         if ((hicr & E1000_HICR_EN) == 0) {
81                 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
82                 ret_val = -E1000_ERR_HOST_INTERFACE_COMMAND;
83                 goto out;
84         }
85         /* check the previous command is completed */
86         for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
87                 hicr = E1000_READ_REG(hw, E1000_HICR);
88                 if (!(hicr & E1000_HICR_C))
89                         break;
90                 msec_delay_irq(1);
91         }
92
93         if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
94                 DEBUGOUT("Previous command timeout failed .\n");
95                 ret_val = -E1000_ERR_HOST_INTERFACE_COMMAND;
96                 goto out;
97         }
98
99 out:
100         return ret_val;
101 }
102
103 /**
104  *  e1000_check_mng_mode_generic - Generic check management mode
105  *  @hw: pointer to the HW structure
106  *
107  *  Reads the firmware semaphore register and returns true (>0) if
108  *  manageability is enabled, else false (0).
109  **/
110 bool e1000_check_mng_mode_generic(struct e1000_hw *hw)
111 {
112         u32 fwsm;
113
114         DEBUGFUNC("igb_check_mng_mode_generic");
115
116         fwsm = E1000_READ_REG(hw, E1000_FWSM);
117
118         return (fwsm & E1000_FWSM_MODE_MASK) ==
119                 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
120 }
121
122 /**
123  *  e1000_enable_tx_pkt_filtering_generic - Enable packet filtering on TX
124  *  @hw: pointer to the HW structure
125  *
126  *  Enables packet filtering on transmit packets if manageability is enabled
127  *  and host interface is enabled.
128  **/
129 bool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw)
130 {
131         struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie;
132         u32 *buffer = (u32 *)&hw->mng_cookie;
133         u32 offset;
134         s32 ret_val, hdr_csum, csum;
135         u8 i, len;
136         bool tx_filter = true;
137
138         DEBUGFUNC("igb_enable_tx_pkt_filtering_generic");
139
140         /* No manageability, no filtering */
141         if (!hw->mac.ops.check_mng_mode(hw)) {
142                 tx_filter = false;
143                 goto out;
144         }
145
146         /*
147          * If we can't read from the host interface for whatever
148          * reason, disable filtering.
149          */
150         ret_val = hw->mac.ops.mng_enable_host_if(hw);
151         if (ret_val != E1000_SUCCESS) {
152                 tx_filter = false;
153                 goto out;
154         }
155
156         /* Read in the header.  Length and offset are in dwords. */
157         len    = E1000_MNG_DHCP_COOKIE_LENGTH >> 2;
158         offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2;
159         for (i = 0; i < len; i++) {
160                 *(buffer + i) = E1000_READ_REG_ARRAY_DWORD(hw,
161                                                            E1000_HOST_IF,
162                                                            offset + i);
163         }
164         hdr_csum = hdr->checksum;
165         hdr->checksum = 0;
166         csum = e1000_calculate_checksum((u8 *)hdr,
167                                         E1000_MNG_DHCP_COOKIE_LENGTH);
168         /*
169          * If either the checksums or signature don't match, then
170          * the cookie area isn't considered valid, in which case we
171          * take the safe route of assuming Tx filtering is enabled.
172          */
173         if (hdr_csum != csum)
174                 goto out;
175         if (hdr->signature != E1000_IAMT_SIGNATURE)
176                 goto out;
177
178         /* Cookie area is valid, make the final check for filtering. */
179         if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING))
180                 tx_filter = false;
181
182 out:
183         hw->mac.tx_pkt_filtering = tx_filter;
184         return tx_filter;
185 }
186
187 /**
188  *  e1000_mng_write_dhcp_info_generic - Writes DHCP info to host interface
189  *  @hw: pointer to the HW structure
190  *  @buffer: pointer to the host interface
191  *  @length: size of the buffer
192  *
193  *  Writes the DHCP information to the host interface.
194  **/
195 s32 e1000_mng_write_dhcp_info_generic(struct e1000_hw *hw, u8 *buffer,
196                                       u16 length)
197 {
198         struct e1000_host_mng_command_header hdr;
199         s32 ret_val;
200         u32 hicr;
201
202         DEBUGFUNC("igb_mng_write_dhcp_info_generic");
203
204         hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
205         hdr.command_length = length;
206         hdr.reserved1 = 0;
207         hdr.reserved2 = 0;
208         hdr.checksum = 0;
209
210         /* Enable the host interface */
211         ret_val = hw->mac.ops.mng_enable_host_if(hw);
212         if (ret_val)
213                 goto out;
214
215         /* Populate the host interface with the contents of "buffer". */
216         ret_val = hw->mac.ops.mng_host_if_write(hw, buffer, length,
217                                           sizeof(hdr), &(hdr.checksum));
218         if (ret_val)
219                 goto out;
220
221         /* Write the manageability command header */
222         ret_val = hw->mac.ops.mng_write_cmd_header(hw, &hdr);
223         if (ret_val)
224                 goto out;
225
226         /* Tell the ARC a new command is pending. */
227         hicr = E1000_READ_REG(hw, E1000_HICR);
228         E1000_WRITE_REG(hw, E1000_HICR, hicr | E1000_HICR_C);
229
230 out:
231         return ret_val;
232 }
233
234 /**
235  *  e1000_mng_write_cmd_header_generic - Writes manageability command header
236  *  @hw: pointer to the HW structure
237  *  @hdr: pointer to the host interface command header
238  *
239  *  Writes the command header after does the checksum calculation.
240  **/
241 s32 e1000_mng_write_cmd_header_generic(struct e1000_hw *hw,
242                                     struct e1000_host_mng_command_header *hdr)
243 {
244         u16 i, length = sizeof(struct e1000_host_mng_command_header);
245
246         DEBUGFUNC("igb_mng_write_cmd_header_generic");
247
248         /* Write the whole command header structure with new checksum. */
249
250         hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length);
251
252         length >>= 2;
253         /* Write the relevant command block into the ram area. */
254         for (i = 0; i < length; i++) {
255                 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, i,
256                                             *((u32 *) hdr + i));
257                 E1000_WRITE_FLUSH(hw);
258         }
259
260         return E1000_SUCCESS;
261 }
262
263 /**
264  *  e1000_mng_host_if_write_generic - Write to the manageability host interface
265  *  @hw: pointer to the HW structure
266  *  @buffer: pointer to the host interface buffer
267  *  @length: size of the buffer
268  *  @offset: location in the buffer to write to
269  *  @sum: sum of the data (not checksum)
270  *
271  *  This function writes the buffer content at the offset given on the host if.
272  *  It also does alignment considerations to do the writes in most efficient
273  *  way.  Also fills up the sum of the buffer in *buffer parameter.
274  **/
275 s32 e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer,
276                                     u16 length, u16 offset, u8 *sum)
277 {
278         u8 *tmp;
279         u8 *bufptr = buffer;
280         u32 data = 0;
281         s32 ret_val = E1000_SUCCESS;
282         u16 remaining, i, j, prev_bytes;
283
284         DEBUGFUNC("igb_mng_host_if_write_generic");
285
286         /* sum = only sum of the data and it is not checksum */
287
288         if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) {
289                 ret_val = -E1000_ERR_PARAM;
290                 goto out;
291         }
292
293         tmp = (u8 *)&data;
294         prev_bytes = offset & 0x3;
295         offset >>= 2;
296
297         if (prev_bytes) {
298                 data = E1000_READ_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset);
299                 for (j = prev_bytes; j < sizeof(u32); j++) {
300                         *(tmp + j) = *bufptr++;
301                         *sum += *(tmp + j);
302                 }
303                 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset, data);
304                 length -= j - prev_bytes;
305                 offset++;
306         }
307
308         remaining = length & 0x3;
309         length -= remaining;
310
311         /* Calculate length in DWORDs */
312         length >>= 2;
313
314         /*
315          * The device driver writes the relevant command block into the
316          * ram area.
317          */
318         for (i = 0; i < length; i++) {
319                 for (j = 0; j < sizeof(u32); j++) {
320                         *(tmp + j) = *bufptr++;
321                         *sum += *(tmp + j);
322                 }
323
324                 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i,
325                                             data);
326         }
327         if (remaining) {
328                 for (j = 0; j < sizeof(u32); j++) {
329                         if (j < remaining)
330                                 *(tmp + j) = *bufptr++;
331                         else
332                                 *(tmp + j) = 0;
333
334                         *sum += *(tmp + j);
335                 }
336                 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i, data);
337         }
338
339 out:
340         return ret_val;
341 }
342
343 /**
344  *  e1000_enable_mng_pass_thru - Enable processing of ARP's
345  *  @hw: pointer to the HW structure
346  *
347  *  Verifies the hardware needs to allow ARPs to be processed by the host.
348  **/
349 bool e1000_enable_mng_pass_thru(struct e1000_hw *hw)
350 {
351         u32 manc;
352         u32 fwsm, factps;
353         bool ret_val = false;
354
355         DEBUGFUNC("igb_enable_mng_pass_thru");
356
357         if (!hw->mac.asf_firmware_present)
358                 goto out;
359
360         manc = E1000_READ_REG(hw, E1000_MANC);
361
362         if (!(manc & E1000_MANC_RCV_TCO_EN) ||
363             !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
364                 goto out;
365
366         if (hw->mac.arc_subsystem_valid) {
367                 fwsm = E1000_READ_REG(hw, E1000_FWSM);
368                 factps = E1000_READ_REG(hw, E1000_FACTPS);
369
370                 if (!(factps & E1000_FACTPS_MNGCG) &&
371                     ((fwsm & E1000_FWSM_MODE_MASK) ==
372                      (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) {
373                         ret_val = true;
374                         goto out;
375                 }
376         } else {
377                 if ((manc & E1000_MANC_SMBUS_EN) &&
378                     !(manc & E1000_MANC_ASF_EN)) {
379                         ret_val = true;
380                         goto out;
381                 }
382         }
383
384 out:
385         return ret_val;
386 }
387
388 #endif