[igb] Add igb driver
[people/pcmattman/gpxe.git] / src / drivers / net / igb / igb_hw.h
1 /*******************************************************************************
2
3   Intel(R) Gigabit Ethernet Linux driver
4   Copyright(c) 2007-2009 Intel Corporation.
5
6   This program is free software; you can redistribute it and/or modify it
7   under the terms and conditions of the GNU General Public License,
8   version 2, as published by the Free Software Foundation.
9
10   This program is distributed in the hope it will be useful, but WITHOUT
11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13   more details.
14
15   You should have received a copy of the GNU General Public License along with
16   this program; if not, write to the Free Software Foundation, Inc.,
17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19   The full GNU General Public License is included in this distribution in
20   the file called "COPYING".
21
22   Contact Information:
23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 FILE_LICENCE ( GPL2_ONLY );
29
30 #ifndef _IGB_HW_H_
31 #define _IGB_HW_H_
32
33 #include "igb_osdep.h"
34 #include "igb_regs.h"
35 #include "igb_defines.h"
36
37 struct e1000_hw;
38
39 #define E1000_DEV_ID_82576                    0x10C9
40 #define E1000_DEV_ID_82576_FIBER              0x10E6
41 #define E1000_DEV_ID_82576_SERDES             0x10E7
42 #define E1000_DEV_ID_82576_QUAD_COPPER        0x10E8
43 #define E1000_DEV_ID_82576_NS                 0x150A
44 #define E1000_DEV_ID_82576_NS_SERDES          0x1518
45 #define E1000_DEV_ID_82576_SERDES_QUAD        0x150D
46 #define E1000_DEV_ID_82575EB_COPPER           0x10A7
47 #define E1000_DEV_ID_82575EB_FIBER_SERDES     0x10A9
48 #define E1000_DEV_ID_82575GB_QUAD_COPPER      0x10D6
49 #define E1000_REVISION_0 0
50 #define E1000_REVISION_1 1
51 #define E1000_REVISION_2 2
52 #define E1000_REVISION_3 3
53 #define E1000_REVISION_4 4
54
55 #define E1000_FUNC_0     0
56 #define E1000_FUNC_1     1
57
58 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0   0
59 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1   3
60
61 enum e1000_mac_type {
62         e1000_undefined = 0,
63         e1000_82575,
64         e1000_82576,
65         e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
66 };
67
68 enum e1000_media_type {
69         e1000_media_type_unknown = 0,
70         e1000_media_type_copper = 1,
71         e1000_media_type_fiber = 2,
72         e1000_media_type_internal_serdes = 3,
73         e1000_num_media_types
74 };
75
76 enum e1000_nvm_type {
77         e1000_nvm_unknown = 0,
78         e1000_nvm_none,
79         e1000_nvm_eeprom_spi,
80         e1000_nvm_flash_hw,
81         e1000_nvm_flash_sw
82 };
83
84 enum e1000_nvm_override {
85         e1000_nvm_override_none = 0,
86         e1000_nvm_override_spi_small,
87         e1000_nvm_override_spi_large,
88 };
89
90 enum e1000_phy_type {
91         e1000_phy_unknown = 0,
92         e1000_phy_none,
93         e1000_phy_m88,
94         e1000_phy_igp,
95         e1000_phy_igp_2,
96         e1000_phy_gg82563,
97         e1000_phy_igp_3,
98         e1000_phy_ife,
99         e1000_phy_vf,
100 };
101
102 enum e1000_bus_type {
103         e1000_bus_type_unknown = 0,
104         e1000_bus_type_pci,
105         e1000_bus_type_pcix,
106         e1000_bus_type_pci_express,
107         e1000_bus_type_reserved
108 };
109
110 enum e1000_bus_speed {
111         e1000_bus_speed_unknown = 0,
112         e1000_bus_speed_33,
113         e1000_bus_speed_66,
114         e1000_bus_speed_100,
115         e1000_bus_speed_120,
116         e1000_bus_speed_133,
117         e1000_bus_speed_2500,
118         e1000_bus_speed_5000,
119         e1000_bus_speed_reserved
120 };
121
122 enum e1000_bus_width {
123         e1000_bus_width_unknown = 0,
124         e1000_bus_width_pcie_x1,
125         e1000_bus_width_pcie_x2,
126         e1000_bus_width_pcie_x4 = 4,
127         e1000_bus_width_pcie_x8 = 8,
128         e1000_bus_width_32,
129         e1000_bus_width_64,
130         e1000_bus_width_reserved
131 };
132
133 enum e1000_1000t_rx_status {
134         e1000_1000t_rx_status_not_ok = 0,
135         e1000_1000t_rx_status_ok,
136         e1000_1000t_rx_status_undefined = 0xFF
137 };
138
139 enum e1000_rev_polarity {
140         e1000_rev_polarity_normal = 0,
141         e1000_rev_polarity_reversed,
142         e1000_rev_polarity_undefined = 0xFF
143 };
144
145 enum e1000_fc_mode {
146         e1000_fc_none = 0,
147         e1000_fc_rx_pause,
148         e1000_fc_tx_pause,
149         e1000_fc_full,
150         e1000_fc_default = 0xFF
151 };
152
153 enum e1000_ms_type {
154         e1000_ms_hw_default = 0,
155         e1000_ms_force_master,
156         e1000_ms_force_slave,
157         e1000_ms_auto
158 };
159
160 enum e1000_smart_speed {
161         e1000_smart_speed_default = 0,
162         e1000_smart_speed_on,
163         e1000_smart_speed_off
164 };
165
166 enum e1000_serdes_link_state {
167         e1000_serdes_link_down = 0,
168         e1000_serdes_link_autoneg_progress,
169         e1000_serdes_link_autoneg_complete,
170         e1000_serdes_link_forced_up
171 };
172
173 /* Receive Descriptor */
174 struct e1000_rx_desc {
175         __le64 buffer_addr; /* Address of the descriptor's data buffer */
176         __le16 length;      /* Length of data DMAed into data buffer */
177         __le16 csum;        /* Packet checksum */
178         u8  status;         /* Descriptor status */
179         u8  errors;         /* Descriptor Errors */
180         __le16 special;
181 };
182
183 /* Receive Descriptor - Extended */
184 union e1000_rx_desc_extended {
185         struct {
186                 __le64 buffer_addr;
187                 __le64 reserved;
188         } read;
189         struct {
190                 struct {
191                         __le32 mrq;           /* Multiple Rx Queues */
192                         union {
193                                 __le32 rss;         /* RSS Hash */
194                                 struct {
195                                         __le16 ip_id;  /* IP id */
196                                         __le16 csum;   /* Packet Checksum */
197                                 } csum_ip;
198                         } hi_dword;
199                 } lower;
200                 struct {
201                         __le32 status_error;  /* ext status/error */
202                         __le16 length;
203                         __le16 vlan;          /* VLAN tag */
204                 } upper;
205         } wb;  /* writeback */
206 };
207
208 #define MAX_PS_BUFFERS 4
209 /* Receive Descriptor - Packet Split */
210 union e1000_rx_desc_packet_split {
211         struct {
212                 /* one buffer for protocol header(s), three data buffers */
213                 __le64 buffer_addr[MAX_PS_BUFFERS];
214         } read;
215         struct {
216                 struct {
217                         __le32 mrq;           /* Multiple Rx Queues */
218                         union {
219                                 __le32 rss;           /* RSS Hash */
220                                 struct {
221                                         __le16 ip_id;    /* IP id */
222                                         __le16 csum;     /* Packet Checksum */
223                                 } csum_ip;
224                         } hi_dword;
225                 } lower;
226                 struct {
227                         __le32 status_error;  /* ext status/error */
228                         __le16 length0;       /* length of buffer 0 */
229                         __le16 vlan;          /* VLAN tag */
230                 } middle;
231                 struct {
232                         __le16 header_status;
233                         __le16 length[3];     /* length of buffers 1-3 */
234                 } upper;
235                 __le64 reserved;
236         } wb; /* writeback */
237 };
238
239 /* Transmit Descriptor */
240 struct e1000_tx_desc {
241         __le64 buffer_addr;   /* Address of the descriptor's data buffer */
242         union {
243                 __le32 data;
244                 struct {
245                         __le16 length;    /* Data buffer length */
246                         u8 cso;           /* Checksum offset */
247                         u8 cmd;           /* Descriptor control */
248                 } flags;
249         } lower;
250         union {
251                 __le32 data;
252                 struct {
253                         u8 status;        /* Descriptor status */
254                         u8 css;           /* Checksum start */
255                         __le16 special;
256                 } fields;
257         } upper;
258 };
259
260 /* Offload Context Descriptor */
261 struct e1000_context_desc {
262         union {
263                 __le32 ip_config;
264                 struct {
265                         u8 ipcss;         /* IP checksum start */
266                         u8 ipcso;         /* IP checksum offset */
267                         __le16 ipcse;     /* IP checksum end */
268                 } ip_fields;
269         } lower_setup;
270         union {
271                 __le32 tcp_config;
272                 struct {
273                         u8 tucss;         /* TCP checksum start */
274                         u8 tucso;         /* TCP checksum offset */
275                         __le16 tucse;     /* TCP checksum end */
276                 } tcp_fields;
277         } upper_setup;
278         __le32 cmd_and_length;
279         union {
280                 __le32 data;
281                 struct {
282                         u8 status;        /* Descriptor status */
283                         u8 hdr_len;       /* Header length */
284                         __le16 mss;       /* Maximum segment size */
285                 } fields;
286         } tcp_seg_setup;
287 };
288
289 /* Offload data descriptor */
290 struct e1000_data_desc {
291         __le64 buffer_addr;   /* Address of the descriptor's buffer address */
292         union {
293                 __le32 data;
294                 struct {
295                         __le16 length;    /* Data buffer length */
296                         u8 typ_len_ext;
297                         u8 cmd;
298                 } flags;
299         } lower;
300         union {
301                 __le32 data;
302                 struct {
303                         u8 status;        /* Descriptor status */
304                         u8 popts;         /* Packet Options */
305                         __le16 special;
306                 } fields;
307         } upper;
308 };
309
310 /* Statistics counters collected by the MAC */
311 struct e1000_hw_stats {
312         u64 crcerrs;
313         u64 algnerrc;
314         u64 symerrs;
315         u64 rxerrc;
316         u64 mpc;
317         u64 scc;
318         u64 ecol;
319         u64 mcc;
320         u64 latecol;
321         u64 colc;
322         u64 dc;
323         u64 tncrs;
324         u64 sec;
325         u64 cexterr;
326         u64 rlec;
327         u64 xonrxc;
328         u64 xontxc;
329         u64 xoffrxc;
330         u64 xofftxc;
331         u64 fcruc;
332         u64 prc64;
333         u64 prc127;
334         u64 prc255;
335         u64 prc511;
336         u64 prc1023;
337         u64 prc1522;
338         u64 gprc;
339         u64 bprc;
340         u64 mprc;
341         u64 gptc;
342         u64 gorc;
343         u64 gotc;
344         u64 rnbc;
345         u64 ruc;
346         u64 rfc;
347         u64 roc;
348         u64 rjc;
349         u64 mgprc;
350         u64 mgpdc;
351         u64 mgptc;
352         u64 tor;
353         u64 tot;
354         u64 tpr;
355         u64 tpt;
356         u64 ptc64;
357         u64 ptc127;
358         u64 ptc255;
359         u64 ptc511;
360         u64 ptc1023;
361         u64 ptc1522;
362         u64 mptc;
363         u64 bptc;
364         u64 tsctc;
365         u64 tsctfc;
366         u64 iac;
367         u64 icrxptc;
368         u64 icrxatc;
369         u64 ictxptc;
370         u64 ictxatc;
371         u64 ictxqec;
372         u64 ictxqmtc;
373         u64 icrxdmtc;
374         u64 icrxoc;
375         u64 cbtmpc;
376         u64 htdpmc;
377         u64 cbrdpc;
378         u64 cbrmpc;
379         u64 rpthc;
380         u64 hgptc;
381         u64 htcbdpc;
382         u64 hgorc;
383         u64 hgotc;
384         u64 lenerrs;
385         u64 scvpc;
386         u64 hrmpc;
387         u64 doosync;
388 };
389
390
391 struct e1000_phy_stats {
392         u32 idle_errors;
393         u32 receive_errors;
394 };
395
396 struct e1000_host_mng_dhcp_cookie {
397         u32 signature;
398         u8  status;
399         u8  reserved0;
400         u16 vlan_id;
401         u32 reserved1;
402         u16 reserved2;
403         u8  reserved3;
404         u8  checksum;
405 };
406
407 /* Host Interface "Rev 1" */
408 struct e1000_host_command_header {
409         u8 command_id;
410         u8 command_length;
411         u8 command_options;
412         u8 checksum;
413 };
414
415 #define E1000_HI_MAX_DATA_LENGTH     252
416 struct e1000_host_command_info {
417         struct e1000_host_command_header command_header;
418         u8 command_data[E1000_HI_MAX_DATA_LENGTH];
419 };
420
421 /* Host Interface "Rev 2" */
422 struct e1000_host_mng_command_header {
423         u8  command_id;
424         u8  checksum;
425         u16 reserved1;
426         u16 reserved2;
427         u16 command_length;
428 };
429
430 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
431 struct e1000_host_mng_command_info {
432         struct e1000_host_mng_command_header command_header;
433         u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
434 };
435
436 #include "igb_mac.h"
437 #include "igb_phy.h"
438 #include "igb_nvm.h"
439 #include "igb_manage.h"
440
441 struct e1000_mac_operations {
442         /* Function pointers for the MAC. */
443         s32  (*init_params)(struct e1000_hw *);
444         s32  (*id_led_init)(struct e1000_hw *);
445         s32  (*blink_led)(struct e1000_hw *);
446         s32  (*check_for_link)(struct e1000_hw *);
447         bool (*check_mng_mode)(struct e1000_hw *hw);
448         s32  (*cleanup_led)(struct e1000_hw *);
449         void (*clear_hw_cntrs)(struct e1000_hw *);
450         void (*clear_vfta)(struct e1000_hw *);
451         s32  (*get_bus_info)(struct e1000_hw *);
452         void (*set_lan_id)(struct e1000_hw *);
453         s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
454         s32  (*led_on)(struct e1000_hw *);
455         s32  (*led_off)(struct e1000_hw *);
456         void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
457         s32  (*reset_hw)(struct e1000_hw *);
458         s32  (*init_hw)(struct e1000_hw *);
459         void (*shutdown_serdes)(struct e1000_hw *);
460         s32  (*setup_link)(struct e1000_hw *);
461         s32  (*setup_physical_interface)(struct e1000_hw *);
462         s32  (*setup_led)(struct e1000_hw *);
463         void (*write_vfta)(struct e1000_hw *, u32, u32);
464         void (*mta_set)(struct e1000_hw *, u32);
465         void (*config_collision_dist)(struct e1000_hw *);
466         void (*rar_set)(struct e1000_hw *, u8*, u32);
467         s32  (*read_mac_addr)(struct e1000_hw *);
468         s32  (*validate_mdi_setting)(struct e1000_hw *);
469         s32  (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*);
470         s32  (*mng_write_cmd_header)(struct e1000_hw *hw,
471                       struct e1000_host_mng_command_header*);
472         s32  (*mng_enable_host_if)(struct e1000_hw *);
473         s32  (*wait_autoneg)(struct e1000_hw *);
474 };
475
476 struct e1000_phy_operations {
477         s32  (*init_params)(struct e1000_hw *);
478         s32  (*acquire)(struct e1000_hw *);
479         s32  (*check_polarity)(struct e1000_hw *);
480         s32  (*check_reset_block)(struct e1000_hw *);
481         s32  (*commit)(struct e1000_hw *);
482 #if 0
483         s32  (*force_speed_duplex)(struct e1000_hw *);
484 #endif
485         s32  (*get_cfg_done)(struct e1000_hw *hw);
486 #if 0
487         s32  (*get_cable_length)(struct e1000_hw *);
488 #endif
489         s32  (*get_info)(struct e1000_hw *);
490         s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
491         s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
492         void (*release)(struct e1000_hw *);
493         s32  (*reset)(struct e1000_hw *);
494         s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
495         s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
496         s32  (*write_reg)(struct e1000_hw *, u32, u16);
497         s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
498         void (*power_up)(struct e1000_hw *);
499         void (*power_down)(struct e1000_hw *);
500 };
501
502 struct e1000_nvm_operations {
503         s32  (*init_params)(struct e1000_hw *);
504         s32  (*acquire)(struct e1000_hw *);
505         s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
506         void (*release)(struct e1000_hw *);
507         void (*reload)(struct e1000_hw *);
508         s32  (*update)(struct e1000_hw *);
509         s32  (*valid_led_default)(struct e1000_hw *, u16 *);
510         s32  (*validate)(struct e1000_hw *);
511         s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
512 };
513
514 struct e1000_mac_info {
515         struct e1000_mac_operations ops;
516         u8 addr[6];
517         u8 perm_addr[6];
518
519         enum e1000_mac_type type;
520
521         u32 collision_delta;
522         u32 ledctl_default;
523         u32 ledctl_mode1;
524         u32 ledctl_mode2;
525         u32 mc_filter_type;
526         u32 tx_packet_delta;
527         u32 txcw;
528
529         u16 current_ifs_val;
530         u16 ifs_max_val;
531         u16 ifs_min_val;
532         u16 ifs_ratio;
533         u16 ifs_step_size;
534         u16 mta_reg_count;
535         u16 uta_reg_count;
536
537         /* Maximum size of the MTA register table in all supported adapters */
538         #define MAX_MTA_REG 128
539         u32 mta_shadow[MAX_MTA_REG];
540         u16 rar_entry_count;
541
542         u8  forced_speed_duplex;
543
544         bool adaptive_ifs;
545         bool arc_subsystem_valid;
546         bool asf_firmware_present;
547         bool autoneg;
548         bool autoneg_failed;
549         bool get_link_status;
550         bool in_ifs_mode;
551         enum e1000_serdes_link_state serdes_link_state;
552         bool serdes_has_link;
553         bool tx_pkt_filtering;
554 };
555
556 struct e1000_phy_info {
557         struct e1000_phy_operations ops;
558         enum e1000_phy_type type;
559
560         enum e1000_1000t_rx_status local_rx;
561         enum e1000_1000t_rx_status remote_rx;
562         enum e1000_ms_type ms_type;
563         enum e1000_ms_type original_ms_type;
564         enum e1000_rev_polarity cable_polarity;
565         enum e1000_smart_speed smart_speed;
566
567         u32 addr;
568         u32 id;
569         u32 reset_delay_us; /* in usec */
570         u32 revision;
571
572         enum e1000_media_type media_type;
573
574         u16 autoneg_advertised;
575         u16 autoneg_mask;
576         u16 cable_length;
577         u16 max_cable_length;
578         u16 min_cable_length;
579
580         u8 mdix;
581
582         bool disable_polarity_correction;
583         bool is_mdix;
584         bool polarity_correction;
585         bool reset_disable;
586         bool speed_downgraded;
587         bool autoneg_wait_to_complete;
588 };
589
590 struct e1000_nvm_info {
591         struct e1000_nvm_operations ops;
592         enum e1000_nvm_type type;
593         enum e1000_nvm_override override;
594
595         u32 flash_bank_size;
596         u32 flash_base_addr;
597
598         u16 word_size;
599         u16 delay_usec;
600         u16 address_bits;
601         u16 opcode_bits;
602         u16 page_size;
603 };
604
605 struct e1000_bus_info {
606         enum e1000_bus_type type;
607         enum e1000_bus_speed speed;
608         enum e1000_bus_width width;
609
610         u16 func;
611         u16 pci_cmd_word;
612 };
613
614 struct e1000_fc_info {
615         u32 high_water;          /* Flow control high-water mark */
616         u32 low_water;           /* Flow control low-water mark */
617         u16 pause_time;          /* Flow control pause timer */
618         bool send_xon;           /* Flow control send XON */
619         bool strict_ieee;        /* Strict IEEE mode */
620         enum e1000_fc_mode current_mode; /* FC mode in effect */
621         enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
622 };
623
624 struct e1000_mbx_operations {
625         s32 (*init_params)(struct e1000_hw *hw);
626         s32 (*read)(struct e1000_hw *, u32 *, u16,  u16);
627         s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
628         s32 (*read_posted)(struct e1000_hw *, u32 *, u16,  u16);
629         s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
630         s32 (*check_for_msg)(struct e1000_hw *, u16);
631         s32 (*check_for_ack)(struct e1000_hw *, u16);
632         s32 (*check_for_rst)(struct e1000_hw *, u16);
633 };
634
635 struct e1000_mbx_stats {
636         u32 msgs_tx;
637         u32 msgs_rx;
638
639         u32 acks;
640         u32 reqs;
641         u32 rsts;
642 };
643
644 struct e1000_mbx_info {
645         struct e1000_mbx_operations ops;
646         struct e1000_mbx_stats stats;
647         u32 timeout;
648         u32 usec_delay;
649         u16 size;
650 };
651
652 struct e1000_dev_spec_82575 {
653         bool sgmii_active;
654         bool global_device_reset;
655 };
656
657 struct e1000_dev_spec_vf {
658         u32     vf_number;
659         u32     v2p_mailbox;
660 };
661
662
663 struct e1000_hw {
664         void *back;
665
666         u8 __iomem *hw_addr;
667         u8 __iomem *flash_address;
668         unsigned long io_base;
669
670         struct e1000_mac_info  mac;
671         struct e1000_fc_info   fc;
672         struct e1000_phy_info  phy;
673         struct e1000_nvm_info  nvm;
674         struct e1000_bus_info  bus;
675         struct e1000_mbx_info mbx;
676         struct e1000_host_mng_dhcp_cookie mng_cookie;
677
678         union {
679                 struct e1000_dev_spec_82575     _82575;
680                 struct e1000_dev_spec_vf        vf;
681         } dev_spec;
682
683         u16 device_id;
684         u16 subsystem_vendor_id;
685         u16 subsystem_device_id;
686         u16 vendor_id;
687
688         u8  revision_id;
689 };
690
691 #include "igb_82575.h"
692
693 /* These functions must be implemented by drivers */
694 s32  igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
695 s32  igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
696
697 #endif /* _IGB_HW_H_ */