Remove MSI/MSIX support. master
authorThomas Miletich <thomas.miletich@gmail.com>
Thu, 2 Jun 2011 12:03:16 +0000 (14:03 +0200)
committerThomas Miletich <thomas.miletich@gmail.com>
Thu, 2 Jun 2011 12:03:16 +0000 (14:03 +0200)
mytg3.c

diff --git a/mytg3.c b/mytg3.c
index cdfa7f4..3af605f 100644 (file)
--- a/mytg3.c
+++ b/mytg3.c
@@ -4905,50 +4905,6 @@ static inline void tg3_full_unlock(struct tg3 *tp)
        spin_unlock_bh(&tp->lock);
 }
 
-/* One-shot MSI handler - Chip automatically disables interrupt
- * after sending MSI so driver doesn't have to do it.
- */
-static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
-{
-       struct tg3_napi *tnapi = dev_id;
-       struct tg3 *tp = tnapi->tp;
-
-       prefetch(tnapi->hw_status);
-       if (tnapi->rx_rcb)
-               prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
-
-       if (likely(!tg3_irq_sync(tp)))
-               napi_schedule(&tnapi->napi);
-
-       return IRQ_HANDLED;
-}
-
-/* MSI ISR - No need to check for interrupt sharing and no need to
- * flush status block and interrupt mailbox. PCI ordering rules
- * guarantee that MSI will arrive after the status block.
- */
-static irqreturn_t tg3_msi(int irq, void *dev_id)
-{
-       struct tg3_napi *tnapi = dev_id;
-       struct tg3 *tp = tnapi->tp;
-
-       prefetch(tnapi->hw_status);
-       if (tnapi->rx_rcb)
-               prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
-       /*
-        * Writing any value to intr-mbox-0 clears PCI INTA# and
-        * chip-internal interrupt pending events.
-        * Writing non-zero to intr-mbox-0 additional tells the
-        * NIC to stop sending us irqs, engaging "in-intr-handler"
-        * event coalescing.
-        */
-       tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
-       if (likely(!tg3_irq_sync(tp)))
-               napi_schedule(&tnapi->napi);
-
-       return IRQ_RETVAL(1);
-}
-
 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
 {
        struct tg3_napi *tnapi = dev_id;
@@ -5050,21 +5006,6 @@ out:
        return IRQ_RETVAL(handled);
 }
 
-/* ISR for interrupt test */
-static irqreturn_t tg3_test_isr(int irq, void *dev_id)
-{
-       struct tg3_napi *tnapi = dev_id;
-       struct tg3 *tp = tnapi->tp;
-       struct tg3_hw_status *sblk = tnapi->hw_status;
-
-       if ((sblk->status & SD_STATUS_UPDATED) ||
-           !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
-               tg3_disable_ints(tp);
-               return IRQ_RETVAL(1);
-       }
-       return IRQ_RETVAL(0);
-}
-
 static int tg3_init_hw(struct tg3 *, int);
 static int tg3_halt(struct tg3 *, int, int);
 
@@ -6302,25 +6243,6 @@ static void tg3_restore_pci_state(struct tg3 *tp)
                pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
                                      pcix_cmd);
        }
-
-       if (tg3_flag(tp, 5780_CLASS)) {
-
-               /* Chip reset on 5780 will reset MSI enable bit,
-                * so need to restore it.
-                */
-               if (tg3_flag(tp, USING_MSI)) {
-                       u16 ctrl;
-
-                       pci_read_config_word(tp->pdev,
-                                            tp->msi_cap + PCI_MSI_FLAGS,
-                                            &ctrl);
-                       pci_write_config_word(tp->pdev,
-                                             tp->msi_cap + PCI_MSI_FLAGS,
-                                             ctrl | PCI_MSI_FLAGS_ENABLE);
-                       val = tr32(MSGINT_MODE);
-                       tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
-               }
-       }
 }
 
 static void tg3_stop_fw(struct tg3 *);
@@ -7650,12 +7572,6 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
        tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
        udelay(100);
 
-       if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1) {
-               val = tr32(MSGINT_MODE);
-               val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
-               tw32(MSGINT_MODE, val);
-       }
-
        if (!tg3_flag(tp, 5705_PLUS)) {
                tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
                udelay(40);
@@ -8151,12 +8067,7 @@ static int tg3_request_irq(struct tg3 *tp, int irq_num)
                name[IFNAMSIZ-1] = 0;
        }
 
-       if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
-               fn = tg3_msi;
-               if (tg3_flag(tp, 1SHOT_MSI))
-                       fn = tg3_msi_1shot;
-               flags = 0;
-       } else {
+       {
                fn = tg3_interrupt;
                if (tg3_flag(tp, TAGGED_STATUS))
                        fn = tg3_interrupt_tagged;
@@ -8166,137 +8077,6 @@ static int tg3_request_irq(struct tg3 *tp, int irq_num)
        return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
 }
 
-static int tg3_test_interrupt(struct tg3 *tp)
-{
-       struct tg3_napi *tnapi = &tp->napi[0];
-       struct net_device *dev = tp->dev;
-       int err, i, intr_ok = 0;
-       u32 val;
-
-       if (!netif_running(dev))
-               return -ENODEV;
-
-       tg3_disable_ints(tp);
-
-       free_irq(tnapi->irq_vec, tnapi);
-
-       /*
-        * Turn off MSI one shot mode.  Otherwise this test has no
-        * observable way to know whether the interrupt was delivered.
-        */
-       if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
-               val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
-               tw32(MSGINT_MODE, val);
-       }
-
-       err = request_irq(tnapi->irq_vec, tg3_test_isr,
-                         IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
-       if (err)
-               return err;
-
-       tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
-       tg3_enable_ints(tp);
-
-       tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
-              tnapi->coal_now);
-
-       for (i = 0; i < 5; i++) {
-               u32 int_mbox, misc_host_ctrl;
-
-               int_mbox = tr32_mailbox(tnapi->int_mbox);
-               misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
-
-               if ((int_mbox != 0) ||
-                   (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
-                       intr_ok = 1;
-                       break;
-               }
-
-               msleep(10);
-       }
-
-       tg3_disable_ints(tp);
-
-       free_irq(tnapi->irq_vec, tnapi);
-
-       err = tg3_request_irq(tp, 0);
-
-       if (err)
-               return err;
-
-       if (intr_ok) {
-               /* Reenable MSI one shot mode. */
-               if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
-                       val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
-                       tw32(MSGINT_MODE, val);
-               }
-               return 0;
-       }
-
-       return -EIO;
-}
-
-/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
- * successfully restored
- */
-static int tg3_test_msi(struct tg3 *tp)
-{
-       int err;
-       u16 pci_cmd;
-
-       if (!tg3_flag(tp, USING_MSI))
-               return 0;
-
-       /* Turn off SERR reporting in case MSI terminates with Master
-        * Abort.
-        */
-       pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
-       pci_write_config_word(tp->pdev, PCI_COMMAND,
-                             pci_cmd & ~PCI_COMMAND_SERR);
-
-       err = tg3_test_interrupt(tp);
-
-       pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
-
-       if (!err)
-               return 0;
-
-       /* other failures */
-       if (err != -EIO)
-               return err;
-
-       /* MSI test failed, go back to INTx mode */
-       netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
-                   "to INTx mode. Please report this failure to the PCI "
-                   "maintainer and include system chipset information\n");
-
-       free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
-
-       pci_disable_msi(tp->pdev);
-
-       tg3_flag_clear(tp, USING_MSI);
-       tp->napi[0].irq_vec = tp->pdev->irq;
-
-       err = tg3_request_irq(tp, 0);
-       if (err)
-               return err;
-
-       /* Need to reset the chip because the MSI cycle may have terminated
-        * with Master Abort.
-        */
-       tg3_full_lock(tp, 1);
-
-       tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
-       err = tg3_init_hw(tp, 1);
-
-       tg3_full_unlock(tp);
-
-       if (err)
-               free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
-
-       return err;
-}
-
 static int tg3_request_firmware(struct tg3 *tp)
 {
        const __be32 *fw_data;
@@ -8328,103 +8108,12 @@ static int tg3_request_firmware(struct tg3 *tp)
        return 0;
 }
 
-static bool tg3_enable_msix(struct tg3 *tp)
-{
-       int i, rc, cpus = num_online_cpus();
-       struct msix_entry msix_ent[tp->irq_max];
-
-       if (cpus == 1)
-               /* Just fallback to the simpler MSI mode. */
-               return false;
-
-       /*
-        * We want as many rx rings enabled as there are cpus.
-        * The first MSIX vector only deals with link interrupts, etc,
-        * so we add one to the number of vectors we are requesting.
-        */
-       tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
-
-       for (i = 0; i < tp->irq_max; i++) {
-               msix_ent[i].entry  = i;
-               msix_ent[i].vector = 0;
-       }
-
-       rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
-       if (rc < 0) {
-               return false;
-       } else if (rc != 0) {
-               if (pci_enable_msix(tp->pdev, msix_ent, rc))
-                       return false;
-               netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
-                             tp->irq_cnt, rc);
-               tp->irq_cnt = rc;
-       }
-
-       for (i = 0; i < tp->irq_max; i++)
-               tp->napi[i].irq_vec = msix_ent[i].vector;
-
-       netif_set_real_num_tx_queues(tp->dev, 1);
-       rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1;
-       if (netif_set_real_num_rx_queues(tp->dev, rc)) {
-               pci_disable_msix(tp->pdev);
-               return false;
-       }
-
-       if (tp->irq_cnt > 1) {
-               tg3_flag_set(tp, ENABLE_RSS);
-
-               if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
-                   GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
-                       tg3_flag_set(tp, ENABLE_TSS);
-                       netif_set_real_num_tx_queues(tp->dev, tp->irq_cnt - 1);
-               }
-       }
-
-       return true;
-}
-
 static void tg3_ints_init(struct tg3 *tp)
 {
-       if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
-           !tg3_flag(tp, TAGGED_STATUS)) {
-               /* All MSI supporting chips should support tagged
-                * status.  Assert that this is the case.
-                */
-               netdev_warn(tp->dev,
-                           "MSI without TAGGED_STATUS? Not using MSI\n");
-               goto defcfg;
-       }
-
-       if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
-               tg3_flag_set(tp, USING_MSIX);
-       else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
-               tg3_flag_set(tp, USING_MSI);
-
-       if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
-               u32 msi_mode = tr32(MSGINT_MODE);
-               if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
-                       msi_mode |= MSGINT_MODE_MULTIVEC_EN;
-               tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
-       }
-defcfg:
-       if (!tg3_flag(tp, USING_MSIX)) {
-               tp->irq_cnt = 1;
-               tp->napi[0].irq_vec = tp->pdev->irq;
-               netif_set_real_num_tx_queues(tp->dev, 1);
-               netif_set_real_num_rx_queues(tp->dev, 1);
-       }
-}
-
-static void tg3_ints_fini(struct tg3 *tp)
-{
-       if (tg3_flag(tp, USING_MSIX))
-               pci_disable_msix(tp->pdev);
-       else if (tg3_flag(tp, USING_MSI))
-               pci_disable_msi(tp->pdev);
-       tg3_flag_clear(tp, USING_MSI);
-       tg3_flag_clear(tp, USING_MSIX);
-       tg3_flag_clear(tp, ENABLE_RSS);
-       tg3_flag_clear(tp, ENABLE_TSS);
+       tp->irq_cnt = 1;
+       tp->napi[0].irq_vec = tp->pdev->irq;
+       netif_set_real_num_tx_queues(tp->dev, 1);
+       netif_set_real_num_rx_queues(tp->dev, 1);
 }
 
 static int tg3_open(struct net_device *dev)
@@ -8518,26 +8207,6 @@ static int tg3_open(struct net_device *dev)
        if (err)
                goto err_out3;
 
-       if (tg3_flag(tp, USING_MSI)) {
-               err = tg3_test_msi(tp);
-
-               if (err) {
-                       tg3_full_lock(tp, 0);
-                       tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
-                       tg3_free_rings(tp);
-                       tg3_full_unlock(tp);
-
-                       goto err_out2;
-               }
-
-               if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
-                       u32 val = tr32(PCIE_TRANSACTION_CFG);
-
-                       tw32(PCIE_TRANSACTION_CFG,
-                            val | PCIE_TRANS_CFG_1SHOT_MSI);
-               }
-       }
-
        tg3_phy_start(tp);
 
        tg3_full_lock(tp, 0);
@@ -8571,7 +8240,6 @@ err_out2:
        tg3_free_consistent(tp);
 
 err_out1:
-       tg3_ints_fini(tp);
        return err;
 }
 
@@ -8604,8 +8272,6 @@ static int tg3_close(struct net_device *dev)
                free_irq(tnapi->irq_vec, tnapi);
        }
 
-       tg3_ints_fini(tp);
-
        tg3_napi_fini(tp);
 
        tg3_free_consistent(tp);
@@ -10623,26 +10289,6 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
 
        tp->irq_max = 1;
 
-       if (tg3_flag(tp, 5750_PLUS)) {
-               tg3_flag_set(tp, SUPPORT_MSI);
-               if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
-                   GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
-                   (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
-                    tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
-                    tp->pdev_peer == tp->pdev))
-                       tg3_flag_clear(tp, SUPPORT_MSI);
-
-               if (tg3_flag(tp, 5755_PLUS) ||
-                   GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
-                       tg3_flag_set(tp, 1SHOT_MSI);
-               }
-
-               if (tg3_flag(tp, 57765_PLUS)) {
-                       tg3_flag_set(tp, SUPPORT_MSIX);
-                       tp->irq_max = TG3_IRQ_MAX_VECS;
-               }
-       }
-
        if (tg3_flag(tp, 5717_PLUS))
                tg3_flag_set(tp, LRG_PROD_RING_CAP);