Initial commit.
authorThomas Miletich <thomas.miletich@gmail.com>
Wed, 25 May 2011 15:04:39 +0000 (17:04 +0200)
committerThomas Miletich <thomas.miletich@gmail.com>
Wed, 25 May 2011 15:04:39 +0000 (17:04 +0200)
.gitignore [new file with mode: 0644]
Makefile [new file with mode: 0644]
tg3.c [new file with mode: 0644]
tg3.h [new file with mode: 0644]

diff --git a/.gitignore b/.gitignore
new file mode 100644 (file)
index 0000000..dd9e363
--- /dev/null
@@ -0,0 +1,8 @@
+*.ko
+*.o
+*.cmd
+*.mod.c
+*.order
+*.symvers
+.tmp_versions/
+
diff --git a/Makefile b/Makefile
new file mode 100644 (file)
index 0000000..4752769
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,9 @@
+
+obj-m += tg3.o
+
+all:
+       make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
+
+clean:
+       make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean
+
diff --git a/tg3.c b/tg3.c
new file mode 100644 (file)
index 0000000..c44913a
--- /dev/null
+++ b/tg3.c
@@ -0,0 +1,15562 @@
+/*
+ * tg3.c: Broadcom Tigon3 ethernet driver.
+ *
+ * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
+ * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
+ * Copyright (C) 2004 Sun Microsystems Inc.
+ * Copyright (C) 2005-2011 Broadcom Corporation.
+ *
+ * Firmware is:
+ *     Derived from proprietary unpublished source code,
+ *     Copyright (C) 2000-2003 Broadcom Corporation.
+ *
+ *     Permission is hereby granted for the distribution of this firmware
+ *     data in hexadecimal or equivalent format, provided this copyright
+ *     notice is accompanying it.
+ */
+
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/stringify.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/compiler.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/in.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/pci.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/ethtool.h>
+#include <linux/mdio.h>
+#include <linux/mii.h>
+#include <linux/phy.h>
+#include <linux/brcmphy.h>
+#include <linux/if_vlan.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/workqueue.h>
+#include <linux/prefetch.h>
+#include <linux/dma-mapping.h>
+#include <linux/firmware.h>
+
+#include <net/checksum.h>
+#include <net/ip.h>
+
+#include <asm/system.h>
+#include <linux/io.h>
+#include <asm/byteorder.h>
+#include <linux/uaccess.h>
+
+#ifdef CONFIG_SPARC
+#include <asm/idprom.h>
+#include <asm/prom.h>
+#endif
+
+#define BAR_0  0
+#define BAR_2  2
+
+#include "tg3.h"
+
+/* Functions & macros to verify TG3_FLAGS types */
+
+static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
+{
+       return test_bit(flag, bits);
+}
+
+static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
+{
+       set_bit(flag, bits);
+}
+
+static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
+{
+       clear_bit(flag, bits);
+}
+
+#define tg3_flag(tp, flag)                             \
+       _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
+#define tg3_flag_set(tp, flag)                         \
+       _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
+#define tg3_flag_clear(tp, flag)                       \
+       _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
+
+#define DRV_MODULE_NAME                "tg3"
+#define TG3_MAJ_NUM                    3
+#define TG3_MIN_NUM                    119
+#define DRV_MODULE_VERSION     \
+       __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
+#define DRV_MODULE_RELDATE     "May 18, 2011"
+
+#define TG3_DEF_MAC_MODE       0
+#define TG3_DEF_RX_MODE                0
+#define TG3_DEF_TX_MODE                0
+#define TG3_DEF_MSG_ENABLE       \
+       (NETIF_MSG_DRV          | \
+        NETIF_MSG_PROBE        | \
+        NETIF_MSG_LINK         | \
+        NETIF_MSG_TIMER        | \
+        NETIF_MSG_IFDOWN       | \
+        NETIF_MSG_IFUP         | \
+        NETIF_MSG_RX_ERR       | \
+        NETIF_MSG_TX_ERR)
+
+/* length of time before we decide the hardware is borked,
+ * and dev->tx_timeout() should be called to fix the problem
+ */
+
+#define TG3_TX_TIMEOUT                 (5 * HZ)
+
+/* hardware minimum and maximum for a single frame's data payload */
+#define TG3_MIN_MTU                    60
+#define TG3_MAX_MTU(tp)        \
+       (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
+
+/* These numbers seem to be hard coded in the NIC firmware somehow.
+ * You can't change the ring sizes, but you can change where you place
+ * them in the NIC onboard memory.
+ */
+#define TG3_RX_STD_RING_SIZE(tp) \
+       (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
+        TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
+#define TG3_DEF_RX_RING_PENDING                200
+#define TG3_RX_JMB_RING_SIZE(tp) \
+       (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
+        TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
+#define TG3_DEF_RX_JUMBO_RING_PENDING  100
+#define TG3_RSS_INDIR_TBL_SIZE         128
+
+/* Do not place this n-ring entries value into the tp struct itself,
+ * we really want to expose these constants to GCC so that modulo et
+ * al.  operations are done with shifts and masks instead of with
+ * hw multiply/modulo instructions.  Another solution would be to
+ * replace things like '% foo' with '& (foo - 1)'.
+ */
+
+#define TG3_TX_RING_SIZE               512
+#define TG3_DEF_TX_RING_PENDING                (TG3_TX_RING_SIZE - 1)
+
+#define TG3_RX_STD_RING_BYTES(tp) \
+       (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
+#define TG3_RX_JMB_RING_BYTES(tp) \
+       (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
+#define TG3_RX_RCB_RING_BYTES(tp) \
+       (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
+#define TG3_TX_RING_BYTES      (sizeof(struct tg3_tx_buffer_desc) * \
+                                TG3_TX_RING_SIZE)
+#define NEXT_TX(N)             (((N) + 1) & (TG3_TX_RING_SIZE - 1))
+
+#define TG3_DMA_BYTE_ENAB              64
+
+#define TG3_RX_STD_DMA_SZ              1536
+#define TG3_RX_JMB_DMA_SZ              9046
+
+#define TG3_RX_DMA_TO_MAP_SZ(x)                ((x) + TG3_DMA_BYTE_ENAB)
+
+#define TG3_RX_STD_MAP_SZ              TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
+#define TG3_RX_JMB_MAP_SZ              TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
+
+#define TG3_RX_STD_BUFF_RING_SIZE(tp) \
+       (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
+
+#define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
+       (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
+
+/* Due to a hardware bug, the 5701 can only DMA to memory addresses
+ * that are at least dword aligned when used in PCIX mode.  The driver
+ * works around this bug by double copying the packet.  This workaround
+ * is built into the normal double copy length check for efficiency.
+ *
+ * However, the double copy is only necessary on those architectures
+ * where unaligned memory accesses are inefficient.  For those architectures
+ * where unaligned memory accesses incur little penalty, we can reintegrate
+ * the 5701 in the normal rx path.  Doing so saves a device structure
+ * dereference by hardcoding the double copy threshold in place.
+ */
+#define TG3_RX_COPY_THRESHOLD          256
+#if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
+       #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
+#else
+       #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
+#endif
+
+/* minimum number of free TX descriptors required to wake up TX process */
+#define TG3_TX_WAKEUP_THRESH(tnapi)            ((tnapi)->tx_pending / 4)
+
+#define TG3_RAW_IP_ALIGN 2
+
+#define TG3_FW_UPDATE_TIMEOUT_SEC      5
+
+#define FIRMWARE_TG3           "tigon/tg3.bin"
+#define FIRMWARE_TG3TSO                "tigon/tg3_tso.bin"
+#define FIRMWARE_TG3TSO5       "tigon/tg3_tso5.bin"
+
+static char version[] __devinitdata =
+       DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
+
+MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
+MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
+MODULE_LICENSE("GPL");
+MODULE_VERSION(DRV_MODULE_VERSION);
+MODULE_FIRMWARE(FIRMWARE_TG3);
+MODULE_FIRMWARE(FIRMWARE_TG3TSO);
+MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
+
+static int tg3_debug = -1;     /* -1 == use TG3_DEF_MSG_ENABLE as value */
+module_param(tg3_debug, int, 0);
+MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
+
+static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
+       {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
+       {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
+       {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
+       {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
+       {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
+       {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
+       {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
+       {}
+};
+
+MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
+
+static const struct {
+       const char string[ETH_GSTRING_LEN];
+} ethtool_stats_keys[] = {
+       { "rx_octets" },
+       { "rx_fragments" },
+       { "rx_ucast_packets" },
+       { "rx_mcast_packets" },
+       { "rx_bcast_packets" },
+       { "rx_fcs_errors" },
+       { "rx_align_errors" },
+       { "rx_xon_pause_rcvd" },
+       { "rx_xoff_pause_rcvd" },
+       { "rx_mac_ctrl_rcvd" },
+       { "rx_xoff_entered" },
+       { "rx_frame_too_long_errors" },
+       { "rx_jabbers" },
+       { "rx_undersize_packets" },
+       { "rx_in_length_errors" },
+       { "rx_out_length_errors" },
+       { "rx_64_or_less_octet_packets" },
+       { "rx_65_to_127_octet_packets" },
+       { "rx_128_to_255_octet_packets" },
+       { "rx_256_to_511_octet_packets" },
+       { "rx_512_to_1023_octet_packets" },
+       { "rx_1024_to_1522_octet_packets" },
+       { "rx_1523_to_2047_octet_packets" },
+       { "rx_2048_to_4095_octet_packets" },
+       { "rx_4096_to_8191_octet_packets" },
+       { "rx_8192_to_9022_octet_packets" },
+
+       { "tx_octets" },
+       { "tx_collisions" },
+
+       { "tx_xon_sent" },
+       { "tx_xoff_sent" },
+       { "tx_flow_control" },
+       { "tx_mac_errors" },
+       { "tx_single_collisions" },
+       { "tx_mult_collisions" },
+       { "tx_deferred" },
+       { "tx_excessive_collisions" },
+       { "tx_late_collisions" },
+       { "tx_collide_2times" },
+       { "tx_collide_3times" },
+       { "tx_collide_4times" },
+       { "tx_collide_5times" },
+       { "tx_collide_6times" },
+       { "tx_collide_7times" },
+       { "tx_collide_8times" },
+       { "tx_collide_9times" },
+       { "tx_collide_10times" },
+       { "tx_collide_11times" },
+       { "tx_collide_12times" },
+       { "tx_collide_13times" },
+       { "tx_collide_14times" },
+       { "tx_collide_15times" },
+       { "tx_ucast_packets" },
+       { "tx_mcast_packets" },
+       { "tx_bcast_packets" },
+       { "tx_carrier_sense_errors" },
+       { "tx_discards" },
+       { "tx_errors" },
+
+       { "dma_writeq_full" },
+       { "dma_write_prioq_full" },
+       { "rxbds_empty" },
+       { "rx_discards" },
+       { "rx_errors" },
+       { "rx_threshold_hit" },
+
+       { "dma_readq_full" },
+       { "dma_read_prioq_full" },
+       { "tx_comp_queue_full" },
+
+       { "ring_set_send_prod_index" },
+       { "ring_status_update" },
+       { "nic_irqs" },
+       { "nic_avoided_irqs" },
+       { "nic_tx_threshold_hit" },
+
+       { "mbuf_lwm_thresh_hit" },
+};
+
+#define TG3_NUM_STATS  ARRAY_SIZE(ethtool_stats_keys)
+
+
+static const struct {
+       const char string[ETH_GSTRING_LEN];
+} ethtool_test_keys[] = {
+       { "nvram test     (online) " },
+       { "link test      (online) " },
+       { "register test  (offline)" },
+       { "memory test    (offline)" },
+       { "loopback test  (offline)" },
+       { "interrupt test (offline)" },
+};
+
+#define TG3_NUM_TEST   ARRAY_SIZE(ethtool_test_keys)
+
+
+static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
+{
+       writel(val, tp->regs + off);
+}
+
+static u32 tg3_read32(struct tg3 *tp, u32 off)
+{
+       return readl(tp->regs + off);
+}
+
+static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
+{
+       writel(val, tp->aperegs + off);
+}
+
+static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
+{
+       return readl(tp->aperegs + off);
+}
+
+static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
+{
+       unsigned long flags;
+
+       spin_lock_irqsave(&tp->indirect_lock, flags);
+       pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
+       pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
+       spin_unlock_irqrestore(&tp->indirect_lock, flags);
+}
+
+static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
+{
+       writel(val, tp->regs + off);
+       readl(tp->regs + off);
+}
+
+static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
+{
+       unsigned long flags;
+       u32 val;
+
+       spin_lock_irqsave(&tp->indirect_lock, flags);
+       pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
+       pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
+       spin_unlock_irqrestore(&tp->indirect_lock, flags);
+       return val;
+}
+
+static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
+{
+       unsigned long flags;
+
+       if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
+               pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
+                                      TG3_64BIT_REG_LOW, val);
+               return;
+       }
+       if (off == TG3_RX_STD_PROD_IDX_REG) {
+               pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
+                                      TG3_64BIT_REG_LOW, val);
+               return;
+       }
+
+       spin_lock_irqsave(&tp->indirect_lock, flags);
+       pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
+       pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
+       spin_unlock_irqrestore(&tp->indirect_lock, flags);
+
+       /* In indirect mode when disabling interrupts, we also need
+        * to clear the interrupt bit in the GRC local ctrl register.
+        */
+       if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
+           (val == 0x1)) {
+               pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
+                                      tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
+       }
+}
+
+static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
+{
+       unsigned long flags;
+       u32 val;
+
+       spin_lock_irqsave(&tp->indirect_lock, flags);
+       pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
+       pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
+       spin_unlock_irqrestore(&tp->indirect_lock, flags);
+       return val;
+}
+
+/* usec_wait specifies the wait time in usec when writing to certain registers
+ * where it is unsafe to read back the register without some delay.
+ * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
+ * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
+ */
+static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
+{
+       if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
+               /* Non-posted methods */
+               tp->write32(tp, off, val);
+       else {
+               /* Posted method */
+               tg3_write32(tp, off, val);
+               if (usec_wait)
+                       udelay(usec_wait);
+               tp->read32(tp, off);
+       }
+       /* Wait again after the read for the posted method to guarantee that
+        * the wait time is met.
+        */
+       if (usec_wait)
+               udelay(usec_wait);
+}
+
+static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
+{
+       tp->write32_mbox(tp, off, val);
+       if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND))
+               tp->read32_mbox(tp, off);
+}
+
+static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
+{
+       void __iomem *mbox = tp->regs + off;
+       writel(val, mbox);
+       if (tg3_flag(tp, TXD_MBOX_HWBUG))
+               writel(val, mbox);
+       if (tg3_flag(tp, MBOX_WRITE_REORDER))
+               readl(mbox);
+}
+
+static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
+{
+       return readl(tp->regs + off + GRCMBOX_BASE);
+}
+
+static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
+{
+       writel(val, tp->regs + off + GRCMBOX_BASE);
+}
+
+#define tw32_mailbox(reg, val)         tp->write32_mbox(tp, reg, val)
+#define tw32_mailbox_f(reg, val)       tw32_mailbox_flush(tp, (reg), (val))
+#define tw32_rx_mbox(reg, val)         tp->write32_rx_mbox(tp, reg, val)
+#define tw32_tx_mbox(reg, val)         tp->write32_tx_mbox(tp, reg, val)
+#define tr32_mailbox(reg)              tp->read32_mbox(tp, reg)
+
+#define tw32(reg, val)                 tp->write32(tp, reg, val)
+#define tw32_f(reg, val)               _tw32_flush(tp, (reg), (val), 0)
+#define tw32_wait_f(reg, val, us)      _tw32_flush(tp, (reg), (val), (us))
+#define tr32(reg)                      tp->read32(tp, reg)
+
+static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
+{
+       unsigned long flags;
+
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
+           (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
+               return;
+
+       spin_lock_irqsave(&tp->indirect_lock, flags);
+       if (tg3_flag(tp, SRAM_USE_CONFIG)) {
+               pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
+               pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
+
+               /* Always leave this as zero. */
+               pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
+       } else {
+               tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
+               tw32_f(TG3PCI_MEM_WIN_DATA, val);
+
+               /* Always leave this as zero. */
+               tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
+       }
+       spin_unlock_irqrestore(&tp->indirect_lock, flags);
+}
+
+static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
+{
+       unsigned long flags;
+
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
+           (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
+               *val = 0;
+               return;
+       }
+
+       spin_lock_irqsave(&tp->indirect_lock, flags);
+       if (tg3_flag(tp, SRAM_USE_CONFIG)) {
+               pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
+               pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
+
+               /* Always leave this as zero. */
+               pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
+       } else {
+               tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
+               *val = tr32(TG3PCI_MEM_WIN_DATA);
+
+               /* Always leave this as zero. */
+               tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
+       }
+       spin_unlock_irqrestore(&tp->indirect_lock, flags);
+}
+
+static void tg3_ape_lock_init(struct tg3 *tp)
+{
+       int i;
+       u32 regbase;
+
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
+               regbase = TG3_APE_LOCK_GRANT;
+       else
+               regbase = TG3_APE_PER_LOCK_GRANT;
+
+       /* Make sure the driver hasn't any stale locks. */
+       for (i = 0; i < 8; i++)
+               tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
+}
+
+static int tg3_ape_lock(struct tg3 *tp, int locknum)
+{
+       int i, off;
+       int ret = 0;
+       u32 status, req, gnt;
+
+       if (!tg3_flag(tp, ENABLE_APE))
+               return 0;
+
+       switch (locknum) {
+       case TG3_APE_LOCK_GRC:
+       case TG3_APE_LOCK_MEM:
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
+               req = TG3_APE_LOCK_REQ;
+               gnt = TG3_APE_LOCK_GRANT;
+       } else {
+               req = TG3_APE_PER_LOCK_REQ;
+               gnt = TG3_APE_PER_LOCK_GRANT;
+       }
+
+       off = 4 * locknum;
+
+       tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
+
+       /* Wait for up to 1 millisecond to acquire lock. */
+       for (i = 0; i < 100; i++) {
+               status = tg3_ape_read32(tp, gnt + off);
+               if (status == APE_LOCK_GRANT_DRIVER)
+                       break;
+               udelay(10);
+       }
+
+       if (status != APE_LOCK_GRANT_DRIVER) {
+               /* Revoke the lock request. */
+               tg3_ape_write32(tp, gnt + off,
+                               APE_LOCK_GRANT_DRIVER);
+
+               ret = -EBUSY;
+       }
+
+       return ret;
+}
+
+static void tg3_ape_unlock(struct tg3 *tp, int locknum)
+{
+       u32 gnt;
+
+       if (!tg3_flag(tp, ENABLE_APE))
+               return;
+
+       switch (locknum) {
+       case TG3_APE_LOCK_GRC:
+       case TG3_APE_LOCK_MEM:
+               break;
+       default:
+               return;
+       }
+
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
+               gnt = TG3_APE_LOCK_GRANT;
+       else
+               gnt = TG3_APE_PER_LOCK_GRANT;
+
+       tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
+}
+
+static void tg3_disable_ints(struct tg3 *tp)
+{
+       int i;
+
+       tw32(TG3PCI_MISC_HOST_CTRL,
+            (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
+       for (i = 0; i < tp->irq_max; i++)
+               tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
+}
+
+static void tg3_enable_ints(struct tg3 *tp)
+{
+       int i;
+
+       tp->irq_sync = 0;
+       wmb();
+
+       tw32(TG3PCI_MISC_HOST_CTRL,
+            (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
+
+       tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
+       for (i = 0; i < tp->irq_cnt; i++) {
+               struct tg3_napi *tnapi = &tp->napi[i];
+
+               tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
+               if (tg3_flag(tp, 1SHOT_MSI))
+                       tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
+
+               tp->coal_now |= tnapi->coal_now;
+       }
+
+       /* Force an initial interrupt */
+       if (!tg3_flag(tp, TAGGED_STATUS) &&
+           (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
+               tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
+       else
+               tw32(HOSTCC_MODE, tp->coal_now);
+
+       tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
+}
+
+static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
+{
+       struct tg3 *tp = tnapi->tp;
+       struct tg3_hw_status *sblk = tnapi->hw_status;
+       unsigned int work_exists = 0;
+
+       /* check for phy events */
+       if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
+               if (sblk->status & SD_STATUS_LINK_CHG)
+                       work_exists = 1;
+       }
+       /* check for RX/TX work to do */
+       if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
+           *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
+               work_exists = 1;
+
+       return work_exists;
+}
+
+/* tg3_int_reenable
+ *  similar to tg3_enable_ints, but it accurately determines whether there
+ *  is new work pending and can return without flushing the PIO write
+ *  which reenables interrupts
+ */
+static void tg3_int_reenable(struct tg3_napi *tnapi)
+{
+       struct tg3 *tp = tnapi->tp;
+
+       tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
+       mmiowb();
+
+       /* When doing tagged status, this work check is unnecessary.
+        * The last_tag we write above tells the chip which piece of
+        * work we've completed.
+        */
+       if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
+               tw32(HOSTCC_MODE, tp->coalesce_mode |
+                    HOSTCC_MODE_ENABLE | tnapi->coal_now);
+}
+
+static void tg3_switch_clocks(struct tg3 *tp)
+{
+       u32 clock_ctrl;
+       u32 orig_clock_ctrl;
+
+       if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
+               return;
+
+       clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
+
+       orig_clock_ctrl = clock_ctrl;
+       clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
+                      CLOCK_CTRL_CLKRUN_OENABLE |
+                      0x1f);
+       tp->pci_clock_ctrl = clock_ctrl;
+
+       if (tg3_flag(tp, 5705_PLUS)) {
+               if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
+                       tw32_wait_f(TG3PCI_CLOCK_CTRL,
+                                   clock_ctrl | CLOCK_CTRL_625_CORE, 40);
+               }
+       } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
+               tw32_wait_f(TG3PCI_CLOCK_CTRL,
+                           clock_ctrl |
+                           (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
+                           40);
+               tw32_wait_f(TG3PCI_CLOCK_CTRL,
+                           clock_ctrl | (CLOCK_CTRL_ALTCLK),
+                           40);
+       }
+       tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
+}
+
+#define PHY_BUSY_LOOPS 5000
+
+static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
+{
+       u32 frame_val;
+       unsigned int loops;
+       int ret;
+
+       if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
+               tw32_f(MAC_MI_MODE,
+                    (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
+               udelay(80);
+       }
+
+       *val = 0x0;
+
+       frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
+                     MI_COM_PHY_ADDR_MASK);
+       frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
+                     MI_COM_REG_ADDR_MASK);
+       frame_val |= (MI_COM_CMD_READ | MI_COM_START);
+
+       tw32_f(MAC_MI_COM, frame_val);
+
+       loops = PHY_BUSY_LOOPS;
+       while (loops != 0) {
+               udelay(10);
+               frame_val = tr32(MAC_MI_COM);
+
+               if ((frame_val & MI_COM_BUSY) == 0) {
+                       udelay(5);
+                       frame_val = tr32(MAC_MI_COM);
+                       break;
+               }
+               loops -= 1;
+       }
+
+       ret = -EBUSY;
+       if (loops != 0) {
+               *val = frame_val & MI_COM_DATA_MASK;
+               ret = 0;
+       }
+
+       if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
+               tw32_f(MAC_MI_MODE, tp->mi_mode);
+               udelay(80);
+       }
+
+       return ret;
+}
+
+static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
+{
+       u32 frame_val;
+       unsigned int loops;
+       int ret;
+
+       if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
+           (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
+               return 0;
+
+       if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
+               tw32_f(MAC_MI_MODE,
+                    (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
+               udelay(80);
+       }
+
+       frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
+                     MI_COM_PHY_ADDR_MASK);
+       frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
+                     MI_COM_REG_ADDR_MASK);
+       frame_val |= (val & MI_COM_DATA_MASK);
+       frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
+
+       tw32_f(MAC_MI_COM, frame_val);
+
+       loops = PHY_BUSY_LOOPS;
+       while (loops != 0) {
+               udelay(10);
+               frame_val = tr32(MAC_MI_COM);
+               if ((frame_val & MI_COM_BUSY) == 0) {
+                       udelay(5);
+                       frame_val = tr32(MAC_MI_COM);
+                       break;
+               }
+               loops -= 1;
+       }
+
+       ret = -EBUSY;
+       if (loops != 0)
+               ret = 0;
+
+       if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
+               tw32_f(MAC_MI_MODE, tp->mi_mode);
+               udelay(80);
+       }
+
+       return ret;
+}
+
+static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
+{
+       int err;
+
+       err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
+       if (err)
+               goto done;
+
+       err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
+       if (err)
+               goto done;
+
+       err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
+                          MII_TG3_MMD_CTRL_DATA_NOINC | devad);
+       if (err)
+               goto done;
+
+       err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
+
+done:
+       return err;
+}
+
+static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
+{
+       int err;
+
+       err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
+       if (err)
+               goto done;
+
+       err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
+       if (err)
+               goto done;
+
+       err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
+                          MII_TG3_MMD_CTRL_DATA_NOINC | devad);
+       if (err)
+               goto done;
+
+       err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
+
+done:
+       return err;
+}
+
+static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
+{
+       int err;
+
+       err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
+       if (!err)
+               err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
+
+       return err;
+}
+
+static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
+{
+       int err;
+
+       err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
+       if (!err)
+               err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
+
+       return err;
+}
+
+static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
+{
+       int err;
+
+       err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
+                          (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
+                          MII_TG3_AUXCTL_SHDWSEL_MISC);
+       if (!err)
+               err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
+
+       return err;
+}
+
+static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
+{
+       if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
+               set |= MII_TG3_AUXCTL_MISC_WREN;
+
+       return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
+}
+
+#define TG3_PHY_AUXCTL_SMDSP_ENABLE(tp) \
+       tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
+                            MII_TG3_AUXCTL_ACTL_SMDSP_ENA | \
+                            MII_TG3_AUXCTL_ACTL_TX_6DB)
+
+#define TG3_PHY_AUXCTL_SMDSP_DISABLE(tp) \
+       tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
+                            MII_TG3_AUXCTL_ACTL_TX_6DB);
+
+static int tg3_bmcr_reset(struct tg3 *tp)
+{
+       u32 phy_control;
+       int limit, err;
+
+       /* OK, reset it, and poll the BMCR_RESET bit until it
+        * clears or we time out.
+        */
+       phy_control = BMCR_RESET;
+       err = tg3_writephy(tp, MII_BMCR, phy_control);
+       if (err != 0)
+               return -EBUSY;
+
+       limit = 5000;
+       while (limit--) {
+               err = tg3_readphy(tp, MII_BMCR, &phy_control);
+               if (err != 0)
+                       return -EBUSY;
+
+               if ((phy_control & BMCR_RESET) == 0) {
+                       udelay(40);
+                       break;
+               }
+               udelay(10);
+       }
+       if (limit < 0)
+               return -EBUSY;
+
+       return 0;
+}
+
+static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
+{
+       struct tg3 *tp = bp->priv;
+       u32 val;
+
+       spin_lock_bh(&tp->lock);
+
+       if (tg3_readphy(tp, reg, &val))
+               val = -EIO;
+
+       spin_unlock_bh(&tp->lock);
+
+       return val;
+}
+
+static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
+{
+       struct tg3 *tp = bp->priv;
+       u32 ret = 0;
+
+       spin_lock_bh(&tp->lock);
+
+       if (tg3_writephy(tp, reg, val))
+               ret = -EIO;
+
+       spin_unlock_bh(&tp->lock);
+
+       return ret;
+}
+
+static int tg3_mdio_reset(struct mii_bus *bp)
+{
+       return 0;
+}
+
+static void tg3_mdio_config_5785(struct tg3 *tp)
+{
+       u32 val;
+       struct phy_device *phydev;
+
+       phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
+       switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
+       case PHY_ID_BCM50610:
+       case PHY_ID_BCM50610M:
+               val = MAC_PHYCFG2_50610_LED_MODES;
+               break;
+       case PHY_ID_BCMAC131:
+               val = MAC_PHYCFG2_AC131_LED_MODES;
+               break;
+       case PHY_ID_RTL8211C:
+               val = MAC_PHYCFG2_RTL8211C_LED_MODES;
+               break;
+       case PHY_ID_RTL8201E:
+               val = MAC_PHYCFG2_RTL8201E_LED_MODES;
+               break;
+       default:
+               return;
+       }
+
+       if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
+               tw32(MAC_PHYCFG2, val);
+
+               val = tr32(MAC_PHYCFG1);
+               val &= ~(MAC_PHYCFG1_RGMII_INT |
+                        MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
+               val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
+               tw32(MAC_PHYCFG1, val);
+
+               return;
+       }
+
+       if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
+               val |= MAC_PHYCFG2_EMODE_MASK_MASK |
+                      MAC_PHYCFG2_FMODE_MASK_MASK |
+                      MAC_PHYCFG2_GMODE_MASK_MASK |
+                      MAC_PHYCFG2_ACT_MASK_MASK   |
+                      MAC_PHYCFG2_QUAL_MASK_MASK |
+                      MAC_PHYCFG2_INBAND_ENABLE;
+
+       tw32(MAC_PHYCFG2, val);
+
+       val = tr32(MAC_PHYCFG1);
+       val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
+                MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
+       if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
+               if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
+                       val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
+               if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
+                       val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
+       }
+       val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
+              MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
+       tw32(MAC_PHYCFG1, val);
+
+       val = tr32(MAC_EXT_RGMII_MODE);
+       val &= ~(MAC_RGMII_MODE_RX_INT_B |
+                MAC_RGMII_MODE_RX_QUALITY |
+                MAC_RGMII_MODE_RX_ACTIVITY |
+                MAC_RGMII_MODE_RX_ENG_DET |
+                MAC_RGMII_MODE_TX_ENABLE |
+                MAC_RGMII_MODE_TX_LOWPWR |
+                MAC_RGMII_MODE_TX_RESET);
+       if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
+               if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
+                       val |= MAC_RGMII_MODE_RX_INT_B |
+                              MAC_RGMII_MODE_RX_QUALITY |
+                              MAC_RGMII_MODE_RX_ACTIVITY |
+                              MAC_RGMII_MODE_RX_ENG_DET;
+               if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
+                       val |= MAC_RGMII_MODE_TX_ENABLE |
+                              MAC_RGMII_MODE_TX_LOWPWR |
+                              MAC_RGMII_MODE_TX_RESET;
+       }
+       tw32(MAC_EXT_RGMII_MODE, val);
+}
+
+static void tg3_mdio_start(struct tg3 *tp)
+{
+       tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
+       tw32_f(MAC_MI_MODE, tp->mi_mode);
+       udelay(80);
+
+       if (tg3_flag(tp, MDIOBUS_INITED) &&
+           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
+               tg3_mdio_config_5785(tp);
+}
+
+static int tg3_mdio_init(struct tg3 *tp)
+{
+       int i;
+       u32 reg;
+       struct phy_device *phydev;
+
+       if (tg3_flag(tp, 5717_PLUS)) {
+               u32 is_serdes;
+
+               tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
+
+               if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
+                       is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
+               else
+                       is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
+                                   TG3_CPMU_PHY_STRAP_IS_SERDES;
+               if (is_serdes)
+                       tp->phy_addr += 7;
+       } else
+               tp->phy_addr = TG3_PHY_MII_ADDR;
+
+       tg3_mdio_start(tp);
+
+       if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
+               return 0;
+
+       tp->mdio_bus = mdiobus_alloc();
+       if (tp->mdio_bus == NULL)
+               return -ENOMEM;
+
+       tp->mdio_bus->name     = "tg3 mdio bus";
+       snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
+                (tp->pdev->bus->number << 8) | tp->pdev->devfn);
+       tp->mdio_bus->priv     = tp;
+       tp->mdio_bus->parent   = &tp->pdev->dev;
+       tp->mdio_bus->read     = &tg3_mdio_read;
+       tp->mdio_bus->write    = &tg3_mdio_write;
+       tp->mdio_bus->reset    = &tg3_mdio_reset;
+       tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
+       tp->mdio_bus->irq      = &tp->mdio_irq[0];
+
+       for (i = 0; i < PHY_MAX_ADDR; i++)
+               tp->mdio_bus->irq[i] = PHY_POLL;
+
+       /* The bus registration will look for all the PHYs on the mdio bus.
+        * Unfortunately, it does not ensure the PHY is powered up before
+        * accessing the PHY ID registers.  A chip reset is the
+        * quickest way to bring the device back to an operational state..
+        */
+       if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
+               tg3_bmcr_reset(tp);
+
+       i = mdiobus_register(tp->mdio_bus);
+       if (i) {
+               dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
+               mdiobus_free(tp->mdio_bus);
+               return i;
+       }
+
+       phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
+
+       if (!phydev || !phydev->drv) {
+               dev_warn(&tp->pdev->dev, "No PHY devices\n");
+               mdiobus_unregister(tp->mdio_bus);
+               mdiobus_free(tp->mdio_bus);
+               return -ENODEV;
+       }
+
+       switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
+       case PHY_ID_BCM57780:
+               phydev->interface = PHY_INTERFACE_MODE_GMII;
+               phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
+               break;
+       case PHY_ID_BCM50610:
+       case PHY_ID_BCM50610M:
+               phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
+                                    PHY_BRCM_RX_REFCLK_UNUSED |
+                                    PHY_BRCM_DIS_TXCRXC_NOENRGY |
+                                    PHY_BRCM_AUTO_PWRDWN_ENABLE;
+               if (tg3_flag(tp, RGMII_INBAND_DISABLE))
+                       phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
+               if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
+                       phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
+               if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
+                       phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
+               /* fallthru */
+       case PHY_ID_RTL8211C:
+               phydev->interface = PHY_INTERFACE_MODE_RGMII;
+               break;
+       case PHY_ID_RTL8201E:
+       case PHY_ID_BCMAC131:
+               phydev->interface = PHY_INTERFACE_MODE_MII;
+               phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
+               tp->phy_flags |= TG3_PHYFLG_IS_FET;
+               break;
+       }
+
+       tg3_flag_set(tp, MDIOBUS_INITED);
+
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
+               tg3_mdio_config_5785(tp);
+
+       return 0;
+}
+
+static void tg3_mdio_fini(struct tg3 *tp)
+{
+       if (tg3_flag(tp, MDIOBUS_INITED)) {
+               tg3_flag_clear(tp, MDIOBUS_INITED);
+               mdiobus_unregister(tp->mdio_bus);
+               mdiobus_free(tp->mdio_bus);
+       }
+}
+
+/* tp->lock is held. */
+static inline void tg3_generate_fw_event(struct tg3 *tp)
+{
+       u32 val;
+
+       val = tr32(GRC_RX_CPU_EVENT);
+       val |= GRC_RX_CPU_DRIVER_EVENT;
+       tw32_f(GRC_RX_CPU_EVENT, val);
+
+       tp->last_event_jiffies = jiffies;
+}
+
+#define TG3_FW_EVENT_TIMEOUT_USEC 2500
+
+/* tp->lock is held. */
+static void tg3_wait_for_event_ack(struct tg3 *tp)
+{
+       int i;
+       unsigned int delay_cnt;
+       long time_remain;
+
+       /* If enough time has passed, no wait is necessary. */
+       time_remain = (long)(tp->last_event_jiffies + 1 +
+                     usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
+                     (long)jiffies;
+       if (time_remain < 0)
+               return;
+
+       /* Check if we can shorten the wait time. */
+       delay_cnt = jiffies_to_usecs(time_remain);
+       if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
+               delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
+       delay_cnt = (delay_cnt >> 3) + 1;
+
+       for (i = 0; i < delay_cnt; i++) {
+               if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
+                       break;
+               udelay(8);
+       }
+}
+
+/* tp->lock is held. */
+static void tg3_ump_link_report(struct tg3 *tp)
+{
+       u32 reg;
+       u32 val;
+
+       if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
+               return;
+
+       tg3_wait_for_event_ack(tp);
+
+       tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
+
+       tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
+
+       val = 0;
+       if (!tg3_readphy(tp, MII_BMCR, &reg))
+               val = reg << 16;
+       if (!tg3_readphy(tp, MII_BMSR, &reg))
+               val |= (reg & 0xffff);
+       tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
+
+       val = 0;
+       if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
+               val = reg << 16;
+       if (!tg3_readphy(tp, MII_LPA, &reg))
+               val |= (reg & 0xffff);
+       tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
+
+       val = 0;
+       if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
+               if (!tg3_readphy(tp, MII_CTRL1000, &reg))
+                       val = reg << 16;
+               if (!tg3_readphy(tp, MII_STAT1000, &reg))
+                       val |= (reg & 0xffff);
+       }
+       tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
+
+       if (!tg3_readphy(tp, MII_PHYADDR, &reg))
+               val = reg << 16;
+       else
+               val = 0;
+       tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
+
+       tg3_generate_fw_event(tp);
+}
+
+static void tg3_link_report(struct tg3 *tp)
+{
+       if (!netif_carrier_ok(tp->dev)) {
+               netif_info(tp, link, tp->dev, "Link is down\n");
+               tg3_ump_link_report(tp);
+       } else if (netif_msg_link(tp)) {
+               netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
+                           (tp->link_config.active_speed == SPEED_1000 ?
+                            1000 :
+                            (tp->link_config.active_speed == SPEED_100 ?
+                             100 : 10)),
+                           (tp->link_config.active_duplex == DUPLEX_FULL ?
+                            "full" : "half"));
+
+               netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
+                           (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
+                           "on" : "off",
+                           (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
+                           "on" : "off");
+
+               if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
+                       netdev_info(tp->dev, "EEE is %s\n",
+                                   tp->setlpicnt ? "enabled" : "disabled");
+
+               tg3_ump_link_report(tp);
+       }
+}
+
+static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
+{
+       u16 miireg;
+
+       if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
+               miireg = ADVERTISE_PAUSE_CAP;
+       else if (flow_ctrl & FLOW_CTRL_TX)
+               miireg = ADVERTISE_PAUSE_ASYM;
+       else if (flow_ctrl & FLOW_CTRL_RX)
+               miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
+       else
+               miireg = 0;
+
+       return miireg;
+}
+
+static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
+{
+       u16 miireg;
+
+       if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
+               miireg = ADVERTISE_1000XPAUSE;
+       else if (flow_ctrl & FLOW_CTRL_TX)
+               miireg = ADVERTISE_1000XPSE_ASYM;
+       else if (flow_ctrl & FLOW_CTRL_RX)
+               miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
+       else
+               miireg = 0;
+
+       return miireg;
+}
+
+static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
+{
+       u8 cap = 0;
+
+       if (lcladv & ADVERTISE_1000XPAUSE) {
+               if (lcladv & ADVERTISE_1000XPSE_ASYM) {
+                       if (rmtadv & LPA_1000XPAUSE)
+                               cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
+                       else if (rmtadv & LPA_1000XPAUSE_ASYM)
+                               cap = FLOW_CTRL_RX;
+               } else {
+                       if (rmtadv & LPA_1000XPAUSE)
+                               cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
+               }
+       } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
+               if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
+                       cap = FLOW_CTRL_TX;
+       }
+
+       return cap;
+}
+
+static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
+{
+       u8 autoneg;
+       u8 flowctrl = 0;
+       u32 old_rx_mode = tp->rx_mode;
+       u32 old_tx_mode = tp->tx_mode;
+
+       if (tg3_flag(tp, USE_PHYLIB))
+               autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
+       else
+               autoneg = tp->link_config.autoneg;
+
+       if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
+               if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
+                       flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
+               else
+                       flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
+       } else
+               flowctrl = tp->link_config.flowctrl;
+
+       tp->link_config.active_flowctrl = flowctrl;
+
+       if (flowctrl & FLOW_CTRL_RX)
+               tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
+       else
+               tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
+
+       if (old_rx_mode != tp->rx_mode)
+               tw32_f(MAC_RX_MODE, tp->rx_mode);
+
+       if (flowctrl & FLOW_CTRL_TX)
+               tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
+       else
+               tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
+
+       if (old_tx_mode != tp->tx_mode)
+               tw32_f(MAC_TX_MODE, tp->tx_mode);
+}
+
+static void tg3_adjust_link(struct net_device *dev)
+{
+       u8 oldflowctrl, linkmesg = 0;
+       u32 mac_mode, lcl_adv, rmt_adv;
+       struct tg3 *tp = netdev_priv(dev);
+       struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
+
+       spin_lock_bh(&tp->lock);
+
+       mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
+                                   MAC_MODE_HALF_DUPLEX);
+
+       oldflowctrl = tp->link_config.active_flowctrl;
+
+       if (phydev->link) {
+               lcl_adv = 0;
+               rmt_adv = 0;
+
+               if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
+                       mac_mode |= MAC_MODE_PORT_MODE_MII;
+               else if (phydev->speed == SPEED_1000 ||
+                        GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
+                       mac_mode |= MAC_MODE_PORT_MODE_GMII;
+               else
+                       mac_mode |= MAC_MODE_PORT_MODE_MII;
+
+               if (phydev->duplex == DUPLEX_HALF)
+                       mac_mode |= MAC_MODE_HALF_DUPLEX;
+               else {
+                       lcl_adv = tg3_advert_flowctrl_1000T(
+                                 tp->link_config.flowctrl);
+
+                       if (phydev->pause)
+                               rmt_adv = LPA_PAUSE_CAP;
+                       if (phydev->asym_pause)
+                               rmt_adv |= LPA_PAUSE_ASYM;
+               }
+
+               tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
+       } else
+               mac_mode |= MAC_MODE_PORT_MODE_GMII;
+
+       if (mac_mode != tp->mac_mode) {
+               tp->mac_mode = mac_mode;
+               tw32_f(MAC_MODE, tp->mac_mode);
+               udelay(40);
+       }
+
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
+               if (phydev->speed == SPEED_10)
+                       tw32(MAC_MI_STAT,
+                            MAC_MI_STAT_10MBPS_MODE |
+                            MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
+               else
+                       tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
+       }
+
+       if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
+               tw32(MAC_TX_LENGTHS,
+                    ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
+                     (6 << TX_LENGTHS_IPG_SHIFT) |
+                     (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
+       else
+               tw32(MAC_TX_LENGTHS,
+                    ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
+                     (6 << TX_LENGTHS_IPG_SHIFT) |
+                     (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
+
+       if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
+           (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
+           phydev->speed != tp->link_config.active_speed ||
+           phydev->duplex != tp->link_config.active_duplex ||
+           oldflowctrl != tp->link_config.active_flowctrl)
+               linkmesg = 1;
+
+       tp->link_config.active_speed = phydev->speed;
+       tp->link_config.active_duplex = phydev->duplex;
+
+       spin_unlock_bh(&tp->lock);
+
+       if (linkmesg)
+               tg3_link_report(tp);
+}
+
+static int tg3_phy_init(struct tg3 *tp)
+{
+       struct phy_device *phydev;
+
+       if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
+               return 0;
+
+       /* Bring the PHY back to a known state. */
+       tg3_bmcr_reset(tp);
+
+       phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
+
+       /* Attach the MAC to the PHY. */
+       phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
+                            phydev->dev_flags, phydev->interface);
+       if (IS_ERR(phydev)) {
+               dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
+               return PTR_ERR(phydev);
+       }
+
+       /* Mask with MAC supported features. */
+       switch (phydev->interface) {
+       case PHY_INTERFACE_MODE_GMII:
+       case PHY_INTERFACE_MODE_RGMII:
+               if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
+                       phydev->supported &= (PHY_GBIT_FEATURES |
+                                             SUPPORTED_Pause |
+                                             SUPPORTED_Asym_Pause);
+                       break;
+               }
+               /* fallthru */
+       case PHY_INTERFACE_MODE_MII:
+               phydev->supported &= (PHY_BASIC_FEATURES |
+                                     SUPPORTED_Pause |
+                                     SUPPORTED_Asym_Pause);
+               break;
+       default:
+               phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
+               return -EINVAL;
+       }
+
+       tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
+
+       phydev->advertising = phydev->supported;
+
+       return 0;
+}
+
+static void tg3_phy_start(struct tg3 *tp)
+{
+       struct phy_device *phydev;
+
+       if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
+               return;
+
+       phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
+
+       if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
+               tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
+               phydev->speed = tp->link_config.orig_speed;
+               phydev->duplex = tp->link_config.orig_duplex;
+               phydev->autoneg = tp->link_config.orig_autoneg;
+               phydev->advertising = tp->link_config.orig_advertising;
+       }
+
+       phy_start(phydev);
+
+       phy_start_aneg(phydev);
+}
+
+static void tg3_phy_stop(struct tg3 *tp)
+{
+       if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
+               return;
+
+       phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
+}
+
+static void tg3_phy_fini(struct tg3 *tp)
+{
+       if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
+               phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
+               tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
+       }
+}
+
+static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
+{
+       u32 phytest;
+
+       if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
+               u32 phy;
+
+               tg3_writephy(tp, MII_TG3_FET_TEST,
+                            phytest | MII_TG3_FET_SHADOW_EN);
+               if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
+                       if (enable)
+                               phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
+                       else
+                               phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
+                       tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
+               }
+               tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
+       }
+}
+
+static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
+{
+       u32 reg;
+
+       if (!tg3_flag(tp, 5705_PLUS) ||
+           (tg3_flag(tp, 5717_PLUS) &&
+            (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
+               return;
+
+       if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
+               tg3_phy_fet_toggle_apd(tp, enable);
+               return;
+       }
+
+       reg = MII_TG3_MISC_SHDW_WREN |
+             MII_TG3_MISC_SHDW_SCR5_SEL |
+             MII_TG3_MISC_SHDW_SCR5_LPED |
+             MII_TG3_MISC_SHDW_SCR5_DLPTLM |
+             MII_TG3_MISC_SHDW_SCR5_SDTL |
+             MII_TG3_MISC_SHDW_SCR5_C125OE;
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
+               reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
+
+       tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
+
+
+       reg = MII_TG3_MISC_SHDW_WREN |
+             MII_TG3_MISC_SHDW_APD_SEL |
+             MII_TG3_MISC_SHDW_APD_WKTM_84MS;
+       if (enable)
+               reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
+
+       tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
+}
+
+static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
+{
+       u32 phy;
+
+       if (!tg3_flag(tp, 5705_PLUS) ||
+           (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
+               return;
+
+       if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
+               u32 ephy;
+
+               if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
+                       u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
+
+                       tg3_writephy(tp, MII_TG3_FET_TEST,
+                                    ephy | MII_TG3_FET_SHADOW_EN);
+                       if (!tg3_readphy(tp, reg, &phy)) {
+                               if (enable)
+                                       phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
+                               else
+                                       phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
+                               tg3_writephy(tp, reg, phy);
+                       }
+                       tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
+               }
+       } else {
+               int ret;
+
+               ret = tg3_phy_auxctl_read(tp,
+                                         MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
+               if (!ret) {
+                       if (enable)
+                               phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
+                       else
+                               phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
+                       tg3_phy_auxctl_write(tp,
+                                            MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
+               }
+       }
+}
+
+static void tg3_phy_set_wirespeed(struct tg3 *tp)
+{
+       int ret;
+       u32 val;
+
+       if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
+               return;
+
+       ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
+       if (!ret)
+               tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
+                                    val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
+}
+
+static void tg3_phy_apply_otp(struct tg3 *tp)
+{
+       u32 otp, phy;
+
+       if (!tp->phy_otp)
+               return;
+
+       otp = tp->phy_otp;
+
+       if (TG3_PHY_AUXCTL_SMDSP_ENABLE(tp))
+               return;
+
+       phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
+       phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
+       tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
+
+       phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
+             ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
+       tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
+
+       phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
+       phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
+       tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
+
+       phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
+       tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
+
+       phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
+       tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
+
+       phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
+             ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
+       tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
+
+       TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
+}
+
+static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
+{
+       u32 val;
+
+       if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
+               return;
+
+       tp->setlpicnt = 0;
+
+       if (tp->link_config.autoneg == AUTONEG_ENABLE &&
+           current_link_up == 1 &&
+           tp->link_config.active_duplex == DUPLEX_FULL &&
+           (tp->link_config.active_speed == SPEED_100 ||
+            tp->link_config.active_speed == SPEED_1000)) {
+               u32 eeectl;
+
+               if (tp->link_config.active_speed == SPEED_1000)
+                       eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
+               else
+                       eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
+
+               tw32(TG3_CPMU_EEE_CTRL, eeectl);
+
+               tg3_phy_cl45_read(tp, MDIO_MMD_AN,
+                                 TG3_CL45_D7_EEERES_STAT, &val);
+
+               if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
+                   val == TG3_CL45_D7_EEERES_STAT_LP_100TX)
+                       tp->setlpicnt = 2;
+       }
+
+       if (!tp->setlpicnt) {
+               val = tr32(TG3_CPMU_EEE_MODE);
+               tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
+       }
+}
+
+static void tg3_phy_eee_enable(struct tg3 *tp)
+{
+       u32 val;
+
+       if (tp->link_config.active_speed == SPEED_1000 &&
+           (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
+            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
+            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
+           !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
+               tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0003);
+               TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
+       }
+
+       val = tr32(TG3_CPMU_EEE_MODE);
+       tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
+}
+
+static int tg3_wait_macro_done(struct tg3 *tp)
+{
+       int limit = 100;
+
+       while (limit--) {
+               u32 tmp32;
+
+               if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
+                       if ((tmp32 & 0x1000) == 0)
+                               break;
+               }
+       }
+       if (limit < 0)
+               return -EBUSY;
+
+       return 0;
+}
+
+static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
+{
+       static const u32 test_pat[4][6] = {
+       { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
+       { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
+       { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
+       { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
+       };
+       int chan;
+
+       for (chan = 0; chan < 4; chan++) {
+               int i;
+
+               tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
+                            (chan * 0x2000) | 0x0200);
+               tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
+
+               for (i = 0; i < 6; i++)
+                       tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
+                                    test_pat[chan][i]);
+
+               tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
+               if (tg3_wait_macro_done(tp)) {
+                       *resetp = 1;
+                       return -EBUSY;
+               }
+
+               tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
+                            (chan * 0x2000) | 0x0200);
+               tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
+               if (tg3_wait_macro_done(tp)) {
+                       *resetp = 1;
+                       return -EBUSY;
+               }
+
+               tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
+               if (tg3_wait_macro_done(tp)) {
+                       *resetp = 1;
+                       return -EBUSY;
+               }
+
+               for (i = 0; i < 6; i += 2) {
+                       u32 low, high;
+
+                       if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
+                           tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
+                           tg3_wait_macro_done(tp)) {
+                               *resetp = 1;
+                               return -EBUSY;
+                       }
+                       low &= 0x7fff;
+                       high &= 0x000f;
+                       if (low != test_pat[chan][i] ||
+                           high != test_pat[chan][i+1]) {
+                               tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
+                               tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
+                               tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
+
+                               return -EBUSY;
+                       }
+               }
+       }
+
+       return 0;
+}
+
+static int tg3_phy_reset_chanpat(struct tg3 *tp)
+{
+       int chan;
+
+       for (chan = 0; chan < 4; chan++) {
+               int i;
+
+               tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
+                            (chan * 0x2000) | 0x0200);
+               tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
+               for (i = 0; i < 6; i++)
+                       tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
+               tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
+               if (tg3_wait_macro_done(tp))
+                       return -EBUSY;
+       }
+
+       return 0;
+}
+
+static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
+{
+       u32 reg32, phy9_orig;
+       int retries, do_phy_reset, err;
+
+       retries = 10;
+       do_phy_reset = 1;
+       do {
+               if (do_phy_reset) {
+                       err = tg3_bmcr_reset(tp);
+                       if (err)
+                               return err;
+                       do_phy_reset = 0;
+               }
+
+               /* Disable transmitter and interrupt.  */
+               if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
+                       continue;
+
+               reg32 |= 0x3000;
+               tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
+
+               /* Set full-duplex, 1000 mbps.  */
+               tg3_writephy(tp, MII_BMCR,
+                            BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
+
+               /* Set to master mode.  */
+               if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
+                       continue;
+
+               tg3_writephy(tp, MII_TG3_CTRL,
+                            (MII_TG3_CTRL_AS_MASTER |
+                             MII_TG3_CTRL_ENABLE_AS_MASTER));
+
+               err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
+               if (err)
+                       return err;
+
+               /* Block the PHY control access.  */
+               tg3_phydsp_write(tp, 0x8005, 0x0800);
+
+               err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
+               if (!err)
+                       break;
+       } while (--retries);
+
+       err = tg3_phy_reset_chanpat(tp);
+       if (err)
+               return err;
+
+       tg3_phydsp_write(tp, 0x8005, 0x0000);
+
+       tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
+       tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
+
+       TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
+
+       tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
+
+       if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
+               reg32 &= ~0x3000;
+               tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
+       } else if (!err)
+               err = -EBUSY;
+
+       return err;
+}
+
+/* This will reset the tigon3 PHY if there is no valid
+ * link unless the FORCE argument is non-zero.
+ */
+static int tg3_phy_reset(struct tg3 *tp)
+{
+       u32 val, cpmuctrl;
+       int err;
+
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
+               val = tr32(GRC_MISC_CFG);
+               tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
+               udelay(40);
+       }
+       err  = tg3_readphy(tp, MII_BMSR, &val);
+       err |= tg3_readphy(tp, MII_BMSR, &val);
+       if (err != 0)
+               return -EBUSY;
+
+       if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
+               netif_carrier_off(tp->dev);
+               tg3_link_report(tp);
+       }
+
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
+           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
+           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
+               err = tg3_phy_reset_5703_4_5(tp);
+               if (err)
+                       return err;
+               goto out;
+       }
+
+       cpmuctrl = 0;
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
+           GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
+               cpmuctrl = tr32(TG3_CPMU_CTRL);
+               if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
+                       tw32(TG3_CPMU_CTRL,
+                            cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
+       }
+
+       err = tg3_bmcr_reset(tp);
+       if (err)
+               return err;
+
+       if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
+               val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
+               tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
+
+               tw32(TG3_CPMU_CTRL, cpmuctrl);
+       }
+
+       if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
+           GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
+               val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
+               if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
+                   CPMU_LSPD_1000MB_MACCLK_12_5) {
+                       val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
+                       udelay(40);
+                       tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
+               }
+       }
+
+       if (tg3_flag(tp, 5717_PLUS) &&
+           (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
+               return 0;
+
+       tg3_phy_apply_otp(tp);
+
+       if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
+               tg3_phy_toggle_apd(tp, true);
+       else
+               tg3_phy_toggle_apd(tp, false);
+
+out:
+       if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
+           !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
+               tg3_phydsp_write(tp, 0x201f, 0x2aaa);
+               tg3_phydsp_write(tp, 0x000a, 0x0323);
+               TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
+       }
+
+       if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
+               tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
+               tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
+       }
+
+       if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
+               if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
+                       tg3_phydsp_write(tp, 0x000a, 0x310b);
+                       tg3_phydsp_write(tp, 0x201f, 0x9506);
+                       tg3_phydsp_write(tp, 0x401f, 0x14e2);
+                       TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
+               }
+       } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
+               if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
+                       tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
+                       if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
+                               tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
+                               tg3_writephy(tp, MII_TG3_TEST1,
+                                            MII_TG3_TEST1_TRIM_EN | 0x4);
+                       } else
+                               tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
+
+                       TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
+               }
+       }
+
+       /* Set Extended packet length bit (bit 14) on all chips that */
+       /* support jumbo frames */
+       if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
+               /* Cannot do read-modify-write on 5401 */
+               tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
+       } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
+               /* Set bit 14 with read-modify-write to preserve other bits */
+               err = tg3_phy_auxctl_read(tp,
+                                         MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
+               if (!err)
+                       tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
+                                          val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
+       }
+
+       /* Set phy register 0x10 bit 0 to high fifo elasticity to support
+        * jumbo frames transmission.
+        */
+       if (tg3_flag(tp, JUMBO_CAPABLE)) {
+               if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
+                       tg3_writephy(tp, MII_TG3_EXT_CTRL,
+                                    val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
+       }
+
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
+               /* adjust output voltage */
+               tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
+       }
+
+       tg3_phy_toggle_automdix(tp, 1);
+       tg3_phy_set_wirespeed(tp);
+       return 0;
+}
+
+static void tg3_frob_aux_power(struct tg3 *tp)
+{
+       bool need_vaux = false;
+
+       /* The GPIOs do something completely different on 57765. */
+       if (!tg3_flag(tp, IS_NIC) ||
+           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
+           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
+               return;
+
+       if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
+            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
+            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
+            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) &&
+           tp->pdev_peer != tp->pdev) {
+               struct net_device *dev_peer;
+
+               dev_peer = pci_get_drvdata(tp->pdev_peer);
+
+               /* remove_one() may have been run on the peer. */
+               if (dev_peer) {
+                       struct tg3 *tp_peer = netdev_priv(dev_peer);
+
+                       if (tg3_flag(tp_peer, INIT_COMPLETE))
+                               return;
+
+                       if (tg3_flag(tp_peer, WOL_ENABLE) ||
+                           tg3_flag(tp_peer, ENABLE_ASF))
+                               need_vaux = true;
+               }
+       }
+
+       if (tg3_flag(tp, WOL_ENABLE) || tg3_flag(tp, ENABLE_ASF))
+               need_vaux = true;
+
+       if (need_vaux) {
+               if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
+                   GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
+                       tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
+                                   (GRC_LCLCTRL_GPIO_OE0 |
+                                    GRC_LCLCTRL_GPIO_OE1 |
+                                    GRC_LCLCTRL_GPIO_OE2 |
+                                    GRC_LCLCTRL_GPIO_OUTPUT0 |
+                                    GRC_LCLCTRL_GPIO_OUTPUT1),
+                                   100);
+               } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
+                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
+                       /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
+                       u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
+                                            GRC_LCLCTRL_GPIO_OE1 |
+                                            GRC_LCLCTRL_GPIO_OE2 |
+                                            GRC_LCLCTRL_GPIO_OUTPUT0 |
+                                            GRC_LCLCTRL_GPIO_OUTPUT1 |
+                                            tp->grc_local_ctrl;
+                       tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
+
+                       grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
+                       tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
+
+                       grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
+                       tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
+               } else {
+                       u32 no_gpio2;
+                       u32 grc_local_ctrl = 0;
+
+                       /* Workaround to prevent overdrawing Amps. */
+                       if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
+                           ASIC_REV_5714) {
+                               grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
+                               tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
+                                           grc_local_ctrl, 100);
+                       }
+
+                       /* On 5753 and variants, GPIO2 cannot be used. */
+                       no_gpio2 = tp->nic_sram_data_cfg &
+                                   NIC_SRAM_DATA_CFG_NO_GPIO2;
+
+                       grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
+                                        GRC_LCLCTRL_GPIO_OE1 |
+                                        GRC_LCLCTRL_GPIO_OE2 |
+                                        GRC_LCLCTRL_GPIO_OUTPUT1 |
+                                        GRC_LCLCTRL_GPIO_OUTPUT2;
+                       if (no_gpio2) {
+                               grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
+                                                   GRC_LCLCTRL_GPIO_OUTPUT2);
+                       }
+                       tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
+                                                   grc_local_ctrl, 100);
+
+                       grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
+
+                       tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
+                                                   grc_local_ctrl, 100);
+
+                       if (!no_gpio2) {
+                               grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
+                               tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
+                                           grc_local_ctrl, 100);
+                       }
+               }
+       } else {
+               if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
+                   GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
+                       tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
+                                   (GRC_LCLCTRL_GPIO_OE1 |
+                                    GRC_LCLCTRL_GPIO_OUTPUT1), 100);
+
+                       tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
+                                   GRC_LCLCTRL_GPIO_OE1, 100);
+
+                       tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
+                                   (GRC_LCLCTRL_GPIO_OE1 |
+                                    GRC_LCLCTRL_GPIO_OUTPUT1), 100);
+               }
+       }
+}
+
+static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
+{
+       if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
+               return 1;
+       else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
+               if (speed != SPEED_10)
+                       return 1;
+       } else if (speed == SPEED_10)
+               return 1;
+
+       return 0;
+}
+
+static int tg3_setup_phy(struct tg3 *, int);
+
+#define RESET_KIND_SHUTDOWN    0
+#define RESET_KIND_INIT                1
+#define RESET_KIND_SUSPEND     2
+
+static void tg3_write_sig_post_reset(struct tg3 *, int);
+static int tg3_halt_cpu(struct tg3 *, u32);
+
+static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
+{
+       u32 val;
+
+       if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
+               if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
+                       u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
+                       u32 serdes_cfg = tr32(MAC_SERDES_CFG);
+
+                       sg_dig_ctrl |=
+                               SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
+                       tw32(SG_DIG_CTRL, sg_dig_ctrl);
+                       tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
+               }
+               return;
+       }
+
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
+               tg3_bmcr_reset(tp);
+               val = tr32(GRC_MISC_CFG);
+               tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
+               udelay(40);
+               return;
+       } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
+               u32 phytest;
+               if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
+                       u32 phy;
+
+                       tg3_writephy(tp, MII_ADVERTISE, 0);
+                       tg3_writephy(tp, MII_BMCR,
+                                    BMCR_ANENABLE | BMCR_ANRESTART);
+
+                       tg3_writephy(tp, MII_TG3_FET_TEST,
+                                    phytest | MII_TG3_FET_SHADOW_EN);
+                       if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
+                               phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
+                               tg3_writephy(tp,
+                                            MII_TG3_FET_SHDW_AUXMODE4,
+                                            phy);
+                       }
+                       tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
+               }
+               return;
+       } else if (do_low_power) {
+               tg3_writephy(tp, MII_TG3_EXT_CTRL,
+                            MII_TG3_EXT_CTRL_FORCE_LED_OFF);
+
+               val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
+                     MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
+                     MII_TG3_AUXCTL_PCTL_VREG_11V;
+               tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
+       }
+
+       /* The PHY should not be powered down on some chips because
+        * of bugs.
+        */
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
+           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
+           (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
+            (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
+               return;
+
+       if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
+           GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
+               val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
+               val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
+               val |= CPMU_LSPD_1000MB_MACCLK_12_5;
+               tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
+       }
+
+       tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
+}
+
+/* tp->lock is held. */
+static int tg3_nvram_lock(struct tg3 *tp)
+{
+       if (tg3_flag(tp, NVRAM)) {
+               int i;
+
+               if (tp->nvram_lock_cnt == 0) {
+                       tw32(NVRAM_SWARB, SWARB_REQ_SET1);
+                       for (i = 0; i < 8000; i++) {
+                               if (tr32(NVRAM_SWARB) & SWARB_GNT1)
+                                       break;
+                               udelay(20);
+                       }
+                       if (i == 8000) {
+                               tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
+                               return -ENODEV;
+                       }
+               }
+               tp->nvram_lock_cnt++;
+       }
+       return 0;
+}
+
+/* tp->lock is held. */
+static void tg3_nvram_unlock(struct tg3 *tp)
+{
+       if (tg3_flag(tp, NVRAM)) {
+               if (tp->nvram_lock_cnt > 0)
+                       tp->nvram_lock_cnt--;
+               if (tp->nvram_lock_cnt == 0)
+                       tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
+       }
+}
+
+/* tp->lock is held. */
+static void tg3_enable_nvram_access(struct tg3 *tp)
+{
+       if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
+               u32 nvaccess = tr32(NVRAM_ACCESS);
+
+               tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
+       }
+}
+
+/* tp->lock is held. */
+static void tg3_disable_nvram_access(struct tg3 *tp)
+{
+       if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
+               u32 nvaccess = tr32(NVRAM_ACCESS);
+
+               tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
+       }
+}
+
+static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
+                                       u32 offset, u32 *val)
+{
+       u32 tmp;
+       int i;
+
+       if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
+               return -EINVAL;
+
+       tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
+                                       EEPROM_ADDR_DEVID_MASK |
+                                       EEPROM_ADDR_READ);
+       tw32(GRC_EEPROM_ADDR,
+            tmp |
+            (0 << EEPROM_ADDR_DEVID_SHIFT) |
+            ((offset << EEPROM_ADDR_ADDR_SHIFT) &
+             EEPROM_ADDR_ADDR_MASK) |
+            EEPROM_ADDR_READ | EEPROM_ADDR_START);
+
+       for (i = 0; i < 1000; i++) {
+               tmp = tr32(GRC_EEPROM_ADDR);
+
+               if (tmp & EEPROM_ADDR_COMPLETE)
+                       break;
+               msleep(1);
+       }
+       if (!(tmp & EEPROM_ADDR_COMPLETE))
+               return -EBUSY;
+
+       tmp = tr32(GRC_EEPROM_DATA);
+
+       /*
+        * The data will always be opposite the native endian
+        * format.  Perform a blind byteswap to compensate.
+        */
+       *val = swab32(tmp);
+
+       return 0;
+}
+
+#define NVRAM_CMD_TIMEOUT 10000
+
+static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
+{
+       int i;
+
+       tw32(NVRAM_CMD, nvram_cmd);
+       for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
+               udelay(10);
+               if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
+                       udelay(10);
+                       break;
+               }
+       }
+
+       if (i == NVRAM_CMD_TIMEOUT)
+               return -EBUSY;
+
+       return 0;
+}
+
+static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
+{
+       if (tg3_flag(tp, NVRAM) &&
+           tg3_flag(tp, NVRAM_BUFFERED) &&
+           tg3_flag(tp, FLASH) &&
+           !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
+           (tp->nvram_jedecnum == JEDEC_ATMEL))
+
+               addr = ((addr / tp->nvram_pagesize) <<
+                       ATMEL_AT45DB0X1B_PAGE_POS) +
+                      (addr % tp->nvram_pagesize);
+
+       return addr;
+}
+
+static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
+{
+       if (tg3_flag(tp, NVRAM) &&
+           tg3_flag(tp, NVRAM_BUFFERED) &&
+           tg3_flag(tp, FLASH) &&
+           !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
+           (tp->nvram_jedecnum == JEDEC_ATMEL))
+
+               addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
+                       tp->nvram_pagesize) +
+                      (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
+
+       return addr;
+}
+
+/* NOTE: Data read in from NVRAM is byteswapped according to
+ * the byteswapping settings for all other register accesses.
+ * tg3 devices are BE devices, so on a BE machine, the data
+ * returned will be exactly as it is seen in NVRAM.  On a LE
+ * machine, the 32-bit value will be byteswapped.
+ */
+static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
+{
+       int ret;
+
+       if (!tg3_flag(tp, NVRAM))
+               return tg3_nvram_read_using_eeprom(tp, offset, val);
+
+       offset = tg3_nvram_phys_addr(tp, offset);
+
+       if (offset > NVRAM_ADDR_MSK)
+               return -EINVAL;
+
+       ret = tg3_nvram_lock(tp);
+       if (ret)
+               return ret;
+
+       tg3_enable_nvram_access(tp);
+
+       tw32(NVRAM_ADDR, offset);
+       ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
+               NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
+
+       if (ret == 0)
+               *val = tr32(NVRAM_RDDATA);
+
+       tg3_disable_nvram_access(tp);
+
+       tg3_nvram_unlock(tp);
+
+       return ret;
+}
+
+/* Ensures NVRAM data is in bytestream format. */
+static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
+{
+       u32 v;
+       int res = tg3_nvram_read(tp, offset, &v);
+       if (!res)
+               *val = cpu_to_be32(v);
+       return res;
+}
+
+/* tp->lock is held. */
+static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
+{
+       u32 addr_high, addr_low;
+       int i;
+
+       addr_high = ((tp->dev->dev_addr[0] << 8) |
+                    tp->dev->dev_addr[1]);
+       addr_low = ((tp->dev->dev_addr[2] << 24) |
+                   (tp->dev->dev_addr[3] << 16) |
+                   (tp->dev->dev_addr[4] <<  8) |
+                   (tp->dev->dev_addr[5] <<  0));
+       for (i = 0; i < 4; i++) {
+               if (i == 1 && skip_mac_1)
+                       continue;
+               tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
+               tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
+       }
+
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
+           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
+               for (i = 0; i < 12; i++) {
+                       tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
+                       tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
+               }
+       }
+
+       addr_high = (tp->dev->dev_addr[0] +
+                    tp->dev->dev_addr[1] +
+                    tp->dev->dev_addr[2] +
+                    tp->dev->dev_addr[3] +
+                    tp->dev->dev_addr[4] +
+                    tp->dev->dev_addr[5]) &
+               TX_BACKOFF_SEED_MASK;
+       tw32(MAC_TX_BACKOFF_SEED, addr_high);
+}
+
+static void tg3_enable_register_access(struct tg3 *tp)
+{
+       /*
+        * Make sure register accesses (indirect or otherwise) will function
+        * correctly.
+        */
+       pci_write_config_dword(tp->pdev,
+                              TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
+}
+
+static int tg3_power_up(struct tg3 *tp)
+{
+       tg3_enable_register_access(tp);
+
+       pci_set_power_state(tp->pdev, PCI_D0);
+
+       /* Switch out of Vaux if it is a NIC */
+       if (tg3_flag(tp, IS_NIC))
+               tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
+
+       return 0;
+}
+
+static int tg3_power_down_prepare(struct tg3 *tp)
+{
+       u32 misc_host_ctrl;
+       bool device_should_wake, do_low_power;
+
+       tg3_enable_register_access(tp);
+
+       /* Restore the CLKREQ setting. */
+       if (tg3_flag(tp, CLKREQ_BUG)) {
+               u16 lnkctl;
+
+               pci_read_config_word(tp->pdev,
+                                    tp->pcie_cap + PCI_EXP_LNKCTL,
+                                    &lnkctl);
+               lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
+               pci_write_config_word(tp->pdev,
+                                     tp->pcie_cap + PCI_EXP_LNKCTL,
+                                     lnkctl);
+       }
+
+       misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
+       tw32(TG3PCI_MISC_HOST_CTRL,
+            misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
+
+       device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
+                            tg3_flag(tp, WOL_ENABLE);
+
+       if (tg3_flag(tp, USE_PHYLIB)) {
+               do_low_power = false;
+               if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
+                   !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
+                       struct phy_device *phydev;
+                       u32 phyid, advertising;
+
+                       phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
+
+                       tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
+
+                       tp->link_config.orig_speed = phydev->speed;
+                       tp->link_config.orig_duplex = phydev->duplex;
+                       tp->link_config.orig_autoneg = phydev->autoneg;
+                       tp->link_config.orig_advertising = phydev->advertising;
+
+                       advertising = ADVERTISED_TP |
+                                     ADVERTISED_Pause |
+                                     ADVERTISED_Autoneg |
+                                     ADVERTISED_10baseT_Half;
+
+                       if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
+                               if (tg3_flag(tp, WOL_SPEED_100MB))
+                                       advertising |=
+                                               ADVERTISED_100baseT_Half |
+                                               ADVERTISED_100baseT_Full |
+                                               ADVERTISED_10baseT_Full;
+                               else
+                                       advertising |= ADVERTISED_10baseT_Full;
+                       }
+
+                       phydev->advertising = advertising;
+
+                       phy_start_aneg(phydev);
+
+                       phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
+                       if (phyid != PHY_ID_BCMAC131) {
+                               phyid &= PHY_BCM_OUI_MASK;
+                               if (phyid == PHY_BCM_OUI_1 ||
+                                   phyid == PHY_BCM_OUI_2 ||
+                                   phyid == PHY_BCM_OUI_3)
+                                       do_low_power = true;
+                       }
+               }
+       } else {
+               do_low_power = true;
+
+               if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
+                       tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
+                       tp->link_config.orig_speed = tp->link_config.speed;
+                       tp->link_config.orig_duplex = tp->link_config.duplex;
+                       tp->link_config.orig_autoneg = tp->link_config.autoneg;
+               }
+
+               if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
+                       tp->link_config.speed = SPEED_10;
+                       tp->link_config.duplex = DUPLEX_HALF;
+                       tp->link_config.autoneg = AUTONEG_ENABLE;
+                       tg3_setup_phy(tp, 0);
+               }
+       }
+
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
+               u32 val;
+
+               val = tr32(GRC_VCPU_EXT_CTRL);
+               tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
+       } else if (!tg3_flag(tp, ENABLE_ASF)) {
+               int i;
+               u32 val;
+
+               for (i = 0; i < 200; i++) {
+                       tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
+                       if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
+                               break;
+                       msleep(1);
+               }
+       }
+       if (tg3_flag(tp, WOL_CAP))
+               tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
+                                                    WOL_DRV_STATE_SHUTDOWN |
+                                                    WOL_DRV_WOL |
+                                                    WOL_SET_MAGIC_PKT);
+
+       if (device_should_wake) {
+               u32 mac_mode;
+
+               if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
+                       if (do_low_power &&
+                           !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
+                               tg3_phy_auxctl_write(tp,
+                                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
+                                              MII_TG3_AUXCTL_PCTL_WOL_EN |
+                                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
+                                              MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
+                               udelay(40);
+                       }
+
+                       if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
+                               mac_mode = MAC_MODE_PORT_MODE_GMII;
+                       else
+                               mac_mode = MAC_MODE_PORT_MODE_MII;
+
+                       mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
+                       if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
+                           ASIC_REV_5700) {
+                               u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
+                                            SPEED_100 : SPEED_10;
+                               if (tg3_5700_link_polarity(tp, speed))
+                                       mac_mode |= MAC_MODE_LINK_POLARITY;
+                               else
+                                       mac_mode &= ~MAC_MODE_LINK_POLARITY;
+                       }
+               } else {
+                       mac_mode = MAC_MODE_PORT_MODE_TBI;
+               }
+
+               if (!tg3_flag(tp, 5750_PLUS))
+                       tw32(MAC_LED_CTRL, tp->led_ctrl);
+
+               mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
+               if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
+                   (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
+                       mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
+
+               if (tg3_flag(tp, ENABLE_APE))
+                       mac_mode |= MAC_MODE_APE_TX_EN |
+                                   MAC_MODE_APE_RX_EN |
+                                   MAC_MODE_TDE_ENABLE;
+
+               tw32_f(MAC_MODE, mac_mode);
+               udelay(100);
+
+               tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
+               udelay(10);
+       }
+
+       if (!tg3_flag(tp, WOL_SPEED_100MB) &&
+           (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
+            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
+               u32 base_val;
+
+               base_val = tp->pci_clock_ctrl;
+               base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
+                            CLOCK_CTRL_TXCLK_DISABLE);
+
+               tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
+                           CLOCK_CTRL_PWRDOWN_PLL133, 40);
+       } else if (tg3_flag(tp, 5780_CLASS) ||
+                  tg3_flag(tp, CPMU_PRESENT) ||
+                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
+               /* do nothing */
+       } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
+               u32 newbits1, newbits2;
+
+               if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
+                   GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
+                       newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
+                                   CLOCK_CTRL_TXCLK_DISABLE |
+                                   CLOCK_CTRL_ALTCLK);
+                       newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
+               } else if (tg3_flag(tp, 5705_PLUS)) {
+                       newbits1 = CLOCK_CTRL_625_CORE;
+                       newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
+               } else {
+                       newbits1 = CLOCK_CTRL_ALTCLK;
+                       newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
+               }
+
+               tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
+                           40);
+
+               tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
+                           40);
+
+               if (!tg3_flag(tp, 5705_PLUS)) {
+                       u32 newbits3;
+
+                       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
+                           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
+                               newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
+                                           CLOCK_CTRL_TXCLK_DISABLE |
+                                           CLOCK_CTRL_44MHZ_CORE);
+                       } else {
+                               newbits3 = CLOCK_CTRL_44MHZ_CORE;
+                       }
+
+                       tw32_wait_f(TG3PCI_CLOCK_CTRL,
+                                   tp->pci_clock_ctrl | newbits3, 40);
+               }
+       }
+
+       if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
+               tg3_power_down_phy(tp, do_low_power);
+
+       tg3_frob_aux_power(tp);
+
+       /* Workaround for unstable PLL clock */
+       if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
+           (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
+               u32 val = tr32(0x7d00);
+
+               val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
+               tw32(0x7d00, val);
+               if (!tg3_flag(tp, ENABLE_ASF)) {
+                       int err;
+
+                       err = tg3_nvram_lock(tp);
+                       tg3_halt_cpu(tp, RX_CPU_BASE);
+                       if (!err)
+                               tg3_nvram_unlock(tp);
+               }
+       }
+
+       tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
+
+       return 0;
+}
+
+static void tg3_power_down(struct tg3 *tp)
+{
+       tg3_power_down_prepare(tp);
+
+       pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
+       pci_set_power_state(tp->pdev, PCI_D3hot);
+}
+
+static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
+{
+       switch (val & MII_TG3_AUX_STAT_SPDMASK) {
+       case MII_TG3_AUX_STAT_10HALF:
+               *speed = SPEED_10;
+               *duplex = DUPLEX_HALF;
+               break;
+
+       case MII_TG3_AUX_STAT_10FULL:
+               *speed = SPEED_10;
+               *duplex = DUPLEX_FULL;
+               break;
+
+       case MII_TG3_AUX_STAT_100HALF:
+               *speed = SPEED_100;
+               *duplex = DUPLEX_HALF;
+               break;
+
+       case MII_TG3_AUX_STAT_100FULL:
+               *speed = SPEED_100;
+               *duplex = DUPLEX_FULL;
+               break;
+
+       case MII_TG3_AUX_STAT_1000HALF:
+               *speed = SPEED_1000;
+               *duplex = DUPLEX_HALF;
+               break;
+
+       case MII_TG3_AUX_STAT_1000FULL:
+               *speed = SPEED_1000;
+               *duplex = DUPLEX_FULL;
+               break;
+
+       default:
+               if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
+                       *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
+                                SPEED_10;
+                       *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
+                                 DUPLEX_HALF;
+                       break;
+               }
+               *speed = SPEED_INVALID;
+               *duplex = DUPLEX_INVALID;
+               break;
+       }
+}
+
+static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
+{
+       int err = 0;
+       u32 val, new_adv;
+
+       new_adv = ADVERTISE_CSMA;
+       if (advertise & ADVERTISED_10baseT_Half)
+               new_adv |= ADVERTISE_10HALF;
+       if (advertise & ADVERTISED_10baseT_Full)
+               new_adv |= ADVERTISE_10FULL;
+       if (advertise & ADVERTISED_100baseT_Half)
+               new_adv |= ADVERTISE_100HALF;
+       if (advertise & ADVERTISED_100baseT_Full)
+               new_adv |= ADVERTISE_100FULL;
+
+       new_adv |= tg3_advert_flowctrl_1000T(flowctrl);
+
+       err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
+       if (err)
+               goto done;
+
+       if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
+               goto done;
+
+       new_adv = 0;
+       if (advertise & ADVERTISED_1000baseT_Half)
+               new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
+       if (advertise & ADVERTISED_1000baseT_Full)
+               new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
+
+       if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
+           tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
+               new_adv |= (MII_TG3_CTRL_AS_MASTER |
+                           MII_TG3_CTRL_ENABLE_AS_MASTER);
+
+       err = tg3_writephy(tp, MII_TG3_CTRL, new_adv);
+       if (err)
+               goto done;
+
+       if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
+               goto done;
+
+       tw32(TG3_CPMU_EEE_MODE,
+            tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
+
+       err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
+       if (!err) {
+               u32 err2;
+
+               switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
+               case ASIC_REV_5717:
+               case ASIC_REV_57765:
+                       if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
+                               tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
+                                                MII_TG3_DSP_CH34TP2_HIBW01);
+                       /* Fall through */
+               case ASIC_REV_5719:
+                       val = MII_TG3_DSP_TAP26_ALNOKO |
+                             MII_TG3_DSP_TAP26_RMRXSTO |
+                             MII_TG3_DSP_TAP26_OPCSINPT;
+                       tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
+               }
+
+               val = 0;
+               /* Advertise 100-BaseTX EEE ability */
+               if (advertise & ADVERTISED_100baseT_Full)
+                       val |= MDIO_AN_EEE_ADV_100TX;
+               /* Advertise 1000-BaseT EEE ability */
+               if (advertise & ADVERTISED_1000baseT_Full)
+                       val |= MDIO_AN_EEE_ADV_1000T;
+               err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
+
+               err2 = TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
+               if (!err)
+                       err = err2;
+       }
+
+done:
+       return err;
+}
+
+static void tg3_phy_copper_begin(struct tg3 *tp)
+{
+       u32 new_adv;
+       int i;
+
+       if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
+               new_adv = ADVERTISED_10baseT_Half |
+                         ADVERTISED_10baseT_Full;
+               if (tg3_flag(tp, WOL_SPEED_100MB))
+                       new_adv |= ADVERTISED_100baseT_Half |
+                                  ADVERTISED_100baseT_Full;
+
+               tg3_phy_autoneg_cfg(tp, new_adv,
+                                   FLOW_CTRL_TX | FLOW_CTRL_RX);
+       } else if (tp->link_config.speed == SPEED_INVALID) {
+               if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
+                       tp->link_config.advertising &=
+                               ~(ADVERTISED_1000baseT_Half |
+                                 ADVERTISED_1000baseT_Full);
+
+               tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
+                                   tp->link_config.flowctrl);
+       } else {
+               /* Asking for a specific link mode. */
+               if (tp->link_config.speed == SPEED_1000) {
+                       if (tp->link_config.duplex == DUPLEX_FULL)
+                               new_adv = ADVERTISED_1000baseT_Full;
+                       else
+                               new_adv = ADVERTISED_1000baseT_Half;
+               } else if (tp->link_config.speed == SPEED_100) {
+                       if (tp->link_config.duplex == DUPLEX_FULL)
+                               new_adv = ADVERTISED_100baseT_Full;
+                       else
+                               new_adv = ADVERTISED_100baseT_Half;
+               } else {
+                       if (tp->link_config.duplex == DUPLEX_FULL)
+                               new_adv = ADVERTISED_10baseT_Full;
+                       else
+                               new_adv = ADVERTISED_10baseT_Half;
+               }
+
+               tg3_phy_autoneg_cfg(tp, new_adv,
+                                   tp->link_config.flowctrl);
+       }
+
+       if (tp->link_config.autoneg == AUTONEG_DISABLE &&
+           tp->link_config.speed != SPEED_INVALID) {
+               u32 bmcr, orig_bmcr;
+
+               tp->link_config.active_speed = tp->link_config.speed;
+               tp->link_config.active_duplex = tp->link_config.duplex;
+
+               bmcr = 0;
+               switch (tp->link_config.speed) {
+               default:
+               case SPEED_10:
+                       break;
+
+               case SPEED_100:
+                       bmcr |= BMCR_SPEED100;
+                       break;
+
+               case SPEED_1000:
+                       bmcr |= TG3_BMCR_SPEED1000;
+                       break;
+               }
+
+               if (tp->link_config.duplex == DUPLEX_FULL)
+                       bmcr |= BMCR_FULLDPLX;
+
+               if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
+                   (bmcr != orig_bmcr)) {
+                       tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
+                       for (i = 0; i < 1500; i++) {
+                               u32 tmp;
+
+                               udelay(10);
+                               if (tg3_readphy(tp, MII_BMSR, &tmp) ||
+                                   tg3_readphy(tp, MII_BMSR, &tmp))
+                                       continue;
+                               if (!(tmp & BMSR_LSTATUS)) {
+                                       udelay(40);
+                                       break;
+                               }
+                       }
+                       tg3_writephy(tp, MII_BMCR, bmcr);
+                       udelay(40);
+               }
+       } else {
+               tg3_writephy(tp, MII_BMCR,
+                            BMCR_ANENABLE | BMCR_ANRESTART);
+       }
+}
+
+static int tg3_init_5401phy_dsp(struct tg3 *tp)
+{
+       int err;
+
+       /* Turn off tap power management. */
+       /* Set Extended packet length bit */
+       err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
+
+       err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
+       err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
+       err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
+       err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
+       err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
+
+       udelay(40);
+
+       return err;
+}
+
+static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
+{
+       u32 adv_reg, all_mask = 0;
+
+       if (mask & ADVERTISED_10baseT_Half)
+               all_mask |= ADVERTISE_10HALF;
+       if (mask & ADVERTISED_10baseT_Full)
+               all_mask |= ADVERTISE_10FULL;
+       if (mask & ADVERTISED_100baseT_Half)
+               all_mask |= ADVERTISE_100HALF;
+       if (mask & ADVERTISED_100baseT_Full)
+               all_mask |= ADVERTISE_100FULL;
+
+       if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
+               return 0;
+
+       if ((adv_reg & all_mask) != all_mask)
+               return 0;
+       if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
+               u32 tg3_ctrl;
+
+               all_mask = 0;
+               if (mask & ADVERTISED_1000baseT_Half)
+                       all_mask |= ADVERTISE_1000HALF;
+               if (mask & ADVERTISED_1000baseT_Full)
+                       all_mask |= ADVERTISE_1000FULL;
+
+               if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
+                       return 0;
+
+               if ((tg3_ctrl & all_mask) != all_mask)
+                       return 0;
+       }
+       return 1;
+}
+
+static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
+{
+       u32 curadv, reqadv;
+
+       if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
+               return 1;
+
+       curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
+       reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
+
+       if (tp->link_config.active_duplex == DUPLEX_FULL) {
+               if (curadv != reqadv)
+                       return 0;
+
+               if (tg3_flag(tp, PAUSE_AUTONEG))
+                       tg3_readphy(tp, MII_LPA, rmtadv);
+       } else {
+               /* Reprogram the advertisement register, even if it
+                * does not affect the current link.  If the link
+                * gets renegotiated in the future, we can save an
+                * additional renegotiation cycle by advertising
+                * it correctly in the first place.
+                */
+               if (curadv != reqadv) {
+                       *lcladv &= ~(ADVERTISE_PAUSE_CAP |
+                                    ADVERTISE_PAUSE_ASYM);
+                       tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
+               }
+       }
+
+       return 1;
+}
+
+static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
+{
+       int current_link_up;
+       u32 bmsr, val;
+       u32 lcl_adv, rmt_adv;
+       u16 current_speed;
+       u8 current_duplex;
+       int i, err;
+
+       tw32(MAC_EVENT, 0);
+
+       tw32_f(MAC_STATUS,
+            (MAC_STATUS_SYNC_CHANGED |
+             MAC_STATUS_CFG_CHANGED |
+             MAC_STATUS_MI_COMPLETION |
+             MAC_STATUS_LNKSTATE_CHANGED));
+       udelay(40);
+
+       if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
+               tw32_f(MAC_MI_MODE,
+                    (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
+               udelay(80);
+       }
+
+       tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
+
+       /* Some third-party PHYs need to be reset on link going
+        * down.
+        */
+       if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
+            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
+            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
+           netif_carrier_ok(tp->dev)) {
+               tg3_readphy(tp, MII_BMSR, &bmsr);
+               if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
+                   !(bmsr & BMSR_LSTATUS))
+                       force_reset = 1;
+       }
+       if (force_reset)
+               tg3_phy_reset(tp);
+
+       if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
+               tg3_readphy(tp, MII_BMSR, &bmsr);
+               if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
+                   !tg3_flag(tp, INIT_COMPLETE))
+                       bmsr = 0;
+
+               if (!(bmsr & BMSR_LSTATUS)) {
+                       err = tg3_init_5401phy_dsp(tp);
+                       if (err)
+                               return err;
+
+                       tg3_readphy(tp, MII_BMSR, &bmsr);
+                       for (i = 0; i < 1000; i++) {
+                               udelay(10);
+                               if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
+                                   (bmsr & BMSR_LSTATUS)) {
+                                       udelay(40);
+                                       break;
+                               }
+                       }
+
+                       if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
+                           TG3_PHY_REV_BCM5401_B0 &&
+                           !(bmsr & BMSR_LSTATUS) &&
+                           tp->link_config.active_speed == SPEED_1000) {
+                               err = tg3_phy_reset(tp);
+                               if (!err)
+                                       err = tg3_init_5401phy_dsp(tp);
+                               if (err)
+                                       return err;
+                       }
+               }
+       } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
+                  tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
+               /* 5701 {A0,B0} CRC bug workaround */
+               tg3_writephy(tp, 0x15, 0x0a75);
+               tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
+               tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
+               tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
+       }
+
+       /* Clear pending interrupts... */
+       tg3_readphy(tp, MII_TG3_ISTAT, &val);
+       tg3_readphy(tp, MII_TG3_ISTAT, &val);
+
+       if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
+               tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
+       else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
+               tg3_writephy(tp, MII_TG3_IMASK, ~0);
+
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
+           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
+               if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
+                       tg3_writephy(tp, MII_TG3_EXT_CTRL,
+                                    MII_TG3_EXT_CTRL_LNK3_LED_MODE);
+               else
+                       tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
+       }
+
+       current_link_up = 0;
+       current_speed = SPEED_INVALID;
+       current_duplex = DUPLEX_INVALID;
+
+       if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
+               err = tg3_phy_auxctl_read(tp,
+                                         MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
+                                         &val);
+               if (!err && !(val & (1 << 10))) {
+                       tg3_phy_auxctl_write(tp,
+                                            MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
+                                            val | (1 << 10));
+                       goto relink;
+               }
+       }
+
+       bmsr = 0;
+       for (i = 0; i < 100; i++) {
+               tg3_readphy(tp, MII_BMSR, &bmsr);
+               if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
+                   (bmsr & BMSR_LSTATUS))
+                       break;
+               udelay(40);
+       }
+
+       if (bmsr & BMSR_LSTATUS) {
+               u32 aux_stat, bmcr;
+
+               tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
+               for (i = 0; i < 2000; i++) {
+                       udelay(10);
+                       if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
+                           aux_stat)
+                               break;
+               }
+
+               tg3_aux_stat_to_speed_duplex(tp, aux_stat,
+                                            &current_speed,
+                                            &current_duplex);
+
+               bmcr = 0;
+               for (i = 0; i < 200; i++) {
+                       tg3_readphy(tp, MII_BMCR, &bmcr);
+                       if (tg3_readphy(tp, MII_BMCR, &bmcr))
+                               continue;
+                       if (bmcr && bmcr != 0x7fff)
+                               break;
+                       udelay(10);
+               }
+
+               lcl_adv = 0;
+               rmt_adv = 0;
+
+               tp->link_config.active_speed = current_speed;
+               tp->link_config.active_duplex = current_duplex;
+
+               if (tp->link_config.autoneg == AUTONEG_ENABLE) {
+                       if ((bmcr & BMCR_ANENABLE) &&
+                           tg3_copper_is_advertising_all(tp,
+                                               tp->link_config.advertising)) {
+                               if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
+                                                                 &rmt_adv))
+                                       current_link_up = 1;
+                       }
+               } else {
+                       if (!(bmcr & BMCR_ANENABLE) &&
+                           tp->link_config.speed == current_speed &&
+                           tp->link_config.duplex == current_duplex &&
+                           tp->link_config.flowctrl ==
+                           tp->link_config.active_flowctrl) {
+                               current_link_up = 1;
+                       }
+               }
+
+               if (current_link_up == 1 &&
+                   tp->link_config.active_duplex == DUPLEX_FULL)
+                       tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
+       }
+
+relink:
+       if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
+               tg3_phy_copper_begin(tp);
+
+               tg3_readphy(tp, MII_BMSR, &bmsr);
+               if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
+                   (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
+                       current_link_up = 1;
+       }
+
+       tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
+       if (current_link_up == 1) {
+               if (tp->link_config.active_speed == SPEED_100 ||
+                   tp->link_config.active_speed == SPEED_10)
+                       tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
+               else
+                       tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
+       } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
+               tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
+       else
+               tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
+
+       tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
+       if (tp->link_config.active_duplex == DUPLEX_HALF)
+               tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
+
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
+               if (current_link_up == 1 &&
+                   tg3_5700_link_polarity(tp, tp->link_config.active_speed))
+                       tp->mac_mode |= MAC_MODE_LINK_POLARITY;
+               else
+                       tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
+       }
+
+       /* ??? Without this setting Netgear GA302T PHY does not
+        * ??? send/receive packets...
+        */
+       if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
+           tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
+               tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
+               tw32_f(MAC_MI_MODE, tp->mi_mode);
+               udelay(80);
+       }
+
+       tw32_f(MAC_MODE, tp->mac_mode);
+       udelay(40);
+
+       tg3_phy_eee_adjust(tp, current_link_up);
+
+       if (tg3_flag(tp, USE_LINKCHG_REG)) {
+               /* Polled via timer. */
+               tw32_f(MAC_EVENT, 0);
+       } else {
+               tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
+       }
+       udelay(40);
+
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
+           current_link_up == 1 &&
+           tp->link_config.active_speed == SPEED_1000 &&
+           (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
+               udelay(120);
+               tw32_f(MAC_STATUS,
+                    (MAC_STATUS_SYNC_CHANGED |
+                     MAC_STATUS_CFG_CHANGED));
+               udelay(40);
+               tg3_write_mem(tp,
+                             NIC_SRAM_FIRMWARE_MBOX,
+                             NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
+       }
+
+       /* Prevent send BD corruption. */
+       if (tg3_flag(tp, CLKREQ_BUG)) {
+               u16 oldlnkctl, newlnkctl;
+
+               pci_read_config_word(tp->pdev,
+                                    tp->pcie_cap + PCI_EXP_LNKCTL,
+                                    &oldlnkctl);
+               if (tp->link_config.active_speed == SPEED_100 ||
+                   tp->link_config.active_speed == SPEED_10)
+                       newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
+               else
+                       newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
+               if (newlnkctl != oldlnkctl)
+                       pci_write_config_word(tp->pdev,
+                                             tp->pcie_cap + PCI_EXP_LNKCTL,
+                                             newlnkctl);
+       }
+
+       if (current_link_up != netif_carrier_ok(tp->dev)) {
+               if (current_link_up)
+                       netif_carrier_on(tp->dev);
+               else
+                       netif_carrier_off(tp->dev);
+               tg3_link_report(tp);
+       }
+
+       return 0;
+}
+
+struct tg3_fiber_aneginfo {
+       int state;
+#define ANEG_STATE_UNKNOWN             0
+#define ANEG_STATE_AN_ENABLE           1
+#define ANEG_STATE_RESTART_INIT                2
+#define ANEG_STATE_RESTART             3
+#define ANEG_STATE_DISABLE_LINK_OK     4
+#define ANEG_STATE_ABILITY_DETECT_INIT 5
+#define ANEG_STATE_ABILITY_DETECT      6
+#define ANEG_STATE_ACK_DETECT_INIT     7
+#define ANEG_STATE_ACK_DETECT          8
+#define ANEG_STATE_COMPLETE_ACK_INIT   9
+#define ANEG_STATE_COMPLETE_ACK                10
+#define ANEG_STATE_IDLE_DETECT_INIT    11
+#define ANEG_STATE_IDLE_DETECT         12
+#define ANEG_STATE_LINK_OK             13
+#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
+#define ANEG_STATE_NEXT_PAGE_WAIT      15
+
+       u32 flags;
+#define MR_AN_ENABLE           0x00000001
+#define MR_RESTART_AN          0x00000002
+#define MR_AN_COMPLETE         0x00000004
+#define MR_PAGE_RX             0x00000008
+#define MR_NP_LOADED           0x00000010
+#define MR_TOGGLE_TX           0x00000020
+#define MR_LP_ADV_FULL_DUPLEX  0x00000040
+#define MR_LP_ADV_HALF_DUPLEX  0x00000080
+#define MR_LP_ADV_SYM_PAUSE    0x00000100
+#define MR_LP_ADV_ASYM_PAUSE   0x00000200
+#define MR_LP_ADV_REMOTE_FAULT1        0x00000400
+#define MR_LP_ADV_REMOTE_FAULT2        0x00000800
+#define MR_LP_ADV_NEXT_PAGE    0x00001000
+#define MR_TOGGLE_RX           0x00002000
+#define MR_NP_RX               0x00004000
+
+#define MR_LINK_OK             0x80000000
+
+       unsigned long link_time, cur_time;
+
+       u32 ability_match_cfg;
+       int ability_match_count;
+
+       char ability_match, idle_match, ack_match;
+
+       u32 txconfig, rxconfig;
+#define ANEG_CFG_NP            0x00000080
+#define ANEG_CFG_ACK           0x00000040
+#define ANEG_CFG_RF2           0x00000020
+#define ANEG_CFG_RF1           0x00000010
+#define ANEG_CFG_PS2           0x00000001
+#define ANEG_CFG_PS1           0x00008000
+#define ANEG_CFG_HD            0x00004000
+#define ANEG_CFG_FD            0x00002000
+#define ANEG_CFG_INVAL         0x00001f06
+
+};
+#define ANEG_OK                0
+#define ANEG_DONE      1
+#define ANEG_TIMER_ENAB        2
+#define ANEG_FAILED    -1
+
+#define ANEG_STATE_SETTLE_TIME 10000
+
+static int tg3_fiber_aneg_smachine(struct tg3 *tp,
+                                  struct tg3_fiber_aneginfo *ap)
+{
+       u16 flowctrl;
+       unsigned long delta;
+       u32 rx_cfg_reg;
+       int ret;
+
+       if (ap->state == ANEG_STATE_UNKNOWN) {
+               ap->rxconfig = 0;
+               ap->link_time = 0;
+               ap->cur_time = 0;
+               ap->ability_match_cfg = 0;
+               ap->ability_match_count = 0;
+               ap->ability_match = 0;
+               ap->idle_match = 0;
+               ap->ack_match = 0;
+       }
+       ap->cur_time++;
+
+       if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
+               rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
+
+               if (rx_cfg_reg != ap->ability_match_cfg) {
+                       ap->ability_match_cfg = rx_cfg_reg;
+                       ap->ability_match = 0;
+                       ap->ability_match_count = 0;
+               } else {
+                       if (++ap->ability_match_count > 1) {
+                               ap->ability_match = 1;
+                               ap->ability_match_cfg = rx_cfg_reg;
+                       }
+               }
+               if (rx_cfg_reg & ANEG_CFG_ACK)
+                       ap->ack_match = 1;
+               else
+                       ap->ack_match = 0;
+
+               ap->idle_match = 0;
+       } else {
+               ap->idle_match = 1;
+               ap->ability_match_cfg = 0;
+               ap->ability_match_count = 0;
+               ap->ability_match = 0;
+               ap->ack_match = 0;
+
+               rx_cfg_reg = 0;
+       }
+
+       ap->rxconfig = rx_cfg_reg;
+       ret = ANEG_OK;
+
+       switch (ap->state) {
+       case ANEG_STATE_UNKNOWN:
+               if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
+                       ap->state = ANEG_STATE_AN_ENABLE;
+
+               /* fallthru */
+       case ANEG_STATE_AN_ENABLE:
+               ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
+               if (ap->flags & MR_AN_ENABLE) {
+                       ap->link_time = 0;
+                       ap->cur_time = 0;
+                       ap->ability_match_cfg = 0;
+                       ap->ability_match_count = 0;
+                       ap->ability_match = 0;
+                       ap->idle_match = 0;
+                       ap->ack_match = 0;
+
+                       ap->state = ANEG_STATE_RESTART_INIT;
+               } else {
+                       ap->state = ANEG_STATE_DISABLE_LINK_OK;
+               }
+               break;
+
+       case ANEG_STATE_RESTART_INIT:
+               ap->link_time = ap->cur_time;
+               ap->flags &= ~(MR_NP_LOADED);
+               ap->txconfig = 0;
+               tw32(MAC_TX_AUTO_NEG, 0);
+               tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
+               tw32_f(MAC_MODE, tp->mac_mode);
+               udelay(40);
+
+               ret = ANEG_TIMER_ENAB;
+               ap->state = ANEG_STATE_RESTART;
+
+               /* fallthru */
+       case ANEG_STATE_RESTART:
+               delta = ap->cur_time - ap->link_time;
+               if (delta > ANEG_STATE_SETTLE_TIME)
+                       ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
+               else
+                       ret = ANEG_TIMER_ENAB;
+               break;
+
+       case ANEG_STATE_DISABLE_LINK_OK:
+               ret = ANEG_DONE;
+               break;
+
+       case ANEG_STATE_ABILITY_DETECT_INIT:
+               ap->flags &= ~(MR_TOGGLE_TX);
+               ap->txconfig = ANEG_CFG_FD;
+               flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
+               if (flowctrl & ADVERTISE_1000XPAUSE)
+                       ap->txconfig |= ANEG_CFG_PS1;
+               if (flowctrl & ADVERTISE_1000XPSE_ASYM)
+                       ap->txconfig |= ANEG_CFG_PS2;
+               tw32(MAC_TX_AUTO_NEG, ap->txconfig);
+               tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
+               tw32_f(MAC_MODE, tp->mac_mode);
+               udelay(40);
+
+               ap->state = ANEG_STATE_ABILITY_DETECT;
+               break;
+
+       case ANEG_STATE_ABILITY_DETECT:
+               if (ap->ability_match != 0 && ap->rxconfig != 0)
+                       ap->state = ANEG_STATE_ACK_DETECT_INIT;
+               break;
+
+       case ANEG_STATE_ACK_DETECT_INIT:
+               ap->txconfig |= ANEG_CFG_ACK;
+               tw32(MAC_TX_AUTO_NEG, ap->txconfig);
+               tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
+               tw32_f(MAC_MODE, tp->mac_mode);
+               udelay(40);
+
+               ap->state = ANEG_STATE_ACK_DETECT;
+
+               /* fallthru */
+       case ANEG_STATE_ACK_DETECT:
+               if (ap->ack_match != 0) {
+                       if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
+                           (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
+                               ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
+                       } else {
+                               ap->state = ANEG_STATE_AN_ENABLE;
+                       }
+               } else if (ap->ability_match != 0 &&
+                          ap->rxconfig == 0) {
+                       ap->state = ANEG_STATE_AN_ENABLE;
+               }
+               break;
+
+       case ANEG_STATE_COMPLETE_ACK_INIT:
+               if (ap->rxconfig & ANEG_CFG_INVAL) {
+                       ret = ANEG_FAILED;
+                       break;
+               }
+               ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
+                              MR_LP_ADV_HALF_DUPLEX |
+                              MR_LP_ADV_SYM_PAUSE |
+                              MR_LP_ADV_ASYM_PAUSE |
+                              MR_LP_ADV_REMOTE_FAULT1 |
+                              MR_LP_ADV_REMOTE_FAULT2 |
+                              MR_LP_ADV_NEXT_PAGE |
+                              MR_TOGGLE_RX |
+                              MR_NP_RX);
+               if (ap->rxconfig & ANEG_CFG_FD)
+                       ap->flags |= MR_LP_ADV_FULL_DUPLEX;
+               if (ap->rxconfig & ANEG_CFG_HD)
+                       ap->flags |= MR_LP_ADV_HALF_DUPLEX;
+               if (ap->rxconfig & ANEG_CFG_PS1)
+                       ap->flags |= MR_LP_ADV_SYM_PAUSE;
+               if (ap->rxconfig & ANEG_CFG_PS2)
+                       ap->flags |= MR_LP_ADV_ASYM_PAUSE;
+               if (ap->rxconfig & ANEG_CFG_RF1)
+                       ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
+               if (ap->rxconfig & ANEG_CFG_RF2)
+                       ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
+               if (ap->rxconfig & ANEG_CFG_NP)
+                       ap->flags |= MR_LP_ADV_NEXT_PAGE;
+
+               ap->link_time = ap->cur_time;
+
+               ap->flags ^= (MR_TOGGLE_TX);
+               if (ap->rxconfig & 0x0008)
+                       ap->flags |= MR_TOGGLE_RX;
+               if (ap->rxconfig & ANEG_CFG_NP)
+                       ap->flags |= MR_NP_RX;
+               ap->flags |= MR_PAGE_RX;
+
+               ap->state = ANEG_STATE_COMPLETE_ACK;
+               ret = ANEG_TIMER_ENAB;
+               break;
+
+       case ANEG_STATE_COMPLETE_ACK:
+               if (ap->ability_match != 0 &&
+                   ap->rxconfig == 0) {
+                       ap->state = ANEG_STATE_AN_ENABLE;
+                       break;
+               }
+               delta = ap->cur_time - ap->link_time;
+               if (delta > ANEG_STATE_SETTLE_TIME) {
+                       if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
+                               ap->state = ANEG_STATE_IDLE_DETECT_INIT;
+                       } else {
+                               if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
+                                   !(ap->flags & MR_NP_RX)) {
+                                       ap->state = ANEG_STATE_IDLE_DETECT_INIT;
+                               } else {
+                                       ret = ANEG_FAILED;
+                               }
+                       }
+               }
+               break;
+
+       case ANEG_STATE_IDLE_DETECT_INIT:
+               ap->link_time = ap->cur_time;
+               tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
+               tw32_f(MAC_MODE, tp->mac_mode);
+               udelay(40);
+
+               ap->state = ANEG_STATE_IDLE_DETECT;
+               ret = ANEG_TIMER_ENAB;
+               break;
+
+       case ANEG_STATE_IDLE_DETECT:
+               if (ap->ability_match != 0 &&
+                   ap->rxconfig == 0) {
+                       ap->state = ANEG_STATE_AN_ENABLE;
+                       break;
+               }
+               delta = ap->cur_time - ap->link_time;
+               if (delta > ANEG_STATE_SETTLE_TIME) {
+                       /* XXX another gem from the Broadcom driver :( */
+                       ap->state = ANEG_STATE_LINK_OK;
+               }
+               break;
+
+       case ANEG_STATE_LINK_OK:
+               ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
+               ret = ANEG_DONE;
+               break;
+
+       case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
+               /* ??? unimplemented */
+               break;
+
+       case ANEG_STATE_NEXT_PAGE_WAIT:
+               /* ??? unimplemented */
+               break;
+
+       default:
+               ret = ANEG_FAILED;
+               break;
+       }
+
+       return ret;
+}
+
+static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
+{
+       int res = 0;
+       struct tg3_fiber_aneginfo aninfo;
+       int status = ANEG_FAILED;
+       unsigned int tick;
+       u32 tmp;
+
+       tw32_f(MAC_TX_AUTO_NEG, 0);
+
+       tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
+       tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
+       udelay(40);
+
+       tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
+       udelay(40);
+
+       memset(&aninfo, 0, sizeof(aninfo));
+       aninfo.flags |= MR_AN_ENABLE;
+       aninfo.state = ANEG_STATE_UNKNOWN;
+       aninfo.cur_time = 0;
+       tick = 0;
+       while (++tick < 195000) {
+               status = tg3_fiber_aneg_smachine(tp, &aninfo);
+               if (status == ANEG_DONE || status == ANEG_FAILED)
+                       break;
+
+               udelay(1);
+       }
+
+       tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
+       tw32_f(MAC_MODE, tp->mac_mode);
+       udelay(40);
+
+       *txflags = aninfo.txconfig;
+       *rxflags = aninfo.flags;
+
+       if (status == ANEG_DONE &&
+           (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
+                            MR_LP_ADV_FULL_DUPLEX)))
+               res = 1;
+
+       return res;
+}
+
+static void tg3_init_bcm8002(struct tg3 *tp)
+{
+       u32 mac_status = tr32(MAC_STATUS);
+       int i;
+
+       /* Reset when initting first time or we have a link. */
+       if (tg3_flag(tp, INIT_COMPLETE) &&
+           !(mac_status & MAC_STATUS_PCS_SYNCED))
+               return;
+
+       /* Set PLL lock range. */
+       tg3_writephy(tp, 0x16, 0x8007);
+
+       /* SW reset */
+       tg3_writephy(tp, MII_BMCR, BMCR_RESET);
+
+       /* Wait for reset to complete. */
+       /* XXX schedule_timeout() ... */
+       for (i = 0; i < 500; i++)
+               udelay(10);
+
+       /* Config mode; select PMA/Ch 1 regs. */
+       tg3_writephy(tp, 0x10, 0x8411);
+
+       /* Enable auto-lock and comdet, select txclk for tx. */
+       tg3_writephy(tp, 0x11, 0x0a10);
+
+       tg3_writephy(tp, 0x18, 0x00a0);
+       tg3_writephy(tp, 0x16, 0x41ff);
+
+       /* Assert and deassert POR. */
+       tg3_writephy(tp, 0x13, 0x0400);
+       udelay(40);
+       tg3_writephy(tp, 0x13, 0x0000);
+
+       tg3_writephy(tp, 0x11, 0x0a50);
+       udelay(40);
+       tg3_writephy(tp, 0x11, 0x0a10);
+
+       /* Wait for signal to stabilize */
+       /* XXX schedule_timeout() ... */
+       for (i = 0; i < 15000; i++)
+               udelay(10);
+
+       /* Deselect the channel register so we can read the PHYID
+        * later.
+        */
+       tg3_writephy(tp, 0x10, 0x8011);
+}
+
+static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
+{
+       u16 flowctrl;
+       u32 sg_dig_ctrl, sg_dig_status;
+       u32 serdes_cfg, expected_sg_dig_ctrl;
+       int workaround, port_a;
+       int current_link_up;
+
+       serdes_cfg = 0;
+       expected_sg_dig_ctrl = 0;
+       workaround = 0;
+       port_a = 1;
+       current_link_up = 0;
+
+       if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
+           tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
+               workaround = 1;
+               if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
+                       port_a = 0;
+
+               /* preserve bits 0-11,13,14 for signal pre-emphasis */
+               /* preserve bits 20-23 for voltage regulator */
+               serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
+       }
+
+       sg_dig_ctrl = tr32(SG_DIG_CTRL);
+
+       if (tp->link_config.autoneg != AUTONEG_ENABLE) {
+               if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
+                       if (workaround) {
+                               u32 val = serdes_cfg;
+
+                               if (port_a)
+                                       val |= 0xc010000;
+                               else
+                                       val |= 0x4010000;
+                               tw32_f(MAC_SERDES_CFG, val);
+                       }
+
+                       tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
+               }
+               if (mac_status & MAC_STATUS_PCS_SYNCED) {
+                       tg3_setup_flow_control(tp, 0, 0);
+                       current_link_up = 1;
+               }
+               goto out;
+       }
+
+       /* Want auto-negotiation.  */
+       expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
+
+       flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
+       if (flowctrl & ADVERTISE_1000XPAUSE)
+               expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
+       if (flowctrl & ADVERTISE_1000XPSE_ASYM)
+               expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
+
+       if (sg_dig_ctrl != expected_sg_dig_ctrl) {
+               if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
+                   tp->serdes_counter &&
+                   ((mac_status & (MAC_STATUS_PCS_SYNCED |
+                                   MAC_STATUS_RCVD_CFG)) ==
+                    MAC_STATUS_PCS_SYNCED)) {
+                       tp->serdes_counter--;
+                       current_link_up = 1;
+                       goto out;
+               }
+restart_autoneg:
+               if (workaround)
+                       tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
+               tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
+               udelay(5);
+               tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
+
+               tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
+               tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
+       } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
+                                MAC_STATUS_SIGNAL_DET)) {
+               sg_dig_status = tr32(SG_DIG_STATUS);
+               mac_status = tr32(MAC_STATUS);
+
+               if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
+                   (mac_status & MAC_STATUS_PCS_SYNCED)) {
+                       u32 local_adv = 0, remote_adv = 0;
+
+                       if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
+                               local_adv |= ADVERTISE_1000XPAUSE;
+                       if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
+                               local_adv |= ADVERTISE_1000XPSE_ASYM;
+
+                       if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
+                               remote_adv |= LPA_1000XPAUSE;
+                       if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
+                               remote_adv |= LPA_1000XPAUSE_ASYM;
+
+                       tg3_setup_flow_control(tp, local_adv, remote_adv);
+                       current_link_up = 1;
+                       tp->serdes_counter = 0;
+                       tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
+               } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
+                       if (tp->serdes_counter)
+                               tp->serdes_counter--;
+                       else {
+                               if (workaround) {
+                                       u32 val = serdes_cfg;
+
+                                       if (port_a)
+                                               val |= 0xc010000;
+                                       else
+                                               val |= 0x4010000;
+
+                                       tw32_f(MAC_SERDES_CFG, val);
+                               }
+
+                               tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
+                               udelay(40);
+
+                               /* Link parallel detection - link is up */
+                               /* only if we have PCS_SYNC and not */
+                               /* receiving config code words */
+                               mac_status = tr32(MAC_STATUS);
+                               if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
+                                   !(mac_status & MAC_STATUS_RCVD_CFG)) {
+                                       tg3_setup_flow_control(tp, 0, 0);
+                                       current_link_up = 1;
+                                       tp->phy_flags |=
+                                               TG3_PHYFLG_PARALLEL_DETECT;
+                                       tp->serdes_counter =
+                                               SERDES_PARALLEL_DET_TIMEOUT;
+                               } else
+                                       goto restart_autoneg;
+                       }
+               }
+       } else {
+               tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
+               tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
+       }
+
+out:
+       return current_link_up;
+}
+
+static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
+{
+       int current_link_up = 0;
+
+       if (!(mac_status & MAC_STATUS_PCS_SYNCED))
+               goto out;
+
+       if (tp->link_config.autoneg == AUTONEG_ENABLE) {
+               u32 txflags, rxflags;
+               int i;
+
+               if (fiber_autoneg(tp, &txflags, &rxflags)) {
+                       u32 local_adv = 0, remote_adv = 0;
+
+                       if (txflags & ANEG_CFG_PS1)
+                               local_adv |= ADVERTISE_1000XPAUSE;
+                       if (txflags & ANEG_CFG_PS2)
+                               local_adv |= ADVERTISE_1000XPSE_ASYM;
+
+                       if (rxflags & MR_LP_ADV_SYM_PAUSE)
+                               remote_adv |= LPA_1000XPAUSE;
+                       if (rxflags & MR_LP_ADV_ASYM_PAUSE)
+                               remote_adv |= LPA_1000XPAUSE_ASYM;
+
+                       tg3_setup_flow_control(tp, local_adv, remote_adv);
+
+                       current_link_up = 1;
+               }
+               for (i = 0; i < 30; i++) {
+                       udelay(20);
+                       tw32_f(MAC_STATUS,
+                              (MAC_STATUS_SYNC_CHANGED |
+                               MAC_STATUS_CFG_CHANGED));
+                       udelay(40);
+                       if ((tr32(MAC_STATUS) &
+                            (MAC_STATUS_SYNC_CHANGED |
+                             MAC_STATUS_CFG_CHANGED)) == 0)
+                               break;
+               }
+
+               mac_status = tr32(MAC_STATUS);
+               if (current_link_up == 0 &&
+                   (mac_status & MAC_STATUS_PCS_SYNCED) &&
+                   !(mac_status & MAC_STATUS_RCVD_CFG))
+                       current_link_up = 1;
+       } else {
+               tg3_setup_flow_control(tp, 0, 0);
+
+               /* Forcing 1000FD link up. */
+               current_link_up = 1;
+
+               tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
+               udelay(40);
+
+               tw32_f(MAC_MODE, tp->mac_mode);
+               udelay(40);
+       }
+
+out:
+       return current_link_up;
+}
+
+static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
+{
+       u32 orig_pause_cfg;
+       u16 orig_active_speed;
+       u8 orig_active_duplex;
+       u32 mac_status;
+       int current_link_up;
+       int i;
+
+       orig_pause_cfg = tp->link_config.active_flowctrl;
+       orig_active_speed = tp->link_config.active_speed;
+       orig_active_duplex = tp->link_config.active_duplex;
+
+       if (!tg3_flag(tp, HW_AUTONEG) &&
+           netif_carrier_ok(tp->dev) &&
+           tg3_flag(tp, INIT_COMPLETE)) {
+               mac_status = tr32(MAC_STATUS);
+               mac_status &= (MAC_STATUS_PCS_SYNCED |
+                              MAC_STATUS_SIGNAL_DET |
+                              MAC_STATUS_CFG_CHANGED |
+                              MAC_STATUS_RCVD_CFG);
+               if (mac_status == (MAC_STATUS_PCS_SYNCED |
+                                  MAC_STATUS_SIGNAL_DET)) {
+                       tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
+                                           MAC_STATUS_CFG_CHANGED));
+                       return 0;
+               }
+       }
+
+       tw32_f(MAC_TX_AUTO_NEG, 0);
+
+       tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
+       tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
+       tw32_f(MAC_MODE, tp->mac_mode);
+       udelay(40);
+
+       if (tp->phy_id == TG3_PHY_ID_BCM8002)
+               tg3_init_bcm8002(tp);
+
+       /* Enable link change event even when serdes polling.  */
+       tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
+       udelay(40);
+
+       current_link_up = 0;
+       mac_status = tr32(MAC_STATUS);
+
+       if (tg3_flag(tp, HW_AUTONEG))
+               current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
+       else
+               current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
+
+       tp->napi[0].hw_status->status =
+               (SD_STATUS_UPDATED |
+                (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
+
+       for (i = 0; i < 100; i++) {
+               tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
+                                   MAC_STATUS_CFG_CHANGED));
+               udelay(5);
+               if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
+                                        MAC_STATUS_CFG_CHANGED |
+                                        MAC_STATUS_LNKSTATE_CHANGED)) == 0)
+                       break;
+       }
+
+       mac_status = tr32(MAC_STATUS);
+       if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
+               current_link_up = 0;
+               if (tp->link_config.autoneg == AUTONEG_ENABLE &&
+                   tp->serdes_counter == 0) {
+                       tw32_f(MAC_MODE, (tp->mac_mode |
+                                         MAC_MODE_SEND_CONFIGS));
+                       udelay(1);
+                       tw32_f(MAC_MODE, tp->mac_mode);
+               }
+       }
+
+       if (current_link_up == 1) {
+               tp->link_config.active_speed = SPEED_1000;
+               tp->link_config.active_duplex = DUPLEX_FULL;
+               tw32(MAC_LED_CTRL, (tp->led_ctrl |
+                                   LED_CTRL_LNKLED_OVERRIDE |
+                                   LED_CTRL_1000MBPS_ON));
+       } else {
+               tp->link_config.active_speed = SPEED_INVALID;
+               tp->link_config.active_duplex = DUPLEX_INVALID;
+               tw32(MAC_LED_CTRL, (tp->led_ctrl |
+                                   LED_CTRL_LNKLED_OVERRIDE |
+                                   LED_CTRL_TRAFFIC_OVERRIDE));
+       }
+
+       if (current_link_up != netif_carrier_ok(tp->dev)) {
+               if (current_link_up)
+                       netif_carrier_on(tp->dev);
+               else
+                       netif_carrier_off(tp->dev);
+               tg3_link_report(tp);
+       } else {
+               u32 now_pause_cfg = tp->link_config.active_flowctrl;
+               if (orig_pause_cfg != now_pause_cfg ||
+                   orig_active_speed != tp->link_config.active_speed ||
+                   orig_active_duplex != tp->link_config.active_duplex)
+                       tg3_link_report(tp);
+       }
+
+       return 0;
+}
+
+static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
+{
+       int current_link_up, err = 0;
+       u32 bmsr, bmcr;
+       u16 current_speed;
+       u8 current_duplex;
+       u32 local_adv, remote_adv;
+
+       tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
+       tw32_f(MAC_MODE, tp->mac_mode);
+       udelay(40);
+
+       tw32(MAC_EVENT, 0);
+
+       tw32_f(MAC_STATUS,
+            (MAC_STATUS_SYNC_CHANGED |
+             MAC_STATUS_CFG_CHANGED |
+             MAC_STATUS_MI_COMPLETION |
+             MAC_STATUS_LNKSTATE_CHANGED));
+       udelay(40);
+
+       if (force_reset)
+               tg3_phy_reset(tp);
+
+       current_link_up = 0;
+       current_speed = SPEED_INVALID;
+       current_duplex = DUPLEX_INVALID;
+
+       err |= tg3_readphy(tp, MII_BMSR, &bmsr);
+       err |= tg3_readphy(tp, MII_BMSR, &bmsr);
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
+               if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
+                       bmsr |= BMSR_LSTATUS;
+               else
+                       bmsr &= ~BMSR_LSTATUS;
+       }
+
+       err |= tg3_readphy(tp, MII_BMCR, &bmcr);
+
+       if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
+           (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
+               /* do nothing, just check for link up at the end */
+       } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
+               u32 adv, new_adv;
+
+               err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
+               new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
+                                 ADVERTISE_1000XPAUSE |
+                                 ADVERTISE_1000XPSE_ASYM |
+                                 ADVERTISE_SLCT);
+
+               new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
+
+               if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
+                       new_adv |= ADVERTISE_1000XHALF;
+               if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
+                       new_adv |= ADVERTISE_1000XFULL;
+
+               if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
+                       tg3_writephy(tp, MII_ADVERTISE, new_adv);
+                       bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
+                       tg3_writephy(tp, MII_BMCR, bmcr);
+
+                       tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
+                       tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
+                       tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
+
+                       return err;
+               }
+       } else {
+               u32 new_bmcr;
+
+               bmcr &= ~BMCR_SPEED1000;
+               new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
+
+               if (tp->link_config.duplex == DUPLEX_FULL)
+                       new_bmcr |= BMCR_FULLDPLX;
+
+               if (new_bmcr != bmcr) {
+                       /* BMCR_SPEED1000 is a reserved bit that needs
+                        * to be set on write.
+                        */
+                       new_bmcr |= BMCR_SPEED1000;
+
+                       /* Force a linkdown */
+                       if (netif_carrier_ok(tp->dev)) {
+                               u32 adv;
+
+                               err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
+                               adv &= ~(ADVERTISE_1000XFULL |
+                                        ADVERTISE_1000XHALF |
+                                        ADVERTISE_SLCT);
+                               tg3_writephy(tp, MII_ADVERTISE, adv);
+                               tg3_writephy(tp, MII_BMCR, bmcr |
+                                                          BMCR_ANRESTART |
+                                                          BMCR_ANENABLE);
+                               udelay(10);
+                               netif_carrier_off(tp->dev);
+                       }
+                       tg3_writephy(tp, MII_BMCR, new_bmcr);
+                       bmcr = new_bmcr;
+                       err |= tg3_readphy(tp, MII_BMSR, &bmsr);
+                       err |= tg3_readphy(tp, MII_BMSR, &bmsr);
+                       if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
+                           ASIC_REV_5714) {
+                               if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
+                                       bmsr |= BMSR_LSTATUS;
+                               else
+                                       bmsr &= ~BMSR_LSTATUS;
+                       }
+                       tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
+               }
+       }
+
+       if (bmsr & BMSR_LSTATUS) {
+               current_speed = SPEED_1000;
+               current_link_up = 1;
+               if (bmcr & BMCR_FULLDPLX)
+                       current_duplex = DUPLEX_FULL;
+               else
+                       current_duplex = DUPLEX_HALF;
+
+               local_adv = 0;
+               remote_adv = 0;
+
+               if (bmcr & BMCR_ANENABLE) {
+                       u32 common;
+
+                       err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
+                       err |= tg3_readphy(tp, MII_LPA, &remote_adv);
+                       common = local_adv & remote_adv;
+                       if (common & (ADVERTISE_1000XHALF |
+                                     ADVERTISE_1000XFULL)) {
+                               if (common & ADVERTISE_1000XFULL)
+                                       current_duplex = DUPLEX_FULL;
+                               else
+                                       current_duplex = DUPLEX_HALF;
+                       } else if (!tg3_flag(tp, 5780_CLASS)) {
+                               /* Link is up via parallel detect */
+                       } else {
+                               current_link_up = 0;
+                       }
+               }
+       }
+
+       if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
+               tg3_setup_flow_control(tp, local_adv, remote_adv);
+
+       tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
+       if (tp->link_config.active_duplex == DUPLEX_HALF)
+               tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
+
+       tw32_f(MAC_MODE, tp->mac_mode);
+       udelay(40);
+
+       tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
+
+       tp->link_config.active_speed = current_speed;
+       tp->link_config.active_duplex = current_duplex;
+
+       if (current_link_up != netif_carrier_ok(tp->dev)) {
+               if (current_link_up)
+                       netif_carrier_on(tp->dev);
+               else {
+                       netif_carrier_off(tp->dev);
+                       tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
+               }
+               tg3_link_report(tp);
+       }
+       return err;
+}
+
+static void tg3_serdes_parallel_detect(struct tg3 *tp)
+{
+       if (tp->serdes_counter) {
+               /* Give autoneg time to complete. */
+               tp->serdes_counter--;
+               return;
+       }
+
+       if (!netif_carrier_ok(tp->dev) &&
+           (tp->link_config.autoneg == AUTONEG_ENABLE)) {
+               u32 bmcr;
+
+               tg3_readphy(tp, MII_BMCR, &bmcr);
+               if (bmcr & BMCR_ANENABLE) {
+                       u32 phy1, phy2;
+
+                       /* Select shadow register 0x1f */
+                       tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
+                       tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
+
+                       /* Select expansion interrupt status register */
+                       tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
+                                        MII_TG3_DSP_EXP1_INT_STAT);
+                       tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
+                       tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
+
+                       if ((phy1 & 0x10) && !(phy2 & 0x20)) {
+                               /* We have signal detect and not receiving
+                                * config code words, link is up by parallel
+                                * detection.
+                                */
+
+                               bmcr &= ~BMCR_ANENABLE;
+                               bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
+                               tg3_writephy(tp, MII_BMCR, bmcr);
+                               tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
+                       }
+               }
+       } else if (netif_carrier_ok(tp->dev) &&
+                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
+                  (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
+               u32 phy2;
+
+               /* Select expansion interrupt status register */
+               tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
+                                MII_TG3_DSP_EXP1_INT_STAT);
+               tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
+               if (phy2 & 0x20) {
+                       u32 bmcr;
+
+                       /* Config code words received, turn on autoneg. */
+                       tg3_readphy(tp, MII_BMCR, &bmcr);
+                       tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
+
+                       tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
+
+               }
+       }
+}
+
+static int tg3_setup_phy(struct tg3 *tp, int force_reset)
+{
+       u32 val;
+       int err;
+
+       if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
+               err = tg3_setup_fiber_phy(tp, force_reset);
+       else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
+               err = tg3_setup_fiber_mii_phy(tp, force_reset);
+       else
+               err = tg3_setup_copper_phy(tp, force_reset);
+
+       if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
+               u32 scale;
+
+               val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
+               if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
+                       scale = 65;
+               else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
+                       scale = 6;
+               else
+                       scale = 12;
+
+               val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
+               val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
+               tw32(GRC_MISC_CFG, val);
+       }
+
+       val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
+             (6 << TX_LENGTHS_IPG_SHIFT);
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
+               val |= tr32(MAC_TX_LENGTHS) &
+                      (TX_LENGTHS_JMB_FRM_LEN_MSK |
+                       TX_LENGTHS_CNT_DWN_VAL_MSK);
+
+       if (tp->link_config.active_speed == SPEED_1000 &&
+           tp->link_config.active_duplex == DUPLEX_HALF)
+               tw32(MAC_TX_LENGTHS, val |
+                    (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
+       else
+               tw32(MAC_TX_LENGTHS, val |
+                    (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
+
+       if (!tg3_flag(tp, 5705_PLUS)) {
+               if (netif_carrier_ok(tp->dev)) {
+                       tw32(HOSTCC_STAT_COAL_TICKS,
+                            tp->coal.stats_block_coalesce_usecs);
+               } else {
+                       tw32(HOSTCC_STAT_COAL_TICKS, 0);
+               }
+       }
+
+       if (tg3_flag(tp, ASPM_WORKAROUND)) {
+               val = tr32(PCIE_PWR_MGMT_THRESH);
+               if (!netif_carrier_ok(tp->dev))
+                       val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
+                             tp->pwrmgmt_thresh;
+               else
+                       val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
+               tw32(PCIE_PWR_MGMT_THRESH, val);
+       }
+
+       return err;
+}
+
+static inline int tg3_irq_sync(struct tg3 *tp)
+{
+       return tp->irq_sync;
+}
+
+static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
+{
+       int i;
+
+       dst = (u32 *)((u8 *)dst + off);
+       for (i = 0; i < len; i += sizeof(u32))
+               *dst++ = tr32(off + i);
+}
+
+static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
+{
+       tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
+       tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
+       tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
+       tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
+       tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
+       tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
+       tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
+       tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
+       tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
+       tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
+       tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
+       tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
+       tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
+       tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
+       tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
+       tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
+       tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
+       tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
+       tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
+
+       if (tg3_flag(tp, SUPPORT_MSIX))
+               tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
+
+       tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
+       tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
+       tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
+       tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
+       tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
+       tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
+       tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
+       tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
+
+       if (!tg3_flag(tp, 5705_PLUS)) {
+               tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
+               tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
+               tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
+       }
+
+       tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
+       tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
+       tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
+       tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
+       tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
+
+       if (tg3_flag(tp, NVRAM))
+               tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
+}
+
+static void tg3_dump_state(struct tg3 *tp)
+{
+       int i;
+       u32 *regs;
+
+       regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
+       if (!regs) {
+               netdev_err(tp->dev, "Failed allocating register dump buffer\n");
+               return;
+       }
+
+       if (tg3_flag(tp, PCI_EXPRESS)) {
+               /* Read up to but not including private PCI registers */
+               for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
+                       regs[i / sizeof(u32)] = tr32(i);
+       } else
+               tg3_dump_legacy_regs(tp, regs);
+
+       for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
+               if (!regs[i + 0] && !regs[i + 1] &&
+                   !regs[i + 2] && !regs[i + 3])
+                       continue;
+
+               netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
+                          i * 4,
+                          regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
+       }
+
+       kfree(regs);
+
+       for (i = 0; i < tp->irq_cnt; i++) {
+               struct tg3_napi *tnapi = &tp->napi[i];
+
+               /* SW status block */
+               netdev_err(tp->dev,
+                        "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
+                          i,
+                          tnapi->hw_status->status,
+                          tnapi->hw_status->status_tag,
+                          tnapi->hw_status->rx_jumbo_consumer,
+                          tnapi->hw_status->rx_consumer,
+                          tnapi->hw_status->rx_mini_consumer,
+                          tnapi->hw_status->idx[0].rx_producer,
+                          tnapi->hw_status->idx[0].tx_consumer);
+
+               netdev_err(tp->dev,
+               "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
+                          i,
+                          tnapi->last_tag, tnapi->last_irq_tag,
+                          tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
+                          tnapi->rx_rcb_ptr,
+                          tnapi->prodring.rx_std_prod_idx,
+                          tnapi->prodring.rx_std_cons_idx,
+                          tnapi->prodring.rx_jmb_prod_idx,
+                          tnapi->prodring.rx_jmb_cons_idx);
+       }
+}
+
+/* This is called whenever we suspect that the system chipset is re-
+ * ordering the sequence of MMIO to the tx send mailbox. The symptom
+ * is bogus tx completions. We try to recover by setting the
+ * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
+ * in the workqueue.
+ */
+static void tg3_tx_recover(struct tg3 *tp)
+{
+       BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
+              tp->write32_tx_mbox == tg3_write_indirect_mbox);
+
+       netdev_warn(tp->dev,
+                   "The system may be re-ordering memory-mapped I/O "
+                   "cycles to the network device, attempting to recover. "
+                   "Please report the problem to the driver maintainer "
+                   "and include system chipset information.\n");
+
+       spin_lock(&tp->lock);
+       tg3_flag_set(tp, TX_RECOVERY_PENDING);
+       spin_unlock(&tp->lock);
+}
+
+static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
+{
+       /* Tell compiler to fetch tx indices from memory. */
+       barrier();
+       return tnapi->tx_pending -
+              ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
+}
+
+/* Tigon3 never reports partial packet sends.  So we do not
+ * need special logic to handle SKBs that have not had all
+ * of their frags sent yet, like SunGEM does.
+ */
+static void tg3_tx(struct tg3_napi *tnapi)
+{
+       struct tg3 *tp = tnapi->tp;
+       u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
+       u32 sw_idx = tnapi->tx_cons;
+       struct netdev_queue *txq;
+       int index = tnapi - tp->napi;
+
+       if (tg3_flag(tp, ENABLE_TSS))
+               index--;
+
+       txq = netdev_get_tx_queue(tp->dev, index);
+
+       while (sw_idx != hw_idx) {
+               struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
+               struct sk_buff *skb = ri->skb;
+               int i, tx_bug = 0;
+
+               if (unlikely(skb == NULL)) {
+                       tg3_tx_recover(tp);
+                       return;
+               }
+
+               pci_unmap_single(tp->pdev,
+                                dma_unmap_addr(ri, mapping),
+                                skb_headlen(skb),
+                                PCI_DMA_TODEVICE);
+
+               ri->skb = NULL;
+
+               sw_idx = NEXT_TX(sw_idx);
+
+               for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
+                       ri = &tnapi->tx_buffers[sw_idx];
+                       if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
+                               tx_bug = 1;
+
+                       pci_unmap_page(tp->pdev,
+                                      dma_unmap_addr(ri, mapping),
+                                      skb_shinfo(skb)->frags[i].size,
+                                      PCI_DMA_TODEVICE);
+                       sw_idx = NEXT_TX(sw_idx);
+               }
+
+               dev_kfree_skb(skb);
+
+               if (unlikely(tx_bug)) {
+                       tg3_tx_recover(tp);
+                       return;
+               }
+       }
+
+       tnapi->tx_cons = sw_idx;
+
+       /* Need to make the tx_cons update visible to tg3_start_xmit()
+        * before checking for netif_queue_stopped().  Without the
+        * memory barrier, there is a small possibility that tg3_start_xmit()
+        * will miss it and cause the queue to be stopped forever.
+        */
+       smp_mb();
+
+       if (unlikely(netif_tx_queue_stopped(txq) &&
+                    (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
+               __netif_tx_lock(txq, smp_processor_id());
+               if (netif_tx_queue_stopped(txq) &&
+                   (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
+                       netif_tx_wake_queue(txq);
+               __netif_tx_unlock(txq);
+       }
+}
+
+static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
+{
+       if (!ri->skb)
+               return;
+
+       pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
+                        map_sz, PCI_DMA_FROMDEVICE);
+       dev_kfree_skb_any(ri->skb);
+       ri->skb = NULL;
+}
+
+/* Returns size of skb allocated or < 0 on error.
+ *
+ * We only need to fill in the address because the other members
+ * of the RX descriptor are invariant, see tg3_init_rings.
+ *
+ * Note the purposeful assymetry of cpu vs. chip accesses.  For
+ * posting buffers we only dirty the first cache line of the RX
+ * descriptor (containing the address).  Whereas for the RX status
+ * buffers the cpu only reads the last cacheline of the RX descriptor
+ * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
+ */
+static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
+                           u32 opaque_key, u32 dest_idx_unmasked)
+{
+       struct tg3_rx_buffer_desc *desc;
+       struct ring_info *map;
+       struct sk_buff *skb;
+       dma_addr_t mapping;
+       int skb_size, dest_idx;
+
+       switch (opaque_key) {
+       case RXD_OPAQUE_RING_STD:
+               dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
+               desc = &tpr->rx_std[dest_idx];
+               map = &tpr->rx_std_buffers[dest_idx];
+               skb_size = tp->rx_pkt_map_sz;
+               break;
+
+       case RXD_OPAQUE_RING_JUMBO:
+               dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
+               desc = &tpr->rx_jmb[dest_idx].std;
+               map = &tpr->rx_jmb_buffers[dest_idx];
+               skb_size = TG3_RX_JMB_MAP_SZ;
+               break;
+
+       default:
+               return -EINVAL;
+       }
+
+       /* Do not overwrite any of the map or rp information
+        * until we are sure we can commit to a new buffer.
+        *
+        * Callers depend upon this behavior and assume that
+        * we leave everything unchanged if we fail.
+        */
+       skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
+       if (skb == NULL)
+               return -ENOMEM;
+
+       skb_reserve(skb, tp->rx_offset);
+
+       mapping = pci_map_single(tp->pdev, skb->data, skb_size,
+                                PCI_DMA_FROMDEVICE);
+       if (pci_dma_mapping_error(tp->pdev, mapping)) {
+               dev_kfree_skb(skb);
+               return -EIO;
+       }
+
+       map->skb = skb;
+       dma_unmap_addr_set(map, mapping, mapping);
+
+       desc->addr_hi = ((u64)mapping >> 32);
+       desc->addr_lo = ((u64)mapping & 0xffffffff);
+
+       return skb_size;
+}
+
+/* We only need to move over in the address because the other
+ * members of the RX descriptor are invariant.  See notes above
+ * tg3_alloc_rx_skb for full details.
+ */
+static void tg3_recycle_rx(struct tg3_napi *tnapi,
+                          struct tg3_rx_prodring_set *dpr,
+                          u32 opaque_key, int src_idx,
+                          u32 dest_idx_unmasked)
+{
+       struct tg3 *tp = tnapi->tp;
+       struct tg3_rx_buffer_desc *src_desc, *dest_desc;
+       struct ring_info *src_map, *dest_map;
+       struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
+       int dest_idx;
+
+       switch (opaque_key) {
+       case RXD_OPAQUE_RING_STD:
+               dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
+               dest_desc = &dpr->rx_std[dest_idx];
+               dest_map = &dpr->rx_std_buffers[dest_idx];
+               src_desc = &spr->rx_std[src_idx];
+               src_map = &spr->rx_std_buffers[src_idx];
+               break;
+
+       case RXD_OPAQUE_RING_JUMBO:
+               dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
+               dest_desc = &dpr->rx_jmb[dest_idx].std;
+               dest_map = &dpr->rx_jmb_buffers[dest_idx];
+               src_desc = &spr->rx_jmb[src_idx].std;
+               src_map = &spr->rx_jmb_buffers[src_idx];
+               break;
+
+       default:
+               return;
+       }
+
+       dest_map->skb = src_map->skb;
+       dma_unmap_addr_set(dest_map, mapping,
+                          dma_unmap_addr(src_map, mapping));
+       dest_desc->addr_hi = src_desc->addr_hi;
+       dest_desc->addr_lo = src_desc->addr_lo;
+
+       /* Ensure that the update to the skb happens after the physical
+        * addresses have been transferred to the new BD location.
+        */
+       smp_wmb();
+
+       src_map->skb = NULL;
+}
+
+/* The RX ring scheme is composed of multiple rings which post fresh
+ * buffers to the chip, and one special ring the chip uses to report
+ * status back to the host.
+ *
+ * The special ring reports the status of received packets to the
+ * host.  The chip does not write into the original descriptor the
+ * RX buffer was obtained from.  The chip simply takes the original
+ * descriptor as provided by the host, updates the status and length
+ * field, then writes this into the next status ring entry.
+ *
+ * Each ring the host uses to post buffers to the chip is described
+ * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
+ * it is first placed into the on-chip ram.  When the packet's length
+ * is known, it walks down the TG3_BDINFO entries to select the ring.
+ * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
+ * which is within the range of the new packet's length is chosen.
+ *
+ * The "separate ring for rx status" scheme may sound queer, but it makes
+ * sense from a cache coherency perspective.  If only the host writes
+ * to the buffer post rings, and only the chip writes to the rx status
+ * rings, then cache lines never move beyond shared-modified state.
+ * If both the host and chip were to write into the same ring, cache line
+ * eviction could occur since both entities want it in an exclusive state.
+ */
+static int tg3_rx(struct tg3_napi *tnapi, int budget)
+{
+       struct tg3 *tp = tnapi->tp;
+       u32 work_mask, rx_std_posted = 0;
+       u32 std_prod_idx, jmb_prod_idx;
+       u32 sw_idx = tnapi->rx_rcb_ptr;
+       u16 hw_idx;
+       int received;
+       struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
+
+       hw_idx = *(tnapi->rx_rcb_prod_idx);
+       /*
+        * We need to order the read of hw_idx and the read of
+        * the opaque cookie.
+        */
+       rmb();
+       work_mask = 0;
+       received = 0;
+       std_prod_idx = tpr->rx_std_prod_idx;
+       jmb_prod_idx = tpr->rx_jmb_prod_idx;
+       while (sw_idx != hw_idx && budget > 0) {
+               struct ring_info *ri;
+               struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
+               unsigned int len;
+               struct sk_buff *skb;
+               dma_addr_t dma_addr;
+               u32 opaque_key, desc_idx, *post_ptr;
+
+               desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
+               opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
+               if (opaque_key == RXD_OPAQUE_RING_STD) {
+                       ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
+                       dma_addr = dma_unmap_addr(ri, mapping);
+                       skb = ri->skb;
+                       post_ptr = &std_prod_idx;
+                       rx_std_posted++;
+               } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
+                       ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
+                       dma_addr = dma_unmap_addr(ri, mapping);
+                       skb = ri->skb;
+                       post_ptr = &jmb_prod_idx;
+               } else
+                       goto next_pkt_nopost;
+
+               work_mask |= opaque_key;
+
+               if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
+                   (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
+               drop_it:
+                       tg3_recycle_rx(tnapi, tpr, opaque_key,
+                                      desc_idx, *post_ptr);
+               drop_it_no_recycle:
+                       /* Other statistics kept track of by card. */
+                       tp->rx_dropped++;
+                       goto next_pkt;
+               }
+
+               len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
+                     ETH_FCS_LEN;
+
+               if (len > TG3_RX_COPY_THRESH(tp)) {
+                       int skb_size;
+
+                       skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
+                                                   *post_ptr);
+                       if (skb_size < 0)
+                               goto drop_it;
+
+                       pci_unmap_single(tp->pdev, dma_addr, skb_size,
+                                        PCI_DMA_FROMDEVICE);
+
+                       /* Ensure that the update to the skb happens
+                        * after the usage of the old DMA mapping.
+                        */
+                       smp_wmb();
+
+                       ri->skb = NULL;
+
+                       skb_put(skb, len);
+               } else {
+                       struct sk_buff *copy_skb;
+
+                       tg3_recycle_rx(tnapi, tpr, opaque_key,
+                                      desc_idx, *post_ptr);
+
+                       copy_skb = netdev_alloc_skb(tp->dev, len +
+                                                   TG3_RAW_IP_ALIGN);
+                       if (copy_skb == NULL)
+                               goto drop_it_no_recycle;
+
+                       skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
+                       skb_put(copy_skb, len);
+                       pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
+                       skb_copy_from_linear_data(skb, copy_skb->data, len);
+                       pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
+
+                       /* We'll reuse the original ring buffer. */
+                       skb = copy_skb;
+               }
+
+               if ((tp->dev->features & NETIF_F_RXCSUM) &&
+                   (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
+                   (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
+                     >> RXD_TCPCSUM_SHIFT) == 0xffff))
+                       skb->ip_summed = CHECKSUM_UNNECESSARY;
+               else
+                       skb_checksum_none_assert(skb);
+
+               skb->protocol = eth_type_trans(skb, tp->dev);
+
+               if (len > (tp->dev->mtu + ETH_HLEN) &&
+                   skb->protocol != htons(ETH_P_8021Q)) {
+                       dev_kfree_skb(skb);
+                       goto drop_it_no_recycle;
+               }
+
+               if (desc->type_flags & RXD_FLAG_VLAN &&
+                   !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
+                       __vlan_hwaccel_put_tag(skb,
+                                              desc->err_vlan & RXD_VLAN_MASK);
+
+               napi_gro_receive(&tnapi->napi, skb);
+
+               received++;
+               budget--;
+
+next_pkt:
+               (*post_ptr)++;
+
+               if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
+                       tpr->rx_std_prod_idx = std_prod_idx &
+                                              tp->rx_std_ring_mask;
+                       tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
+                                    tpr->rx_std_prod_idx);
+                       work_mask &= ~RXD_OPAQUE_RING_STD;
+                       rx_std_posted = 0;
+               }
+next_pkt_nopost:
+               sw_idx++;
+               sw_idx &= tp->rx_ret_ring_mask;
+
+               /* Refresh hw_idx to see if there is new work */
+               if (sw_idx == hw_idx) {
+                       hw_idx = *(tnapi->rx_rcb_prod_idx);
+                       rmb();
+               }
+       }
+
+       /* ACK the status ring. */
+       tnapi->rx_rcb_ptr = sw_idx;
+       tw32_rx_mbox(tnapi->consmbox, sw_idx);
+
+       /* Refill RX ring(s). */
+       if (!tg3_flag(tp, ENABLE_RSS)) {
+               if (work_mask & RXD_OPAQUE_RING_STD) {
+                       tpr->rx_std_prod_idx = std_prod_idx &
+                                              tp->rx_std_ring_mask;
+                       tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
+                                    tpr->rx_std_prod_idx);
+               }
+               if (work_mask & RXD_OPAQUE_RING_JUMBO) {
+                       tpr->rx_jmb_prod_idx = jmb_prod_idx &
+                                              tp->rx_jmb_ring_mask;
+                       tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
+                                    tpr->rx_jmb_prod_idx);
+               }
+               mmiowb();
+       } else if (work_mask) {
+               /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
+                * updated before the producer indices can be updated.
+                */
+               smp_wmb();
+
+               tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
+               tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
+
+               if (tnapi != &tp->napi[1])
+                       napi_schedule(&tp->napi[1].napi);
+       }
+
+       return received;
+}
+
+static void tg3_poll_link(struct tg3 *tp)
+{
+       /* handle link change and other phy events */
+       if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
+               struct tg3_hw_status *sblk = tp->napi[0].hw_status;
+
+               if (sblk->status & SD_STATUS_LINK_CHG) {
+                       sblk->status = SD_STATUS_UPDATED |
+                                      (sblk->status & ~SD_STATUS_LINK_CHG);
+                       spin_lock(&tp->lock);
+                       if (tg3_flag(tp, USE_PHYLIB)) {
+                               tw32_f(MAC_STATUS,
+                                    (MAC_STATUS_SYNC_CHANGED |
+                                     MAC_STATUS_CFG_CHANGED |
+                                     MAC_STATUS_MI_COMPLETION |
+                                     MAC_STATUS_LNKSTATE_CHANGED));
+                               udelay(40);
+                       } else
+                               tg3_setup_phy(tp, 0);
+                       spin_unlock(&tp->lock);
+               }
+       }
+}
+
+static int tg3_rx_prodring_xfer(struct tg3 *tp,
+                               struct tg3_rx_prodring_set *dpr,
+                               struct tg3_rx_prodring_set *spr)
+{
+       u32 si, di, cpycnt, src_prod_idx;
+       int i, err = 0;
+
+       while (1) {
+               src_prod_idx = spr->rx_std_prod_idx;
+
+               /* Make sure updates to the rx_std_buffers[] entries and the
+                * standard producer index are seen in the correct order.
+                */
+               smp_rmb();
+
+               if (spr->rx_std_cons_idx == src_prod_idx)
+                       break;
+
+               if (spr->rx_std_cons_idx < src_prod_idx)
+                       cpycnt = src_prod_idx - spr->rx_std_cons_idx;
+               else
+                       cpycnt = tp->rx_std_ring_mask + 1 -
+                                spr->rx_std_cons_idx;
+
+               cpycnt = min(cpycnt,
+                            tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
+
+               si = spr->rx_std_cons_idx;
+               di = dpr->rx_std_prod_idx;
+
+               for (i = di; i < di + cpycnt; i++) {
+                       if (dpr->rx_std_buffers[i].skb) {
+                               cpycnt = i - di;
+                               err = -ENOSPC;
+                               break;
+                       }
+               }
+
+               if (!cpycnt)
+                       break;
+
+               /* Ensure that updates to the rx_std_buffers ring and the
+                * shadowed hardware producer ring from tg3_recycle_skb() are
+                * ordered correctly WRT the skb check above.
+                */
+               smp_rmb();
+
+               memcpy(&dpr->rx_std_buffers[di],
+                      &spr->rx_std_buffers[si],
+                      cpycnt * sizeof(struct ring_info));
+
+               for (i = 0; i < cpycnt; i++, di++, si++) {
+                       struct tg3_rx_buffer_desc *sbd, *dbd;
+                       sbd = &spr->rx_std[si];
+                       dbd = &dpr->rx_std[di];
+                       dbd->addr_hi = sbd->addr_hi;
+                       dbd->addr_lo = sbd->addr_lo;
+               }
+
+               spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
+                                      tp->rx_std_ring_mask;
+               dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
+                                      tp->rx_std_ring_mask;
+       }
+
+       while (1) {
+               src_prod_idx = spr->rx_jmb_prod_idx;
+
+               /* Make sure updates to the rx_jmb_buffers[] entries and
+                * the jumbo producer index are seen in the correct order.
+                */
+               smp_rmb();
+
+               if (spr->rx_jmb_cons_idx == src_prod_idx)
+                       break;
+
+               if (spr->rx_jmb_cons_idx < src_prod_idx)
+                       cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
+               else
+                       cpycnt = tp->rx_jmb_ring_mask + 1 -
+                                spr->rx_jmb_cons_idx;
+
+               cpycnt = min(cpycnt,
+                            tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
+
+               si = spr->rx_jmb_cons_idx;
+               di = dpr->rx_jmb_prod_idx;
+
+               for (i = di; i < di + cpycnt; i++) {
+                       if (dpr->rx_jmb_buffers[i].skb) {
+                               cpycnt = i - di;
+                               err = -ENOSPC;
+                               break;
+                       }
+               }
+
+               if (!cpycnt)
+                       break;
+
+               /* Ensure that updates to the rx_jmb_buffers ring and the
+                * shadowed hardware producer ring from tg3_recycle_skb() are
+                * ordered correctly WRT the skb check above.
+                */
+               smp_rmb();
+
+               memcpy(&dpr->rx_jmb_buffers[di],
+                      &spr->rx_jmb_buffers[si],
+                      cpycnt * sizeof(struct ring_info));
+
+               for (i = 0; i < cpycnt; i++, di++, si++) {
+                       struct tg3_rx_buffer_desc *sbd, *dbd;
+                       sbd = &spr->rx_jmb[si].std;
+                       dbd = &dpr->rx_jmb[di].std;
+                       dbd->addr_hi = sbd->addr_hi;
+                       dbd->addr_lo = sbd->addr_lo;
+               }
+
+               spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
+                                      tp->rx_jmb_ring_mask;
+               dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
+                                      tp->rx_jmb_ring_mask;
+       }
+
+       return err;
+}
+
+static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
+{
+       struct tg3 *tp = tnapi->tp;
+
+       /* run TX completion thread */
+       if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
+               tg3_tx(tnapi);
+               if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
+                       return work_done;
+       }
+
+       /* run RX thread, within the bounds set by NAPI.
+        * All RX "locking" is done by ensuring outside
+        * code synchronizes with tg3->napi.poll()
+        */
+       if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
+               work_done += tg3_rx(tnapi, budget - work_done);
+
+       if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
+               struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
+               int i, err = 0;
+               u32 std_prod_idx = dpr->rx_std_prod_idx;
+               u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
+
+               for (i = 1; i < tp->irq_cnt; i++)
+                       err |= tg3_rx_prodring_xfer(tp, dpr,
+                                                   &tp->napi[i].prodring);
+
+               wmb();
+
+               if (std_prod_idx != dpr->rx_std_prod_idx)
+                       tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
+                                    dpr->rx_std_prod_idx);
+
+               if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
+                       tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
+                                    dpr->rx_jmb_prod_idx);
+
+               mmiowb();
+
+               if (err)
+                       tw32_f(HOSTCC_MODE, tp->coal_now);
+       }
+
+       return work_done;
+}
+
+static int tg3_poll_msix(struct napi_struct *napi, int budget)
+{
+       struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
+       struct tg3 *tp = tnapi->tp;
+       int work_done = 0;
+       struct tg3_hw_status *sblk = tnapi->hw_status;
+
+       while (1) {
+               work_done = tg3_poll_work(tnapi, work_done, budget);
+
+               if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
+                       goto tx_recovery;
+
+               if (unlikely(work_done >= budget))
+                       break;
+
+               /* tp->last_tag is used in tg3_int_reenable() below
+                * to tell the hw how much work has been processed,
+                * so we must read it before checking for more work.
+                */
+               tnapi->last_tag = sblk->status_tag;
+               tnapi->last_irq_tag = tnapi->last_tag;
+               rmb();
+
+               /* check for RX/TX work to do */
+               if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
+                          *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
+                       napi_complete(napi);
+                       /* Reenable interrupts. */
+                       tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
+                       mmiowb();
+                       break;
+               }
+       }
+
+       return work_done;
+
+tx_recovery:
+       /* work_done is guaranteed to be less than budget. */
+       napi_complete(napi);
+       schedule_work(&tp->reset_task);
+       return work_done;
+}
+
+static void tg3_process_error(struct tg3 *tp)
+{
+       u32 val;
+       bool real_error = false;
+
+       if (tg3_flag(tp, ERROR_PROCESSED))
+               return;
+
+       /* Check Flow Attention register */
+       val = tr32(HOSTCC_FLOW_ATTN);
+       if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
+               netdev_err(tp->dev, "FLOW Attention error.  Resetting chip.\n");
+               real_error = true;
+       }
+
+       if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
+               netdev_err(tp->dev, "MSI Status error.  Resetting chip.\n");
+               real_error = true;
+       }
+
+       if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
+               netdev_err(tp->dev, "DMA Status error.  Resetting chip.\n");
+               real_error = true;
+       }
+
+       if (!real_error)
+               return;
+
+       tg3_dump_state(tp);
+
+       tg3_flag_set(tp, ERROR_PROCESSED);
+       schedule_work(&tp->reset_task);
+}
+
+static int tg3_poll(struct napi_struct *napi, int budget)
+{
+       struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
+       struct tg3 *tp = tnapi->tp;
+       int work_done = 0;
+       struct tg3_hw_status *sblk = tnapi->hw_status;
+
+       while (1) {
+               if (sblk->status & SD_STATUS_ERROR)
+                       tg3_process_error(tp);
+
+               tg3_poll_link(tp);
+
+               work_done = tg3_poll_work(tnapi, work_done, budget);
+
+               if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
+                       goto tx_recovery;
+
+               if (unlikely(work_done >= budget))
+                       break;
+
+               if (tg3_flag(tp, TAGGED_STATUS)) {
+                       /* tp->last_tag is used in tg3_int_reenable() below
+                        * to tell the hw how much work has been processed,
+                        * so we must read it before checking for more work.
+                        */
+                       tnapi->last_tag = sblk->status_tag;
+                       tnapi->last_irq_tag = tnapi->last_tag;
+                       rmb();
+               } else
+                       sblk->status &= ~SD_STATUS_UPDATED;
+
+               if (likely(!tg3_has_work(tnapi))) {
+                       napi_complete(napi);
+                       tg3_int_reenable(tnapi);
+                       break;
+               }
+       }
+
+       return work_done;
+
+tx_recovery:
+       /* work_done is guaranteed to be less than budget. */
+       napi_complete(napi);
+       schedule_work(&tp->reset_task);
+       return work_done;
+}
+
+static void tg3_napi_disable(struct tg3 *tp)
+{
+       int i;
+
+       for (i = tp->irq_cnt - 1; i >= 0; i--)
+               napi_disable(&tp->napi[i].napi);
+}
+
+static void tg3_napi_enable(struct tg3 *tp)
+{
+       int i;
+
+       for (i = 0; i < tp->irq_cnt; i++)
+               napi_enable(&tp->napi[i].napi);
+}
+
+static void tg3_napi_init(struct tg3 *tp)
+{
+       int i;
+
+       netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
+       for (i = 1; i < tp->irq_cnt; i++)
+               netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
+}
+
+static void tg3_napi_fini(struct tg3 *tp)
+{
+       int i;
+
+       for (i = 0; i < tp->irq_cnt; i++)
+               netif_napi_del(&tp->napi[i].napi);
+}
+
+static inline void tg3_netif_stop(struct tg3 *tp)
+{
+       tp->dev->trans_start = jiffies; /* prevent tx timeout */
+       tg3_napi_disable(tp);
+       netif_tx_disable(tp->dev);
+}
+
+static inline void tg3_netif_start(struct tg3 *tp)
+{
+       /* NOTE: unconditional netif_tx_wake_all_queues is only
+        * appropriate so long as all callers are assured to
+        * have free tx slots (such as after tg3_init_hw)
+        */
+       netif_tx_wake_all_queues(tp->dev);
+
+       tg3_napi_enable(tp);
+       tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
+       tg3_enable_ints(tp);
+}
+
+static void tg3_irq_quiesce(struct tg3 *tp)
+{
+       int i;
+
+       BUG_ON(tp->irq_sync);
+
+       tp->irq_sync = 1;
+       smp_mb();
+
+       for (i = 0; i < tp->irq_cnt; i++)
+               synchronize_irq(tp->napi[i].irq_vec);
+}
+
+/* Fully shutdown all tg3 driver activity elsewhere in the system.
+ * If irq_sync is non-zero, then the IRQ handler must be synchronized
+ * with as well.  Most of the time, this is not necessary except when
+ * shutting down the device.
+ */
+static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
+{
+       spin_lock_bh(&tp->lock);
+       if (irq_sync)
+               tg3_irq_quiesce(tp);
+}
+
+static inline void tg3_full_unlock(struct tg3 *tp)
+{
+       spin_unlock_bh(&tp->lock);
+}
+
+/* One-shot MSI handler - Chip automatically disables interrupt
+ * after sending MSI so driver doesn't have to do it.
+ */
+static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
+{
+       struct tg3_napi *tnapi = dev_id;
+       struct tg3 *tp = tnapi->tp;
+
+       prefetch(tnapi->hw_status);
+       if (tnapi->rx_rcb)
+               prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
+
+       if (likely(!tg3_irq_sync(tp)))
+               napi_schedule(&tnapi->napi);
+
+       return IRQ_HANDLED;
+}
+
+/* MSI ISR - No need to check for interrupt sharing and no need to
+ * flush status block and interrupt mailbox. PCI ordering rules
+ * guarantee that MSI will arrive after the status block.
+ */
+static irqreturn_t tg3_msi(int irq, void *dev_id)
+{
+       struct tg3_napi *tnapi = dev_id;
+       struct tg3 *tp = tnapi->tp;
+
+       prefetch(tnapi->hw_status);
+       if (tnapi->rx_rcb)
+               prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
+       /*
+        * Writing any value to intr-mbox-0 clears PCI INTA# and
+        * chip-internal interrupt pending events.
+        * Writing non-zero to intr-mbox-0 additional tells the
+        * NIC to stop sending us irqs, engaging "in-intr-handler"
+        * event coalescing.
+        */
+       tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
+       if (likely(!tg3_irq_sync(tp)))
+               napi_schedule(&tnapi->napi);
+
+       return IRQ_RETVAL(1);
+}
+
+static irqreturn_t tg3_interrupt(int irq, void *dev_id)
+{
+       struct tg3_napi *tnapi = dev_id;
+       struct tg3 *tp = tnapi->tp;
+       struct tg3_hw_status *sblk = tnapi->hw_status;
+       unsigned int handled = 1;
+
+       /* In INTx mode, it is possible for the interrupt to arrive at
+        * the CPU before the status block posted prior to the interrupt.
+        * Reading the PCI State register will confirm whether the
+        * interrupt is ours and will flush the status block.
+        */
+       if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
+               if (tg3_flag(tp, CHIP_RESETTING) ||
+                   (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
+                       handled = 0;
+                       goto out;
+               }
+       }
+
+       /*
+        * Writing any value to intr-mbox-0 clears PCI INTA# and
+        * chip-internal interrupt pending events.
+        * Writing non-zero to intr-mbox-0 additional tells the
+        * NIC to stop sending us irqs, engaging "in-intr-handler"
+        * event coalescing.
+        *
+        * Flush the mailbox to de-assert the IRQ immediately to prevent
+        * spurious interrupts.  The flush impacts performance but
+        * excessive spurious interrupts can be worse in some cases.
+        */
+       tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
+       if (tg3_irq_sync(tp))
+               goto out;
+       sblk->status &= ~SD_STATUS_UPDATED;
+       if (likely(tg3_has_work(tnapi))) {
+               prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
+               napi_schedule(&tnapi->napi);
+       } else {
+               /* No work, shared interrupt perhaps?  re-enable
+                * interrupts, and flush that PCI write
+                */
+               tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
+                              0x00000000);
+       }
+out:
+       return IRQ_RETVAL(handled);
+}
+
+static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
+{
+       struct tg3_napi *tnapi = dev_id;
+       struct tg3 *tp = tnapi->tp;
+       struct tg3_hw_status *sblk = tnapi->hw_status;
+       unsigned int handled = 1;
+
+       /* In INTx mode, it is possible for the interrupt to arrive at
+        * the CPU before the status block posted prior to the interrupt.
+        * Reading the PCI State register will confirm whether the
+        * interrupt is ours and will flush the status block.
+        */
+       if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
+               if (tg3_flag(tp, CHIP_RESETTING) ||
+                   (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
+                       handled = 0;
+                       goto out;
+               }
+       }
+
+       /*
+        * writing any value to intr-mbox-0 clears PCI INTA# and
+        * chip-internal interrupt pending events.
+        * writing non-zero to intr-mbox-0 additional tells the
+        * NIC to stop sending us irqs, engaging "in-intr-handler"
+        * event coalescing.
+        *
+        * Flush the mailbox to de-assert the IRQ immediately to prevent
+        * spurious interrupts.  The flush impacts performance but
+        * excessive spurious interrupts can be worse in some cases.
+        */
+       tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
+
+       /*
+        * In a shared interrupt configuration, sometimes other devices'
+        * interrupts will scream.  We record the current status tag here
+        * so that the above check can report that the screaming interrupts
+        * are unhandled.  Eventually they will be silenced.
+        */
+       tnapi->last_irq_tag = sblk->status_tag;
+
+       if (tg3_irq_sync(tp))
+               goto out;
+
+       prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
+
+       napi_schedule(&tnapi->napi);
+
+out:
+       return IRQ_RETVAL(handled);
+}
+
+/* ISR for interrupt test */
+static irqreturn_t tg3_test_isr(int irq, void *dev_id)
+{
+       struct tg3_napi *tnapi = dev_id;
+       struct tg3 *tp = tnapi->tp;
+       struct tg3_hw_status *sblk = tnapi->hw_status;
+
+       if ((sblk->status & SD_STATUS_UPDATED) ||
+           !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
+               tg3_disable_ints(tp);
+               return IRQ_RETVAL(1);
+       }
+       return IRQ_RETVAL(0);
+}
+
+static int tg3_init_hw(struct tg3 *, int);
+static int tg3_halt(struct tg3 *, int, int);
+
+/* Restart hardware after configuration changes, self-test, etc.
+ * Invoked with tp->lock held.
+ */
+static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
+       __releases(tp->lock)
+       __acquires(tp->lock)
+{
+       int err;
+
+       err = tg3_init_hw(tp, reset_phy);
+       if (err) {
+               netdev_err(tp->dev,
+                          "Failed to re-initialize device, aborting\n");
+               tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
+               tg3_full_unlock(tp);
+               del_timer_sync(&tp->timer);
+               tp->irq_sync = 0;
+               tg3_napi_enable(tp);
+               dev_close(tp->dev);
+               tg3_full_lock(tp, 0);
+       }
+       return err;
+}
+
+#ifdef CONFIG_NET_POLL_CONTROLLER
+static void tg3_poll_controller(struct net_device *dev)
+{
+       int i;
+       struct tg3 *tp = netdev_priv(dev);
+
+       for (i = 0; i < tp->irq_cnt; i++)
+               tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
+}
+#endif
+
+static void tg3_reset_task(struct work_struct *work)
+{
+       struct tg3 *tp = container_of(work, struct tg3, reset_task);
+       int err;
+       unsigned int restart_timer;
+
+       tg3_full_lock(tp, 0);
+
+       if (!netif_running(tp->dev)) {
+               tg3_full_unlock(tp);
+               return;
+       }
+
+       tg3_full_unlock(tp);
+
+       tg3_phy_stop(tp);
+
+       tg3_netif_stop(tp);
+
+       tg3_full_lock(tp, 1);
+
+       restart_timer = tg3_flag(tp, RESTART_TIMER);
+       tg3_flag_clear(tp, RESTART_TIMER);
+
+       if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
+               tp->write32_tx_mbox = tg3_write32_tx_mbox;
+               tp->write32_rx_mbox = tg3_write_flush_reg32;
+               tg3_flag_set(tp, MBOX_WRITE_REORDER);
+               tg3_flag_clear(tp, TX_RECOVERY_PENDING);
+       }
+
+       tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
+       err = tg3_init_hw(tp, 1);
+       if (err)
+               goto out;
+
+       tg3_netif_start(tp);
+
+       if (restart_timer)
+               mod_timer(&tp->timer, jiffies + 1);
+
+out:
+       tg3_full_unlock(tp);
+
+       if (!err)
+               tg3_phy_start(tp);
+}
+
+static void tg3_tx_timeout(struct net_device *dev)
+{
+       struct tg3 *tp = netdev_priv(dev);
+
+       if (netif_msg_tx_err(tp)) {
+               netdev_err(dev, "transmit timed out, resetting\n");
+               tg3_dump_state(tp);
+       }
+
+       schedule_work(&tp->reset_task);
+}
+
+/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
+static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
+{
+       u32 base = (u32) mapping & 0xffffffff;
+
+       return (base > 0xffffdcc0) && (base + len + 8 < base);
+}
+
+/* Test for DMA addresses > 40-bit */
+static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
+                                         int len)
+{
+#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
+       if (tg3_flag(tp, 40BIT_DMA_BUG))
+               return ((u64) mapping + len) > DMA_BIT_MASK(40);
+       return 0;
+#else
+       return 0;
+#endif
+}
+
+static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
+                       dma_addr_t mapping, int len, u32 flags,
+                       u32 mss_and_is_end)
+{
+       struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
+       int is_end = (mss_and_is_end & 0x1);
+       u32 mss = (mss_and_is_end >> 1);
+       u32 vlan_tag = 0;
+
+       if (is_end)
+               flags |= TXD_FLAG_END;
+       if (flags & TXD_FLAG_VLAN) {
+               vlan_tag = flags >> 16;
+               flags &= 0xffff;
+       }
+       vlan_tag |= (mss << TXD_MSS_SHIFT);
+
+       txd->addr_hi = ((u64) mapping >> 32);
+       txd->addr_lo = ((u64) mapping & 0xffffffff);
+       txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
+       txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
+}
+
+static void tg3_skb_error_unmap(struct tg3_napi *tnapi,
+                               struct sk_buff *skb, int last)
+{
+       int i;
+       u32 entry = tnapi->tx_prod;
+       struct ring_info *txb = &tnapi->tx_buffers[entry];
+
+       pci_unmap_single(tnapi->tp->pdev,
+                        dma_unmap_addr(txb, mapping),
+                        skb_headlen(skb),
+                        PCI_DMA_TODEVICE);
+       for (i = 0; i <= last; i++) {
+               skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
+
+               entry = NEXT_TX(entry);
+               txb = &tnapi->tx_buffers[entry];
+
+               pci_unmap_page(tnapi->tp->pdev,
+                              dma_unmap_addr(txb, mapping),
+                              frag->size, PCI_DMA_TODEVICE);
+       }
+}
+
+/* Workaround 4GB and 40-bit hardware DMA bugs. */
+static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
+                                      struct sk_buff *skb,
+                                      u32 base_flags, u32 mss)
+{
+       struct tg3 *tp = tnapi->tp;
+       struct sk_buff *new_skb;
+       dma_addr_t new_addr = 0;
+       u32 entry = tnapi->tx_prod;
+       int ret = 0;
+
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
+               new_skb = skb_copy(skb, GFP_ATOMIC);
+       else {
+               int more_headroom = 4 - ((unsigned long)skb->data & 3);
+
+               new_skb = skb_copy_expand(skb,
+                                         skb_headroom(skb) + more_headroom,
+                                         skb_tailroom(skb), GFP_ATOMIC);
+       }
+
+       if (!new_skb) {
+               ret = -1;
+       } else {
+               /* New SKB is guaranteed to be linear. */
+               new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
+                                         PCI_DMA_TODEVICE);
+               /* Make sure the mapping succeeded */
+               if (pci_dma_mapping_error(tp->pdev, new_addr)) {
+                       ret = -1;
+                       dev_kfree_skb(new_skb);
+
+               /* Make sure new skb does not cross any 4G boundaries.
+                * Drop the packet if it does.
+                */
+               } else if (tg3_flag(tp, 4G_DMA_BNDRY_BUG) &&
+                          tg3_4g_overflow_test(new_addr, new_skb->len)) {
+                       pci_unmap_single(tp->pdev, new_addr, new_skb->len,
+                                        PCI_DMA_TODEVICE);
+                       ret = -1;
+                       dev_kfree_skb(new_skb);
+               } else {
+                       tnapi->tx_buffers[entry].skb = new_skb;
+                       dma_unmap_addr_set(&tnapi->tx_buffers[entry],
+                                          mapping, new_addr);
+
+                       tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
+                                   base_flags, 1 | (mss << 1));
+               }
+       }
+
+       dev_kfree_skb(skb);
+
+       return ret;
+}
+
+static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
+
+/* Use GSO to workaround a rare TSO bug that may be triggered when the
+ * TSO header is greater than 80 bytes.
+ */
+static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
+{
+       struct sk_buff *segs, *nskb;
+       u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
+
+       /* Estimate the number of fragments in the worst case */
+       if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
+               netif_stop_queue(tp->dev);
+
+               /* netif_tx_stop_queue() must be done before checking
+                * checking tx index in tg3_tx_avail() below, because in
+                * tg3_tx(), we update tx index before checking for
+                * netif_tx_queue_stopped().
+                */
+               smp_mb();
+               if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
+                       return NETDEV_TX_BUSY;
+
+               netif_wake_queue(tp->dev);
+       }
+
+       segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
+       if (IS_ERR(segs))
+               goto tg3_tso_bug_end;
+
+       do {
+               nskb = segs;
+               segs = segs->next;
+               nskb->next = NULL;
+               tg3_start_xmit(nskb, tp->dev);
+       } while (segs);
+
+tg3_tso_bug_end:
+       dev_kfree_skb(skb);
+
+       return NETDEV_TX_OK;
+}
+
+/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
+ * support TG3_FLAG_HW_TSO_1 or firmware TSO only.
+ */
+static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+       struct tg3 *tp = netdev_priv(dev);
+       u32 len, entry, base_flags, mss;
+       int i = -1, would_hit_hwbug;
+       dma_addr_t mapping;
+       struct tg3_napi *tnapi;
+       struct netdev_queue *txq;
+       unsigned int last;
+
+       txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
+       tnapi = &tp->napi[skb_get_queue_mapping(skb)];
+       if (tg3_flag(tp, ENABLE_TSS))
+               tnapi++;
+
+       /* We are running in BH disabled context with netif_tx_lock
+        * and TX reclaim runs via tp->napi.poll inside of a software
+        * interrupt.  Furthermore, IRQ processing runs lockless so we have
+        * no IRQ context deadlocks to worry about either.  Rejoice!
+        */
+       if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
+               if (!netif_tx_queue_stopped(txq)) {
+                       netif_tx_stop_queue(txq);
+
+                       /* This is a hard error, log it. */
+                       netdev_err(dev,
+                                  "BUG! Tx Ring full when queue awake!\n");
+               }
+               return NETDEV_TX_BUSY;
+       }
+
+       entry = tnapi->tx_prod;
+       base_flags = 0;
+       if (skb->ip_summed == CHECKSUM_PARTIAL)
+               base_flags |= TXD_FLAG_TCPUDP_CSUM;
+
+       mss = skb_shinfo(skb)->gso_size;
+       if (mss) {
+               struct iphdr *iph;
+               u32 tcp_opt_len, hdr_len;
+
+               if (skb_header_cloned(skb) &&
+                   pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
+                       dev_kfree_skb(skb);
+                       goto out_unlock;
+               }
+
+               iph = ip_hdr(skb);
+               tcp_opt_len = tcp_optlen(skb);
+
+               if (skb_is_gso_v6(skb)) {
+                       hdr_len = skb_headlen(skb) - ETH_HLEN;
+               } else {
+                       u32 ip_tcp_len;
+
+                       ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
+                       hdr_len = ip_tcp_len + tcp_opt_len;
+
+                       iph->check = 0;
+                       iph->tot_len = htons(mss + hdr_len);
+               }
+
+               if (unlikely((ETH_HLEN + hdr_len) > 80) &&
+                   tg3_flag(tp, TSO_BUG))
+                       return tg3_tso_bug(tp, skb);
+
+               base_flags |= (TXD_FLAG_CPU_PRE_DMA |
+                              TXD_FLAG_CPU_POST_DMA);
+
+               if (tg3_flag(tp, HW_TSO_1) ||
+                   tg3_flag(tp, HW_TSO_2) ||
+                   tg3_flag(tp, HW_TSO_3)) {
+                       tcp_hdr(skb)->check = 0;
+                       base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
+               } else
+                       tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
+                                                                iph->daddr, 0,
+                                                                IPPROTO_TCP,
+                                                                0);
+
+               if (tg3_flag(tp, HW_TSO_3)) {
+                       mss |= (hdr_len & 0xc) << 12;
+                       if (hdr_len & 0x10)
+                               base_flags |= 0x00000010;
+                       base_flags |= (hdr_len & 0x3e0) << 5;
+               } else if (tg3_flag(tp, HW_TSO_2))
+                       mss |= hdr_len << 9;
+               else if (tg3_flag(tp, HW_TSO_1) ||
+                        GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
+                       if (tcp_opt_len || iph->ihl > 5) {
+                               int tsflags;
+
+                               tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
+                               mss |= (tsflags << 11);
+                       }
+               } else {
+                       if (tcp_opt_len || iph->ihl > 5) {
+                               int tsflags;
+
+                               tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
+                               base_flags |= tsflags << 12;
+                       }
+               }
+       }
+
+       if (vlan_tx_tag_present(skb))
+               base_flags |= (TXD_FLAG_VLAN |
+                              (vlan_tx_tag_get(skb) << 16));
+
+       if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
+           !mss && skb->len > VLAN_ETH_FRAME_LEN)
+               base_flags |= TXD_FLAG_JMB_PKT;
+
+       len = skb_headlen(skb);
+
+       mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
+       if (pci_dma_mapping_error(tp->pdev, mapping)) {
+               dev_kfree_skb(skb);
+               goto out_unlock;
+       }
+
+       tnapi->tx_buffers[entry].skb = skb;
+       dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
+
+       would_hit_hwbug = 0;
+
+       if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
+               would_hit_hwbug = 1;
+
+       if (tg3_flag(tp, 4G_DMA_BNDRY_BUG) &&
+           tg3_4g_overflow_test(mapping, len))
+               would_hit_hwbug = 1;
+
+       if (tg3_flag(tp, 40BIT_DMA_LIMIT_BUG) &&
+           tg3_40bit_overflow_test(tp, mapping, len))
+               would_hit_hwbug = 1;
+
+       if (tg3_flag(tp, 5701_DMA_BUG))
+               would_hit_hwbug = 1;
+
+       tg3_set_txd(tnapi, entry, mapping, len, base_flags,
+                   (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
+
+       entry = NEXT_TX(entry);
+
+       /* Now loop through additional data fragments, and queue them. */
+       if (skb_shinfo(skb)->nr_frags > 0) {
+               last = skb_shinfo(skb)->nr_frags - 1;
+               for (i = 0; i <= last; i++) {
+                       skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
+
+                       len = frag->size;
+                       mapping = pci_map_page(tp->pdev,
+                                              frag->page,
+                                              frag->page_offset,
+                                              len, PCI_DMA_TODEVICE);
+
+                       tnapi->tx_buffers[entry].skb = NULL;
+                       dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
+                                          mapping);
+                       if (pci_dma_mapping_error(tp->pdev, mapping))
+                               goto dma_error;
+
+                       if (tg3_flag(tp, SHORT_DMA_BUG) &&
+                           len <= 8)
+                               would_hit_hwbug = 1;
+
+                       if (tg3_flag(tp, 4G_DMA_BNDRY_BUG) &&
+                           tg3_4g_overflow_test(mapping, len))
+                               would_hit_hwbug = 1;
+
+                       if (tg3_flag(tp, 40BIT_DMA_LIMIT_BUG) &&
+                           tg3_40bit_overflow_test(tp, mapping, len))
+                               would_hit_hwbug = 1;
+
+                       if (tg3_flag(tp, HW_TSO_1) ||
+                           tg3_flag(tp, HW_TSO_2) ||
+                           tg3_flag(tp, HW_TSO_3))
+                               tg3_set_txd(tnapi, entry, mapping, len,
+                                           base_flags, (i == last)|(mss << 1));
+                       else
+                               tg3_set_txd(tnapi, entry, mapping, len,
+                                           base_flags, (i == last));
+
+                       entry = NEXT_TX(entry);
+               }
+       }
+
+       if (would_hit_hwbug) {
+               tg3_skb_error_unmap(tnapi, skb, i);
+
+               /* If the workaround fails due to memory/mapping
+                * failure, silently drop this packet.
+                */
+               if (tigon3_dma_hwbug_workaround(tnapi, skb, base_flags, mss))
+                       goto out_unlock;
+
+               entry = NEXT_TX(tnapi->tx_prod);
+       }
+
+       /* Packets are ready, update Tx producer idx local and on card. */
+       tw32_tx_mbox(tnapi->prodmbox, entry);
+
+       tnapi->tx_prod = entry;
+       if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
+               netif_tx_stop_queue(txq);
+
+               /* netif_tx_stop_queue() must be done before checking
+                * checking tx index in tg3_tx_avail() below, because in
+                * tg3_tx(), we update tx index before checking for
+                * netif_tx_queue_stopped().
+                */
+               smp_mb();
+               if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
+                       netif_tx_wake_queue(txq);
+       }
+
+out_unlock:
+       mmiowb();
+
+       return NETDEV_TX_OK;
+
+dma_error:
+       tg3_skb_error_unmap(tnapi, skb, i);
+       dev_kfree_skb(skb);
+       tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
+       return NETDEV_TX_OK;
+}
+
+static void tg3_set_loopback(struct net_device *dev, u32 features)
+{
+       struct tg3 *tp = netdev_priv(dev);
+
+       if (features & NETIF_F_LOOPBACK) {
+               if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
+                       return;
+
+               /*
+                * Clear MAC_MODE_HALF_DUPLEX or you won't get packets back in
+                * loopback mode if Half-Duplex mode was negotiated earlier.
+                */
+               tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
+
+               /* Enable internal MAC loopback mode */
+               tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
+               spin_lock_bh(&tp->lock);
+               tw32(MAC_MODE, tp->mac_mode);
+               netif_carrier_on(tp->dev);
+               spin_unlock_bh(&tp->lock);
+               netdev_info(dev, "Internal MAC loopback mode enabled.\n");
+       } else {
+               if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
+                       return;
+
+               /* Disable internal MAC loopback mode */
+               tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
+               spin_lock_bh(&tp->lock);
+               tw32(MAC_MODE, tp->mac_mode);
+               /* Force link status check */
+               tg3_setup_phy(tp, 1);
+               spin_unlock_bh(&tp->lock);
+               netdev_info(dev, "Internal MAC loopback mode disabled.\n");
+       }
+}
+
+static u32 tg3_fix_features(struct net_device *dev, u32 features)
+{
+       struct tg3 *tp = netdev_priv(dev);
+
+       if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
+               features &= ~NETIF_F_ALL_TSO;
+
+       return features;
+}
+
+static int tg3_set_features(struct net_device *dev, u32 features)
+{
+       u32 changed = dev->features ^ features;
+
+       if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
+               tg3_set_loopback(dev, features);
+
+       return 0;
+}
+
+static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
+                              int new_mtu)
+{
+       dev->mtu = new_mtu;
+
+       if (new_mtu > ETH_DATA_LEN) {
+               if (tg3_flag(tp, 5780_CLASS)) {
+                       netdev_update_features(dev);
+                       tg3_flag_clear(tp, TSO_CAPABLE);
+               } else {
+                       tg3_flag_set(tp, JUMBO_RING_ENABLE);
+               }
+       } else {
+               if (tg3_flag(tp, 5780_CLASS)) {
+                       tg3_flag_set(tp, TSO_CAPABLE);
+                       netdev_update_features(dev);
+               }
+               tg3_flag_clear(tp, JUMBO_RING_ENABLE);
+       }
+}
+
+static int tg3_change_mtu(struct net_device *dev, int new_mtu)
+{
+       struct tg3 *tp = netdev_priv(dev);
+       int err;
+
+       if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
+               return -EINVAL;
+
+       if (!netif_running(dev)) {
+               /* We'll just catch it later when the
+                * device is up'd.
+                */
+               tg3_set_mtu(dev, tp, new_mtu);
+               return 0;
+       }
+
+       tg3_phy_stop(tp);
+
+       tg3_netif_stop(tp);
+
+       tg3_full_lock(tp, 1);
+
+       tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
+
+       tg3_set_mtu(dev, tp, new_mtu);
+
+       err = tg3_restart_hw(tp, 0);
+
+       if (!err)
+               tg3_netif_start(tp);
+
+       tg3_full_unlock(tp);
+
+       if (!err)
+               tg3_phy_start(tp);
+
+       return err;
+}
+
+static void tg3_rx_prodring_free(struct tg3 *tp,
+                                struct tg3_rx_prodring_set *tpr)
+{
+       int i;
+
+       if (tpr != &tp->napi[0].prodring) {
+               for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
+                    i = (i + 1) & tp->rx_std_ring_mask)
+                       tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
+                                       tp->rx_pkt_map_sz);
+
+               if (tg3_flag(tp, JUMBO_CAPABLE)) {
+                       for (i = tpr->rx_jmb_cons_idx;
+                            i != tpr->rx_jmb_prod_idx;
+                            i = (i + 1) & tp->rx_jmb_ring_mask) {
+                               tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
+                                               TG3_RX_JMB_MAP_SZ);
+                       }
+               }
+
+               return;
+       }
+
+       for (i = 0; i <= tp->rx_std_ring_mask; i++)
+               tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
+                               tp->rx_pkt_map_sz);
+
+       if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
+               for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
+                       tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
+                                       TG3_RX_JMB_MAP_SZ);
+       }
+}
+
+/* Initialize rx rings for packet processing.
+ *
+ * The chip has been shut down and the driver detached from
+ * the networking, so no interrupts or new tx packets will
+ * end up in the driver.  tp->{tx,}lock are held and thus
+ * we may not sleep.
+ */
+static int tg3_rx_prodring_alloc(struct tg3 *tp,
+                                struct tg3_rx_prodring_set *tpr)
+{
+       u32 i, rx_pkt_dma_sz;
+
+       tpr->rx_std_cons_idx = 0;
+       tpr->rx_std_prod_idx = 0;
+       tpr->rx_jmb_cons_idx = 0;
+       tpr->rx_jmb_prod_idx = 0;
+
+       if (tpr != &tp->napi[0].prodring) {
+               memset(&tpr->rx_std_buffers[0], 0,
+                      TG3_RX_STD_BUFF_RING_SIZE(tp));
+               if (tpr->rx_jmb_buffers)
+                       memset(&tpr->rx_jmb_buffers[0], 0,
+                              TG3_RX_JMB_BUFF_RING_SIZE(tp));
+               goto done;
+       }
+
+       /* Zero out all descriptors. */
+       memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
+
+       rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
+       if (tg3_flag(tp, 5780_CLASS) &&
+           tp->dev->mtu > ETH_DATA_LEN)
+               rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
+       tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
+
+       /* Initialize invariants of the rings, we only set this
+        * stuff once.  This works because the card does not
+        * write into the rx buffer posting rings.
+        */
+       for (i = 0; i <= tp->rx_std_ring_mask; i++) {
+               struct tg3_rx_buffer_desc *rxd;
+
+               rxd = &tpr->rx_std[i];
+               rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
+               rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
+               rxd->opaque = (RXD_OPAQUE_RING_STD |
+                              (i << RXD_OPAQUE_INDEX_SHIFT));
+       }
+
+       /* Now allocate fresh SKBs for each rx ring. */
+       for (i = 0; i < tp->rx_pending; i++) {
+               if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
+                       netdev_warn(tp->dev,
+                                   "Using a smaller RX standard ring. Only "
+                                   "%d out of %d buffers were allocated "
+                                   "successfully\n", i, tp->rx_pending);
+                       if (i == 0)
+                               goto initfail;
+                       tp->rx_pending = i;
+                       break;
+               }
+       }
+
+       if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
+               goto done;
+
+       memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
+
+       if (!tg3_flag(tp, JUMBO_RING_ENABLE))
+               goto done;
+
+       for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
+               struct tg3_rx_buffer_desc *rxd;
+
+               rxd = &tpr->rx_jmb[i].std;
+               rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
+               rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
+                                 RXD_FLAG_JUMBO;
+               rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
+                      (i << RXD_OPAQUE_INDEX_SHIFT));
+       }
+
+       for (i = 0; i < tp->rx_jumbo_pending; i++) {
+               if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
+                       netdev_warn(tp->dev,
+                                   "Using a smaller RX jumbo ring. Only %d "
+                                   "out of %d buffers were allocated "
+                                   "successfully\n", i, tp->rx_jumbo_pending);
+                       if (i == 0)
+                               goto initfail;
+                       tp->rx_jumbo_pending = i;
+                       break;
+               }
+       }
+
+done:
+       return 0;
+
+initfail:
+       tg3_rx_prodring_free(tp, tpr);
+       return -ENOMEM;
+}
+
+static void tg3_rx_prodring_fini(struct tg3 *tp,
+                                struct tg3_rx_prodring_set *tpr)
+{
+       kfree(tpr->rx_std_buffers);
+       tpr->rx_std_buffers = NULL;
+       kfree(tpr->rx_jmb_buffers);
+       tpr->rx_jmb_buffers = NULL;
+       if (tpr->rx_std) {
+               dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
+                                 tpr->rx_std, tpr->rx_std_mapping);
+               tpr->rx_std = NULL;
+       }
+       if (tpr->rx_jmb) {
+               dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
+                                 tpr->rx_jmb, tpr->rx_jmb_mapping);
+               tpr->rx_jmb = NULL;
+       }
+}
+
+static int tg3_rx_prodring_init(struct tg3 *tp,
+                               struct tg3_rx_prodring_set *tpr)
+{
+       tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
+                                     GFP_KERNEL);
+       if (!tpr->rx_std_buffers)
+               return -ENOMEM;
+
+       tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
+                                        TG3_RX_STD_RING_BYTES(tp),
+                                        &tpr->rx_std_mapping,
+                                        GFP_KERNEL);
+       if (!tpr->rx_std)
+               goto err_out;
+
+       if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
+               tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
+                                             GFP_KERNEL);
+               if (!tpr->rx_jmb_buffers)
+                       goto err_out;
+
+               tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
+                                                TG3_RX_JMB_RING_BYTES(tp),
+                                                &tpr->rx_jmb_mapping,
+                                                GFP_KERNEL);
+               if (!tpr->rx_jmb)
+                       goto err_out;
+       }
+
+       return 0;
+
+err_out:
+       tg3_rx_prodring_fini(tp, tpr);
+       return -ENOMEM;
+}
+
+/* Free up pending packets in all rx/tx rings.
+ *
+ * The chip has been shut down and the driver detached from
+ * the networking, so no interrupts or new tx packets will
+ * end up in the driver.  tp->{tx,}lock is not held and we are not
+ * in an interrupt context and thus may sleep.
+ */
+static void tg3_free_rings(struct tg3 *tp)
+{
+       int i, j;
+
+       for (j = 0; j < tp->irq_cnt; j++) {
+               struct tg3_napi *tnapi = &tp->napi[j];
+
+               tg3_rx_prodring_free(tp, &tnapi->prodring);
+
+               if (!tnapi->tx_buffers)
+                       continue;
+
+               for (i = 0; i < TG3_TX_RING_SIZE; ) {
+                       struct ring_info *txp;
+                       struct sk_buff *skb;
+                       unsigned int k;
+
+                       txp = &tnapi->tx_buffers[i];
+                       skb = txp->skb;
+
+                       if (skb == NULL) {
+                               i++;
+                               continue;
+                       }
+
+                       pci_unmap_single(tp->pdev,
+                                        dma_unmap_addr(txp, mapping),
+                                        skb_headlen(skb),
+                                        PCI_DMA_TODEVICE);
+                       txp->skb = NULL;
+
+                       i++;
+
+                       for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
+                               txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
+                               pci_unmap_page(tp->pdev,
+                                              dma_unmap_addr(txp, mapping),
+                                              skb_shinfo(skb)->frags[k].size,
+                                              PCI_DMA_TODEVICE);
+                               i++;
+                       }
+
+                       dev_kfree_skb_any(skb);
+               }
+       }
+}
+
+/* Initialize tx/rx rings for packet processing.
+ *
+ * The chip has been shut down and the driver detached from
+ * the networking, so no interrupts or new tx packets will
+ * end up in the driver.  tp->{tx,}lock are held and thus
+ * we may not sleep.
+ */
+static int tg3_init_rings(struct tg3 *tp)
+{
+       int i;
+
+       /* Free up all the SKBs. */
+       tg3_free_rings(tp);
+
+       for (i = 0; i < tp->irq_cnt; i++) {
+               struct tg3_napi *tnapi = &tp->napi[i];
+
+               tnapi->last_tag = 0;
+               tnapi->last_irq_tag = 0;
+               tnapi->hw_status->status = 0;
+               tnapi->hw_status->status_tag = 0;
+               memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
+
+               tnapi->tx_prod = 0;
+               tnapi->tx_cons = 0;
+               if (tnapi->tx_ring)
+                       memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
+
+               tnapi->rx_rcb_ptr = 0;
+               if (tnapi->rx_rcb)
+                       memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
+
+               if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
+                       tg3_free_rings(tp);
+                       return -ENOMEM;
+               }
+       }
+
+       return 0;
+}
+
+/*
+ * Must not be invoked with interrupt sources disabled and
+ * the hardware shutdown down.
+ */
+static void tg3_free_consistent(struct tg3 *tp)
+{
+       int i;
+
+       for (i = 0; i < tp->irq_cnt; i++) {
+               struct tg3_napi *tnapi = &tp->napi[i];
+
+               if (tnapi->tx_ring) {
+                       dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
+                               tnapi->tx_ring, tnapi->tx_desc_mapping);
+                       tnapi->tx_ring = NULL;
+               }
+
+               kfree(tnapi->tx_buffers);
+               tnapi->tx_buffers = NULL;
+
+               if (tnapi->rx_rcb) {
+                       dma_free_coherent(&tp->pdev->dev,
+                                         TG3_RX_RCB_RING_BYTES(tp),
+                                         tnapi->rx_rcb,
+                                         tnapi->rx_rcb_mapping);
+                       tnapi->rx_rcb = NULL;
+               }
+
+               tg3_rx_prodring_fini(tp, &tnapi->prodring);
+
+               if (tnapi->hw_status) {
+                       dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
+                                         tnapi->hw_status,
+                                         tnapi->status_mapping);
+                       tnapi->hw_status = NULL;
+               }
+       }
+
+       if (tp->hw_stats) {
+               dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
+                                 tp->hw_stats, tp->stats_mapping);
+               tp->hw_stats = NULL;
+       }
+}
+
+/*
+ * Must not be invoked with interrupt sources disabled and
+ * the hardware shutdown down.  Can sleep.
+ */
+static int tg3_alloc_consistent(struct tg3 *tp)
+{
+       int i;
+
+       tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev,
+                                         sizeof(struct tg3_hw_stats),
+                                         &tp->stats_mapping,
+                                         GFP_KERNEL);
+       if (!tp->hw_stats)
+               goto err_out;
+
+       memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
+
+       for (i = 0; i < tp->irq_cnt; i++) {
+               struct tg3_napi *tnapi = &tp->napi[i];
+               struct tg3_hw_status *sblk;
+
+               tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev,
+                                                     TG3_HW_STATUS_SIZE,
+                                                     &tnapi->status_mapping,
+                                                     GFP_KERNEL);
+               if (!tnapi->hw_status)
+                       goto err_out;
+
+               memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
+               sblk = tnapi->hw_status;
+
+               if (tg3_rx_prodring_init(tp, &tnapi->prodring))
+                       goto err_out;
+
+               /* If multivector TSS is enabled, vector 0 does not handle
+                * tx interrupts.  Don't allocate any resources for it.
+                */
+               if ((!i && !tg3_flag(tp, ENABLE_TSS)) ||
+                   (i && tg3_flag(tp, ENABLE_TSS))) {
+                       tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
+                                                   TG3_TX_RING_SIZE,
+                                                   GFP_KERNEL);
+                       if (!tnapi->tx_buffers)
+                               goto err_out;
+
+                       tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
+                                                           TG3_TX_RING_BYTES,
+                                                       &tnapi->tx_desc_mapping,
+                                                           GFP_KERNEL);
+                       if (!tnapi->tx_ring)
+                               goto err_out;
+               }
+
+               /*
+                * When RSS is enabled, the status block format changes
+                * slightly.  The "rx_jumbo_consumer", "reserved",
+                * and "rx_mini_consumer" members get mapped to the
+                * other three rx return ring producer indexes.
+                */
+               switch (i) {
+               default:
+                       tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
+                       break;
+               case 2:
+                       tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
+                       break;
+               case 3:
+                       tnapi->rx_rcb_prod_idx = &sblk->reserved;
+                       break;
+               case 4:
+                       tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
+                       break;
+               }
+
+               /*
+                * If multivector RSS is enabled, vector 0 does not handle
+                * rx or tx interrupts.  Don't allocate any resources for it.
+                */
+               if (!i && tg3_flag(tp, ENABLE_RSS))
+                       continue;
+
+               tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev,
+                                                  TG3_RX_RCB_RING_BYTES(tp),
+                                                  &tnapi->rx_rcb_mapping,
+                                                  GFP_KERNEL);
+               if (!tnapi->rx_rcb)
+                       goto err_out;
+
+               memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
+       }
+
+       return 0;
+
+err_out:
+       tg3_free_consistent(tp);
+       return -ENOMEM;
+}
+
+#define MAX_WAIT_CNT 1000
+
+/* To stop a block, clear the enable bit and poll till it
+ * clears.  tp->lock is held.
+ */
+static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
+{
+       unsigned int i;
+       u32 val;
+
+       if (tg3_flag(tp, 5705_PLUS)) {
+               switch (ofs) {
+               case RCVLSC_MODE:
+               case DMAC_MODE:
+               case MBFREE_MODE:
+               case BUFMGR_MODE:
+               case MEMARB_MODE:
+                       /* We can't enable/disable these bits of the
+                        * 5705/5750, just say success.
+                        */
+                       return 0;
+
+               default:
+                       break;
+               }
+       }
+
+       val = tr32(ofs);
+       val &= ~enable_bit;
+       tw32_f(ofs, val);
+
+       for (i = 0; i < MAX_WAIT_CNT; i++) {
+               udelay(100);
+               val = tr32(ofs);
+               if ((val & enable_bit) == 0)
+                       break;
+       }
+
+       if (i == MAX_WAIT_CNT && !silent) {
+               dev_err(&tp->pdev->dev,
+                       "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
+                       ofs, enable_bit);
+               return -ENODEV;
+       }
+
+       return 0;
+}
+
+/* tp->lock is held. */
+static int tg3_abort_hw(struct tg3 *tp, int silent)
+{
+       int i, err;
+
+       tg3_disable_ints(tp);
+
+       tp->rx_mode &= ~RX_MODE_ENABLE;
+       tw32_f(MAC_RX_MODE, tp->rx_mode);
+       udelay(10);
+
+       err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
+       err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
+       err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
+       err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
+       err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
+       err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
+
+       err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
+       err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
+       err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
+       err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
+       err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
+       err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
+       err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
+
+       tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
+       tw32_f(MAC_MODE, tp->mac_mode);
+       udelay(40);
+
+       tp->tx_mode &= ~TX_MODE_ENABLE;
+       tw32_f(MAC_TX_MODE, tp->tx_mode);
+
+       for (i = 0; i < MAX_WAIT_CNT; i++) {
+               udelay(100);
+               if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
+                       break;
+       }
+       if (i >= MAX_WAIT_CNT) {
+               dev_err(&tp->pdev->dev,
+                       "%s timed out, TX_MODE_ENABLE will not clear "
+                       "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
+               err |= -ENODEV;
+       }
+
+       err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
+       err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
+       err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
+
+       tw32(FTQ_RESET, 0xffffffff);
+       tw32(FTQ_RESET, 0x00000000);
+
+       err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
+       err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
+
+       for (i = 0; i < tp->irq_cnt; i++) {
+               struct tg3_napi *tnapi = &tp->napi[i];
+               if (tnapi->hw_status)
+                       memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
+       }
+       if (tp->hw_stats)
+               memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
+
+       return err;
+}
+
+static void tg3_ape_send_event(struct tg3 *tp, u32 event)
+{
+       int i;
+       u32 apedata;
+
+       /* NCSI does not support APE events */
+       if (tg3_flag(tp, APE_HAS_NCSI))
+               return;
+
+       apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
+       if (apedata != APE_SEG_SIG_MAGIC)
+               return;
+
+       apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
+       if (!(apedata & APE_FW_STATUS_READY))
+               return;
+
+       /* Wait for up to 1 millisecond for APE to service previous event. */
+       for (i = 0; i < 10; i++) {
+               if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
+                       return;
+
+               apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
+
+               if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
+                       tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
+                                       event | APE_EVENT_STATUS_EVENT_PENDING);
+
+               tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
+
+               if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
+                       break;
+
+               udelay(100);
+       }
+
+       if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
+               tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
+}
+
+static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
+{
+       u32 event;
+       u32 apedata;
+
+       if (!tg3_flag(tp, ENABLE_APE))
+               return;
+
+       switch (kind) {
+       case RESET_KIND_INIT:
+               tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
+                               APE_HOST_SEG_SIG_MAGIC);
+               tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
+                               APE_HOST_SEG_LEN_MAGIC);
+               apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
+               tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
+               tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
+                       APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
+               tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
+                               APE_HOST_BEHAV_NO_PHYLOCK);
+               tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
+                                   TG3_APE_HOST_DRVR_STATE_START);
+
+               event = APE_EVENT_STATUS_STATE_START;
+               break;
+       case RESET_KIND_SHUTDOWN:
+               /* With the interface we are currently using,
+                * APE does not track driver state.  Wiping
+                * out the HOST SEGMENT SIGNATURE forces
+                * the APE to assume OS absent status.
+                */
+               tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
+
+               if (device_may_wakeup(&tp->pdev->dev) &&
+                   tg3_flag(tp, WOL_ENABLE)) {
+                       tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
+                                           TG3_APE_HOST_WOL_SPEED_AUTO);
+                       apedata = TG3_APE_HOST_DRVR_STATE_WOL;
+               } else
+                       apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
+
+               tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
+
+               event = APE_EVENT_STATUS_STATE_UNLOAD;
+               break;
+       case RESET_KIND_SUSPEND:
+               event = APE_EVENT_STATUS_STATE_SUSPEND;
+               break;
+       default:
+               return;
+       }
+
+       event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
+
+       tg3_ape_send_event(tp, event);
+}
+
+/* tp->lock is held. */
+static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
+{
+       tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
+                     NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
+
+       if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
+               switch (kind) {
+               case RESET_KIND_INIT:
+                       tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
+                                     DRV_STATE_START);
+                       break;
+
+               case RESET_KIND_SHUTDOWN:
+                       tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
+                                     DRV_STATE_UNLOAD);
+                       break;
+
+               case RESET_KIND_SUSPEND:
+                       tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
+                                     DRV_STATE_SUSPEND);
+                       break;
+
+               default:
+                       break;
+               }
+       }
+
+       if (kind == RESET_KIND_INIT ||
+           kind == RESET_KIND_SUSPEND)
+               tg3_ape_driver_state_change(tp, kind);
+}
+
+/* tp->lock is held. */
+static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
+{
+       if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
+               switch (kind) {
+               case RESET_KIND_INIT:
+                       tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
+                                     DRV_STATE_START_DONE);
+                       break;
+
+               case RESET_KIND_SHUTDOWN:
+                       tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
+                                     DRV_STATE_UNLOAD_DONE);
+                       break;
+
+               default:
+                       break;
+               }
+       }
+
+       if (kind == RESET_KIND_SHUTDOWN)
+               tg3_ape_driver_state_change(tp, kind);
+}
+
+/* tp->lock is held. */
+static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
+{
+       if (tg3_flag(tp, ENABLE_ASF)) {
+               switch (kind) {
+               case RESET_KIND_INIT:
+                       tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
+                                     DRV_STATE_START);
+                       break;
+
+               case RESET_KIND_SHUTDOWN:
+                       tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
+                                     DRV_STATE_UNLOAD);
+                       break;
+
+               case RESET_KIND_SUSPEND:
+                       tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
+                                     DRV_STATE_SUSPEND);
+                       break;
+
+               default:
+                       break;
+               }
+       }
+}
+
+static int tg3_poll_fw(struct tg3 *tp)
+{
+       int i;
+       u32 val;
+
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
+               /* Wait up to 20ms for init done. */
+               for (i = 0; i < 200; i++) {
+                       if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
+                               return 0;
+                       udelay(100);
+               }
+               return -ENODEV;
+       }
+
+       /* Wait for firmware initialization to complete. */
+       for (i = 0; i < 100000; i++) {
+               tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
+               if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
+                       break;
+               udelay(10);
+       }
+
+       /* Chip might not be fitted with firmware.  Some Sun onboard
+        * parts are configured like that.  So don't signal the timeout
+        * of the above loop as an error, but do report the lack of
+        * running firmware once.
+        */
+       if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
+               tg3_flag_set(tp, NO_FWARE_REPORTED);
+
+               netdev_info(tp->dev, "No firmware running\n");
+       }
+
+       if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
+               /* The 57765 A0 needs a little more
+                * time to do some important work.
+                */
+               mdelay(10);
+       }
+
+       return 0;
+}
+
+/* Save PCI command register before chip reset */
+static void tg3_save_pci_state(struct tg3 *tp)
+{
+       pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
+}
+
+/* Restore PCI state after chip reset */
+static void tg3_restore_pci_state(struct tg3 *tp)
+{
+       u32 val;
+
+       /* Re-enable indirect register accesses. */
+       pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
+                              tp->misc_host_ctrl);
+
+       /* Set MAX PCI retry to zero. */
+       val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
+       if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
+           tg3_flag(tp, PCIX_MODE))
+               val |= PCISTATE_RETRY_SAME_DMA;
+       /* Allow reads and writes to the APE register and memory space. */
+       if (tg3_flag(tp, ENABLE_APE))
+               val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
+                      PCISTATE_ALLOW_APE_SHMEM_WR |
+                      PCISTATE_ALLOW_APE_PSPACE_WR;
+       pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
+
+       pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
+
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
+               if (tg3_flag(tp, PCI_EXPRESS))
+                       pcie_set_readrq(tp->pdev, tp->pcie_readrq);
+               else {
+                       pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
+                                             tp->pci_cacheline_sz);
+                       pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
+                                             tp->pci_lat_timer);
+               }
+       }
+
+       /* Make sure PCI-X relaxed ordering bit is clear. */
+       if (tg3_flag(tp, PCIX_MODE)) {
+               u16 pcix_cmd;
+
+               pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
+                                    &pcix_cmd);
+               pcix_cmd &= ~PCI_X_CMD_ERO;
+               pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
+                                     pcix_cmd);
+       }
+
+       if (tg3_flag(tp, 5780_CLASS)) {
+
+               /* Chip reset on 5780 will reset MSI enable bit,
+                * so need to restore it.
+                */
+               if (tg3_flag(tp, USING_MSI)) {
+                       u16 ctrl;
+
+                       pci_read_config_word(tp->pdev,
+                                            tp->msi_cap + PCI_MSI_FLAGS,
+                                            &ctrl);
+                       pci_write_config_word(tp->pdev,
+                                             tp->msi_cap + PCI_MSI_FLAGS,
+                                             ctrl | PCI_MSI_FLAGS_ENABLE);
+                       val = tr32(MSGINT_MODE);
+                       tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
+               }
+       }
+}
+
+static void tg3_stop_fw(struct tg3 *);
+
+/* tp->lock is held. */
+static int tg3_chip_reset(struct tg3 *tp)
+{
+       u32 val;
+       void (*write_op)(struct tg3 *, u32, u32);
+       int i, err;
+
+       tg3_nvram_lock(tp);
+
+       tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
+
+       /* No matching tg3_nvram_unlock() after this because
+        * chip reset below will undo the nvram lock.
+        */
+       tp->nvram_lock_cnt = 0;
+
+       /* GRC_MISC_CFG core clock reset will clear the memory
+        * enable bit in PCI register 4 and the MSI enable bit
+        * on some chips, so we save relevant registers here.
+        */
+       tg3_save_pci_state(tp);
+
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
+           tg3_flag(tp, 5755_PLUS))
+               tw32(GRC_FASTBOOT_PC, 0);
+
+       /*
+        * We must avoid the readl() that normally takes place.
+        * It locks machines, causes machine checks, and other
+        * fun things.  So, temporarily disable the 5701
+        * hardware workaround, while we do the reset.
+        */
+       write_op = tp->write32;
+       if (write_op == tg3_write_flush_reg32)
+               tp->write32 = tg3_write32;
+
+       /* Prevent the irq handler from reading or writing PCI registers
+        * during chip reset when the memory enable bit in the PCI command
+        * register may be cleared.  The chip does not generate interrupt
+        * at this time, but the irq handler may still be called due to irq
+        * sharing or irqpoll.
+        */
+       tg3_flag_set(tp, CHIP_RESETTING);
+       for (i = 0; i < tp->irq_cnt; i++) {
+               struct tg3_napi *tnapi = &tp->napi[i];
+               if (tnapi->hw_status) {
+                       tnapi->hw_status->status = 0;
+                       tnapi->hw_status->status_tag = 0;
+               }
+               tnapi->last_tag = 0;
+               tnapi->last_irq_tag = 0;
+       }
+       smp_mb();
+
+       for (i = 0; i < tp->irq_cnt; i++)
+               synchronize_irq(tp->napi[i].irq_vec);
+
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
+               val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
+               tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
+       }
+
+       /* do the reset */
+       val = GRC_MISC_CFG_CORECLK_RESET;
+
+       if (tg3_flag(tp, PCI_EXPRESS)) {
+               /* Force PCIe 1.0a mode */
+               if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
+                   !tg3_flag(tp, 57765_PLUS) &&
+                   tr32(TG3_PCIE_PHY_TSTCTL) ==
+                   (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
+                       tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
+
+               if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
+                       tw32(GRC_MISC_CFG, (1 << 29));
+                       val |= (1 << 29);
+               }
+       }
+
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
+               tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
+               tw32(GRC_VCPU_EXT_CTRL,
+                    tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
+       }
+
+       /* Manage gphy power for all CPMU absent PCIe devices. */
+       if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
+               val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
+
+       tw32(GRC_MISC_CFG, val);
+
+       /* restore 5701 hardware bug workaround write method */
+       tp->write32 = write_op;
+
+       /* Unfortunately, we have to delay before the PCI read back.
+        * Some 575X chips even will not respond to a PCI cfg access
+        * when the reset command is given to the chip.
+        *
+        * How do these hardware designers expect things to work
+        * properly if the PCI write is posted for a long period
+        * of time?  It is always necessary to have some method by
+        * which a register read back can occur to push the write
+        * out which does the reset.
+        *
+        * For most tg3 variants the trick below was working.
+        * Ho hum...
+        */
+       udelay(120);
+
+       /* Flush PCI posted writes.  The normal MMIO registers
+        * are inaccessible at this time so this is the only
+        * way to make this reliably (actually, this is no longer
+        * the case, see above).  I tried to use indirect
+        * register read/write but this upset some 5701 variants.
+        */
+       pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
+
+       udelay(120);
+
+       if (tg3_flag(tp, PCI_EXPRESS) && tp->pcie_cap) {
+               u16 val16;
+
+               if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
+                       int i;
+                       u32 cfg_val;
+
+                       /* Wait for link training to complete.  */
+                       for (i = 0; i < 5000; i++)
+                               udelay(100);
+
+                       pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
+                       pci_write_config_dword(tp->pdev, 0xc4,
+                                              cfg_val | (1 << 15));
+               }
+
+               /* Clear the "no snoop" and "relaxed ordering" bits. */
+               pci_read_config_word(tp->pdev,
+                                    tp->pcie_cap + PCI_EXP_DEVCTL,
+                                    &val16);
+               val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
+                          PCI_EXP_DEVCTL_NOSNOOP_EN);
+               /*
+                * Older PCIe devices only support the 128 byte
+                * MPS setting.  Enforce the restriction.
+                */
+               if (!tg3_flag(tp, CPMU_PRESENT))
+                       val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
+               pci_write_config_word(tp->pdev,
+                                     tp->pcie_cap + PCI_EXP_DEVCTL,
+                                     val16);
+
+               pcie_set_readrq(tp->pdev, tp->pcie_readrq);
+
+               /* Clear error status */
+               pci_write_config_word(tp->pdev,
+                                     tp->pcie_cap + PCI_EXP_DEVSTA,
+                                     PCI_EXP_DEVSTA_CED |
+                                     PCI_EXP_DEVSTA_NFED |
+                                     PCI_EXP_DEVSTA_FED |
+                                     PCI_EXP_DEVSTA_URD);
+       }
+
+       tg3_restore_pci_state(tp);
+
+       tg3_flag_clear(tp, CHIP_RESETTING);
+       tg3_flag_clear(tp, ERROR_PROCESSED);
+
+       val = 0;
+       if (tg3_flag(tp, 5780_CLASS))
+               val = tr32(MEMARB_MODE);
+       tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
+
+       if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
+               tg3_stop_fw(tp);
+               tw32(0x5000, 0x400);
+       }
+
+       tw32(GRC_MODE, tp->grc_mode);
+
+       if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
+               val = tr32(0xc4);
+
+               tw32(0xc4, val | (1 << 15));
+       }
+
+       if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
+           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
+               tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
+               if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
+                       tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
+               tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
+       }
+
+       if (tg3_flag(tp, ENABLE_APE))
+               tp->mac_mode = MAC_MODE_APE_TX_EN |
+                              MAC_MODE_APE_RX_EN |
+                              MAC_MODE_TDE_ENABLE;
+
+       if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
+               tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
+               val = tp->mac_mode;
+       } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
+               tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
+               val = tp->mac_mode;
+       } else
+               val = 0;
+
+       tw32_f(MAC_MODE, val);
+       udelay(40);
+
+       tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
+
+       err = tg3_poll_fw(tp);
+       if (err)
+               return err;
+
+       tg3_mdio_start(tp);
+
+       if (tg3_flag(tp, PCI_EXPRESS) &&
+           tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
+           GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
+           !tg3_flag(tp, 57765_PLUS)) {
+               val = tr32(0x7c00);
+
+               tw32(0x7c00, val | (1 << 25));
+       }
+
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
+               val = tr32(TG3_CPMU_CLCK_ORIDE);
+               tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
+       }
+
+       /* Reprobe ASF enable state.  */
+       tg3_flag_clear(tp, ENABLE_ASF);
+       tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
+       tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
+       if (val == NIC_SRAM_DATA_SIG_MAGIC) {
+               u32 nic_cfg;
+
+               tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
+               if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
+                       tg3_flag_set(tp, ENABLE_ASF);
+                       tp->last_event_jiffies = jiffies;
+                       if (tg3_flag(tp, 5750_PLUS))
+                               tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
+               }
+       }
+
+       return 0;
+}
+
+/* tp->lock is held. */
+static void tg3_stop_fw(struct tg3 *tp)
+{
+       if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
+               /* Wait for RX cpu to ACK the previous event. */
+               tg3_wait_for_event_ack(tp);
+
+               tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
+
+               tg3_generate_fw_event(tp);
+
+               /* Wait for RX cpu to ACK this event. */
+               tg3_wait_for_event_ack(tp);
+       }
+}
+
+/* tp->lock is held. */
+static int tg3_halt(struct tg3 *tp, int kind, int silent)
+{
+       int err;
+
+       tg3_stop_fw(tp);
+
+       tg3_write_sig_pre_reset(tp, kind);
+
+       tg3_abort_hw(tp, silent);
+       err = tg3_chip_reset(tp);
+
+       __tg3_set_mac_addr(tp, 0);
+
+       tg3_write_sig_legacy(tp, kind);
+       tg3_write_sig_post_reset(tp, kind);
+
+       if (err)
+               return err;
+
+       return 0;
+}
+
+#define RX_CPU_SCRATCH_BASE    0x30000
+#define RX_CPU_SCRATCH_SIZE    0x04000
+#define TX_CPU_SCRATCH_BASE    0x34000
+#define TX_CPU_SCRATCH_SIZE    0x04000
+
+/* tp->lock is held. */
+static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
+{
+       int i;
+
+       BUG_ON(offset == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
+
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
+               u32 val = tr32(GRC_VCPU_EXT_CTRL);
+
+               tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
+               return 0;
+       }
+       if (offset == RX_CPU_BASE) {
+               for (i = 0; i < 10000; i++) {
+                       tw32(offset + CPU_STATE, 0xffffffff);
+                       tw32(offset + CPU_MODE,  CPU_MODE_HALT);
+                       if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
+                               break;
+               }
+
+               tw32(offset + CPU_STATE, 0xffffffff);
+               tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
+               udelay(10);
+       } else {
+               for (i = 0; i < 10000; i++) {
+                       tw32(offset + CPU_STATE, 0xffffffff);
+                       tw32(offset + CPU_MODE,  CPU_MODE_HALT);
+                       if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
+                               break;
+               }
+       }
+
+       if (i >= 10000) {
+               netdev_err(tp->dev, "%s timed out, %s CPU\n",
+                          __func__, offset == RX_CPU_BASE ? "RX" : "TX");
+               return -ENODEV;
+       }
+
+       /* Clear firmware's nvram arbitration. */
+       if (tg3_flag(tp, NVRAM))
+               tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
+       return 0;
+}
+
+struct fw_info {
+       unsigned int fw_base;
+       unsigned int fw_len;
+       const __be32 *fw_data;
+};
+
+/* tp->lock is held. */
+static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
+                                int cpu_scratch_size, struct fw_info *info)
+{
+       int err, lock_err, i;
+       void (*write_op)(struct tg3 *, u32, u32);
+
+       if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
+               netdev_err(tp->dev,
+                          "%s: Trying to load TX cpu firmware which is 5705\n",
+                          __func__);
+               return -EINVAL;
+       }
+
+       if (tg3_flag(tp, 5705_PLUS))
+               write_op = tg3_write_mem;
+       else
+               write_op = tg3_write_indirect_reg32;
+
+       /* It is possible that bootcode is still loading at this point.
+        * Get the nvram lock first before halting the cpu.
+        */
+       lock_err = tg3_nvram_lock(tp);
+       err = tg3_halt_cpu(tp, cpu_base);
+       if (!lock_err)
+               tg3_nvram_unlock(tp);
+       if (err)
+               goto out;
+
+       for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
+               write_op(tp, cpu_scratch_base + i, 0);
+       tw32(cpu_base + CPU_STATE, 0xffffffff);
+       tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
+       for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
+               write_op(tp, (cpu_scratch_base +
+                             (info->fw_base & 0xffff) +
+                             (i * sizeof(u32))),
+                             be32_to_cpu(info->fw_data[i]));
+
+       err = 0;
+
+out:
+       return err;
+}
+
+/* tp->lock is held. */
+static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
+{
+       struct fw_info info;
+       const __be32 *fw_data;
+       int err, i;
+
+       fw_data = (void *)tp->fw->data;
+
+       /* Firmware blob starts with version numbers, followed by
+          start address and length. We are setting complete length.
+          length = end_address_of_bss - start_address_of_text.
+          Remainder is the blob to be loaded contiguously
+          from start address. */
+
+       info.fw_base = be32_to_cpu(fw_data[1]);
+       info.fw_len = tp->fw->size - 12;
+       info.fw_data = &fw_data[3];
+
+       err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
+                                   RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
+                                   &info);
+       if (err)
+               return err;
+
+       err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
+                                   TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
+                                   &info);
+       if (err)
+               return err;
+
+       /* Now startup only the RX cpu. */
+       tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
+       tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
+
+       for (i = 0; i < 5; i++) {
+               if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
+                       break;
+               tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
+               tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
+               tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
+               udelay(1000);
+       }
+       if (i >= 5) {
+               netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
+                          "should be %08x\n", __func__,
+                          tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
+               return -ENODEV;
+       }
+       tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
+       tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
+
+       return 0;
+}
+
+/* tp->lock is held. */
+static int tg3_load_tso_firmware(struct tg3 *tp)
+{
+       struct fw_info info;
+       const __be32 *fw_data;
+       unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
+       int err, i;
+
+       if (tg3_flag(tp, HW_TSO_1) ||
+           tg3_flag(tp, HW_TSO_2) ||
+           tg3_flag(tp, HW_TSO_3))
+               return 0;
+
+       fw_data = (void *)tp->fw->data;
+
+       /* Firmware blob starts with version numbers, followed by
+          start address and length. We are setting complete length.
+          length = end_address_of_bss - start_address_of_text.
+          Remainder is the blob to be loaded contiguously
+          from start address. */
+
+       info.fw_base = be32_to_cpu(fw_data[1]);
+       cpu_scratch_size = tp->fw_len;
+       info.fw_len = tp->fw->size - 12;
+       info.fw_data = &fw_data[3];
+
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
+               cpu_base = RX_CPU_BASE;
+               cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
+       } else {
+               cpu_base = TX_CPU_BASE;
+               cpu_scratch_base = TX_CPU_SCRATCH_BASE;
+               cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
+       }
+
+       err = tg3_load_firmware_cpu(tp, cpu_base,
+                                   cpu_scratch_base, cpu_scratch_size,
+                                   &info);
+       if (err)
+               return err;
+
+       /* Now startup the cpu. */
+       tw32(cpu_base + CPU_STATE, 0xffffffff);
+       tw32_f(cpu_base + CPU_PC, info.fw_base);
+
+       for (i = 0; i < 5; i++) {
+               if (tr32(cpu_base + CPU_PC) == info.fw_base)
+                       break;
+               tw32(cpu_base + CPU_STATE, 0xffffffff);
+               tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
+               tw32_f(cpu_base + CPU_PC, info.fw_base);
+               udelay(1000);
+       }
+       if (i >= 5) {
+               netdev_err(tp->dev,
+                          "%s fails to set CPU PC, is %08x should be %08x\n",
+                          __func__, tr32(cpu_base + CPU_PC), info.fw_base);
+               return -ENODEV;
+       }
+       tw32(cpu_base + CPU_STATE, 0xffffffff);
+       tw32_f(cpu_base + CPU_MODE,  0x00000000);
+       return 0;
+}
+
+
+static int tg3_set_mac_addr(struct net_device *dev, void *p)
+{
+       struct tg3 *tp = netdev_priv(dev);
+       struct sockaddr *addr = p;
+       int err = 0, skip_mac_1 = 0;
+
+       if (!is_valid_ether_addr(addr->sa_data))
+               return -EINVAL;
+
+       memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
+
+       if (!netif_running(dev))
+               return 0;
+
+       if (tg3_flag(tp, ENABLE_ASF)) {
+               u32 addr0_high, addr0_low, addr1_high, addr1_low;
+
+               addr0_high = tr32(MAC_ADDR_0_HIGH);
+               addr0_low = tr32(MAC_ADDR_0_LOW);
+               addr1_high = tr32(MAC_ADDR_1_HIGH);
+               addr1_low = tr32(MAC_ADDR_1_LOW);
+
+               /* Skip MAC addr 1 if ASF is using it. */
+               if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
+                   !(addr1_high == 0 && addr1_low == 0))
+                       skip_mac_1 = 1;
+       }
+       spin_lock_bh(&tp->lock);
+       __tg3_set_mac_addr(tp, skip_mac_1);
+       spin_unlock_bh(&tp->lock);
+
+       return err;
+}
+
+/* tp->lock is held. */
+static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
+                          dma_addr_t mapping, u32 maxlen_flags,
+                          u32 nic_addr)
+{
+       tg3_write_mem(tp,
+                     (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
+                     ((u64) mapping >> 32));
+       tg3_write_mem(tp,
+                     (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
+                     ((u64) mapping & 0xffffffff));
+       tg3_write_mem(tp,
+                     (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
+                      maxlen_flags);
+
+       if (!tg3_flag(tp, 5705_PLUS))
+               tg3_write_mem(tp,
+                             (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
+                             nic_addr);
+}
+
+static void __tg3_set_rx_mode(struct net_device *);
+static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
+{
+       int i;
+
+       if (!tg3_flag(tp, ENABLE_TSS)) {
+               tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
+               tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
+               tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
+       } else {
+               tw32(HOSTCC_TXCOL_TICKS, 0);
+               tw32(HOSTCC_TXMAX_FRAMES, 0);
+               tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
+       }
+
+       if (!tg3_flag(tp, ENABLE_RSS)) {
+               tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
+               tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
+               tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
+       } else {
+               tw32(HOSTCC_RXCOL_TICKS, 0);
+               tw32(HOSTCC_RXMAX_FRAMES, 0);
+               tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
+       }
+
+       if (!tg3_flag(tp, 5705_PLUS)) {
+               u32 val = ec->stats_block_coalesce_usecs;
+
+               tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
+               tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
+
+               if (!netif_carrier_ok(tp->dev))
+                       val = 0;
+
+               tw32(HOSTCC_STAT_COAL_TICKS, val);
+       }
+
+       for (i = 0; i < tp->irq_cnt - 1; i++) {
+               u32 reg;
+
+               reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
+               tw32(reg, ec->rx_coalesce_usecs);
+               reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
+               tw32(reg, ec->rx_max_coalesced_frames);
+               reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
+               tw32(reg, ec->rx_max_coalesced_frames_irq);
+
+               if (tg3_flag(tp, ENABLE_TSS)) {
+                       reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
+                       tw32(reg, ec->tx_coalesce_usecs);
+                       reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
+                       tw32(reg, ec->tx_max_coalesced_frames);
+                       reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
+                       tw32(reg, ec->tx_max_coalesced_frames_irq);
+               }
+       }
+
+       for (; i < tp->irq_max - 1; i++) {
+               tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
+               tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
+               tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
+
+               if (tg3_flag(tp, ENABLE_TSS)) {
+                       tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
+                       tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
+                       tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
+               }
+       }
+}
+
+/* tp->lock is held. */
+static void tg3_rings_reset(struct tg3 *tp)
+{
+       int i;
+       u32 stblk, txrcb, rxrcb, limit;
+       struct tg3_napi *tnapi = &tp->napi[0];
+
+       /* Disable all transmit rings but the first. */
+       if (!tg3_flag(tp, 5705_PLUS))
+               limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
+       else if (tg3_flag(tp, 5717_PLUS))
+               limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
+       else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
+               limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
+       else
+               limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
+
+       for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
+            txrcb < limit; txrcb += TG3_BDINFO_SIZE)
+               tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
+                             BDINFO_FLAGS_DISABLED);
+
+
+       /* Disable all receive return rings but the first. */
+       if (tg3_flag(tp, 5717_PLUS))
+               limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
+       else if (!tg3_flag(tp, 5705_PLUS))
+               limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
+       else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
+                GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
+               limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
+       else
+               limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
+
+       for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
+            rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
+               tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
+                             BDINFO_FLAGS_DISABLED);
+
+       /* Disable interrupts */
+       tw32_mailbox_f(tp->napi[0].int_mbox, 1);
+
+       /* Zero mailbox registers. */
+       if (tg3_flag(tp, SUPPORT_MSIX)) {
+               for (i = 1; i < tp->irq_max; i++) {
+                       tp->napi[i].tx_prod = 0;
+                       tp->napi[i].tx_cons = 0;
+                       if (tg3_flag(tp, ENABLE_TSS))
+                               tw32_mailbox(tp->napi[i].prodmbox, 0);
+                       tw32_rx_mbox(tp->napi[i].consmbox, 0);
+                       tw32_mailbox_f(tp->napi[i].int_mbox, 1);
+               }
+               if (!tg3_flag(tp, ENABLE_TSS))
+                       tw32_mailbox(tp->napi[0].prodmbox, 0);
+       } else {
+               tp->napi[0].tx_prod = 0;
+               tp->napi[0].tx_cons = 0;
+               tw32_mailbox(tp->napi[0].prodmbox, 0);
+               tw32_rx_mbox(tp->napi[0].consmbox, 0);
+       }
+
+       /* Make sure the NIC-based send BD rings are disabled. */
+       if (!tg3_flag(tp, 5705_PLUS)) {
+               u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
+               for (i = 0; i < 16; i++)
+                       tw32_tx_mbox(mbox + i * 8, 0);
+       }
+
+       txrcb = NIC_SRAM_SEND_RCB;
+       rxrcb = NIC_SRAM_RCV_RET_RCB;
+
+       /* Clear status block in ram. */
+       memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
+
+       /* Set status block DMA address */
+       tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
+            ((u64) tnapi->status_mapping >> 32));
+       tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
+            ((u64) tnapi->status_mapping & 0xffffffff));
+
+       if (tnapi->tx_ring) {
+               tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
+                              (TG3_TX_RING_SIZE <<
+                               BDINFO_FLAGS_MAXLEN_SHIFT),
+                              NIC_SRAM_TX_BUFFER_DESC);
+               txrcb += TG3_BDINFO_SIZE;
+       }
+
+       if (tnapi->rx_rcb) {
+               tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
+                              (tp->rx_ret_ring_mask + 1) <<
+                               BDINFO_FLAGS_MAXLEN_SHIFT, 0);
+               rxrcb += TG3_BDINFO_SIZE;
+       }
+
+       stblk = HOSTCC_STATBLCK_RING1;
+
+       for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
+               u64 mapping = (u64)tnapi->status_mapping;
+               tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
+               tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
+
+               /* Clear status block in ram. */
+               memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
+
+               if (tnapi->tx_ring) {
+                       tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
+                                      (TG3_TX_RING_SIZE <<
+                                       BDINFO_FLAGS_MAXLEN_SHIFT),
+                                      NIC_SRAM_TX_BUFFER_DESC);
+                       txrcb += TG3_BDINFO_SIZE;
+               }
+
+               tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
+                              ((tp->rx_ret_ring_mask + 1) <<
+                               BDINFO_FLAGS_MAXLEN_SHIFT), 0);
+
+               stblk += 8;
+               rxrcb += TG3_BDINFO_SIZE;
+       }
+}
+
+static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
+{
+       u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
+
+       if (!tg3_flag(tp, 5750_PLUS) ||
+           tg3_flag(tp, 5780_CLASS) ||
+           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
+           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
+               bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
+       else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
+                GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
+               bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
+       else
+               bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
+
+       nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
+       host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
+
+       val = min(nic_rep_thresh, host_rep_thresh);
+       tw32(RCVBDI_STD_THRESH, val);
+
+       if (tg3_flag(tp, 57765_PLUS))
+               tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
+
+       if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
+               return;
+
+       if (!tg3_flag(tp, 5705_PLUS))
+               bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
+       else
+               bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717;
+
+       host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
+
+       val = min(bdcache_maxcnt / 2, host_rep_thresh);
+       tw32(RCVBDI_JUMBO_THRESH, val);
+
+       if (tg3_flag(tp, 57765_PLUS))
+               tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
+}
+
+/* tp->lock is held. */
+static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
+{
+       u32 val, rdmac_mode;
+       int i, err, limit;
+       struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
+
+       tg3_disable_ints(tp);
+
+       tg3_stop_fw(tp);
+
+       tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
+
+       if (tg3_flag(tp, INIT_COMPLETE))
+               tg3_abort_hw(tp, 1);
+
+       /* Enable MAC control of LPI */
+       if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
+               tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL,
+                      TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
+                      TG3_CPMU_EEE_LNKIDL_UART_IDL);
+
+               tw32_f(TG3_CPMU_EEE_CTRL,
+                      TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
+
+               val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
+                     TG3_CPMU_EEEMD_LPI_IN_TX |
+                     TG3_CPMU_EEEMD_LPI_IN_RX |
+                     TG3_CPMU_EEEMD_EEE_ENABLE;
+
+               if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
+                       val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
+
+               if (tg3_flag(tp, ENABLE_APE))
+                       val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
+
+               tw32_f(TG3_CPMU_EEE_MODE, val);
+
+               tw32_f(TG3_CPMU_EEE_DBTMR1,
+                      TG3_CPMU_DBTMR1_PCIEXIT_2047US |
+                      TG3_CPMU_DBTMR1_LNKIDLE_2047US);
+
+               tw32_f(TG3_CPMU_EEE_DBTMR2,
+                      TG3_CPMU_DBTMR2_APE_TX_2047US |
+                      TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
+       }
+
+       if (reset_phy)
+               tg3_phy_reset(tp);
+
+       err = tg3_chip_reset(tp);
+       if (err)
+               return err;
+
+       tg3_write_sig_legacy(tp, RESET_KIND_INIT);
+
+       if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
+               val = tr32(TG3_CPMU_CTRL);
+               val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
+               tw32(TG3_CPMU_CTRL, val);
+
+               val = tr32(TG3_CPMU_LSPD_10MB_CLK);
+               val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
+               val |= CPMU_LSPD_10MB_MACCLK_6_25;
+               tw32(TG3_CPMU_LSPD_10MB_CLK, val);
+
+               val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
+               val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
+               val |= CPMU_LNK_AWARE_MACCLK_6_25;
+               tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
+
+               val = tr32(TG3_CPMU_HST_ACC);
+               val &= ~CPMU_HST_ACC_MACCLK_MASK;
+               val |= CPMU_HST_ACC_MACCLK_6_25;
+               tw32(TG3_CPMU_HST_ACC, val);
+       }
+
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
+               val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
+               val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
+                      PCIE_PWR_MGMT_L1_THRESH_4MS;
+               tw32(PCIE_PWR_MGMT_THRESH, val);
+
+               val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
+               tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
+
+               tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
+
+               val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
+               tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
+       }
+
+       if (tg3_flag(tp, L1PLLPD_EN)) {
+               u32 grc_mode = tr32(GRC_MODE);
+
+               /* Access the lower 1K of PL PCIE block registers. */
+               val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
+               tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
+
+               val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
+               tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
+                    val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);