Ported bnx2 driver from Etherboot 5.4.
[people/mcb30/gpxe.git] / src / drivers / net / bnx2.h
1 /* bnx2.h: Broadcom NX2 network driver.
2  *
3  * Copyright (c) 2004, 2005, 2006 Broadcom Corporation
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation.
8  *
9  * Written by: Michael Chan  (mchan@broadcom.com)
10  */
11
12
13 #ifndef BNX2_H
14 #define BNX2_H
15
16 #define L1_CACHE_BYTES 128 /* Rough approximaition of the cache line size */
17 #define L1_CACHE_ALIGN(X) (((X) + L1_CACHE_BYTES-1)&~(L1_CACHE_BYTES -1))
18
19 typedef unsigned long dma_addr_t;
20
21 /* From pci.h */
22 typedef int pci_power_t;
23
24 #define PCI_D0          ((pci_power_t) 0)
25 #define PCI_D1          ((pci_power_t) 1)
26 #define PCI_D2          ((pci_power_t) 2)
27 #define PCI_D3hot       ((pci_power_t) 3)
28 #define PCI_D3cold      ((pci_power_t) 4)
29 #define PCI_UNKNOWN     ((pci_power_t) 5)
30 #define PCI_POWER_ERROR ((pci_power_t) -1)
31
32 /* From pci_regs.h */
33
34 #define  PCI_CAP_ID_PCIX        0x07    /* PCI-X */
35 #define  PCI_X_CMD              2       /* Modes & Features */
36 #define  PCI_X_CMD_ERO          0x0002  /* Enable Relaxed Ordering */
37
38 /* From mii.h */
39
40 /* Indicates what features are advertised by the interface. */
41 #define ADVERTISED_10baseT_Half         (1 << 0)
42 #define ADVERTISED_10baseT_Full         (1 << 1)
43 #define ADVERTISED_100baseT_Half        (1 << 2)
44 #define ADVERTISED_100baseT_Full        (1 << 3)
45 #define ADVERTISED_1000baseT_Half       (1 << 4)
46 #define ADVERTISED_1000baseT_Full       (1 << 5)
47 #define ADVERTISED_Autoneg              (1 << 6)
48 #define ADVERTISED_TP                   (1 << 7)
49 #define ADVERTISED_AUI                  (1 << 8)
50 #define ADVERTISED_MII                  (1 << 9)
51 #define ADVERTISED_FIBRE                (1 << 10)
52 #define ADVERTISED_BNC                  (1 << 11)
53
54 /* The following are all involved in forcing a particular link
55  * mode for the device for setting things.  When getting the
56  * devices settings, these indicate the current mode and whether
57  * it was foced up into this mode or autonegotiated.
58  */
59
60 /* Duplex, half or full. */
61 #define DUPLEX_HALF             0x00
62 #define DUPLEX_FULL             0x01
63 #define DUPLEX_INVALID          0x02
64
65 /* Which connector port. */
66 #define PORT_TP                 0x00
67 #define PORT_AUI                0x01
68 #define PORT_MII                0x02
69 #define PORT_FIBRE              0x03
70 #define PORT_BNC                0x04
71
72 /* Which tranceiver to use. */
73 #define XCVR_INTERNAL           0x00
74 #define XCVR_EXTERNAL           0x01
75 #define XCVR_DUMMY1             0x02
76 #define XCVR_DUMMY2             0x03
77 #define XCVR_DUMMY3             0x04
78
79 /* Enable or disable autonegotiation.  If this is set to enable,
80  * the forced link modes above are completely ignored.
81  */
82 #define AUTONEG_DISABLE         0x00
83 #define AUTONEG_ENABLE          0x01
84
85 /* Wake-On-Lan options. */
86 #define WAKE_PHY                (1 << 0)
87 #define WAKE_UCAST              (1 << 1)
88 #define WAKE_MCAST              (1 << 2)
89 #define WAKE_BCAST              (1 << 3)
90 #define WAKE_ARP                (1 << 4)
91 #define WAKE_MAGIC              (1 << 5)
92 #define WAKE_MAGICSECURE        (1 << 6) /* only meaningful if WAKE_MAGIC */
93
94 /* Generic MII registers. */
95
96 #define MII_BMCR            0x00        /* Basic mode control register */
97 #define MII_BMSR            0x01        /* Basic mode status register  */
98 #define MII_PHYSID1         0x02        /* PHYS ID 1                   */
99 #define MII_PHYSID2         0x03        /* PHYS ID 2                   */
100 #define MII_ADVERTISE       0x04        /* Advertisement control reg   */
101 #define MII_LPA             0x05        /* Link partner ability reg    */
102 #define MII_EXPANSION       0x06        /* Expansion register          */
103 #define MII_CTRL1000        0x09        /* 1000BASE-T control          */
104 #define MII_STAT1000        0x0a        /* 1000BASE-T status           */
105 #define MII_DCOUNTER        0x12        /* Disconnect counter          */
106 #define MII_FCSCOUNTER      0x13        /* False carrier counter       */
107 #define MII_NWAYTEST        0x14        /* N-way auto-neg test reg     */
108 #define MII_RERRCOUNTER     0x15        /* Receive error counter       */
109 #define MII_SREVISION       0x16        /* Silicon revision            */
110 #define MII_RESV1           0x17        /* Reserved...                 */
111 #define MII_LBRERROR        0x18        /* Lpback, rx, bypass error    */
112 #define MII_PHYADDR         0x19        /* PHY address                 */
113 #define MII_RESV2           0x1a        /* Reserved...                 */
114 #define MII_TPISTATUS       0x1b        /* TPI status for 10mbps       */
115 #define MII_NCONFIG         0x1c        /* Network interface config    */
116
117 /* Basic mode control register. */
118 #define BMCR_RESV               0x007f  /* Unused...                   */
119 #define BMCR_SPEED1000          0x0040  /* MSB of Speed (1000)         */
120 #define BMCR_CTST               0x0080  /* Collision test              */
121 #define BMCR_FULLDPLX           0x0100  /* Full duplex                 */
122 #define BMCR_ANRESTART          0x0200  /* Auto negotiation restart    */
123 #define BMCR_ISOLATE            0x0400  /* Disconnect DP83840 from MII */
124 #define BMCR_PDOWN              0x0800  /* Powerdown the DP83840       */
125 #define BMCR_ANENABLE           0x1000  /* Enable auto negotiation     */
126 #define BMCR_SPEED100           0x2000  /* Select 100Mbps              */
127 #define BMCR_LOOPBACK           0x4000  /* TXD loopback bits           */
128 #define BMCR_RESET              0x8000  /* Reset the DP83840           */
129
130 /* Basic mode status register. */
131 #define BMSR_ERCAP              0x0001  /* Ext-reg capability          */
132 #define BMSR_JCD                0x0002  /* Jabber detected             */
133 #define BMSR_LSTATUS            0x0004  /* Link status                 */
134 #define BMSR_ANEGCAPABLE        0x0008  /* Able to do auto-negotiation */
135 #define BMSR_RFAULT             0x0010  /* Remote fault detected       */
136 #define BMSR_ANEGCOMPLETE       0x0020  /* Auto-negotiation complete   */
137 #define BMSR_RESV               0x07c0  /* Unused...                   */
138 #define BMSR_10HALF             0x0800  /* Can do 10mbps, half-duplex  */
139 #define BMSR_10FULL             0x1000  /* Can do 10mbps, full-duplex  */
140 #define BMSR_100HALF            0x2000  /* Can do 100mbps, half-duplex */
141 #define BMSR_100FULL            0x4000  /* Can do 100mbps, full-duplex */
142 #define BMSR_100BASE4           0x8000  /* Can do 100mbps, 4k packets  */
143
144 /* Advertisement control register. */
145 #define ADVERTISE_SLCT          0x001f  /* Selector bits               */
146 #define ADVERTISE_CSMA          0x0001  /* Only selector supported     */
147 #define ADVERTISE_10HALF        0x0020  /* Try for 10mbps half-duplex  */
148 #define ADVERTISE_10FULL        0x0040  /* Try for 10mbps full-duplex  */
149 #define ADVERTISE_100HALF       0x0080  /* Try for 100mbps half-duplex */
150 #define ADVERTISE_100FULL       0x0100  /* Try for 100mbps full-duplex */
151 #define ADVERTISE_100BASE4      0x0200  /* Try for 100mbps 4k packets  */
152 #define ADVERTISE_RESV          0x1c00  /* Unused...                   */
153 #define ADVERTISE_RFAULT        0x2000  /* Say we can detect faults    */
154 #define ADVERTISE_LPACK         0x4000  /* Ack link partners response  */
155 #define ADVERTISE_NPAGE         0x8000  /* Next page bit               */
156 #define ADVERTISE_1000XFULL     0x0020  /* Try for 1000BASE-X full-duplex */
157 #define ADVERTISE_10FULL        0x0040  /* Try for 10mbps full-duplex  */
158 #define ADVERTISE_1000XHALF     0x0040  /* Try for 1000BASE-X half-duplex */
159 #define ADVERTISE_1000XPAUSE    0x0080  /* Try for 1000BASE-X pause    */
160 #define ADVERTISE_PAUSE_CAP     0x0400  /* Try for pause               */
161 #define ADVERTISE_1000XPSE_ASYM 0x0100  /* Try for 1000BASE-X asym pause */
162 #define ADVERTISE_PAUSE_ASYM    0x0800  /* Try for asymetric pause     */
163
164 #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
165                         ADVERTISE_CSMA)
166 #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
167                        ADVERTISE_100HALF | ADVERTISE_100FULL)
168
169 /* Link partner ability register. */
170 #define LPA_SLCT                0x001f  /* Same as advertise selector  */
171 #define LPA_10HALF              0x0020  /* Can do 10mbps half-duplex   */
172 #define LPA_10FULL              0x0040  /* Can do 10mbps full-duplex   */
173 #define LPA_100HALF             0x0080  /* Can do 100mbps half-duplex  */
174 #define LPA_100FULL             0x0100  /* Can do 100mbps full-duplex  */
175 #define LPA_100BASE4            0x0200  /* Can do 100mbps 4k packets   */
176 #define LPA_RESV                0x1c00  /* Unused...                   */
177 #define LPA_RFAULT              0x2000  /* Link partner faulted        */
178 #define LPA_LPACK               0x4000  /* Link partner acked us       */
179 #define LPA_NPAGE               0x8000  /* Next page bit               */
180
181 #define LPA_DUPLEX              (LPA_10FULL | LPA_100FULL)
182 #define LPA_100                 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
183
184 /* Expansion register for auto-negotiation. */
185 #define EXPANSION_NWAY          0x0001  /* Can do N-way auto-nego      */
186 #define EXPANSION_LCWP          0x0002  /* Got new RX page code word   */
187 #define EXPANSION_ENABLENPAGE   0x0004  /* This enables npage words    */
188 #define EXPANSION_NPCAPABLE     0x0008  /* Link partner supports npage */
189 #define EXPANSION_MFAULTS       0x0010  /* Multiple faults detected    */
190 #define EXPANSION_RESV          0xffe0  /* Unused...                   */
191
192 /* 1000BASE-T Control register */
193 #define ADVERTISE_1000FULL      0x0200  /* Advertise 1000BASE-T full duplex */
194 #define ADVERTISE_1000HALF      0x0100  /* Advertise 1000BASE-T half duplex */
195
196 /* N-way test register. */
197 #define NWAYTEST_RESV1          0x00ff  /* Unused...                   */
198 #define NWAYTEST_LOOPBACK       0x0100  /* Enable loopback for N-way   */
199 #define NWAYTEST_RESV2          0xfe00  /* Unused...                   */
200
201 /* The following are all involved in forcing a particular link
202  *  * mode for the device for setting things.  When getting the
203  *   * devices settings, these indicate the current mode and whether
204  *    * it was foced up into this mode or autonegotiated.
205  *     */
206
207 /* The forced speed, 10Mb, 100Mb, gigabit. */
208 #define SPEED_10                10
209 #define SPEED_100               100
210 #define SPEED_1000              1000
211 #define SPEED_2500              2500
212 #define SPEED_INVALID           0 /* XXX was 3 */
213
214
215 /* Duplex, half or full. */
216 #define DUPLEX_HALF             0x00
217 #define DUPLEX_FULL             0x01
218 #define DUPLEX_INVALID          0x02
219
220 /* Which connector port. */
221 #define PORT_TP                 0x00
222 #define PORT_AUI                0x01
223 #define PORT_MII                0x02
224 #define PORT_FIBRE              0x03
225 #define PORT_BNC                0x04
226
227 /* Which tranceiver to use. */
228 #define XCVR_INTERNAL           0x00
229 #define XCVR_EXTERNAL           0x01
230 #define XCVR_DUMMY1             0x02
231 #define XCVR_DUMMY2             0x03
232 #define XCVR_DUMMY3             0x04
233
234 /* Enable or disable autonegotiation.  If this is set to enable,
235  *  * the forced link modes above are completely ignored.
236  *   */
237 #define AUTONEG_DISABLE         0x00
238 #define AUTONEG_ENABLE          0x01
239
240 /* Wake-On-Lan options. */
241 #define WAKE_PHY                (1 << 0)
242 #define WAKE_UCAST              (1 << 1)
243 #define WAKE_MCAST              (1 << 2)
244 #define WAKE_BCAST              (1 << 3)
245 #define WAKE_ARP                (1 << 4)
246 #define WAKE_MAGIC              (1 << 5)
247 #define WAKE_MAGICSECURE        (1 << 6) /* only meaningful if WAKE_MAGIC */
248
249 /* Hardware data structures and register definitions automatically
250  * generated from RTL code. Do not modify.
251  */
252
253 /*
254  *  tx_bd definition
255  */
256 struct tx_bd {
257         u32 tx_bd_haddr_hi;
258         u32 tx_bd_haddr_lo;                                   
259         u32 tx_bd_mss_nbytes;                                     
260         u32 tx_bd_vlan_tag_flags;                                      
261                 #define TX_BD_FLAGS_CONN_FAULT          (1<<0)
262                 #define TX_BD_FLAGS_TCP_UDP_CKSUM       (1<<1)
263                 #define TX_BD_FLAGS_IP_CKSUM            (1<<2)
264                 #define TX_BD_FLAGS_VLAN_TAG            (1<<3)
265                 #define TX_BD_FLAGS_COAL_NOW            (1<<4)
266                 #define TX_BD_FLAGS_DONT_GEN_CRC        (1<<5)
267                 #define TX_BD_FLAGS_END                 (1<<6)
268                 #define TX_BD_FLAGS_START               (1<<7)
269                 #define TX_BD_FLAGS_SW_OPTION_WORD      (0x1f<<8)
270                 #define TX_BD_FLAGS_SW_FLAGS            (1<<13)
271                 #define TX_BD_FLAGS_SW_SNAP             (1<<14)
272                 #define TX_BD_FLAGS_SW_LSO              (1<<15)
273
274 };
275
276
277 /*
278  *  rx_bd definition
279  */
280 struct rx_bd {
281         u32 rx_bd_haddr_hi;
282         u32 rx_bd_haddr_lo;
283         u32 rx_bd_len;
284         u32 rx_bd_flags;
285                 #define RX_BD_FLAGS_NOPUSH              (1<<0)
286                 #define RX_BD_FLAGS_DUMMY               (1<<1)
287                 #define RX_BD_FLAGS_END                 (1<<2)
288                 #define RX_BD_FLAGS_START               (1<<3)
289
290 };
291
292
293 /*
294  *  status_block definition
295  */
296 struct status_block {
297         u32 status_attn_bits;
298                 #define STATUS_ATTN_BITS_LINK_STATE             (1L<<0)
299                 #define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT     (1L<<1)
300                 #define STATUS_ATTN_BITS_TX_BD_READ_ABORT       (1L<<2)
301                 #define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT      (1L<<3)
302                 #define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT     (1L<<4)
303                 #define STATUS_ATTN_BITS_TX_DMA_ABORT           (1L<<5)
304                 #define STATUS_ATTN_BITS_TX_PATCHUP_ABORT       (1L<<6)
305                 #define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT     (1L<<7)
306                 #define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT    (1L<<8)
307                 #define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT        (1L<<9)
308                 #define STATUS_ATTN_BITS_RX_MBUF_ABORT          (1L<<10)
309                 #define STATUS_ATTN_BITS_RX_LOOKUP_ABORT        (1L<<11)
310                 #define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT     (1L<<12)
311                 #define STATUS_ATTN_BITS_RX_V2P_ABORT           (1L<<13)
312                 #define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT      (1L<<14)
313                 #define STATUS_ATTN_BITS_RX_DMA_ABORT           (1L<<15)
314                 #define STATUS_ATTN_BITS_COMPLETION_ABORT       (1L<<16)
315                 #define STATUS_ATTN_BITS_HOST_COALESCE_ABORT    (1L<<17)
316                 #define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT    (1L<<18)
317                 #define STATUS_ATTN_BITS_CONTEXT_ABORT          (1L<<19)
318                 #define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT    (1L<<20)
319                 #define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT    (1L<<21)
320                 #define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT   (1L<<22)
321                 #define STATUS_ATTN_BITS_MAC_ABORT              (1L<<23)
322                 #define STATUS_ATTN_BITS_TIMER_ABORT            (1L<<24)
323                 #define STATUS_ATTN_BITS_DMAE_ABORT             (1L<<25)
324                 #define STATUS_ATTN_BITS_FLSH_ABORT             (1L<<26)
325                 #define STATUS_ATTN_BITS_GRC_ABORT              (1L<<27)
326                 #define STATUS_ATTN_BITS_PARITY_ERROR           (1L<<31)
327
328         u32 status_attn_bits_ack;
329 #if __BYTE_ORDER == __BIG_ENDIAN
330         u16 status_tx_quick_consumer_index0;
331         u16 status_tx_quick_consumer_index1;
332         u16 status_tx_quick_consumer_index2;
333         u16 status_tx_quick_consumer_index3;
334         u16 status_rx_quick_consumer_index0;
335         u16 status_rx_quick_consumer_index1;
336         u16 status_rx_quick_consumer_index2;
337         u16 status_rx_quick_consumer_index3;
338         u16 status_rx_quick_consumer_index4;
339         u16 status_rx_quick_consumer_index5;
340         u16 status_rx_quick_consumer_index6;
341         u16 status_rx_quick_consumer_index7;
342         u16 status_rx_quick_consumer_index8;
343         u16 status_rx_quick_consumer_index9;
344         u16 status_rx_quick_consumer_index10;
345         u16 status_rx_quick_consumer_index11;
346         u16 status_rx_quick_consumer_index12;
347         u16 status_rx_quick_consumer_index13;
348         u16 status_rx_quick_consumer_index14;
349         u16 status_rx_quick_consumer_index15;
350         u16 status_completion_producer_index;
351         u16 status_cmd_consumer_index;
352         u16 status_idx;
353         u16 status_unused;
354 #elif __BYTE_ORDER == __LITTLE_ENDIAN
355         u16 status_tx_quick_consumer_index1;
356         u16 status_tx_quick_consumer_index0;
357         u16 status_tx_quick_consumer_index3;
358         u16 status_tx_quick_consumer_index2;
359         u16 status_rx_quick_consumer_index1;
360         u16 status_rx_quick_consumer_index0;
361         u16 status_rx_quick_consumer_index3;
362         u16 status_rx_quick_consumer_index2;
363         u16 status_rx_quick_consumer_index5;
364         u16 status_rx_quick_consumer_index4;
365         u16 status_rx_quick_consumer_index7;
366         u16 status_rx_quick_consumer_index6;
367         u16 status_rx_quick_consumer_index9;
368         u16 status_rx_quick_consumer_index8;
369         u16 status_rx_quick_consumer_index11;
370         u16 status_rx_quick_consumer_index10;
371         u16 status_rx_quick_consumer_index13;
372         u16 status_rx_quick_consumer_index12;
373         u16 status_rx_quick_consumer_index15;
374         u16 status_rx_quick_consumer_index14;
375         u16 status_cmd_consumer_index;
376         u16 status_completion_producer_index;
377         u16 status_unused;
378         u16 status_idx;
379 #endif
380 };
381
382
383 /*
384  *  statistics_block definition
385  */
386 struct statistics_block {
387         u32 stat_IfHCInOctets_hi;
388         u32 stat_IfHCInOctets_lo;
389         u32 stat_IfHCInBadOctets_hi;
390         u32 stat_IfHCInBadOctets_lo;
391         u32 stat_IfHCOutOctets_hi;
392         u32 stat_IfHCOutOctets_lo;
393         u32 stat_IfHCOutBadOctets_hi;
394         u32 stat_IfHCOutBadOctets_lo;
395         u32 stat_IfHCInUcastPkts_hi;
396         u32 stat_IfHCInUcastPkts_lo;
397         u32 stat_IfHCInMulticastPkts_hi;
398         u32 stat_IfHCInMulticastPkts_lo;
399         u32 stat_IfHCInBroadcastPkts_hi;
400         u32 stat_IfHCInBroadcastPkts_lo;
401         u32 stat_IfHCOutUcastPkts_hi;
402         u32 stat_IfHCOutUcastPkts_lo;
403         u32 stat_IfHCOutMulticastPkts_hi;
404         u32 stat_IfHCOutMulticastPkts_lo;
405         u32 stat_IfHCOutBroadcastPkts_hi;
406         u32 stat_IfHCOutBroadcastPkts_lo;
407         u32 stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
408         u32 stat_Dot3StatsCarrierSenseErrors;
409         u32 stat_Dot3StatsFCSErrors;
410         u32 stat_Dot3StatsAlignmentErrors;
411         u32 stat_Dot3StatsSingleCollisionFrames;
412         u32 stat_Dot3StatsMultipleCollisionFrames;
413         u32 stat_Dot3StatsDeferredTransmissions;
414         u32 stat_Dot3StatsExcessiveCollisions;
415         u32 stat_Dot3StatsLateCollisions;
416         u32 stat_EtherStatsCollisions;
417         u32 stat_EtherStatsFragments;
418         u32 stat_EtherStatsJabbers;
419         u32 stat_EtherStatsUndersizePkts;
420         u32 stat_EtherStatsOverrsizePkts;
421         u32 stat_EtherStatsPktsRx64Octets;
422         u32 stat_EtherStatsPktsRx65Octetsto127Octets;
423         u32 stat_EtherStatsPktsRx128Octetsto255Octets;
424         u32 stat_EtherStatsPktsRx256Octetsto511Octets;
425         u32 stat_EtherStatsPktsRx512Octetsto1023Octets;
426         u32 stat_EtherStatsPktsRx1024Octetsto1522Octets;
427         u32 stat_EtherStatsPktsRx1523Octetsto9022Octets;
428         u32 stat_EtherStatsPktsTx64Octets;
429         u32 stat_EtherStatsPktsTx65Octetsto127Octets;
430         u32 stat_EtherStatsPktsTx128Octetsto255Octets;
431         u32 stat_EtherStatsPktsTx256Octetsto511Octets;
432         u32 stat_EtherStatsPktsTx512Octetsto1023Octets;
433         u32 stat_EtherStatsPktsTx1024Octetsto1522Octets;
434         u32 stat_EtherStatsPktsTx1523Octetsto9022Octets;
435         u32 stat_XonPauseFramesReceived;
436         u32 stat_XoffPauseFramesReceived;
437         u32 stat_OutXonSent;
438         u32 stat_OutXoffSent;
439         u32 stat_FlowControlDone;
440         u32 stat_MacControlFramesReceived;
441         u32 stat_XoffStateEntered;
442         u32 stat_IfInFramesL2FilterDiscards;
443         u32 stat_IfInRuleCheckerDiscards;
444         u32 stat_IfInFTQDiscards;
445         u32 stat_IfInMBUFDiscards;
446         u32 stat_IfInRuleCheckerP4Hit;
447         u32 stat_CatchupInRuleCheckerDiscards;
448         u32 stat_CatchupInFTQDiscards;
449         u32 stat_CatchupInMBUFDiscards;
450         u32 stat_CatchupInRuleCheckerP4Hit;
451         u32 stat_GenStat00;
452         u32 stat_GenStat01;
453         u32 stat_GenStat02;
454         u32 stat_GenStat03;
455         u32 stat_GenStat04;
456         u32 stat_GenStat05;
457         u32 stat_GenStat06;
458         u32 stat_GenStat07;
459         u32 stat_GenStat08;
460         u32 stat_GenStat09;
461         u32 stat_GenStat10;
462         u32 stat_GenStat11;
463         u32 stat_GenStat12;
464         u32 stat_GenStat13;
465         u32 stat_GenStat14;
466         u32 stat_GenStat15;
467 };
468
469
470 /*
471  *  l2_fhdr definition
472  */
473 struct l2_fhdr {
474         u32 l2_fhdr_status;
475                 #define L2_FHDR_STATUS_RULE_CLASS       (0x7<<0)
476                 #define L2_FHDR_STATUS_RULE_P2          (1<<3)
477                 #define L2_FHDR_STATUS_RULE_P3          (1<<4)
478                 #define L2_FHDR_STATUS_RULE_P4          (1<<5)
479                 #define L2_FHDR_STATUS_L2_VLAN_TAG      (1<<6)
480                 #define L2_FHDR_STATUS_L2_LLC_SNAP      (1<<7)
481                 #define L2_FHDR_STATUS_RSS_HASH         (1<<8)
482                 #define L2_FHDR_STATUS_IP_DATAGRAM      (1<<13)
483                 #define L2_FHDR_STATUS_TCP_SEGMENT      (1<<14)
484                 #define L2_FHDR_STATUS_UDP_DATAGRAM     (1<<15)
485
486                 #define L2_FHDR_ERRORS_BAD_CRC          (1<<17)
487                 #define L2_FHDR_ERRORS_PHY_DECODE       (1<<18)
488                 #define L2_FHDR_ERRORS_ALIGNMENT        (1<<19)
489                 #define L2_FHDR_ERRORS_TOO_SHORT        (1<<20)
490                 #define L2_FHDR_ERRORS_GIANT_FRAME      (1<<21)
491                 #define L2_FHDR_ERRORS_TCP_XSUM         (1<<28)
492                 #define L2_FHDR_ERRORS_UDP_XSUM         (1<<31)
493
494         u32 l2_fhdr_hash;
495 #if __BYTE_ORDER == __BIG_ENDIAN
496         u16 l2_fhdr_pkt_len;
497         u16 l2_fhdr_vlan_tag;
498         u16 l2_fhdr_ip_xsum;
499         u16 l2_fhdr_tcp_udp_xsum;
500 #elif __BYTE_ORDER == __LITTLE_ENDIAN
501         u16 l2_fhdr_vlan_tag;
502         u16 l2_fhdr_pkt_len;
503         u16 l2_fhdr_tcp_udp_xsum;
504         u16 l2_fhdr_ip_xsum;
505 #endif
506 };
507
508
509 /*
510  *  l2_context definition
511  */
512 #define BNX2_L2CTX_TYPE                                 0x00000000
513 #define BNX2_L2CTX_TYPE_SIZE_L2                          ((0xc0/0x20)<<16)
514 #define BNX2_L2CTX_TYPE_TYPE                             (0xf<<28)
515 #define BNX2_L2CTX_TYPE_TYPE_EMPTY                       (0<<28)
516 #define BNX2_L2CTX_TYPE_TYPE_L2                          (1<<28)
517
518 #define BNX2_L2CTX_TX_HOST_BIDX                         0x00000088
519 #define BNX2_L2CTX_EST_NBD                              0x00000088
520 #define BNX2_L2CTX_CMD_TYPE                             0x00000088
521 #define BNX2_L2CTX_CMD_TYPE_TYPE                         (0xf<<24)
522 #define BNX2_L2CTX_CMD_TYPE_TYPE_L2                      (0<<24)
523 #define BNX2_L2CTX_CMD_TYPE_TYPE_TCP                     (1<<24)
524
525 #define BNX2_L2CTX_TX_HOST_BSEQ                         0x00000090
526 #define BNX2_L2CTX_TSCH_BSEQ                            0x00000094
527 #define BNX2_L2CTX_TBDR_BSEQ                            0x00000098
528 #define BNX2_L2CTX_TBDR_BOFF                            0x0000009c
529 #define BNX2_L2CTX_TBDR_BIDX                            0x0000009c
530 #define BNX2_L2CTX_TBDR_BHADDR_HI                       0x000000a0
531 #define BNX2_L2CTX_TBDR_BHADDR_LO                       0x000000a4
532 #define BNX2_L2CTX_TXP_BOFF                             0x000000a8
533 #define BNX2_L2CTX_TXP_BIDX                             0x000000a8
534 #define BNX2_L2CTX_TXP_BSEQ                             0x000000ac
535
536
537 /*
538  *  l2_bd_chain_context definition
539  */
540 #define BNX2_L2CTX_BD_PRE_READ                          0x00000000
541 #define BNX2_L2CTX_CTX_SIZE                             0x00000000
542 #define BNX2_L2CTX_CTX_TYPE                             0x00000000
543 #define BNX2_L2CTX_CTX_TYPE_SIZE_L2                      ((0x20/20)<<16)
544 #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE              (0xf<<28)
545 #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED    (0<<28)
546 #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE        (1<<28)
547
548 #define BNX2_L2CTX_HOST_BDIDX                           0x00000004
549 #define BNX2_L2CTX_HOST_BSEQ                            0x00000008
550 #define BNX2_L2CTX_NX_BSEQ                              0x0000000c
551 #define BNX2_L2CTX_NX_BDHADDR_HI                        0x00000010
552 #define BNX2_L2CTX_NX_BDHADDR_LO                        0x00000014
553 #define BNX2_L2CTX_NX_BDIDX                             0x00000018
554
555
556 /*
557  *  pci_config_l definition
558  *  offset: 0000
559  */
560 #define BNX2_PCICFG_MISC_CONFIG                         0x00000068
561 #define BNX2_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP         (1L<<2)
562 #define BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP      (1L<<3)
563 #define BNX2_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA            (1L<<5)
564 #define BNX2_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP     (1L<<6)
565 #define BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA           (1L<<7)
566 #define BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ             (1L<<8)
567 #define BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY             (1L<<9)
568 #define BNX2_PCICFG_MISC_CONFIG_ASIC_METAL_REV           (0xffL<<16)
569 #define BNX2_PCICFG_MISC_CONFIG_ASIC_BASE_REV            (0xfL<<24)
570 #define BNX2_PCICFG_MISC_CONFIG_ASIC_ID                  (0xfL<<28)
571
572 #define BNX2_PCICFG_MISC_STATUS                         0x0000006c
573 #define BNX2_PCICFG_MISC_STATUS_INTA_VALUE               (1L<<0)
574 #define BNX2_PCICFG_MISC_STATUS_32BIT_DET                (1L<<1)
575 #define BNX2_PCICFG_MISC_STATUS_M66EN                    (1L<<2)
576 #define BNX2_PCICFG_MISC_STATUS_PCIX_DET                 (1L<<3)
577 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED               (0x3L<<4)
578 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_66            (0L<<4)
579 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_100           (1L<<4)
580 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_133           (2L<<4)
581 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE      (3L<<4)
582
583 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS              0x00000070
584 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET       (0xfL<<0)
585 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ         (0L<<0)
586 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ         (1L<<0)
587 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ         (2L<<0)
588 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ         (3L<<0)
589 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ         (4L<<0)
590 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ         (5L<<0)
591 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ         (6L<<0)
592 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ        (7L<<0)
593 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW   (0xfL<<0)
594 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE      (1L<<6)
595 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT  (1L<<7)
596 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC      (0x7L<<8)
597 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF        (0L<<8)
598 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12   (1L<<8)
599 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6    (2L<<8)
600 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62   (4L<<8)
601 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PLAY_DEAD     (1L<<11)
602 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED    (0xfL<<12)
603 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100        (0L<<12)
604 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80         (1L<<12)
605 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50         (2L<<12)
606 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40         (4L<<12)
607 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25         (8L<<12)
608 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP     (1L<<16)
609 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_PLL_STOP  (1L<<17)
610 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18   (1L<<18)
611 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_USE_SPD_DET   (1L<<19)
612 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED      (0xfffL<<20)
613
614 #define BNX2_PCICFG_REG_WINDOW_ADDRESS                  0x00000078
615 #define BNX2_PCICFG_REG_WINDOW                          0x00000080
616 #define BNX2_PCICFG_INT_ACK_CMD                         0x00000084
617 #define BNX2_PCICFG_INT_ACK_CMD_INDEX                    (0xffffL<<0)
618 #define BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID              (1L<<16)
619 #define BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM         (1L<<17)
620 #define BNX2_PCICFG_INT_ACK_CMD_MASK_INT                 (1L<<18)
621
622 #define BNX2_PCICFG_STATUS_BIT_SET_CMD                  0x00000088
623 #define BNX2_PCICFG_STATUS_BIT_CLEAR_CMD                0x0000008c
624 #define BNX2_PCICFG_MAILBOX_QUEUE_ADDR                  0x00000090
625 #define BNX2_PCICFG_MAILBOX_QUEUE_DATA                  0x00000094
626
627
628 /*
629  *  pci_reg definition
630  *  offset: 0x400
631  */
632 #define BNX2_PCI_GRC_WINDOW_ADDR                        0x00000400
633 #define BNX2_PCI_GRC_WINDOW_ADDR_PCI_GRC_WINDOW_ADDR_VALUE       (0x3ffffL<<8)
634
635 #define BNX2_PCI_CONFIG_1                               0x00000404
636 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY                  (0x7L<<8)
637 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_OFF              (0L<<8)
638 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_16               (1L<<8)
639 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_32               (2L<<8)
640 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_64               (3L<<8)
641 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_128              (4L<<8)
642 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_256              (5L<<8)
643 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_512              (6L<<8)
644 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_1024             (7L<<8)
645 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY                 (0x7L<<11)
646 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_OFF             (0L<<11)
647 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_16              (1L<<11)
648 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_32              (2L<<11)
649 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_64              (3L<<11)
650 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_128             (4L<<11)
651 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_256             (5L<<11)
652 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_512             (6L<<11)
653 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_1024            (7L<<11)
654
655 #define BNX2_PCI_CONFIG_2                               0x00000408
656 #define BNX2_PCI_CONFIG_2_BAR1_SIZE                      (0xfL<<0)
657 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_DISABLED             (0L<<0)
658 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_64K                  (1L<<0)
659 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_128K                 (2L<<0)
660 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_256K                 (3L<<0)
661 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_512K                 (4L<<0)
662 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_1M                   (5L<<0)
663 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_2M                   (6L<<0)
664 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_4M                   (7L<<0)
665 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_8M                   (8L<<0)
666 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_16M                  (9L<<0)
667 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_32M                  (10L<<0)
668 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_64M                  (11L<<0)
669 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_128M                 (12L<<0)
670 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_256M                 (13L<<0)
671 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_512M                 (14L<<0)
672 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_1G                   (15L<<0)
673 #define BNX2_PCI_CONFIG_2_BAR1_64ENA                     (1L<<4)
674 #define BNX2_PCI_CONFIG_2_EXP_ROM_RETRY                  (1L<<5)
675 #define BNX2_PCI_CONFIG_2_CFG_CYCLE_RETRY                (1L<<6)
676 #define BNX2_PCI_CONFIG_2_FIRST_CFG_DONE                 (1L<<7)
677 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE                   (0xffL<<8)
678 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED          (0L<<8)
679 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_1K                (1L<<8)
680 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_2K                (2L<<8)
681 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_4K                (3L<<8)
682 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_8K                (4L<<8)
683 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_16K               (5L<<8)
684 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_32K               (6L<<8)
685 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_64K               (7L<<8)
686 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_128K              (8L<<8)
687 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_256K              (9L<<8)
688 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_512K              (10L<<8)
689 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_1M                (11L<<8)
690 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_2M                (12L<<8)
691 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_4M                (13L<<8)
692 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_8M                (14L<<8)
693 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_16M               (15L<<8)
694 #define BNX2_PCI_CONFIG_2_MAX_SPLIT_LIMIT                (0x1fL<<16)
695 #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT                 (0x3L<<21)
696 #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_512             (0L<<21)
697 #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_1K              (1L<<21)
698 #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_2K              (2L<<21)
699 #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_4K              (3L<<21)
700 #define BNX2_PCI_CONFIG_2_FORCE_32_BIT_MSTR              (1L<<23)
701 #define BNX2_PCI_CONFIG_2_FORCE_32_BIT_TGT               (1L<<24)
702 #define BNX2_PCI_CONFIG_2_KEEP_REQ_ASSERT                (1L<<25)
703
704 #define BNX2_PCI_CONFIG_3                               0x0000040c
705 #define BNX2_PCI_CONFIG_3_STICKY_BYTE                    (0xffL<<0)
706 #define BNX2_PCI_CONFIG_3_FORCE_PME                      (1L<<24)
707 #define BNX2_PCI_CONFIG_3_PME_STATUS                     (1L<<25)
708 #define BNX2_PCI_CONFIG_3_PME_ENABLE                     (1L<<26)
709 #define BNX2_PCI_CONFIG_3_PM_STATE                       (0x3L<<27)
710 #define BNX2_PCI_CONFIG_3_VAUX_PRESET                    (1L<<30)
711 #define BNX2_PCI_CONFIG_3_PCI_POWER                      (1L<<31)
712
713 #define BNX2_PCI_PM_DATA_A                              0x00000410
714 #define BNX2_PCI_PM_DATA_A_PM_DATA_0_PRG                 (0xffL<<0)
715 #define BNX2_PCI_PM_DATA_A_PM_DATA_1_PRG                 (0xffL<<8)
716 #define BNX2_PCI_PM_DATA_A_PM_DATA_2_PRG                 (0xffL<<16)
717 #define BNX2_PCI_PM_DATA_A_PM_DATA_3_PRG                 (0xffL<<24)
718
719 #define BNX2_PCI_PM_DATA_B                              0x00000414
720 #define BNX2_PCI_PM_DATA_B_PM_DATA_4_PRG                 (0xffL<<0)
721 #define BNX2_PCI_PM_DATA_B_PM_DATA_5_PRG                 (0xffL<<8)
722 #define BNX2_PCI_PM_DATA_B_PM_DATA_6_PRG                 (0xffL<<16)
723 #define BNX2_PCI_PM_DATA_B_PM_DATA_7_PRG                 (0xffL<<24)
724
725 #define BNX2_PCI_SWAP_DIAG0                             0x00000418
726 #define BNX2_PCI_SWAP_DIAG1                             0x0000041c
727 #define BNX2_PCI_EXP_ROM_ADDR                           0x00000420
728 #define BNX2_PCI_EXP_ROM_ADDR_ADDRESS                    (0x3fffffL<<2)
729 #define BNX2_PCI_EXP_ROM_ADDR_REQ                        (1L<<31)
730
731 #define BNX2_PCI_EXP_ROM_DATA                           0x00000424
732 #define BNX2_PCI_VPD_INTF                               0x00000428
733 #define BNX2_PCI_VPD_INTF_INTF_REQ                       (1L<<0)
734
735 #define BNX2_PCI_VPD_ADDR_FLAG                          0x0000042c
736 #define BNX2_PCI_VPD_ADDR_FLAG_ADDRESS                   (0x1fff<<2)
737 #define BNX2_PCI_VPD_ADDR_FLAG_WR                        (1<<15)
738
739 #define BNX2_PCI_VPD_DATA                               0x00000430
740 #define BNX2_PCI_ID_VAL1                                0x00000434
741 #define BNX2_PCI_ID_VAL1_DEVICE_ID                       (0xffffL<<0)
742 #define BNX2_PCI_ID_VAL1_VENDOR_ID                       (0xffffL<<16)
743
744 #define BNX2_PCI_ID_VAL2                                0x00000438
745 #define BNX2_PCI_ID_VAL2_SUBSYSTEM_VENDOR_ID             (0xffffL<<0)
746 #define BNX2_PCI_ID_VAL2_SUBSYSTEM_ID                    (0xffffL<<16)
747
748 #define BNX2_PCI_ID_VAL3                                0x0000043c
749 #define BNX2_PCI_ID_VAL3_CLASS_CODE                      (0xffffffL<<0)
750 #define BNX2_PCI_ID_VAL3_REVISION_ID                     (0xffL<<24)
751
752 #define BNX2_PCI_ID_VAL4                                0x00000440
753 #define BNX2_PCI_ID_VAL4_CAP_ENA                         (0xfL<<0)
754 #define BNX2_PCI_ID_VAL4_CAP_ENA_0                       (0L<<0)
755 #define BNX2_PCI_ID_VAL4_CAP_ENA_1                       (1L<<0)
756 #define BNX2_PCI_ID_VAL4_CAP_ENA_2                       (2L<<0)
757 #define BNX2_PCI_ID_VAL4_CAP_ENA_3                       (3L<<0)
758 #define BNX2_PCI_ID_VAL4_CAP_ENA_4                       (4L<<0)
759 #define BNX2_PCI_ID_VAL4_CAP_ENA_5                       (5L<<0)
760 #define BNX2_PCI_ID_VAL4_CAP_ENA_6                       (6L<<0)
761 #define BNX2_PCI_ID_VAL4_CAP_ENA_7                       (7L<<0)
762 #define BNX2_PCI_ID_VAL4_CAP_ENA_8                       (8L<<0)
763 #define BNX2_PCI_ID_VAL4_CAP_ENA_9                       (9L<<0)
764 #define BNX2_PCI_ID_VAL4_CAP_ENA_10                      (10L<<0)
765 #define BNX2_PCI_ID_VAL4_CAP_ENA_11                      (11L<<0)
766 #define BNX2_PCI_ID_VAL4_CAP_ENA_12                      (12L<<0)
767 #define BNX2_PCI_ID_VAL4_CAP_ENA_13                      (13L<<0)
768 #define BNX2_PCI_ID_VAL4_CAP_ENA_14                      (14L<<0)
769 #define BNX2_PCI_ID_VAL4_CAP_ENA_15                      (15L<<0)
770 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG                    (0x3L<<6)
771 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_0                  (0L<<6)
772 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_1                  (1L<<6)
773 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_2                  (2L<<6)
774 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_3                  (3L<<6)
775 #define BNX2_PCI_ID_VAL4_MSI_LIMIT                       (0x7L<<9)
776 #define BNX2_PCI_ID_VAL4_MSI_ADVERTIZE                   (0x7L<<12)
777 #define BNX2_PCI_ID_VAL4_MSI_ENABLE                      (1L<<15)
778 #define BNX2_PCI_ID_VAL4_MAX_64_ADVERTIZE                (1L<<16)
779 #define BNX2_PCI_ID_VAL4_MAX_133_ADVERTIZE               (1L<<17)
780 #define BNX2_PCI_ID_VAL4_MAX_MEM_READ_SIZE               (0x3L<<21)
781 #define BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE                  (0x7L<<23)
782 #define BNX2_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE             (0x7L<<26)
783
784 #define BNX2_PCI_ID_VAL5                                0x00000444
785 #define BNX2_PCI_ID_VAL5_D1_SUPPORT                      (1L<<0)
786 #define BNX2_PCI_ID_VAL5_D2_SUPPORT                      (1L<<1)
787 #define BNX2_PCI_ID_VAL5_PME_IN_D0                       (1L<<2)
788 #define BNX2_PCI_ID_VAL5_PME_IN_D1                       (1L<<3)
789 #define BNX2_PCI_ID_VAL5_PME_IN_D2                       (1L<<4)
790 #define BNX2_PCI_ID_VAL5_PME_IN_D3_HOT                   (1L<<5)
791
792 #define BNX2_PCI_PCIX_EXTENDED_STATUS                   0x00000448
793 #define BNX2_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP           (1L<<8)
794 #define BNX2_PCI_PCIX_EXTENDED_STATUS_LONG_BURST         (1L<<9)
795 #define BNX2_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_CLASS       (0xfL<<16)
796 #define BNX2_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_IDX         (0xffL<<24)
797
798 #define BNX2_PCI_ID_VAL6                                0x0000044c
799 #define BNX2_PCI_ID_VAL6_MAX_LAT                         (0xffL<<0)
800 #define BNX2_PCI_ID_VAL6_MIN_GNT                         (0xffL<<8)
801 #define BNX2_PCI_ID_VAL6_BIST                            (0xffL<<16)
802
803 #define BNX2_PCI_MSI_DATA                               0x00000450
804 #define BNX2_PCI_MSI_DATA_PCI_MSI_DATA                   (0xffffL<<0)
805
806 #define BNX2_PCI_MSI_ADDR_H                             0x00000454
807 #define BNX2_PCI_MSI_ADDR_L                             0x00000458
808
809
810 /*
811  *  misc_reg definition
812  *  offset: 0x800
813  */
814 #define BNX2_MISC_COMMAND                               0x00000800
815 #define BNX2_MISC_COMMAND_ENABLE_ALL                     (1L<<0)
816 #define BNX2_MISC_COMMAND_DISABLE_ALL                    (1L<<1)
817 #define BNX2_MISC_COMMAND_CORE_RESET                     (1L<<4)
818 #define BNX2_MISC_COMMAND_HARD_RESET                     (1L<<5)
819 #define BNX2_MISC_COMMAND_PAR_ERROR                      (1L<<8)
820 #define BNX2_MISC_COMMAND_PAR_ERR_RAM                    (0x7fL<<16)
821
822 #define BNX2_MISC_CFG                                   0x00000804
823 #define BNX2_MISC_CFG_PCI_GRC_TMOUT                      (1L<<0)
824 #define BNX2_MISC_CFG_NVM_WR_EN                          (0x3L<<1)
825 #define BNX2_MISC_CFG_NVM_WR_EN_PROTECT                  (0L<<1)
826 #define BNX2_MISC_CFG_NVM_WR_EN_PCI                      (1L<<1)
827 #define BNX2_MISC_CFG_NVM_WR_EN_ALLOW                    (2L<<1)
828 #define BNX2_MISC_CFG_NVM_WR_EN_ALLOW2                   (3L<<1)
829 #define BNX2_MISC_CFG_BIST_EN                            (1L<<3)
830 #define BNX2_MISC_CFG_CK25_OUT_ALT_SRC                   (1L<<4)
831 #define BNX2_MISC_CFG_BYPASS_BSCAN                       (1L<<5)
832 #define BNX2_MISC_CFG_BYPASS_EJTAG                       (1L<<6)
833 #define BNX2_MISC_CFG_CLK_CTL_OVERRIDE                   (1L<<7)
834 #define BNX2_MISC_CFG_LEDMODE                            (0x3L<<8)
835 #define BNX2_MISC_CFG_LEDMODE_MAC                        (0L<<8)
836 #define BNX2_MISC_CFG_LEDMODE_GPHY1                      (1L<<8)
837 #define BNX2_MISC_CFG_LEDMODE_GPHY2                      (2L<<8)
838
839 #define BNX2_MISC_ID                                    0x00000808
840 #define BNX2_MISC_ID_BOND_ID                             (0xfL<<0)
841 #define BNX2_MISC_ID_CHIP_METAL                          (0xffL<<4)
842 #define BNX2_MISC_ID_CHIP_REV                            (0xfL<<12)
843 #define BNX2_MISC_ID_CHIP_NUM                            (0xffffL<<16)
844
845 #define BNX2_MISC_ENABLE_STATUS_BITS                    0x0000080c
846 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE         (1L<<0)
847 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE   (1L<<1)
848 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE  (1L<<2)
849 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE         (1L<<3)
850 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE       (1L<<4)
851 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE   (1L<<5)
852 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE         (1L<<6)
853 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE  (1L<<7)
854 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE         (1L<<8)
855 #define BNX2_MISC_ENABLE_STATUS_BITS_EMAC_ENABLE         (1L<<9)
856 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE        (1L<<10)
857 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE    (1L<<11)
858 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE      (1L<<12)
859 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE    (1L<<13)
860 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE         (1L<<14)
861 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE       (1L<<15)
862 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE  (1L<<16)
863 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE       (1L<<17)
864 #define BNX2_MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE   (1L<<18)
865 #define BNX2_MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE        (1L<<19)
866 #define BNX2_MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE        (1L<<20)
867 #define BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE      (1L<<21)
868 #define BNX2_MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE        (1L<<22)
869 #define BNX2_MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE        (1L<<23)
870 #define BNX2_MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE       (1L<<24)
871 #define BNX2_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE        (1L<<25)
872 #define BNX2_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE   (1L<<26)
873 #define BNX2_MISC_ENABLE_STATUS_BITS_UMP_ENABLE          (1L<<27)
874
875 #define BNX2_MISC_ENABLE_SET_BITS                       0x00000810
876 #define BNX2_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE    (1L<<0)
877 #define BNX2_MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE      (1L<<1)
878 #define BNX2_MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE     (1L<<2)
879 #define BNX2_MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE    (1L<<3)
880 #define BNX2_MISC_ENABLE_SET_BITS_TX_DMA_ENABLE          (1L<<4)
881 #define BNX2_MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE      (1L<<5)
882 #define BNX2_MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE    (1L<<6)
883 #define BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE     (1L<<7)
884 #define BNX2_MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE    (1L<<8)
885 #define BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE            (1L<<9)
886 #define BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE   (1L<<10)
887 #define BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE       (1L<<11)
888 #define BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE         (1L<<12)
889 #define BNX2_MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE       (1L<<13)
890 #define BNX2_MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE    (1L<<14)
891 #define BNX2_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE          (1L<<15)
892 #define BNX2_MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE     (1L<<16)
893 #define BNX2_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE          (1L<<17)
894 #define BNX2_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE      (1L<<18)
895 #define BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE   (1L<<19)
896 #define BNX2_MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE   (1L<<20)
897 #define BNX2_MISC_ENABLE_SET_BITS_CONTEXT_ENABLE         (1L<<21)
898 #define BNX2_MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE   (1L<<22)
899 #define BNX2_MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE   (1L<<23)
900 #define BNX2_MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE  (1L<<24)
901 #define BNX2_MISC_ENABLE_SET_BITS_TIMER_ENABLE           (1L<<25)
902 #define BNX2_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE      (1L<<26)
903 #define BNX2_MISC_ENABLE_SET_BITS_UMP_ENABLE             (1L<<27)
904
905 #define BNX2_MISC_ENABLE_CLR_BITS                       0x00000814
906 #define BNX2_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE    (1L<<0)
907 #define BNX2_MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE      (1L<<1)
908 #define BNX2_MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE     (1L<<2)
909 #define BNX2_MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE    (1L<<3)
910 #define BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE          (1L<<4)
911 #define BNX2_MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE      (1L<<5)
912 #define BNX2_MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE    (1L<<6)
913 #define BNX2_MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE     (1L<<7)
914 #define BNX2_MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE    (1L<<8)
915 #define BNX2_MISC_ENABLE_CLR_BITS_EMAC_ENABLE            (1L<<9)
916 #define BNX2_MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE   (1L<<10)
917 #define BNX2_MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE       (1L<<11)
918 #define BNX2_MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE         (1L<<12)
919 #define BNX2_MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE       (1L<<13)
920 #define BNX2_MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE    (1L<<14)
921 #define BNX2_MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE          (1L<<15)
922 #define BNX2_MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE     (1L<<16)
923 #define BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE          (1L<<17)
924 #define BNX2_MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE      (1L<<18)
925 #define BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE   (1L<<19)
926 #define BNX2_MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE   (1L<<20)
927 #define BNX2_MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE         (1L<<21)
928 #define BNX2_MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE   (1L<<22)
929 #define BNX2_MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE   (1L<<23)
930 #define BNX2_MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE  (1L<<24)
931 #define BNX2_MISC_ENABLE_CLR_BITS_TIMER_ENABLE           (1L<<25)
932 #define BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE      (1L<<26)
933 #define BNX2_MISC_ENABLE_CLR_BITS_UMP_ENABLE             (1L<<27)
934
935 #define BNX2_MISC_CLOCK_CONTROL_BITS                    0x00000818
936 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET     (0xfL<<0)
937 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ       (0L<<0)
938 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ       (1L<<0)
939 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ       (2L<<0)
940 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ       (3L<<0)
941 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ       (4L<<0)
942 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ       (5L<<0)
943 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ       (6L<<0)
944 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ      (7L<<0)
945 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW         (0xfL<<0)
946 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE    (1L<<6)
947 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT        (1L<<7)
948 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC    (0x7L<<8)
949 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF      (0L<<8)
950 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12         (1L<<8)
951 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6  (2L<<8)
952 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62         (4L<<8)
953 #define BNX2_MISC_CLOCK_CONTROL_BITS_PLAY_DEAD           (1L<<11)
954 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED  (0xfL<<12)
955 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100      (0L<<12)
956 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80       (1L<<12)
957 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50       (2L<<12)
958 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40       (4L<<12)
959 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25       (8L<<12)
960 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP   (1L<<16)
961 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_PLL_STOP        (1L<<17)
962 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_18         (1L<<18)
963 #define BNX2_MISC_CLOCK_CONTROL_BITS_USE_SPD_DET         (1L<<19)
964 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED            (0xfffL<<20)
965
966 #define BNX2_MISC_GPIO                                  0x0000081c
967 #define BNX2_MISC_GPIO_VALUE                             (0xffL<<0)
968 #define BNX2_MISC_GPIO_SET                               (0xffL<<8)
969 #define BNX2_MISC_GPIO_CLR                               (0xffL<<16)
970 #define BNX2_MISC_GPIO_FLOAT                             (0xffL<<24)
971
972 #define BNX2_MISC_GPIO_INT                              0x00000820
973 #define BNX2_MISC_GPIO_INT_INT_STATE                     (0xfL<<0)
974 #define BNX2_MISC_GPIO_INT_OLD_VALUE                     (0xfL<<8)
975 #define BNX2_MISC_GPIO_INT_OLD_SET                       (0xfL<<16)
976 #define BNX2_MISC_GPIO_INT_OLD_CLR                       (0xfL<<24)
977
978 #define BNX2_MISC_CONFIG_LFSR                           0x00000824
979 #define BNX2_MISC_CONFIG_LFSR_DIV                        (0xffffL<<0)
980
981 #define BNX2_MISC_LFSR_MASK_BITS                        0x00000828
982 #define BNX2_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE     (1L<<0)
983 #define BNX2_MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE       (1L<<1)
984 #define BNX2_MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE      (1L<<2)
985 #define BNX2_MISC_LFSR_MASK_BITS_TX_PROCESSOR_ENABLE     (1L<<3)
986 #define BNX2_MISC_LFSR_MASK_BITS_TX_DMA_ENABLE           (1L<<4)
987 #define BNX2_MISC_LFSR_MASK_BITS_TX_PATCHUP_ENABLE       (1L<<5)
988 #define BNX2_MISC_LFSR_MASK_BITS_TX_PAYLOAD_Q_ENABLE     (1L<<6)
989 #define BNX2_MISC_LFSR_MASK_BITS_TX_HEADER_Q_ENABLE      (1L<<7)
990 #define BNX2_MISC_LFSR_MASK_BITS_TX_ASSEMBLER_ENABLE     (1L<<8)
991 #define BNX2_MISC_LFSR_MASK_BITS_EMAC_ENABLE             (1L<<9)
992 #define BNX2_MISC_LFSR_MASK_BITS_RX_PARSER_MAC_ENABLE    (1L<<10)
993 #define BNX2_MISC_LFSR_MASK_BITS_RX_PARSER_CATCHUP_ENABLE        (1L<<11)
994 #define BNX2_MISC_LFSR_MASK_BITS_RX_MBUF_ENABLE          (1L<<12)
995 #define BNX2_MISC_LFSR_MASK_BITS_RX_LOOKUP_ENABLE        (1L<<13)
996 #define BNX2_MISC_LFSR_MASK_BITS_RX_PROCESSOR_ENABLE     (1L<<14)
997 #define BNX2_MISC_LFSR_MASK_BITS_RX_V2P_ENABLE           (1L<<15)
998 #define BNX2_MISC_LFSR_MASK_BITS_RX_BD_CACHE_ENABLE      (1L<<16)
999 #define BNX2_MISC_LFSR_MASK_BITS_RX_DMA_ENABLE           (1L<<17)
1000 #define BNX2_MISC_LFSR_MASK_BITS_COMPLETION_ENABLE       (1L<<18)
1001 #define BNX2_MISC_LFSR_MASK_BITS_HOST_COALESCE_ENABLE    (1L<<19)
1002 #define BNX2_MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE    (1L<<20)
1003 #define BNX2_MISC_LFSR_MASK_BITS_CONTEXT_ENABLE          (1L<<21)
1004 #define BNX2_MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE    (1L<<22)
1005 #define BNX2_MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE    (1L<<23)
1006 #define BNX2_MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE   (1L<<24)
1007 #define BNX2_MISC_LFSR_MASK_BITS_TIMER_ENABLE            (1L<<25)
1008 #define BNX2_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE       (1L<<26)
1009 #define BNX2_MISC_LFSR_MASK_BITS_UMP_ENABLE              (1L<<27)
1010
1011 #define BNX2_MISC_ARB_REQ0                              0x0000082c
1012 #define BNX2_MISC_ARB_REQ1                              0x00000830
1013 #define BNX2_MISC_ARB_REQ2                              0x00000834
1014 #define BNX2_MISC_ARB_REQ3                              0x00000838
1015 #define BNX2_MISC_ARB_REQ4                              0x0000083c
1016 #define BNX2_MISC_ARB_FREE0                             0x00000840
1017 #define BNX2_MISC_ARB_FREE1                             0x00000844
1018 #define BNX2_MISC_ARB_FREE2                             0x00000848
1019 #define BNX2_MISC_ARB_FREE3                             0x0000084c
1020 #define BNX2_MISC_ARB_FREE4                             0x00000850
1021 #define BNX2_MISC_ARB_REQ_STATUS0                       0x00000854
1022 #define BNX2_MISC_ARB_REQ_STATUS1                       0x00000858
1023 #define BNX2_MISC_ARB_REQ_STATUS2                       0x0000085c
1024 #define BNX2_MISC_ARB_REQ_STATUS3                       0x00000860
1025 #define BNX2_MISC_ARB_REQ_STATUS4                       0x00000864
1026 #define BNX2_MISC_ARB_GNT0                              0x00000868
1027 #define BNX2_MISC_ARB_GNT0_0                             (0x7L<<0)
1028 #define BNX2_MISC_ARB_GNT0_1                             (0x7L<<4)
1029 #define BNX2_MISC_ARB_GNT0_2                             (0x7L<<8)
1030 #define BNX2_MISC_ARB_GNT0_3                             (0x7L<<12)
1031 #define BNX2_MISC_ARB_GNT0_4                             (0x7L<<16)
1032 #define BNX2_MISC_ARB_GNT0_5                             (0x7L<<20)
1033 #define BNX2_MISC_ARB_GNT0_6                             (0x7L<<24)
1034 #define BNX2_MISC_ARB_GNT0_7                             (0x7L<<28)
1035
1036 #define BNX2_MISC_ARB_GNT1                              0x0000086c
1037 #define BNX2_MISC_ARB_GNT1_8                             (0x7L<<0)
1038 #define BNX2_MISC_ARB_GNT1_9                             (0x7L<<4)
1039 #define BNX2_MISC_ARB_GNT1_10                            (0x7L<<8)
1040 #define BNX2_MISC_ARB_GNT1_11                            (0x7L<<12)
1041 #define BNX2_MISC_ARB_GNT1_12                            (0x7L<<16)
1042 #define BNX2_MISC_ARB_GNT1_13                            (0x7L<<20)
1043 #define BNX2_MISC_ARB_GNT1_14                            (0x7L<<24)
1044 #define BNX2_MISC_ARB_GNT1_15                            (0x7L<<28)
1045
1046 #define BNX2_MISC_ARB_GNT2                              0x00000870
1047 #define BNX2_MISC_ARB_GNT2_16                            (0x7L<<0)
1048 #define BNX2_MISC_ARB_GNT2_17                            (0x7L<<4)
1049 #define BNX2_MISC_ARB_GNT2_18                            (0x7L<<8)
1050 #define BNX2_MISC_ARB_GNT2_19                            (0x7L<<12)
1051 #define BNX2_MISC_ARB_GNT2_20                            (0x7L<<16)
1052 #define BNX2_MISC_ARB_GNT2_21                            (0x7L<<20)
1053 #define BNX2_MISC_ARB_GNT2_22                            (0x7L<<24)
1054 #define BNX2_MISC_ARB_GNT2_23                            (0x7L<<28)
1055
1056 #define BNX2_MISC_ARB_GNT3                              0x00000874
1057 #define BNX2_MISC_ARB_GNT3_24                            (0x7L<<0)
1058 #define BNX2_MISC_ARB_GNT3_25                            (0x7L<<4)
1059 #define BNX2_MISC_ARB_GNT3_26                            (0x7L<<8)
1060 #define BNX2_MISC_ARB_GNT3_27                            (0x7L<<12)
1061 #define BNX2_MISC_ARB_GNT3_28                            (0x7L<<16)
1062 #define BNX2_MISC_ARB_GNT3_29                            (0x7L<<20)
1063 #define BNX2_MISC_ARB_GNT3_30                            (0x7L<<24)
1064 #define BNX2_MISC_ARB_GNT3_31                            (0x7L<<28)
1065
1066 #define BNX2_MISC_PRBS_CONTROL                          0x00000878
1067 #define BNX2_MISC_PRBS_CONTROL_EN                        (1L<<0)
1068 #define BNX2_MISC_PRBS_CONTROL_RSTB                      (1L<<1)
1069 #define BNX2_MISC_PRBS_CONTROL_INV                       (1L<<2)
1070 #define BNX2_MISC_PRBS_CONTROL_ERR_CLR                   (1L<<3)
1071 #define BNX2_MISC_PRBS_CONTROL_ORDER                     (0x3L<<4)
1072 #define BNX2_MISC_PRBS_CONTROL_ORDER_7TH                 (0L<<4)
1073 #define BNX2_MISC_PRBS_CONTROL_ORDER_15TH                (1L<<4)
1074 #define BNX2_MISC_PRBS_CONTROL_ORDER_23RD                (2L<<4)
1075 #define BNX2_MISC_PRBS_CONTROL_ORDER_31ST                (3L<<4)
1076
1077 #define BNX2_MISC_PRBS_STATUS                           0x0000087c
1078 #define BNX2_MISC_PRBS_STATUS_LOCK                       (1L<<0)
1079 #define BNX2_MISC_PRBS_STATUS_STKY                       (1L<<1)
1080 #define BNX2_MISC_PRBS_STATUS_ERRORS                     (0x3fffL<<2)
1081 #define BNX2_MISC_PRBS_STATUS_STATE                      (0xfL<<16)
1082
1083 #define BNX2_MISC_SM_ASF_CONTROL                        0x00000880
1084 #define BNX2_MISC_SM_ASF_CONTROL_ASF_RST                 (1L<<0)
1085 #define BNX2_MISC_SM_ASF_CONTROL_TSC_EN                  (1L<<1)
1086 #define BNX2_MISC_SM_ASF_CONTROL_WG_TO                   (1L<<2)
1087 #define BNX2_MISC_SM_ASF_CONTROL_HB_TO                   (1L<<3)
1088 #define BNX2_MISC_SM_ASF_CONTROL_PA_TO                   (1L<<4)
1089 #define BNX2_MISC_SM_ASF_CONTROL_PL_TO                   (1L<<5)
1090 #define BNX2_MISC_SM_ASF_CONTROL_RT_TO                   (1L<<6)
1091 #define BNX2_MISC_SM_ASF_CONTROL_SMB_EVENT               (1L<<7)
1092 #define BNX2_MISC_SM_ASF_CONTROL_RES                     (0xfL<<8)
1093 #define BNX2_MISC_SM_ASF_CONTROL_SMB_EN                  (1L<<12)
1094 #define BNX2_MISC_SM_ASF_CONTROL_SMB_BB_EN               (1L<<13)
1095 #define BNX2_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT        (1L<<14)
1096 #define BNX2_MISC_SM_ASF_CONTROL_SMB_AUTOREAD            (1L<<15)
1097 #define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1           (0x3fL<<16)
1098 #define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2           (0x3fL<<24)
1099 #define BNX2_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0       (1L<<30)
1100 #define BNX2_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN          (1L<<31)
1101
1102 #define BNX2_MISC_SMB_IN                                0x00000884
1103 #define BNX2_MISC_SMB_IN_DAT_IN                          (0xffL<<0)
1104 #define BNX2_MISC_SMB_IN_RDY                             (1L<<8)
1105 #define BNX2_MISC_SMB_IN_DONE                            (1L<<9)
1106 #define BNX2_MISC_SMB_IN_FIRSTBYTE                       (1L<<10)
1107 #define BNX2_MISC_SMB_IN_STATUS                          (0x7L<<11)
1108 #define BNX2_MISC_SMB_IN_STATUS_OK                       (0x0L<<11)
1109 #define BNX2_MISC_SMB_IN_STATUS_PEC                      (0x1L<<11)
1110 #define BNX2_MISC_SMB_IN_STATUS_OFLOW                    (0x2L<<11)
1111 #define BNX2_MISC_SMB_IN_STATUS_STOP                     (0x3L<<11)
1112 #define BNX2_MISC_SMB_IN_STATUS_TIMEOUT                  (0x4L<<11)
1113
1114 #define BNX2_MISC_SMB_OUT                               0x00000888
1115 #define BNX2_MISC_SMB_OUT_DAT_OUT                        (0xffL<<0)
1116 #define BNX2_MISC_SMB_OUT_RDY                            (1L<<8)
1117 #define BNX2_MISC_SMB_OUT_START                          (1L<<9)
1118 #define BNX2_MISC_SMB_OUT_LAST                           (1L<<10)
1119 #define BNX2_MISC_SMB_OUT_ACC_TYPE                       (1L<<11)
1120 #define BNX2_MISC_SMB_OUT_ENB_PEC                        (1L<<12)
1121 #define BNX2_MISC_SMB_OUT_GET_RX_LEN                     (1L<<13)
1122 #define BNX2_MISC_SMB_OUT_SMB_READ_LEN                   (0x3fL<<14)
1123 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS                 (0xfL<<20)
1124 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_OK              (0L<<20)
1125 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK      (1L<<20)
1126 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK        (9L<<20)
1127 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW           (2L<<20)
1128 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_STOP            (3L<<20)
1129 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT         (4L<<20)
1130 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST      (5L<<20)
1131 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST        (0xdL<<20)
1132 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK          (0x6L<<20)
1133 #define BNX2_MISC_SMB_OUT_SMB_OUT_SLAVEMODE              (1L<<24)
1134 #define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_EN                 (1L<<25)
1135 #define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_IN                 (1L<<26)
1136 #define BNX2_MISC_SMB_OUT_SMB_OUT_CLK_EN                 (1L<<27)
1137 #define BNX2_MISC_SMB_OUT_SMB_OUT_CLK_IN                 (1L<<28)
1138
1139 #define BNX2_MISC_SMB_WATCHDOG                          0x0000088c
1140 #define BNX2_MISC_SMB_WATCHDOG_WATCHDOG                  (0xffffL<<0)
1141
1142 #define BNX2_MISC_SMB_HEARTBEAT                         0x00000890
1143 #define BNX2_MISC_SMB_HEARTBEAT_HEARTBEAT                (0xffffL<<0)
1144
1145 #define BNX2_MISC_SMB_POLL_ASF                          0x00000894
1146 #define BNX2_MISC_SMB_POLL_ASF_POLL_ASF                  (0xffffL<<0)
1147
1148 #define BNX2_MISC_SMB_POLL_LEGACY                       0x00000898
1149 #define BNX2_MISC_SMB_POLL_LEGACY_POLL_LEGACY            (0xffffL<<0)
1150
1151 #define BNX2_MISC_SMB_RETRAN                            0x0000089c
1152 #define BNX2_MISC_SMB_RETRAN_RETRAN                      (0xffL<<0)
1153
1154 #define BNX2_MISC_SMB_TIMESTAMP                         0x000008a0
1155 #define BNX2_MISC_SMB_TIMESTAMP_TIMESTAMP                (0xffffffffL<<0)
1156
1157 #define BNX2_MISC_PERR_ENA0                             0x000008a4
1158 #define BNX2_MISC_PERR_ENA0_COM_MISC_CTXC                (1L<<0)
1159 #define BNX2_MISC_PERR_ENA0_COM_MISC_REGF                (1L<<1)
1160 #define BNX2_MISC_PERR_ENA0_COM_MISC_SCPAD               (1L<<2)
1161 #define BNX2_MISC_PERR_ENA0_CP_MISC_CTXC                 (1L<<3)
1162 #define BNX2_MISC_PERR_ENA0_CP_MISC_REGF                 (1L<<4)
1163 #define BNX2_MISC_PERR_ENA0_CP_MISC_SCPAD                (1L<<5)
1164 #define BNX2_MISC_PERR_ENA0_CS_MISC_TMEM                 (1L<<6)
1165 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM0               (1L<<7)
1166 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM1               (1L<<8)
1167 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM2               (1L<<9)
1168 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM3               (1L<<10)
1169 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM4               (1L<<11)
1170 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM5               (1L<<12)
1171 #define BNX2_MISC_PERR_ENA0_CTX_MISC_PGTBL               (1L<<13)
1172 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR0                (1L<<14)
1173 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR1                (1L<<15)
1174 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR2                (1L<<16)
1175 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR3                (1L<<17)
1176 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR4                (1L<<18)
1177 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW0                (1L<<19)
1178 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW1                (1L<<20)
1179 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW2                (1L<<21)
1180 #define BNX2_MISC_PERR_ENA0_HC_MISC_DMA                  (1L<<22)
1181 #define BNX2_MISC_PERR_ENA0_MCP_MISC_REGF                (1L<<23)
1182 #define BNX2_MISC_PERR_ENA0_MCP_MISC_SCPAD               (1L<<24)
1183 #define BNX2_MISC_PERR_ENA0_MQ_MISC_CTX                  (1L<<25)
1184 #define BNX2_MISC_PERR_ENA0_RBDC_MISC                    (1L<<26)
1185 #define BNX2_MISC_PERR_ENA0_RBUF_MISC_MB                 (1L<<27)
1186 #define BNX2_MISC_PERR_ENA0_RBUF_MISC_PTR                (1L<<28)
1187 #define BNX2_MISC_PERR_ENA0_RDE_MISC_RPC                 (1L<<29)
1188 #define BNX2_MISC_PERR_ENA0_RDE_MISC_RPM                 (1L<<30)
1189 #define BNX2_MISC_PERR_ENA0_RV2P_MISC_CB0REGS            (1L<<31)
1190
1191 #define BNX2_MISC_PERR_ENA1                             0x000008a8
1192 #define BNX2_MISC_PERR_ENA1_RV2P_MISC_CB1REGS            (1L<<0)
1193 #define BNX2_MISC_PERR_ENA1_RV2P_MISC_P1IRAM             (1L<<1)
1194 #define BNX2_MISC_PERR_ENA1_RV2P_MISC_P2IRAM             (1L<<2)
1195 #define BNX2_MISC_PERR_ENA1_RXP_MISC_CTXC                (1L<<3)
1196 #define BNX2_MISC_PERR_ENA1_RXP_MISC_REGF                (1L<<4)
1197 #define BNX2_MISC_PERR_ENA1_RXP_MISC_SCPAD               (1L<<5)
1198 #define BNX2_MISC_PERR_ENA1_RXP_MISC_RBUFC               (1L<<6)
1199 #define BNX2_MISC_PERR_ENA1_TBDC_MISC                    (1L<<7)
1200 #define BNX2_MISC_PERR_ENA1_TDMA_MISC                    (1L<<8)
1201 #define BNX2_MISC_PERR_ENA1_THBUF_MISC_MB0               (1L<<9)
1202 #define BNX2_MISC_PERR_ENA1_THBUF_MISC_MB1               (1L<<10)
1203 #define BNX2_MISC_PERR_ENA1_TPAT_MISC_REGF               (1L<<11)
1204 #define BNX2_MISC_PERR_ENA1_TPAT_MISC_SCPAD              (1L<<12)
1205 #define BNX2_MISC_PERR_ENA1_TPBUF_MISC_MB                (1L<<13)
1206 #define BNX2_MISC_PERR_ENA1_TSCH_MISC_LR                 (1L<<14)
1207 #define BNX2_MISC_PERR_ENA1_TXP_MISC_CTXC                (1L<<15)
1208 #define BNX2_MISC_PERR_ENA1_TXP_MISC_REGF                (1L<<16)
1209 #define BNX2_MISC_PERR_ENA1_TXP_MISC_SCPAD               (1L<<17)
1210 #define BNX2_MISC_PERR_ENA1_UMP_MISC_FIORX               (1L<<18)
1211 #define BNX2_MISC_PERR_ENA1_UMP_MISC_FIOTX               (1L<<19)
1212 #define BNX2_MISC_PERR_ENA1_UMP_MISC_RX                  (1L<<20)
1213 #define BNX2_MISC_PERR_ENA1_UMP_MISC_TX                  (1L<<21)
1214 #define BNX2_MISC_PERR_ENA1_RDMAQ_MISC                   (1L<<22)
1215 #define BNX2_MISC_PERR_ENA1_CSQ_MISC                     (1L<<23)
1216 #define BNX2_MISC_PERR_ENA1_CPQ_MISC                     (1L<<24)
1217 #define BNX2_MISC_PERR_ENA1_MCPQ_MISC                    (1L<<25)
1218 #define BNX2_MISC_PERR_ENA1_RV2PMQ_MISC                  (1L<<26)
1219 #define BNX2_MISC_PERR_ENA1_RV2PPQ_MISC                  (1L<<27)
1220 #define BNX2_MISC_PERR_ENA1_RV2PTQ_MISC                  (1L<<28)
1221 #define BNX2_MISC_PERR_ENA1_RXPQ_MISC                    (1L<<29)
1222 #define BNX2_MISC_PERR_ENA1_RXPCQ_MISC                   (1L<<30)
1223 #define BNX2_MISC_PERR_ENA1_RLUPQ_MISC                   (1L<<31)
1224
1225 #define BNX2_MISC_PERR_ENA2                             0x000008ac
1226 #define BNX2_MISC_PERR_ENA2_COMQ_MISC                    (1L<<0)
1227 #define BNX2_MISC_PERR_ENA2_COMXQ_MISC                   (1L<<1)
1228 #define BNX2_MISC_PERR_ENA2_COMTQ_MISC                   (1L<<2)
1229 #define BNX2_MISC_PERR_ENA2_TSCHQ_MISC                   (1L<<3)
1230 #define BNX2_MISC_PERR_ENA2_TBDRQ_MISC                   (1L<<4)
1231 #define BNX2_MISC_PERR_ENA2_TXPQ_MISC                    (1L<<5)
1232 #define BNX2_MISC_PERR_ENA2_TDMAQ_MISC                   (1L<<6)
1233 #define BNX2_MISC_PERR_ENA2_TPATQ_MISC                   (1L<<7)
1234 #define BNX2_MISC_PERR_ENA2_TASQ_MISC                    (1L<<8)
1235
1236 #define BNX2_MISC_DEBUG_VECTOR_SEL                      0x000008b0
1237 #define BNX2_MISC_DEBUG_VECTOR_SEL_0                     (0xfffL<<0)
1238 #define BNX2_MISC_DEBUG_VECTOR_SEL_1                     (0xfffL<<12)
1239
1240 #define BNX2_MISC_VREG_CONTROL                          0x000008b4
1241 #define BNX2_MISC_VREG_CONTROL_1_2                       (0xfL<<0)
1242 #define BNX2_MISC_VREG_CONTROL_2_5                       (0xfL<<4)
1243
1244 #define BNX2_MISC_FINAL_CLK_CTL_VAL                     0x000008b8
1245 #define BNX2_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL       (0x3ffffffL<<6)
1246
1247 #define BNX2_MISC_UNUSED0                               0x000008bc
1248
1249
1250 /*
1251  *  nvm_reg definition
1252  *  offset: 0x6400
1253  */
1254 #define BNX2_NVM_COMMAND                                0x00006400
1255 #define BNX2_NVM_COMMAND_RST                             (1L<<0)
1256 #define BNX2_NVM_COMMAND_DONE                            (1L<<3)
1257 #define BNX2_NVM_COMMAND_DOIT                            (1L<<4)
1258 #define BNX2_NVM_COMMAND_WR                              (1L<<5)
1259 #define BNX2_NVM_COMMAND_ERASE                           (1L<<6)
1260 #define BNX2_NVM_COMMAND_FIRST                           (1L<<7)
1261 #define BNX2_NVM_COMMAND_LAST                            (1L<<8)
1262 #define BNX2_NVM_COMMAND_WREN                            (1L<<16)
1263 #define BNX2_NVM_COMMAND_WRDI                            (1L<<17)
1264 #define BNX2_NVM_COMMAND_EWSR                            (1L<<18)
1265 #define BNX2_NVM_COMMAND_WRSR                            (1L<<19)
1266
1267 #define BNX2_NVM_STATUS                                 0x00006404
1268 #define BNX2_NVM_STATUS_PI_FSM_STATE                     (0xfL<<0)
1269 #define BNX2_NVM_STATUS_EE_FSM_STATE                     (0xfL<<4)
1270 #define BNX2_NVM_STATUS_EQ_FSM_STATE                     (0xfL<<8)
1271
1272 #define BNX2_NVM_WRITE                                  0x00006408
1273 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE                   (0xffffffffL<<0)
1274 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG          (0L<<0)
1275 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_EECLK             (1L<<0)
1276 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_EEDATA            (2L<<0)
1277 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SCLK              (4L<<0)
1278 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_CS_B              (8L<<0)
1279 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SO                (16L<<0)
1280 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SI                (32L<<0)
1281
1282 #define BNX2_NVM_ADDR                                   0x0000640c
1283 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE                     (0xffffffL<<0)
1284 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG            (0L<<0)
1285 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_EECLK               (1L<<0)
1286 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_EEDATA              (2L<<0)
1287 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SCLK                (4L<<0)
1288 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS_B                (8L<<0)
1289 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO                  (16L<<0)
1290 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI                  (32L<<0)
1291
1292 #define BNX2_NVM_READ                                   0x00006410
1293 #define BNX2_NVM_READ_NVM_READ_VALUE                     (0xffffffffL<<0)
1294 #define BNX2_NVM_READ_NVM_READ_VALUE_BIT_BANG            (0L<<0)
1295 #define BNX2_NVM_READ_NVM_READ_VALUE_EECLK               (1L<<0)
1296 #define BNX2_NVM_READ_NVM_READ_VALUE_EEDATA              (2L<<0)
1297 #define BNX2_NVM_READ_NVM_READ_VALUE_SCLK                (4L<<0)
1298 #define BNX2_NVM_READ_NVM_READ_VALUE_CS_B                (8L<<0)
1299 #define BNX2_NVM_READ_NVM_READ_VALUE_SO                  (16L<<0)
1300 #define BNX2_NVM_READ_NVM_READ_VALUE_SI                  (32L<<0)
1301
1302 #define BNX2_NVM_CFG1                                   0x00006414
1303 #define BNX2_NVM_CFG1_FLASH_MODE                         (1L<<0)
1304 #define BNX2_NVM_CFG1_BUFFER_MODE                        (1L<<1)
1305 #define BNX2_NVM_CFG1_PASS_MODE                          (1L<<2)
1306 #define BNX2_NVM_CFG1_BITBANG_MODE                       (1L<<3)
1307 #define BNX2_NVM_CFG1_STATUS_BIT                         (0x7L<<4)
1308 #define BNX2_NVM_CFG1_STATUS_BIT_FLASH_RDY               (0L<<4)
1309 #define BNX2_NVM_CFG1_STATUS_BIT_BUFFER_RDY              (7L<<4)
1310 #define BNX2_NVM_CFG1_SPI_CLK_DIV                        (0xfL<<7)
1311 #define BNX2_NVM_CFG1_SEE_CLK_DIV                        (0x7ffL<<11)
1312 #define BNX2_NVM_CFG1_PROTECT_MODE                       (1L<<24)
1313 #define BNX2_NVM_CFG1_FLASH_SIZE                         (1L<<25)
1314 #define BNX2_NVM_CFG1_COMPAT_BYPASSS                     (1L<<31)
1315
1316 #define BNX2_NVM_CFG2                                   0x00006418
1317 #define BNX2_NVM_CFG2_ERASE_CMD                          (0xffL<<0)
1318 #define BNX2_NVM_CFG2_DUMMY                              (0xffL<<8)
1319 #define BNX2_NVM_CFG2_STATUS_CMD                         (0xffL<<16)
1320
1321 #define BNX2_NVM_CFG3                                   0x0000641c
1322 #define BNX2_NVM_CFG3_BUFFER_RD_CMD                      (0xffL<<0)
1323 #define BNX2_NVM_CFG3_WRITE_CMD                          (0xffL<<8)
1324 #define BNX2_NVM_CFG3_BUFFER_WRITE_CMD                   (0xffL<<16)
1325 #define BNX2_NVM_CFG3_READ_CMD                           (0xffL<<24)
1326
1327 #define BNX2_NVM_SW_ARB                                 0x00006420
1328 #define BNX2_NVM_SW_ARB_ARB_REQ_SET0                     (1L<<0)
1329 #define BNX2_NVM_SW_ARB_ARB_REQ_SET1                     (1L<<1)
1330 #define BNX2_NVM_SW_ARB_ARB_REQ_SET2                     (1L<<2)
1331 #define BNX2_NVM_SW_ARB_ARB_REQ_SET3                     (1L<<3)
1332 #define BNX2_NVM_SW_ARB_ARB_REQ_CLR0                     (1L<<4)
1333 #define BNX2_NVM_SW_ARB_ARB_REQ_CLR1                     (1L<<5)
1334 #define BNX2_NVM_SW_ARB_ARB_REQ_CLR2                     (1L<<6)
1335 #define BNX2_NVM_SW_ARB_ARB_REQ_CLR3                     (1L<<7)
1336 #define BNX2_NVM_SW_ARB_ARB_ARB0                         (1L<<8)
1337 #define BNX2_NVM_SW_ARB_ARB_ARB1                         (1L<<9)
1338 #define BNX2_NVM_SW_ARB_ARB_ARB2                         (1L<<10)
1339 #define BNX2_NVM_SW_ARB_ARB_ARB3                         (1L<<11)
1340 #define BNX2_NVM_SW_ARB_REQ0                             (1L<<12)
1341 #define BNX2_NVM_SW_ARB_REQ1                             (1L<<13)
1342 #define BNX2_NVM_SW_ARB_REQ2                             (1L<<14)
1343 #define BNX2_NVM_SW_ARB_REQ3                             (1L<<15)
1344
1345 #define BNX2_NVM_ACCESS_ENABLE                          0x00006424
1346 #define BNX2_NVM_ACCESS_ENABLE_EN                        (1L<<0)
1347 #define BNX2_NVM_ACCESS_ENABLE_WR_EN                     (1L<<1)
1348
1349 #define BNX2_NVM_WRITE1                                 0x00006428
1350 #define BNX2_NVM_WRITE1_WREN_CMD                         (0xffL<<0)
1351 #define BNX2_NVM_WRITE1_WRDI_CMD                         (0xffL<<8)
1352 #define BNX2_NVM_WRITE1_SR_DATA                          (0xffL<<16)
1353
1354
1355
1356 /*
1357  *  dma_reg definition
1358  *  offset: 0xc00
1359  */
1360 #define BNX2_DMA_COMMAND                                0x00000c00
1361 #define BNX2_DMA_COMMAND_ENABLE                          (1L<<0)
1362
1363 #define BNX2_DMA_STATUS                                 0x00000c04
1364 #define BNX2_DMA_STATUS_PAR_ERROR_STATE                  (1L<<0)
1365 #define BNX2_DMA_STATUS_READ_TRANSFERS_STAT              (1L<<16)
1366 #define BNX2_DMA_STATUS_READ_DELAY_PCI_CLKS_STAT         (1L<<17)
1367 #define BNX2_DMA_STATUS_BIG_READ_TRANSFERS_STAT          (1L<<18)
1368 #define BNX2_DMA_STATUS_BIG_READ_DELAY_PCI_CLKS_STAT     (1L<<19)
1369 #define BNX2_DMA_STATUS_BIG_READ_RETRY_AFTER_DATA_STAT   (1L<<20)
1370 #define BNX2_DMA_STATUS_WRITE_TRANSFERS_STAT             (1L<<21)
1371 #define BNX2_DMA_STATUS_WRITE_DELAY_PCI_CLKS_STAT        (1L<<22)
1372 #define BNX2_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT         (1L<<23)
1373 #define BNX2_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT    (1L<<24)
1374 #define BNX2_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT  (1L<<25)
1375
1376 #define BNX2_DMA_CONFIG                                 0x00000c08
1377 #define BNX2_DMA_CONFIG_DATA_BYTE_SWAP                   (1L<<0)
1378 #define BNX2_DMA_CONFIG_DATA_WORD_SWAP                   (1L<<1)
1379 #define BNX2_DMA_CONFIG_CNTL_BYTE_SWAP                   (1L<<4)
1380 #define BNX2_DMA_CONFIG_CNTL_WORD_SWAP                   (1L<<5)
1381 #define BNX2_DMA_CONFIG_ONE_DMA                          (1L<<6)
1382 #define BNX2_DMA_CONFIG_CNTL_TWO_DMA                     (1L<<7)
1383 #define BNX2_DMA_CONFIG_CNTL_FPGA_MODE                   (1L<<8)
1384 #define BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA               (1L<<10)
1385 #define BNX2_DMA_CONFIG_CNTL_PCI_COMP_DLY                (1L<<11)
1386 #define BNX2_DMA_CONFIG_NO_RCHANS_IN_USE                 (0xfL<<12)
1387 #define BNX2_DMA_CONFIG_NO_WCHANS_IN_USE                 (0xfL<<16)
1388 #define BNX2_DMA_CONFIG_PCI_CLK_CMP_BITS                 (0x7L<<20)
1389 #define BNX2_DMA_CONFIG_PCI_FAST_CLK_CMP                 (1L<<23)
1390 #define BNX2_DMA_CONFIG_BIG_SIZE                         (0xfL<<24)
1391 #define BNX2_DMA_CONFIG_BIG_SIZE_NONE                    (0x0L<<24)
1392 #define BNX2_DMA_CONFIG_BIG_SIZE_64                      (0x1L<<24)
1393 #define BNX2_DMA_CONFIG_BIG_SIZE_128                     (0x2L<<24)
1394 #define BNX2_DMA_CONFIG_BIG_SIZE_256                     (0x4L<<24)
1395 #define BNX2_DMA_CONFIG_BIG_SIZE_512                     (0x8L<<24)
1396
1397 #define BNX2_DMA_BLACKOUT                               0x00000c0c
1398 #define BNX2_DMA_BLACKOUT_RD_RETRY_BLACKOUT              (0xffL<<0)
1399 #define BNX2_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT          (0xffL<<8)
1400 #define BNX2_DMA_BLACKOUT_WR_RETRY_BLACKOUT              (0xffL<<16)
1401
1402 #define BNX2_DMA_RCHAN_STAT                             0x00000c30
1403 #define BNX2_DMA_RCHAN_STAT_COMP_CODE_0                  (0x7L<<0)
1404 #define BNX2_DMA_RCHAN_STAT_PAR_ERR_0                    (1L<<3)
1405 #define BNX2_DMA_RCHAN_STAT_COMP_CODE_1                  (0x7L<<4)
1406 #define BNX2_DMA_RCHAN_STAT_PAR_ERR_1                    (1L<<7)
1407 #define BNX2_DMA_RCHAN_STAT_COMP_CODE_2                  (0x7L<<8)
1408 #define BNX2_DMA_RCHAN_STAT_PAR_ERR_2                    (1L<<11)
1409 #define BNX2_DMA_RCHAN_STAT_COMP_CODE_3                  (0x7L<<12)
1410 #define BNX2_DMA_RCHAN_STAT_PAR_ERR_3                    (1L<<15)
1411 #define BNX2_DMA_RCHAN_STAT_COMP_CODE_4                  (0x7L<<16)
1412 #define BNX2_DMA_RCHAN_STAT_PAR_ERR_4                    (1L<<19)
1413 #define BNX2_DMA_RCHAN_STAT_COMP_CODE_5                  (0x7L<<20)
1414 #define BNX2_DMA_RCHAN_STAT_PAR_ERR_5                    (1L<<23)
1415 #define BNX2_DMA_RCHAN_STAT_COMP_CODE_6                  (0x7L<<24)
1416 #define BNX2_DMA_RCHAN_STAT_PAR_ERR_6                    (1L<<27)
1417 #define BNX2_DMA_RCHAN_STAT_COMP_CODE_7                  (0x7L<<28)
1418 #define BNX2_DMA_RCHAN_STAT_PAR_ERR_7                    (1L<<31)
1419
1420 #define BNX2_DMA_WCHAN_STAT                             0x00000c34
1421 #define BNX2_DMA_WCHAN_STAT_COMP_CODE_0                  (0x7L<<0)
1422 #define BNX2_DMA_WCHAN_STAT_PAR_ERR_0                    (1L<<3)
1423 #define BNX2_DMA_WCHAN_STAT_COMP_CODE_1                  (0x7L<<4)
1424 #define BNX2_DMA_WCHAN_STAT_PAR_ERR_1                    (1L<<7)
1425 #define BNX2_DMA_WCHAN_STAT_COMP_CODE_2                  (0x7L<<8)
1426 #define BNX2_DMA_WCHAN_STAT_PAR_ERR_2                    (1L<<11)
1427 #define BNX2_DMA_WCHAN_STAT_COMP_CODE_3                  (0x7L<<12)
1428 #define BNX2_DMA_WCHAN_STAT_PAR_ERR_3                    (1L<<15)
1429 #define BNX2_DMA_WCHAN_STAT_COMP_CODE_4                  (0x7L<<16)
1430 #define BNX2_DMA_WCHAN_STAT_PAR_ERR_4                    (1L<<19)
1431 #define BNX2_DMA_WCHAN_STAT_COMP_CODE_5                  (0x7L<<20)
1432 #define BNX2_DMA_WCHAN_STAT_PAR_ERR_5                    (1L<<23)
1433 #define BNX2_DMA_WCHAN_STAT_COMP_CODE_6                  (0x7L<<24)
1434 #define BNX2_DMA_WCHAN_STAT_PAR_ERR_6                    (1L<<27)
1435 #define BNX2_DMA_WCHAN_STAT_COMP_CODE_7                  (0x7L<<28)
1436 #define BNX2_DMA_WCHAN_STAT_PAR_ERR_7                    (1L<<31)
1437
1438 #define BNX2_DMA_RCHAN_ASSIGNMENT                       0x00000c38
1439 #define BNX2_DMA_RCHAN_ASSIGNMENT_0                      (0xfL<<0)
1440 #define BNX2_DMA_RCHAN_ASSIGNMENT_1                      (0xfL<<4)
1441 #define BNX2_DMA_RCHAN_ASSIGNMENT_2                      (0xfL<<8)
1442 #define BNX2_DMA_RCHAN_ASSIGNMENT_3                      (0xfL<<12)
1443 #define BNX2_DMA_RCHAN_ASSIGNMENT_4                      (0xfL<<16)
1444 #define BNX2_DMA_RCHAN_ASSIGNMENT_5                      (0xfL<<20)
1445 #define BNX2_DMA_RCHAN_ASSIGNMENT_6                      (0xfL<<24)
1446 #define BNX2_DMA_RCHAN_ASSIGNMENT_7                      (0xfL<<28)
1447
1448 #define BNX2_DMA_WCHAN_ASSIGNMENT                       0x00000c3c
1449 #define BNX2_DMA_WCHAN_ASSIGNMENT_0                      (0xfL<<0)
1450 #define BNX2_DMA_WCHAN_ASSIGNMENT_1                      (0xfL<<4)
1451 #define BNX2_DMA_WCHAN_ASSIGNMENT_2                      (0xfL<<8)
1452 #define BNX2_DMA_WCHAN_ASSIGNMENT_3                      (0xfL<<12)
1453 #define BNX2_DMA_WCHAN_ASSIGNMENT_4                      (0xfL<<16)
1454 #define BNX2_DMA_WCHAN_ASSIGNMENT_5                      (0xfL<<20)
1455 #define BNX2_DMA_WCHAN_ASSIGNMENT_6                      (0xfL<<24)
1456 #define BNX2_DMA_WCHAN_ASSIGNMENT_7                      (0xfL<<28)
1457
1458 #define BNX2_DMA_RCHAN_STAT_00                          0x00000c40
1459 #define BNX2_DMA_RCHAN_STAT_00_RCHAN_STA_HOST_ADDR_LOW   (0xffffffffL<<0)
1460
1461 #define BNX2_DMA_RCHAN_STAT_01                          0x00000c44
1462 #define BNX2_DMA_RCHAN_STAT_01_RCHAN_STA_HOST_ADDR_HIGH  (0xffffffffL<<0)
1463
1464 #define BNX2_DMA_RCHAN_STAT_02                          0x00000c48
1465 #define BNX2_DMA_RCHAN_STAT_02_LENGTH                    (0xffffL<<0)
1466 #define BNX2_DMA_RCHAN_STAT_02_WORD_SWAP                 (1L<<16)
1467 #define BNX2_DMA_RCHAN_STAT_02_BYTE_SWAP                 (1L<<17)
1468 #define BNX2_DMA_RCHAN_STAT_02_PRIORITY_LVL              (1L<<18)
1469
1470 #define BNX2_DMA_RCHAN_STAT_10                          0x00000c4c
1471 #define BNX2_DMA_RCHAN_STAT_11                          0x00000c50
1472 #define BNX2_DMA_RCHAN_STAT_12                          0x00000c54
1473 #define BNX2_DMA_RCHAN_STAT_20                          0x00000c58
1474 #define BNX2_DMA_RCHAN_STAT_21                          0x00000c5c
1475 #define BNX2_DMA_RCHAN_STAT_22                          0x00000c60
1476 #define BNX2_DMA_RCHAN_STAT_30                          0x00000c64
1477 #define BNX2_DMA_RCHAN_STAT_31                          0x00000c68
1478 #define BNX2_DMA_RCHAN_STAT_32                          0x00000c6c
1479 #define BNX2_DMA_RCHAN_STAT_40                          0x00000c70
1480 #define BNX2_DMA_RCHAN_STAT_41                          0x00000c74
1481 #define BNX2_DMA_RCHAN_STAT_42                          0x00000c78
1482 #define BNX2_DMA_RCHAN_STAT_50                          0x00000c7c
1483 #define BNX2_DMA_RCHAN_STAT_51                          0x00000c80
1484 #define BNX2_DMA_RCHAN_STAT_52                          0x00000c84
1485 #define BNX2_DMA_RCHAN_STAT_60                          0x00000c88
1486 #define BNX2_DMA_RCHAN_STAT_61                          0x00000c8c
1487 #define BNX2_DMA_RCHAN_STAT_62                          0x00000c90
1488 #define BNX2_DMA_RCHAN_STAT_70                          0x00000c94
1489 #define BNX2_DMA_RCHAN_STAT_71                          0x00000c98
1490 #define BNX2_DMA_RCHAN_STAT_72                          0x00000c9c
1491 #define BNX2_DMA_WCHAN_STAT_00                          0x00000ca0
1492 #define BNX2_DMA_WCHAN_STAT_00_WCHAN_STA_HOST_ADDR_LOW   (0xffffffffL<<0)
1493
1494 #define BNX2_DMA_WCHAN_STAT_01                          0x00000ca4
1495 #define BNX2_DMA_WCHAN_STAT_01_WCHAN_STA_HOST_ADDR_HIGH  (0xffffffffL<<0)
1496
1497 #define BNX2_DMA_WCHAN_STAT_02                          0x00000ca8
1498 #define BNX2_DMA_WCHAN_STAT_02_LENGTH                    (0xffffL<<0)
1499 #define BNX2_DMA_WCHAN_STAT_02_WORD_SWAP                 (1L<<16)
1500 #define BNX2_DMA_WCHAN_STAT_02_BYTE_SWAP                 (1L<<17)
1501 #define BNX2_DMA_WCHAN_STAT_02_PRIORITY_LVL              (1L<<18)
1502
1503 #define BNX2_DMA_WCHAN_STAT_10                          0x00000cac
1504 #define BNX2_DMA_WCHAN_STAT_11                          0x00000cb0
1505 #define BNX2_DMA_WCHAN_STAT_12                          0x00000cb4
1506 #define BNX2_DMA_WCHAN_STAT_20                          0x00000cb8
1507 #define BNX2_DMA_WCHAN_STAT_21                          0x00000cbc
1508 #define BNX2_DMA_WCHAN_STAT_22                          0x00000cc0
1509 #define BNX2_DMA_WCHAN_STAT_30                          0x00000cc4
1510 #define BNX2_DMA_WCHAN_STAT_31                          0x00000cc8
1511 #define BNX2_DMA_WCHAN_STAT_32                          0x00000ccc
1512 #define BNX2_DMA_WCHAN_STAT_40                          0x00000cd0
1513 #define BNX2_DMA_WCHAN_STAT_41                          0x00000cd4
1514 #define BNX2_DMA_WCHAN_STAT_42                          0x00000cd8
1515 #define BNX2_DMA_WCHAN_STAT_50                          0x00000cdc
1516 #define BNX2_DMA_WCHAN_STAT_51                          0x00000ce0
1517 #define BNX2_DMA_WCHAN_STAT_52                          0x00000ce4
1518 #define BNX2_DMA_WCHAN_STAT_60                          0x00000ce8
1519 #define BNX2_DMA_WCHAN_STAT_61                          0x00000cec
1520 #define BNX2_DMA_WCHAN_STAT_62                          0x00000cf0
1521 #define BNX2_DMA_WCHAN_STAT_70                          0x00000cf4
1522 #define BNX2_DMA_WCHAN_STAT_71                          0x00000cf8
1523 #define BNX2_DMA_WCHAN_STAT_72                          0x00000cfc
1524 #define BNX2_DMA_ARB_STAT_00                            0x00000d00
1525 #define BNX2_DMA_ARB_STAT_00_MASTER                      (0xffffL<<0)
1526 #define BNX2_DMA_ARB_STAT_00_MASTER_ENC                  (0xffL<<16)
1527 #define BNX2_DMA_ARB_STAT_00_CUR_BINMSTR                 (0xffL<<24)
1528
1529 #define BNX2_DMA_ARB_STAT_01                            0x00000d04
1530 #define BNX2_DMA_ARB_STAT_01_LPR_RPTR                    (0xfL<<0)
1531 #define BNX2_DMA_ARB_STAT_01_LPR_WPTR                    (0xfL<<4)
1532 #define BNX2_DMA_ARB_STAT_01_LPB_RPTR                    (0xfL<<8)
1533 #define BNX2_DMA_ARB_STAT_01_LPB_WPTR                    (0xfL<<12)
1534 #define BNX2_DMA_ARB_STAT_01_HPR_RPTR                    (0xfL<<16)
1535 #define BNX2_DMA_ARB_STAT_01_HPR_WPTR                    (0xfL<<20)
1536 #define BNX2_DMA_ARB_STAT_01_HPB_RPTR                    (0xfL<<24)
1537 #define BNX2_DMA_ARB_STAT_01_HPB_WPTR                    (0xfL<<28)
1538
1539 #define BNX2_DMA_FUSE_CTRL0_CMD                         0x00000f00
1540 #define BNX2_DMA_FUSE_CTRL0_CMD_PWRUP_DONE               (1L<<0)
1541 #define BNX2_DMA_FUSE_CTRL0_CMD_SHIFT_DONE               (1L<<1)
1542 #define BNX2_DMA_FUSE_CTRL0_CMD_SHIFT                    (1L<<2)
1543 #define BNX2_DMA_FUSE_CTRL0_CMD_LOAD                     (1L<<3)
1544 #define BNX2_DMA_FUSE_CTRL0_CMD_SEL                      (0xfL<<8)
1545
1546 #define BNX2_DMA_FUSE_CTRL0_DATA                        0x00000f04
1547 #define BNX2_DMA_FUSE_CTRL1_CMD                         0x00000f08
1548 #define BNX2_DMA_FUSE_CTRL1_CMD_PWRUP_DONE               (1L<<0)
1549 #define BNX2_DMA_FUSE_CTRL1_CMD_SHIFT_DONE               (1L<<1)
1550 #define BNX2_DMA_FUSE_CTRL1_CMD_SHIFT                    (1L<<2)
1551 #define BNX2_DMA_FUSE_CTRL1_CMD_LOAD                     (1L<<3)
1552 #define BNX2_DMA_FUSE_CTRL1_CMD_SEL                      (0xfL<<8)
1553
1554 #define BNX2_DMA_FUSE_CTRL1_DATA                        0x00000f0c
1555 #define BNX2_DMA_FUSE_CTRL2_CMD                         0x00000f10
1556 #define BNX2_DMA_FUSE_CTRL2_CMD_PWRUP_DONE               (1L<<0)
1557 #define BNX2_DMA_FUSE_CTRL2_CMD_SHIFT_DONE               (1L<<1)
1558 #define BNX2_DMA_FUSE_CTRL2_CMD_SHIFT                    (1L<<2)
1559 #define BNX2_DMA_FUSE_CTRL2_CMD_LOAD                     (1L<<3)
1560 #define BNX2_DMA_FUSE_CTRL2_CMD_SEL                      (0xfL<<8)
1561
1562 #define BNX2_DMA_FUSE_CTRL2_DATA                        0x00000f14
1563
1564
1565 /*
1566  *  context_reg definition
1567  *  offset: 0x1000
1568  */
1569 #define BNX2_CTX_COMMAND                                0x00001000
1570 #define BNX2_CTX_COMMAND_ENABLED                         (1L<<0)
1571
1572 #define BNX2_CTX_STATUS                                 0x00001004
1573 #define BNX2_CTX_STATUS_LOCK_WAIT                        (1L<<0)
1574 #define BNX2_CTX_STATUS_READ_STAT                        (1L<<16)
1575 #define BNX2_CTX_STATUS_WRITE_STAT                       (1L<<17)
1576 #define BNX2_CTX_STATUS_ACC_STALL_STAT                   (1L<<18)
1577 #define BNX2_CTX_STATUS_LOCK_STALL_STAT                  (1L<<19)
1578
1579 #define BNX2_CTX_VIRT_ADDR                              0x00001008
1580 #define BNX2_CTX_VIRT_ADDR_VIRT_ADDR                     (0x7fffL<<6)
1581
1582 #define BNX2_CTX_PAGE_TBL                               0x0000100c
1583 #define BNX2_CTX_PAGE_TBL_PAGE_TBL                       (0x3fffL<<6)
1584
1585 #define BNX2_CTX_DATA_ADR                               0x00001010
1586 #define BNX2_CTX_DATA_ADR_DATA_ADR                       (0x7ffffL<<2)
1587
1588 #define BNX2_CTX_DATA                                   0x00001014
1589 #define BNX2_CTX_LOCK                                   0x00001018
1590 #define BNX2_CTX_LOCK_TYPE                               (0x7L<<0)
1591 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_VOID                (0x0L<<0)
1592 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE            (0x7L<<0)
1593 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL            (0x1L<<0)
1594 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TX                  (0x2L<<0)
1595 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TIMER               (0x4L<<0)
1596 #define BNX2_CTX_LOCK_CID_VALUE                          (0x3fffL<<7)
1597 #define BNX2_CTX_LOCK_GRANTED                            (1L<<26)
1598 #define BNX2_CTX_LOCK_MODE                               (0x7L<<27)
1599 #define BNX2_CTX_LOCK_MODE_UNLOCK                        (0x0L<<27)
1600 #define BNX2_CTX_LOCK_MODE_IMMEDIATE                     (0x1L<<27)
1601 #define BNX2_CTX_LOCK_MODE_SURE                          (0x2L<<27)
1602 #define BNX2_CTX_LOCK_STATUS                             (1L<<30)
1603 #define BNX2_CTX_LOCK_REQ                                (1L<<31)
1604
1605 #define BNX2_CTX_ACCESS_STATUS                          0x00001040
1606 #define BNX2_CTX_ACCESS_STATUS_MASTERENCODED             (0xfL<<0)
1607 #define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYSM            (0x3L<<10)
1608 #define BNX2_CTX_ACCESS_STATUS_PAGETABLEINITSM           (0x3L<<12)
1609 #define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM        (0x3L<<14)
1610 #define BNX2_CTX_ACCESS_STATUS_QUALIFIED_REQUEST         (0x7ffL<<17)
1611
1612 #define BNX2_CTX_DBG_LOCK_STATUS                        0x00001044
1613 #define BNX2_CTX_DBG_LOCK_STATUS_SM                      (0x3ffL<<0)
1614 #define BNX2_CTX_DBG_LOCK_STATUS_MATCH                   (0x3ffL<<22)
1615
1616 #define BNX2_CTX_CHNL_LOCK_STATUS_0                     0x00001080
1617 #define BNX2_CTX_CHNL_LOCK_STATUS_0_CID                  (0x3fffL<<0)
1618 #define BNX2_CTX_CHNL_LOCK_STATUS_0_TYPE                 (0x3L<<14)
1619 #define BNX2_CTX_CHNL_LOCK_STATUS_0_MODE                 (1L<<16)
1620
1621 #define BNX2_CTX_CHNL_LOCK_STATUS_1                     0x00001084
1622 #define BNX2_CTX_CHNL_LOCK_STATUS_2                     0x00001088
1623 #define BNX2_CTX_CHNL_LOCK_STATUS_3                     0x0000108c
1624 #define BNX2_CTX_CHNL_LOCK_STATUS_4                     0x00001090
1625 #define BNX2_CTX_CHNL_LOCK_STATUS_5                     0x00001094
1626 #define BNX2_CTX_CHNL_LOCK_STATUS_6                     0x00001098
1627 #define BNX2_CTX_CHNL_LOCK_STATUS_7                     0x0000109c
1628 #define BNX2_CTX_CHNL_LOCK_STATUS_8                     0x000010a0
1629
1630
1631 /*
1632  *  emac_reg definition
1633  *  offset: 0x1400
1634  */
1635 #define BNX2_EMAC_MODE                                  0x00001400
1636 #define BNX2_EMAC_MODE_RESET                             (1L<<0)
1637 #define BNX2_EMAC_MODE_HALF_DUPLEX                       (1L<<1)
1638 #define BNX2_EMAC_MODE_PORT                              (0x3L<<2)
1639 #define BNX2_EMAC_MODE_PORT_NONE                         (0L<<2)
1640 #define BNX2_EMAC_MODE_PORT_MII                          (1L<<2)
1641 #define BNX2_EMAC_MODE_PORT_GMII                         (2L<<2)
1642 #define BNX2_EMAC_MODE_PORT_MII_10                       (3L<<2)
1643 #define BNX2_EMAC_MODE_MAC_LOOP                          (1L<<4)
1644 #define BNX2_EMAC_MODE_25G                               (1L<<5)
1645 #define BNX2_EMAC_MODE_TAGGED_MAC_CTL                    (1L<<7)
1646 #define BNX2_EMAC_MODE_TX_BURST                          (1L<<8)
1647 #define BNX2_EMAC_MODE_MAX_DEFER_DROP_ENA                (1L<<9)
1648 #define BNX2_EMAC_MODE_EXT_LINK_POL                      (1L<<10)
1649 #define BNX2_EMAC_MODE_FORCE_LINK                        (1L<<11)
1650 #define BNX2_EMAC_MODE_MPKT                              (1L<<18)
1651 #define BNX2_EMAC_MODE_MPKT_RCVD                         (1L<<19)
1652 #define BNX2_EMAC_MODE_ACPI_RCVD                         (1L<<20)
1653
1654 #define BNX2_EMAC_STATUS                                0x00001404
1655 #define BNX2_EMAC_STATUS_LINK                            (1L<<11)
1656 #define BNX2_EMAC_STATUS_LINK_CHANGE                     (1L<<12)
1657 #define BNX2_EMAC_STATUS_MI_COMPLETE                     (1L<<22)
1658 #define BNX2_EMAC_STATUS_MI_INT                          (1L<<23)
1659 #define BNX2_EMAC_STATUS_AP_ERROR                        (1L<<24)
1660 #define BNX2_EMAC_STATUS_PARITY_ERROR_STATE              (1L<<31)
1661
1662 #define BNX2_EMAC_ATTENTION_ENA                         0x00001408
1663 #define BNX2_EMAC_ATTENTION_ENA_LINK                     (1L<<11)
1664 #define BNX2_EMAC_ATTENTION_ENA_MI_COMPLETE              (1L<<22)
1665 #define BNX2_EMAC_ATTENTION_ENA_MI_INT                   (1L<<23)
1666 #define BNX2_EMAC_ATTENTION_ENA_AP_ERROR                 (1L<<24)
1667
1668 #define BNX2_EMAC_LED                                   0x0000140c
1669 #define BNX2_EMAC_LED_OVERRIDE                           (1L<<0)
1670 #define BNX2_EMAC_LED_1000MB_OVERRIDE                    (1L<<1)
1671 #define BNX2_EMAC_LED_100MB_OVERRIDE                     (1L<<2)
1672 #define BNX2_EMAC_LED_10MB_OVERRIDE                      (1L<<3)
1673 #define BNX2_EMAC_LED_TRAFFIC_OVERRIDE                   (1L<<4)
1674 #define BNX2_EMAC_LED_BLNK_TRAFFIC                       (1L<<5)
1675 #define BNX2_EMAC_LED_TRAFFIC                            (1L<<6)
1676 #define BNX2_EMAC_LED_1000MB                             (1L<<7)
1677 #define BNX2_EMAC_LED_100MB                              (1L<<8)
1678 #define BNX2_EMAC_LED_10MB                               (1L<<9)
1679 #define BNX2_EMAC_LED_TRAFFIC_STAT                       (1L<<10)
1680 #define BNX2_EMAC_LED_BLNK_RATE                          (0xfffL<<19)
1681 #define BNX2_EMAC_LED_BLNK_RATE_ENA                      (1L<<31)
1682
1683 #define BNX2_EMAC_MAC_MATCH0                            0x00001410
1684 #define BNX2_EMAC_MAC_MATCH1                            0x00001414
1685 #define BNX2_EMAC_MAC_MATCH2                            0x00001418
1686 #define BNX2_EMAC_MAC_MATCH3                            0x0000141c
1687 #define BNX2_EMAC_MAC_MATCH4                            0x00001420
1688 #define BNX2_EMAC_MAC_MATCH5                            0x00001424
1689 #define BNX2_EMAC_MAC_MATCH6                            0x00001428
1690 #define BNX2_EMAC_MAC_MATCH7                            0x0000142c
1691 #define BNX2_EMAC_MAC_MATCH8                            0x00001430
1692 #define BNX2_EMAC_MAC_MATCH9                            0x00001434
1693 #define BNX2_EMAC_MAC_MATCH10                           0x00001438
1694 #define BNX2_EMAC_MAC_MATCH11                           0x0000143c
1695 #define BNX2_EMAC_MAC_MATCH12                           0x00001440
1696 #define BNX2_EMAC_MAC_MATCH13                           0x00001444
1697 #define BNX2_EMAC_MAC_MATCH14                           0x00001448
1698 #define BNX2_EMAC_MAC_MATCH15                           0x0000144c
1699 #define BNX2_EMAC_MAC_MATCH16                           0x00001450
1700 #define BNX2_EMAC_MAC_MATCH17                           0x00001454
1701 #define BNX2_EMAC_MAC_MATCH18                           0x00001458
1702 #define BNX2_EMAC_MAC_MATCH19                           0x0000145c
1703 #define BNX2_EMAC_MAC_MATCH20                           0x00001460
1704 #define BNX2_EMAC_MAC_MATCH21                           0x00001464
1705 #define BNX2_EMAC_MAC_MATCH22                           0x00001468
1706 #define BNX2_EMAC_MAC_MATCH23                           0x0000146c
1707 #define BNX2_EMAC_MAC_MATCH24                           0x00001470
1708 #define BNX2_EMAC_MAC_MATCH25                           0x00001474
1709 #define BNX2_EMAC_MAC_MATCH26                           0x00001478
1710 #define BNX2_EMAC_MAC_MATCH27                           0x0000147c
1711 #define BNX2_EMAC_MAC_MATCH28                           0x00001480
1712 #define BNX2_EMAC_MAC_MATCH29                           0x00001484
1713 #define BNX2_EMAC_MAC_MATCH30                           0x00001488
1714 #define BNX2_EMAC_MAC_MATCH31                           0x0000148c
1715 #define BNX2_EMAC_BACKOFF_SEED                          0x00001498
1716 #define BNX2_EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED         (0x3ffL<<0)
1717
1718 #define BNX2_EMAC_RX_MTU_SIZE                           0x0000149c
1719 #define BNX2_EMAC_RX_MTU_SIZE_MTU_SIZE                   (0xffffL<<0)
1720 #define BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA                  (1L<<31)
1721
1722 #define BNX2_EMAC_SERDES_CNTL                           0x000014a4
1723 #define BNX2_EMAC_SERDES_CNTL_RXR                        (0x7L<<0)
1724 #define BNX2_EMAC_SERDES_CNTL_RXG                        (0x3L<<3)
1725 #define BNX2_EMAC_SERDES_CNTL_RXCKSEL                    (1L<<6)
1726 #define BNX2_EMAC_SERDES_CNTL_TXBIAS                     (0x7L<<7)
1727 #define BNX2_EMAC_SERDES_CNTL_BGMAX                      (1L<<10)
1728 #define BNX2_EMAC_SERDES_CNTL_BGMIN                      (1L<<11)
1729 #define BNX2_EMAC_SERDES_CNTL_TXMODE                     (1L<<12)
1730 #define BNX2_EMAC_SERDES_CNTL_TXEDGE                     (1L<<13)
1731 #define BNX2_EMAC_SERDES_CNTL_SERDES_MODE                (1L<<14)
1732 #define BNX2_EMAC_SERDES_CNTL_PLLTEST                    (1L<<15)
1733 #define BNX2_EMAC_SERDES_CNTL_CDET_EN                    (1L<<16)
1734 #define BNX2_EMAC_SERDES_CNTL_TBI_LBK                    (1L<<17)
1735 #define BNX2_EMAC_SERDES_CNTL_REMOTE_LBK                 (1L<<18)
1736 #define BNX2_EMAC_SERDES_CNTL_REV_PHASE                  (1L<<19)
1737 #define BNX2_EMAC_SERDES_CNTL_REGCTL12                   (0x3L<<20)
1738 #define BNX2_EMAC_SERDES_CNTL_REGCTL25                   (0x3L<<22)
1739
1740 #define BNX2_EMAC_SERDES_STATUS                         0x000014a8
1741 #define BNX2_EMAC_SERDES_STATUS_RX_STAT                  (0xffL<<0)
1742 #define BNX2_EMAC_SERDES_STATUS_COMMA_DET                (1L<<8)
1743
1744 #define BNX2_EMAC_MDIO_COMM                             0x000014ac
1745 #define BNX2_EMAC_MDIO_COMM_DATA                         (0xffffL<<0)
1746 #define BNX2_EMAC_MDIO_COMM_REG_ADDR                     (0x1fL<<16)
1747 #define BNX2_EMAC_MDIO_COMM_PHY_ADDR                     (0x1fL<<21)
1748 #define BNX2_EMAC_MDIO_COMM_COMMAND                      (0x3L<<26)
1749 #define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0          (0L<<26)
1750 #define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE                (1L<<26)
1751 #define BNX2_EMAC_MDIO_COMM_COMMAND_READ                 (2L<<26)
1752 #define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3          (3L<<26)
1753 #define BNX2_EMAC_MDIO_COMM_FAIL                         (1L<<28)
1754 #define BNX2_EMAC_MDIO_COMM_START_BUSY                   (1L<<29)
1755 #define BNX2_EMAC_MDIO_COMM_DISEXT                       (1L<<30)
1756
1757 #define BNX2_EMAC_MDIO_STATUS                           0x000014b0
1758 #define BNX2_EMAC_MDIO_STATUS_LINK                       (1L<<0)
1759 #define BNX2_EMAC_MDIO_STATUS_10MB                       (1L<<1)
1760
1761 #define BNX2_EMAC_MDIO_MODE                             0x000014b4
1762 #define BNX2_EMAC_MDIO_MODE_SHORT_PREAMBLE               (1L<<1)
1763 #define BNX2_EMAC_MDIO_MODE_AUTO_POLL                    (1L<<4)
1764 #define BNX2_EMAC_MDIO_MODE_BIT_BANG                     (1L<<8)
1765 #define BNX2_EMAC_MDIO_MODE_MDIO                         (1L<<9)
1766 #define BNX2_EMAC_MDIO_MODE_MDIO_OE                      (1L<<10)
1767 #define BNX2_EMAC_MDIO_MODE_MDC                          (1L<<11)
1768 #define BNX2_EMAC_MDIO_MODE_MDINT                        (1L<<12)
1769 #define BNX2_EMAC_MDIO_MODE_CLOCK_CNT                    (0x1fL<<16)
1770
1771 #define BNX2_EMAC_MDIO_AUTO_STATUS                      0x000014b8
1772 #define BNX2_EMAC_MDIO_AUTO_STATUS_AUTO_ERR              (1L<<0)
1773
1774 #define BNX2_EMAC_TX_MODE                               0x000014bc
1775 #define BNX2_EMAC_TX_MODE_RESET                          (1L<<0)
1776 #define BNX2_EMAC_TX_MODE_EXT_PAUSE_EN                   (1L<<3)
1777 #define BNX2_EMAC_TX_MODE_FLOW_EN                        (1L<<4)
1778 #define BNX2_EMAC_TX_MODE_BIG_BACKOFF                    (1L<<5)
1779 #define BNX2_EMAC_TX_MODE_LONG_PAUSE                     (1L<<6)
1780 #define BNX2_EMAC_TX_MODE_LINK_AWARE                     (1L<<7)
1781
1782 #define BNX2_EMAC_TX_STATUS                             0x000014c0
1783 #define BNX2_EMAC_TX_STATUS_XOFFED                       (1L<<0)
1784 #define BNX2_EMAC_TX_STATUS_XOFF_SENT                    (1L<<1)
1785 #define BNX2_EMAC_TX_STATUS_XON_SENT                     (1L<<2)
1786 #define BNX2_EMAC_TX_STATUS_LINK_UP                      (1L<<3)
1787 #define BNX2_EMAC_TX_STATUS_UNDERRUN                     (1L<<4)
1788
1789 #define BNX2_EMAC_TX_LENGTHS                            0x000014c4
1790 #define BNX2_EMAC_TX_LENGTHS_SLOT                        (0xffL<<0)
1791 #define BNX2_EMAC_TX_LENGTHS_IPG                         (0xfL<<8)
1792 #define BNX2_EMAC_TX_LENGTHS_IPG_CRS                     (0x3L<<12)
1793
1794 #define BNX2_EMAC_RX_MODE                               0x000014c8
1795 #define BNX2_EMAC_RX_MODE_RESET                          (1L<<0)
1796 #define BNX2_EMAC_RX_MODE_FLOW_EN                        (1L<<2)
1797 #define BNX2_EMAC_RX_MODE_KEEP_MAC_CONTROL               (1L<<3)
1798 #define BNX2_EMAC_RX_MODE_KEEP_PAUSE                     (1L<<4)
1799 #define BNX2_EMAC_RX_MODE_ACCEPT_OVERSIZE                (1L<<5)
1800 #define BNX2_EMAC_RX_MODE_ACCEPT_RUNTS                   (1L<<6)
1801 #define BNX2_EMAC_RX_MODE_LLC_CHK                        (1L<<7)
1802 #define BNX2_EMAC_RX_MODE_PROMISCUOUS                    (1L<<8)
1803 #define BNX2_EMAC_RX_MODE_NO_CRC_CHK                     (1L<<9)
1804 #define BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG                  (1L<<10)
1805 #define BNX2_EMAC_RX_MODE_FILT_BROADCAST                 (1L<<11)
1806 #define BNX2_EMAC_RX_MODE_SORT_MODE                      (1L<<12)
1807
1808 #define BNX2_EMAC_RX_STATUS                             0x000014cc
1809 #define BNX2_EMAC_RX_STATUS_FFED                         (1L<<0)
1810 #define BNX2_EMAC_RX_STATUS_FF_RECEIVED                  (1L<<1)
1811 #define BNX2_EMAC_RX_STATUS_N_RECEIVED                   (1L<<2)
1812
1813 #define BNX2_EMAC_MULTICAST_HASH0                       0x000014d0
1814 #define BNX2_EMAC_MULTICAST_HASH1                       0x000014d4
1815 #define BNX2_EMAC_MULTICAST_HASH2                       0x000014d8
1816 #define BNX2_EMAC_MULTICAST_HASH3                       0x000014dc
1817 #define BNX2_EMAC_MULTICAST_HASH4                       0x000014e0
1818 #define BNX2_EMAC_MULTICAST_HASH5                       0x000014e4
1819 #define BNX2_EMAC_MULTICAST_HASH6                       0x000014e8
1820 #define BNX2_EMAC_MULTICAST_HASH7                       0x000014ec
1821 #define BNX2_EMAC_RX_STAT_IFHCINOCTETS                  0x00001500
1822 #define BNX2_EMAC_RX_STAT_IFHCINBADOCTETS               0x00001504
1823 #define BNX2_EMAC_RX_STAT_ETHERSTATSFRAGMENTS           0x00001508
1824 #define BNX2_EMAC_RX_STAT_IFHCINUCASTPKTS               0x0000150c
1825 #define BNX2_EMAC_RX_STAT_IFHCINMULTICASTPKTS           0x00001510
1826 #define BNX2_EMAC_RX_STAT_IFHCINBROADCASTPKTS           0x00001514
1827 #define BNX2_EMAC_RX_STAT_DOT3STATSFCSERRORS            0x00001518
1828 #define BNX2_EMAC_RX_STAT_DOT3STATSALIGNMENTERRORS      0x0000151c
1829 #define BNX2_EMAC_RX_STAT_DOT3STATSCARRIERSENSEERRORS   0x00001520
1830 #define BNX2_EMAC_RX_STAT_XONPAUSEFRAMESRECEIVED        0x00001524
1831 #define BNX2_EMAC_RX_STAT_XOFFPAUSEFRAMESRECEIVED       0x00001528
1832 #define BNX2_EMAC_RX_STAT_MACCONTROLFRAMESRECEIVED      0x0000152c
1833 #define BNX2_EMAC_RX_STAT_XOFFSTATEENTERED              0x00001530
1834 #define BNX2_EMAC_RX_STAT_DOT3STATSFRAMESTOOLONG        0x00001534
1835 #define BNX2_EMAC_RX_STAT_ETHERSTATSJABBERS             0x00001538
1836 #define BNX2_EMAC_RX_STAT_ETHERSTATSUNDERSIZEPKTS       0x0000153c
1837 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS64OCTETS        0x00001540
1838 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS     0x00001544
1839 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS    0x00001548
1840 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS    0x0000154c
1841 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS   0x00001550
1842 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS  0x00001554
1843 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS  0x00001558
1844 #define BNX2_EMAC_RXMAC_DEBUG0                          0x0000155c
1845 #define BNX2_EMAC_RXMAC_DEBUG1                          0x00001560
1846 #define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT      (1L<<0)
1847 #define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE          (1L<<1)
1848 #define BNX2_EMAC_RXMAC_DEBUG1_BAD_CRC                   (1L<<2)
1849 #define BNX2_EMAC_RXMAC_DEBUG1_RX_ERROR                  (1L<<3)
1850 #define BNX2_EMAC_RXMAC_DEBUG1_ALIGN_ERROR               (1L<<4)
1851 #define BNX2_EMAC_RXMAC_DEBUG1_LAST_DATA                 (1L<<5)
1852 #define BNX2_EMAC_RXMAC_DEBUG1_ODD_BYTE_START            (1L<<6)
1853 #define BNX2_EMAC_RXMAC_DEBUG1_BYTE_COUNT                (0xffffL<<7)
1854 #define BNX2_EMAC_RXMAC_DEBUG1_SLOT_TIME                 (0xffL<<23)
1855
1856 #define BNX2_EMAC_RXMAC_DEBUG2                          0x00001564
1857 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE                  (0x7L<<0)
1858 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_IDLE             (0x0L<<0)
1859 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SFD              (0x1L<<0)
1860 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_DATA             (0x2L<<0)
1861 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP            (0x3L<<0)
1862 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_EXT              (0x4L<<0)
1863 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_DROP             (0x5L<<0)
1864 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SDROP            (0x6L<<0)
1865 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_FC               (0x7L<<0)
1866 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE                 (0xfL<<3)
1867 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE            (0x0L<<3)
1868 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0           (0x1L<<3)
1869 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1           (0x2L<<3)
1870 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2           (0x3L<<3)
1871 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3           (0x4L<<3)
1872 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT           (0x5L<<3)
1873 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT            (0x6L<<3)
1874 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS          (0x7L<<3)
1875 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_LAST            (0x8L<<3)
1876 #define BNX2_EMAC_RXMAC_DEBUG2_BYTE_IN                   (0xffL<<7)
1877 #define BNX2_EMAC_RXMAC_DEBUG2_FALSEC                    (1L<<15)
1878 #define BNX2_EMAC_RXMAC_DEBUG2_TAGGED                    (1L<<16)
1879 #define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE               (1L<<18)
1880 #define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE          (0L<<18)
1881 #define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED        (1L<<18)
1882 #define BNX2_EMAC_RXMAC_DEBUG2_SE_COUNTER                (0xfL<<19)
1883 #define BNX2_EMAC_RXMAC_DEBUG2_QUANTA                    (0x1fL<<23)
1884
1885 #define BNX2_EMAC_RXMAC_DEBUG3                          0x00001568
1886 #define BNX2_EMAC_RXMAC_DEBUG3_PAUSE_CTR                 (0xffffL<<0)
1887 #define BNX2_EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR             (0xffffL<<16)
1888
1889 #define BNX2_EMAC_RXMAC_DEBUG4                          0x0000156c
1890 #define BNX2_EMAC_RXMAC_DEBUG4_TYPE_FIELD                (0xffffL<<0)
1891 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE                (0x3fL<<16)
1892 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE           (0x0L<<16)
1893 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2          (0x1L<<16)
1894 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3          (0x2L<<16)
1895 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI            (0x3L<<16)
1896 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2          (0x7L<<16)
1897 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3          (0x5L<<16)
1898 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1           (0x6L<<16)
1899 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2           (0x7L<<16)
1900 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3           (0x8L<<16)
1901 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2            (0x9L<<16)
1902 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC3            (0xaL<<16)
1903 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1         (0xeL<<16)
1904 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2         (0xfL<<16)
1905 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK         (0x10L<<16)
1906 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC             (0x11L<<16)
1907 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC2            (0x12L<<16)
1908 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC3            (0x13L<<16)
1909 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1           (0x14L<<16)
1910 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2           (0x15L<<16)
1911 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3           (0x16L<<16)
1912 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE          (0x17L<<16)
1913 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC             (0x18L<<16)
1914 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE          (0x19L<<16)
1915 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_CMD            (0x1aL<<16)
1916 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MAC            (0x1bL<<16)
1917 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH          (0x1cL<<16)
1918 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF           (0x1dL<<16)
1919 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_XON            (0x1eL<<16)
1920 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED         (0x1fL<<16)
1921 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED        (0x20L<<16)
1922 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE          (0x21L<<16)
1923 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL           (0x22L<<16)
1924 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA1           (0x23L<<16)
1925 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA2           (0x24L<<16)
1926 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA3           (0x25L<<16)
1927 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE          (0x26L<<16)
1928 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE         (0x27L<<16)
1929 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL          (0x28L<<16)
1930 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE          (0x29L<<16)
1931 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_DROP           (0x2aL<<16)
1932 #define BNX2_EMAC_RXMAC_DEBUG4_DROP_PKT                  (1L<<22)
1933 #define BNX2_EMAC_RXMAC_DEBUG4_SLOT_FILLED               (1L<<23)
1934 #define BNX2_EMAC_RXMAC_DEBUG4_FALSE_CARRIER             (1L<<24)
1935 #define BNX2_EMAC_RXMAC_DEBUG4_LAST_DATA                 (1L<<25)
1936 #define BNX2_EMAC_RXMAC_DEBUG4_sfd_FOUND                 (1L<<26)
1937 #define BNX2_EMAC_RXMAC_DEBUG4_ADVANCE                   (1L<<27)
1938 #define BNX2_EMAC_RXMAC_DEBUG4_START                     (1L<<28)
1939
1940 #define BNX2_EMAC_RXMAC_DEBUG5                          0x00001570
1941 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM                  (0x7L<<0)
1942 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE             (0L<<0)
1943 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF         (1L<<0)
1944 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT        (2L<<0)
1945 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC     (3L<<0)
1946 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE      (4L<<0)
1947 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL      (5L<<0)
1948 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT    (6L<<0)
1949 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1                (0x7L<<4)
1950 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW            (0x0L<<4)
1951 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT           (0x1L<<4)
1952 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF           (0x2L<<4)
1953 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF           (0x3L<<4)
1954 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF            (0x4L<<4)
1955 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF          (0x6L<<4)
1956 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF          (0x7L<<4)
1957 #define BNX2_EMAC_RXMAC_DEBUG5_EOF_DETECTED              (1L<<7)
1958 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF0                (0x7L<<8)
1959 #define BNX2_EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL         (1L<<11)
1960 #define BNX2_EMAC_RXMAC_DEBUG5_LOAD_CCODE                (1L<<12)
1961 #define BNX2_EMAC_RXMAC_DEBUG5_LOAD_DATA                 (1L<<13)
1962 #define BNX2_EMAC_RXMAC_DEBUG5_LOAD_STAT                 (1L<<14)
1963 #define BNX2_EMAC_RXMAC_DEBUG5_CLR_STAT                  (1L<<15)
1964 #define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE             (0x3L<<16)
1965 #define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT            (1L<<19)
1966 #define BNX2_EMAC_RXMAC_DEBUG5_FMLEN                     (0xfffL<<20)
1967
1968 #define BNX2_EMAC_RX_STAT_AC0                           0x00001580
1969 #define BNX2_EMAC_RX_STAT_AC1                           0x00001584
1970 #define BNX2_EMAC_RX_STAT_AC2                           0x00001588
1971 #define BNX2_EMAC_RX_STAT_AC3                           0x0000158c
1972 #define BNX2_EMAC_RX_STAT_AC4                           0x00001590
1973 #define BNX2_EMAC_RX_STAT_AC5                           0x00001594
1974 #define BNX2_EMAC_RX_STAT_AC6                           0x00001598
1975 #define BNX2_EMAC_RX_STAT_AC7                           0x0000159c
1976 #define BNX2_EMAC_RX_STAT_AC8                           0x000015a0
1977 #define BNX2_EMAC_RX_STAT_AC9                           0x000015a4
1978 #define BNX2_EMAC_RX_STAT_AC10                          0x000015a8
1979 #define BNX2_EMAC_RX_STAT_AC11                          0x000015ac
1980 #define BNX2_EMAC_RX_STAT_AC12                          0x000015b0
1981 #define BNX2_EMAC_RX_STAT_AC13                          0x000015b4
1982 #define BNX2_EMAC_RX_STAT_AC14                          0x000015b8
1983 #define BNX2_EMAC_RX_STAT_AC15                          0x000015bc
1984 #define BNX2_EMAC_RX_STAT_AC16                          0x000015c0
1985 #define BNX2_EMAC_RX_STAT_AC17                          0x000015c4
1986 #define BNX2_EMAC_RX_STAT_AC18                          0x000015c8
1987 #define BNX2_EMAC_RX_STAT_AC19                          0x000015cc
1988 #define BNX2_EMAC_RX_STAT_AC20                          0x000015d0
1989 #define BNX2_EMAC_RX_STAT_AC21                          0x000015d4
1990 #define BNX2_EMAC_RX_STAT_AC22                          0x000015d8
1991 #define BNX2_EMAC_RXMAC_SUC_DBG_OVERRUNVEC              0x000015dc
1992 #define BNX2_EMAC_TX_STAT_IFHCOUTOCTETS                 0x00001600
1993 #define BNX2_EMAC_TX_STAT_IFHCOUTBADOCTETS              0x00001604
1994 #define BNX2_EMAC_TX_STAT_ETHERSTATSCOLLISIONS          0x00001608
1995 #define BNX2_EMAC_TX_STAT_OUTXONSENT                    0x0000160c
1996 #define BNX2_EMAC_TX_STAT_OUTXOFFSENT                   0x00001610
1997 #define BNX2_EMAC_TX_STAT_FLOWCONTROLDONE               0x00001614
1998 #define BNX2_EMAC_TX_STAT_DOT3STATSSINGLECOLLISIONFRAMES        0x00001618
1999 #define BNX2_EMAC_TX_STAT_DOT3STATSMULTIPLECOLLISIONFRAMES      0x0000161c
2000 #define BNX2_EMAC_TX_STAT_DOT3STATSDEFERREDTRANSMISSIONS        0x00001620
2001 #define BNX2_EMAC_TX_STAT_DOT3STATSEXCESSIVECOLLISIONS  0x00001624
2002 #define BNX2_EMAC_TX_STAT_DOT3STATSLATECOLLISIONS       0x00001628
2003 #define BNX2_EMAC_TX_STAT_IFHCOUTUCASTPKTS              0x0000162c
2004 #define BNX2_EMAC_TX_STAT_IFHCOUTMULTICASTPKTS          0x00001630
2005 #define BNX2_EMAC_TX_STAT_IFHCOUTBROADCASTPKTS          0x00001634
2006 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS64OCTETS        0x00001638
2007 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS     0x0000163c
2008 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS    0x00001640
2009 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS    0x00001644
2010 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS   0x00001648
2011 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS  0x0000164c
2012 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS  0x00001650
2013 #define BNX2_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS    0x00001654
2014 #define BNX2_EMAC_TXMAC_DEBUG0                          0x00001658
2015 #define BNX2_EMAC_TXMAC_DEBUG1                          0x0000165c
2016 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE                 (0xfL<<0)
2017 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE            (0x0L<<0)
2018 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_START0          (0x1L<<0)
2019 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0           (0x4L<<0)
2020 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1           (0x5L<<0)
2021 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2           (0x6L<<0)
2022 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3           (0x7L<<0)
2023 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0           (0x8L<<0)
2024 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1           (0x9L<<0)
2025 #define BNX2_EMAC_TXMAC_DEBUG1_CRS_ENABLE                (1L<<4)
2026 #define BNX2_EMAC_TXMAC_DEBUG1_BAD_CRC                   (1L<<5)
2027 #define BNX2_EMAC_TXMAC_DEBUG1_SE_COUNTER                (0xfL<<6)
2028 #define BNX2_EMAC_TXMAC_DEBUG1_SEND_PAUSE                (1L<<10)
2029 #define BNX2_EMAC_TXMAC_DEBUG1_LATE_COLLISION            (1L<<11)
2030 #define BNX2_EMAC_TXMAC_DEBUG1_MAX_DEFER                 (1L<<12)
2031 #define BNX2_EMAC_TXMAC_DEBUG1_DEFERRED                  (1L<<13)
2032 #define BNX2_EMAC_TXMAC_DEBUG1_ONE_BYTE                  (1L<<14)
2033 #define BNX2_EMAC_TXMAC_DEBUG1_IPG_TIME                  (0xfL<<15)
2034 #define BNX2_EMAC_TXMAC_DEBUG1_SLOT_TIME                 (0xffL<<19)
2035
2036 #define BNX2_EMAC_TXMAC_DEBUG2                          0x00001660
2037 #define BNX2_EMAC_TXMAC_DEBUG2_BACK_OFF                  (0x3ffL<<0)
2038 #define BNX2_EMAC_TXMAC_DEBUG2_BYTE_COUNT                (0xffffL<<10)
2039 #define BNX2_EMAC_TXMAC_DEBUG2_COL_COUNT                 (0x1fL<<26)
2040 #define BNX2_EMAC_TXMAC_DEBUG2_COL_BIT                   (1L<<31)
2041
2042 #define BNX2_EMAC_TXMAC_DEBUG3                          0x00001664
2043 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE                  (0xfL<<0)
2044 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_IDLE             (0x0L<<0)
2045 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_PRE1             (0x1L<<0)
2046 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_PRE2             (0x2L<<0)
2047 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_SFD              (0x3L<<0)
2048 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_DATA             (0x4L<<0)
2049 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_CRC1             (0x5L<<0)
2050 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_CRC2             (0x6L<<0)
2051 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_EXT              (0x7L<<0)
2052 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_STATB            (0x8L<<0)
2053 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_STATG            (0x9L<<0)
2054 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_JAM              (0xaL<<0)
2055 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_EJAM             (0xbL<<0)
2056 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_BJAM             (0xcL<<0)
2057 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT            (0xdL<<0)
2058 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF          (0xeL<<0)
2059 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE                (0x7L<<4)
2060 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE           (0x0L<<4)
2061 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT           (0x1L<<4)
2062 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_UNI            (0x2L<<4)
2063 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_MC             (0x3L<<4)
2064 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC2            (0x4L<<4)
2065 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC3            (0x5L<<4)
2066 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC             (0x6L<<4)
2067 #define BNX2_EMAC_TXMAC_DEBUG3_CRS_DONE                  (1L<<7)
2068 #define BNX2_EMAC_TXMAC_DEBUG3_XOFF                      (1L<<8)
2069 #define BNX2_EMAC_TXMAC_DEBUG3_SE_COUNTER                (0xfL<<9)
2070 #define BNX2_EMAC_TXMAC_DEBUG3_QUANTA_COUNTER            (0x1fL<<13)
2071
2072 #define BNX2_EMAC_TXMAC_DEBUG4                          0x00001668
2073 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_COUNTER             (0xffffL<<0)
2074 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE               (0xfL<<16)
2075 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE          (0x0L<<16)
2076 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1          (0x2L<<16)
2077 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2          (0x3L<<16)
2078 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3          (0x6L<<16)
2079 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1          (0x7L<<16)
2080 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2          (0x5L<<16)
2081 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3          (0x4L<<16)
2082 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE          (0xcL<<16)
2083 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD           (0xeL<<16)
2084 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME          (0xaL<<16)
2085 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1          (0x8L<<16)
2086 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2          (0x9L<<16)
2087 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT          (0xdL<<16)
2088 #define BNX2_EMAC_TXMAC_DEBUG4_STATS0_VALID              (1L<<20)
2089 #define BNX2_EMAC_TXMAC_DEBUG4_APPEND_CRC                (1L<<21)
2090 #define BNX2_EMAC_TXMAC_DEBUG4_SLOT_FILLED               (1L<<22)
2091 #define BNX2_EMAC_TXMAC_DEBUG4_MAX_DEFER                 (1L<<23)
2092 #define BNX2_EMAC_TXMAC_DEBUG4_SEND_EXTEND               (1L<<24)
2093 #define BNX2_EMAC_TXMAC_DEBUG4_SEND_PADDING              (1L<<25)
2094 #define BNX2_EMAC_TXMAC_DEBUG4_EOF_LOC                   (1L<<26)
2095 #define BNX2_EMAC_TXMAC_DEBUG4_COLLIDING                 (1L<<27)
2096 #define BNX2_EMAC_TXMAC_DEBUG4_COL_IN                    (1L<<28)
2097 #define BNX2_EMAC_TXMAC_DEBUG4_BURSTING                  (1L<<29)
2098 #define BNX2_EMAC_TXMAC_DEBUG4_ADVANCE                   (1L<<30)
2099 #define BNX2_EMAC_TXMAC_DEBUG4_GO                        (1L<<31)
2100
2101 #define BNX2_EMAC_TX_STAT_AC0                           0x00001680
2102 #define BNX2_EMAC_TX_STAT_AC1                           0x00001684
2103 #define BNX2_EMAC_TX_STAT_AC2                           0x00001688
2104 #define BNX2_EMAC_TX_STAT_AC3                           0x0000168c
2105 #define BNX2_EMAC_TX_STAT_AC4                           0x00001690
2106 #define BNX2_EMAC_TX_STAT_AC5                           0x00001694
2107 #define BNX2_EMAC_TX_STAT_AC6                           0x00001698
2108 #define BNX2_EMAC_TX_STAT_AC7                           0x0000169c
2109 #define BNX2_EMAC_TX_STAT_AC8                           0x000016a0
2110 #define BNX2_EMAC_TX_STAT_AC9                           0x000016a4
2111 #define BNX2_EMAC_TX_STAT_AC10                          0x000016a8
2112 #define BNX2_EMAC_TX_STAT_AC11                          0x000016ac
2113 #define BNX2_EMAC_TX_STAT_AC12                          0x000016b0
2114 #define BNX2_EMAC_TX_STAT_AC13                          0x000016b4
2115 #define BNX2_EMAC_TX_STAT_AC14                          0x000016b8
2116 #define BNX2_EMAC_TX_STAT_AC15                          0x000016bc
2117 #define BNX2_EMAC_TX_STAT_AC16                          0x000016c0
2118 #define BNX2_EMAC_TX_STAT_AC17                          0x000016c4
2119 #define BNX2_EMAC_TX_STAT_AC18                          0x000016c8
2120 #define BNX2_EMAC_TX_STAT_AC19                          0x000016cc
2121 #define BNX2_EMAC_TX_STAT_AC20                          0x000016d0
2122 #define BNX2_EMAC_TX_STAT_AC21                          0x000016d4
2123 #define BNX2_EMAC_TXMAC_SUC_DBG_OVERRUNVEC              0x000016d8
2124
2125
2126 /*
2127  *  rpm_reg definition
2128  *  offset: 0x1800
2129  */
2130 #define BNX2_RPM_COMMAND                                0x00001800
2131 #define BNX2_RPM_COMMAND_ENABLED                         (1L<<0)
2132 #define BNX2_RPM_COMMAND_OVERRUN_ABORT                   (1L<<4)
2133
2134 #define BNX2_RPM_STATUS                                 0x00001804
2135 #define BNX2_RPM_STATUS_MBUF_WAIT                        (1L<<0)
2136 #define BNX2_RPM_STATUS_FREE_WAIT                        (1L<<1)
2137
2138 #define BNX2_RPM_CONFIG                                 0x00001808
2139 #define BNX2_RPM_CONFIG_NO_PSD_HDR_CKSUM                 (1L<<0)
2140 #define BNX2_RPM_CONFIG_ACPI_ENA                         (1L<<1)
2141 #define BNX2_RPM_CONFIG_ACPI_KEEP                        (1L<<2)
2142 #define BNX2_RPM_CONFIG_MP_KEEP                          (1L<<3)
2143 #define BNX2_RPM_CONFIG_SORT_VECT_VAL                    (0xfL<<4)
2144 #define BNX2_RPM_CONFIG_IGNORE_VLAN                      (1L<<31)
2145
2146 #define BNX2_RPM_VLAN_MATCH0                            0x00001810
2147 #define BNX2_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE        (0xfffL<<0)
2148
2149 #define BNX2_RPM_VLAN_MATCH1                            0x00001814
2150 #define BNX2_RPM_VLAN_MATCH1_RPM_VLAN_MTCH1_VALUE        (0xfffL<<0)
2151
2152 #define BNX2_RPM_VLAN_MATCH2                            0x00001818
2153 #define BNX2_RPM_VLAN_MATCH2_RPM_VLAN_MTCH2_VALUE        (0xfffL<<0)
2154
2155 #define BNX2_RPM_VLAN_MATCH3                            0x0000181c
2156 #define BNX2_RPM_VLAN_MATCH3_RPM_VLAN_MTCH3_VALUE        (0xfffL<<0)
2157
2158 #define BNX2_RPM_SORT_USER0                             0x00001820
2159 #define BNX2_RPM_SORT_USER0_PM_EN                        (0xffffL<<0)
2160 #define BNX2_RPM_SORT_USER0_BC_EN                        (1L<<16)
2161 #define BNX2_RPM_SORT_USER0_MC_EN                        (1L<<17)
2162 #define BNX2_RPM_SORT_USER0_MC_HSH_EN                    (1L<<18)
2163 #define BNX2_RPM_SORT_USER0_PROM_EN                      (1L<<19)
2164 #define BNX2_RPM_SORT_USER0_VLAN_EN                      (0xfL<<20)
2165 #define BNX2_RPM_SORT_USER0_PROM_VLAN                    (1L<<24)
2166 #define BNX2_RPM_SORT_USER0_ENA                          (1L<<31)
2167
2168 #define BNX2_RPM_SORT_USER1                             0x00001824
2169 #define BNX2_RPM_SORT_USER1_PM_EN                        (0xffffL<<0)
2170 #define BNX2_RPM_SORT_USER1_BC_EN                        (1L<<16)
2171 #define BNX2_RPM_SORT_USER1_MC_EN                        (1L<<17)
2172 #define BNX2_RPM_SORT_USER1_MC_HSH_EN                    (1L<<18)
2173 #define BNX2_RPM_SORT_USER1_PROM_EN                      (1L<<19)
2174 #define BNX2_RPM_SORT_USER1_VLAN_EN                      (0xfL<<20)
2175 #define BNX2_RPM_SORT_USER1_PROM_VLAN                    (1L<<24)
2176 #define BNX2_RPM_SORT_USER1_ENA                          (1L<<31)
2177
2178 #define BNX2_RPM_SORT_USER2                             0x00001828
2179 #define BNX2_RPM_SORT_USER2_PM_EN                        (0xffffL<<0)
2180 #define BNX2_RPM_SORT_USER2_BC_EN                        (1L<<16)
2181 #define BNX2_RPM_SORT_USER2_MC_EN                        (1L<<17)
2182 #define BNX2_RPM_SORT_USER2_MC_HSH_EN                    (1L<<18)
2183 #define BNX2_RPM_SORT_USER2_PROM_EN                      (1L<<19)
2184 #define BNX2_RPM_SORT_USER2_VLAN_EN                      (0xfL<<20)
2185 #define BNX2_RPM_SORT_USER2_PROM_VLAN                    (1L<<24)
2186 #define BNX2_RPM_SORT_USER2_ENA                          (1L<<31)
2187
2188 #define BNX2_RPM_SORT_USER3                             0x0000182c
2189 #define BNX2_RPM_SORT_USER3_PM_EN                        (0xffffL<<0)
2190 #define BNX2_RPM_SORT_USER3_BC_EN                        (1L<<16)
2191 #define BNX2_RPM_SORT_USER3_MC_EN                        (1L<<17)
2192 #define BNX2_RPM_SORT_USER3_MC_HSH_EN                    (1L<<18)
2193 #define BNX2_RPM_SORT_USER3_PROM_EN                      (1L<<19)
2194 #define BNX2_RPM_SORT_USER3_VLAN_EN                      (0xfL<<20)
2195 #define BNX2_RPM_SORT_USER3_PROM_VLAN                    (1L<<24)
2196 #define BNX2_RPM_SORT_USER3_ENA                          (1L<<31)
2197
2198 #define BNX2_RPM_STAT_L2_FILTER_DISCARDS                0x00001840
2199 #define BNX2_RPM_STAT_RULE_CHECKER_DISCARDS             0x00001844
2200 #define BNX2_RPM_STAT_IFINFTQDISCARDS                   0x00001848
2201 #define BNX2_RPM_STAT_IFINMBUFDISCARD                   0x0000184c
2202 #define BNX2_RPM_STAT_RULE_CHECKER_P4_HIT               0x00001850
2203 #define BNX2_RPM_STAT_AC0                               0x00001880
2204 #define BNX2_RPM_STAT_AC1                               0x00001884
2205 #define BNX2_RPM_STAT_AC2                               0x00001888
2206 #define BNX2_RPM_STAT_AC3                               0x0000188c
2207 #define BNX2_RPM_STAT_AC4                               0x00001890
2208 #define BNX2_RPM_RC_CNTL_0                              0x00001900
2209 #define BNX2_RPM_RC_CNTL_0_OFFSET                        (0xffL<<0)
2210 #define BNX2_RPM_RC_CNTL_0_CLASS                         (0x7L<<8)
2211 #define BNX2_RPM_RC_CNTL_0_PRIORITY                      (1L<<11)
2212 #define BNX2_RPM_RC_CNTL_0_P4                            (1L<<12)
2213 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE                      (0x7L<<13)
2214 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_START                (0L<<13)
2215 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_IP                   (1L<<13)
2216 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_TCP                  (2L<<13)
2217 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_UDP                  (3L<<13)
2218 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_DATA                 (4L<<13)
2219 #define BNX2_RPM_RC_CNTL_0_COMP                          (0x3L<<16)
2220 #define BNX2_RPM_RC_CNTL_0_COMP_EQUAL                    (0L<<16)
2221 #define BNX2_RPM_RC_CNTL_0_COMP_NEQUAL                   (1L<<16)
2222 #define BNX2_RPM_RC_CNTL_0_COMP_GREATER                  (2L<<16)
2223 #define BNX2_RPM_RC_CNTL_0_COMP_LESS                     (3L<<16)
2224 #define BNX2_RPM_RC_CNTL_0_SBIT                          (1L<<19)
2225 #define BNX2_RPM_RC_CNTL_0_CMDSEL                        (0xfL<<20)
2226 #define BNX2_RPM_RC_CNTL_0_MAP                           (1L<<24)
2227 #define BNX2_RPM_RC_CNTL_0_DISCARD                       (1L<<25)
2228 #define BNX2_RPM_RC_CNTL_0_MASK                          (1L<<26)
2229 #define BNX2_RPM_RC_CNTL_0_P1                            (1L<<27)
2230 #define BNX2_RPM_RC_CNTL_0_P2                            (1L<<28)
2231 #define BNX2_RPM_RC_CNTL_0_P3                            (1L<<29)
2232 #define BNX2_RPM_RC_CNTL_0_NBIT                          (1L<<30)
2233
2234 #define BNX2_RPM_RC_VALUE_MASK_0                        0x00001904
2235 #define BNX2_RPM_RC_VALUE_MASK_0_VALUE                   (0xffffL<<0)
2236 #define BNX2_RPM_RC_VALUE_MASK_0_MASK                    (0xffffL<<16)
2237
2238 #define BNX2_RPM_RC_CNTL_1                              0x00001908
2239 #define BNX2_RPM_RC_CNTL_1_A                             (0x3ffffL<<0)
2240 #define BNX2_RPM_RC_CNTL_1_B                             (0xfffL<<19)
2241
2242 #define BNX2_RPM_RC_VALUE_MASK_1                        0x0000190c
2243 #define BNX2_RPM_RC_CNTL_2                              0x00001910
2244 #define BNX2_RPM_RC_CNTL_2_A                             (0x3ffffL<<0)
2245 #define BNX2_RPM_RC_CNTL_2_B                             (0xfffL<<19)
2246
2247 #define BNX2_RPM_RC_VALUE_MASK_2                        0x00001914
2248 #define BNX2_RPM_RC_CNTL_3                              0x00001918
2249 #define BNX2_RPM_RC_CNTL_3_A                             (0x3ffffL<<0)
2250 #define BNX2_RPM_RC_CNTL_3_B                             (0xfffL<<19)
2251
2252 #define BNX2_RPM_RC_VALUE_MASK_3                        0x0000191c
2253 #define BNX2_RPM_RC_CNTL_4                              0x00001920
2254 #define BNX2_RPM_RC_CNTL_4_A                             (0x3ffffL<<0)
2255 #define BNX2_RPM_RC_CNTL_4_B                             (0xfffL<<19)
2256
2257 #define BNX2_RPM_RC_VALUE_MASK_4                        0x00001924
2258 #define BNX2_RPM_RC_CNTL_5                              0x00001928
2259 #define BNX2_RPM_RC_CNTL_5_A                             (0x3ffffL<<0)
2260 #define BNX2_RPM_RC_CNTL_5_B                             (0xfffL<<19)
2261
2262 #define BNX2_RPM_RC_VALUE_MASK_5                        0x0000192c
2263 #define BNX2_RPM_RC_CNTL_6                              0x00001930
2264 #define BNX2_RPM_RC_CNTL_6_A                             (0x3ffffL<<0)
2265 #define BNX2_RPM_RC_CNTL_6_B                             (0xfffL<<19)
2266
2267 #define BNX2_RPM_RC_VALUE_MASK_6                        0x00001934
2268 #define BNX2_RPM_RC_CNTL_7                              0x00001938
2269 #define BNX2_RPM_RC_CNTL_7_A                             (0x3ffffL<<0)
2270 #define BNX2_RPM_RC_CNTL_7_B                             (0xfffL<<19)
2271
2272 #define BNX2_RPM_RC_VALUE_MASK_7                        0x0000193c
2273 #define BNX2_RPM_RC_CNTL_8                              0x00001940
2274 #define BNX2_RPM_RC_CNTL_8_A                             (0x3ffffL<<0)
2275 #define BNX2_RPM_RC_CNTL_8_B                             (0xfffL<<19)
2276
2277 #define BNX2_RPM_RC_VALUE_MASK_8                        0x00001944
2278 #define BNX2_RPM_RC_CNTL_9                              0x00001948
2279 #define BNX2_RPM_RC_CNTL_9_A                             (0x3ffffL<<0)
2280 #define BNX2_RPM_RC_CNTL_9_B                             (0xfffL<<19)
2281
2282 #define BNX2_RPM_RC_VALUE_MASK_9                        0x0000194c
2283 #define BNX2_RPM_RC_CNTL_10                             0x00001950
2284 #define BNX2_RPM_RC_CNTL_10_A                            (0x3ffffL<<0)
2285 #define BNX2_RPM_RC_CNTL_10_B                            (0xfffL<<19)
2286
2287 #define BNX2_RPM_RC_VALUE_MASK_10                       0x00001954
2288 #define BNX2_RPM_RC_CNTL_11                             0x00001958
2289 #define BNX2_RPM_RC_CNTL_11_A                            (0x3ffffL<<0)
2290 #define BNX2_RPM_RC_CNTL_11_B                            (0xfffL<<19)
2291
2292 #define BNX2_RPM_RC_VALUE_MASK_11                       0x0000195c
2293 #define BNX2_RPM_RC_CNTL_12                             0x00001960
2294 #define BNX2_RPM_RC_CNTL_12_A                            (0x3ffffL<<0)
2295 #define BNX2_RPM_RC_CNTL_12_B                            (0xfffL<<19)
2296
2297 #define BNX2_RPM_RC_VALUE_MASK_12                       0x00001964
2298 #define BNX2_RPM_RC_CNTL_13                             0x00001968
2299 #define BNX2_RPM_RC_CNTL_13_A                            (0x3ffffL<<0)
2300 #define BNX2_RPM_RC_CNTL_13_B                            (0xfffL<<19)
2301
2302 #define BNX2_RPM_RC_VALUE_MASK_13                       0x0000196c
2303 #define BNX2_RPM_RC_CNTL_14                             0x00001970
2304 #define BNX2_RPM_RC_CNTL_14_A                            (0x3ffffL<<0)
2305 #define BNX2_RPM_RC_CNTL_14_B                            (0xfffL<<19)
2306
2307 #define BNX2_RPM_RC_VALUE_MASK_14                       0x00001974
2308 #define BNX2_RPM_RC_CNTL_15                             0x00001978
2309 #define BNX2_RPM_RC_CNTL_15_A                            (0x3ffffL<<0)
2310 #define BNX2_RPM_RC_CNTL_15_B                            (0xfffL<<19)
2311
2312 #define BNX2_RPM_RC_VALUE_MASK_15                       0x0000197c
2313 #define BNX2_RPM_RC_CONFIG                              0x00001980
2314 #define BNX2_RPM_RC_CONFIG_RULE_ENABLE                   (0xffffL<<0)
2315 #define BNX2_RPM_RC_CONFIG_DEF_CLASS                     (0x7L<<24)
2316
2317 #define BNX2_RPM_DEBUG0                                 0x00001984
2318 #define BNX2_RPM_DEBUG0_FM_BCNT                          (0xffffL<<0)
2319 #define BNX2_RPM_DEBUG0_T_DATA_OFST_VLD                  (1L<<16)
2320 #define BNX2_RPM_DEBUG0_T_UDP_OFST_VLD                   (1L<<17)
2321 #define BNX2_RPM_DEBUG0_T_TCP_OFST_VLD                   (1L<<18)
2322 #define BNX2_RPM_DEBUG0_T_IP_OFST_VLD                    (1L<<19)
2323 #define BNX2_RPM_DEBUG0_IP_MORE_FRGMT                    (1L<<20)
2324 #define BNX2_RPM_DEBUG0_T_IP_NO_TCP_UDP_HDR              (1L<<21)
2325 #define BNX2_RPM_DEBUG0_LLC_SNAP                         (1L<<22)
2326 #define BNX2_RPM_DEBUG0_FM_STARTED                       (1L<<23)
2327 #define BNX2_RPM_DEBUG0_DONE                             (1L<<24)
2328 #define BNX2_RPM_DEBUG0_WAIT_4_DONE                      (1L<<25)
2329 #define BNX2_RPM_DEBUG0_USE_TPBUF_CKSUM                  (1L<<26)
2330 #define BNX2_RPM_DEBUG0_RX_NO_PSD_HDR_CKSUM              (1L<<27)
2331 #define BNX2_RPM_DEBUG0_IGNORE_VLAN                      (1L<<28)
2332 #define BNX2_RPM_DEBUG0_RP_ENA_ACTIVE                    (1L<<31)
2333
2334 #define BNX2_RPM_DEBUG1                                 0x00001988
2335 #define BNX2_RPM_DEBUG1_FSM_CUR_ST                       (0xffffL<<0)
2336 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_IDLE                  (0L<<0)
2337 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL          (1L<<0)
2338 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC        (2L<<0)
2339 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP           (4L<<0)
2340 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP           (8L<<0)
2341 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_IP_START              (16L<<0)
2342 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_IP                    (32L<<0)
2343 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_TCP                   (64L<<0)
2344 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_UDP                   (128L<<0)
2345 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_AH                    (256L<<0)
2346 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP                   (512L<<0)
2347 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD           (1024L<<0)
2348 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_DATA                  (2048L<<0)
2349 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRY             (0x2000L<<0)
2350 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRYOUT          (0x4000L<<0)
2351 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_LATCH_RESULT          (0x8000L<<0)
2352 #define BNX2_RPM_DEBUG1_HDR_BCNT                         (0x7ffL<<16)
2353 #define BNX2_RPM_DEBUG1_UNKNOWN_ETYPE_D                  (1L<<28)
2354 #define BNX2_RPM_DEBUG1_VLAN_REMOVED_D2                  (1L<<29)
2355 #define BNX2_RPM_DEBUG1_VLAN_REMOVED_D1                  (1L<<30)
2356 #define BNX2_RPM_DEBUG1_EOF_0XTRA_WD                     (1L<<31)
2357
2358 #define BNX2_RPM_DEBUG2                                 0x0000198c
2359 #define BNX2_RPM_DEBUG2_CMD_HIT_VEC                      (0xffffL<<0)
2360 #define BNX2_RPM_DEBUG2_IP_BCNT                          (0xffL<<16)
2361 #define BNX2_RPM_DEBUG2_THIS_CMD_M4                      (1L<<24)
2362 #define BNX2_RPM_DEBUG2_THIS_CMD_M3                      (1L<<25)
2363 #define BNX2_RPM_DEBUG2_THIS_CMD_M2                      (1L<<26)
2364 #define BNX2_RPM_DEBUG2_THIS_CMD_M1                      (1L<<27)
2365 #define BNX2_RPM_DEBUG2_IPIPE_EMPTY                      (1L<<28)
2366 #define BNX2_RPM_DEBUG2_FM_DISCARD                       (1L<<29)
2367 #define BNX2_RPM_DEBUG2_LAST_RULE_IN_FM_D2               (1L<<30)
2368 #define BNX2_RPM_DEBUG2_LAST_RULE_IN_FM_D1               (1L<<31)
2369
2370 #define BNX2_RPM_DEBUG3                                 0x00001990
2371 #define BNX2_RPM_DEBUG3_AVAIL_MBUF_PTR                   (0x1ffL<<0)
2372 #define BNX2_RPM_DEBUG3_RDE_RLUPQ_WR_REQ_INT             (1L<<9)
2373 #define BNX2_RPM_DEBUG3_RDE_RBUF_WR_LAST_INT             (1L<<10)
2374 #define BNX2_RPM_DEBUG3_RDE_RBUF_WR_REQ_INT              (1L<<11)
2375 #define BNX2_RPM_DEBUG3_RDE_RBUF_FREE_REQ                (1L<<12)
2376 #define BNX2_RPM_DEBUG3_RDE_RBUF_ALLOC_REQ               (1L<<13)
2377 #define BNX2_RPM_DEBUG3_DFSM_MBUF_NOTAVAIL               (1L<<14)
2378 #define BNX2_RPM_DEBUG3_RBUF_RDE_SOF_DROP                (1L<<15)
2379 #define BNX2_RPM_DEBUG3_DFIFO_VLD_ENTRY_CT               (0xfL<<16)
2380 #define BNX2_RPM_DEBUG3_RDE_SRC_FIFO_ALMFULL             (1L<<21)
2381 #define BNX2_RPM_DEBUG3_DROP_NXT_VLD                     (1L<<22)
2382 #define BNX2_RPM_DEBUG3_DROP_NXT                         (1L<<23)
2383 #define BNX2_RPM_DEBUG3_FTQ_FSM                          (0x3L<<24)
2384 #define BNX2_RPM_DEBUG3_FTQ_FSM_IDLE                     (0x0L<<24)
2385 #define BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_ACK                 (0x1L<<24)
2386 #define BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_FREE                (0x2L<<24)
2387 #define BNX2_RPM_DEBUG3_MBWRITE_FSM                      (0x3L<<26)
2388 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_SOF             (0x0L<<26)
2389 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_GET_MBUF             (0x1L<<26)
2390 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_DMA_DATA             (0x2L<<26)
2391 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_DATA            (0x3L<<26)
2392 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_EOF             (0x4L<<26)
2393 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_MF_ACK          (0x5L<<26)
2394 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_DROP_NXT_VLD    (0x6L<<26)
2395 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_DONE                 (0x7L<<26)
2396 #define BNX2_RPM_DEBUG3_MBFREE_FSM                       (1L<<29)
2397 #define BNX2_RPM_DEBUG3_MBFREE_FSM_IDLE                  (0L<<29)
2398 #define BNX2_RPM_DEBUG3_MBFREE_FSM_WAIT_ACK              (1L<<29)
2399 #define BNX2_RPM_DEBUG3_MBALLOC_FSM                      (1L<<30)
2400 #define BNX2_RPM_DEBUG3_MBALLOC_FSM_ET_MBUF              (0x0L<<30)
2401 #define BNX2_RPM_DEBUG3_MBALLOC_FSM_IVE_MBUF             (0x1L<<30)
2402 #define BNX2_RPM_DEBUG3_CCODE_EOF_ERROR                  (1L<<31)
2403
2404 #define BNX2_RPM_DEBUG4                                 0x00001994
2405 #define BNX2_RPM_DEBUG4_DFSM_MBUF_CLUSTER                (0x1ffffffL<<0)
2406 #define BNX2_RPM_DEBUG4_DFIFO_CUR_CCODE                  (0x7L<<25)
2407 #define BNX2_RPM_DEBUG4_MBWRITE_FSM                      (0x7L<<28)
2408 #define BNX2_RPM_DEBUG4_DFIFO_EMPTY                      (1L<<31)
2409
2410 #define BNX2_RPM_DEBUG5                                 0x00001998
2411 #define BNX2_RPM_DEBUG5_RDROP_WPTR                       (0x1fL<<0)
2412 #define BNX2_RPM_DEBUG5_RDROP_ACPI_RPTR                  (0x1fL<<5)
2413 #define BNX2_RPM_DEBUG5_RDROP_MC_RPTR                    (0x1fL<<10)
2414 #define BNX2_RPM_DEBUG5_RDROP_RC_RPTR                    (0x1fL<<15)
2415 #define BNX2_RPM_DEBUG5_RDROP_ACPI_EMPTY                 (1L<<20)
2416 #define BNX2_RPM_DEBUG5_RDROP_MC_EMPTY                   (1L<<21)
2417 #define BNX2_RPM_DEBUG5_RDROP_AEOF_VEC_AT_RDROP_MC_RPTR  (1L<<22)
2418 #define BNX2_RPM_DEBUG5_HOLDREG_WOL_DROP_INT             (1L<<23)
2419 #define BNX2_RPM_DEBUG5_HOLDREG_DISCARD                  (1L<<24)
2420 #define BNX2_RPM_DEBUG5_HOLDREG_MBUF_NOTAVAIL            (1L<<25)
2421 #define BNX2_RPM_DEBUG5_HOLDREG_MC_EMPTY                 (1L<<26)
2422 #define BNX2_RPM_DEBUG5_HOLDREG_RC_EMPTY                 (1L<<27)
2423 #define BNX2_RPM_DEBUG5_HOLDREG_FC_EMPTY                 (1L<<28)
2424 #define BNX2_RPM_DEBUG5_HOLDREG_ACPI_EMPTY               (1L<<29)
2425 #define BNX2_RPM_DEBUG5_HOLDREG_FULL_T                   (1L<<30)
2426 #define BNX2_RPM_DEBUG5_HOLDREG_RD                       (1L<<31)
2427
2428 #define BNX2_RPM_DEBUG6                                 0x0000199c
2429 #define BNX2_RPM_DEBUG6_ACPI_VEC                         (0xffffL<<0)
2430 #define BNX2_RPM_DEBUG6_VEC                              (0xffffL<<16)
2431
2432 #define BNX2_RPM_DEBUG7                                 0x000019a0
2433 #define BNX2_RPM_DEBUG7_RPM_DBG7_LAST_CRC                (0xffffffffL<<0)
2434
2435 #define BNX2_RPM_DEBUG8                                 0x000019a4
2436 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM                      (0xfL<<0)
2437 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_IDLE                 (0L<<0)
2438 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR          (1L<<0)
2439 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR          (2L<<0)
2440 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR          (3L<<0)
2441 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF       (4L<<0)
2442 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_DATA              (5L<<0)
2443 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W0_ADDR              (6L<<0)
2444 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W1_ADDR              (7L<<0)
2445 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W2_ADDR              (8L<<0)
2446 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_ADDR              (9L<<0)
2447 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_WAIT_THBUF           (10L<<0)
2448 #define BNX2_RPM_DEBUG8_COMPARE_AT_W0                    (1L<<4)
2449 #define BNX2_RPM_DEBUG8_COMPARE_AT_W3_DATA               (1L<<5)
2450 #define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_WAIT              (1L<<6)
2451 #define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_W3                (1L<<7)
2452 #define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_W2                (1L<<8)
2453 #define BNX2_RPM_DEBUG8_EOF_W_LTEQ6_VLDBYTES             (1L<<9)
2454 #define BNX2_RPM_DEBUG8_EOF_W_LTEQ4_VLDBYTES             (1L<<10)
2455 #define BNX2_RPM_DEBUG8_NXT_EOF_W_12_VLDBYTES            (1L<<11)
2456 #define BNX2_RPM_DEBUG8_EOF_DET                          (1L<<12)
2457 #define BNX2_RPM_DEBUG8_SOF_DET                          (1L<<13)
2458 #define BNX2_RPM_DEBUG8_WAIT_4_SOF                       (1L<<14)
2459 #define BNX2_RPM_DEBUG8_ALL_DONE                         (1L<<15)
2460 #define BNX2_RPM_DEBUG8_THBUF_ADDR                       (0x7fL<<16)
2461 #define BNX2_RPM_DEBUG8_BYTE_CTR                         (0xffL<<24)
2462
2463 #define BNX2_RPM_DEBUG9                                 0x000019a8
2464 #define BNX2_RPM_DEBUG9_OUTFIFO_COUNT                    (0x7L<<0)
2465 #define BNX2_RPM_DEBUG9_RDE_ACPI_RDY                     (1L<<3)
2466 #define BNX2_RPM_DEBUG9_VLD_RD_ENTRY_CT                  (0x7L<<4)
2467 #define BNX2_RPM_DEBUG9_OUTFIFO_OVERRUN_OCCURRED         (1L<<28)
2468 #define BNX2_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED          (1L<<29)
2469 #define BNX2_RPM_DEBUG9_ACPI_MATCH_INT                   (1L<<30)
2470 #define BNX2_RPM_DEBUG9_ACPI_ENABLE_SYN                  (1L<<31)
2471
2472 #define BNX2_RPM_ACPI_DBG_BUF_W00                       0x000019c0
2473 #define BNX2_RPM_ACPI_DBG_BUF_W01                       0x000019c4
2474 #define BNX2_RPM_ACPI_DBG_BUF_W02                       0x000019c8
2475 #define BNX2_RPM_ACPI_DBG_BUF_W03                       0x000019cc
2476 #define BNX2_RPM_ACPI_DBG_BUF_W10                       0x000019d0
2477 #define BNX2_RPM_ACPI_DBG_BUF_W11                       0x000019d4
2478 #define BNX2_RPM_ACPI_DBG_BUF_W12                       0x000019d8
2479 #define BNX2_RPM_ACPI_DBG_BUF_W13                       0x000019dc
2480 #define BNX2_RPM_ACPI_DBG_BUF_W20                       0x000019e0
2481 #define BNX2_RPM_ACPI_DBG_BUF_W21                       0x000019e4
2482 #define BNX2_RPM_ACPI_DBG_BUF_W22                       0x000019e8
2483 #define BNX2_RPM_ACPI_DBG_BUF_W23                       0x000019ec
2484 #define BNX2_RPM_ACPI_DBG_BUF_W30                       0x000019f0
2485 #define BNX2_RPM_ACPI_DBG_BUF_W31                       0x000019f4
2486 #define BNX2_RPM_ACPI_DBG_BUF_W32                       0x000019f8
2487 #define BNX2_RPM_ACPI_DBG_BUF_W33                       0x000019fc
2488
2489
2490 /*
2491  *  rbuf_reg definition
2492  *  offset: 0x200000
2493  */
2494 #define BNX2_RBUF_COMMAND                               0x00200000
2495 #define BNX2_RBUF_COMMAND_ENABLED                        (1L<<0)
2496 #define BNX2_RBUF_COMMAND_FREE_INIT                      (1L<<1)
2497 #define BNX2_RBUF_COMMAND_RAM_INIT                       (1L<<2)
2498 #define BNX2_RBUF_COMMAND_OVER_FREE                      (1L<<4)
2499 #define BNX2_RBUF_COMMAND_ALLOC_REQ                      (1L<<5)
2500
2501 #define BNX2_RBUF_STATUS1                               0x00200004
2502 #define BNX2_RBUF_STATUS1_FREE_COUNT                     (0x3ffL<<0)
2503
2504 #define BNX2_RBUF_STATUS2                               0x00200008
2505 #define BNX2_RBUF_STATUS2_FREE_TAIL                      (0x3ffL<<0)
2506 #define BNX2_RBUF_STATUS2_FREE_HEAD                      (0x3ffL<<16)
2507
2508 #define BNX2_RBUF_CONFIG                                0x0020000c
2509 #define BNX2_RBUF_CONFIG_XOFF_TRIP                       (0x3ffL<<0)
2510 #define BNX2_RBUF_CONFIG_XON_TRIP                        (0x3ffL<<16)
2511
2512 #define BNX2_RBUF_FW_BUF_ALLOC                          0x00200010
2513 #define BNX2_RBUF_FW_BUF_ALLOC_VALUE                     (0x1ffL<<7)
2514
2515 #define BNX2_RBUF_FW_BUF_FREE                           0x00200014
2516 #define BNX2_RBUF_FW_BUF_FREE_COUNT                      (0x7fL<<0)
2517 #define BNX2_RBUF_FW_BUF_FREE_TAIL                       (0x1ffL<<7)
2518 #define BNX2_RBUF_FW_BUF_FREE_HEAD                       (0x1ffL<<16)
2519
2520 #define BNX2_RBUF_FW_BUF_SEL                            0x00200018
2521 #define BNX2_RBUF_FW_BUF_SEL_COUNT                       (0x7fL<<0)
2522 #define BNX2_RBUF_FW_BUF_SEL_TAIL                        (0x1ffL<<7)
2523 #define BNX2_RBUF_FW_BUF_SEL_HEAD                        (0x1ffL<<16)
2524
2525 #define BNX2_RBUF_CONFIG2                               0x0020001c
2526 #define BNX2_RBUF_CONFIG2_MAC_DROP_TRIP                  (0x3ffL<<0)
2527 #define BNX2_RBUF_CONFIG2_MAC_KEEP_TRIP                  (0x3ffL<<16)
2528
2529 #define BNX2_RBUF_CONFIG3                               0x00200020
2530 #define BNX2_RBUF_CONFIG3_CU_DROP_TRIP                   (0x3ffL<<0)
2531 #define BNX2_RBUF_CONFIG3_CU_KEEP_TRIP                   (0x3ffL<<16)
2532
2533 #define BNX2_RBUF_PKT_DATA                              0x00208000
2534 #define BNX2_RBUF_CLIST_DATA                            0x00210000
2535 #define BNX2_RBUF_BUF_DATA                              0x00220000
2536
2537
2538 /*
2539  *  rv2p_reg definition
2540  *  offset: 0x2800
2541  */
2542 #define BNX2_RV2P_COMMAND                               0x00002800
2543 #define BNX2_RV2P_COMMAND_ENABLED                        (1L<<0)
2544 #define BNX2_RV2P_COMMAND_PROC1_INTRPT                   (1L<<1)
2545 #define BNX2_RV2P_COMMAND_PROC2_INTRPT                   (1L<<2)
2546 #define BNX2_RV2P_COMMAND_ABORT0                         (1L<<4)
2547 #define BNX2_RV2P_COMMAND_ABORT1                         (1L<<5)
2548 #define BNX2_RV2P_COMMAND_ABORT2                         (1L<<6)
2549 #define BNX2_RV2P_COMMAND_ABORT3                         (1L<<7)
2550 #define BNX2_RV2P_COMMAND_ABORT4                         (1L<<8)
2551 #define BNX2_RV2P_COMMAND_ABORT5                         (1L<<9)
2552 #define BNX2_RV2P_COMMAND_PROC1_RESET                    (1L<<16)
2553 #define BNX2_RV2P_COMMAND_PROC2_RESET                    (1L<<17)
2554 #define BNX2_RV2P_COMMAND_CTXIF_RESET                    (1L<<18)
2555
2556 #define BNX2_RV2P_STATUS                                0x00002804
2557 #define BNX2_RV2P_STATUS_ALWAYS_0                        (1L<<0)
2558 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT0_CNT              (1L<<8)
2559 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT1_CNT              (1L<<9)
2560 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT2_CNT              (1L<<10)
2561 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT3_CNT              (1L<<11)
2562 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT4_CNT              (1L<<12)
2563 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT5_CNT              (1L<<13)
2564
2565 #define BNX2_RV2P_CONFIG                                0x00002808
2566 #define BNX2_RV2P_CONFIG_STALL_PROC1                     (1L<<0)
2567 #define BNX2_RV2P_CONFIG_STALL_PROC2                     (1L<<1)
2568 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT0           (1L<<8)
2569 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT1           (1L<<9)
2570 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT2           (1L<<10)
2571 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT3           (1L<<11)
2572 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT4           (1L<<12)
2573 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT5           (1L<<13)
2574 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT0           (1L<<16)
2575 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT1           (1L<<17)
2576 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT2           (1L<<18)
2577 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT3           (1L<<19)
2578 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT4           (1L<<20)
2579 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT5           (1L<<21)
2580 #define BNX2_RV2P_CONFIG_PAGE_SIZE                       (0xfL<<24)
2581 #define BNX2_RV2P_CONFIG_PAGE_SIZE_256                   (0L<<24)
2582 #define BNX2_RV2P_CONFIG_PAGE_SIZE_512                   (1L<<24)
2583 #define BNX2_RV2P_CONFIG_PAGE_SIZE_1K                    (2L<<24)
2584 #define BNX2_RV2P_CONFIG_PAGE_SIZE_2K                    (3L<<24)
2585 #define BNX2_RV2P_CONFIG_PAGE_SIZE_4K                    (4L<<24)
2586 #define BNX2_RV2P_CONFIG_PAGE_SIZE_8K                    (5L<<24)
2587 #define BNX2_RV2P_CONFIG_PAGE_SIZE_16K                   (6L<<24)
2588 #define BNX2_RV2P_CONFIG_PAGE_SIZE_32K                   (7L<<24)
2589 #define BNX2_RV2P_CONFIG_PAGE_SIZE_64K                   (8L<<24)
2590 #define BNX2_RV2P_CONFIG_PAGE_SIZE_128K                  (9L<<24)
2591 #define BNX2_RV2P_CONFIG_PAGE_SIZE_256K                  (10L<<24)
2592 #define BNX2_RV2P_CONFIG_PAGE_SIZE_512K                  (11L<<24)
2593 #define BNX2_RV2P_CONFIG_PAGE_SIZE_1M                    (12L<<24)
2594
2595 #define BNX2_RV2P_GEN_BFR_ADDR_0                        0x00002810
2596 #define BNX2_RV2P_GEN_BFR_ADDR_0_VALUE                   (0xffffL<<16)
2597
2598 #define BNX2_RV2P_GEN_BFR_ADDR_1                        0x00002814
2599 #define BNX2_RV2P_GEN_BFR_ADDR_1_VALUE                   (0xffffL<<16)
2600
2601 #define BNX2_RV2P_GEN_BFR_ADDR_2                        0x00002818
2602 #define BNX2_RV2P_GEN_BFR_ADDR_2_VALUE                   (0xffffL<<16)
2603
2604 #define BNX2_RV2P_GEN_BFR_ADDR_3                        0x0000281c
2605 #define BNX2_RV2P_GEN_BFR_ADDR_3_VALUE                   (0xffffL<<16)
2606
2607 #define BNX2_RV2P_INSTR_HIGH                            0x00002830
2608 #define BNX2_RV2P_INSTR_HIGH_HIGH                        (0x1fL<<0)
2609
2610 #define BNX2_RV2P_INSTR_LOW                             0x00002834
2611 #define BNX2_RV2P_PROC1_ADDR_CMD                        0x00002838
2612 #define BNX2_RV2P_PROC1_ADDR_CMD_ADD                     (0x3ffL<<0)
2613 #define BNX2_RV2P_PROC1_ADDR_CMD_RDWR                    (1L<<31)
2614
2615 #define BNX2_RV2P_PROC2_ADDR_CMD                        0x0000283c
2616 #define BNX2_RV2P_PROC2_ADDR_CMD_ADD                     (0x3ffL<<0)
2617 #define BNX2_RV2P_PROC2_ADDR_CMD_RDWR                    (1L<<31)
2618
2619 #define BNX2_RV2P_PROC1_GRC_DEBUG                       0x00002840
2620 #define BNX2_RV2P_PROC2_GRC_DEBUG                       0x00002844
2621 #define BNX2_RV2P_GRC_PROC_DEBUG                        0x00002848
2622 #define BNX2_RV2P_DEBUG_VECT_PEEK                       0x0000284c
2623 #define BNX2_RV2P_DEBUG_VECT_PEEK_1_VALUE                (0x7ffL<<0)
2624 #define BNX2_RV2P_DEBUG_VECT_PEEK_1_PEEK_EN              (1L<<11)
2625 #define BNX2_RV2P_DEBUG_VECT_PEEK_1_SEL                  (0xfL<<12)
2626 #define BNX2_RV2P_DEBUG_VECT_PEEK_2_VALUE                (0x7ffL<<16)
2627 #define BNX2_RV2P_DEBUG_VECT_PEEK_2_PEEK_EN              (1L<<27)
2628 #define BNX2_RV2P_DEBUG_VECT_PEEK_2_SEL                  (0xfL<<28)
2629
2630 #define BNX2_RV2P_PFTQ_DATA                             0x00002b40
2631 #define BNX2_RV2P_PFTQ_CMD                              0x00002b78
2632 #define BNX2_RV2P_PFTQ_CMD_OFFSET                        (0x3ffL<<0)
2633 #define BNX2_RV2P_PFTQ_CMD_WR_TOP                        (1L<<10)
2634 #define BNX2_RV2P_PFTQ_CMD_WR_TOP_0                      (0L<<10)
2635 #define BNX2_RV2P_PFTQ_CMD_WR_TOP_1                      (1L<<10)
2636 #define BNX2_RV2P_PFTQ_CMD_SFT_RESET                     (1L<<25)
2637 #define BNX2_RV2P_PFTQ_CMD_RD_DATA                       (1L<<26)
2638 #define BNX2_RV2P_PFTQ_CMD_ADD_INTERVEN                  (1L<<27)
2639 #define BNX2_RV2P_PFTQ_CMD_ADD_DATA                      (1L<<28)
2640 #define BNX2_RV2P_PFTQ_CMD_INTERVENE_CLR                 (1L<<29)
2641 #define BNX2_RV2P_PFTQ_CMD_POP                           (1L<<30)
2642 #define BNX2_RV2P_PFTQ_CMD_BUSY                          (1L<<31)
2643
2644 #define BNX2_RV2P_PFTQ_CTL                              0x00002b7c
2645 #define BNX2_RV2P_PFTQ_CTL_INTERVENE                     (1L<<0)
2646 #define BNX2_RV2P_PFTQ_CTL_OVERFLOW                      (1L<<1)
2647 #define BNX2_RV2P_PFTQ_CTL_FORCE_INTERVENE               (1L<<2)
2648 #define BNX2_RV2P_PFTQ_CTL_MAX_DEPTH                     (0x3ffL<<12)
2649 #define BNX2_RV2P_PFTQ_CTL_CUR_DEPTH                     (0x3ffL<<22)
2650
2651 #define BNX2_RV2P_TFTQ_DATA                             0x00002b80
2652 #define BNX2_RV2P_TFTQ_CMD                              0x00002bb8
2653 #define BNX2_RV2P_TFTQ_CMD_OFFSET                        (0x3ffL<<0)
2654 #define BNX2_RV2P_TFTQ_CMD_WR_TOP                        (1L<<10)
2655 #define BNX2_RV2P_TFTQ_CMD_WR_TOP_0                      (0L<<10)
2656 #define BNX2_RV2P_TFTQ_CMD_WR_TOP_1                      (1L<<10)
2657 #define BNX2_RV2P_TFTQ_CMD_SFT_RESET                     (1L<<25)
2658 #define BNX2_RV2P_TFTQ_CMD_RD_DATA                       (1L<<26)
2659 #define BNX2_RV2P_TFTQ_CMD_ADD_INTERVEN                  (1L<<27)
2660 #define BNX2_RV2P_TFTQ_CMD_ADD_DATA                      (1L<<28)
2661 #define BNX2_RV2P_TFTQ_CMD_INTERVENE_CLR                 (1L<<29)
2662 #define BNX2_RV2P_TFTQ_CMD_POP                           (1L<<30)
2663 #define BNX2_RV2P_TFTQ_CMD_BUSY                          (1L<<31)
2664
2665 #define BNX2_RV2P_TFTQ_CTL                              0x00002bbc
2666 #define BNX2_RV2P_TFTQ_CTL_INTERVENE                     (1L<<0)
2667 #define BNX2_RV2P_TFTQ_CTL_OVERFLOW                      (1L<<1)
2668 #define BNX2_RV2P_TFTQ_CTL_FORCE_INTERVENE               (1L<<2)
2669 #define BNX2_RV2P_TFTQ_CTL_MAX_DEPTH                     (0x3ffL<<12)
2670 #define BNX2_RV2P_TFTQ_CTL_CUR_DEPTH                     (0x3ffL<<22)
2671
2672 #define BNX2_RV2P_MFTQ_DATA                             0x00002bc0
2673 #define BNX2_RV2P_MFTQ_CMD                              0x00002bf8
2674 #define BNX2_RV2P_MFTQ_CMD_OFFSET                        (0x3ffL<<0)
2675 #define BNX2_RV2P_MFTQ_CMD_WR_TOP                        (1L<<10)
2676 #define BNX2_RV2P_MFTQ_CMD_WR_TOP_0                      (0L<<10)
2677 #define BNX2_RV2P_MFTQ_CMD_WR_TOP_1                      (1L<<10)
2678 #define BNX2_RV2P_MFTQ_CMD_SFT_RESET                     (1L<<25)
2679 #define BNX2_RV2P_MFTQ_CMD_RD_DATA                       (1L<<26)
2680 #define BNX2_RV2P_MFTQ_CMD_ADD_INTERVEN                  (1L<<27)
2681 #define BNX2_RV2P_MFTQ_CMD_ADD_DATA                      (1L<<28)
2682 #define BNX2_RV2P_MFTQ_CMD_INTERVENE_CLR                 (1L<<29)
2683 #define BNX2_RV2P_MFTQ_CMD_POP                           (1L<<30)
2684 #define BNX2_RV2P_MFTQ_CMD_BUSY                          (1L<<31)
2685
2686 #define BNX2_RV2P_MFTQ_CTL                              0x00002bfc
2687 #define BNX2_RV2P_MFTQ_CTL_INTERVENE                     (1L<<0)
2688 #define BNX2_RV2P_MFTQ_CTL_OVERFLOW                      (1L<<1)
2689 #define BNX2_RV2P_MFTQ_CTL_FORCE_INTERVENE               (1L<<2)
2690 #define BNX2_RV2P_MFTQ_CTL_MAX_DEPTH                     (0x3ffL<<12)
2691 #define BNX2_RV2P_MFTQ_CTL_CUR_DEPTH                     (0x3ffL<<22)
2692
2693
2694
2695 /*
2696  *  mq_reg definition
2697  *  offset: 0x3c00
2698  */
2699 #define BNX2_MQ_COMMAND                                 0x00003c00
2700 #define BNX2_MQ_COMMAND_ENABLED                          (1L<<0)
2701 #define BNX2_MQ_COMMAND_OVERFLOW                         (1L<<4)
2702 #define BNX2_MQ_COMMAND_WR_ERROR                         (1L<<5)
2703 #define BNX2_MQ_COMMAND_RD_ERROR                         (1L<<6)
2704
2705 #define BNX2_MQ_STATUS                                  0x00003c04
2706 #define BNX2_MQ_STATUS_CTX_ACCESS_STAT                   (1L<<16)
2707 #define BNX2_MQ_STATUS_CTX_ACCESS64_STAT                 (1L<<17)
2708 #define BNX2_MQ_STATUS_PCI_STALL_STAT                    (1L<<18)
2709
2710 #define BNX2_MQ_CONFIG                                  0x00003c08
2711 #define BNX2_MQ_CONFIG_TX_HIGH_PRI                       (1L<<0)
2712 #define BNX2_MQ_CONFIG_HALT_DIS                          (1L<<1)
2713 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE                  (0x7L<<4)
2714 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256              (0L<<4)
2715 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_512              (1L<<4)
2716 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_1K               (2L<<4)
2717 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_2K               (3L<<4)
2718 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_4K               (4L<<4)
2719 #define BNX2_MQ_CONFIG_MAX_DEPTH                         (0x7fL<<8)
2720 #define BNX2_MQ_CONFIG_CUR_DEPTH                         (0x7fL<<20)
2721
2722 #define BNX2_MQ_ENQUEUE1                                0x00003c0c
2723 #define BNX2_MQ_ENQUEUE1_OFFSET                          (0x3fL<<2)
2724 #define BNX2_MQ_ENQUEUE1_CID                             (0x3fffL<<8)
2725 #define BNX2_MQ_ENQUEUE1_BYTE_MASK                       (0xfL<<24)
2726 #define BNX2_MQ_ENQUEUE1_KNL_MODE                        (1L<<28)
2727
2728 #define BNX2_MQ_ENQUEUE2                                0x00003c10
2729 #define BNX2_MQ_BAD_WR_ADDR                             0x00003c14
2730 #define BNX2_MQ_BAD_RD_ADDR                             0x00003c18
2731 #define BNX2_MQ_KNL_BYP_WIND_START                      0x00003c1c
2732 #define BNX2_MQ_KNL_BYP_WIND_START_VALUE                 (0xfffffL<<12)
2733
2734 #define BNX2_MQ_KNL_WIND_END                            0x00003c20
2735 #define BNX2_MQ_KNL_WIND_END_VALUE                       (0xffffffL<<8)
2736
2737 #define BNX2_MQ_KNL_WRITE_MASK1                         0x00003c24
2738 #define BNX2_MQ_KNL_TX_MASK1                            0x00003c28
2739 #define BNX2_MQ_KNL_CMD_MASK1                           0x00003c2c
2740 #define BNX2_MQ_KNL_COND_ENQUEUE_MASK1                  0x00003c30
2741 #define BNX2_MQ_KNL_RX_V2P_MASK1                        0x00003c34
2742 #define BNX2_MQ_KNL_WRITE_MASK2                         0x00003c38
2743 #define BNX2_MQ_KNL_TX_MASK2                            0x00003c3c
2744 #define BNX2_MQ_KNL_CMD_MASK2                           0x00003c40
2745 #define BNX2_MQ_KNL_COND_ENQUEUE_MASK2                  0x00003c44
2746 #define BNX2_MQ_KNL_RX_V2P_MASK2                        0x00003c48
2747 #define BNX2_MQ_KNL_BYP_WRITE_MASK1                     0x00003c4c
2748 #define BNX2_MQ_KNL_BYP_TX_MASK1                        0x00003c50
2749 #define BNX2_MQ_KNL_BYP_CMD_MASK1                       0x00003c54
2750 #define BNX2_MQ_KNL_BYP_COND_ENQUEUE_MASK1              0x00003c58
2751 #define BNX2_MQ_KNL_BYP_RX_V2P_MASK1                    0x00003c5c
2752 #define BNX2_MQ_KNL_BYP_WRITE_MASK2                     0x00003c60
2753 #define BNX2_MQ_KNL_BYP_TX_MASK2                        0x00003c64
2754 #define BNX2_MQ_KNL_BYP_CMD_MASK2                       0x00003c68
2755 #define BNX2_MQ_KNL_BYP_COND_ENQUEUE_MASK2              0x00003c6c
2756 #define BNX2_MQ_KNL_BYP_RX_V2P_MASK2                    0x00003c70
2757 #define BNX2_MQ_MEM_WR_ADDR                             0x00003c74
2758 #define BNX2_MQ_MEM_WR_ADDR_VALUE                        (0x3fL<<0)
2759
2760 #define BNX2_MQ_MEM_WR_DATA0                            0x00003c78
2761 #define BNX2_MQ_MEM_WR_DATA0_VALUE                       (0xffffffffL<<0)
2762
2763 #define BNX2_MQ_MEM_WR_DATA1                            0x00003c7c
2764 #define BNX2_MQ_MEM_WR_DATA1_VALUE                       (0xffffffffL<<0)
2765
2766 #define BNX2_MQ_MEM_WR_DATA2                            0x00003c80
2767 #define BNX2_MQ_MEM_WR_DATA2_VALUE                       (0x3fffffffL<<0)
2768
2769 #define BNX2_MQ_MEM_RD_ADDR                             0x00003c84
2770 #define BNX2_MQ_MEM_RD_ADDR_VALUE                        (0x3fL<<0)
2771
2772 #define BNX2_MQ_MEM_RD_DATA0                            0x00003c88
2773 #define BNX2_MQ_MEM_RD_DATA0_VALUE                       (0xffffffffL<<0)
2774
2775 #define BNX2_MQ_MEM_RD_DATA1                            0x00003c8c
2776 #define BNX2_MQ_MEM_RD_DATA1_VALUE                       (0xffffffffL<<0)
2777
2778 #define BNX2_MQ_MEM_RD_DATA2                            0x00003c90
2779 #define BNX2_MQ_MEM_RD_DATA2_VALUE                       (0x3fffffffL<<0)
2780
2781
2782
2783 /*
2784  *  tbdr_reg definition
2785  *  offset: 0x5000
2786  */
2787 #define BNX2_TBDR_COMMAND                               0x00005000
2788 #define BNX2_TBDR_COMMAND_ENABLE                         (1L<<0)
2789 #define BNX2_TBDR_COMMAND_SOFT_RST                       (1L<<1)
2790 #define BNX2_TBDR_COMMAND_MSTR_ABORT                     (1L<<4)
2791
2792 #define BNX2_TBDR_STATUS                                0x00005004
2793 #define BNX2_TBDR_STATUS_DMA_WAIT                        (1L<<0)
2794 #define BNX2_TBDR_STATUS_FTQ_WAIT                        (1L<<1)
2795 #define BNX2_TBDR_STATUS_FIFO_OVERFLOW                   (1L<<2)
2796 #define BNX2_TBDR_STATUS_FIFO_UNDERFLOW                  (1L<<3)
2797 #define BNX2_TBDR_STATUS_SEARCHMISS_ERROR                (1L<<4)
2798 #define BNX2_TBDR_STATUS_FTQ_ENTRY_CNT                   (1L<<5)
2799 #define BNX2_TBDR_STATUS_BURST_CNT                       (1L<<6)
2800
2801 #define BNX2_TBDR_CONFIG                                0x00005008
2802 #define BNX2_TBDR_CONFIG_MAX_BDS                         (0xffL<<0)
2803 #define BNX2_TBDR_CONFIG_SWAP_MODE                       (1L<<8)
2804 #define BNX2_TBDR_CONFIG_PRIORITY                        (1L<<9)
2805 #define BNX2_TBDR_CONFIG_CACHE_NEXT_PAGE_PTRS            (1L<<10)
2806 #define BNX2_TBDR_CONFIG_PAGE_SIZE                       (0xfL<<24)
2807 #define BNX2_TBDR_CONFIG_PAGE_SIZE_256                   (0L<<24)
2808 #define BNX2_TBDR_CONFIG_PAGE_SIZE_512                   (1L<<24)
2809 #define BNX2_TBDR_CONFIG_PAGE_SIZE_1K                    (2L<<24)
2810 #define BNX2_TBDR_CONFIG_PAGE_SIZE_2K                    (3L<<24)
2811 #define BNX2_TBDR_CONFIG_PAGE_SIZE_4K                    (4L<<24)
2812 #define BNX2_TBDR_CONFIG_PAGE_SIZE_8K                    (5L<<24)
2813 #define BNX2_TBDR_CONFIG_PAGE_SIZE_16K                   (6L<<24)
2814 #define BNX2_TBDR_CONFIG_PAGE_SIZE_32K                   (7L<<24)
2815 #define BNX2_TBDR_CONFIG_PAGE_SIZE_64K                   (8L<<24)
2816 #define BNX2_TBDR_CONFIG_PAGE_SIZE_128K                  (9L<<24)
2817 #define BNX2_TBDR_CONFIG_PAGE_SIZE_256K                  (10L<<24)
2818 #define BNX2_TBDR_CONFIG_PAGE_SIZE_512K                  (11L<<24)
2819 #define BNX2_TBDR_CONFIG_PAGE_SIZE_1M                    (12L<<24)
2820
2821 #define BNX2_TBDR_DEBUG_VECT_PEEK                       0x0000500c
2822 #define BNX2_TBDR_DEBUG_VECT_PEEK_1_VALUE                (0x7ffL<<0)
2823 #define BNX2_TBDR_DEBUG_VECT_PEEK_1_PEEK_EN              (1L<<11)
2824 #define BNX2_TBDR_DEBUG_VECT_PEEK_1_SEL                  (0xfL<<12)
2825 #define BNX2_TBDR_DEBUG_VECT_PEEK_2_VALUE                (0x7ffL<<16)
2826 #define BNX2_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN              (1L<<27)
2827 #define BNX2_TBDR_DEBUG_VECT_PEEK_2_SEL                  (0xfL<<28)
2828
2829 #define BNX2_TBDR_FTQ_DATA                              0x000053c0
2830 #define BNX2_TBDR_FTQ_CMD                               0x000053f8
2831 #define BNX2_TBDR_FTQ_CMD_OFFSET                         (0x3ffL<<0)
2832 #define BNX2_TBDR_FTQ_CMD_WR_TOP                         (1L<<10)
2833 #define BNX2_TBDR_FTQ_CMD_WR_TOP_0                       (0L<<10)
2834 #define BNX2_TBDR_FTQ_CMD_WR_TOP_1                       (1L<<10)
2835 #define BNX2_TBDR_FTQ_CMD_SFT_RESET                      (1L<<25)
2836 #define BNX2_TBDR_FTQ_CMD_RD_DATA                        (1L<<26)
2837 #define BNX2_TBDR_FTQ_CMD_ADD_INTERVEN                   (1L<<27)
2838 #define BNX2_TBDR_FTQ_CMD_ADD_DATA                       (1L<<28)
2839 #define BNX2_TBDR_FTQ_CMD_INTERVENE_CLR                  (1L<<29)
2840 #define BNX2_TBDR_FTQ_CMD_POP                            (1L<<30)
2841 #define BNX2_TBDR_FTQ_CMD_BUSY                           (1L<<31)
2842
2843 #define BNX2_TBDR_FTQ_CTL                               0x000053fc
2844 #define BNX2_TBDR_FTQ_CTL_INTERVENE                      (1L<<0)
2845 #define BNX2_TBDR_FTQ_CTL_OVERFLOW                       (1L<<1)
2846 #define BNX2_TBDR_FTQ_CTL_FORCE_INTERVENE                (1L<<2)
2847 #define BNX2_TBDR_FTQ_CTL_MAX_DEPTH                      (0x3ffL<<12)
2848 #define BNX2_TBDR_FTQ_CTL_CUR_DEPTH                      (0x3ffL<<22)
2849
2850
2851
2852 /*
2853  *  tdma_reg definition
2854  *  offset: 0x5c00
2855  */
2856 #define BNX2_TDMA_COMMAND                               0x00005c00
2857 #define BNX2_TDMA_COMMAND_ENABLED                        (1L<<0)
2858 #define BNX2_TDMA_COMMAND_MASTER_ABORT                   (1L<<4)
2859 #define BNX2_TDMA_COMMAND_BAD_L2_LENGTH_ABORT            (1L<<7)
2860
2861 #define BNX2_TDMA_STATUS                                0x00005c04
2862 #define BNX2_TDMA_STATUS_DMA_WAIT                        (1L<<0)
2863 #define BNX2_TDMA_STATUS_PAYLOAD_WAIT                    (1L<<1)
2864 #define BNX2_TDMA_STATUS_PATCH_FTQ_WAIT                  (1L<<2)
2865 #define BNX2_TDMA_STATUS_LOCK_WAIT                       (1L<<3)
2866 #define BNX2_TDMA_STATUS_FTQ_ENTRY_CNT                   (1L<<16)
2867 #define BNX2_TDMA_STATUS_BURST_CNT                       (1L<<17)
2868
2869 #define BNX2_TDMA_CONFIG                                0x00005c08
2870 #define BNX2_TDMA_CONFIG_ONE_DMA                         (1L<<0)
2871 #define BNX2_TDMA_CONFIG_ONE_RECORD                      (1L<<1)
2872 #define BNX2_TDMA_CONFIG_LIMIT_SZ                        (0xfL<<4)
2873 #define BNX2_TDMA_CONFIG_LIMIT_SZ_64                     (0L<<4)
2874 #define BNX2_TDMA_CONFIG_LIMIT_SZ_128                    (0x4L<<4)
2875 #define BNX2_TDMA_CONFIG_LIMIT_SZ_256                    (0x6L<<4)
2876 #define BNX2_TDMA_CONFIG_LIMIT_SZ_512                    (0x8L<<4)
2877 #define BNX2_TDMA_CONFIG_LINE_SZ                         (0xfL<<8)
2878 #define BNX2_TDMA_CONFIG_LINE_SZ_64                      (0L<<8)
2879 #define BNX2_TDMA_CONFIG_LINE_SZ_128                     (4L<<8)
2880 #define BNX2_TDMA_CONFIG_LINE_SZ_256                     (6L<<8)
2881 #define BNX2_TDMA_CONFIG_LINE_SZ_512                     (8L<<8)
2882 #define BNX2_TDMA_CONFIG_ALIGN_ENA                       (1L<<15)
2883 #define BNX2_TDMA_CONFIG_CHK_L2_BD                       (1L<<16)
2884 #define BNX2_TDMA_CONFIG_FIFO_CMP                        (0xfL<<20)
2885
2886 #define BNX2_TDMA_PAYLOAD_PROD                          0x00005c0c
2887 #define BNX2_TDMA_PAYLOAD_PROD_VALUE                     (0x1fffL<<3)
2888
2889 #define BNX2_TDMA_DBG_WATCHDOG                          0x00005c10
2890 #define BNX2_TDMA_DBG_TRIGGER                           0x00005c14
2891 #define BNX2_TDMA_DMAD_FSM                              0x00005c80
2892 #define BNX2_TDMA_DMAD_FSM_BD_INVLD                      (1L<<0)
2893 #define BNX2_TDMA_DMAD_FSM_PUSH                          (0xfL<<4)
2894 #define BNX2_TDMA_DMAD_FSM_ARB_TBDC                      (0x3L<<8)
2895 #define BNX2_TDMA_DMAD_FSM_ARB_CTX                       (1L<<12)
2896 #define BNX2_TDMA_DMAD_FSM_DR_INTF                       (1L<<16)
2897 #define BNX2_TDMA_DMAD_FSM_DMAD                          (0x7L<<20)
2898 #define BNX2_TDMA_DMAD_FSM_BD                            (0xfL<<24)
2899
2900 #define BNX2_TDMA_DMAD_STATUS                           0x00005c84
2901 #define BNX2_TDMA_DMAD_STATUS_RHOLD_PUSH_ENTRY           (0x3L<<0)
2902 #define BNX2_TDMA_DMAD_STATUS_RHOLD_DMAD_ENTRY           (0x3L<<4)
2903 #define BNX2_TDMA_DMAD_STATUS_RHOLD_BD_ENTRY             (0x3L<<8)
2904 #define BNX2_TDMA_DMAD_STATUS_IFTQ_ENUM                  (0xfL<<12)
2905
2906 #define BNX2_TDMA_DR_INTF_FSM                           0x00005c88
2907 #define BNX2_TDMA_DR_INTF_FSM_L2_COMP                    (0x3L<<0)
2908 #define BNX2_TDMA_DR_INTF_FSM_TPATQ                      (0x7L<<4)
2909 #define BNX2_TDMA_DR_INTF_FSM_TPBUF                      (0x3L<<8)
2910 #define BNX2_TDMA_DR_INTF_FSM_DR_BUF                     (0x7L<<12)
2911 #define BNX2_TDMA_DR_INTF_FSM_DMAD                       (0x7L<<16)
2912
2913 #define BNX2_TDMA_DR_INTF_STATUS                        0x00005c8c
2914 #define BNX2_TDMA_DR_INTF_STATUS_HOLE_PHASE              (0x7L<<0)
2915 #define BNX2_TDMA_DR_INTF_STATUS_DATA_AVAIL              (0x3L<<4)
2916 #define BNX2_TDMA_DR_INTF_STATUS_SHIFT_ADDR              (0x7L<<8)
2917 #define BNX2_TDMA_DR_INTF_STATUS_NXT_PNTR                (0xfL<<12)
2918 #define BNX2_TDMA_DR_INTF_STATUS_BYTE_COUNT              (0x7L<<16)
2919
2920 #define BNX2_TDMA_FTQ_DATA                              0x00005fc0
2921 #define BNX2_TDMA_FTQ_CMD                               0x00005ff8
2922 #define BNX2_TDMA_FTQ_CMD_OFFSET                         (0x3ffL<<0)
2923 #define BNX2_TDMA_FTQ_CMD_WR_TOP                         (1L<<10)
2924 #define BNX2_TDMA_FTQ_CMD_WR_TOP_0                       (0L<<10)
2925 #define BNX2_TDMA_FTQ_CMD_WR_TOP_1                       (1L<<10)
2926 #define BNX2_TDMA_FTQ_CMD_SFT_RESET                      (1L<<25)
2927 #define BNX2_TDMA_FTQ_CMD_RD_DATA                        (1L<<26)
2928 #define BNX2_TDMA_FTQ_CMD_ADD_INTERVEN                   (1L<<27)
2929 #define BNX2_TDMA_FTQ_CMD_ADD_DATA                       (1L<<28)
2930 #define BNX2_TDMA_FTQ_CMD_INTERVENE_CLR                  (1L<<29)
2931 #define BNX2_TDMA_FTQ_CMD_POP                            (1L<<30)
2932 #define BNX2_TDMA_FTQ_CMD_BUSY                           (1L<<31)
2933
2934 #define BNX2_TDMA_FTQ_CTL                               0x00005ffc
2935 #define BNX2_TDMA_FTQ_CTL_INTERVENE                      (1L<<0)
2936 #define BNX2_TDMA_FTQ_CTL_OVERFLOW                       (1L<<1)
2937 #define BNX2_TDMA_FTQ_CTL_FORCE_INTERVENE                (1L<<2)
2938 #define BNX2_TDMA_FTQ_CTL_MAX_DEPTH                      (0x3ffL<<12)
2939 #define BNX2_TDMA_FTQ_CTL_CUR_DEPTH                      (0x3ffL<<22)
2940
2941
2942
2943 /*
2944  *  hc_reg definition
2945  *  offset: 0x6800
2946  */
2947 #define BNX2_HC_COMMAND                                 0x00006800
2948 #define BNX2_HC_COMMAND_ENABLE                           (1L<<0)
2949 #define BNX2_HC_COMMAND_SKIP_ABORT                       (1L<<4)
2950 #define BNX2_HC_COMMAND_COAL_NOW                         (1L<<16)
2951 #define BNX2_HC_COMMAND_COAL_NOW_WO_INT                  (1L<<17)
2952 #define BNX2_HC_COMMAND_STATS_NOW                        (1L<<18)
2953 #define BNX2_HC_COMMAND_FORCE_INT                        (0x3L<<19)
2954 #define BNX2_HC_COMMAND_FORCE_INT_NULL                   (0L<<19)
2955 #define BNX2_HC_COMMAND_FORCE_INT_HIGH                   (1L<<19)
2956 #define BNX2_HC_COMMAND_FORCE_INT_LOW                    (2L<<19)
2957 #define BNX2_HC_COMMAND_FORCE_INT_FREE                   (3L<<19)
2958 #define BNX2_HC_COMMAND_CLR_STAT_NOW                     (1L<<21)
2959
2960 #define BNX2_HC_STATUS                                  0x00006804
2961 #define BNX2_HC_STATUS_MASTER_ABORT                      (1L<<0)
2962 #define BNX2_HC_STATUS_PARITY_ERROR_STATE                (1L<<1)
2963 #define BNX2_HC_STATUS_PCI_CLK_CNT_STAT                  (1L<<16)
2964 #define BNX2_HC_STATUS_CORE_CLK_CNT_STAT                 (1L<<17)
2965 #define BNX2_HC_STATUS_NUM_STATUS_BLOCKS_STAT            (1L<<18)
2966 #define BNX2_HC_STATUS_NUM_INT_GEN_STAT                  (1L<<19)
2967 #define BNX2_HC_STATUS_NUM_INT_MBOX_WR_STAT              (1L<<20)
2968 #define BNX2_HC_STATUS_CORE_CLKS_TO_HW_INTACK_STAT       (1L<<23)
2969 #define BNX2_HC_STATUS_CORE_CLKS_TO_SW_INTACK_STAT       (1L<<24)
2970 #define BNX2_HC_STATUS_CORE_CLKS_DURING_SW_INTACK_STAT   (1L<<25)
2971
2972 #define BNX2_HC_CONFIG                                  0x00006808
2973 #define BNX2_HC_CONFIG_COLLECT_STATS                     (1L<<0)
2974 #define BNX2_HC_CONFIG_RX_TMR_MODE                       (1L<<1)
2975 #define BNX2_HC_CONFIG_TX_TMR_MODE                       (1L<<2)
2976 #define BNX2_HC_CONFIG_COM_TMR_MODE                      (1L<<3)
2977 #define BNX2_HC_CONFIG_CMD_TMR_MODE                      (1L<<4)
2978 #define BNX2_HC_CONFIG_STATISTIC_PRIORITY                (1L<<5)
2979 #define BNX2_HC_CONFIG_STATUS_PRIORITY                   (1L<<6)
2980 #define BNX2_HC_CONFIG_STAT_MEM_ADDR                     (0xffL<<8)
2981
2982 #define BNX2_HC_ATTN_BITS_ENABLE                        0x0000680c
2983 #define BNX2_HC_STATUS_ADDR_L                           0x00006810
2984 #define BNX2_HC_STATUS_ADDR_H                           0x00006814
2985 #define BNX2_HC_STATISTICS_ADDR_L                       0x00006818
2986 #define BNX2_HC_STATISTICS_ADDR_H                       0x0000681c
2987 #define BNX2_HC_TX_QUICK_CONS_TRIP                      0x00006820
2988 #define BNX2_HC_TX_QUICK_CONS_TRIP_VALUE                 (0xffL<<0)
2989 #define BNX2_HC_TX_QUICK_CONS_TRIP_INT                   (0xffL<<16)
2990
2991 #define BNX2_HC_COMP_PROD_TRIP                          0x00006824
2992 #define BNX2_HC_COMP_PROD_TRIP_VALUE                     (0xffL<<0)
2993 #define BNX2_HC_COMP_PROD_TRIP_INT                       (0xffL<<16)
2994
2995 #define BNX2_HC_RX_QUICK_CONS_TRIP                      0x00006828
2996 #define BNX2_HC_RX_QUICK_CONS_TRIP_VALUE                 (0xffL<<0)
2997 #define BNX2_HC_RX_QUICK_CONS_TRIP_INT                   (0xffL<<16)
2998
2999 #define BNX2_HC_RX_TICKS                                0x0000682c
3000 #define BNX2_HC_RX_TICKS_VALUE                           (0x3ffL<<0)
3001 #define BNX2_HC_RX_TICKS_INT                             (0x3ffL<<16)
3002
3003 #define BNX2_HC_TX_TICKS                                0x00006830
3004 #define BNX2_HC_TX_TICKS_VALUE                           (0x3ffL<<0)
3005 #define BNX2_HC_TX_TICKS_INT                             (0x3ffL<<16)
3006
3007 #define BNX2_HC_COM_TICKS                               0x00006834
3008 #define BNX2_HC_COM_TICKS_VALUE                          (0x3ffL<<0)
3009 #define BNX2_HC_COM_TICKS_INT                            (0x3ffL<<16)
3010
3011 #define BNX2_HC_CMD_TICKS                               0x00006838
3012 #define BNX2_HC_CMD_TICKS_VALUE                          (0x3ffL<<0)
3013 #define BNX2_HC_CMD_TICKS_INT                            (0x3ffL<<16)
3014
3015 #define BNX2_HC_PERIODIC_TICKS                          0x0000683c
3016 #define BNX2_HC_PERIODIC_TICKS_HC_PERIODIC_TICKS         (0xffffL<<0)
3017
3018 #define BNX2_HC_STAT_COLLECT_TICKS                      0x00006840
3019 #define BNX2_HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS    (0xffL<<4)
3020
3021 #define BNX2_HC_STATS_TICKS                             0x00006844
3022 #define BNX2_HC_STATS_TICKS_HC_STAT_TICKS                (0xffffL<<8)
3023
3024 #define BNX2_HC_STAT_MEM_DATA                           0x0000684c
3025 #define BNX2_HC_STAT_GEN_SEL_0                          0x00006850
3026 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0                 (0x7fL<<0)
3027 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0       (0L<<0)
3028 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1       (1L<<0)
3029 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2       (2L<<0)
3030 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3       (3L<<0)
3031 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4       (4L<<0)
3032 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5       (5L<<0)
3033 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6       (6L<<0)
3034 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7       (7L<<0)
3035 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8       (8L<<0)
3036 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9       (9L<<0)
3037 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10      (10L<<0)
3038 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11      (11L<<0)
3039 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0       (12L<<0)
3040 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1       (13L<<0)
3041 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2       (14L<<0)
3042 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3       (15L<<0)
3043 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4       (16L<<0)
3044 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5       (17L<<0)
3045 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6       (18L<<0)
3046 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7       (19L<<0)
3047 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0       (20L<<0)
3048 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1       (21L<<0)
3049 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2       (22L<<0)
3050 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3       (23L<<0)
3051 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4       (24L<<0)
3052 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5       (25L<<0)
3053 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6       (26L<<0)
3054 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7       (27L<<0)
3055 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8       (28L<<0)
3056 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9       (29L<<0)
3057 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10      (30L<<0)
3058 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11      (31L<<0)
3059 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0      (32L<<0)
3060 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1      (33L<<0)
3061 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2      (34L<<0)
3062 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3      (35L<<0)
3063 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0        (36L<<0)
3064 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1        (37L<<0)
3065 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2        (38L<<0)
3066 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3        (39L<<0)
3067 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4        (40L<<0)
3068 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5        (41L<<0)
3069 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6        (42L<<0)
3070 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7        (43L<<0)
3071 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0       (44L<<0)
3072 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1       (45L<<0)
3073 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2       (46L<<0)
3074 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3       (47L<<0)
3075 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4       (48L<<0)
3076 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5       (49L<<0)
3077 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6       (50L<<0)
3078 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7       (51L<<0)
3079 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_PCI_CLK_CNT     (52L<<0)
3080 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT    (53L<<0)
3081 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS    (54L<<0)
3082 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN  (55L<<0)
3083 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR      (56L<<0)
3084 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK       (59L<<0)
3085 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK       (60L<<0)
3086 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK   (61L<<0)
3087 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT    (62L<<0)
3088 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT   (63L<<0)
3089 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT    (64L<<0)
3090 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT   (65L<<0)
3091 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT         (66L<<0)
3092 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT  (67L<<0)
3093 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT         (68L<<0)
3094 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT        (69L<<0)
3095 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT        (70L<<0)
3096 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT        (71L<<0)
3097 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT         (72L<<0)
3098 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT         (73L<<0)
3099 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT         (74L<<0)
3100 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT  (75L<<0)
3101 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT         (76L<<0)
3102 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT         (77L<<0)
3103 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT  (78L<<0)
3104 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT   (79L<<0)
3105 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT   (80L<<0)
3106 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT         (81L<<0)
3107 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT         (82L<<0)
3108 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT  (83L<<0)
3109 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT  (84L<<0)
3110 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_TRANSFERS_CNT         (85L<<0)
3111 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_DELAY_PCI_CLKS_CNT    (86L<<0)
3112 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_TRANSFERS_CNT     (87L<<0)
3113 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_DELAY_PCI_CLKS_CNT        (88L<<0)