4 Copyright (c) 2006 -2007, Intel Corporation All rights
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5 reserved. This program and the accompanying materials are
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6 licensed and made available under the terms and conditions of
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7 the BSD License which accompanies this distribution. The full
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8 text of the license may be found at
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9 http://opensource.org/licenses/bsd-license.php
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11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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16 #ifndef __PAL_CALL_LIB_H__
\r
17 #define __PAL_CALL_LIB_H__
\r
19 #define PAL_SUCCESS 0x0
\r
22 // CacheType of PAL_CACHE_FLUSH.
\r
24 #define PAL_CACHE_FLUSH_INSTRUCTION_ALL 1
\r
25 #define PAL_CACHE_FLUSH_DATA_ALL 2
\r
26 #define PAL_CACHE_FLUSH_ALL 3
\r
27 #define PAL_CACHE_FLUSH_SYNC_TO_DATA 4
\r
31 // Bitmask of Opearation of PAL_CACHE_FLUSH.
\r
33 #define PAL_CACHE_FLUSH_INVALIDATE_LINES BIT0
\r
34 #define PAL_CACHE_FLUSH_NO_INVALIDATE_LINES 0
\r
35 #define PAL_CACHE_FLUSH_POLL_INTERRUPT BIT1
\r
36 #define PAL_CACHE_FLUSH_NO_INTERRUPT 0
\r
40 PAL Procedure - PAL_CACHE_FLUSH.
\r
42 Flush the instruction or data caches. It is required by IPF.
\r
43 The PAL procedure supports the Static Registers calling
\r
44 convention. It could be called at virtual mode and physical
\r
47 @param Index Index of PAL_CACHE_FLUSH within the
\r
48 list of PAL procedures.
\r
50 @param CacheType Unsigned 64-bit integer indicating
\r
51 which cache to flush.
\r
53 @param Operation Formatted bit vector indicating the
\r
54 operation of this call.
\r
56 @param ProgressIndicator Unsigned 64-bit integer specifying
\r
57 the starting position of the flush
\r
60 @return R9 Unsigned 64-bit integer specifying the vector
\r
61 number of the pending interrupt.
\r
63 @return R10 Unsigned 64-bit integer specifying the
\r
64 starting position of the flush operation.
\r
66 @return R11 Unsigned 64-bit integer specifying the vector
\r
67 number of the pending interrupt.
\r
69 @return Status 2 - Call completed without error, but a PMI
\r
70 was taken during the execution of this
\r
73 @return Status 1 - Call has not completed flushing due to
\r
74 a pending interrupt.
\r
76 @return Status 0 - Call completed without error
\r
78 @return Status -2 - Invalid argument
\r
80 @return Status -3 - Call completed with error
\r
83 #define PAL_CACHE_FLUSH 1
\r
87 // Attributes of PAL_CACHE_CONFIG_INFO1
\r
89 #define PAL_CACHE_ATTR_WT 0
\r
90 #define PAL_CACHE_ATTR_WB 1
\r
93 // PAL_CACHE_CONFIG_INFO1.StoreHint
\r
95 #define PAL_CACHE_STORE_TEMPORAL 0
\r
96 #define PAL_CACHE_STORE_NONE_TEMPORAL 3
\r
99 // PAL_CACHE_CONFIG_INFO1.StoreHint
\r
101 #define PAL_CACHE_STORE_TEMPORAL_LVL_1 0
\r
102 #define PAL_CACHE_STORE_NONE_TEMPORAL_LVL_ALL 3
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105 // PAL_CACHE_CONFIG_INFO1.StoreHint
\r
107 #define PAL_CACHE_LOAD_TEMPORAL_LVL_1 0
\r
108 #define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_1 1
\r
109 #define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_ALL 3
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112 // Detail the characteristics of a given processor controlled
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113 // cache in the cache hierarchy.
\r
116 UINT64 IsUnified : 1;
\r
117 UINT64 Attributes : 2;
\r
118 UINT64 Associativity:8;
\r
121 UINT64 StoreLatency:8;
\r
122 UINT64 StoreHint:8;
\r
124 } PAL_CACHE_INFO_RETURN1;
\r
127 // Detail the characteristics of a given processor controlled
\r
128 // cache in the cache hierarchy.
\r
131 UINT64 CacheSize:32;
\r
132 UINT64 AliasBoundary:8;
\r
133 UINT64 TagLsBits:8;
\r
134 UINT64 TagMsBits:8;
\r
135 } PAL_CACHE_INFO_RETURN2;
\r
139 PAL Procedure - PAL_CACHE_INFO.
\r
141 Return detailed instruction or data cache information. It is
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142 required by IPF. The PAL procedure supports the Static
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143 Registers calling convention. It could be called at virtual
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144 mode and physical mode.
\r
146 @param Index Index of PAL_CACHE_INFO within the list of
\r
149 @param CacheLevel Unsigned 64-bit integer specifying the
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150 level in the cache hierarchy for which
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151 information is requested. This value must
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152 be between 0 and one less than the value
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153 returned in the cache_levels return value
\r
154 from PAL_CACHE_SUMMARY.
\r
156 @param CacheType Unsigned 64-bit integer with a value of 1
\r
157 for instruction cache and 2 for data or
\r
158 unified cache. All other values are
\r
161 @param Reserved Should be 0.
\r
164 @return R9 Detail the characteristics of a given
\r
165 processor controlled cache in the cache
\r
166 hierarchy. See PAL_CACHE_INFO_RETURN1.
\r
168 @return R10 Detail the characteristics of a given
\r
169 processor controlled cache in the cache
\r
170 hierarchy. See PAL_CACHE_INFO_RETURN2.
\r
172 @return R11 Reserved with 0.
\r
175 @return Status 0 - Call completed without error
\r
177 @return Status -2 - Invalid argument
\r
179 @return Status -3 - Call completed with error
\r
182 #define PAL_CACHE_INFO 2
\r
187 // Level of PAL_CACHE_INIT.
\r
189 #define PAL_CACHE_INIT_ALL 0xffffffffffffffffULL
\r
194 #define PAL_CACHE_INIT_TYPE_INSTRUCTION 0x1
\r
195 #define PAL_CACHE_INIT_TYPE_DATA 0x2
\r
196 #define PAL_CACHE_INIT_TYPE_INSTRUCTION_AND_DATA 0x3
\r
199 // Restrict of PAL_CACHE_INIT.
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201 #define PAL_CACHE_INIT_NO_RESTRICT 0
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202 #define PAL_CACHE_INIT_RESTRICTED 1
\r
206 PAL Procedure - PAL_CACHE_INIT.
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208 Initialize the instruction or data caches. It is required by
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209 IPF. The PAL procedure supports the Static Registers calling
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210 convention. It could be called at physical mode.
\r
212 @param Index Index of PAL_CACHE_INIT within the list of PAL
\r
215 @param Level Unsigned 64-bit integer containing the level of
\r
216 cache to initialize. If the cache level can be
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217 initialized independently, only that level will
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218 be initialized. Otherwise
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219 implementation-dependent side-effects will
\r
222 @param CacheType Unsigned 64-bit integer with a value of 1 to
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223 initialize the instruction cache, 2 to
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224 initialize the data cache, or 3 to
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225 initialize both. All other values are
\r
228 @param Restrict Unsigned 64-bit integer with a value of 0 or
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229 1. All other values are reserved. If
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230 restrict is 1 and initializing the specified
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231 level and cache_type of the cache would
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232 cause side-effects, PAL_CACHE_INIT will
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233 return -4 instead of initializing the cache.
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236 @return Status 0 - Call completed without error
\r
238 @return Status -2 - Invalid argument
\r
240 @return Status -3 - Call completed with error.
\r
242 @return Status -4 - Call could not initialize the specified
\r
243 level and cache_type of the cache without
\r
244 side-effects and restrict was 1.
\r
247 #define PAL_CACHE_INIT 3
\r
251 // PAL_CACHE_PROTECTION.Method.
\r
253 #define PAL_CACHE_PROTECTION_NONE_PROTECT 0
\r
254 #define PAL_CACHE_PROTECTION_ODD_PROTECT 1
\r
255 #define PAL_CACHE_PROTECTION_EVEN_PROTECT 2
\r
256 #define PAL_CACHE_PROTECTION_ECC_PROTECT 3
\r
261 // PAL_CACHE_PROTECTION.TagOrData.
\r
263 #define PAL_CACHE_PROTECTION_PROTECT_DATA 0
\r
264 #define PAL_CACHE_PROTECTION_PROTECT_TAG 1
\r
265 #define PAL_CACHE_PROTECTION_PROTECT_TAG_ANDTHEN_DATA 2
\r
266 #define PAL_CACHE_PROTECTION_PROTECT_DATA_ANDTHEN_TAG 3
\r
269 // 32-bit protection information structures.
\r
273 UINT32 TagProtLsb:6;
\r
274 UINT32 TagProtMsb:6;
\r
277 UINT32 TagOrData:2;
\r
278 } PAL_CACHE_PROTECTION;
\r
282 PAL Procedure - PAL_CACHE_PROT_INFO.
\r
284 Return instruction or data cache protection information. It is
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285 required by IPF. The PAL procedure supports the Static
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286 Registers calling convention. It could be called at physical
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287 mode and Virtual mode.
\r
289 @param Index Index of PAL_CACHE_PROT_INFO within the list of
\r
292 @param CacheLevel Unsigned 64-bit integer specifying the level
\r
293 in the cache hierarchy for which information
\r
294 is requested. This value must be between 0
\r
295 and one less than the value returned in the
\r
296 cache_levels return value from
\r
299 @param CacheType Unsigned 64-bit integer with a value of 1
\r
300 for instruction cache and 2 for data or
\r
301 unified cache. All other values are
\r
304 @return R9 Detail the characteristics of a given
\r
305 processor controlled cache in the cache
\r
306 hierarchy. See PAL_CACHE_PROTECTION[0..1].
\r
308 @return R10 Detail the characteristics of a given
\r
309 processor controlled cache in the cache
\r
310 hierarchy. See PAL_CACHE_PROTECTION[2..3].
\r
312 @return R11 Detail the characteristics of a given
\r
313 processor controlled cache in the cache
\r
314 hierarchy. See PAL_CACHE_PROTECTION[4..5].
\r
317 @return Status 0 - Call completed without error
\r
319 @return Status -2 - Invalid argument
\r
321 @return Status -3 - Call completed with error.
\r
324 #define PAL_CACHE_PROT_INFO 38
\r
328 @param ThreadId The thread identifier of the logical
\r
329 processor for which information is being
\r
330 returned. This value will be unique on a per
\r
333 @param CoreId The core identifier of the logical processor
\r
334 for which information is being returned.
\r
335 This value will be unique on a per physical
\r
336 processor package basis.
\r
340 UINT64 ThreadId : 16;
\r
341 UINT64 Reserved1: 16;
\r
343 UINT64 Reserved2: 16;
\r
344 } PAL_PCOC_N_CACHE_INFO1;
\r
348 @param LogicalAddress Logical address: geographical address
\r
349 of the logical processor for which
\r
350 information is being returned. This is
\r
351 the same value that is returned by the
\r
352 PAL_FIXED_ADDR procedure when it is
\r
353 called on the logical processor.
\r
357 UINT64 LogicalAddress : 16;
\r
358 UINT64 Reserved1: 16;
\r
359 UINT64 Reserved2: 32;
\r
360 } PAL_PCOC_N_CACHE_INFO2;
\r
364 PAL Procedure - PAL_CACHE_SHARED_INFO.
\r
366 Returns information on which logical processors share caches.
\r
367 It is optional. The PAL procedure supports the Static
\r
368 Registers calling convention. It could be called at physical
\r
369 mode and Virtual mode.
\r
371 @param Index Index of PAL_CACHE_SHARED_INFO within the list
\r
374 @param CacheLevel Unsigned 64-bit integer specifying the
\r
375 level in the cache hierarchy for which
\r
376 information is requested. This value must
\r
377 be between 0 and one less than the value
\r
378 returned in the cache_levels return value
\r
379 from PAL_CACHE_SUMMARY.
\r
381 @param CacheType Unsigned 64-bit integer with a value of 1
\r
382 for instruction cache and 2 for data or
\r
383 unified cache. All other values are
\r
386 @param ProcNumber Unsigned 64-bit integer that specifies for
\r
387 which logical processor information is
\r
388 being requested. This input argument must
\r
389 be zero for the first call to this
\r
390 procedure and can be a maximum value of
\r
391 one less than the number of logical
\r
392 processors sharing this cache, which is
\r
393 returned by the num_shared return value.
\r
395 @return R9 Unsigned integer that returns the number of
\r
396 logical processors that share the processor
\r
397 cache level and type, for which information was
\r
400 @return R10 The format of PAL_PCOC_N_CACHE_INFO1.
\r
402 @return R11 The format of PAL_PCOC_N_CACHE_INFO2.
\r
404 @return Status 0 - Call completed without error
\r
406 @return Status -1 - Unimplemented procedure
\r
408 @return Status -2 - Invalid argument
\r
410 @return Status -3 - Call completed with error.
\r
413 #define PAL_CACHE_SHARED_INFO 43
\r
418 PAL Procedure - PAL_CACHE_SUMMARY.
\r
420 Return a summary of the cache hierarchy. It is required by
\r
421 IPF. The PAL procedure supports the Static Registers calling
\r
422 convention. It could be called at physical mode and Virtual
\r
425 @param Index Index of PAL_CACHE_SUMMARY within the list of
\r
429 @return R9 CacheLevels Unsigned 64-bit integer denoting the
\r
430 number of levels of cache
\r
431 implemented by the processor.
\r
432 Strictly, this is the number of
\r
433 levels for which the cache
\r
434 controller is integrated into the
\r
435 processor (the cache SRAMs may be
\r
436 external to the processor).
\r
438 @return R10 UniqueCaches Unsigned 64-bit integer denoting the
\r
439 number of unique caches implemented
\r
440 by the processor. This has a maximum
\r
441 of 2*cache_levels, but may be less
\r
442 if any of the levels in the cache
\r
443 hierarchy are unified caches or do
\r
444 not have both instruction and data
\r
447 @return Status 0 - Call completed without error
\r
449 @return Status -2 - Invalid argument
\r
451 @return Status -3 - Call completed with error.
\r
454 #define PAL_CACHE_SUMMARY 4
\r
458 // Virtual Memory Attributes implemented by processor.
\r
460 #define PAL_MEMORY_ATTR_WB 0
\r
461 #define PAL_MEMORY_ATTR_WC 6
\r
462 #define PAL_MEMORY_ATTR_UC 4
\r
463 #define PAL_MEMORY_ATTR_UCE 5
\r
464 #define PAL_MEMORY_ATTR_NATPAGE 7
\r
468 PAL Procedure - PAL_MEM_ATTRIB.
\r
470 Return a list of supported memory attributes.. It is required
\r
471 by IPF. The PAL procedure supports the Static Registers calling
\r
472 convention. It could be called at physical mode and Virtual
\r
475 @param Index Index of PAL_MEM_ATTRIB within the list of PAL
\r
479 @return R9 Attributes 8-bit vector of memory attributes
\r
480 implemented by processor. See Virtual
\r
481 Memory Attributes above.
\r
483 @return Status 0 - Call completed without error
\r
485 @return Status -2 - Invalid argument
\r
487 @return Status -3 - Call completed with error.
\r
491 #define PAL_MEM_ATTRIB 5
\r
495 PAL Procedure - PAL_PREFETCH_VISIBILITY.
\r
497 Used in architected sequence to transition pages from a
\r
498 cacheable, speculative attribute to an uncacheable attribute.
\r
499 It is required by IPF. The PAL procedure supports the Static
\r
500 Registers calling convention. It could be called at physical
\r
501 mode and Virtual mode.
\r
503 @param Index Index of PAL_PREFETCH_VISIBILITY within the list
\r
506 @param TransitionType Unsigned integer specifying the type
\r
507 of memory attribute transition that is
\r
510 @return Status 1 Call completed without error; this
\r
511 call is not necessary on remote
\r
514 @return Status 0 - Call completed without error
\r
516 @return Status -2 - Invalid argument
\r
518 @return Status -3 - Call completed with error.
\r
521 #define PAL_PREFETCH_VISIBILITY 41
\r
525 PAL Procedure - PAL_PTCE_INFO.
\r
527 Return information needed for ptc.e instruction to purge
\r
528 entire TC. It is required by IPF. The PAL procedure supports
\r
529 the Static Registers calling convention. It could be called at
\r
530 physical mode and Virtual mode.
\r
532 @param Index Index of PAL_PTCE_INFO within the list
\r
535 @return R9 Unsigned 64-bit integer denoting the beginning
\r
536 address to be used by the first PTCE instruction
\r
539 @return R10 Two unsigned 32-bit integers denoting the loop
\r
540 counts of the outer (loop 1) and inner (loop 2)
\r
541 purge loops. count1 (loop 1) is contained in bits
\r
542 63:32 of the parameter, and count2 (loop 2) is
\r
543 contained in bits 31:0 of the parameter.
\r
545 @return R11 Two unsigned 32-bit integers denoting the loop
\r
546 strides of the outer (loop 1) and inner (loop 2)
\r
547 purge loops. stride1 (loop 1) is contained in bits
\r
548 63:32 of the parameter, and stride2 (loop 2) is
\r
549 contained in bits 31:0 of the parameter.
\r
551 @return Status 0 - Call completed without error
\r
553 @return Status -2 - Invalid argument
\r
555 @return Status -3 - Call completed with error.
\r
558 #define PAL_PTCE_INFO 6
\r
564 @param NumberSets Unsigned 8-bit integer denoting the number
\r
565 of hash sets for the specified level
\r
566 (1=fully associative)
\r
568 @param NumberWays Unsigned 8-bit integer denoting the
\r
569 associativity of the specified level
\r
572 @param NumberEntries Unsigned 16-bit integer denoting the
\r
573 number of entries in the specified TC.
\r
576 @param PageSizeIsOptimized Flag denoting whether the
\r
577 specified level is optimized for
\r
578 the region's preferred page size
\r
579 (1=optimized) tc_pages indicates
\r
580 which page sizes are usable by
\r
581 this translation cache.
\r
583 @param TcIsUnified Flag denoting whether the specified TC is
\r
584 unified (1=unified).
\r
586 @param EntriesReduction Flag denoting whether installed
\r
587 translation registers will reduce
\r
588 the number of entries within the
\r
593 UINT64 NumberSets:8;
\r
594 UINT64 NumberWays:8;
\r
595 UINT64 NumberEntries:16;
\r
596 UINT64 PageSizeIsOptimized:1;
\r
597 UINT64 TcIsUnified:1;
\r
598 UINT64 EntriesReduction:1;
\r
603 PAL Procedure - PAL_VM_INFO.
\r
605 Return detailed information about virtual memory features
\r
606 supported in the processor. It is required by IPF. The PAL
\r
607 procedure supports the Static Registers calling convention. It
\r
608 could be called at physical mode and Virtual mode.
\r
610 @param Index Index of PAL_VM_INFO within the list
\r
613 @param TcLevel Unsigned 64-bit integer specifying the level
\r
614 in the TLB hierarchy for which information is
\r
615 required. This value must be between 0 and one
\r
616 less than the value returned in the
\r
617 vm_info_1.num_tc_levels return value from
\r
620 @param TcType Unsigned 64-bit integer with a value of 1 for
\r
621 instruction translation cache and 2 for data
\r
622 or unified translation cache. All other values
\r
625 @return R9 8-byte formatted value returning information
\r
626 about the specified TC. See PAL_TC_INFO above.
\r
628 @return R10 64-bit vector containing a bit for each page
\r
629 size supported in the specified TC, where bit
\r
630 position n indicates a page size of 2**n.
\r
632 @return Status 0 - Call completed without error
\r
634 @return Status -2 - Invalid argument
\r
636 @return Status -3 - Call completed with error.
\r
639 #define PAL_VM_INFO 7
\r
644 PAL Procedure - PAL_VM_PAGE_SIZE.
\r
646 Return virtual memory TC and hardware walker page sizes
\r
647 supported in the processor. It is required by IPF. The PAL
\r
648 procedure supports the Static Registers calling convention. It
\r
649 could be called at physical mode and Virtual mode.
\r
651 @param Index Index of PAL_VM_PAGE_SIZE within the list
\r
655 @return R9 64-bit vector containing a bit for each
\r
656 architected page size that is supported for
\r
657 TLB insertions and region registers.
\r
659 @return R10 64-bit vector containing a bit for each
\r
660 architected page size supported for TLB purge
\r
663 @return Status 0 - Call completed without error
\r
665 @return Status -2 - Invalid argument
\r
667 @return Status -3 - Call completed with error.
\r
670 #define PAL_VM_PAGE_SIZE 34
\r
674 @param WalkerPresent 1-bit flag indicating whether a hardware
\r
675 TLB walker is implemented (1 = walker
\r
678 @param WidthOfPhysicalAddress Unsigned 7-bit integer
\r
679 denoting the number of bits of
\r
680 physical address implemented.
\r
682 @param WidthOfKey Unsigned 8-bit integer denoting the number
\r
683 of bits mplemented in the PKR.key field.
\r
685 @param MaxPkrIndex Unsigned 8-bit integer denoting the
\r
686 maximum PKR index (number of PKRs-1).
\r
688 @param HashTagId Unsigned 8-bit integer which uniquely
\r
689 identifies the processor hash and tag
\r
692 @param MaxDtrIndex Unsigned 8 bit integer denoting the
\r
693 maximum data translation register index
\r
694 (number of dtr entries - 1).
\r
696 @param MaxItrIndex Unsigned 8 bit integer denoting the
\r
697 maximum instruction translation register
\r
698 index (number of itr entries - 1).
\r
700 @param NumberOfUniqueTc Unsigned 8-bit integer denoting the
\r
701 number of unique TCs implemented.
\r
702 This is a maximum of
\r
705 @param NumberOfTcLevels Unsigned 8-bit integer denoting the
\r
706 number of TC levels.
\r
710 UINT64 WalkerPresent:1;
\r
711 UINT64 WidthOfPhysicalAddress: 7;
\r
712 UINT64 WidthOfKey:8;
\r
713 UINT64 MaxPkrIndex:8;
\r
714 UINT64 HashTagId:8;
\r
715 UINT64 MaxDtrIndex:8;
\r
716 UINT64 MaxItrIndex:8;
\r
717 UINT64 NumberOfUniqueTc:8;
\r
718 UINT64 NumberOfTcLevels:8;
\r
723 @param WidthOfVirtualAddress Unsigned 8-bit integer denoting
\r
724 is the total number of virtual
\r
727 @param WidthOfRid Unsigned 8-bit integer denoting the number
\r
728 of bits implemented in the RR.rid field.
\r
730 @param MaxPurgedTlbs Unsigned 16 bit integer denoting the
\r
731 maximum number of concurrent outstanding
\r
732 TLB purges allowed by the processor. A
\r
733 value of 0 indicates one outstanding
\r
734 purge allowed. A value of 216-1
\r
735 indicates no limit on outstanding
\r
736 purges. All other values indicate the
\r
737 actual number of concurrent outstanding
\r
742 UINT64 WidthOfVirtualAddress:8;
\r
743 UINT64 WidthOfRid:8;
\r
744 UINT64 MaxPurgedTlbs:16;
\r
745 UINT64 Reserved:32;
\r
750 PAL Procedure - PAL_VM_SUMMARY.
\r
752 Return summary information about virtual memory features
\r
753 supported in the processor. It is required by IPF. The PAL
\r
754 procedure supports the Static Registers calling convention. It
\r
755 could be called at physical mode and Virtual mode.
\r
757 @param Index Index of PAL_VM_SUMMARY within the list
\r
761 @return R9 8-byte formatted value returning global virtual
\r
762 memory information. See PAL_VM_INFO1 above.
\r
764 @return R10 8-byte formatted value returning global virtual
\r
765 memory information. See PAL_VM_INFO2 above.
\r
767 @return Status 0 - Call completed without error
\r
769 @return Status -2 - Invalid argument
\r
771 @return Status -3 - Call completed with error.
\r
774 #define PAL_VM_SUMMARY 8
\r
778 // Bit mask of TR_valid flag.
\r
780 #define PAL_TR_ACCESS_RIGHT_IS_VALID BIT0
\r
781 #define PAL_TR_PRIVILEGE_LEVEL_IS_VALID BIT1
\r
782 #define PAL_TR_DIRTY_IS_VALID BIT2
\r
783 #define PAL_TR_MEMORY_ATTR_IS_VALID BIT3
\r
788 PAL Procedure - PAL_VM_TR_READ.
\r
790 Read contents of a translation register. It is required by
\r
791 IPF. The PAL procedure supports the Stacked Register calling
\r
792 convention. It could be called at physical mode.
\r
794 @param Index Index of PAL_VM_TR_READ within the list
\r
797 @param RegNumber Unsigned 64-bit number denoting which TR to
\r
800 @param TrType Unsigned 64-bit number denoting whether to
\r
801 read an ITR (0) or DTR (1). All other values
\r
804 @param TrBuffer 64-bit pointer to the 32-byte memory buffer in
\r
805 which translation data is returned.
\r
807 @return R9 Formatted bit vector denoting which fields are
\r
808 valid. See TR_valid above.
\r
810 @return Status 0 - Call completed without error
\r
812 @return Status -2 - Invalid argument
\r
814 @return Status -3 - Call completed with error.
\r
817 #define PAL_VM_TR_READ 261
\r
823 // Bit Mask of Processor Bus Fesatures .
\r
828 When 0, bus data errors are detected and single bit errors are
\r
829 corrected. When 1, no error detection or correction is done.
\r
832 #define PAL_BUS_DISABLE_DATA_ERROR_SIGNALLING BIT63
\r
837 When 0, bus address errors are signalled on the bus. When 1,
\r
838 no bus errors are signalled on the bus. If Disable Bus Address
\r
839 Error Checking is 1, this bit is ignored.
\r
842 #define PAL_BUS_DISABLE_ADDRESS_ERROR_SIGNALLING BIT62
\r
849 When 0, bus errors are detected, single bit errors are
\r
850 corrected., and a CMCI or MCA is generated internally to the
\r
851 processor. When 1, no bus address errors are detected or
\r
855 #define PAL_BUS_DISABLE_ADDRESS_ERROR_CHECK BIT61
\r
860 When 0, bus protocol errors (BINIT#) are signaled by the
\r
861 processor on the bus. When 1, bus protocol errors (BINIT#) are
\r
862 not signaled on the bus. If Disable Bus Initialization Event
\r
863 Checking is 1, this bit is ignored.
\r
866 #define PAL_BUS_DISABLE_INITIALIZATION_EVENT_SIGNALLING BIT60
\r
871 When 0, bus protocol errors (BINIT#) are detected and sampled
\r
872 and an MCA is generated internally to the processor. When 1,
\r
873 the processor will ignore bus protocol error conditions
\r
877 #define PAL_BUS_DISABLE_INITIALIZATION_EVENT_CHECK BIT59
\r
883 When 0, BERR# is signalled if a bus error is detected. When 1,
\r
884 bus errors are not signalled on the bus.
\r
887 #define PAL_BUS_DISABLE_ERROR_SIGNALLING BIT58
\r
894 When 0, BERR# is signalled when internal processor requestor
\r
895 initiated bus errors are detected. When 1, internal requester
\r
896 bus errors are not signalled on the bus.
\r
899 #define PAL_BUS_DISABLE__INTERNAL_ERROR_SIGNALLING BIT57
\r
904 When 0, the processor takes an MCA if BERR# is asserted. When
\r
905 1, the processor ignores the BERR# signal.
\r
908 #define PAL_BUS_DISABLE_ERROR_CHECK BIT56
\r
913 When 0, the processor asserts BINIT# if it detects a parity
\r
914 error on the signals which identify the transactions to which
\r
915 this is a response. When 1, the processor ignores parity on
\r
919 #define PAL_BUS_DISABLE_RSP_ERROR_CHECK BIT55
\r
924 When 0, the in-order transaction queue is limited only by the
\r
925 number of hardware entries. When 1, the processor's in-order
\r
926 transactions queue is limited to one entry.
\r
929 #define PAL_BUS_DISABLE_TRANSACTION_QUEUE BIT54
\r
933 Enable a bus cache line replacement transaction when a cache
\r
934 line in the exclusive state is replaced from the highest level
\r
935 processor cache and is not present in the lower level processor
\r
936 caches. When 0, no bus cache line replacement transaction will
\r
937 be seen on the bus. When 1, bus cache line replacement
\r
938 transactions will be seen on the bus when the above condition is
\r
942 #define PAL_BUS_ENABLE_EXCLUSIVE_CACHE_LINE_REPLACEMENT BIT53
\r
947 Enable a bus cache line replacement transaction when a cache
\r
948 line in the shared or exclusive state is replaced from the
\r
949 highest level processor cache and is not present in the lower
\r
950 level processor caches.
\r
951 When 0, no bus cache line replacement transaction will be seen
\r
952 on the bus. When 1, bus cache line replacement transactions
\r
953 will be seen on the bus when the above condition is detected.
\r
956 #define PAL_BUS_ENABLE_SHARED_CACHE_LINE_REPLACEMENT BIT52
\r
962 When 0, the data bus is configured at the 2x data transfer
\r
963 rate.When 1, the data bus is configured at the 1x data
\r
964 transfer rate, 30 Opt. Req. Disable Bus Lock Mask. When 0, the
\r
965 processor executes locked transactions atomically. When 1, the
\r
966 processor masks the bus lock signal and executes locked
\r
967 transactions as a non-atomic series of transactions.
\r
970 #define PAL_BUS_ENABLE_HALF_TRANSFER BIT30
\r
974 When 0, the processor will deassert bus request when finished
\r
975 with each transaction. When 1, the processor will continue to
\r
976 assert bus request after it has finished, if it was the last
\r
977 agent to own the bus and if there are no other pending
\r
981 #define PAL_BUS_REQUEST_BUS_PARKING BIT29
\r
986 PAL Procedure - PAL_BUS_GET_FEATURES.
\r
988 Return configurable processor bus interface features and their
\r
989 current settings. It is required by IPF. The PAL procedure
\r
990 supports the Stacked Register calling convention. It could be
\r
991 called at physical mode.
\r
993 @param Index Index of PAL_BUS_GET_FEATURES within the list
\r
996 @return R9 64-bit vector of features implemented.
\r
997 (1=implemented, 0=not implemented)
\r
999 @return R10 64-bit vector of current feature settings.
\r
1001 @return R11 64-bit vector of features controllable by
\r
1002 software. (1=controllable, 0= not controllable)
\r
1004 @return Status 0 - Call completed without error
\r
1006 @return Status -2 - Invalid argument
\r
1008 @return Status -3 - Call completed with error.
\r
1011 #define PAL_BUS_GET_FEATURES 9
\r
1015 PAL Procedure - PAL_BUS_SET_FEATURES.
\r
1017 Enable or disable configurable features in processor bus
\r
1018 interface. It is required by IPF. It is required by IPF. The PAL procedure
\r
1019 supports the Static Registers calling convention. It could be
\r
1020 called at physical mode.
\r
1022 @param Index Index of PAL_BUS_SET_FEATURES within the list
\r
1023 of PAL procedures.
\r
1025 @param FeatureSelect 64-bit vector denoting desired state of
\r
1026 each feature (1=select, 0=non-select).
\r
1028 @return Status 0 - Call completed without error
\r
1030 @return Status -2 - Invalid argument
\r
1032 @return Status -3 - Call completed with error.
\r
1035 #define PAL_BUS_SET_FEATURES 10
\r
1040 PAL Procedure - PAL_DEBUG_INFO.
\r
1042 Return the number of instruction and data breakpoint
\r
1043 registers. It is required by IPF. It is required by IPF. The
\r
1044 PAL procedure supports the Static Registers calling
\r
1045 convention. It could be called at physical mode and virtual
\r
1048 @param Index Index of PAL_DEBUG_INFO within the list of PAL
\r
1051 @return R9 Unsigned 64-bit integer denoting the number of
\r
1052 pairs of instruction debug registers implemented
\r
1053 by the processor.
\r
1055 @return R10 Unsigned 64-bit integer denoting the number of
\r
1056 pairs of data debug registers implemented by the
\r
1059 @return Status 0 - Call completed without error
\r
1061 @return Status -2 - Invalid argument
\r
1063 @return Status -3 - Call completed with error.
\r
1066 #define PAL_DEBUG_INFO 11
\r
1070 PAL Procedure - PAL_FIXED_ADDR.
\r
1072 Return the fixed component of a processor¡¯s directed address.
\r
1073 It is required by IPF. It is required by IPF. The PAL
\r
1074 procedure supports the Static Registers calling convention. It
\r
1075 could be called at physical mode and virtual mode.
\r
1077 @param Index Index of PAL_FIXED_ADDR within the list of PAL
\r
1080 @return R9 Fixed geographical address of this processor.
\r
1083 @return Status 0 - Call completed without error
\r
1085 @return Status -2 - Invalid argument
\r
1087 @return Status -3 - Call completed with error.
\r
1090 #define PAL_FIXED_ADDR 12
\r
1094 PAL Procedure - PAL_FREQ_BASE.
\r
1096 Return the frequency of the output clock for use by the
\r
1097 platform, if generated by the processor. It is optinal. The
\r
1098 PAL procedure supports the Static Registers calling
\r
1099 convention. It could be called at physical mode and virtual
\r
1102 @param Index Index of PAL_FREQ_BASE within the list of PAL
\r
1105 @return R9 Base frequency of the platform if generated by the
\r
1109 @return Status 0 - Call completed without error
\r
1111 @return Status -1 - Unimplemented procedure
\r
1113 @return Status -2 - Invalid argument
\r
1115 @return Status -3 - Call completed with error.
\r
1118 #define PAL_FREQ_BASE 13
\r
1123 PAL Procedure - PAL_FREQ_RATIOS.
\r
1125 Return ratio of processor, bus, and interval time counter to
\r
1126 processor input clock or output clock for platform use, if
\r
1127 generated by the processor. It is required by IPF. The PAL
\r
1128 procedure supports the Static Registers calling convention. It
\r
1129 could be called at physical mode and virtual mode.
\r
1131 @param Index Index of PAL_FREQ_RATIOS within the list of PAL
\r
1134 @return R9 Ratio of the processor frequency to the input
\r
1135 clock of the processor, if the platform clock is
\r
1136 generated externally or to the output clock to the
\r
1137 platform, if the platform clock is generated by
\r
1140 @return R10 Ratio of the bus frequency to the input clock of
\r
1141 the processor, if the platform clock is generated
\r
1142 externally or to the output clock to the platform,
\r
1143 if the platform clock is generated by the
\r
1146 @return R11 Ratio of the interval timer counter rate to input
\r
1147 clock of the processor, if the platform clock is
\r
1148 generated externally or to the output clock to the
\r
1149 platform, if the platform clock is generated by
\r
1152 @return Status 0 - Call completed without error
\r
1154 @return Status -2 - Invalid argument
\r
1156 @return Status -3 - Call completed with error.
\r
1159 #define PAL_FREQ_RATIOS 14
\r
1163 @param NumberOfLogicalProcessors Total number of logical
\r
1164 processors on this physical
\r
1165 processor package that are
\r
1168 @param ThreadsPerCore Number of threads per core.
\r
1170 @param CoresPerProcessor Total number of cores on this
\r
1171 physical processor package.
\r
1173 @param PhysicalProcessorPackageId Physical processor package
\r
1174 identifier which was
\r
1175 assigned at reset by the
\r
1177 controller. This value may
\r
1178 or may not be unique
\r
1179 across the entire platform
\r
1180 since it depends on the
\r
1181 platform vendor's policy.
\r
1184 UINT64 NumberOfLogicalProcessors:16;
\r
1185 UINT64 ThreadsPerCore:8;
\r
1186 UINT64 Reserved1:8;
\r
1187 UINT64 CoresPerProcessor;
\r
1188 UINT64 Reserved2:8;
\r
1189 UINT64 PhysicalProcessorPackageId:8;
\r
1190 UINT64 Reserved3:8;
\r
1191 } PAL_LOGICAL_PROCESSPR_OVERVIEW;
\r
1195 @param ThreadId The thread identifier of the logical
\r
1196 processor for which information is being
\r
1197 returned. This value will be unique on a per
\r
1200 @param CoreId The core identifier of the logical processor
\r
1201 for which information is being returned.
\r
1202 This value will be unique on a per physical
\r
1203 processor package basis.
\r
1207 UINT64 ThreadId:16;
\r
1208 UINT64 Reserved1:16;
\r
1210 UINT64 Reserved2:16;
\r
1211 } PAL_LOGICAL_PROCESSORN_INFO1;
\r
1216 @param LogicalAddress Geographical address of the logical
\r
1217 processor for which information is being
\r
1218 returned. This is the same value that is
\r
1219 returned by the PAL_FIXED_ADDR procedure
\r
1220 when it is called on the logical
\r
1226 UINT64 LogicalAddress:16;
\r
1227 UINT64 Reserved:48;
\r
1228 } PAL_LOGICAL_PROCESSORN_INFO2;
\r
1232 PAL Procedure - PAL_LOGICAL_TO_PHYSICAL.
\r
1234 Return information on which logical processors map to a
\r
1235 physical processor die. It is optinal. The PAL procedure
\r
1236 supports the Static Registers calling convention. It could be
\r
1237 called at physical mode and virtual mode.
\r
1239 @param Index Index of PAL_LOGICAL_TO_PHYSICAL within the list of PAL
\r
1242 @param ProcessorNumber Signed 64-bit integer that specifies
\r
1243 for which logical processor
\r
1244 information is being requested. When
\r
1245 this input argument is -1, information
\r
1246 is returned about the logical
\r
1247 processor on which the procedure call
\r
1248 is made. This input argument must be
\r
1249 in the range of 1 up to one less than
\r
1250 the number of logical processors
\r
1251 returned by num_log in the
\r
1252 log_overview return value.
\r
1255 @return R9 The format of PAL_LOGICAL_PROCESSPR_OVERVIEW.
\r
1257 @return R10 The format of PAL_LOGICAL_PROCESSORN_INFO1.
\r
1259 @return R11 The format of PAL_LOGICAL_PROCESSORN_INFO2.
\r
1262 @return Status 0 - Call completed without error
\r
1264 @return Status -1 - Unimplemented procedure
\r
1266 @return Status -2 - Invalid argument
\r
1268 @return Status -3 - Call completed with error.
\r
1271 #define PAL_LOGICAL_TO_PHYSICAL 42
\r
1276 @param NumberOfPmcPairs Unsigned 8-bit number defining the
\r
1277 number of generic PMC/PMD pairs.
\r
1279 @param WidthOfCounter Unsigned 8-bit number in the range
\r
1280 0:60 defining the number of
\r
1281 implemented counter bits.
\r
1283 @param TypeOfCycleCounting Unsigned 8-bit number defining the
\r
1284 event type for counting processor
\r
1288 @param TypeOfRetiredInstructionBundle Retired Unsigned 8-bit
\r
1289 number defining the
\r
1290 event type for retired
\r
1291 instruction bundles.
\r
1295 UINT64 NumberOfPmcPairs:8;
\r
1296 UINT64 WidthOfCounter:8;
\r
1297 UINT64 TypeOfCycleCounting:8;
\r
1298 UINT64 TypeOfRetiredInstructionBundle:8;
\r
1299 UINT64 Reserved:32;
\r
1300 } PAL_PERFORMANCE_INFO;
\r
1304 PAL Procedure - PAL_PERF_MON_INFO.
\r
1306 Return the number and type of performance monitors. It is
\r
1307 required by IPF. The PAL procedure supports the Static
\r
1308 Registers calling convention. It could be called at physical
\r
1309 mode and virtual mode.
\r
1311 @param Index Index of PAL_PERF_MON_INFO within the list of
\r
1314 @param PerformanceBuffer An address to an 8-byte aligned
\r
1315 128-byte memory buffer.
\r
1318 @return R9 Information about the performance monitors
\r
1319 implemented. See PAL_PERFORMANCE_INFO;
\r
1321 @return Status 0 - Call completed without error
\r
1323 @return Status -2 - Invalid argument
\r
1325 @return Status -3 - Call completed with error.
\r
1328 #define PAL_PERF_MON_INFO 15
\r
1330 #define PAL_PLATFORM_ADDR_INTERRUPT_BLOCK_TOKEN 0x0
\r
1331 #define PAL_PLATFORM_ADDR_IO_BLOCK_TOKEN 0x1
\r
1335 PAL Procedure - PAL_PLATFORM_ADDR.
\r
1337 Specify processor interrupt block address and I/O port space
\r
1338 address. It is required by IPF. The PAL procedure supports the
\r
1339 Static Registers calling convention. It could be called at
\r
1340 physical mode and virtual mode.
\r
1342 @param Index Index of PAL_PLATFORM_ADDR within the list of
\r
1345 @param Type Unsigned 64-bit integer specifying the type of
\r
1346 block. 0 indicates that the processor interrupt
\r
1347 block pointer should be initialized. 1 indicates
\r
1348 that the processor I/O block pointer should be
\r
1351 @param Address Unsigned 64-bit integer specifying the address
\r
1352 to which the processor I/O block or interrupt
\r
1353 block shall be set. The address must specify
\r
1354 an implemented physical address on the
\r
1355 processor model, bit 63 is ignored.
\r
1358 @return Status 0 - Call completed without error
\r
1360 @return Status -1 - Unimplemented procedure.
\r
1362 @return Status -2 - Invalid argument
\r
1364 @return Status -3 - Call completed with error.
\r
1367 #define PAL_PLATFORM_ADDR 16
\r
1372 @param EnableBerrPromotion Bit63. Enable BERR promotion. When
\r
1373 1, the Bus Error (BERR) signal is
\r
1374 promoted to the Bus Initialization
\r
1375 (BINIT) signal, and the BINIT pin
\r
1376 is asserted on the occurrence of
\r
1377 each Bus Error. Setting this bit
\r
1378 has no effect if BINIT signalling
\r
1380 PAL_BUS_GET/SET_FEATURES)
\r
1382 @param EnableMcaPromotion Bit62, Enable MCA promotion. When
\r
1383 1, machine check aborts (MCAs) are
\r
1384 promoted to the Bus Error signal,
\r
1385 and the BERR pin is assert on each
\r
1386 occurrence of an MCA. Setting this
\r
1387 bit has no effect if BERR
\r
1388 signalling is disabled. (See
\r
1389 PAL_BUS_GET/SET_FEATURES)
\r
1391 @param EnableMcaToBinitPromotion Bit61, Enable MCA to BINIT
\r
1392 promotion. When 1, machine
\r
1393 check aborts (MCAs) are
\r
1394 promoted to the Bus
\r
1395 Initialization signal, and
\r
1396 the BINIT pin is assert on
\r
1397 each occurrence of an MCA.
\r
1398 Setting this bit has no
\r
1399 effect if BINIT signalling
\r
1401 PAL_BUS_GET/SET_FEATURES)
\r
1403 @param EnableCmciPromotion Bit60, Enable CMCI promotion When
\r
1404 1, Corrected Machine Check
\r
1405 Interrupts (CMCI) are promoted to
\r
1406 MCAs. They are also further
\r
1407 promoted to BERR if bit 39, Enable
\r
1408 MCA promotion, is also set and
\r
1409 they are promoted to BINIT if bit
\r
1410 38, Enable MCA to BINIT promotion,
\r
1411 is also set. This bit has no
\r
1412 effect if MCA signalling is
\r
1414 PAL_BUS_GET/SET_FEATURES)
\r
1416 @param DisableCache Bit59, Disable Cache. When 0, the
\r
1417 processor performs cast outs on
\r
1418 cacheable pages and issues and responds
\r
1419 to coherency requests normally. When 1,
\r
1420 the processor performs a memory access
\r
1421 for each reference regardless of cache
\r
1422 contents and issues no coherence
\r
1423 requests and responds as if the line
\r
1424 were not present. Cache contents cannot
\r
1425 be relied upon when the cache is
\r
1426 disabled. WARNING: Semaphore
\r
1427 instructions may not be atomic or may
\r
1428 cause Unsupported Data Reference faults
\r
1429 if caches are disabled.
\r
1431 @param DisableCoherency Bit58, Disable Coherency. When 0,
\r
1432 the processor uses normal coherency
\r
1433 requests and responses. When 1, the
\r
1434 processor answers all requests as if
\r
1435 the line were not present.
\r
1437 @param DisableDPM Bit57, Disable Dynamic Power Management
\r
1438 (DPM). When 0, the hardware may reduce
\r
1439 power consumption by removing the clock
\r
1440 input from idle functional units. When 1,
\r
1441 all functional units will receive clock
\r
1442 input, even when idle.
\r
1444 @param DisableBinitWithTimeout Bit56, Disable a BINIT on
\r
1445 internal processor time-out.
\r
1446 When 0, the processor may
\r
1447 generate a BINIT on an
\r
1448 internal processor time-out.
\r
1449 When 1, the processor will not
\r
1450 generate a BINIT on an
\r
1451 internal processor time-out.
\r
1452 The event is silently ignored.
\r
1455 @param EnableEnvNotification Bit55, Enable external
\r
1456 notification when the processor
\r
1457 detects hardware errors caused
\r
1458 by environmental factors that
\r
1459 could cause loss of
\r
1460 deterministic behavior of the
\r
1461 processor. When 1, this bit will
\r
1462 enable external notification,
\r
1463 when 0 external notification is
\r
1464 not provided. The type of
\r
1465 external notification of these
\r
1466 errors is processor-dependent. A
\r
1467 loss of processor deterministic
\r
1468 behavior is considered to have
\r
1470 environmentally induced errors
\r
1471 cause the processor to deviate
\r
1472 from its normal execution and
\r
1473 eventually causes different
\r
1474 behavior which can be observed
\r
1475 at the processor bus pins.
\r
1476 Processor errors that do not
\r
1477 have this effects (i.e.,
\r
1478 software induced machine checks)
\r
1479 may or may not be promoted
\r
1480 depending on the processor
\r
1483 @param EnableVmsw Bit54, Enable the use of the vmsw
\r
1484 instruction. When 0, the vmsw instruction
\r
1485 causes a Virtualization fault when
\r
1486 executed at the most privileged level.
\r
1487 When 1, this bit will enable normal
\r
1488 operation of the vmsw instruction.
\r
1490 @param EnableMcaOnDataPoisoning Bit53, Enable MCA signaling
\r
1491 on data-poisoning event
\r
1492 detection. When 0, a CMCI
\r
1493 will be signaled on error
\r
1494 detection. When 1, an MCA
\r
1495 will be signaled on error
\r
1496 detection. If this feature
\r
1497 is not supported, then the
\r
1498 corresponding argument is
\r
1499 ignored when calling
\r
1500 PAL_PROC_SET_FEATURES. Note
\r
1501 that the functionality of
\r
1502 this bit is independent of
\r
1503 the setting in bit 60
\r
1504 (Enable CMCI promotion), and
\r
1505 that the bit 60 setting does
\r
1506 not affect CMCI signaling
\r
1507 for data-poisoning related
\r
1508 events. Volume 2: Processor
\r
1509 Abstraction Layer 2:431
\r
1510 PAL_PROC_GET_FEATURES
\r
1512 @param DisablePState Bit52, Disable P-states. When 1, the PAL
\r
1513 P-state procedures (PAL_PSTATE_INFO,
\r
1514 PAL_SET_PSTATE, PAL_GET_PSTATE) will
\r
1515 return with a status of -1
\r
1516 (Unimplemented procedure).
\r
1518 @param DisableBranchPrediction Bit47, Disable Dynamic branch
\r
1519 prediction. When 0, the
\r
1520 processor may predict branch
\r
1521 targets and speculatively
\r
1522 execute, but may not commit
\r
1523 results. When 1, the processor
\r
1524 must wait until branch targets
\r
1525 are known to execute.
\r
1527 @param DisableDynamicInsCachePrefetch Bit46, Disable
\r
1528 DynamicInstruction Cache
\r
1529 Prefetch. When 0, the
\r
1530 processor may prefetch
\r
1531 into the caches any
\r
1532 instruction which has
\r
1533 not been executed, but
\r
1534 whose execution is
\r
1536 instructions may not be
\r
1537 fetched until needed or
\r
1538 hinted for execution.
\r
1539 (Prefetch for a hinted
\r
1540 branch is allowed even
\r
1541 when dynamic instruction
\r
1545 @param DisableDynamicDataCachePrefetch Bit45, Disable Dynamic
\r
1546 Data Cache Prefetch.
\r
1547 When 0, the processor
\r
1548 may prefetch into the
\r
1549 caches any data which
\r
1550 has not been accessed
\r
1552 execution, but which
\r
1554 accessed. When 1, no
\r
1555 data may be fetched
\r
1556 until it is needed for
\r
1557 instruction execution
\r
1558 or is fetched by an
\r
1559 lfetch instruction.
\r
1561 @param DisableSpontaneousDeferral Bit44, Disable Spontaneous
\r
1562 Deferral. When 1, the
\r
1563 processor may optionally
\r
1564 defer speculative loads
\r
1565 that do not encounter any
\r
1566 exception conditions, but
\r
1567 that trigger other
\r
1568 implementation-dependent
\r
1569 conditions (e.g., cache
\r
1570 miss). When 0, spontaneous
\r
1571 deferral is disabled.
\r
1573 @param DisableDynamicPrediction Bit43, Disable Dynamic
\r
1574 Predicate Prediction. When
\r
1575 0, the processor may predict
\r
1576 predicate results and
\r
1577 execute speculatively, but
\r
1578 may not commit results until
\r
1579 the actual predicates are
\r
1580 known. When 1, the processor
\r
1581 shall not execute predicated
\r
1582 instructions until the
\r
1583 actual predicates are known.
\r
1585 @param NoXr1ThroughXr3 Bit42, No XR1 through XR3 implemented.
\r
1586 Denotes whether XR1 XR3 are
\r
1587 implemented for machine check
\r
1588 recovery. This feature may only be
\r
1589 interrogated by PAL_PROC_GET_FEATURES.
\r
1590 It may not be enabled or disabled by
\r
1591 PAL_PROC_SET_FEATURES. The
\r
1592 corresponding argument is ignored.
\r
1594 @param NoXipXpsrXfs Bit41, No XIP, XPSR, and XFS
\r
1595 implemented. Denotes whether XIP, XPSR,
\r
1596 and XFS are implemented for machine
\r
1597 check recovery. This feature may only be
\r
1598 interrogated by PAL_PROC_GET_FEATURES.
\r
1599 It may not be enabled or disabled by
\r
1600 PAL_PROC_SET_FEATURES. The corresponding
\r
1601 argument is ignored.
\r
1603 @param NoVM Bit40, No Virtual Machine features implemented.
\r
1604 Denotes whether PSR.vm is implemented. This
\r
1605 feature may only be interrogated by
\r
1606 PAL_PROC_GET_FEATURES. It may not be enabled or
\r
1607 disabled by PAL_PROC_SET_FEATURES. The
\r
1608 corresponding argument is ignored.
\r
1610 @param NoVariablePState Bit39, No Variable P-state
\r
1611 performance: A value of 1, indicates
\r
1612 that a processor implements
\r
1613 techniques to optimize performance
\r
1614 for the given P-state power budget
\r
1615 by dynamically varying the
\r
1616 frequency, such that maximum
\r
1617 performance is achieved for the
\r
1618 power budget. A value of 0,
\r
1619 indicates that P-states have no
\r
1620 frequency variation or very small
\r
1621 frequency variations for their given
\r
1622 power budget. This feature may only
\r
1623 be interrogated by
\r
1624 PAL_PROC_GET_FEATURES. it may not be
\r
1625 enabled or disabled by
\r
1626 PAL_PROC_SET_FEATURES. The
\r
1627 corresponding argument is ignored.
\r
1630 @param NoSimpleImpInUndefinedIns Bit38, No Simple
\r
1632 unimplemented instruction
\r
1633 addresses. Denotes how an
\r
1634 unimplemented instruction
\r
1635 address is recorded in IIP
\r
1636 on an Unimplemented
\r
1637 Instruction Address trap or
\r
1638 fault. When 1, the full
\r
1639 unimplemented address is
\r
1640 recorded in IIP; when 0, the
\r
1641 address is sign extended
\r
1642 (virtual addresses) or zero
\r
1643 extended (physical
\r
1644 addresses). This feature may
\r
1645 only be interrogated by
\r
1646 PAL_PROC_GET_FEATURES. It
\r
1647 may not be enabled or
\r
1649 PAL_PROC_SET_FEATURES. The
\r
1650 corresponding argument is
\r
1653 @param NoPresentPmi Bit37, No INIT, PMI, and LINT pins
\r
1654 present. Denotes the absence of INIT,
\r
1655 PMI, LINT0 and LINT1 pins on the
\r
1656 processor. When 1, the pins are absent.
\r
1657 When 0, the pins are present. This
\r
1658 feature may only be interrogated by
\r
1659 PAL_PROC_GET_FEATURES. It may not be
\r
1660 enabled or disabled by
\r
1661 PAL_PROC_SET_FEATURES. The corresponding
\r
1662 argument is ignored.
\r
1664 @param FaultInUndefinedIns Bit36, No Unimplemented
\r
1665 instruction address reported as
\r
1666 fault. Denotes how the processor
\r
1667 reports the detection of
\r
1668 unimplemented instruction
\r
1669 addresses. When 1, the processor
\r
1670 reports an Unimplemented
\r
1671 Instruction Address fault on the
\r
1672 unimplemented address; when 0, it
\r
1673 reports an Unimplemented
\r
1674 Instruction Address trap on the
\r
1675 previous instruction in program
\r
1676 order. This feature may only be
\r
1678 PAL_PROC_GET_FEATURES. It may not
\r
1679 be enabled or disabled by
\r
1680 PAL_PROC_SET_FEATURES. The
\r
1681 corresponding argument is
\r
1686 UINT64 Reserved1:36;
\r
1687 UINT64 FaultInUndefinedIns:1;
\r
1688 UINT64 NoPresentPmi:1;
\r
1689 UINT64 NoSimpleImpInUndefinedIns:1;
\r
1690 UINT64 NoVariablePState:1;
\r
1692 UINT64 NoXipXpsrXfs:1;
\r
1693 UINT64 NoXr1ThroughXr3:1;
\r
1694 UINT64 DisableDynamicPrediction:1;
\r
1695 UINT64 DisableSpontaneousDeferral:1;
\r
1696 UINT64 DisableDynamicDataCachePrefetch:1;
\r
1697 UINT64 DisableDynamicInsCachePrefetch:1;
\r
1698 UINT64 DisableBranchPrediction:1;
\r
1699 UINT64 Reserved2:4;
\r
1700 UINT64 DisablePState:1;
\r
1701 UINT64 EnableMcaOnDataPoisoning:1;
\r
1702 UINT64 EnableVmsw:1;
\r
1703 UINT64 EnableEnvNotification:1;
\r
1704 UINT64 DisableBinitWithTimeout:1;
\r
1705 UINT64 DisableDPM:1;
\r
1706 UINT64 DisableCoherency:1;
\r
1707 UINT64 DisableCache:1;
\r
1708 UINT64 EnableCmciPromotion:1;
\r
1709 UINT64 EnableMcaToBinitPromotion:1;
\r
1710 UINT64 EnableMcaPromotion:1;
\r
1711 UINT64 EnableBerrPromotion:1;
\r
1712 } PAL_PROCESSOR_FEATURES;
\r
1716 PAL Procedure - PAL_PROC_GET_FEATURES.
\r
1718 Return configurable processor features and their current
\r
1719 setting. It is required by IPF. The PAL procedure supports the
\r
1720 Static Registers calling convention. It could be called at
\r
1721 physical mode and virtual mode.
\r
1723 @param Index Index of PAL_PROC_GET_FEATURES within the list of
\r
1726 @param Reserved Reserved parameter.
\r
1728 @param FeatureSet Feature set information is being requested
\r
1732 @return R9 64-bit vector of features implemented. See
\r
1733 PAL_PROCESSOR_FEATURES.
\r
1735 @return R10 64-bit vector of current feature settings. See
\r
1736 PAL_PROCESSOR_FEATURES.
\r
1738 @return R11 64-bit vector of features controllable by
\r
1741 @return Status 1 - Call completed without error; The
\r
1742 feature_set passed is not supported but a
\r
1743 feature_set of a larger value is supported.
\r
1745 @return Status 0 - Call completed without error
\r
1747 @return Status -2 - Invalid argument
\r
1749 @return Status -3 - Call completed with error.
\r
1751 @return Status -8 - feature_set passed is beyond the maximum
\r
1752 feature_set supported
\r
1755 #define PAL_PROC_GET_FEATURES 17
\r
1760 PAL Procedure - PAL_PROC_SET_FEATURES.
\r
1762 Enable or disable configurable processor features. It is
\r
1763 required by IPF. The PAL procedure supports the Static
\r
1764 Registers calling convention. It could be called at physical
\r
1767 @param Index Index of PAL_PROC_SET_FEATURES within the list of
\r
1770 @param FeatureSelect 64-bit vector denoting desired state of
\r
1771 each feature (1=select, 0=non-select).
\r
1773 @param FeatureSet Feature set to apply changes to. See
\r
1774 PAL_PROC_GET_FEATURES for more information
\r
1779 @return Status 1 - Call completed without error; The
\r
1780 feature_set passed is not supported but a
\r
1781 feature_set of a larger value is supported
\r
1783 @return Status 0 - Call completed without error
\r
1785 @return Status -2 - Invalid argument
\r
1787 @return Status -3 - Call completed with error.
\r
1789 @return Status -8 - feature_set passed is beyond the maximum
\r
1790 feature_set supported
\r
1793 #define PAL_PROC_SET_FEATURES 18
\r
1797 // Value of PAL_REGISTER_INFO.InfoRequest.
\r
1799 #define PAL_APPLICATION_REGISTER_IMPLEMENTED 0
\r
1800 #define PAL_APPLICATION_REGISTER_READABLE 1
\r
1801 #define PAL_CONTROL_REGISTER_IMPLEMENTED 2
\r
1802 #define PAL_CONTROL_REGISTER_READABLE 3
\r
1807 PAL Procedure - PAL_REGISTER_INFO.
\r
1809 Return AR and CR register information. It is required by IPF.
\r
1810 The PAL procedure supports the Static Registers calling
\r
1811 convention. It could be called at physical mode and virtual
\r
1814 @param Index Index of PAL_REGISTER_INFO within the list of
\r
1817 @param InfoRequest Unsigned 64-bit integer denoting what
\r
1818 register information is requested. See
\r
1819 PAL_REGISTER_INFO.InfoRequest above.
\r
1821 @return R9 64-bit vector denoting information for registers
\r
1822 0-63. Bit 0 is register 0, bit 63 is register 63.
\r
1824 @return R10 64-bit vector denoting information for registers
\r
1825 64-127. Bit 0 is register 64, bit 63 is register
\r
1829 @return Status 0 - Call completed without error
\r
1831 @return Status -2 - Invalid argument
\r
1833 @return Status -3 - Call completed with error.
\r
1837 #define PAL_REGISTER_INFO 39
\r
1841 PAL Procedure - PAL_RSE_INFO.
\r
1843 Return RSE information. It is required by IPF. The PAL
\r
1844 procedure supports the Static Registers calling convention. It
\r
1845 could be called at physical mode and virtual mode.
\r
1847 @param Index Index of PAL_RSE_INFO within the list of
\r
1850 @param InfoRequest Unsigned 64-bit integer denoting what
\r
1851 register information is requested. See
\r
1852 PAL_REGISTER_INFO.InfoRequest above.
\r
1854 @return R9 Number of physical stacked general registers.
\r
1856 @return R10 RSE hints supported by processor.
\r
1858 @return Status 0 - Call completed without error
\r
1860 @return Status -2 - Invalid argument
\r
1862 @return Status -3 - Call completed with error.
\r
1866 #define PAL_RSE_INFO 19
\r
1870 @param VersionOfPalB Is a 16-bit binary coded decimal (BCD)
\r
1871 number that provides identification
\r
1872 information about the PAL_B firmware.
\r
1874 @param PalVendor Is an unsigned 8-bit integer indicating the
\r
1875 vendor of the PAL code.
\r
1877 @param VersionOfPalB Is a 16-bit binary coded decimal (BCD)
\r
1878 number that provides identification
\r
1879 information about the PAL_A firmware. In
\r
1880 the split PAL_A model, this return value
\r
1881 is the version number of the
\r
1882 processor-specific PAL_A. The generic
\r
1883 PAL_A version is not returned by this
\r
1884 procedure in the split PAL_A model.
\r
1888 UINT64 VersionOfPalB:16;
\r
1889 UINT64 Reserved1:8;
\r
1890 UINT64 PalVendor:8;
\r
1891 UINT64 VersionOfPalA:16;
\r
1892 UINT64 Reserved2:16;
\r
1893 } PAL_VERSION_INFO;
\r
1897 PAL Procedure - PAL_VERSION.
\r
1899 Return version of PAL code. It is required by IPF. The PAL
\r
1900 procedure supports the Static Registers calling convention. It
\r
1901 could be called at physical mode and virtual mode.
\r
1903 @param Index Index of PAL_VERSION within the list of
\r
1906 @param InfoRequest Unsigned 64-bit integer denoting what
\r
1907 register information is requested. See
\r
1908 PAL_REGISTER_INFO.InfoRequest above.
\r
1910 @return R9 8-byte formatted value returning the minimum PAL
\r
1911 version needed for proper operation of the
\r
1912 processor. See PAL_VERSION_INFO above.
\r
1914 @return R10 8-byte formatted value returning the current PAL
\r
1915 version running on the processor. See
\r
1916 PAL_VERSION_INFO above.
\r
1918 @return Status 0 - Call completed without error
\r
1920 @return Status -2 - Invalid argument
\r
1922 @return Status -3 - Call completed with error.
\r
1926 #define PAL_VERSION 20
\r
1931 // Vectors of PAL_MC_CLEAR_LOG.pending
\r
1933 #define PAL_MC_PENDING BIT0
\r
1934 #define PAL_INIT_PENDING BIT1
\r
1938 PAL Procedure - PAL_MC_CLEAR_LOG.
\r
1940 Clear all error information from processor error logging
\r
1941 registers. It is required by IPF. The PAL procedure supports
\r
1942 the Static Registers calling convention. It could be called at
\r
1943 physical mode and virtual mode.
\r
1945 @param Index Index of PAL_MC_CLEAR_LOG within the list of
\r
1949 @return R9 64-bit vector denoting whether an event is
\r
1950 pending. See PAL_MC_CLEAR_LOG.pending above.
\r
1953 @return Status 0 - Call completed without error
\r
1955 @return Status -2 - Invalid argument
\r
1957 @return Status -3 - Call completed with error.
\r
1961 #define PAL_MC_CLEAR_LOG 21
\r
1965 PAL Procedure - PAL_MC_DRAIN.
\r
1967 Ensure that all operations that could cause an MCA have
\r
1968 completed. It is required by IPF. The PAL procedure supports
\r
1969 the Static Registers calling convention. It could be called at
\r
1970 physical mode and virtual mode.
\r
1972 @param Index Index of PAL_MC_DRAIN within the list of PAL
\r
1976 @return Status 0 - Call completed without error
\r
1978 @return Status -2 - Invalid argument
\r
1980 @return Status -3 - Call completed with error.
\r
1984 #define PAL_MC_DRAIN 22
\r
1989 PAL Procedure - PAL_MC_DYNAMIC_STATE.
\r
1991 Return Processor Dynamic State for logging by SAL. It is
\r
1992 optional. The PAL procedure supports the Static Registers
\r
1993 calling convention. It could be called at physical mode.
\r
1995 @param Index Index of PAL_MC_DYNAMIC_STATE within the list of PAL
\r
1998 @param Offset Offset of the next 8 bytes of Dynamic Processor
\r
1999 State to return. (multiple of 8).
\r
2001 @return R9 Unsigned 64-bit integer denoting bytes of Dynamic
\r
2002 Processor State returned.
\r
2004 @return R10 Next 8 bytes of Dynamic Processor State.
\r
2006 @return Status 0 - Call completed without error
\r
2008 @return Status -1 - Unimplemented procedure.
\r
2010 @return Status -2 - Invalid argument
\r
2012 @return Status -3 - Call completed with error.
\r
2016 #define PAL_MC_DYNAMIC_STATE 24
\r
2021 // Values of PAL_MC_ERROR_INFO.InfoIndex.
\r
2023 #define PAL_PROCESSOR_ERROR_MAP 0
\r
2024 #define PAL_PROCESSOR_STATE_PARAM 1
\r
2025 #define PAL_STRUCTURE_SPECIFIC_ERROR 2
\r
2029 @param CoreId Bit3:0, Processor core ID (default is 0 for
\r
2030 processors with a single core)
\r
2032 @param ThreadId Bit7:4, Logical thread ID (default is 0 for
\r
2033 processors that execute a single thread)
\r
2035 @param InfoOfInsCache Bit11:8, Error information is
\r
2036 available for 1st, 2nd, 3rd, and 4th
\r
2037 level instruction caches.
\r
2039 @param InfoOfDataCache Bit15:12, Error information is
\r
2040 available for 1st, 2nd, 3rd, and 4th
\r
2041 level data/unified caches.
\r
2043 @param InfoOfInsTlb Bit19:16 Error information is available
\r
2044 for 1st, 2nd, 3rd, and 4th level
\r
2047 @param InfoOfDataTlb Bit23:20, Error information is available
\r
2048 for 1st, 2nd, 3rd, and 4th level
\r
2051 @param InfoOfProcessorBus Bit27:24 Error information is
\r
2052 available for the 1st, 2nd, 3rd,
\r
2053 and 4th level processor bus
\r
2056 @param InfoOfRegisterFile Bit31:28 Error information is
\r
2057 available on register file
\r
2060 @param InfoOfMicroArch Bit47:32, Error information is
\r
2061 available on micro-architectural
\r
2067 UINT64 ThreadId:4;
\r
2068 UINT64 InfoOfInsCache:4;
\r
2069 UINT64 InfoOfDataCache:4;
\r
2070 UINT64 InfoOfInsTlb:4;
\r
2071 UINT64 InfoOfDataTlb:4;
\r
2072 UINT64 InfoOfProcessorBus:4;
\r
2073 UINT64 InfoOfRegisterFile:4;
\r
2074 UINT64 InfoOfMicroArch:4;
\r
2075 UINT64 Reserved:16;
\r
2076 } PAL_MC_ERROR_INFO_LEVEL_INDEX;
\r
2079 // Value of PAL_MC_ERROR_INFO.ErrorTypeIndex
\r
2081 #define PAL_ERR_INFO_BY_LEVEL_INDEX 0
\r
2082 #define PAL_ERR_INFO_TARGET_ADDRESS 1
\r
2083 #define PAL_ERR_INFO_REQUESTER_IDENTIFIER 2
\r
2084 #define PAL_ERR_INFO_REPONSER_INDENTIFIER 3
\r
2085 #define PAL_ERR_INFO_PRECISE_INSTRUCTION_POINTER 4
\r
2089 @param Operation Bit3:0, Type of cache operation that caused
\r
2090 the machine check: 0 - unknown or internal
\r
2091 error 1 - load 2 - store 3 - instruction
\r
2092 fetch or instruction prefetch 4 - data
\r
2093 prefetch (both hardware and software) 5 -
\r
2094 snoop (coherency check) 6 - cast out
\r
2095 (explicit or implicit write-back of a cache
\r
2096 line) 7 - move in (cache line fill)
\r
2098 @param FailedCacheLevel Bit5:4 Level of cache where the
\r
2099 error occurred. A value of 0
\r
2100 indicates the first level of cache.
\r
2102 @param FailedInDataPart Bit8, Failure located in the data
\r
2103 part of the cache line.
\r
2105 @param FailedInTagPart Bit9, Failure located in the tag part
\r
2106 of the cache line.
\r
2108 @param FailedInDataCache Bit10, Failure located in the data
\r
2111 @param FailedInInsCache Bit11, Failure located in the
\r
2112 instruction cache.
\r
2115 @param Mesi Bit14:12, 0 - cache line is invalid. 1 - cache
\r
2116 line is held shared. 2 - cache line is held
\r
2117 exclusive. 3 - cache line is modified. All other
\r
2118 values are reserved.
\r
2120 @param MesiIsValid Bit15, The mesi field in the cache_check
\r
2121 parameter is valid.
\r
2123 @param FailedWay Bit20:16, Failure located in the way of
\r
2124 the cache indicated by this value.
\r
2126 @param WayIndexIsValid Bit21, The way and index field in the
\r
2127 cache_check parameter is valid.
\r
2129 @param MultipleBitsError Bit23, A multiple-bit error was
\r
2130 detected, and data was poisoned for
\r
2131 the corresponding cache line during
\r
2134 @param IndexOfCacheLineError Bit51:32, Index of the cache
\r
2135 line where the error occurred.
\r
2137 @param InstructionSet Bit54, Instruction set. If this value
\r
2138 is set to zero, the instruction that
\r
2139 generated the machine check was an
\r
2140 Intel Itanium instruction. If this bit
\r
2141 is set to one, the instruction that
\r
2142 generated the machine check was IA-32
\r
2145 @param InstructionSetIsValid Bit55, The is field in the
\r
2146 cache_check parameter is valid.
\r
2148 @param PrivilegeLevel Bit57:56, Privilege level. The
\r
2149 privilege level of the instruction
\r
2150 bundle responsible for generating the
\r
2153 @param PrivilegeLevelIsValide Bit58, The pl field of the
\r
2154 cache_check parameter is
\r
2157 @param McCorrected Bit59, Machine check corrected: This bit
\r
2158 is set to one to indicate that the machine
\r
2159 check has been corrected.
\r
2161 @param TargetAddressIsValid Bit60, Target address is valid:
\r
2162 This bit is set to one to
\r
2163 indicate that a valid target
\r
2164 address has been logged.
\r
2166 @param RequesterIdentifier Bit61, Requester identifier: This
\r
2167 bit is set to one to indicate that
\r
2168 a valid requester identifier has
\r
2171 @param ResponserIdentifier Bit62, Responder identifier: This
\r
2172 bit is set to one to indicate that
\r
2173 a valid responder identifier has
\r
2176 @param PreciseInsPointer Bit63, Precise instruction pointer.
\r
2177 This bit is set to one to indicate
\r
2178 that a valid precise instruction
\r
2179 pointer has been logged.
\r
2183 UINT64 Operation:4;
\r
2184 UINT64 FailedCacheLevel:2;
\r
2185 UINT64 Reserved1:2;
\r
2186 UINT64 FailedInDataPart:1;
\r
2187 UINT64 FailedInTagPart:1;
\r
2188 UINT64 FailedInDataCache:1;
\r
2189 UINT64 FailedInInsCache:1;
\r
2191 UINT64 MesiIsValid:1;
\r
2192 UINT64 FailedWay:5;
\r
2193 UINT64 WayIndexIsValid:1;
\r
2195 UINT64 Reserved2:1;
\r
2196 UINT64 MultipleBitsError:1;
\r
2197 UINT64 Reserved3:8;
\r
2198 UINT64 IndexOfCacheLineError:20;
\r
2199 UINT64 Reserved4:2;
\r
2200 UINT64 InstructionSet:1;
\r
2201 UINT64 InstructionSetIsValid:1;
\r
2203 UINT64 PrivilegeLevel:2;
\r
2204 UINT64 PrivilegeLevelIsValide:1;
\r
2206 UINT64 McCorrected:1;
\r
2208 UINT64 TargetAddressIsValid:1;
\r
2209 UINT64 RequesterIdentifier:1;
\r
2210 UINT64 ResponserIdentifier:1;
\r
2211 UINT64 PreciseInsPointer:1;
\r
2213 } PAL_CACHE_CHECK_INFO;
\r
2217 @param FailedSlot Bit7:0, Slot number of the translation
\r
2218 register where the failure occurred.
\r
2220 @param FailedSlotIsValid Bit8, The tr_slot field in the
\r
2221 TLB_check parameter is valid.
\r
2223 @param TlbLevel Bit11:10, The level of the TLB where the
\r
2224 error occurred. A value of 0 indicates the
\r
2225 first level of TLB
\r
2227 @param FailedInDataTr Bit16, Error occurred in the data
\r
2228 translation registers.
\r
2230 @param FailedInInsTr Bit17, Error occurred in the instruction
\r
2231 translation registers
\r
2233 @param FailedInDataTc Bit18, Error occurred in data
\r
2234 translation cache.
\r
2236 @param FailedInInsTc Bit19, Error occurred in the instruction
\r
2237 translation cache.
\r
2239 @param FailedOperation Bit23:20, Type of cache operation that
\r
2240 caused the machine check: 0 - unknown
\r
2241 1 - TLB access due to load instruction
\r
2242 2 - TLB access due to store
\r
2243 instruction 3 - TLB access due to
\r
2244 instruction fetch or instruction
\r
2245 prefetch 4 - TLB access due to data
\r
2246 prefetch (both hardware and software)
\r
2247 5 - TLB shoot down access 6 - TLB
\r
2248 probe instruction (probe, tpa) 7 -
\r
2249 move in (VHPT fill) 8 - purge (insert
\r
2250 operation that purges entries or a TLB
\r
2251 purge instruction) All other values
\r
2254 @param InstructionSet Bit54, Instruction set. If this value
\r
2255 is set to zero, the instruction that
\r
2256 generated the machine check was an
\r
2257 Intel Itanium instruction. If this bit
\r
2258 is set to one, the instruction that
\r
2259 generated the machine check was IA-32
\r
2262 @param InstructionSetIsValid Bit55, The is field in the
\r
2263 TLB_check parameter is valid.
\r
2265 @param PrivelegeLevel Bit57:56, Privilege level. The
\r
2266 privilege level of the instruction
\r
2267 bundle responsible for generating the
\r
2270 @param PrivelegeLevelIsValid Bit58, The pl field of the
\r
2271 TLB_check parameter is valid.
\r
2273 @param McCorrected Bit59, Machine check corrected: This bit
\r
2274 is set to one to indicate that the machine
\r
2275 check has been corrected.
\r
2277 @param TargetAddressIsValid Bit60, Target address is valid:
\r
2278 This bit is set to one to
\r
2279 indicate that a valid target
\r
2280 address has been logged.
\r
2282 @param RequesterIdentifier Bit61 Requester identifier: This
\r
2283 bit is set to one to indicate that
\r
2284 a valid requester identifier has
\r
2287 @param ResponserIdentifier Bit62, Responder identifier: This
\r
2288 bit is set to one to indicate that
\r
2289 a valid responder identifier has
\r
2292 @param PreciseInsPointer Bit63 Precise instruction pointer.
\r
2293 This bit is set to one to indicate
\r
2294 that a valid precise instruction
\r
2295 pointer has been logged.
\r
2298 UINT64 FailedSlot:8;
\r
2299 UINT64 FailedSlotIsValid:1;
\r
2300 UINT64 Reserved1 :1;
\r
2301 UINT64 TlbLevel:2;
\r
2302 UINT64 Reserved2 :4;
\r
2303 UINT64 FailedInDataTr:1;
\r
2304 UINT64 FailedInInsTr:1;
\r
2305 UINT64 FailedInDataTc:1;
\r
2306 UINT64 FailedInInsTc:1;
\r
2307 UINT64 FailedOperation:4;
\r
2308 UINT64 Reserved3:30;
\r
2309 UINT64 InstructionSet:1;
\r
2310 UINT64 InstructionSetIsValid:1;
\r
2311 UINT64 PrivelegeLevel:2;
\r
2312 UINT64 PrivelegeLevelIsValid:1;
\r
2313 UINT64 McCorrected:1;
\r
2314 UINT64 TargetAddressIsValid:1;
\r
2315 UINT64 RequesterIdentifier:1;
\r
2316 UINT64 ResponserIdentifier:1;
\r
2317 UINT64 PreciseInsPointer:1;
\r
2318 } PAL_TLB_CHECK_INFO;
\r
2322 PAL Procedure - PAL_MC_ERROR_INFO.
\r
2324 Return Processor Machine Check Information and Processor
\r
2325 Static State for logging by SAL. It is required by IPF. The
\r
2326 PAL procedure supports the Static Registers calling
\r
2327 convention. It could be called at physical and virtual mode.
\r
2329 @param Index Index of PAL_MC_ERROR_INFO within the list of PAL
\r
2332 @param InfoIndex Unsigned 64-bit integer identifying the
\r
2333 error information that is being requested.
\r
2334 See PAL_MC_ERROR_INFO.InfoIndex.
\r
2336 @param LevelIndex 8-byte formatted value identifying the
\r
2337 structure to return error information
\r
2338 on. See PAL_MC_ERROR_INFO_LEVEL_INDEX.
\r
2340 @param ErrorTypeIndex Unsigned 64-bit integer denoting the
\r
2341 type of error information that is
\r
2342 being requested for the structure
\r
2343 identified in LevelIndex.
\r
2346 @return R9 Error information returned. The format of this
\r
2347 value is dependant on the input values passed.
\r
2349 @return R10 If this value is zero, all the error information
\r
2350 specified by err_type_index has been returned. If
\r
2351 this value is one, more structure-specific error
\r
2352 information is available and the caller needs to
\r
2353 make this procedure call again with level_index
\r
2354 unchanged and err_type_index, incremented.
\r
2357 @return Status 0 - Call completed without error
\r
2359 @return Status -2 - Invalid argument
\r
2361 @return Status -3 - Call completed with error.
\r
2363 @return Status -6 - Argument was valid, but no error
\r
2364 information was available
\r
2368 #define PAL_MC_ERROR_INFO 25
\r
2372 PAL Procedure - PAL_MC_EXPECTED.
\r
2374 Set/Reset Expected Machine Check Indicator. It is required by
\r
2375 IPF. The PAL procedure supports the Static Registers calling
\r
2376 convention. It could be called at physical mode.
\r
2378 @param Index Index of PAL_MC_EXPECTED within the list of PAL
\r
2381 @param Expected Unsigned integer with a value of 0 or 1 to
\r
2382 set or reset the hardware resource
\r
2383 PALE_CHECK examines for expected machine
\r
2387 @return R9 Unsigned integer denoting whether a machine check
\r
2388 was previously expected.
\r
2391 @return Status 0 - Call completed without error
\r
2393 @return Status -2 - Invalid argument
\r
2395 @return Status -3 - Call completed with error.
\r
2398 #define PAL_MC_EXPECTED 23
\r
2402 PAL Procedure - PAL_MC_REGISTER_MEM.
\r
2404 Register min-state save area with PAL for machine checks and
\r
2405 inits. It is required by IPF. The PAL procedure supports the
\r
2406 Static Registers calling convention. It could be called at
\r
2409 @param Index Index of PAL_MC_REGISTER_MEM within the list of PAL
\r
2412 @param Address Physical address of the buffer to be
\r
2413 registered with PAL.
\r
2417 @return Status 0 - Call completed without error
\r
2419 @return Status -2 - Invalid argument
\r
2421 @return Status -3 - Call completed with error.
\r
2424 #define PAL_MC_REGISTER_MEM 27
\r
2428 PAL Procedure - PAL_MC_RESUME.
\r
2430 Restore minimal architected state and return to interrupted
\r
2431 process. It is required by IPF. The PAL procedure supports the
\r
2432 Static Registers calling convention. It could be called at
\r
2435 @param Index Index of PAL_MC_RESUME within the list of PAL
\r
2438 @param SetCmci Unsigned 64 bit integer denoting whether to
\r
2439 set the CMC interrupt. A value of 0 indicates
\r
2440 not to set the interrupt, a value of 1
\r
2441 indicated to set the interrupt, and all other
\r
2442 values are reserved.
\r
2444 @param SavePtr Physical address of min-state save area used
\r
2445 to used to restore processor state.
\r
2447 @param NewContext Unsigned 64-bit integer denoting whether
\r
2448 the caller is returning to a new context.
\r
2449 A value of 0 indicates the caller is
\r
2450 returning to the interrupted context, a
\r
2451 value of 1 indicates that the caller is
\r
2452 returning to a new context.
\r
2456 @return Status -2 - Invalid argument
\r
2458 @return Status -3 - Call completed with error.
\r
2461 #define PAL_MC_RESUME 26
\r
2465 PAL Procedure - PAL_HALT.
\r
2467 Enter the low-power HALT state or an implementation-dependent
\r
2468 low-power state. It is optinal. The PAL procedure supports the
\r
2469 Static Registers calling convention. It could be called at
\r
2472 @param Index Index of PAL_HALT within the list of PAL
\r
2475 @param HaltState Unsigned 64-bit integer denoting low power
\r
2478 @param IoDetailPtr 8-byte aligned physical address pointer to
\r
2479 information on the type of I/O
\r
2480 (load/store) requested.
\r
2483 @return R9 Value returned if a load instruction is requested
\r
2484 in the io_detail_ptr
\r
2487 @return Status 0 - Call completed without error
\r
2489 @return Status -1 - Unimplemented procedure
\r
2491 @return Status -2 - Invalid argument
\r
2493 @return Status -3 - Call completed with error.
\r
2496 #define PAL_HALT 28
\r
2501 PAL Procedure - PAL_HALT_INFO.
\r
2503 Return the low power capabilities of the processor. It is
\r
2504 required by IPF. The PAL procedure supports the
\r
2505 Stacked Registers calling convention. It could be called at
\r
2506 physical and virtual mode.
\r
2508 @param Index Index of PAL_HALT_INFO within the list of PAL
\r
2511 @param PowerBuffer 64-bit pointer to a 64-byte buffer aligned
\r
2512 on an 8-byte boundary.
\r
2516 @return Status 0 - Call completed without error
\r
2518 @return Status -2 - Invalid argument
\r
2520 @return Status -3 - Call completed with error.
\r
2523 #define PAL_HALT_INFO 257
\r
2528 PAL Procedure - PAL_HALT_LIGHT.
\r
2530 Enter the low power LIGHT HALT state. It is required by
\r
2531 IPF. The PAL procedure supports the Static Registers calling
\r
2532 convention. It could be called at physical and virtual mode.
\r
2534 @param Index Index of PAL_HALT_LIGHT within the list of PAL
\r
2538 @return Status 0 - Call completed without error
\r
2540 @return Status -2 - Invalid argument
\r
2542 @return Status -3 - Call completed with error.
\r
2545 #define PAL_HALT_LIGHT 29
\r
2549 PAL Procedure - PAL_CACHE_LINE_INIT.
\r
2551 Initialize tags and data of a cache line for processor
\r
2552 testing. It is required by IPF. The PAL procedure supports the
\r
2553 Static Registers calling convention. It could be called at
\r
2554 physical and virtual mode.
\r
2556 @param Index Index of PAL_CACHE_LINE_INIT within the list of PAL
\r
2559 @param Address Unsigned 64-bit integer value denoting the
\r
2560 physical address from which the physical page
\r
2561 number is to be generated. The address must be
\r
2562 an implemented physical address, bit 63 must
\r
2565 @param DataValue 64-bit data value which is used to
\r
2566 initialize the cache line.
\r
2569 @return Status 0 - Call completed without error
\r
2571 @return Status -2 - Invalid argument
\r
2573 @return Status -3 - Call completed with error.
\r
2576 #define PAL_CACHE_LINE_INIT 31
\r
2580 PAL Procedure - PAL_CACHE_READ.
\r
2582 Read tag and data of a cache line for diagnostic testing. It
\r
2583 is optional. The PAL procedure supports the
\r
2584 Satcked Registers calling convention. It could be called at
\r
2587 @param Index Index of PAL_CACHE_READ within the list of PAL
\r
2590 @param LineId 8-byte formatted value describing where in the
\r
2591 cache to read the data.
\r
2593 @param Address 64-bit 8-byte aligned physical address from
\r
2594 which to read the data. The address must be an
\r
2595 implemented physical address on the processor
\r
2596 model with bit 63 set to zero.
\r
2598 @return R9 Right-justified value returned from the cache
\r
2601 @return R10 The number of bits returned in data.
\r
2603 @return R11 The status of the cache line.
\r
2607 @return Status 1 - The word at address was found in the
\r
2608 cache, but the line was invalid.
\r
2610 @return Status 0 - Call completed without error
\r
2612 @return Status -2 - Invalid argument
\r
2614 @return Status -3 - Call completed with error.
\r
2616 @return Status -5 - The word at address was not found in the
\r
2619 @return Status -7 - The operation requested is not supported
\r
2620 for this cache_type and level.
\r
2623 #define PAL_CACHE_READ 259
\r
2628 Write tag and data of a cache for diagnostic testing. It is
\r
2629 optional. The PAL procedure supports the Satcked Registers
\r
2630 calling convention. It could be called at physical mode.
\r
2632 @param Index Index of PAL_CACHE_WRITE within the list of PAL
\r
2635 @param LineId 8-byte formatted value describing where in the
\r
2636 cache to write the data.
\r
2638 @param Address 64-bit 8-byte aligned physical address at
\r
2639 which the data should be written. The address
\r
2640 must be an implemented physical address on the
\r
2641 processor model with bit 63 set to 0.
\r
2643 @param Data Unsigned 64-bit integer value to write into
\r
2644 the specified part of the cache.
\r
2647 @return Status 0 - Call completed without error
\r
2649 @return Status -2 - Invalid argument
\r
2651 @return Status -3 - Call completed with error.
\r
2654 @return Status -7 - The operation requested is not supported
\r
2655 for this cache_type and level.
\r
2658 #define PAL_CACHE_WRITE 260
\r
2662 PAL Procedure - PAL_TEST_INFO.
\r
2664 Returns alignment and size requirements needed for the memory
\r
2665 buffer passed to the PAL_TEST_PROC procedure as well as
\r
2666 information on self-test control words for the processor self
\r
2667 tests. It is required by IPF. The PAL procedure supports the
\r
2668 Static Registers calling convention. It could be called at
\r
2671 @param Index Index of PAL_TEST_INFO within the list of PAL
\r
2674 @param TestPhase Unsigned integer that specifies which phase
\r
2675 of the processor self-test information is
\r
2676 being requested on. A value of 0 indicates
\r
2677 the phase two of the processor self-test and
\r
2678 a value of 1 indicates phase one of the
\r
2679 processor self-test. All other values are
\r
2682 @return R9 Unsigned 64-bit integer denoting the number of
\r
2683 bytes of main memory needed to perform the second
\r
2684 phase of processor self-test.
\r
2686 @return R10 Unsigned 64-bit integer denoting the alignment
\r
2687 required for the memory buffer.
\r
2689 @return R11 48-bit wide bit-field indicating if control of
\r
2690 the processor self-tests is supported and which
\r
2691 bits of the test_control field are defined for
\r
2695 @return Status 0 - Call completed without error
\r
2697 @return Status -2 - Invalid argument
\r
2699 @return Status -3 - Call completed with error.
\r
2703 #define PAL_TEST_INFO 37
\r
2707 @param BufferSize Indicates the size in bytes of the memory
\r
2708 buffer that is passed to this procedure.
\r
2709 BufferSize must be greater than or equal in
\r
2710 size to the bytes_needed return value from
\r
2711 PAL_TEST_INFO, otherwise this procedure will
\r
2712 return with an invalid argument return
\r
2715 @param TestPhase Defines which phase of the processor
\r
2716 self-tests are requested to be run. A value
\r
2717 of zero indicates to run phase two of the
\r
2718 processor self-tests. Phase two of the
\r
2719 processor self-tests are ones that require
\r
2720 external memory to execute correctly. A
\r
2721 value of one indicates to run phase one of
\r
2722 the processor self-tests. Phase one of the
\r
2723 processor self-tests are tests run during
\r
2724 PALE_RESET and do not depend on external
\r
2725 memory to run correctly. When the caller
\r
2726 requests to have phase one of the processor
\r
2727 self-test run via this procedure call, a
\r
2728 memory buffer may be needed to save and
\r
2729 restore state as required by the PAL calling
\r
2730 conventions. The procedure PAL_TEST_INFO
\r
2731 informs the caller about the requirements of
\r
2732 the memory buffer.
\r
2736 UINT64 BufferSize:56;
\r
2737 UINT64 TestPhase:8;
\r
2738 } PAL_TEST_INFO_INFO;
\r
2742 @param TestControl This is an ordered implementation-specific
\r
2743 control word that allows the user control
\r
2744 over the length and runtime of the
\r
2745 processor self-tests. This control word is
\r
2746 ordered from the longest running tests up
\r
2747 to the shortest running tests with bit 0
\r
2748 controlling the longest running test. PAL
\r
2749 may not implement all 47-bits of the
\r
2750 test_control word. PAL communicates if a
\r
2751 bit provides control by placing a zero in
\r
2752 that bit. If a bit provides no control,
\r
2753 PAL will place a one in it. PAL will have
\r
2754 two sets of test_control bits for the two
\r
2755 phases of the processor self-test. PAL
\r
2756 provides information about implemented
\r
2757 test_control bits at the hand-off from PAL
\r
2758 to SAL for the firmware recovery check.
\r
2759 These test_control bits provide control
\r
2760 for phase one of processor self-test. It
\r
2761 also provides this information via the PAL
\r
2762 procedure call PAL_TEST_INFO for both the
\r
2763 phase one and phase two processor tests
\r
2764 depending on which information the caller
\r
2765 is requesting. PAL interprets these bits
\r
2766 as input parameters on two occasions. The
\r
2767 first time is when SAL passes control back
\r
2768 to PAL after the firmware recovery check.
\r
2769 The second time is when a call to
\r
2770 PAL_TEST_PROC is made. When PAL interprets
\r
2771 these bits it will only interpret
\r
2772 implemented test_control bits and will
\r
2773 ignore the values located in the
\r
2774 unimplemented test_control bits. PAL
\r
2775 interprets the implemented bits such that
\r
2776 if a bit contains a zero, this indicates
\r
2777 to run the test. If a bit contains a one,
\r
2778 this indicates to PAL to skip the test. If
\r
2779 the cs bit indicates that control is not
\r
2780 available, the test_control bits will be
\r
2781 ignored or generate an illegal argument in
\r
2782 procedure calls if the caller sets these
\r
2785 @param ControlSupport This bit defines if an implementation
\r
2786 supports control of the PAL self-tests
\r
2787 via the self-test control word. If
\r
2788 this bit is 0, the implementation does
\r
2789 not support control of the processor
\r
2790 self-tests via the self-test control
\r
2791 word. If this bit is 1, the
\r
2792 implementation does support control of
\r
2793 the processor self-tests via the
\r
2794 self-test control word. If control is
\r
2795 not supported, GR37 will be ignored at
\r
2796 the hand-off between SAL and PAL after
\r
2797 the firmware recovery check and the
\r
2798 PAL procedures related to the
\r
2799 processor self-tests may return
\r
2800 illegal arguments if a user tries to
\r
2801 use the self-test control features.
\r
2805 UINT64 TestControl:47;
\r
2806 UINT64 ControlSupport:1;
\r
2807 UINT64 Reserved:16;
\r
2808 } PAL_SELF_TEST_CONTROL;
\r
2812 @param Attributes Specifies the memory attributes that are
\r
2813 allowed to be used with the memory buffer
\r
2814 passed to this procedure. The attributes
\r
2815 parameter is a vector where each bit
\r
2816 represents one of the virtual memory
\r
2817 attributes defined by the architecture.See
\r
2818 MEMORY_AATRIBUTES. The caller is required
\r
2819 to support the cacheable attribute for the
\r
2820 memory buffer, otherwise an invalid
\r
2821 argument will be returned.
\r
2824 @param TestControl Is the self-test control word
\r
2825 corresponding to the test_phase passed.
\r
2826 This test_control directs the coverage and
\r
2827 runtime of the processor self-tests
\r
2828 specified by the test_phase input
\r
2829 argument. Information on if this
\r
2830 feature is implemented and the number of
\r
2831 bits supported can be obtained by the
\r
2832 PAL_TEST_INFO procedure call. If this
\r
2833 feature is implemented by the processor,
\r
2834 the caller can selectively skip parts of
\r
2835 the processor self-test by setting
\r
2836 test_control bits to a one. If a bit has a
\r
2837 zero, this test will be run. The values in
\r
2838 the unimplemented bits are ignored. If
\r
2839 PAL_TEST_INFO indicated that the self-test
\r
2840 control word is not implemented, this
\r
2841 procedure will return with an invalid
\r
2842 argument status if the caller sets any of
\r
2843 the test_control bits. See
\r
2844 PAL_SELF_TEST_CONTROL.
\r
2847 UINT64 Attributes:8;
\r
2848 UINT64 Reserved:8;
\r
2849 UINT64 TestControl:48;
\r
2850 } PAL_TEST_CONTROL;
\r
2854 PAL Procedure - PAL_TEST_PROC.
\r
2856 Perform late processor self test. It is required by IPF. The
\r
2857 PAL procedure supports the Static Registers calling
\r
2858 convention. It could be called at physical mode.
\r
2860 @param Index Index of PAL_TEST_PROC within the list of PAL
\r
2863 @param TestAddress 64-bit physical address of main memory
\r
2864 area to be used by processor self-test.
\r
2865 The memory region passed must be
\r
2866 cacheable, bit 63 must be zero.
\r
2868 @param TestInfo Input argument specifying the size of the
\r
2869 memory buffer passed and the phase of the
\r
2870 processor self-test that should be run. See
\r
2873 @param TestParam Input argument specifying the self-test
\r
2874 control word and the allowable memory
\r
2875 attributes that can be used with the memory
\r
2876 buffer. See PAL_TEST_CONTROL.
\r
2878 @return R9 Formatted 8-byte value denoting the state of the
\r
2879 processor after self-test
\r
2883 @return Status 1 - Call completed without error, but hardware
\r
2884 failures occurred during self-test.
\r
2886 @return Status 0 - Call completed without error
\r
2888 @return Status -2 - Invalid argument
\r
2890 @return Status -3 - Call completed with error.
\r
2894 #define PAL_TEST_PROC 258
\r
2898 @param NumberOfInterruptControllers Number of interrupt
\r
2899 controllers currently
\r
2900 enabled on the system.
\r
2902 @param NumberOfProcessors Number of processors currently
\r
2903 enabled on the system.
\r
2907 UINT32 NumberOfInterruptControllers;
\r
2908 UINT32 NumberOfProcessors;
\r
2909 } PAL_PLATFORM_INFO;
\r
2913 PAL Procedure - PAL_COPY_INFO.
\r
2915 Return information needed to relocate PAL procedures and PAL
\r
2916 PMI code to memory. It is required by IPF. The PAL procedure
\r
2917 supports the Static Registers calling convention. It could be
\r
2918 called at physical mode.
\r
2920 @param Index Index of PAL_COPY_INFO within the list of PAL
\r
2923 @param CopyType Unsigned integer denoting type of procedures
\r
2924 for which copy information is requested.
\r
2926 @param PlatformInfo 8-byte formatted value describing the
\r
2927 number of processors and the number of
\r
2928 interrupt controllers currently enabled
\r
2929 on the system. See PAL_PLATFORM_INFO.
\r
2932 @param McaProcStateInfo Unsigned integer denoting the number
\r
2933 of bytes that SAL needs for the
\r
2934 min-state save area for each
\r
2939 @return R9 Unsigned integer denoting the number of bytes of
\r
2940 PAL information that must be copied to main
\r
2943 @return R10 Unsigned integer denoting the starting alignment
\r
2944 of the data to be copied.
\r
2946 @return Status 0 - Call completed without error
\r
2948 @return Status -2 - Invalid argument
\r
2950 @return Status -3 - Call completed with error.
\r
2954 #define PAL_COPY_INFO 30
\r
2958 PAL Procedure - PAL_COPY_PAL.
\r
2960 Relocate PAL procedures and PAL PMI code to memory. It is
\r
2961 required by IPF. The PAL procedure supports the Stacked
\r
2962 Registers calling convention. It could be called at physical
\r
2965 @param Index Index of PAL_COPY_PAL within the list of PAL
\r
2968 @param TargetAddress Physical address of a memory buffer to
\r
2969 copy relocatable PAL procedures and PAL
\r
2972 @param AllocSize Unsigned integer denoting the size of the
\r
2973 buffer passed by SAL for the copy operation.
\r
2976 @param CopyOption Unsigned integer indicating whether
\r
2977 relocatable PAL code and PAL PMI code
\r
2978 should be copied from firmware address
\r
2979 space to main memory.
\r
2982 @return R9 Unsigned integer denoting the offset of PAL_PROC
\r
2983 in the relocatable segment copied.
\r
2985 @return Status 0 - Call completed without error
\r
2987 @return Status -2 - Invalid argument
\r
2989 @return Status -3 - Call completed with error.
\r
2993 #define PAL_COPY_PAL 256
\r
2997 PAL Procedure - PAL_ENTER_IA_32_ENV.
\r
2999 Enter IA-32 System environment. It is optional. The PAL
\r
3000 procedure supports the Static Registers calling convention.
\r
3001 It could be called at physical mode.
\r
3003 Note: Since this is a special call, it does not follow the PAL
\r
3004 static register calling convention. GR28 contains the index of
\r
3005 PAL_ENTER_IA_32_ENV within the list of PAL procedures. All other
\r
3006 input arguments including GR29-GR31 are setup by SAL to values
\r
3007 as required by the IA-32 operating system defined in Table
\r
3008 11-67. The registers that are designated as preserved, scratch,
\r
3009 input arguments and procedure return values by the static
\r
3010 procedure calling convention are not followed by this call. For
\r
3011 instance, GR5 and GR6 need not be preserved since these are
\r
3012 regarded as scratch by the IA-32 operating system. Note: In an
\r
3013 MP system, this call must be COMPLETED on the first CPU to enter
\r
3014 the IA-32 System Environment (may or may not be the BSP) prior
\r
3015 to being called on the remaining processors in the MP system.
\r
3017 @param Index GR28 contains the index of the
\r
3018 PAL_ENTER_IA_32_ENV call within the list of PAL
\r
3022 @return Status The status is returned in GR4.
\r
3023 -1 - Un-implemented procedure 0 JMPE detected
\r
3024 at privilege level
\r
3026 0 - 1 SAL allocated buffer for IA-32 System
\r
3027 Environment operation is too small
\r
3029 2 - IA-32 Firmware Checksum Error
\r
3031 3 - SAL allocated buffer for IA-32 System
\r
3032 Environment operation is not properly aligned
\r
3034 4 - Error in SAL MP Info Table
\r
3036 5 - Error in SAL Memory Descriptor Table
\r
3038 6 - Error in SAL System Table
\r
3040 7 - Inconsistent IA-32 state
\r
3042 8 - IA-32 Firmware Internal Error
\r
3044 9 - IA-32 Soft Reset (Note: remaining register
\r
3045 state is undefined for this termination
\r
3048 10 - Machine Check Error
\r
3050 11 - Error in SAL I/O Intercept Table
\r
3052 12 - Processor exit due to other processor in
\r
3053 MP system terminating the IA32 system
\r
3054 environment. (Note: remaining register state
\r
3055 is undefined for this termination reason.)
\r
3057 13 - Itanium architecture-based state
\r
3058 corruption by either SAL PMI handler or I/O
\r
3059 Intercept callback function.
\r
3063 #define PAL_ENTER_IA_32_ENV 33
\r
3067 PAL Procedure - PAL_PMI_ENTRYPOINT.
\r
3069 Register PMI memory entrypoints with processor. It is required
\r
3070 by IPF. The PAL procedure supports the Stacked Registers
\r
3071 calling convention. It could be called at physical mode.
\r
3073 @param Index Index of PAL_PMI_ENTRYPOINT within the list of
\r
3076 @param SalPmiEntry 256-byte aligned physical address of SAL
\r
3077 PMI entrypoint in memory.
\r
3080 @return Status 0 - Call completed without error
\r
3082 @return Status -2 - Invalid argument
\r
3084 @return Status -3 - Call completed with error.
\r
3088 #define PAL_PMI_ENTRYPOINT 32
\r
3093 The ASCII brand identification string will be copied to the
\r
3094 address specified in the address input argument. The processor
\r
3095 brand identification string is defined to be a maximum of 128
\r
3096 characters long; 127 bytes will contain characters and the 128th
\r
3097 byte is defined to be NULL (0). A processor may return less than
\r
3098 the 127 ASCII characters as long as the string is null
\r
3099 terminated. The string length will be placed in the brand_info
\r
3103 #define PAL_BRAND_INFO_ID_REQUEST 0
\r
3107 PAL Procedure - PAL_BRAND_INFO.
\r
3109 Provides processor branding information. It is optional by
\r
3110 IPF. The PAL procedure supports the Stacked Registers calling
\r
3111 convention. It could be called at physical and Virtual mode.
\r
3114 @param Index Index of PAL_BRAND_INFO within the list of PAL
\r
3117 @param InfoRequest Unsigned 64-bit integer specifying the
\r
3118 information that is being requested. (See
\r
3119 PAL_BRAND_INFO_ID_REQUEST)
\r
3121 @param Address Unsigned 64-bit integer specifying the
\r
3122 address of the 128-byte block to which the
\r
3123 processor brand string shall be written.
\r
3126 @reture R9 Brand information returned. The format of this
\r
3127 value is dependent on the input values passed.
\r
3130 @return Status 0 - Call completed without error
\r
3132 @return Status -1 - Unimplemented procedure
\r
3134 @return Status -2 - Invalid argument
\r
3136 @return Status -3 - Call completed with error.
\r
3138 @return Status -6 - Input argument is not implemented.
\r
3141 #define PAL_BRAND_INFO 274
\r
3145 PAL Procedure - PAL_GET_HW_POLICY.
\r
3147 Returns the current hardware resource sharing policy of the
\r
3148 processor. It is optional by IPF. The PAL procedure supports
\r
3149 the Static Registers calling convention. It could be called at
\r
3150 physical and Virtual mode.
\r
3153 @param Index Index of PAL_GET_HW_POLICY within the list of PAL
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