Correct symbol violations reported by "make symcheck"
[people/lynusvaz/gpxe.git] / src / drivers / net / tg3.c
1 /* $Id$
2  * tg3.c: Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001, 2002 Jeff Garzik (jgarzik@mandrakesoft.com)
6  * Copyright (C) 2003 Eric Biederman (ebiederman@lnxi.com)  [etherboot port]
7  */
8
9 /* 11-13-2003   timlegge        Fix Issue with NetGear GA302T 
10  * 11-18-2003   ebiederm        Generalize NetGear Fix to what the code was supposed to be.
11  * 01-06-2005   Alf (Frederic Olivie) Add Dell bcm 5751 (0x1677) support
12  */
13
14 #include "etherboot.h"
15 #include "nic.h"
16 #include "pci.h"
17 #include "timer.h"
18 #include "string.h"
19 #include "shared.h"
20 #include "tg3.h"
21
22 #define SUPPORT_COPPER_PHY  1
23 #define SUPPORT_FIBER_PHY   1
24 #define SUPPORT_LINK_REPORT 1
25 #define SUPPORT_PARTNO_STR  1
26 #define SUPPORT_PHY_STR     1
27
28 static struct tg3 tg3;
29
30 /* Dummy defines for error handling */
31 #define EBUSY  1
32 #define ENODEV 2
33 #define EINVAL 3
34 #define ENOMEM 4
35
36
37 /* These numbers seem to be hard coded in the NIC firmware somehow.
38  * You can't change the ring sizes, but you can change where you place
39  * them in the NIC onboard memory.
40  */
41 #define TG3_RX_RING_SIZE                512
42 #define TG3_DEF_RX_RING_PENDING         20      /* RX_RING_PENDING seems to be o.k. at 20 and 200 */
43 #define TG3_RX_RCB_RING_SIZE    1024
44
45 /*      (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ? \
46          512 : 1024) */
47 #define TG3_TX_RING_SIZE                512
48 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
49
50 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_RING_SIZE)
51 #define TG3_RX_RCB_RING_BYTES   (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_RCB_RING_SIZE)
52
53 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * TG3_TX_RING_SIZE)
54 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
55 #define PREV_TX(N)              (((N) - 1) & (TG3_TX_RING_SIZE - 1))
56
57 #define RX_PKT_BUF_SZ           (1536 + 2 + 64)
58
59 struct eth_frame {
60         uint8_t  dst_addr[ETH_ALEN];
61         uint8_t  src_addr[ETH_ALEN];
62         uint16_t type;
63         uint8_t  data [ETH_FRAME_LEN - ETH_HLEN];
64 };
65
66 struct bss {
67         struct tg3_rx_buffer_desc rx_std[TG3_RX_RING_SIZE];
68         struct tg3_rx_buffer_desc rx_rcb[TG3_RX_RCB_RING_SIZE];
69         struct tg3_tx_buffer_desc tx_ring[TG3_TX_RING_SIZE];
70         struct tg3_hw_status      hw_status;
71         struct tg3_hw_stats       hw_stats;
72         unsigned char             rx_bufs[TG3_DEF_RX_RING_PENDING][RX_PKT_BUF_SZ];
73         struct eth_frame          tx_frame[2];
74 } tg3_bss __shared;
75
76 /**
77  * pci_save_state - save the PCI configuration space of a device before suspending
78  * @dev: - PCI device that we're dealing with
79  * @buffer: - buffer to hold config space context
80  *
81  * @buffer must be large enough to hold the entire PCI 2.2 config space 
82  * (>= 64 bytes).
83  */
84 static int pci_save_state(struct pci_device *dev, uint32_t *buffer)
85 {
86         int i;
87         for (i = 0; i < 16; i++)
88                 pci_read_config_dword(dev, i * 4,&buffer[i]);
89         return 0;
90 }
91
92 /** 
93  * pci_restore_state - Restore the saved state of a PCI device
94  * @dev: - PCI device that we're dealing with
95  * @buffer: - saved PCI config space
96  *
97  */
98 static int pci_restore_state(struct pci_device *dev, uint32_t *buffer)
99 {
100         int i;
101
102         for (i = 0; i < 16; i++)
103                 pci_write_config_dword(dev,i * 4, buffer[i]);
104         return 0;
105 }
106
107 static void tg3_write_indirect_reg32(uint32_t off, uint32_t val)
108 {
109         pci_write_config_dword(tg3.pdev, TG3PCI_REG_BASE_ADDR, off);
110         pci_write_config_dword(tg3.pdev, TG3PCI_REG_DATA, val);
111 }
112
113 #define tw32(reg,val)           tg3_write_indirect_reg32((reg),(val))
114 #define tw32_mailbox(reg, val)  writel(((val) & 0xffffffff), tg3.regs + (reg))
115 #define tw16(reg,val)           writew(((val) & 0xffff), tg3.regs + (reg))
116 #define tw8(reg,val)            writeb(((val) & 0xff), tg3.regs + (reg))
117 #define tr32(reg)               readl(tg3.regs + (reg))
118 #define tr16(reg)               readw(tg3.regs + (reg))
119 #define tr8(reg)                readb(tg3.regs + (reg))
120
121 static void tw32_carefully(uint32_t reg, uint32_t val)
122 {
123         tw32(reg, val);
124         tr32(reg);
125         udelay(100);
126 }
127
128 static void tw32_mailbox2(uint32_t reg, uint32_t val)
129 {
130         tw32_mailbox(reg, val);
131         tr32(reg);
132 }
133
134 static void tg3_write_mem(uint32_t off, uint32_t val)
135 {
136         pci_write_config_dword(tg3.pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
137         pci_write_config_dword(tg3.pdev, TG3PCI_MEM_WIN_DATA, val);
138
139         /* Always leave this as zero. */
140         pci_write_config_dword(tg3.pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
141 }
142
143 static void tg3_read_mem(uint32_t off, uint32_t *val)
144 {
145         pci_write_config_dword(tg3.pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
146         pci_read_config_dword(tg3.pdev, TG3PCI_MEM_WIN_DATA, val);
147
148         /* Always leave this as zero. */
149         pci_write_config_dword(tg3.pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
150 }
151
152 static void tg3_disable_ints(struct tg3 *tp)
153 {
154         tw32(TG3PCI_MISC_HOST_CTRL,
155              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
156         tw32_mailbox2(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
157 }
158
159 static void tg3_switch_clocks(struct tg3 *tp)
160 {
161         uint32_t orig_clock_ctrl, clock_ctrl;
162
163         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
164
165         orig_clock_ctrl = clock_ctrl;
166         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN | CLOCK_CTRL_CLKRUN_OENABLE | 0x1f);
167         tp->pci_clock_ctrl = clock_ctrl;
168         
169         if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) &&
170             (!((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
171                && (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) &&
172                 (orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE)!=0) {
173                 tw32_carefully(TG3PCI_CLOCK_CTRL, 
174                         clock_ctrl | (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK));
175                 tw32_carefully(TG3PCI_CLOCK_CTRL, 
176                         clock_ctrl | (CLOCK_CTRL_ALTCLK));
177         }
178         tw32_carefully(TG3PCI_CLOCK_CTRL, clock_ctrl);
179 }
180
181 #define PHY_BUSY_LOOPS  5000
182
183 static int tg3_readphy(struct tg3 *tp, int reg, uint32_t *val)
184 {
185         uint32_t frame_val;
186         int loops, ret;
187
188         tw32_carefully(MAC_MI_MODE, tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL);
189
190         *val = 0xffffffff;
191
192         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
193                       MI_COM_PHY_ADDR_MASK);
194         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
195                       MI_COM_REG_ADDR_MASK);
196         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
197         
198         tw32_carefully(MAC_MI_COM, frame_val);
199
200         loops = PHY_BUSY_LOOPS;
201         while (loops-- > 0) {
202                 udelay(10);
203                 frame_val = tr32(MAC_MI_COM);
204
205                 if ((frame_val & MI_COM_BUSY) == 0) {
206                         udelay(5);
207                         frame_val = tr32(MAC_MI_COM);
208                         break;
209                 }
210         }
211
212         ret = -EBUSY;
213         if (loops > 0) {
214                 *val = frame_val & MI_COM_DATA_MASK;
215                 ret = 0;
216         }
217
218         tw32_carefully(MAC_MI_MODE, tp->mi_mode);
219
220         return ret;
221 }
222
223 static int tg3_writephy(struct tg3 *tp, int reg, uint32_t val)
224 {
225         uint32_t frame_val;
226         int loops, ret;
227
228         tw32_carefully(MAC_MI_MODE, tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL);
229
230         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
231                       MI_COM_PHY_ADDR_MASK);
232         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
233                       MI_COM_REG_ADDR_MASK);
234         frame_val |= (val & MI_COM_DATA_MASK);
235         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
236         
237         tw32_carefully(MAC_MI_COM, frame_val);
238
239         loops = PHY_BUSY_LOOPS;
240         while (loops-- > 0) {
241                 udelay(10);
242                 frame_val = tr32(MAC_MI_COM);
243                 if ((frame_val & MI_COM_BUSY) == 0) {
244                         udelay(5);
245                         frame_val = tr32(MAC_MI_COM);
246                         break;
247                 }
248         }
249
250         ret = -EBUSY;
251         if (loops > 0)
252                 ret = 0;
253
254         tw32_carefully(MAC_MI_MODE, tp->mi_mode);
255
256         return ret;
257 }
258
259 static int tg3_writedsp(struct tg3 *tp, uint16_t addr, uint16_t val)
260 {
261         int err;
262         err  = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, addr);
263         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
264         return err;
265 }
266
267
268 static void tg3_phy_set_wirespeed(struct tg3 *tp)
269 {
270         uint32_t val;
271
272         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
273                 return;
274
275         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007);
276         tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
277         tg3_writephy(tp, MII_TG3_AUX_CTRL, (val | (1 << 15) | (1 << 4)));
278 }
279
280 static int tg3_bmcr_reset(struct tg3 *tp)
281 {
282         uint32_t phy_control;
283         int limit, err;
284
285         /* OK, reset it, and poll the BMCR_RESET bit until it
286          * clears or we time out.
287          */
288         phy_control = BMCR_RESET;
289         err = tg3_writephy(tp, MII_BMCR, phy_control);
290         if (err != 0)
291                 return -EBUSY;
292
293         limit = 5000;
294         while (limit--) {
295                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
296                 if (err != 0)
297                         return -EBUSY;
298
299                 if ((phy_control & BMCR_RESET) == 0) {
300                         udelay(40);
301                         break;
302                 }
303                 udelay(10);
304         }
305         if (limit <= 0)
306                 return -EBUSY;
307
308         return 0;
309 }
310
311 static int tg3_wait_macro_done(struct tg3 *tp)
312 {
313         int limit = 100;
314
315         while (limit--) {
316                 uint32_t tmp32;
317
318                 tg3_readphy(tp, 0x16, &tmp32);
319                 if ((tmp32 & 0x1000) == 0)
320                         break;
321         }
322         if (limit <= 0)
323                 return -EBUSY;
324
325         return 0;
326 }
327
328 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
329 {
330         static const uint32_t test_pat[4][6] = {
331         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
332         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
333         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
334         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
335         };
336         int chan;
337
338         for (chan = 0; chan < 4; chan++) {
339                 int i;
340
341                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
342                         (chan * 0x2000) | 0x0200);
343                 tg3_writephy(tp, 0x16, 0x0002);
344
345                 for (i = 0; i < 6; i++)
346                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
347                                 test_pat[chan][i]);
348
349                 tg3_writephy(tp, 0x16, 0x0202);
350                 if (tg3_wait_macro_done(tp)) {
351                         *resetp = 1;
352                         return -EBUSY;
353                 }
354
355                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
356                              (chan * 0x2000) | 0x0200);
357                 tg3_writephy(tp, 0x16, 0x0082);
358                 if (tg3_wait_macro_done(tp)) {
359                         *resetp = 1;
360                         return -EBUSY;
361                 }
362
363                 tg3_writephy(tp, 0x16, 0x0802);
364                 if (tg3_wait_macro_done(tp)) {
365                         *resetp = 1;
366                         return -EBUSY;
367                 }
368
369                 for (i = 0; i < 6; i += 2) {
370                         uint32_t low, high;
371
372                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low);
373                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high);
374                         if (tg3_wait_macro_done(tp)) {
375                                 *resetp = 1;
376                                 return -EBUSY;
377                         }
378                         low &= 0x7fff;
379                         high &= 0x000f;
380                         if (low != test_pat[chan][i] ||
381                             high != test_pat[chan][i+1]) {
382                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
383                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
384                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
385
386                                 return -EBUSY;
387                         }
388                 }
389         }
390
391         return 0;
392 }
393
394 static int tg3_phy_reset_chanpat(struct tg3 *tp)
395 {
396         int chan;
397
398         for (chan = 0; chan < 4; chan++) {
399                 int i;
400
401                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
402                              (chan * 0x2000) | 0x0200);
403                 tg3_writephy(tp, 0x16, 0x0002);
404                 for (i = 0; i < 6; i++)
405                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
406                 tg3_writephy(tp, 0x16, 0x0202);
407                 if (tg3_wait_macro_done(tp))
408                         return -EBUSY;
409         }
410
411         return 0;
412 }
413
414 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
415 {
416         uint32_t reg32, phy9_orig;
417         int retries, do_phy_reset, err;
418
419         retries = 10;
420         do_phy_reset = 1;
421         do {
422                 if (do_phy_reset) {
423                         err = tg3_bmcr_reset(tp);
424                         if (err)
425                                 return err;
426                         do_phy_reset = 0;
427                 }
428                 
429                 /* Disable transmitter and interrupt.  */
430                 tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32);
431                 reg32 |= 0x3000;
432                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
433
434                 /* Set full-duplex, 1000 mbps.  */
435                 tg3_writephy(tp, MII_BMCR,
436                         BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
437
438                 /* Set to master mode.  */
439                 tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig);
440                 tg3_writephy(tp, MII_TG3_CTRL,
441                         (MII_TG3_CTRL_AS_MASTER |
442                                 MII_TG3_CTRL_ENABLE_AS_MASTER));
443
444                 /* Enable SM_DSP_CLOCK and 6dB.  */
445                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
446
447                 /* Block the PHY control access.  */
448                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
449                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
450
451                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
452                 if (!err)
453                         break;
454         } while (--retries);
455
456         err = tg3_phy_reset_chanpat(tp);
457         if (err)
458                 return err;
459
460         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
461         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
462
463         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
464         tg3_writephy(tp, 0x16, 0x0000);
465
466         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
467
468         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
469
470         tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32);
471         reg32 &= ~0x3000;
472         tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
473
474         return err;
475 }
476
477 /* This will reset the tigon3 PHY if there is no valid
478  * link.
479  */
480 static int tg3_phy_reset(struct tg3 *tp)
481 {
482         uint32_t phy_status;
483         int err;
484
485         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
486         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
487         if (err != 0)
488                 return -EBUSY;
489
490         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) ||
491                 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
492                 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
493                 err = tg3_phy_reset_5703_4_5(tp);
494                 if (err)
495                         return err;
496                 goto out;
497         }
498         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
499           // Taken from Broadcom's source code
500           tg3_writephy(tp, 0x18, 0x0c00);
501           tg3_writephy(tp, 0x17, 0x000a);
502           tg3_writephy(tp, 0x15, 0x310b);
503           tg3_writephy(tp, 0x17, 0x201f);
504           tg3_writephy(tp, 0x15, 0x9506);
505           tg3_writephy(tp, 0x17, 0x401f);
506           tg3_writephy(tp, 0x15, 0x14e2);
507           tg3_writephy(tp, 0x18, 0x0400);
508         }
509         err = tg3_bmcr_reset(tp);
510         if (err)
511                 return err;
512  out:
513         tg3_phy_set_wirespeed(tp);
514         return 0;
515 }
516
517 static void tg3_set_power_state_0(struct tg3 *tp)
518 {
519         uint16_t power_control;
520         int pm = tp->pm_cap;
521
522         /* Make sure register accesses (indirect or otherwise)
523          * will function correctly.
524          */
525         pci_write_config_dword(tp->pdev,  TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
526
527         pci_read_config_word(tp->pdev, pm + PCI_PM_CTRL, &power_control);
528
529         power_control |= PCI_PM_CTRL_PME_STATUS;
530         power_control &= ~(PCI_PM_CTRL_STATE_MASK);
531         power_control |= 0;
532         pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
533
534         tw32_carefully(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
535
536         return;
537 }
538
539
540 #if SUPPORT_LINK_REPORT
541 static void tg3_link_report(struct tg3 *tp)
542 {
543         if (!tp->carrier_ok) {
544                 printf("Link is down.\n");
545         } else {
546                 printf("Link is up at %d Mbps, %s duplex. %s %s %s\n",
547                         (tp->link_config.active_speed == SPEED_1000 ?
548                                1000 :
549                         (tp->link_config.active_speed == SPEED_100 ?
550                                 100 : 10)),
551                         (tp->link_config.active_duplex == DUPLEX_FULL ?  
552                                 "full" : "half"),
553                         (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "TX" : "",
554                         (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "RX" : "",
555                         (tp->tg3_flags & (TG3_FLAG_TX_PAUSE |TG3_FLAG_RX_PAUSE)) ? "flow control" : "");
556         }
557 }
558 #else
559 #define tg3_link_report(tp)
560 #endif
561
562 static void tg3_setup_flow_control(struct tg3 *tp, uint32_t local_adv, uint32_t remote_adv)
563 {
564         uint32_t new_tg3_flags = 0;
565
566         if (local_adv & ADVERTISE_PAUSE_CAP) {
567                 if (local_adv & ADVERTISE_PAUSE_ASYM) {
568                         if (remote_adv & LPA_PAUSE_CAP)
569                                 new_tg3_flags |=
570                                         (TG3_FLAG_RX_PAUSE |
571                                          TG3_FLAG_TX_PAUSE);
572                         else if (remote_adv & LPA_PAUSE_ASYM)
573                                 new_tg3_flags |=
574                                         (TG3_FLAG_RX_PAUSE);
575                 } else {
576                         if (remote_adv & LPA_PAUSE_CAP)
577                                 new_tg3_flags |=
578                                         (TG3_FLAG_RX_PAUSE |
579                                          TG3_FLAG_TX_PAUSE);
580                 }
581         } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
582                 if ((remote_adv & LPA_PAUSE_CAP) &&
583                     (remote_adv & LPA_PAUSE_ASYM))
584                         new_tg3_flags |= TG3_FLAG_TX_PAUSE;
585         }
586
587         tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
588         tp->tg3_flags |= new_tg3_flags;
589
590         if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
591                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
592         else
593                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
594
595         if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
596                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
597         else
598                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
599 }
600
601 #if SUPPORT_COPPER_PHY
602 static void tg3_aux_stat_to_speed_duplex(
603         struct tg3 *tp __unused, uint32_t val, uint8_t *speed, uint8_t *duplex)
604 {
605         static const uint8_t map[] = {
606                 [0] = (SPEED_INVALID << 2) | DUPLEX_INVALID,
607                 [MII_TG3_AUX_STAT_10HALF >> 8]   = (SPEED_10 << 2) | DUPLEX_HALF,
608                 [MII_TG3_AUX_STAT_10FULL >> 8]   = (SPEED_10 << 2) | DUPLEX_FULL,
609                 [MII_TG3_AUX_STAT_100HALF >> 8]  = (SPEED_100 << 2) | DUPLEX_HALF,
610                 [MII_TG3_AUX_STAT_100_4 >> 8] = (SPEED_INVALID << 2) | DUPLEX_INVALID,
611                 [MII_TG3_AUX_STAT_100FULL >> 8]  = (SPEED_100 << 2) | DUPLEX_FULL,
612                 [MII_TG3_AUX_STAT_1000HALF >> 8] = (SPEED_1000 << 2) | DUPLEX_HALF,
613                 [MII_TG3_AUX_STAT_1000FULL >> 8] = (SPEED_1000 << 2) | DUPLEX_FULL,
614         };
615         uint8_t result;
616         result = map[(val & MII_TG3_AUX_STAT_SPDMASK) >> 8];
617         *speed = result >> 2;
618         *duplex = result & 3;
619 }
620
621 static int tg3_phy_copper_begin(struct tg3 *tp)
622 {
623         uint32_t new_adv;
624
625         tp->link_config.advertising =
626                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
627                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
628                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
629                         ADVERTISED_Autoneg | ADVERTISED_MII);
630         
631         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY) {
632                 tp->link_config.advertising &=
633                         ~(ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
634         }
635         
636         new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
637         if (tp->link_config.advertising & ADVERTISED_10baseT_Half) {
638                 new_adv |= ADVERTISE_10HALF;
639         }
640         if (tp->link_config.advertising & ADVERTISED_10baseT_Full) {
641                 new_adv |= ADVERTISE_10FULL;
642         }
643         if (tp->link_config.advertising & ADVERTISED_100baseT_Half) {
644                 new_adv |= ADVERTISE_100HALF;
645         }
646         if (tp->link_config.advertising & ADVERTISED_100baseT_Full) {
647                 new_adv |= ADVERTISE_100FULL;
648         }
649         tg3_writephy(tp, MII_ADVERTISE, new_adv);
650         
651         if (tp->link_config.advertising &
652                 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
653                 new_adv = 0;
654                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half) {
655                         new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
656                 }
657                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full) {
658                         new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
659                 }
660                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
661                         (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
662                                 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)) {
663                         new_adv |= (MII_TG3_CTRL_AS_MASTER |
664                                 MII_TG3_CTRL_ENABLE_AS_MASTER);
665                 }
666                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
667         } else {
668                 tg3_writephy(tp, MII_TG3_CTRL, 0);
669         }
670
671         tg3_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
672
673         return 0;
674 }
675
676 static int tg3_init_5401phy_dsp(struct tg3 *tp)
677 {
678         int err;
679
680         /* Turn off tap power management. */
681         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c20);
682         
683         err |= tg3_writedsp(tp, 0x0012, 0x1804);
684         err |= tg3_writedsp(tp, 0x0013, 0x1204);
685         err |= tg3_writedsp(tp, 0x8006, 0x0132);
686         err |= tg3_writedsp(tp, 0x8006, 0x0232);
687         err |= tg3_writedsp(tp, 0x201f, 0x0a20);
688
689         udelay(40);
690
691         return err;
692 }
693
694 static int tg3_setup_copper_phy(struct tg3 *tp)
695 {
696         int current_link_up;
697         uint32_t bmsr, dummy;
698         int i, err;
699
700         tw32_carefully(MAC_STATUS,
701                 (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED
702                  | MAC_STATUS_LNKSTATE_CHANGED));
703
704         tp->mi_mode = MAC_MI_MODE_BASE;
705         tw32_carefully(MAC_MI_MODE, tp->mi_mode);
706
707         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
708
709         /* Some third-party PHYs need to be reset on link going
710          * down.
711          */
712         if (    (       (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) ||
713                         (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
714                         (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)) &&
715                 (tp->carrier_ok)) {
716                 tg3_readphy(tp, MII_BMSR, &bmsr);
717                 tg3_readphy(tp, MII_BMSR, &bmsr);
718                 if (!(bmsr & BMSR_LSTATUS))
719                         tg3_phy_reset(tp);
720         }
721
722         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
723                 tg3_readphy(tp, MII_BMSR, &bmsr);
724                 tg3_readphy(tp, MII_BMSR, &bmsr);
725
726                 if (!(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
727                         bmsr = 0;
728
729                 if (!(bmsr & BMSR_LSTATUS)) {
730                         err = tg3_init_5401phy_dsp(tp);
731                         if (err)
732                                 return err;
733
734                         tg3_readphy(tp, MII_BMSR, &bmsr);
735                         for (i = 0; i < 1000; i++) {
736                                 udelay(10);
737                                 tg3_readphy(tp, MII_BMSR, &bmsr);
738                                 if (bmsr & BMSR_LSTATUS) {
739                                         udelay(40);
740                                         break;
741                                 }
742                         }
743
744                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
745                             !(bmsr & BMSR_LSTATUS) &&
746                             tp->link_config.active_speed == SPEED_1000) {
747                                 err = tg3_phy_reset(tp);
748                                 if (!err)
749                                         err = tg3_init_5401phy_dsp(tp);
750                                 if (err)
751                                         return err;
752                         }
753                 }
754         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
755                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
756                 /* 5701 {A0,B0} CRC bug workaround */
757                 tg3_writephy(tp, 0x15, 0x0a75);
758                 tg3_writephy(tp, 0x1c, 0x8c68);
759                 tg3_writephy(tp, 0x1c, 0x8d68);
760                 tg3_writephy(tp, 0x1c, 0x8c68);
761         }
762
763         /* Clear pending interrupts... */
764         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
765         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
766
767         tg3_writephy(tp, MII_TG3_IMASK, ~0);
768
769         if (tp->led_mode == led_mode_three_link)
770                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
771                              MII_TG3_EXT_CTRL_LNK3_LED_MODE);
772         else
773                 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
774
775         current_link_up = 0;
776
777         tg3_readphy(tp, MII_BMSR, &bmsr);
778         tg3_readphy(tp, MII_BMSR, &bmsr);
779
780         if (bmsr & BMSR_LSTATUS) {
781                 uint32_t aux_stat, bmcr;
782
783                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
784                 for (i = 0; i < 2000; i++) {
785                         udelay(10);
786                         tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
787                         if (aux_stat)
788                                 break;
789                 }
790
791                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
792                         &tp->link_config.active_speed,
793                         &tp->link_config.active_duplex);
794                 tg3_readphy(tp, MII_BMCR, &bmcr);
795                 tg3_readphy(tp, MII_BMCR, &bmcr);
796                 if (bmcr & BMCR_ANENABLE) {
797                         uint32_t gig_ctrl;
798                         
799                         current_link_up = 1;
800                         
801                         /* Force autoneg restart if we are exiting
802                          * low power mode.
803                          */
804                         tg3_readphy(tp, MII_TG3_CTRL, &gig_ctrl);
805                         if (!(gig_ctrl & (MII_TG3_CTRL_ADV_1000_HALF |
806                                       MII_TG3_CTRL_ADV_1000_FULL))) {
807                                 current_link_up = 0;
808                         }
809                 } else {
810                         current_link_up = 0;
811                 }
812         }
813
814         if (current_link_up == 1 &&
815                 (tp->link_config.active_duplex == DUPLEX_FULL)) {
816                 uint32_t local_adv, remote_adv;
817
818                 tg3_readphy(tp, MII_ADVERTISE, &local_adv);
819                 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
820
821                 tg3_readphy(tp, MII_LPA, &remote_adv);
822                 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
823
824                 /* If we are not advertising full pause capability,
825                  * something is wrong.  Bring the link down and reconfigure.
826                  */
827                 if (local_adv != ADVERTISE_PAUSE_CAP) {
828                         current_link_up = 0;
829                 } else {
830                         tg3_setup_flow_control(tp, local_adv, remote_adv);
831                 }
832         }
833
834         if (current_link_up == 0) {
835                 uint32_t tmp;
836
837                 tg3_phy_copper_begin(tp);
838
839                 tg3_readphy(tp, MII_BMSR, &tmp);
840                 tg3_readphy(tp, MII_BMSR, &tmp);
841                 if (tmp & BMSR_LSTATUS)
842                         current_link_up = 1;
843         }
844
845         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
846         if (current_link_up == 1) {
847                 if (tp->link_config.active_speed == SPEED_100 ||
848                     tp->link_config.active_speed == SPEED_10)
849                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
850                 else
851                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
852         } else
853                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
854
855         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
856         if (tp->link_config.active_duplex == DUPLEX_HALF)
857                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
858
859         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
860         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
861                 if ((tp->led_mode == led_mode_link10) ||
862                     (current_link_up == 1 &&
863                      tp->link_config.active_speed == SPEED_10))
864                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
865         } else {
866                 if (current_link_up == 1)
867                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
868                 tw32(MAC_LED_CTRL, LED_CTRL_PHY_MODE_1);
869         }
870
871         /* ??? Without this setting Netgear GA302T PHY does not
872          * ??? send/receive packets...
873          * With this other PHYs cannot bring up the link
874          */
875         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
876                 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
877                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
878                 tw32_carefully(MAC_MI_MODE, tp->mi_mode);
879         }
880
881         tw32_carefully(MAC_MODE, tp->mac_mode);
882
883         /* Link change polled. */
884         tw32_carefully(MAC_EVENT, 0);
885
886         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
887             current_link_up == 1 &&
888             tp->link_config.active_speed == SPEED_1000 &&
889             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
890              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
891                 udelay(120);
892                 tw32_carefully(MAC_STATUS,
893                         (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED));
894                 tg3_write_mem(
895                               NIC_SRAM_FIRMWARE_MBOX,
896                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
897         }
898
899         if (current_link_up != tp->carrier_ok) {
900                 tp->carrier_ok = current_link_up;
901                 tg3_link_report(tp);
902         }
903
904         return 0;
905 }
906 #else
907 #define tg3_setup_copper_phy(TP) (-EINVAL)
908 #endif /* SUPPORT_COPPER_PHY */
909
910 #if SUPPORT_FIBER_PHY
911 struct tg3_fiber_aneginfo {
912         int state;
913 #define ANEG_STATE_UNKNOWN              0
914 #define ANEG_STATE_AN_ENABLE            1
915 #define ANEG_STATE_RESTART_INIT         2
916 #define ANEG_STATE_RESTART              3
917 #define ANEG_STATE_DISABLE_LINK_OK      4
918 #define ANEG_STATE_ABILITY_DETECT_INIT  5
919 #define ANEG_STATE_ABILITY_DETECT       6
920 #define ANEG_STATE_ACK_DETECT_INIT      7
921 #define ANEG_STATE_ACK_DETECT           8
922 #define ANEG_STATE_COMPLETE_ACK_INIT    9
923 #define ANEG_STATE_COMPLETE_ACK         10
924 #define ANEG_STATE_IDLE_DETECT_INIT     11
925 #define ANEG_STATE_IDLE_DETECT          12
926 #define ANEG_STATE_LINK_OK              13
927 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
928 #define ANEG_STATE_NEXT_PAGE_WAIT       15
929
930         uint32_t flags;
931 #define MR_AN_ENABLE            0x00000001
932 #define MR_RESTART_AN           0x00000002
933 #define MR_AN_COMPLETE          0x00000004
934 #define MR_PAGE_RX              0x00000008
935 #define MR_NP_LOADED            0x00000010
936 #define MR_TOGGLE_TX            0x00000020
937 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
938 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
939 #define MR_LP_ADV_SYM_PAUSE     0x00000100
940 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
941 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
942 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
943 #define MR_LP_ADV_NEXT_PAGE     0x00001000
944 #define MR_TOGGLE_RX            0x00002000
945 #define MR_NP_RX                0x00004000
946
947 #define MR_LINK_OK              0x80000000
948
949         unsigned long link_time, cur_time;
950
951         uint32_t ability_match_cfg;
952         int ability_match_count;
953
954         char ability_match, idle_match, ack_match;
955
956         uint32_t txconfig, rxconfig;
957 #define ANEG_CFG_NP             0x00000080
958 #define ANEG_CFG_ACK            0x00000040
959 #define ANEG_CFG_RF2            0x00000020
960 #define ANEG_CFG_RF1            0x00000010
961 #define ANEG_CFG_PS2            0x00000001
962 #define ANEG_CFG_PS1            0x00008000
963 #define ANEG_CFG_HD             0x00004000
964 #define ANEG_CFG_FD             0x00002000
965 #define ANEG_CFG_INVAL          0x00001f06
966
967 };
968 #define ANEG_OK         0
969 #define ANEG_DONE       1
970 #define ANEG_TIMER_ENAB 2
971 #define ANEG_FAILED     -1
972
973 #define ANEG_STATE_SETTLE_TIME  10000
974
975 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
976                                    struct tg3_fiber_aneginfo *ap)
977 {
978         unsigned long delta;
979         uint32_t rx_cfg_reg;
980         int ret;
981
982         if (ap->state == ANEG_STATE_UNKNOWN) {
983                 ap->rxconfig = 0;
984                 ap->link_time = 0;
985                 ap->cur_time = 0;
986                 ap->ability_match_cfg = 0;
987                 ap->ability_match_count = 0;
988                 ap->ability_match = 0;
989                 ap->idle_match = 0;
990                 ap->ack_match = 0;
991         }
992         ap->cur_time++;
993
994         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
995                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
996
997                 if (rx_cfg_reg != ap->ability_match_cfg) {
998                         ap->ability_match_cfg = rx_cfg_reg;
999                         ap->ability_match = 0;
1000                         ap->ability_match_count = 0;
1001                 } else {
1002                         if (++ap->ability_match_count > 1) {
1003                                 ap->ability_match = 1;
1004                                 ap->ability_match_cfg = rx_cfg_reg;
1005                         }
1006                 }
1007                 if (rx_cfg_reg & ANEG_CFG_ACK)
1008                         ap->ack_match = 1;
1009                 else
1010                         ap->ack_match = 0;
1011
1012                 ap->idle_match = 0;
1013         } else {
1014                 ap->idle_match = 1;
1015                 ap->ability_match_cfg = 0;
1016                 ap->ability_match_count = 0;
1017                 ap->ability_match = 0;
1018                 ap->ack_match = 0;
1019
1020                 rx_cfg_reg = 0;
1021         }
1022
1023         ap->rxconfig = rx_cfg_reg;
1024         ret = ANEG_OK;
1025
1026         switch(ap->state) {
1027         case ANEG_STATE_UNKNOWN:
1028                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
1029                         ap->state = ANEG_STATE_AN_ENABLE;
1030
1031                 /* fallthru */
1032         case ANEG_STATE_AN_ENABLE:
1033                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
1034                 if (ap->flags & MR_AN_ENABLE) {
1035                         ap->link_time = 0;
1036                         ap->cur_time = 0;
1037                         ap->ability_match_cfg = 0;
1038                         ap->ability_match_count = 0;
1039                         ap->ability_match = 0;
1040                         ap->idle_match = 0;
1041                         ap->ack_match = 0;
1042
1043                         ap->state = ANEG_STATE_RESTART_INIT;
1044                 } else {
1045                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
1046                 }
1047                 break;
1048
1049         case ANEG_STATE_RESTART_INIT:
1050                 ap->link_time = ap->cur_time;
1051                 ap->flags &= ~(MR_NP_LOADED);
1052                 ap->txconfig = 0;
1053                 tw32(MAC_TX_AUTO_NEG, 0);
1054                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1055                 tw32_carefully(MAC_MODE, tp->mac_mode);
1056
1057                 ret = ANEG_TIMER_ENAB;
1058                 ap->state = ANEG_STATE_RESTART;
1059
1060                 /* fallthru */
1061         case ANEG_STATE_RESTART:
1062                 delta = ap->cur_time - ap->link_time;
1063                 if (delta > ANEG_STATE_SETTLE_TIME) {
1064                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
1065                 } else {
1066                         ret = ANEG_TIMER_ENAB;
1067                 }
1068                 break;
1069
1070         case ANEG_STATE_DISABLE_LINK_OK:
1071                 ret = ANEG_DONE;
1072                 break;
1073
1074         case ANEG_STATE_ABILITY_DETECT_INIT:
1075                 ap->flags &= ~(MR_TOGGLE_TX);
1076                 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
1077                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
1078                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1079                 tw32_carefully(MAC_MODE, tp->mac_mode);
1080
1081                 ap->state = ANEG_STATE_ABILITY_DETECT;
1082                 break;
1083
1084         case ANEG_STATE_ABILITY_DETECT:
1085                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
1086                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
1087                 }
1088                 break;
1089
1090         case ANEG_STATE_ACK_DETECT_INIT:
1091                 ap->txconfig |= ANEG_CFG_ACK;
1092                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
1093                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1094                 tw32_carefully(MAC_MODE, tp->mac_mode);
1095
1096                 ap->state = ANEG_STATE_ACK_DETECT;
1097
1098                 /* fallthru */
1099         case ANEG_STATE_ACK_DETECT:
1100                 if (ap->ack_match != 0) {
1101                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
1102                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
1103                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
1104                         } else {
1105                                 ap->state = ANEG_STATE_AN_ENABLE;
1106                         }
1107                 } else if (ap->ability_match != 0 &&
1108                            ap->rxconfig == 0) {
1109                         ap->state = ANEG_STATE_AN_ENABLE;
1110                 }
1111                 break;
1112
1113         case ANEG_STATE_COMPLETE_ACK_INIT:
1114                 if (ap->rxconfig & ANEG_CFG_INVAL) {
1115                         ret = ANEG_FAILED;
1116                         break;
1117                 }
1118                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
1119                                MR_LP_ADV_HALF_DUPLEX |
1120                                MR_LP_ADV_SYM_PAUSE |
1121                                MR_LP_ADV_ASYM_PAUSE |
1122                                MR_LP_ADV_REMOTE_FAULT1 |
1123                                MR_LP_ADV_REMOTE_FAULT2 |
1124                                MR_LP_ADV_NEXT_PAGE |
1125                                MR_TOGGLE_RX |
1126                                MR_NP_RX);
1127                 if (ap->rxconfig & ANEG_CFG_FD)
1128                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
1129                 if (ap->rxconfig & ANEG_CFG_HD)
1130                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
1131                 if (ap->rxconfig & ANEG_CFG_PS1)
1132                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
1133                 if (ap->rxconfig & ANEG_CFG_PS2)
1134                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
1135                 if (ap->rxconfig & ANEG_CFG_RF1)
1136                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
1137                 if (ap->rxconfig & ANEG_CFG_RF2)
1138                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
1139                 if (ap->rxconfig & ANEG_CFG_NP)
1140                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
1141
1142                 ap->link_time = ap->cur_time;
1143
1144                 ap->flags ^= (MR_TOGGLE_TX);
1145                 if (ap->rxconfig & 0x0008)
1146                         ap->flags |= MR_TOGGLE_RX;
1147                 if (ap->rxconfig & ANEG_CFG_NP)
1148                         ap->flags |= MR_NP_RX;
1149                 ap->flags |= MR_PAGE_RX;
1150
1151                 ap->state = ANEG_STATE_COMPLETE_ACK;
1152                 ret = ANEG_TIMER_ENAB;
1153                 break;
1154
1155         case ANEG_STATE_COMPLETE_ACK:
1156                 if (ap->ability_match != 0 &&
1157                     ap->rxconfig == 0) {
1158                         ap->state = ANEG_STATE_AN_ENABLE;
1159                         break;
1160                 }
1161                 delta = ap->cur_time - ap->link_time;
1162                 if (delta > ANEG_STATE_SETTLE_TIME) {
1163                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
1164                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
1165                         } else {
1166                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
1167                                     !(ap->flags & MR_NP_RX)) {
1168                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
1169                                 } else {
1170                                         ret = ANEG_FAILED;
1171                                 }
1172                         }
1173                 }
1174                 break;
1175
1176         case ANEG_STATE_IDLE_DETECT_INIT:
1177                 ap->link_time = ap->cur_time;
1178                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
1179                 tw32_carefully(MAC_MODE, tp->mac_mode);
1180
1181                 ap->state = ANEG_STATE_IDLE_DETECT;
1182                 ret = ANEG_TIMER_ENAB;
1183                 break;
1184
1185         case ANEG_STATE_IDLE_DETECT:
1186                 if (ap->ability_match != 0 &&
1187                     ap->rxconfig == 0) {
1188                         ap->state = ANEG_STATE_AN_ENABLE;
1189                         break;
1190                 }
1191                 delta = ap->cur_time - ap->link_time;
1192                 if (delta > ANEG_STATE_SETTLE_TIME) {
1193                         /* XXX another gem from the Broadcom driver :( */
1194                         ap->state = ANEG_STATE_LINK_OK;
1195                 }
1196                 break;
1197
1198         case ANEG_STATE_LINK_OK:
1199                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
1200                 ret = ANEG_DONE;
1201                 break;
1202
1203         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
1204                 /* ??? unimplemented */
1205                 break;
1206
1207         case ANEG_STATE_NEXT_PAGE_WAIT:
1208                 /* ??? unimplemented */
1209                 break;
1210
1211         default:
1212                 ret = ANEG_FAILED;
1213                 break;
1214         };
1215
1216         return ret;
1217 }
1218
1219 static int tg3_setup_fiber_phy(struct tg3 *tp)
1220 {
1221         uint32_t orig_pause_cfg;
1222         uint16_t orig_active_speed;
1223         uint8_t orig_active_duplex;
1224         int current_link_up;
1225         int i;
1226
1227         orig_pause_cfg =
1228                 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
1229                                   TG3_FLAG_TX_PAUSE));
1230         orig_active_speed = tp->link_config.active_speed;
1231         orig_active_duplex = tp->link_config.active_duplex;
1232
1233         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
1234         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
1235         tw32_carefully(MAC_MODE, tp->mac_mode);
1236
1237         /* Reset when initting first time or we have a link. */
1238         if (!(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) ||
1239             (tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED)) {
1240                 /* Set PLL lock range. */
1241                 tg3_writephy(tp, 0x16, 0x8007);
1242
1243                 /* SW reset */
1244                 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
1245
1246                 /* Wait for reset to complete. */
1247                 mdelay(5);
1248
1249                 /* Config mode; select PMA/Ch 1 regs. */
1250                 tg3_writephy(tp, 0x10, 0x8411);
1251
1252                 /* Enable auto-lock and comdet, select txclk for tx. */
1253                 tg3_writephy(tp, 0x11, 0x0a10);
1254
1255                 tg3_writephy(tp, 0x18, 0x00a0);
1256                 tg3_writephy(tp, 0x16, 0x41ff);
1257
1258                 /* Assert and deassert POR. */
1259                 tg3_writephy(tp, 0x13, 0x0400);
1260                 udelay(40);
1261                 tg3_writephy(tp, 0x13, 0x0000);
1262
1263                 tg3_writephy(tp, 0x11, 0x0a50);
1264                 udelay(40);
1265                 tg3_writephy(tp, 0x11, 0x0a10);
1266
1267                 /* Wait for signal to stabilize */
1268                 mdelay(150);
1269
1270                 /* Deselect the channel register so we can read the PHYID
1271                  * later.
1272                  */
1273                 tg3_writephy(tp, 0x10, 0x8011);
1274         }
1275
1276         /* Disable link change interrupt.  */
1277         tw32_carefully(MAC_EVENT, 0);
1278
1279         current_link_up = 0;
1280         if (tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED) {
1281                 if (!(tp->tg3_flags & TG3_FLAG_GOT_SERDES_FLOWCTL)) {
1282                         struct tg3_fiber_aneginfo aninfo;
1283                         int status = ANEG_FAILED;
1284                         unsigned int tick;
1285                         uint32_t tmp;
1286
1287                         memset(&aninfo, 0, sizeof(aninfo));
1288                         aninfo.flags |= (MR_AN_ENABLE);
1289
1290                         tw32(MAC_TX_AUTO_NEG, 0);
1291
1292                         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
1293                         tw32_carefully(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
1294
1295                         tw32_carefully(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
1296
1297                         aninfo.state = ANEG_STATE_UNKNOWN;
1298                         aninfo.cur_time = 0;
1299                         tick = 0;
1300                         while (++tick < 195000) {
1301                                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
1302                                 if (status == ANEG_DONE ||
1303                                     status == ANEG_FAILED)
1304                                         break;
1305
1306                                 udelay(1);
1307                         }
1308
1309                         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
1310                         tw32_carefully(MAC_MODE, tp->mac_mode);
1311
1312                         if (status == ANEG_DONE &&
1313                             (aninfo.flags &
1314                              (MR_AN_COMPLETE | MR_LINK_OK |
1315                               MR_LP_ADV_FULL_DUPLEX))) {
1316                                 uint32_t local_adv, remote_adv;
1317
1318                                 local_adv = ADVERTISE_PAUSE_CAP;
1319                                 remote_adv = 0;
1320                                 if (aninfo.flags & MR_LP_ADV_SYM_PAUSE)
1321                                         remote_adv |= LPA_PAUSE_CAP;
1322                                 if (aninfo.flags & MR_LP_ADV_ASYM_PAUSE)
1323                                         remote_adv |= LPA_PAUSE_ASYM;
1324
1325                                 tg3_setup_flow_control(tp, local_adv, remote_adv);
1326
1327                                 tp->tg3_flags |=
1328                                         TG3_FLAG_GOT_SERDES_FLOWCTL;
1329                                 current_link_up = 1;
1330                         }
1331                         for (i = 0; i < 60; i++) {
1332                                 udelay(20);
1333                                 tw32_carefully(MAC_STATUS,
1334                                         (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED));
1335                                 if ((tr32(MAC_STATUS) &
1336                                      (MAC_STATUS_SYNC_CHANGED |
1337                                       MAC_STATUS_CFG_CHANGED)) == 0)
1338                                         break;
1339                         }
1340                         if (current_link_up == 0 &&
1341                             (tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED)) {
1342                                 current_link_up = 1;
1343                         }
1344                 } else {
1345                         /* Forcing 1000FD link up. */
1346                         current_link_up = 1;
1347                 }
1348         }
1349
1350         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1351         tw32_carefully(MAC_MODE, tp->mac_mode);
1352
1353         tp->hw_status->status =
1354                 (SD_STATUS_UPDATED |
1355                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
1356
1357         for (i = 0; i < 100; i++) {
1358                 udelay(20);
1359                 tw32_carefully(MAC_STATUS,
1360                         (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED));
1361                 if ((tr32(MAC_STATUS) &
1362                      (MAC_STATUS_SYNC_CHANGED |
1363                       MAC_STATUS_CFG_CHANGED)) == 0)
1364                         break;
1365         }
1366
1367         if ((tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED) == 0)
1368                 current_link_up = 0;
1369
1370         if (current_link_up == 1) {
1371                 tp->link_config.active_speed = SPEED_1000;
1372                 tp->link_config.active_duplex = DUPLEX_FULL;
1373         } else {
1374                 tp->link_config.active_speed = SPEED_INVALID;
1375                 tp->link_config.active_duplex = DUPLEX_INVALID;
1376         }
1377
1378         if (current_link_up != tp->carrier_ok) {
1379                 tp->carrier_ok = current_link_up;
1380                 tg3_link_report(tp);
1381         } else {
1382                 uint32_t now_pause_cfg =
1383                         tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
1384                                          TG3_FLAG_TX_PAUSE);
1385                 if (orig_pause_cfg != now_pause_cfg ||
1386                     orig_active_speed != tp->link_config.active_speed ||
1387                     orig_active_duplex != tp->link_config.active_duplex)
1388                         tg3_link_report(tp);
1389         }
1390
1391         if ((tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED) == 0) {
1392                 tw32_carefully(MAC_MODE, tp->mac_mode | MAC_MODE_LINK_POLARITY);
1393                 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
1394                         tw32_carefully(MAC_MODE, tp->mac_mode);
1395                 }
1396         }
1397
1398         return 0;
1399 }
1400 #else
1401 #define tg3_setup_fiber_phy(TP) (-EINVAL)
1402 #endif /* SUPPORT_FIBER_PHY */
1403
1404 static int tg3_setup_phy(struct tg3 *tp)
1405 {
1406         int err;
1407
1408         if (tp->phy_id == PHY_ID_SERDES) {
1409                 err = tg3_setup_fiber_phy(tp);
1410         } else {
1411                 err = tg3_setup_copper_phy(tp);
1412         }
1413
1414         if (tp->link_config.active_speed == SPEED_1000 &&
1415             tp->link_config.active_duplex == DUPLEX_HALF)
1416                 tw32(MAC_TX_LENGTHS,
1417                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1418                       (6 << TX_LENGTHS_IPG_SHIFT) |
1419                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1420         else
1421                 tw32(MAC_TX_LENGTHS,
1422                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1423                       (6 << TX_LENGTHS_IPG_SHIFT) |
1424                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1425
1426         return err;
1427 }
1428
1429
1430 #define MAX_WAIT_CNT 1000
1431
1432 /* To stop a block, clear the enable bit and poll till it
1433  * clears.  
1434  */
1435 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, uint32_t enable_bit)
1436 {
1437         unsigned int i;
1438         uint32_t val;
1439
1440         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1441                 switch(ofs) {
1442                 case RCVLSC_MODE:
1443                 case DMAC_MODE:
1444                 case MBFREE_MODE:
1445                 case BUFMGR_MODE:
1446                 case MEMARB_MODE:
1447                         /* We can't enable/disable these bits of the
1448                          * 5705, just say success.
1449                          */
1450                         return 0;
1451                 default:
1452                         break;
1453                 }
1454         }
1455         val = tr32(ofs);
1456         val &= ~enable_bit;
1457         tw32(ofs, val);
1458         tr32(ofs);
1459
1460         for (i = 0; i < MAX_WAIT_CNT; i++) {
1461                 udelay(100);
1462                 val = tr32(ofs);
1463                 if ((val & enable_bit) == 0)
1464                         break;
1465         }
1466
1467         if (i == MAX_WAIT_CNT) {
1468                 printf("tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
1469                        ofs, enable_bit);
1470                 return -ENODEV;
1471         }
1472
1473         return 0;
1474 }
1475
1476 static int tg3_abort_hw(struct tg3 *tp)
1477 {
1478         int i, err;
1479
1480         tg3_disable_ints(tp);
1481
1482         tp->rx_mode &= ~RX_MODE_ENABLE;
1483         tw32_carefully(MAC_RX_MODE, tp->rx_mode);
1484
1485         err  = tg3_stop_block(tp, RCVBDI_MODE,   RCVBDI_MODE_ENABLE);
1486         err |= tg3_stop_block(tp, RCVLPC_MODE,   RCVLPC_MODE_ENABLE);
1487         err |= tg3_stop_block(tp, RCVLSC_MODE,   RCVLSC_MODE_ENABLE);
1488         err |= tg3_stop_block(tp, RCVDBDI_MODE,  RCVDBDI_MODE_ENABLE);
1489         err |= tg3_stop_block(tp, RCVDCC_MODE,   RCVDCC_MODE_ENABLE);
1490         err |= tg3_stop_block(tp, RCVCC_MODE,    RCVCC_MODE_ENABLE);
1491
1492         err |= tg3_stop_block(tp, SNDBDS_MODE,   SNDBDS_MODE_ENABLE);
1493         err |= tg3_stop_block(tp, SNDBDI_MODE,   SNDBDI_MODE_ENABLE);
1494         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1495         err |= tg3_stop_block(tp, RDMAC_MODE,    RDMAC_MODE_ENABLE);
1496         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
1497         err |= tg3_stop_block(tp, SNDBDC_MODE,   SNDBDC_MODE_ENABLE);
1498         if (err)
1499                 goto out;
1500
1501         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
1502         tw32_carefully(MAC_MODE, tp->mac_mode);
1503
1504         tp->tx_mode &= ~TX_MODE_ENABLE;
1505         tw32_carefully(MAC_TX_MODE, tp->tx_mode);
1506
1507         for (i = 0; i < MAX_WAIT_CNT; i++) {
1508                 udelay(100);
1509                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
1510                         break;
1511         }
1512         if (i >= MAX_WAIT_CNT) {
1513                 printf("tg3_abort_hw timed out TX_MODE_ENABLE will not clear MAC_TX_MODE=%x\n",
1514                         tr32(MAC_TX_MODE));
1515                 return -ENODEV;
1516         }
1517
1518         err  = tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE);
1519         err |= tg3_stop_block(tp, WDMAC_MODE,  WDMAC_MODE_ENABLE);
1520         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE);
1521
1522         tw32(FTQ_RESET, 0xffffffff);
1523         tw32(FTQ_RESET, 0x00000000);
1524
1525         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE);
1526         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE);
1527         if (err)
1528                 goto out;
1529
1530         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
1531
1532 out:
1533         return err;
1534 }
1535
1536 static void tg3_chip_reset(struct tg3 *tp)
1537 {
1538         uint32_t val;
1539
1540         if (!(tp->tg3_flags2 & TG3_FLG2_SUN_5704)) {
1541                 /* Force NVRAM to settle.
1542                  * This deals with a chip bug which can result in EEPROM
1543                  * corruption.
1544                  */
1545                 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
1546                         int i;
1547         
1548                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
1549                         for (i = 0; i < 100000; i++) {
1550                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
1551                                         break;
1552                                 udelay(10);
1553                         }
1554                 }
1555         }
1556         /* In Etherboot we don't need to worry about the 5701
1557          * REG_WRITE_BUG because we do all register writes indirectly.
1558          */
1559
1560         // Alf: here patched
1561         /* do the reset */
1562         val = GRC_MISC_CFG_CORECLK_RESET;
1563         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
1564             || (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1565                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
1566         }
1567
1568         // Alf : Please VALIDATE THIS.
1569         // It is necessary in my case (5751) to prevent a reboot, but
1570         // I have no idea about a side effect on any other version.
1571         // It appears to be what's done in tigon3.c from Broadcom
1572         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
1573           tw32(GRC_MISC_CFG, 0x20000000) ;
1574           val |= 0x20000000 ;
1575         }
1576
1577         tw32(GRC_MISC_CFG, val);
1578
1579         /* Flush PCI posted writes.  The normal MMIO registers
1580          * are inaccessible at this time so this is the only
1581          * way to make this reliably.  I tried to use indirect
1582          * register read/write but this upset some 5701 variants.
1583          */
1584         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
1585
1586         udelay(120);
1587
1588         /* Re-enable indirect register accesses. */
1589         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
1590                                tp->misc_host_ctrl);
1591
1592         /* Set MAX PCI retry to zero. */
1593         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
1594         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
1595             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
1596                 val |= PCISTATE_RETRY_SAME_DMA;
1597         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
1598
1599         pci_restore_state(tp->pdev, tp->pci_cfg_state);
1600
1601         /* Make sure PCI-X relaxed ordering bit is clear. */
1602         pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
1603         val &= ~PCIX_CAPS_RELAXED_ORDERING;
1604         pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
1605
1606         tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
1607
1608         if (((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0) &&
1609                 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
1610                 tp->pci_clock_ctrl |=
1611                         (CLOCK_CTRL_FORCE_CLKRUN | CLOCK_CTRL_CLKRUN_OENABLE);
1612                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
1613         }
1614
1615         tw32(TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
1616 }
1617
1618 static void tg3_stop_fw(struct tg3 *tp)
1619 {
1620         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
1621                 uint32_t val;
1622                 int i;
1623
1624                 tg3_write_mem(NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1625                 val = tr32(GRC_RX_CPU_EVENT);
1626                 val |= (1 << 14);
1627                 tw32(GRC_RX_CPU_EVENT, val);
1628
1629                 /* Wait for RX cpu to ACK the event.  */
1630                 for (i = 0; i < 100; i++) {
1631                         if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
1632                                 break;
1633                         udelay(1);
1634                 }
1635         }
1636 }
1637
1638 static int tg3_restart_fw(struct tg3 *tp, uint32_t state)
1639 {
1640         uint32_t val;
1641         int i;
1642         
1643         tg3_write_mem(NIC_SRAM_FIRMWARE_MBOX, 
1644                 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1645         /* Wait for firmware initialization to complete. */
1646         for (i = 0; i < 100000; i++) {
1647                 tg3_read_mem(NIC_SRAM_FIRMWARE_MBOX, &val);
1648                 if (val == (uint32_t) ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1649                         break;
1650                 udelay(10);
1651         }
1652         if (i >= 100000 &&
1653                     !(tp->tg3_flags2 & TG3_FLG2_SUN_5704)) {
1654                 printf("Firmware will not restart magic=%x\n",
1655                         val);
1656                 return -ENODEV;
1657         }
1658         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1659           state = DRV_STATE_SUSPEND;
1660         }
1661
1662         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
1663             (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)) {
1664           // Enable PCIE bug fix
1665           tg3_read_mem(0x7c00, &val);
1666           tg3_write_mem(0x7c00, val | 0x02000000);
1667         }
1668         tg3_write_mem(NIC_SRAM_FW_DRV_STATE_MBOX, state);
1669         return 0;
1670 }
1671
1672 static int tg3_halt(struct tg3 *tp)
1673 {
1674         tg3_stop_fw(tp);
1675         tg3_abort_hw(tp);
1676         tg3_chip_reset(tp);
1677         return tg3_restart_fw(tp, DRV_STATE_UNLOAD);
1678 }
1679
1680 static void __tg3_set_mac_addr(struct tg3 *tp)
1681 {
1682         uint32_t addr_high, addr_low;
1683         int i;
1684
1685         addr_high = ((tp->nic->node_addr[0] << 8) |
1686                      tp->nic->node_addr[1]);
1687         addr_low = ((tp->nic->node_addr[2] << 24) |
1688                     (tp->nic->node_addr[3] << 16) |
1689                     (tp->nic->node_addr[4] <<  8) |
1690                     (tp->nic->node_addr[5] <<  0));
1691         for (i = 0; i < 4; i++) {
1692                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
1693                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
1694         }
1695
1696         if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
1697                 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
1698                 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705)) {
1699                 for(i = 0; i < 12; i++) {
1700                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
1701                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
1702                 }
1703         }
1704         addr_high = (tp->nic->node_addr[0] +
1705                      tp->nic->node_addr[1] +
1706                      tp->nic->node_addr[2] +
1707                      tp->nic->node_addr[3] +
1708                      tp->nic->node_addr[4] +
1709                      tp->nic->node_addr[5]) &
1710                 TX_BACKOFF_SEED_MASK;
1711         tw32(MAC_TX_BACKOFF_SEED, addr_high);
1712 }
1713
1714 static void tg3_set_bdinfo(struct tg3 *tp, uint32_t bdinfo_addr,
1715                            dma_addr_t mapping, uint32_t maxlen_flags,
1716                            uint32_t nic_addr)
1717 {
1718         tg3_write_mem((bdinfo_addr +
1719                        TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
1720                       ((uint64_t) mapping >> 32));
1721         tg3_write_mem((bdinfo_addr +
1722                        TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
1723                       ((uint64_t) mapping & 0xffffffff));
1724         tg3_write_mem((bdinfo_addr +
1725                        TG3_BDINFO_MAXLEN_FLAGS),
1726                        maxlen_flags);
1727         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
1728                 tg3_write_mem((bdinfo_addr + TG3_BDINFO_NIC_ADDR), nic_addr);
1729         }
1730 }
1731
1732
1733 static void tg3_init_rings(struct tg3 *tp)
1734 {
1735         unsigned i;
1736
1737         /* Zero out the tg3 variables */
1738         memset(&tg3_bss, 0, sizeof(tg3_bss));
1739         tp->rx_std    = &tg3_bss.rx_std[0];
1740         tp->rx_rcb    = &tg3_bss.rx_rcb[0];
1741         tp->tx_ring   = &tg3_bss.tx_ring[0];
1742         tp->hw_status = &tg3_bss.hw_status;
1743         tp->hw_stats  = &tg3_bss.hw_stats;
1744         tp->mac_mode  = 0;
1745
1746
1747         /* Initialize tx/rx rings for packet processing.
1748          *
1749          * The chip has been shut down and the driver detached from
1750          * the networking, so no interrupts or new tx packets will
1751          * end up in the driver.
1752          */
1753
1754         /* Initialize invariants of the rings, we only set this
1755          * stuff once.  This works because the card does not
1756          * write into the rx buffer posting rings.
1757          */
1758         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
1759                 struct tg3_rx_buffer_desc *rxd;
1760
1761                 rxd = &tp->rx_std[i];
1762                 rxd->idx_len = (RX_PKT_BUF_SZ - 2 - 64) << RXD_LEN_SHIFT;
1763                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
1764                 rxd->opaque = (RXD_OPAQUE_RING_STD | (i << RXD_OPAQUE_INDEX_SHIFT));
1765
1766                 /* Note where the receive buffer for the ring is placed */
1767                 rxd->addr_hi = 0;
1768                 rxd->addr_lo = virt_to_bus(
1769                         &tg3_bss.rx_bufs[i%TG3_DEF_RX_RING_PENDING][2]);
1770         }
1771 }
1772
1773 #define TG3_WRITE_SETTINGS(TABLE) \
1774 do { \
1775         const uint32_t *_table, *_end; \
1776         _table = TABLE; \
1777         _end = _table + sizeof(TABLE)/sizeof(TABLE[0]);  \
1778         for(; _table < _end; _table += 2) { \
1779                 tw32(_table[0], _table[1]); \
1780         } \
1781 } while(0)
1782
1783
1784 /* initialize/reset the tg3 */
1785 static int tg3_setup_hw(struct tg3 *tp)
1786 {
1787         uint32_t val, rdmac_mode;
1788         int i, err, limit;
1789
1790         /* Simply don't support setups with extremly buggy firmware in etherboot */
1791         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
1792                 printf("Error 5701_A0 firmware bug detected\n");
1793                 return -EINVAL;
1794         }
1795
1796         tg3_disable_ints(tp);
1797
1798         /* Originally this was all in tg3_init_hw */
1799
1800         /* Force the chip into D0. */
1801         tg3_set_power_state_0(tp);
1802
1803         tg3_switch_clocks(tp);
1804
1805         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
1806
1807         // This should go somewhere else
1808 #define T3_PCIE_CAPABILITY_ID_REG           0xD0
1809 #define T3_PCIE_CAPABILITY_ID               0x10
1810 #define T3_PCIE_CAPABILITY_REG              0xD2
1811
1812         /* Originally this was all in tg3_reset_hw */
1813
1814         tg3_stop_fw(tp);
1815
1816         /* No need to call tg3_abort_hw here, it is called before tg3_setup_hw. */
1817
1818         tg3_chip_reset(tp);
1819
1820         tw32(GRC_MODE, tp->grc_mode);  /* Redundant? */
1821
1822         err = tg3_restart_fw(tp, DRV_STATE_START);
1823         if (err)
1824                 return err;
1825
1826         if (tp->phy_id == PHY_ID_SERDES) {
1827                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
1828         }
1829         tw32_carefully(MAC_MODE, tp->mac_mode);
1830
1831
1832         /* This works around an issue with Athlon chipsets on
1833          * B3 tigon3 silicon.  This bit has no effect on any
1834          * other revision.
1835          * Alf: Except 5750 ! (which reboots)
1836          */
1837
1838         if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
1839           tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
1840         tw32_carefully(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
1841
1842         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
1843             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
1844                 val = tr32(TG3PCI_PCISTATE);
1845                 val |= PCISTATE_RETRY_SAME_DMA;
1846                 tw32(TG3PCI_PCISTATE, val);
1847         }
1848
1849         /* Descriptor ring init may make accesses to the
1850          * NIC SRAM area to setup the TX descriptors, so we
1851          * can only do this after the hardware has been
1852          * successfully reset.
1853          */
1854         tg3_init_rings(tp);
1855
1856         /* Clear statistics/status block in chip */
1857         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
1858                 for (i = NIC_SRAM_STATS_BLK;
1859                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
1860                      i += sizeof(uint32_t)) {
1861                         tg3_write_mem(i, 0);
1862                         udelay(40);
1863                 }
1864         }
1865
1866         /* This value is determined during the probe time DMA
1867          * engine test, tg3_setup_dma.
1868          */
1869         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
1870
1871         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
1872                           GRC_MODE_4X_NIC_SEND_RINGS |
1873                           GRC_MODE_NO_TX_PHDR_CSUM |
1874                           GRC_MODE_NO_RX_PHDR_CSUM);
1875         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
1876         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1877         tp->grc_mode |= GRC_MODE_NO_RX_PHDR_CSUM;
1878
1879         tw32(GRC_MODE,
1880                 tp->grc_mode | 
1881                 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
1882
1883         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
1884         tw32(GRC_MISC_CFG,
1885              (65 << GRC_MISC_CFG_PRESCALAR_SHIFT));
1886
1887         /* Initialize MBUF/DESC pool. */
1888         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
1889                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
1890                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
1891                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
1892                 else
1893                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
1894                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
1895                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
1896         }
1897         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE)) {
1898                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
1899                      tp->bufmgr_config.mbuf_read_dma_low_water);
1900                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
1901                      tp->bufmgr_config.mbuf_mac_rx_low_water);
1902                 tw32(BUFMGR_MB_HIGH_WATER,
1903                      tp->bufmgr_config.mbuf_high_water);
1904         } else {
1905                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
1906                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
1907                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
1908                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
1909                 tw32(BUFMGR_MB_HIGH_WATER,
1910                      tp->bufmgr_config.mbuf_high_water_jumbo);
1911         }
1912         tw32(BUFMGR_DMA_LOW_WATER,
1913              tp->bufmgr_config.dma_low_water);
1914         tw32(BUFMGR_DMA_HIGH_WATER,
1915              tp->bufmgr_config.dma_high_water);
1916
1917         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
1918         for (i = 0; i < 2000; i++) {
1919                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
1920                         break;
1921                 udelay(10);
1922         }
1923         if (i >= 2000) {
1924                 printf("tg3_setup_hw cannot enable BUFMGR\n");
1925                 return -ENODEV;
1926         }
1927
1928         tw32(FTQ_RESET, 0xffffffff);
1929         tw32(FTQ_RESET, 0x00000000);
1930         for (i = 0; i < 2000; i++) {
1931                 if (tr32(FTQ_RESET) == 0x00000000)
1932                         break;
1933                 udelay(10);
1934         }
1935         if (i >= 2000) {
1936                 printf("tg3_setup_hw cannot reset FTQ\n");
1937                 return -ENODEV;
1938         }
1939
1940         /* Initialize TG3_BDINFO's at:
1941          *  RCVDBDI_STD_BD:     standard eth size rx ring
1942          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
1943          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
1944          *
1945          * like so:
1946          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
1947          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
1948          *                              ring attribute flags
1949          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
1950          *
1951          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
1952          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
1953          *
1954          * ??? No space allocated for mini receive ring? :(
1955          *
1956          * The size of each ring is fixed in the firmware, but the location is
1957          * configurable.
1958          */
1959         {
1960                 static const uint32_t table_all[] = {
1961                         /* Setup replenish thresholds. */
1962                         RCVBDI_STD_THRESH, TG3_DEF_RX_RING_PENDING / 8,
1963
1964                         /* Etherboot lives below 4GB */
1965                         RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, 0,
1966                         RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR, NIC_SRAM_RX_BUFFER_DESC,
1967                 };
1968                 static const uint32_t table_not_5705[] = {
1969                         /* Buffer maximum length */
1970                         RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT,
1971                         
1972                         /* Disable the mini frame rx ring */
1973                         RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,      BDINFO_FLAGS_DISABLED,
1974                         
1975                         /* Disable the jumbo frame rx ring */
1976                         RCVBDI_JUMBO_THRESH, 0,
1977                         RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, BDINFO_FLAGS_DISABLED,
1978                         
1979                         
1980                 };
1981                 TG3_WRITE_SETTINGS(table_all);
1982                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, 
1983                         virt_to_bus(tp->rx_std));
1984                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1985                         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
1986                                 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
1987                 } else {
1988                         TG3_WRITE_SETTINGS(table_not_5705);
1989                 }
1990         }
1991
1992         
1993         /* There is only one send ring on 5705, no need to explicitly
1994          * disable the others.
1995          */
1996         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
1997                 /* Clear out send RCB ring in SRAM. */
1998                 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
1999                         tg3_write_mem(i + TG3_BDINFO_MAXLEN_FLAGS, BDINFO_FLAGS_DISABLED);
2000         }
2001
2002         tp->tx_prod = 0;
2003         tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
2004         tw32_mailbox2(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
2005
2006         tg3_set_bdinfo(tp,
2007                 NIC_SRAM_SEND_RCB,
2008                 virt_to_bus(tp->tx_ring),
2009                 (TG3_TX_RING_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT),
2010                 NIC_SRAM_TX_BUFFER_DESC);
2011
2012         /* There is only one receive return ring on 5705, no need to explicitly
2013          * disable the others.
2014          */
2015         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
2016                 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK; i += TG3_BDINFO_SIZE) {
2017                         tg3_write_mem(i + TG3_BDINFO_MAXLEN_FLAGS,
2018                                 BDINFO_FLAGS_DISABLED);
2019                 }
2020         }
2021
2022         tp->rx_rcb_ptr = 0;
2023         tw32_mailbox2(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
2024
2025         tg3_set_bdinfo(tp,
2026                 NIC_SRAM_RCV_RET_RCB,
2027                 virt_to_bus(tp->rx_rcb),
2028                 (TG3_RX_RCB_RING_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT),
2029                 0);
2030
2031         tp->rx_std_ptr = TG3_DEF_RX_RING_PENDING;
2032         tw32_mailbox2(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
2033                      tp->rx_std_ptr);
2034
2035         tw32_mailbox2(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW, 0);
2036
2037         /* Initialize MAC address and backoff seed. */
2038         __tg3_set_mac_addr(tp);
2039
2040         /* Calculate RDMAC_MODE setting early, we need it to determine
2041          * the RCVLPC_STATE_ENABLE mask.
2042          */
2043         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
2044                 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
2045                 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
2046                 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
2047                 RDMAC_MODE_LNGREAD_ENAB);
2048         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
2049                 rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
2050         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2051                 if (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
2052                         if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
2053                                 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
2054                                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
2055                         }
2056                 }
2057         }
2058
2059         /* Setup host coalescing engine. */
2060         tw32(HOSTCC_MODE, 0);
2061         for (i = 0; i < 2000; i++) {
2062                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
2063                         break;
2064                 udelay(10);
2065         }
2066
2067         tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
2068                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
2069         tw32_carefully(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
2070
2071         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
2072         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
2073                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
2074                                        GRC_LCLCTRL_GPIO_OUTPUT1);
2075         tw32_carefully(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
2076
2077         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
2078         tr32(MAILBOX_INTERRUPT_0);
2079
2080         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
2081                 tw32_carefully(DMAC_MODE, DMAC_MODE_ENABLE);
2082         }
2083
2084         val = ( WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
2085                 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
2086                 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
2087                 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
2088                 WDMAC_MODE_LNGREAD_ENAB);
2089         if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) &&
2090                 ((tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) != 0) &&
2091                 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
2092                 val |= WDMAC_MODE_RX_ACCEL;
2093         }
2094         tw32_carefully(WDMAC_MODE, val);
2095
2096         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
2097                 val = tr32(TG3PCI_X_CAPS);
2098                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
2099                         val &= PCIX_CAPS_BURST_MASK;
2100                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
2101                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2102                         val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
2103                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
2104                         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
2105                                 val |= (tp->split_mode_max_reqs <<
2106                                         PCIX_CAPS_SPLIT_SHIFT);
2107                 }
2108                 tw32(TG3PCI_X_CAPS, val);
2109         }
2110
2111         tw32_carefully(RDMAC_MODE, rdmac_mode);
2112         {
2113                 static const uint32_t table_all[] = {
2114                         /* MTU + ethernet header + FCS + optional VLAN tag */
2115                         MAC_RX_MTU_SIZE, ETH_MAX_MTU + ETH_HLEN + 8,
2116                         
2117                         /* The slot time is changed by tg3_setup_phy if we
2118                          * run at gigabit with half duplex.
2119                          */
2120                         MAC_TX_LENGTHS, 
2121                         (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2122                         (6 << TX_LENGTHS_IPG_SHIFT) |
2123                         (32 << TX_LENGTHS_SLOT_TIME_SHIFT),
2124                         
2125                         /* Receive rules. */
2126                         MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS,
2127                         RCVLPC_CONFIG, 0x0181,
2128                         
2129                         /* Receive/send statistics. */
2130                         RCVLPC_STATS_ENABLE, 0xffffff,
2131                         RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE,
2132                         SNDDATAI_STATSENAB, 0xffffff,
2133                         SNDDATAI_STATSCTRL, (SNDDATAI_SCTRL_ENABLE |SNDDATAI_SCTRL_FASTUPD),
2134                         
2135                         /* Host coalescing engine */
2136                         HOSTCC_RXCOL_TICKS, 0,
2137                         HOSTCC_TXCOL_TICKS, LOW_TXCOL_TICKS,
2138                         HOSTCC_RXMAX_FRAMES, 1,
2139                         HOSTCC_TXMAX_FRAMES, LOW_RXMAX_FRAMES,
2140                         HOSTCC_RXCOAL_MAXF_INT, 1,
2141                         HOSTCC_TXCOAL_MAXF_INT, 0,
2142                         
2143                         /* Status/statistics block address. */
2144                         /* Etherboot lives below 4GB, so HIGH == 0 */
2145                         HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, 0,
2146
2147                         /* No need to enable 32byte coalesce mode. */
2148                         HOSTCC_MODE, HOSTCC_MODE_ENABLE | 0,
2149                         
2150                         RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE,
2151                         RCVLPC_MODE, RCVLPC_MODE_ENABLE,
2152                         
2153                         RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE,
2154
2155                         SNDDATAC_MODE, SNDDATAC_MODE_ENABLE,
2156                         SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE,
2157                         RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB,
2158                         RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ,
2159                         SNDDATAI_MODE, SNDDATAI_MODE_ENABLE,
2160                         SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE,
2161                         SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE,
2162                         
2163                         /* Accept all multicast frames. */
2164                         MAC_HASH_REG_0, 0xffffffff,
2165                         MAC_HASH_REG_1, 0xffffffff,
2166                         MAC_HASH_REG_2, 0xffffffff,
2167                         MAC_HASH_REG_3, 0xffffffff,
2168                 };
2169                 static const uint32_t table_not_5705[] = {
2170                         /* Host coalescing engine */
2171                         HOSTCC_RXCOAL_TICK_INT, 0,
2172                         HOSTCC_TXCOAL_TICK_INT, 0,
2173
2174                         /* Status/statistics block address. */
2175                         /* Etherboot lives below 4GB, so HIGH == 0 */
2176                         HOSTCC_STAT_COAL_TICKS, DEFAULT_STAT_COAL_TICKS,
2177                         HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, 0,
2178                         HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK,
2179                         HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK,
2180
2181                         RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE,
2182
2183                         MBFREE_MODE, MBFREE_MODE_ENABLE,
2184                 };
2185                 TG3_WRITE_SETTINGS(table_all);
2186                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
2187                         virt_to_bus(tp->hw_stats));
2188                 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
2189                         virt_to_bus(tp->hw_status));
2190                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
2191                         TG3_WRITE_SETTINGS(table_not_5705);
2192                 }
2193         }
2194
2195         tp->tx_mode = TX_MODE_ENABLE;
2196         tw32_carefully(MAC_TX_MODE, tp->tx_mode);
2197
2198         tp->rx_mode = RX_MODE_ENABLE;
2199         tw32_carefully(MAC_RX_MODE, tp->rx_mode);
2200
2201         tp->mi_mode = MAC_MI_MODE_BASE;
2202         tw32_carefully(MAC_MI_MODE, tp->mi_mode);
2203
2204         tw32(MAC_LED_CTRL, 0);
2205         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2206         if (tp->phy_id == PHY_ID_SERDES) {
2207                 tw32_carefully(MAC_RX_MODE, RX_MODE_RESET);
2208         }
2209         tp->rx_mode |= RX_MODE_KEEP_VLAN_TAG; /* drop tagged vlan packets */
2210         tw32_carefully(MAC_RX_MODE, tp->rx_mode);
2211
2212         if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
2213                 tw32(MAC_SERDES_CFG, 0x616000);
2214
2215         /* Prevent chip from dropping frames when flow control
2216          * is enabled.
2217          */
2218         tw32(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
2219         tr32(MAC_LOW_WMARK_MAX_RX_FRAME);
2220
2221         err = tg3_setup_phy(tp);
2222
2223         /* Ignore CRC stats */
2224
2225         /* Initialize receive rules. */
2226         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
2227         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
2228         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
2229         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
2230
2231         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
2232             || (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750))
2233                 limit = 8;
2234         else
2235                 limit = 16;
2236         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
2237                 limit -= 4;
2238         switch (limit) {
2239         case 16:        tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
2240         case 15:        tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
2241         case 14:        tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
2242         case 13:        tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
2243         case 12:        tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
2244         case 11:        tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
2245         case 10:        tw32(MAC_RCV_RULE_9,  0);  tw32(MAC_RCV_VALUE_9,  0);
2246         case 9:         tw32(MAC_RCV_RULE_8,  0);  tw32(MAC_RCV_VALUE_8,  0);
2247         case 8:         tw32(MAC_RCV_RULE_7,  0);  tw32(MAC_RCV_VALUE_7,  0);
2248         case 7:         tw32(MAC_RCV_RULE_6,  0);  tw32(MAC_RCV_VALUE_6,  0);
2249         case 6:         tw32(MAC_RCV_RULE_5,  0);  tw32(MAC_RCV_VALUE_5,  0);
2250         case 5:         tw32(MAC_RCV_RULE_4,  0);  tw32(MAC_RCV_VALUE_4,  0);
2251         case 4:         /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
2252         case 3:         /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
2253         case 2:
2254         case 1:
2255         default:
2256                 break;
2257         };
2258
2259         return err;
2260 }
2261
2262
2263
2264 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
2265 static void tg3_nvram_init(struct tg3 *tp)
2266 {
2267         tw32(GRC_EEPROM_ADDR,
2268              (EEPROM_ADDR_FSM_RESET |
2269               (EEPROM_DEFAULT_CLOCK_PERIOD <<
2270                EEPROM_ADDR_CLKPERD_SHIFT)));
2271
2272         mdelay(1);
2273
2274         /* Enable seeprom accesses. */
2275         tw32_carefully(GRC_LOCAL_CTRL,
2276                 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
2277
2278         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2279             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2280                 uint32_t nvcfg1 = tr32(NVRAM_CFG1);
2281
2282                 tp->tg3_flags |= TG3_FLAG_NVRAM;
2283                 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
2284                         if (nvcfg1 & NVRAM_CFG1_BUFFERED_MODE)
2285                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
2286                 } else {
2287                         nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
2288                         tw32(NVRAM_CFG1, nvcfg1);
2289                 }
2290
2291         } else {
2292                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
2293         }
2294 }
2295
2296
2297 static int tg3_nvram_read_using_eeprom(
2298         struct tg3 *tp __unused, uint32_t offset, uint32_t *val)
2299 {
2300         uint32_t tmp;
2301         int i;
2302
2303         if (offset > EEPROM_ADDR_ADDR_MASK ||
2304                 (offset % 4) != 0) {
2305                 return -EINVAL;
2306         }
2307
2308         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2309                                         EEPROM_ADDR_DEVID_MASK |
2310                                         EEPROM_ADDR_READ);
2311         tw32(GRC_EEPROM_ADDR,
2312              tmp |
2313              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2314              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2315               EEPROM_ADDR_ADDR_MASK) |
2316              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2317
2318         for (i = 0; i < 10000; i++) {
2319                 tmp = tr32(GRC_EEPROM_ADDR);
2320
2321                 if (tmp & EEPROM_ADDR_COMPLETE)
2322                         break;
2323                 udelay(100);
2324         }
2325         if (!(tmp & EEPROM_ADDR_COMPLETE)) {
2326                 return -EBUSY;
2327         }
2328
2329         *val = tr32(GRC_EEPROM_DATA);
2330         return 0;
2331 }
2332
2333 static int tg3_nvram_read(struct tg3 *tp, uint32_t offset, uint32_t *val)
2334 {
2335         int i, saw_done_clear;
2336
2337         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2338                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2339
2340         if (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED)
2341                 offset = ((offset / NVRAM_BUFFERED_PAGE_SIZE) <<
2342                           NVRAM_BUFFERED_PAGE_POS) +
2343                         (offset % NVRAM_BUFFERED_PAGE_SIZE);
2344
2345         if (offset > NVRAM_ADDR_MSK)
2346                 return -EINVAL;
2347
2348         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2349         for (i = 0; i < 1000; i++) {
2350                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2351                         break;
2352                 udelay(20);
2353         }
2354
2355         tw32(NVRAM_ADDR, offset);
2356         tw32(NVRAM_CMD,
2357              NVRAM_CMD_RD | NVRAM_CMD_GO |
2358              NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2359
2360         /* Wait for done bit to clear then set again. */
2361         saw_done_clear = 0;
2362         for (i = 0; i < 1000; i++) {
2363                 udelay(10);
2364                 if (!saw_done_clear &&
2365                     !(tr32(NVRAM_CMD) & NVRAM_CMD_DONE))
2366                         saw_done_clear = 1;
2367                 else if (saw_done_clear &&
2368                          (tr32(NVRAM_CMD) & NVRAM_CMD_DONE))
2369                         break;
2370         }
2371         if (i >= 1000) {
2372                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2373                 return -EBUSY;
2374         }
2375
2376         *val = bswap_32(tr32(NVRAM_RDDATA));
2377         tw32(NVRAM_SWARB, 0x20);
2378
2379         return 0;
2380 }
2381
2382 struct subsys_tbl_ent {
2383         uint16_t subsys_vendor, subsys_devid;
2384         uint32_t phy_id;
2385 };
2386
2387 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
2388         /* Broadcom boards. */
2389         { 0x14e4, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
2390         { 0x14e4, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
2391         { 0x14e4, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
2392         { 0x14e4, 0x0003, PHY_ID_SERDES  }, /* BCM95700A9 */
2393         { 0x14e4, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
2394         { 0x14e4, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
2395         { 0x14e4, 0x0007, PHY_ID_SERDES  }, /* BCM95701A7 */
2396         { 0x14e4, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
2397         { 0x14e4, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
2398         { 0x14e4, 0x0009, PHY_ID_BCM5701 }, /* BCM95703Ax1 */
2399         { 0x14e4, 0x8009, PHY_ID_BCM5701 }, /* BCM95703Ax2 */
2400
2401         /* 3com boards. */
2402         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
2403         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
2404         /* { PCI_VENDOR_ID_3COM, 0x1002, PHY_ID_XXX },     3C996CT */
2405         /* { PCI_VENDOR_ID_3COM, 0x1003, PHY_ID_XXX },     3C997T */
2406         { PCI_VENDOR_ID_3COM, 0x1004, PHY_ID_SERDES  }, /* 3C996SX */
2407         /* { PCI_VENDOR_ID_3COM, 0x1005, PHY_ID_XXX },     3C997SZ */
2408         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
2409         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
2410
2411         /* DELL boards. */
2412         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
2413         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
2414         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
2415         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
2416         { PCI_VENDOR_ID_DELL, 0x0179, PHY_ID_BCM5751 }, /* EtherXpress */
2417
2418         /* Compaq boards. */
2419         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
2420         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
2421         { PCI_VENDOR_ID_COMPAQ, 0x007d, PHY_ID_SERDES  }, /* CHANGELING */
2422         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
2423         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }  /* NC7780_2 */
2424 };
2425
2426 static int tg3_phy_probe(struct tg3 *tp)
2427 {
2428         uint32_t eeprom_phy_id, hw_phy_id_1, hw_phy_id_2;
2429         uint32_t hw_phy_id, hw_phy_id_masked;
2430         enum phy_led_mode eeprom_led_mode;
2431         uint32_t val;
2432         unsigned i;
2433         int eeprom_signature_found, err;
2434
2435         tp->phy_id = PHY_ID_INVALID;
2436
2437         for (i = 0; i < sizeof(subsys_id_to_phy_id)/sizeof(subsys_id_to_phy_id[0]); i++) {
2438                 if ((subsys_id_to_phy_id[i].subsys_vendor == tp->subsystem_vendor) &&
2439                         (subsys_id_to_phy_id[i].subsys_devid == tp->subsystem_device)) {
2440                         tp->phy_id = subsys_id_to_phy_id[i].phy_id;
2441                         break;
2442                 }
2443         }
2444
2445         eeprom_phy_id = PHY_ID_INVALID;
2446         eeprom_led_mode = led_mode_auto;
2447         eeprom_signature_found = 0;
2448         tg3_read_mem(NIC_SRAM_DATA_SIG, &val);
2449         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
2450                 uint32_t nic_cfg;
2451
2452                 tg3_read_mem(NIC_SRAM_DATA_CFG, &nic_cfg);
2453                 tp->nic_sram_data_cfg = nic_cfg;
2454
2455                 eeprom_signature_found = 1;
2456
2457                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
2458                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER) {
2459                         eeprom_phy_id = PHY_ID_SERDES;
2460                 } else {
2461                         uint32_t nic_phy_id;
2462
2463                         tg3_read_mem(NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
2464                         if (nic_phy_id != 0) {
2465                                 uint32_t id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
2466                                 uint32_t id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
2467
2468                                 eeprom_phy_id  = (id1 >> 16) << 10;
2469                                 eeprom_phy_id |= (id2 & 0xfc00) << 16;
2470                                 eeprom_phy_id |= (id2 & 0x03ff) <<  0;
2471                         }
2472                 }
2473
2474                 switch (nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK) {
2475                 case NIC_SRAM_DATA_CFG_LED_TRIPLE_SPD:
2476                         eeprom_led_mode = led_mode_three_link;
2477                         break;
2478
2479                 case NIC_SRAM_DATA_CFG_LED_LINK_SPD:
2480                         eeprom_led_mode = led_mode_link10;
2481                         break;
2482
2483                 default:
2484                         eeprom_led_mode = led_mode_auto;
2485                         break;
2486                 };
2487                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) ||
2488                         (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
2489                         (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) &&
2490                         (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP)) {
2491                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
2492                 }
2493
2494                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE)
2495                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
2496                 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
2497                         tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
2498         }
2499
2500         /* Now read the physical PHY_ID from the chip and verify
2501          * that it is sane.  If it doesn't look good, we fall back
2502          * to either the hard-coded table based PHY_ID and failing
2503          * that the value found in the eeprom area.
2504          */
2505         err  = tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
2506         err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
2507
2508         hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
2509         hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
2510         hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
2511
2512         hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
2513
2514         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
2515                 tp->phy_id = hw_phy_id;
2516         } else {
2517                 /* phy_id currently holds the value found in the
2518                  * subsys_id_to_phy_id[] table or PHY_ID_INVALID
2519                  * if a match was not found there.
2520                  */
2521                 if (tp->phy_id == PHY_ID_INVALID) {
2522                         if (!eeprom_signature_found ||
2523                             !KNOWN_PHY_ID(eeprom_phy_id & PHY_ID_MASK))
2524                                 return -ENODEV;
2525                         tp->phy_id = eeprom_phy_id;
2526                 }
2527         }
2528
2529         err = tg3_phy_reset(tp);
2530         if (err)
2531                 return err;
2532
2533         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2534             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
2535                 uint32_t mii_tg3_ctrl;
2536                 
2537                 /* These chips, when reset, only advertise 10Mb
2538                  * capabilities.  Fix that.
2539                  */
2540                 err  = tg3_writephy(tp, MII_ADVERTISE,
2541                                     (ADVERTISE_CSMA |
2542                                      ADVERTISE_PAUSE_CAP |
2543                                      ADVERTISE_10HALF |
2544                                      ADVERTISE_10FULL |
2545                                      ADVERTISE_100HALF |
2546                                      ADVERTISE_100FULL));
2547                 mii_tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
2548                                 MII_TG3_CTRL_ADV_1000_FULL |
2549                                 MII_TG3_CTRL_AS_MASTER |
2550                                 MII_TG3_CTRL_ENABLE_AS_MASTER);
2551                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2552                         mii_tg3_ctrl = 0;
2553
2554                 err |= tg3_writephy(tp, MII_TG3_CTRL, mii_tg3_ctrl);
2555                 err |= tg3_writephy(tp, MII_BMCR,
2556                                     (BMCR_ANRESTART | BMCR_ANENABLE));
2557         }
2558
2559         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
2560                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2561                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2562                 tg3_writedsp(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
2563         }
2564
2565         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2566                 tg3_writephy(tp, 0x1c, 0x8d68);
2567                 tg3_writephy(tp, 0x1c, 0x8d68);
2568         }
2569
2570         /* Enable Ethernet@WireSpeed */
2571         tg3_phy_set_wirespeed(tp);
2572
2573         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
2574                 err = tg3_init_5401phy_dsp(tp);
2575         }
2576
2577         /* Determine the PHY led mode. 
2578          * Be careful if this gets set wrong it can result in an inability to 
2579          * establish a link.
2580          */
2581         if (tp->phy_id == PHY_ID_SERDES) {
2582                 tp->led_mode = led_mode_three_link;
2583         }
2584         else if (tp->subsystem_vendor == PCI_VENDOR_ID_DELL) {
2585                 tp->led_mode = led_mode_link10;
2586         } else {
2587                 tp->led_mode = led_mode_three_link;
2588                 if (eeprom_signature_found &&
2589                     eeprom_led_mode != led_mode_auto)
2590                         tp->led_mode = eeprom_led_mode;
2591         }
2592
2593         if (tp->phy_id == PHY_ID_SERDES)
2594                 tp->link_config.advertising =
2595                         (ADVERTISED_1000baseT_Half |
2596                          ADVERTISED_1000baseT_Full |
2597                          ADVERTISED_Autoneg |
2598                          ADVERTISED_FIBRE);
2599         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2600                 tp->link_config.advertising &=
2601                         ~(ADVERTISED_1000baseT_Half |
2602                           ADVERTISED_1000baseT_Full);
2603
2604         return err;
2605 }
2606
2607 #if SUPPORT_PARTNO_STR
2608 static void tg3_read_partno(struct tg3 *tp)
2609 {
2610         unsigned char vpd_data[256];
2611         int i;
2612
2613         for (i = 0; i < 256; i += 4) {
2614                 uint32_t tmp;
2615
2616                 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
2617                         goto out_not_found;
2618
2619                 vpd_data[i + 0] = ((tmp >>  0) & 0xff);
2620                 vpd_data[i + 1] = ((tmp >>  8) & 0xff);
2621                 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
2622                 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
2623         }
2624
2625         /* Now parse and find the part number. */
2626         for (i = 0; i < 256; ) {
2627                 unsigned char val = vpd_data[i];
2628                 int block_end;
2629
2630                 if (val == 0x82 || val == 0x91) {
2631                         i = (i + 3 +
2632                              (vpd_data[i + 1] +
2633                               (vpd_data[i + 2] << 8)));
2634                         continue;
2635                 }
2636
2637                 if (val != 0x90)
2638                         goto out_not_found;
2639
2640                 block_end = (i + 3 +
2641                              (vpd_data[i + 1] +
2642                               (vpd_data[i + 2] << 8)));
2643                 i += 3;
2644                 while (i < block_end) {
2645                         if (vpd_data[i + 0] == 'P' &&
2646                             vpd_data[i + 1] == 'N') {
2647                                 int partno_len = vpd_data[i + 2];
2648
2649                                 if (partno_len > 24)
2650                                         goto out_not_found;
2651
2652                                 memcpy(tp->board_part_number,
2653                                        &vpd_data[i + 3],
2654                                        partno_len);
2655
2656                                 /* Success. */
2657                                 return;
2658                         }
2659                 }
2660
2661                 /* Part number not found. */
2662                 goto out_not_found;
2663         }
2664
2665 out_not_found:
2666         memcpy(tp->board_part_number, "none", sizeof("none"));
2667 }
2668 #else
2669 #define tg3_read_partno(TP) ((TP)->board_part_number[0] = '\0')
2670 #endif
2671
2672 static int tg3_get_invariants(struct tg3 *tp)
2673 {
2674         uint32_t misc_ctrl_reg;
2675         uint32_t pci_state_reg, grc_misc_cfg;
2676         uint16_t pci_cmd;
2677         uint8_t  pci_latency;
2678         uint32_t val ;
2679         int err;
2680
2681         /* Read the subsystem vendor and device ids */
2682         pci_read_config_word(tp->pdev, PCI_SUBSYSTEM_VENDOR_ID, &tp->subsystem_vendor);
2683         pci_read_config_word(tp->pdev, PCI_SUBSYSTEM_ID, &tp->subsystem_device);
2684
2685         /* The sun_5704 code needs infrastructure etherboot does have
2686          * ignore it for now.
2687          */
2688
2689         /* If we have an AMD 762 or Intel ICH/ICH0 chipset, write
2690          * reordering to the mailbox registers done by the host
2691          * controller can cause major troubles.  We read back from
2692          * every mailbox register write to force the writes to be
2693          * posted to the chip in order.
2694          *
2695          * TG3_FLAG_MBOX_WRITE_REORDER has been forced on.
2696          */
2697
2698         /* Force memory write invalidate off.  If we leave it on,
2699          * then on 5700_BX chips we have to enable a workaround.
2700          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundry
2701          * to match the cacheline size.  The Broadcom driver have this
2702          * workaround but turns MWI off all the times so never uses
2703          * it.  This seems to suggest that the workaround is insufficient.
2704          */
2705         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
2706         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
2707         /* Also, force SERR#/PERR# in PCI command. */
2708         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
2709         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
2710
2711         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
2712          * has the register indirect write enable bit set before
2713          * we try to access any of the MMIO registers.  It is also
2714          * critical that the PCI-X hw workaround situation is decided
2715          * before that as well.
2716          */
2717         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, &misc_ctrl_reg);
2718
2719         tp->pci_chip_rev_id = (misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT);
2720
2721         /* Initialize misc host control in PCI block. */
2722         tp->misc_host_ctrl |= (misc_ctrl_reg &
2723                                MISC_HOST_CTRL_CHIPREV);
2724         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
2725                                tp->misc_host_ctrl);
2726
2727         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, &pci_latency);
2728         if (pci_latency < 64) {
2729                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, 64);
2730         }
2731
2732         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &pci_state_reg);
2733
2734         /* If this is a 5700 BX chipset, and we are in PCI-X
2735          * mode, enable register write workaround.
2736          *
2737          * The workaround is to use indirect register accesses
2738          * for all chip writes not to mailbox registers.
2739          *
2740          * In etherboot to simplify things we just always use this work around.
2741          */
2742         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
2743                 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
2744         }
2745         /* Back to back register writes can cause problems on the 5701,
2746          * the workaround is to read back all reg writes except those to
2747          * mailbox regs.
2748          * In etherboot we always use indirect register accesses so
2749          * we don't see this.
2750          */
2751
2752         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
2753                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
2754         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
2755                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
2756
2757         /* Chip-specific fixup from Broadcom driver */
2758         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
2759             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
2760                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
2761                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
2762         }
2763
2764         /* determine if it is PCIE system */
2765         // Alf : I have no idea what this is about...
2766         // But it's definitely usefull
2767         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
2768           val = tr32(TG3PCI_MSI_CAP_ID) ;
2769           if (((val >> 8) & 0xff) == T3_PCIE_CAPABILITY_ID_REG) {
2770             val = tr32(T3_PCIE_CAPABILITY_ID_REG) ;
2771             if ((val & 0xff) == T3_PCIE_CAPABILITY_ID) {
2772               tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS ;
2773             }
2774           }
2775         }
2776
2777         /* Force the chip into D0. */
2778         tg3_set_power_state_0(tp);
2779
2780         /* Etherboot does not ask the tg3 to do checksums */
2781         /* Etherboot does not ask the tg3 to do jumbo frames */
2782         /* Ehterboot does not ask the tg3 to use WakeOnLan. */
2783
2784         /* A few boards don't want Ethernet@WireSpeed phy feature */
2785         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
2786             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
2787                 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2788                         (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
2789                         (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1))) {
2790                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
2791         }
2792
2793         /* Avoid tagged irq status etherboot does not use irqs */
2794
2795         /* Only 5701 and later support tagged irq status mode.
2796          * Also, 5788 chips cannot use tagged irq status.
2797          *
2798          * However, since etherboot does not use irqs avoid tagged irqs
2799          * status  because the interrupt condition is more difficult to
2800          * fully clear in that mode.
2801          */
2802         
2803         /* Since some 5700_AX && 5700_BX have problems with 32BYTE
2804          * coalesce_mode, and the rest work fine anything set.
2805          * Don't enable HOST_CC_MODE_32BYTE in etherboot.
2806          */
2807
2808         /* Initialize MAC MI mode, polling disabled. */
2809         tw32_carefully(MAC_MI_MODE, tp->mi_mode);
2810
2811         /* Initialize data/descriptor byte/word swapping. */
2812         tw32(GRC_MODE, tp->grc_mode);
2813
2814         tg3_switch_clocks(tp);
2815
2816         /* Clear this out for sanity. */
2817         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
2818
2819         /* Etherboot does not need to check if the PCIX_TARGET_HWBUG
2820          * is needed.  It always uses it.
2821          */
2822         
2823         udelay(50);
2824         tg3_nvram_init(tp);
2825
2826         /* The TX descriptors will reside in main memory.
2827          */
2828
2829         /* See which board we are using.
2830          */
2831         grc_misc_cfg = tr32(GRC_MISC_CFG);
2832         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
2833
2834         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
2835             grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5704CIOBE) {
2836                 tp->tg3_flags |= TG3_FLAG_SPLIT_MODE;
2837                 tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ;
2838         }
2839
2840         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
2841             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
2842              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
2843                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
2844
2845 #define PCI_DEVICE_ID_TIGON3_5901       0x170d
2846 #define PCI_DEVICE_ID_TIGON3_5901_2     0x170e
2847
2848         /* these are limited to 10/100 only */
2849         if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) &&
2850                     ((grc_misc_cfg == 0x8000) || (grc_misc_cfg == 0x4000))) ||
2851                 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2852                         (tp->pdev->vendor_id == PCI_VENDOR_ID_BROADCOM) &&
2853                         ((tp->pdev->device_id == PCI_DEVICE_ID_TIGON3_5901) ||
2854                                 (tp->pdev->device_id == PCI_DEVICE_ID_TIGON3_5901_2)))) {
2855                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
2856         }
2857
2858         err = tg3_phy_probe(tp);
2859         if (err) {
2860                 printf("phy probe failed, err %d\n", err);
2861         }
2862
2863         tg3_read_partno(tp);
2864
2865
2866         /* 5700 BX chips need to have their TX producer index mailboxes
2867          * written twice to workaround a bug.
2868          * In etherboot we do this unconditionally to simplify things.
2869          */
2870
2871         /* 5700 chips can get confused if TX buffers straddle the
2872          * 4GB address boundary in some cases.
2873          * 
2874          * In etherboot we can ignore the problem as etherboot lives below 4GB.
2875          */
2876
2877         /* In etherboot wake-on-lan is unconditionally disabled */
2878         return err;
2879 }
2880
2881 static int  tg3_get_device_address(struct tg3 *tp)
2882 {
2883         struct nic *nic = tp->nic;
2884         uint32_t hi, lo, mac_offset;
2885
2886         if (PCI_FUNC(tp->pdev->busdevfn) == 0)
2887                 mac_offset = 0x7c;
2888         else
2889                 mac_offset = 0xcc;
2890
2891         /* First try to get it from MAC address mailbox. */
2892         tg3_read_mem(NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
2893         if ((hi >> 16) == 0x484b) {
2894                 nic->node_addr[0] = (hi >>  8) & 0xff;
2895                 nic->node_addr[1] = (hi >>  0) & 0xff;
2896
2897                 tg3_read_mem(NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
2898                 nic->node_addr[2] = (lo >> 24) & 0xff;
2899                 nic->node_addr[3] = (lo >> 16) & 0xff;
2900                 nic->node_addr[4] = (lo >>  8) & 0xff;
2901                 nic->node_addr[5] = (lo >>  0) & 0xff;
2902         }
2903         /* Next, try NVRAM. */
2904         else if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
2905                  !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
2906                 nic->node_addr[0] = ((hi >> 16) & 0xff);
2907                 nic->node_addr[1] = ((hi >> 24) & 0xff);
2908                 nic->node_addr[2] = ((lo >>  0) & 0xff);
2909                 nic->node_addr[3] = ((lo >>  8) & 0xff);
2910                 nic->node_addr[4] = ((lo >> 16) & 0xff);
2911                 nic->node_addr[5] = ((lo >> 24) & 0xff);
2912         }
2913         /* Finally just fetch it out of the MAC control regs. */
2914         else {
2915                 hi = tr32(MAC_ADDR_0_HIGH);
2916                 lo = tr32(MAC_ADDR_0_LOW);
2917
2918                 nic->node_addr[5] = lo & 0xff;
2919                 nic->node_addr[4] = (lo >> 8) & 0xff;
2920                 nic->node_addr[3] = (lo >> 16) & 0xff;
2921                 nic->node_addr[2] = (lo >> 24) & 0xff;
2922                 nic->node_addr[1] = hi & 0xff;
2923                 nic->node_addr[0] = (hi >> 8) & 0xff;
2924         }
2925
2926         return 0;
2927 }
2928
2929
2930 static int tg3_setup_dma(struct tg3 *tp)
2931 {
2932         tw32(TG3PCI_CLOCK_CTRL, 0);
2933
2934         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) == 0) {
2935                 tp->dma_rwctrl =
2936                         (0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
2937                         (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT) |
2938                         (0x7 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
2939                         (0x7 << DMA_RWCTRL_READ_WATER_SHIFT) |
2940                         (0x0f << DMA_RWCTRL_MIN_DMA_SHIFT);
2941                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2942                         tp->dma_rwctrl &= ~(DMA_RWCTRL_MIN_DMA << DMA_RWCTRL_MIN_DMA_SHIFT);
2943                 }
2944         } else {
2945                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
2946                         tp->dma_rwctrl =
2947                                 (0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
2948                                 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT) |
2949                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
2950                                 (0x7 << DMA_RWCTRL_READ_WATER_SHIFT) |
2951                                 (0x00 << DMA_RWCTRL_MIN_DMA_SHIFT);
2952                 else
2953                         tp->dma_rwctrl =
2954                                 (0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
2955                                 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT) |
2956                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
2957                                 (0x3 << DMA_RWCTRL_READ_WATER_SHIFT) |
2958                                 (0x0f << DMA_RWCTRL_MIN_DMA_SHIFT);
2959
2960                 /* Wheee, some more chip bugs... */
2961                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) ||
2962                         (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)) {
2963                         uint32_t ccval = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
2964
2965                         if ((ccval == 0x6) || (ccval == 0x7)) {
2966                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
2967                         }
2968                 }
2969         }
2970
2971         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) ||
2972                 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)) {
2973                 tp->dma_rwctrl &= ~(DMA_RWCTRL_MIN_DMA << DMA_RWCTRL_MIN_DMA_SHIFT);
2974         }
2975
2976         /*
2977           Alf : Tried that, but it does not work. Should be this way though :-(
2978         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
2979           tp->dma_rwctrl |= 0x001f0000;
2980         }
2981         */
2982         tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
2983
2984         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
2985
2986         return 0;
2987 }
2988
2989 static void tg3_init_link_config(struct tg3 *tp)
2990 {
2991         tp->link_config.advertising =
2992                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2993                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
2994                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
2995                  ADVERTISED_Autoneg | ADVERTISED_MII);
2996         tp->carrier_ok = 0;
2997         tp->link_config.active_speed = SPEED_INVALID;
2998         tp->link_config.active_duplex = DUPLEX_INVALID;
2999 }
3000
3001
3002 #if SUPPORT_PHY_STR
3003 static const char * tg3_phy_string(struct tg3 *tp)
3004 {
3005         switch (tp->phy_id & PHY_ID_MASK) {
3006         case PHY_ID_BCM5400:    return "5400";
3007         case PHY_ID_BCM5401:    return "5401";
3008         case PHY_ID_BCM5411:    return "5411";
3009         case PHY_ID_BCM5701:    return "5701";
3010         case PHY_ID_BCM5703:    return "5703";
3011         case PHY_ID_BCM5704:    return "5704";
3012         case PHY_ID_BCM5705:    return "5705";
3013         case PHY_ID_BCM5750:    return "5750";
3014         case PHY_ID_BCM5751:    return "5751"; 
3015         case PHY_ID_BCM8002:    return "8002/serdes";
3016         case PHY_ID_SERDES:     return "serdes";
3017         default:                return "unknown";
3018         };
3019 }
3020 #else
3021 #define tg3_phy_string(TP) "?"
3022 #endif
3023
3024
3025 static void tg3_poll_link(struct tg3 *tp)
3026 {
3027         uint32_t mac_stat;
3028
3029         mac_stat = tr32(MAC_STATUS);
3030         if (tp->phy_id == PHY_ID_SERDES) {
3031                 if (tp->carrier_ok?
3032                         (mac_stat & MAC_STATUS_LNKSTATE_CHANGED):
3033                         (mac_stat & MAC_STATUS_PCS_SYNCED)) {
3034                         tw32_carefully(MAC_MODE, tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK);
3035                         tw32_carefully(MAC_MODE, tp->mac_mode);
3036
3037                         tg3_setup_phy(tp);
3038                 }
3039         }
3040         else {
3041                 if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED) {
3042                         tg3_setup_phy(tp);
3043                 }
3044         }
3045 }
3046
3047 /**************************************************************************
3048 POLL - Wait for a frame
3049 ***************************************************************************/
3050 static void tg3_ack_irqs(struct tg3 *tp)
3051 {
3052         if (tp->hw_status->status & SD_STATUS_UPDATED) {
3053                 /*
3054                  * writing any value to intr-mbox-0 clears PCI INTA# and
3055                  * chip-internal interrupt pending events.
3056                  * writing non-zero to intr-mbox-0 additional tells the
3057                  * NIC to stop sending us irqs, engaging "in-intr-handler"
3058                  * event coalescing.
3059                  */
3060                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 
3061                         0x00000001);
3062                 /*
3063                  * Flush PCI write.  This also guarantees that our
3064                  * status block has been flushed to host memory.
3065                  */
3066                 tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
3067                 tp->hw_status->status &= ~SD_STATUS_UPDATED;
3068         }
3069 }
3070
3071 static int tg3_poll(struct nic *nic, int retrieve)
3072 {
3073         /* return true if there's an ethernet packet ready to read */
3074         /* nic->packet should contain data on return */
3075         /* nic->packetlen should contain length of data */
3076
3077         struct tg3 *tp = &tg3;
3078         int result;
3079
3080         result = 0;
3081
3082         if ( (tp->hw_status->idx[0].rx_producer != tp->rx_rcb_ptr) && !retrieve ) 
3083           return 1;
3084
3085         tg3_ack_irqs(tp);
3086
3087         if (tp->hw_status->idx[0].rx_producer != tp->rx_rcb_ptr) {
3088                 struct tg3_rx_buffer_desc *desc;
3089                 unsigned int len;
3090                 desc = &tp->rx_rcb[tp->rx_rcb_ptr];
3091                 if ((desc->opaque & RXD_OPAQUE_RING_MASK) == RXD_OPAQUE_RING_STD) {
3092                         len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3093                         
3094                         nic->packetlen = len;
3095                         memcpy(nic->packet, bus_to_virt(desc->addr_lo), len);
3096                         result = 1;
3097                 }
3098                 tp->rx_rcb_ptr = (tp->rx_rcb_ptr + 1) % TG3_RX_RCB_RING_SIZE;
3099                 
3100                 /* ACK the status ring */
3101                 tw32_mailbox2(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, tp->rx_rcb_ptr);
3102
3103                 /* Refill RX ring. */
3104                 if (result) {
3105                         tp->rx_std_ptr = (tp->rx_std_ptr + 1) % TG3_RX_RING_SIZE;
3106                         tw32_mailbox2(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW, tp->rx_std_ptr);
3107                 }
3108         }
3109         tg3_poll_link(tp);
3110         return result;
3111 }
3112
3113 /**************************************************************************
3114 TRANSMIT - Transmit a frame
3115 ***************************************************************************/
3116 #if 0
3117 static void tg3_set_txd(struct tg3 *tp, int entry,
3118         dma_addr_t mapping, int len, uint32_t flags,
3119         uint32_t mss_and_is_end)
3120 {
3121         struct tg3_tx_buffer_desc *txd =  &tp->tx_ring[entry];
3122         int is_end = (mss_and_is_end & 0x1);
3123         if (is_end) {
3124                 flags |= TXD_FLAG_END;
3125         }
3126
3127         txd->addr_hi   = 0;
3128         txd->addr_lo   = mapping & 0xffffffff;
3129         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3130         txd->vlan_tag  = 0 << TXD_VLAN_TAG_SHIFT;
3131 }
3132 #endif
3133
3134 static void tg3_transmit(struct nic *nic, const char *dst_addr,
3135         unsigned int type, unsigned int size, const char *packet)
3136 {
3137         static int frame_idx;
3138         struct eth_frame *frame;
3139         
3140         /* send the packet to destination */
3141         struct tg3_tx_buffer_desc *txd;
3142         struct tg3 *tp;
3143         uint32_t entry;
3144         int i;
3145
3146         /* Wait until there is a free packet frame */
3147         tp = &tg3;
3148         i = 0;
3149         entry = tp->tx_prod;
3150         while((tp->hw_status->idx[0].tx_consumer != entry) &&
3151                 (tp->hw_status->idx[0].tx_consumer != PREV_TX(entry))) {
3152                 mdelay(10);     /* give the nick a chance */
3153                 poll_interruptions();
3154                 if (++i > 500) { /* timeout 5s for transmit */
3155                         printf("transmit timed out\n");
3156                         tg3_halt(tp);
3157                         tg3_setup_hw(tp);
3158                         return;
3159                 }
3160         }
3161         if (i != 0) {
3162                 printf("#");
3163         }
3164         
3165         /* Copy the packet to the our local buffer */
3166         frame = &tg3_bss.tx_frame[frame_idx];
3167         memcpy(frame[frame_idx].dst_addr, dst_addr, ETH_ALEN);
3168         memcpy(frame[frame_idx].src_addr, nic->node_addr, ETH_ALEN);
3169         frame[frame_idx].type = htons(type);
3170         memset(frame[frame_idx].data, 0, sizeof(frame[frame_idx].data));
3171         memcpy(frame[frame_idx].data, packet, size);
3172
3173         /* Setup the ring buffer entry to transmit */
3174         txd            = &tp->tx_ring[entry];
3175         txd->addr_hi   = 0; /* Etherboot runs under 4GB */
3176         txd->addr_lo   = virt_to_bus(&frame[frame_idx]);
3177         txd->len_flags = ((size + ETH_HLEN) << TXD_LEN_SHIFT) | TXD_FLAG_END;
3178         txd->vlan_tag  = 0 << TXD_VLAN_TAG_SHIFT;
3179
3180         /* Advance to the next entry */
3181         entry = NEXT_TX(entry);
3182         frame_idx ^= 1;
3183
3184         /* Packets are ready, update Tx producer idx local and on card */
3185         tw32_mailbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3186         tw32_mailbox2((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3187         tp->tx_prod = entry;
3188 }
3189
3190 /**************************************************************************
3191 DISABLE - Turn off ethernet interface
3192 ***************************************************************************/
3193 static void tg3_disable ( struct nic *nic __unused ) {
3194         struct tg3 *tp = &tg3;
3195         /* put the card in its initial state */
3196         /* This function serves 3 purposes.
3197          * This disables DMA and interrupts so we don't receive
3198          *  unexpected packets or interrupts from the card after
3199          *  etherboot has finished. 
3200          * This frees resources so etherboot may use
3201          *  this driver on another interface
3202          * This allows etherboot to reinitialize the interface
3203          *  if something is something goes wrong.
3204          */
3205         tg3_halt(tp);
3206         tp->tg3_flags &= ~(TG3_FLAG_INIT_COMPLETE|TG3_FLAG_GOT_SERDES_FLOWCTL);
3207         tp->carrier_ok = 0;
3208         iounmap((void *)tp->regs);
3209 }
3210
3211 /**************************************************************************
3212 IRQ - Enable, Disable, or Force interrupts
3213 ***************************************************************************/
3214 static void tg3_irq(struct nic *nic __unused, irq_action_t action __unused)
3215 {
3216   switch ( action ) {
3217   case DISABLE :
3218     break;
3219   case ENABLE :
3220     break;
3221   case FORCE :
3222     break;
3223   }
3224 }
3225
3226 static struct nic_operations tg3_operations = {
3227         .connect        = dummy_connect,
3228         .poll           = tg3_poll,
3229         .transmit       = tg3_transmit,
3230         .irq            = tg3_irq,
3231
3232 };
3233
3234 /**************************************************************************
3235 PROBE - Look for an adapter, this routine's visible to the outside
3236 You should omit the last argument struct pci_device * for a non-PCI NIC
3237 ***************************************************************************/
3238 static int tg3_probe ( struct nic *nic, struct pci_device *pdev ) {
3239
3240         struct tg3 *tp = &tg3;
3241         unsigned long tg3reg_base, tg3reg_len;
3242         int i, err, pm_cap;
3243
3244         memset(tp, 0, sizeof(*tp));
3245
3246         adjust_pci_device(pdev);
3247
3248         pci_fill_nic ( nic, pdev );
3249         nic->irqno  = 0;
3250
3251         /* Find power-management capability. */
3252         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3253         if (pm_cap == 0) {
3254                 printf("Cannot find PowerManagement capability, aborting.\n");
3255                 return 0;
3256         }
3257         tg3reg_base = pci_bar_start(pdev, PCI_BASE_ADDRESS_0);
3258         if (tg3reg_base == -1UL) {
3259                 printf("Unuseable bar\n");
3260                 return 0;
3261         }
3262         tg3reg_len  = pci_bar_size(pdev,  PCI_BASE_ADDRESS_0);
3263
3264         tp->pdev       = pdev;
3265         tp->nic        = nic;
3266         tp->pm_cap     = pm_cap;
3267         tp->rx_mode    = 0;
3268         tp->tx_mode    = 0;
3269         tp->mi_mode    = MAC_MI_MODE_BASE;
3270         tp->tg3_flags  = 0 & ~TG3_FLAG_INIT_COMPLETE; 
3271         
3272         /* The word/byte swap controls here control register access byte
3273          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
3274          * setting below.
3275          */
3276         tp->misc_host_ctrl =
3277                 MISC_HOST_CTRL_MASK_PCI_INT |
3278                 MISC_HOST_CTRL_WORD_SWAP |
3279                 MISC_HOST_CTRL_INDIR_ACCESS |
3280                 MISC_HOST_CTRL_PCISTATE_RW;
3281
3282         /* The NONFRM (non-frame) byte/word swap controls take effect
3283          * on descriptor entries, anything which isn't packet data.
3284          *
3285          * The StrongARM chips on the board (one for tx, one for rx)
3286          * are running in big-endian mode.
3287          */
3288         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
3289                         GRC_MODE_WSWAP_NONFRM_DATA);
3290 #if __BYTE_ORDER == __BIG_ENDIAN
3291         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
3292 #endif
3293         tp->regs = (unsigned long) ioremap(tg3reg_base, tg3reg_len);
3294         if (tp->regs == 0UL) {
3295                 printf("Cannot map device registers, aborting\n");
3296                 return 0;
3297         }
3298
3299         tg3_init_link_config(tp);
3300
3301         err = tg3_get_invariants(tp);
3302         if (err) {
3303                 printf("Problem fetching invariants of chip, aborting.\n");
3304                 goto err_out_iounmap;
3305         }
3306
3307         err = tg3_get_device_address(tp);
3308         if (err) {
3309                 printf("Could not obtain valid ethernet address, aborting.\n");
3310                 goto err_out_iounmap;
3311         }
3312         printf("Ethernet addr: %!\n", nic->node_addr);
3313
3314         tg3_setup_dma(tp);
3315
3316         /* Now that we have fully setup the chip, save away a snapshot
3317          * of the PCI config space.  We need to restore this after
3318          * GRC_MISC_CFG core clock resets and some resume events.
3319          */
3320         pci_save_state(tp->pdev, tp->pci_cfg_state);
3321
3322         printf("Tigon3 [partno(%s) rev %hx PHY(%s)] (PCI%s:%s:%s)\n",
3323                 tp->board_part_number,
3324                 tp->pci_chip_rev_id,
3325                 tg3_phy_string(tp),
3326                 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "X" : ""),
3327                 ((tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED) ?
3328                         ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "133MHz" : "66MHz") :
3329                         ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "100MHz" : "33MHz")),
3330                 ((tp->tg3_flags & TG3_FLAG_PCI_32BIT) ? "32-bit" : "64-bit"));
3331
3332
3333         err = tg3_setup_hw(tp); 
3334         if (err) {
3335                 goto err_out_disable;
3336         } 
3337         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
3338
3339         /* Wait for a reasonable time for the link to come up */
3340         tg3_poll_link(tp);
3341         for(i = 0; !tp->carrier_ok && (i < VALID_LINK_TIMEOUT*100); i++) {
3342                 mdelay(1);
3343                 tg3_poll_link(tp);
3344         }
3345         if (!tp->carrier_ok){
3346                 printf("Valid link not established\n");
3347                 goto err_out_disable;
3348         }
3349
3350         nic->nic_op     = &tg3_operations;
3351         return 1;
3352
3353  err_out_iounmap:
3354         iounmap((void *)tp->regs);
3355         return 0;
3356  err_out_disable:
3357         tg3_disable(nic);
3358         return 0;
3359 }
3360
3361
3362 static struct pci_id tg3_nics[] = {
3363 PCI_ROM(0x14e4, 0x1644, "tg3-5700",        "Broadcom Tigon 3 5700"),
3364 PCI_ROM(0x14e4, 0x1645, "tg3-5701",        "Broadcom Tigon 3 5701"),
3365 PCI_ROM(0x14e4, 0x1646, "tg3-5702",        "Broadcom Tigon 3 5702"),
3366 PCI_ROM(0x14e4, 0x1647, "tg3-5703",        "Broadcom Tigon 3 5703"),
3367 PCI_ROM(0x14e4, 0x1648, "tg3-5704",        "Broadcom Tigon 3 5704"),
3368 PCI_ROM(0x14e4, 0x164d, "tg3-5702FE",      "Broadcom Tigon 3 5702FE"),
3369 PCI_ROM(0x14e4, 0x1653, "tg3-5705",        "Broadcom Tigon 3 5705"),
3370 PCI_ROM(0x14e4, 0x1654, "tg3-5705_2",      "Broadcom Tigon 3 5705_2"),
3371 PCI_ROM(0x14e4, 0x165d, "tg3-5705M",       "Broadcom Tigon 3 5705M"),
3372 PCI_ROM(0x14e4, 0x165e, "tg3-5705M_2",     "Broadcom Tigon 3 5705M_2"),
3373 PCI_ROM(0x14e4, 0x1677, "tg3-5751",        "Broadcom Tigon 3 5751"),
3374 PCI_ROM(0x14e4, 0x1696, "tg3-5782",        "Broadcom Tigon 3 5782"),
3375 PCI_ROM(0x14e4, 0x169c, "tg3-5788",        "Broadcom Tigon 3 5788"),
3376 PCI_ROM(0x14e4, 0x16a6, "tg3-5702X",       "Broadcom Tigon 3 5702X"),
3377 PCI_ROM(0x14e4, 0x16a7, "tg3-5703X",       "Broadcom Tigon 3 5703X"),
3378 PCI_ROM(0x14e4, 0x16a8, "tg3-5704S",       "Broadcom Tigon 3 5704S"),
3379 PCI_ROM(0x14e4, 0x16c6, "tg3-5702A3",      "Broadcom Tigon 3 5702A3"),
3380 PCI_ROM(0x14e4, 0x16c7, "tg3-5703A3",      "Broadcom Tigon 3 5703A3"),
3381 PCI_ROM(0x14e4, 0x170d, "tg3-5901",        "Broadcom Tigon 3 5901"),
3382 PCI_ROM(0x14e4, 0x170e, "tg3-5901_2",      "Broadcom Tigon 3 5901_2"),
3383 PCI_ROM(0x1148, 0x4400, "tg3-9DXX",        "Syskonnect 9DXX"),
3384 PCI_ROM(0x1148, 0x4500, "tg3-9MXX",        "Syskonnect 9MXX"),
3385 PCI_ROM(0x173b, 0x03e8, "tg3-ac1000",      "Altima AC1000"),
3386 PCI_ROM(0x173b, 0x03e9, "tg3-ac1001",      "Altima AC1001"),
3387 PCI_ROM(0x173b, 0x03ea, "tg3-ac9100",      "Altima AC9100"),
3388 PCI_ROM(0x173b, 0x03eb, "tg3-ac1003",      "Altima AC1003"),
3389 };
3390
3391 PCI_DRIVER ( tg3_driver, tg3_nics, PCI_NO_CLASS );
3392
3393 DRIVER ( "TG3", nic_driver, pci_driver, tg3_driver,
3394          tg3_probe, tg3_disable );