Ported bnx2 driver from Etherboot 5.4.
[people/lynusvaz/gpxe.git] / src / drivers / net / bnx2.c
1 /* bnx2.c: Broadcom NX2 network driver.
2  *
3  * Copyright (c) 2004, 2005, 2006 Broadcom Corporation
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation.
8  *
9  * Written by: Michael Chan  (mchan@broadcom.com)
10  *
11  * Etherboot port by Ryan Jackson (rjackson@lnxi.com), based on driver
12  * version 1.4.40 from linux 2.6.17
13  */
14
15
16 #include "etherboot.h"
17 #include "nic.h"
18 #include <gpxe/pci.h>
19 #include <gpxe/ethernet.h>
20 #include "timer.h"
21 #include "string.h"
22 #include "bnx2.h"
23 #include "bnx2_fw.h"
24
25 /* Dummy defines for error handling */
26 #define EBUSY  1
27 #define ENODEV 2
28 #define EINVAL 3
29 #define ENOMEM 4
30 #define EIO    5
31
32 /* The bnx2 seems to be picky about the alignment of the receive buffers
33  * and possibly the status block.
34  */
35 static struct bss {
36         struct tx_bd tx_desc_ring[TX_DESC_CNT];
37         struct rx_bd rx_desc_ring[RX_DESC_CNT];
38         unsigned char rx_buf[RX_BUF_CNT][RX_BUF_SIZE];
39         struct status_block status_blk;
40         struct statistics_block stats_blk;
41 } bnx2_bss;
42
43 struct bnx2 bnx2;
44
45 static struct flash_spec flash_table[] =
46 {
47         /* Slow EEPROM */
48         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
49          1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
50          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
51          "EEPROM - slow"},
52         /* Expansion entry 0001 */
53         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
54          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
55          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
56          "Entry 0001"},
57         /* Saifun SA25F010 (non-buffered flash) */
58         /* strap, cfg1, & write1 need updates */
59         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
60          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
61          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
62          "Non-buffered flash (128kB)"},
63         /* Saifun SA25F020 (non-buffered flash) */
64         /* strap, cfg1, & write1 need updates */
65         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
66          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
67          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
68          "Non-buffered flash (256kB)"},
69         /* Expansion entry 0100 */
70         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
71          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
72          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
73          "Entry 0100"},
74         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
75         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,        
76          0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
77          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
78          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
79         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
80         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
81          0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
82          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
83          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
84         /* Saifun SA25F005 (non-buffered flash) */
85         /* strap, cfg1, & write1 need updates */
86         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
87          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
88          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
89          "Non-buffered flash (64kB)"},
90         /* Fast EEPROM */
91         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
92          1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
93          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
94          "EEPROM - fast"},
95         /* Expansion entry 1001 */
96         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
97          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
98          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
99          "Entry 1001"},
100         /* Expansion entry 1010 */
101         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
102          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
103          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
104          "Entry 1010"},
105         /* ATMEL AT45DB011B (buffered flash) */
106         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
107          1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
108          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
109          "Buffered flash (128kB)"},
110         /* Expansion entry 1100 */
111         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
112          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
113          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
114          "Entry 1100"},
115         /* Expansion entry 1101 */
116         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
117          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
118          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
119          "Entry 1101"},
120         /* Ateml Expansion entry 1110 */
121         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
122          1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
123          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
124          "Entry 1110 (Atmel)"},
125         /* ATMEL AT45DB021B (buffered flash) */
126         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
127          1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
128          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
129          "Buffered flash (256kB)"},
130 };
131
132 static u32
133 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
134 {
135         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
136         return (REG_RD(bp, BNX2_PCICFG_REG_WINDOW));
137 }
138
139 static void
140 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
141 {
142         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
143         REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
144 }
145
146 static void
147 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
148 {
149         offset += cid_addr;
150         REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
151         REG_WR(bp, BNX2_CTX_DATA, val);
152 }
153
154 static int
155 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
156 {
157         u32 val1;
158         int i, ret;
159
160         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
161                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
162                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
163
164                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
165                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
166
167                 udelay(40);
168         }
169
170         val1 = (bp->phy_addr << 21) | (reg << 16) |
171                 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
172                 BNX2_EMAC_MDIO_COMM_START_BUSY;
173         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
174
175         for (i = 0; i < 50; i++) {
176                 udelay(10);
177
178                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
179                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
180                         udelay(5);
181
182                         val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
183                         val1 &= BNX2_EMAC_MDIO_COMM_DATA;
184
185                         break;
186                 }
187         }
188
189         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
190                 *val = 0x0;
191                 ret = -EBUSY;
192         }
193         else {
194                 *val = val1;
195                 ret = 0;
196         }
197
198         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
199                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
200                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
201
202                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
203                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
204
205                 udelay(40);
206         }
207
208         return ret;
209 }
210
211 static int
212 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
213 {
214         u32 val1;
215         int i, ret;
216
217         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
218                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
219                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
220
221                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
222                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
223
224                 udelay(40);
225         }
226
227         val1 = (bp->phy_addr << 21) | (reg << 16) | val |
228                 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
229                 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
230         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
231     
232         for (i = 0; i < 50; i++) {
233                 udelay(10);
234
235                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
236                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
237                         udelay(5);
238                         break;
239                 }
240         }
241
242         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
243                 ret = -EBUSY;
244         else
245                 ret = 0;
246
247         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
248                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
249                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
250
251                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
252                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
253
254                 udelay(40);
255         }
256
257         return ret;
258 }
259
260 static void
261 bnx2_disable_int(struct bnx2 *bp)
262 {
263         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
264                BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
265         REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
266
267 }
268
269 static int
270 bnx2_alloc_mem(struct bnx2 *bp)
271 {
272         bp->tx_desc_ring = bnx2_bss.tx_desc_ring;
273         bp->tx_desc_mapping = virt_to_bus(bp->tx_desc_ring);
274
275         bp->rx_desc_ring = bnx2_bss.rx_desc_ring;
276         memset(bp->rx_desc_ring, 0, sizeof(struct rx_bd) * RX_DESC_CNT);
277         bp->rx_desc_mapping = virt_to_bus(bp->rx_desc_ring);
278
279         memset(&bnx2_bss.status_blk, 0, sizeof(struct status_block));
280         bp->status_blk = &bnx2_bss.status_blk;
281         bp->status_blk_mapping = virt_to_bus(&bnx2_bss.status_blk);
282
283         bp->stats_blk = &bnx2_bss.stats_blk;
284         memset(&bnx2_bss.stats_blk, 0, sizeof(struct statistics_block));
285         bp->stats_blk_mapping = virt_to_bus(&bnx2_bss.stats_blk);
286
287         return 0;
288 }
289
290 static void
291 bnx2_report_fw_link(struct bnx2 *bp)
292 {
293         u32 fw_link_status = 0;
294
295         if (bp->link_up) {
296                 u32 bmsr;
297
298                 switch (bp->line_speed) {
299                 case SPEED_10:
300                         if (bp->duplex == DUPLEX_HALF)
301                                 fw_link_status = BNX2_LINK_STATUS_10HALF;
302                         else
303                                 fw_link_status = BNX2_LINK_STATUS_10FULL;
304                         break;
305                 case SPEED_100:
306                         if (bp->duplex == DUPLEX_HALF)
307                                 fw_link_status = BNX2_LINK_STATUS_100HALF;
308                         else
309                                 fw_link_status = BNX2_LINK_STATUS_100FULL;
310                         break;
311                 case SPEED_1000:
312                         if (bp->duplex == DUPLEX_HALF)
313                                 fw_link_status = BNX2_LINK_STATUS_1000HALF;
314                         else
315                                 fw_link_status = BNX2_LINK_STATUS_1000FULL;
316                         break;
317                 case SPEED_2500:
318                         if (bp->duplex == DUPLEX_HALF)
319                                 fw_link_status = BNX2_LINK_STATUS_2500HALF;
320                         else
321                                 fw_link_status = BNX2_LINK_STATUS_2500FULL;
322                         break;
323                 }
324
325                 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
326
327                 if (bp->autoneg) {
328                         fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
329
330                         bnx2_read_phy(bp, MII_BMSR, &bmsr);
331                         bnx2_read_phy(bp, MII_BMSR, &bmsr);
332
333                         if (!(bmsr & BMSR_ANEGCOMPLETE) ||
334                             bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)
335                                 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
336                         else
337                                 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
338                 }
339         }
340         else
341                 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
342
343         REG_WR_IND(bp, bp->shmem_base + BNX2_LINK_STATUS, fw_link_status);
344 }
345
346 static void
347 bnx2_report_link(struct bnx2 *bp)
348 {
349         if (bp->link_up) {
350                 printf("NIC Link is Up, ");
351
352                 printf("%d Mbps ", bp->line_speed);
353
354                 if (bp->duplex == DUPLEX_FULL)
355                         printf("full duplex");
356                 else
357                         printf("half duplex");
358
359                 if (bp->flow_ctrl) {
360                         if (bp->flow_ctrl & FLOW_CTRL_RX) {
361                                 printf(", receive ");
362                                 if (bp->flow_ctrl & FLOW_CTRL_TX)
363                                         printf("& transmit ");
364                         }
365                         else {
366                                 printf(", transmit ");
367                         }
368                         printf("flow control ON");
369                 }
370                 printf("\n");
371         }
372         else {
373                 printf("NIC Link is Down\n");
374         }
375
376         bnx2_report_fw_link(bp);
377 }
378
379 static void
380 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
381 {
382         u32 local_adv, remote_adv;
383
384         bp->flow_ctrl = 0;
385         if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) != 
386                 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
387
388                 if (bp->duplex == DUPLEX_FULL) {
389                         bp->flow_ctrl = bp->req_flow_ctrl;
390                 }
391                 return;
392         }
393
394         if (bp->duplex != DUPLEX_FULL) {
395                 return;
396         }
397
398         if ((bp->phy_flags & PHY_SERDES_FLAG) &&
399             (CHIP_NUM(bp) == CHIP_NUM_5708)) {
400                 u32 val;
401
402                 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
403                 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
404                         bp->flow_ctrl |= FLOW_CTRL_TX;
405                 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
406                         bp->flow_ctrl |= FLOW_CTRL_RX;
407                 return;
408         }
409
410         bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
411         bnx2_read_phy(bp, MII_LPA, &remote_adv);
412
413         if (bp->phy_flags & PHY_SERDES_FLAG) {
414                 u32 new_local_adv = 0;
415                 u32 new_remote_adv = 0;
416
417                 if (local_adv & ADVERTISE_1000XPAUSE)
418                         new_local_adv |= ADVERTISE_PAUSE_CAP;
419                 if (local_adv & ADVERTISE_1000XPSE_ASYM)
420                         new_local_adv |= ADVERTISE_PAUSE_ASYM;
421                 if (remote_adv & ADVERTISE_1000XPAUSE)
422                         new_remote_adv |= ADVERTISE_PAUSE_CAP;
423                 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
424                         new_remote_adv |= ADVERTISE_PAUSE_ASYM;
425
426                 local_adv = new_local_adv;
427                 remote_adv = new_remote_adv;
428         }
429
430         /* See Table 28B-3 of 802.3ab-1999 spec. */
431         if (local_adv & ADVERTISE_PAUSE_CAP) {
432                 if(local_adv & ADVERTISE_PAUSE_ASYM) {
433                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
434                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
435                         }
436                         else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
437                                 bp->flow_ctrl = FLOW_CTRL_RX;
438                         }
439                 }
440                 else {
441                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
442                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
443                         }
444                 }
445         }
446         else if (local_adv & ADVERTISE_PAUSE_ASYM) {
447                 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
448                         (remote_adv & ADVERTISE_PAUSE_ASYM)) {
449
450                         bp->flow_ctrl = FLOW_CTRL_TX;
451                 }
452         }
453 }
454
455 static int
456 bnx2_5708s_linkup(struct bnx2 *bp)
457 {
458         u32 val;
459
460         bp->link_up = 1;
461         bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
462         switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
463                 case BCM5708S_1000X_STAT1_SPEED_10:
464                         bp->line_speed = SPEED_10;
465                         break;
466                 case BCM5708S_1000X_STAT1_SPEED_100:
467                         bp->line_speed = SPEED_100;
468                         break;
469                 case BCM5708S_1000X_STAT1_SPEED_1G:
470                         bp->line_speed = SPEED_1000;
471                         break;
472                 case BCM5708S_1000X_STAT1_SPEED_2G5:
473                         bp->line_speed = SPEED_2500;
474                         break;
475         }
476         if (val & BCM5708S_1000X_STAT1_FD)
477                 bp->duplex = DUPLEX_FULL;
478         else
479                 bp->duplex = DUPLEX_HALF;
480
481         return 0;
482 }
483
484 static int
485 bnx2_5706s_linkup(struct bnx2 *bp)
486 {
487         u32 bmcr, local_adv, remote_adv, common;
488
489         bp->link_up = 1;
490         bp->line_speed = SPEED_1000;
491
492         bnx2_read_phy(bp, MII_BMCR, &bmcr);
493         if (bmcr & BMCR_FULLDPLX) {
494                 bp->duplex = DUPLEX_FULL;
495         }
496         else {
497                 bp->duplex = DUPLEX_HALF;
498         }
499
500         if (!(bmcr & BMCR_ANENABLE)) {
501                 return 0;
502         }
503
504         bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
505         bnx2_read_phy(bp, MII_LPA, &remote_adv);
506
507         common = local_adv & remote_adv;
508         if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
509
510                 if (common & ADVERTISE_1000XFULL) {
511                         bp->duplex = DUPLEX_FULL;
512                 }
513                 else {
514                         bp->duplex = DUPLEX_HALF;
515                 }
516         }
517
518         return 0;
519 }
520
521 static int
522 bnx2_copper_linkup(struct bnx2 *bp)
523 {
524         u32 bmcr;
525
526         bnx2_read_phy(bp, MII_BMCR, &bmcr);
527         if (bmcr & BMCR_ANENABLE) {
528                 u32 local_adv, remote_adv, common;
529
530                 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
531                 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
532
533                 common = local_adv & (remote_adv >> 2);
534                 if (common & ADVERTISE_1000FULL) {
535                         bp->line_speed = SPEED_1000;
536                         bp->duplex = DUPLEX_FULL;
537                 }
538                 else if (common & ADVERTISE_1000HALF) {
539                         bp->line_speed = SPEED_1000;
540                         bp->duplex = DUPLEX_HALF;
541                 }
542                 else {
543                         bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
544                         bnx2_read_phy(bp, MII_LPA, &remote_adv);
545
546                         common = local_adv & remote_adv;
547                         if (common & ADVERTISE_100FULL) {
548                                 bp->line_speed = SPEED_100;
549                                 bp->duplex = DUPLEX_FULL;
550                         }
551                         else if (common & ADVERTISE_100HALF) {
552                                 bp->line_speed = SPEED_100;
553                                 bp->duplex = DUPLEX_HALF;
554                         }
555                         else if (common & ADVERTISE_10FULL) {
556                                 bp->line_speed = SPEED_10;
557                                 bp->duplex = DUPLEX_FULL;
558                         }
559                         else if (common & ADVERTISE_10HALF) {
560                                 bp->line_speed = SPEED_10;
561                                 bp->duplex = DUPLEX_HALF;
562                         }
563                         else {
564                                 bp->line_speed = 0;
565                                 bp->link_up = 0;
566                         }
567                 }
568         }
569         else {
570                 if (bmcr & BMCR_SPEED100) {
571                         bp->line_speed = SPEED_100;
572                 }
573                 else {
574                         bp->line_speed = SPEED_10;
575                 }
576                 if (bmcr & BMCR_FULLDPLX) {
577                         bp->duplex = DUPLEX_FULL;
578                 }
579                 else {
580                         bp->duplex = DUPLEX_HALF;
581                 }
582         }
583
584         return 0;
585 }
586
587 static int
588 bnx2_set_mac_link(struct bnx2 *bp)
589 {
590         u32 val;
591
592         REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
593         if (bp->link_up && (bp->line_speed == SPEED_1000) &&
594                 (bp->duplex == DUPLEX_HALF)) {
595                 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
596         }
597
598         /* Configure the EMAC mode register. */
599         val = REG_RD(bp, BNX2_EMAC_MODE);
600
601         val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
602                 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
603                 BNX2_EMAC_MODE_25G);
604
605         if (bp->link_up) {
606                 switch (bp->line_speed) {
607                         case SPEED_10:
608                                 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
609                                         val |= BNX2_EMAC_MODE_PORT_MII_10;
610                                         break;
611                                 }
612                                 /* fall through */
613                         case SPEED_100:
614                                 val |= BNX2_EMAC_MODE_PORT_MII;
615                                 break;
616                         case SPEED_2500:
617                                 val |= BNX2_EMAC_MODE_25G;
618                                 /* fall through */
619                         case SPEED_1000:
620                                 val |= BNX2_EMAC_MODE_PORT_GMII;
621                                 break;
622                 }
623         }
624         else {
625                 val |= BNX2_EMAC_MODE_PORT_GMII;
626         }
627
628         /* Set the MAC to operate in the appropriate duplex mode. */
629         if (bp->duplex == DUPLEX_HALF)
630                 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
631         REG_WR(bp, BNX2_EMAC_MODE, val);
632
633         /* Enable/disable rx PAUSE. */
634         bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
635
636         if (bp->flow_ctrl & FLOW_CTRL_RX)
637                 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
638         REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
639
640         /* Enable/disable tx PAUSE. */
641         val = REG_RD(bp, BNX2_EMAC_TX_MODE);
642         val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
643
644         if (bp->flow_ctrl & FLOW_CTRL_TX)
645                 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
646         REG_WR(bp, BNX2_EMAC_TX_MODE, val);
647
648         /* Acknowledge the interrupt. */
649         REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
650
651         return 0;
652 }
653
654 static int
655 bnx2_set_link(struct bnx2 *bp)
656 {
657         u32 bmsr;
658         u8 link_up;
659
660         if (bp->loopback == MAC_LOOPBACK) {
661                 bp->link_up = 1;
662                 return 0;
663         }
664
665         link_up = bp->link_up;
666
667         bnx2_read_phy(bp, MII_BMSR, &bmsr);
668         bnx2_read_phy(bp, MII_BMSR, &bmsr);
669
670         if ((bp->phy_flags & PHY_SERDES_FLAG) &&
671             (CHIP_NUM(bp) == CHIP_NUM_5706)) {
672                 u32 val;
673
674                 val = REG_RD(bp, BNX2_EMAC_STATUS);
675                 if (val & BNX2_EMAC_STATUS_LINK)
676                         bmsr |= BMSR_LSTATUS;
677                 else
678                         bmsr &= ~BMSR_LSTATUS;
679         }
680
681         if (bmsr & BMSR_LSTATUS) {
682                 bp->link_up = 1;
683
684                 if (bp->phy_flags & PHY_SERDES_FLAG) {
685                         if (CHIP_NUM(bp) == CHIP_NUM_5706)
686                                 bnx2_5706s_linkup(bp);
687                         else if (CHIP_NUM(bp) == CHIP_NUM_5708)
688                                 bnx2_5708s_linkup(bp);
689                 }
690                 else {
691                         bnx2_copper_linkup(bp);
692                 }
693                 bnx2_resolve_flow_ctrl(bp);
694         }
695         else {
696                 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
697                         (bp->autoneg & AUTONEG_SPEED)) {
698
699                         u32 bmcr;
700
701                         bnx2_read_phy(bp, MII_BMCR, &bmcr);
702                         if (!(bmcr & BMCR_ANENABLE)) {
703                                 bnx2_write_phy(bp, MII_BMCR, bmcr |
704                                         BMCR_ANENABLE);
705                         }
706                 }
707                 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
708                 bp->link_up = 0;
709         }
710
711         if (bp->link_up != link_up) {
712                 bnx2_report_link(bp);
713         }
714
715         bnx2_set_mac_link(bp);
716
717         return 0;
718 }
719
720 static int
721 bnx2_reset_phy(struct bnx2 *bp)
722 {
723         int i;
724         u32 reg;
725
726         bnx2_write_phy(bp, MII_BMCR, BMCR_RESET);
727
728 #define PHY_RESET_MAX_WAIT 100
729         for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
730                 udelay(10);
731
732                 bnx2_read_phy(bp, MII_BMCR, &reg);
733                 if (!(reg & BMCR_RESET)) {
734                         udelay(20);
735                         break;
736                 }
737         }
738         if (i == PHY_RESET_MAX_WAIT) {
739                 return -EBUSY;
740         }
741         return 0;
742 }
743
744 static u32
745 bnx2_phy_get_pause_adv(struct bnx2 *bp)
746 {
747         u32 adv = 0;
748
749         if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
750                 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
751
752                 if (bp->phy_flags & PHY_SERDES_FLAG) {
753                         adv = ADVERTISE_1000XPAUSE;
754                 }
755                 else {
756                         adv = ADVERTISE_PAUSE_CAP;
757                 }
758         }
759         else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
760                 if (bp->phy_flags & PHY_SERDES_FLAG) {
761                         adv = ADVERTISE_1000XPSE_ASYM;
762                 }
763                 else {
764                         adv = ADVERTISE_PAUSE_ASYM;
765                 }
766         }
767         else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
768                 if (bp->phy_flags & PHY_SERDES_FLAG) {
769                         adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
770                 }
771                 else {
772                         adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
773                 }
774         }
775         return adv;
776 }
777
778 static int
779 bnx2_setup_serdes_phy(struct bnx2 *bp)
780 {
781         u32 adv, bmcr, up1;
782         u32 new_adv = 0;
783
784         if (!(bp->autoneg & AUTONEG_SPEED)) {
785                 u32 new_bmcr;
786                 int force_link_down = 0;
787
788                 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
789                         bnx2_read_phy(bp, BCM5708S_UP1, &up1);
790                         if (up1 & BCM5708S_UP1_2G5) {
791                                 up1 &= ~BCM5708S_UP1_2G5;
792                                 bnx2_write_phy(bp, BCM5708S_UP1, up1);
793                                 force_link_down = 1;
794                         }
795                 }
796
797                 bnx2_read_phy(bp, MII_ADVERTISE, &adv);
798                 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
799
800                 bnx2_read_phy(bp, MII_BMCR, &bmcr);
801                 new_bmcr = bmcr & ~BMCR_ANENABLE;
802                 new_bmcr |= BMCR_SPEED1000;
803                 if (bp->req_duplex == DUPLEX_FULL) {
804                         adv |= ADVERTISE_1000XFULL;
805                         new_bmcr |= BMCR_FULLDPLX;
806                 }
807                 else {
808                         adv |= ADVERTISE_1000XHALF;
809                         new_bmcr &= ~BMCR_FULLDPLX;
810                 }
811                 if ((new_bmcr != bmcr) || (force_link_down)) {
812                         /* Force a link down visible on the other side */
813                         if (bp->link_up) {
814                                 bnx2_write_phy(bp, MII_ADVERTISE, adv &
815                                                ~(ADVERTISE_1000XFULL |
816                                                  ADVERTISE_1000XHALF));
817                                 bnx2_write_phy(bp, MII_BMCR, bmcr |
818                                         BMCR_ANRESTART | BMCR_ANENABLE);
819
820                                 bp->link_up = 0;
821                                 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
822                         }
823                         bnx2_write_phy(bp, MII_ADVERTISE, adv);
824                         bnx2_write_phy(bp, MII_BMCR, new_bmcr);
825                 }
826                 return 0;
827         }
828
829         if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
830                 bnx2_read_phy(bp, BCM5708S_UP1, &up1);
831                 up1 |= BCM5708S_UP1_2G5;
832                 bnx2_write_phy(bp, BCM5708S_UP1, up1);
833         }
834
835         if (bp->advertising & ADVERTISED_1000baseT_Full)
836                 new_adv |= ADVERTISE_1000XFULL;
837
838         new_adv |= bnx2_phy_get_pause_adv(bp);
839
840         bnx2_read_phy(bp, MII_ADVERTISE, &adv);
841         bnx2_read_phy(bp, MII_BMCR, &bmcr);
842
843         bp->serdes_an_pending = 0;
844         if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
845                 /* Force a link down visible on the other side */
846                 if (bp->link_up) {
847                         int i;
848
849                         bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
850                         for (i = 0; i < 110; i++) {
851                                 udelay(100);
852                         }
853                 }
854
855                 bnx2_write_phy(bp, MII_ADVERTISE, new_adv);
856                 bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART |
857                         BMCR_ANENABLE);
858 #if 0
859                 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
860                         /* Speed up link-up time when the link partner
861                          * does not autonegotiate which is very common
862                          * in blade servers. Some blade servers use
863                          * IPMI for kerboard input and it's important
864                          * to minimize link disruptions. Autoneg. involves
865                          * exchanging base pages plus 3 next pages and
866                          * normally completes in about 120 msec.
867                          */
868                         bp->current_interval = SERDES_AN_TIMEOUT;
869                         bp->serdes_an_pending = 1;
870                         mod_timer(&bp->timer, jiffies + bp->current_interval);
871                 }
872 #endif
873         }
874
875         return 0;
876 }
877
878 #define ETHTOOL_ALL_FIBRE_SPEED                                         \
879         (ADVERTISED_1000baseT_Full)
880
881 #define ETHTOOL_ALL_COPPER_SPEED                                        \
882         (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |            \
883         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |           \
884         ADVERTISED_1000baseT_Full)
885
886 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
887         ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
888         
889 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
890
891 static int
892 bnx2_setup_copper_phy(struct bnx2 *bp)
893 {
894         u32 bmcr;
895         u32 new_bmcr;
896
897         bnx2_read_phy(bp, MII_BMCR, &bmcr);
898
899         if (bp->autoneg & AUTONEG_SPEED) {
900                 u32 adv_reg, adv1000_reg;
901                 u32 new_adv_reg = 0;
902                 u32 new_adv1000_reg = 0;
903
904                 bnx2_read_phy(bp, MII_ADVERTISE, &adv_reg);
905                 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
906                         ADVERTISE_PAUSE_ASYM);
907
908                 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
909                 adv1000_reg &= PHY_ALL_1000_SPEED;
910
911                 if (bp->advertising & ADVERTISED_10baseT_Half)
912                         new_adv_reg |= ADVERTISE_10HALF;
913                 if (bp->advertising & ADVERTISED_10baseT_Full)
914                         new_adv_reg |= ADVERTISE_10FULL;
915                 if (bp->advertising & ADVERTISED_100baseT_Half)
916                         new_adv_reg |= ADVERTISE_100HALF;
917                 if (bp->advertising & ADVERTISED_100baseT_Full)
918                         new_adv_reg |= ADVERTISE_100FULL;
919                 if (bp->advertising & ADVERTISED_1000baseT_Full)
920                         new_adv1000_reg |= ADVERTISE_1000FULL;
921                 
922                 new_adv_reg |= ADVERTISE_CSMA;
923
924                 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
925
926                 if ((adv1000_reg != new_adv1000_reg) ||
927                         (adv_reg != new_adv_reg) ||
928                         ((bmcr & BMCR_ANENABLE) == 0)) {
929
930                         bnx2_write_phy(bp, MII_ADVERTISE, new_adv_reg);
931                         bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
932                         bnx2_write_phy(bp, MII_BMCR, BMCR_ANRESTART |
933                                 BMCR_ANENABLE);
934                 }
935                 else if (bp->link_up) {
936                         /* Flow ctrl may have changed from auto to forced */
937                         /* or vice-versa. */
938
939                         bnx2_resolve_flow_ctrl(bp);
940                         bnx2_set_mac_link(bp);
941                 }
942                 return 0;
943         }
944
945         new_bmcr = 0;
946         if (bp->req_line_speed == SPEED_100) {
947                 new_bmcr |= BMCR_SPEED100;
948         }
949         if (bp->req_duplex == DUPLEX_FULL) {
950                 new_bmcr |= BMCR_FULLDPLX;
951         }
952         if (new_bmcr != bmcr) {
953                 u32 bmsr;
954                 int i = 0;
955
956                 bnx2_read_phy(bp, MII_BMSR, &bmsr);
957                 bnx2_read_phy(bp, MII_BMSR, &bmsr);
958                 
959                 if (bmsr & BMSR_LSTATUS) {
960                         /* Force link down */
961                         bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
962                         do {
963                                 udelay(100);
964                                 bnx2_read_phy(bp, MII_BMSR, &bmsr);
965                                 bnx2_read_phy(bp, MII_BMSR, &bmsr);
966                                 i++;
967                         } while ((bmsr & BMSR_LSTATUS) && (i < 620));
968                 }
969
970                 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
971
972                 /* Normally, the new speed is setup after the link has
973                  * gone down and up again. In some cases, link will not go
974                  * down so we need to set up the new speed here.
975                  */
976                 if (bmsr & BMSR_LSTATUS) {
977                         bp->line_speed = bp->req_line_speed;
978                         bp->duplex = bp->req_duplex;
979                         bnx2_resolve_flow_ctrl(bp);
980                         bnx2_set_mac_link(bp);
981                 }
982         }
983         return 0;
984 }
985
986 static int
987 bnx2_setup_phy(struct bnx2 *bp)
988 {
989         if (bp->loopback == MAC_LOOPBACK)
990                 return 0;
991
992         if (bp->phy_flags & PHY_SERDES_FLAG) {
993                 return (bnx2_setup_serdes_phy(bp));
994         }
995         else {
996                 return (bnx2_setup_copper_phy(bp));
997         }
998 }
999
1000 static int
1001 bnx2_init_5708s_phy(struct bnx2 *bp)
1002 {
1003         u32 val;
1004
1005         bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
1006         bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
1007         bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1008
1009         bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
1010         val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
1011         bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
1012
1013         bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
1014         val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
1015         bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
1016
1017         if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
1018                 bnx2_read_phy(bp, BCM5708S_UP1, &val);
1019                 val |= BCM5708S_UP1_2G5;
1020                 bnx2_write_phy(bp, BCM5708S_UP1, val);
1021         }
1022
1023         if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
1024             (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
1025             (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
1026                 /* increase tx signal amplitude */
1027                 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1028                                BCM5708S_BLK_ADDR_TX_MISC);
1029                 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
1030                 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
1031                 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
1032                 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1033         }
1034
1035         val = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG) &
1036               BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
1037
1038         if (val) {
1039                 u32 is_backplane;
1040
1041                 is_backplane = REG_RD_IND(bp, bp->shmem_base +
1042                                           BNX2_SHARED_HW_CFG_CONFIG);
1043                 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
1044                         bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1045                                        BCM5708S_BLK_ADDR_TX_MISC);
1046                         bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
1047                         bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1048                                        BCM5708S_BLK_ADDR_DIG);
1049                 }
1050         }
1051         return 0;
1052 }
1053
1054 static int
1055 bnx2_init_5706s_phy(struct bnx2 *bp)
1056 {
1057         u32 val;
1058
1059         bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
1060
1061         if (CHIP_NUM(bp) == CHIP_NUM_5706) {
1062                 REG_WR(bp, BNX2_MISC_UNUSED0, 0x300);
1063         }
1064
1065
1066         bnx2_write_phy(bp, 0x18, 0x7);
1067         bnx2_read_phy(bp, 0x18, &val);
1068         bnx2_write_phy(bp, 0x18, val & ~0x4007);
1069
1070         bnx2_write_phy(bp, 0x1c, 0x6c00);
1071         bnx2_read_phy(bp, 0x1c, &val);
1072         bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
1073
1074         return 0;
1075 }
1076
1077 static int
1078 bnx2_init_copper_phy(struct bnx2 *bp)
1079 {
1080         u32 val;
1081
1082         bp->phy_flags |= PHY_CRC_FIX_FLAG;
1083
1084         if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
1085                 bnx2_write_phy(bp, 0x18, 0x0c00);
1086                 bnx2_write_phy(bp, 0x17, 0x000a);
1087                 bnx2_write_phy(bp, 0x15, 0x310b);
1088                 bnx2_write_phy(bp, 0x17, 0x201f);
1089                 bnx2_write_phy(bp, 0x15, 0x9506);
1090                 bnx2_write_phy(bp, 0x17, 0x401f);
1091                 bnx2_write_phy(bp, 0x15, 0x14e2);
1092                 bnx2_write_phy(bp, 0x18, 0x0400);
1093         }
1094
1095         bnx2_write_phy(bp, 0x18, 0x7);
1096         bnx2_read_phy(bp, 0x18, &val);
1097         bnx2_write_phy(bp, 0x18, val & ~0x4007);
1098
1099         bnx2_read_phy(bp, 0x10, &val);
1100         bnx2_write_phy(bp, 0x10, val & ~0x1);
1101
1102         /* ethernet@wirespeed */
1103         bnx2_write_phy(bp, 0x18, 0x7007);
1104         bnx2_read_phy(bp, 0x18, &val);
1105         bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
1106         return 0;
1107 }
1108
1109 static int
1110 bnx2_init_phy(struct bnx2 *bp)
1111 {
1112         u32 val;
1113         int rc = 0;
1114
1115         bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG;
1116         bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG;
1117
1118         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
1119
1120         bnx2_reset_phy(bp);
1121
1122         bnx2_read_phy(bp, MII_PHYSID1, &val);
1123         bp->phy_id = val << 16;
1124         bnx2_read_phy(bp, MII_PHYSID2, &val);
1125         bp->phy_id |= val & 0xffff;
1126
1127         if (bp->phy_flags & PHY_SERDES_FLAG) {
1128                 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1129                         rc = bnx2_init_5706s_phy(bp);
1130                 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1131                         rc = bnx2_init_5708s_phy(bp);
1132         }
1133         else {
1134                 rc = bnx2_init_copper_phy(bp);
1135         }
1136
1137         bnx2_setup_phy(bp);
1138
1139         return rc;
1140 }
1141
1142 static int
1143 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
1144 {
1145         int i;
1146         u32 val;
1147
1148         bp->fw_wr_seq++;
1149         msg_data |= bp->fw_wr_seq;
1150
1151         REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
1152
1153         /* wait for an acknowledgement. */
1154         for (i = 0; i < (FW_ACK_TIME_OUT_MS / 50); i++) {
1155                 mdelay(50);
1156
1157                 val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_MB);
1158
1159                 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
1160                         break;
1161         }
1162         if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
1163                 return 0;
1164
1165         /* If we timed out, inform the firmware that this is the case. */
1166         if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
1167                 if (!silent)
1168                         printf("fw sync timeout, reset code = %x\n", msg_data);
1169
1170                 msg_data &= ~BNX2_DRV_MSG_CODE;
1171                 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
1172
1173                 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
1174
1175                 return -EBUSY;
1176         }
1177
1178         if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
1179                 return -EIO;
1180
1181         return 0;
1182 }
1183
1184 static void
1185 bnx2_init_context(struct bnx2 *bp)
1186 {
1187         u32 vcid;
1188
1189         vcid = 96;
1190         while (vcid) {
1191                 u32 vcid_addr, pcid_addr, offset;
1192
1193                 vcid--;
1194
1195                 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
1196                         u32 new_vcid;
1197
1198                         vcid_addr = GET_PCID_ADDR(vcid);
1199                         if (vcid & 0x8) {
1200                                 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
1201                         }
1202                         else {
1203                                 new_vcid = vcid;
1204                         }
1205                         pcid_addr = GET_PCID_ADDR(new_vcid);
1206                 }
1207                 else {
1208                         vcid_addr = GET_CID_ADDR(vcid);
1209                         pcid_addr = vcid_addr;
1210                 }
1211
1212                 REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00);
1213                 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1214
1215                 /* Zero out the context. */
1216                 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) {
1217                         CTX_WR(bp, 0x00, offset, 0);
1218                 }
1219
1220                 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
1221                 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1222         }
1223 }
1224
1225 static int
1226 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
1227 {
1228         u16 good_mbuf[512];
1229         u32 good_mbuf_cnt;
1230         u32 val;
1231
1232         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
1233                 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
1234
1235         good_mbuf_cnt = 0;
1236
1237         /* Allocate a bunch of mbufs and save the good ones in an array. */
1238         val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1239         while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
1240                 REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ);
1241
1242                 val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC);
1243
1244                 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
1245
1246                 /* The addresses with Bit 9 set are bad memory blocks. */
1247                 if (!(val & (1 << 9))) {
1248                         good_mbuf[good_mbuf_cnt] = (u16) val;
1249                         good_mbuf_cnt++;
1250                 }
1251
1252                 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1253         }
1254
1255         /* Free the good ones back to the mbuf pool thus discarding
1256          * all the bad ones. */
1257         while (good_mbuf_cnt) {
1258                 good_mbuf_cnt--;
1259
1260                 val = good_mbuf[good_mbuf_cnt];
1261                 val = (val << 9) | val | 1;
1262
1263                 REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val);
1264         }
1265         return 0;
1266 }
1267
1268 static void
1269 bnx2_set_mac_addr(struct bnx2 *bp) 
1270 {
1271         u32 val;
1272         u8 *mac_addr = bp->nic->node_addr;
1273
1274         val = (mac_addr[0] << 8) | mac_addr[1];
1275
1276         REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
1277
1278         val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 
1279                 (mac_addr[4] << 8) | mac_addr[5];
1280
1281         REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
1282 }
1283
1284 static void
1285 bnx2_set_rx_mode(struct nic *nic __unused)
1286 {
1287         struct bnx2 *bp = &bnx2;
1288         u32 rx_mode, sort_mode;
1289         int i;
1290
1291         rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
1292                                   BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
1293         sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
1294
1295         if (!(bp->flags & ASF_ENABLE_FLAG)) {
1296                 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
1297         }
1298
1299         /* Accept all multicasts */
1300         for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
1301                 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
1302                        0xffffffff);
1303         }
1304         sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
1305
1306         if (rx_mode != bp->rx_mode) {
1307                 bp->rx_mode = rx_mode;
1308                 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
1309         }
1310
1311         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
1312         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
1313         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
1314 }
1315
1316 static void
1317 load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len, u32 rv2p_proc)
1318 {
1319         unsigned int i;
1320         u32 val;
1321
1322
1323         for (i = 0; i < rv2p_code_len; i += 8) {
1324                 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, *rv2p_code);
1325                 rv2p_code++;
1326                 REG_WR(bp, BNX2_RV2P_INSTR_LOW, *rv2p_code);
1327                 rv2p_code++;
1328
1329                 if (rv2p_proc == RV2P_PROC1) {
1330                         val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
1331                         REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
1332                 }
1333                 else {
1334                         val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
1335                         REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
1336                 }
1337         }
1338
1339         /* Reset the processor, un-stall is done later. */
1340         if (rv2p_proc == RV2P_PROC1) {
1341                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
1342         }
1343         else {
1344                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
1345         }
1346 }
1347
1348 static void
1349 load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
1350 {
1351         u32 offset;
1352         u32 val;
1353
1354         /* Halt the CPU. */
1355         val = REG_RD_IND(bp, cpu_reg->mode);
1356         val |= cpu_reg->mode_value_halt;
1357         REG_WR_IND(bp, cpu_reg->mode, val);
1358         REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
1359
1360         /* Load the Text area. */
1361         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
1362         if (fw->text) {
1363                 unsigned int j;
1364
1365                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
1366                         REG_WR_IND(bp, offset, fw->text[j]);
1367                 }
1368         }
1369
1370         /* Load the Data area. */
1371         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
1372         if (fw->data) {
1373                 unsigned int j;
1374
1375                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
1376                         REG_WR_IND(bp, offset, fw->data[j]);
1377                 }
1378         }
1379
1380         /* Load the SBSS area. */
1381         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
1382         if (fw->sbss) {
1383                 unsigned int j;
1384
1385                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
1386                         REG_WR_IND(bp, offset, fw->sbss[j]);
1387                 }
1388         }
1389
1390         /* Load the BSS area. */
1391         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
1392         if (fw->bss) {
1393                 unsigned int j;
1394
1395                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
1396                         REG_WR_IND(bp, offset, fw->bss[j]);
1397                 }
1398         }
1399
1400         /* Load the Read-Only area. */
1401         offset = cpu_reg->spad_base +
1402                 (fw->rodata_addr - cpu_reg->mips_view_base);
1403         if (fw->rodata) {
1404                 unsigned int j;
1405
1406                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
1407                         REG_WR_IND(bp, offset, fw->rodata[j]);
1408                 }
1409         }
1410
1411         /* Clear the pre-fetch instruction. */
1412         REG_WR_IND(bp, cpu_reg->inst, 0);
1413         REG_WR_IND(bp, cpu_reg->pc, fw->start_addr);
1414
1415         /* Start the CPU. */
1416         val = REG_RD_IND(bp, cpu_reg->mode);
1417         val &= ~cpu_reg->mode_value_halt;
1418         REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
1419         REG_WR_IND(bp, cpu_reg->mode, val);
1420 }
1421
1422 static void
1423 bnx2_init_cpus(struct bnx2 *bp)
1424 {
1425         struct cpu_reg cpu_reg;
1426         struct fw_info fw;
1427
1428         /* Unfortunately, it looks like we need to load the firmware
1429          * before the card will work properly.  That means this driver
1430          * will be huge by Etherboot standards (approx. 50K compressed).
1431          */
1432
1433         /* Initialize the RV2P processor. */
1434         load_rv2p_fw(bp, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1), RV2P_PROC1);
1435         load_rv2p_fw(bp, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2), RV2P_PROC2);
1436
1437         /* Initialize the RX Processor. */
1438         cpu_reg.mode = BNX2_RXP_CPU_MODE;
1439         cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
1440         cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
1441         cpu_reg.state = BNX2_RXP_CPU_STATE;
1442         cpu_reg.state_value_clear = 0xffffff;
1443         cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
1444         cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
1445         cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
1446         cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
1447         cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
1448         cpu_reg.spad_base = BNX2_RXP_SCRATCH;
1449         cpu_reg.mips_view_base = 0x8000000;
1450
1451         fw.ver_major = bnx2_RXP_b06FwReleaseMajor;
1452         fw.ver_minor = bnx2_RXP_b06FwReleaseMinor;
1453         fw.ver_fix = bnx2_RXP_b06FwReleaseFix;
1454         fw.start_addr = bnx2_RXP_b06FwStartAddr;
1455
1456         fw.text_addr = bnx2_RXP_b06FwTextAddr;
1457         fw.text_len = bnx2_RXP_b06FwTextLen;
1458         fw.text_index = 0;
1459         fw.text = bnx2_RXP_b06FwText;
1460
1461         fw.data_addr = bnx2_RXP_b06FwDataAddr;
1462         fw.data_len = bnx2_RXP_b06FwDataLen;
1463         fw.data_index = 0;
1464         fw.data = bnx2_RXP_b06FwData;
1465
1466         fw.sbss_addr = bnx2_RXP_b06FwSbssAddr;
1467         fw.sbss_len = bnx2_RXP_b06FwSbssLen;
1468         fw.sbss_index = 0;
1469         fw.sbss = bnx2_RXP_b06FwSbss;
1470
1471         fw.bss_addr = bnx2_RXP_b06FwBssAddr;
1472         fw.bss_len = bnx2_RXP_b06FwBssLen;
1473         fw.bss_index = 0;
1474         fw.bss = bnx2_RXP_b06FwBss;
1475
1476         fw.rodata_addr = bnx2_RXP_b06FwRodataAddr;
1477         fw.rodata_len = bnx2_RXP_b06FwRodataLen;
1478         fw.rodata_index = 0;
1479         fw.rodata = bnx2_RXP_b06FwRodata;
1480
1481         load_cpu_fw(bp, &cpu_reg, &fw);
1482
1483         /* Initialize the TX Processor. */
1484         cpu_reg.mode = BNX2_TXP_CPU_MODE;
1485         cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
1486         cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
1487         cpu_reg.state = BNX2_TXP_CPU_STATE;
1488         cpu_reg.state_value_clear = 0xffffff;
1489         cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
1490         cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
1491         cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
1492         cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
1493         cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
1494         cpu_reg.spad_base = BNX2_TXP_SCRATCH;
1495         cpu_reg.mips_view_base = 0x8000000;
1496     
1497         fw.ver_major = bnx2_TXP_b06FwReleaseMajor;
1498         fw.ver_minor = bnx2_TXP_b06FwReleaseMinor;
1499         fw.ver_fix = bnx2_TXP_b06FwReleaseFix;
1500         fw.start_addr = bnx2_TXP_b06FwStartAddr;
1501
1502         fw.text_addr = bnx2_TXP_b06FwTextAddr;
1503         fw.text_len = bnx2_TXP_b06FwTextLen;
1504         fw.text_index = 0;
1505         fw.text = bnx2_TXP_b06FwText;
1506
1507         fw.data_addr = bnx2_TXP_b06FwDataAddr;
1508         fw.data_len = bnx2_TXP_b06FwDataLen;
1509         fw.data_index = 0;
1510         fw.data = bnx2_TXP_b06FwData;
1511
1512         fw.sbss_addr = bnx2_TXP_b06FwSbssAddr;
1513         fw.sbss_len = bnx2_TXP_b06FwSbssLen;
1514         fw.sbss_index = 0;
1515         fw.sbss = bnx2_TXP_b06FwSbss;
1516
1517         fw.bss_addr = bnx2_TXP_b06FwBssAddr;
1518         fw.bss_len = bnx2_TXP_b06FwBssLen;
1519         fw.bss_index = 0;
1520         fw.bss = bnx2_TXP_b06FwBss;
1521
1522         fw.rodata_addr = bnx2_TXP_b06FwRodataAddr;
1523         fw.rodata_len = bnx2_TXP_b06FwRodataLen;
1524         fw.rodata_index = 0;
1525         fw.rodata = bnx2_TXP_b06FwRodata;
1526
1527         load_cpu_fw(bp, &cpu_reg, &fw);
1528
1529         /* Initialize the TX Patch-up Processor. */
1530         cpu_reg.mode = BNX2_TPAT_CPU_MODE;
1531         cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
1532         cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
1533         cpu_reg.state = BNX2_TPAT_CPU_STATE;
1534         cpu_reg.state_value_clear = 0xffffff;
1535         cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
1536         cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
1537         cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
1538         cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
1539         cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
1540         cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
1541         cpu_reg.mips_view_base = 0x8000000;
1542     
1543         fw.ver_major = bnx2_TPAT_b06FwReleaseMajor;
1544         fw.ver_minor = bnx2_TPAT_b06FwReleaseMinor;
1545         fw.ver_fix = bnx2_TPAT_b06FwReleaseFix;
1546         fw.start_addr = bnx2_TPAT_b06FwStartAddr;
1547
1548         fw.text_addr = bnx2_TPAT_b06FwTextAddr;
1549         fw.text_len = bnx2_TPAT_b06FwTextLen;
1550         fw.text_index = 0;
1551         fw.text = bnx2_TPAT_b06FwText;
1552
1553         fw.data_addr = bnx2_TPAT_b06FwDataAddr;
1554         fw.data_len = bnx2_TPAT_b06FwDataLen;
1555         fw.data_index = 0;
1556         fw.data = bnx2_TPAT_b06FwData;
1557
1558         fw.sbss_addr = bnx2_TPAT_b06FwSbssAddr;
1559         fw.sbss_len = bnx2_TPAT_b06FwSbssLen;
1560         fw.sbss_index = 0;
1561         fw.sbss = bnx2_TPAT_b06FwSbss;
1562
1563         fw.bss_addr = bnx2_TPAT_b06FwBssAddr;
1564         fw.bss_len = bnx2_TPAT_b06FwBssLen;
1565         fw.bss_index = 0;
1566         fw.bss = bnx2_TPAT_b06FwBss;
1567
1568         fw.rodata_addr = bnx2_TPAT_b06FwRodataAddr;
1569         fw.rodata_len = bnx2_TPAT_b06FwRodataLen;
1570         fw.rodata_index = 0;
1571         fw.rodata = bnx2_TPAT_b06FwRodata;
1572
1573         load_cpu_fw(bp, &cpu_reg, &fw);
1574
1575         /* Initialize the Completion Processor. */
1576         cpu_reg.mode = BNX2_COM_CPU_MODE;
1577         cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
1578         cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
1579         cpu_reg.state = BNX2_COM_CPU_STATE;
1580         cpu_reg.state_value_clear = 0xffffff;
1581         cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
1582         cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
1583         cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
1584         cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
1585         cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
1586         cpu_reg.spad_base = BNX2_COM_SCRATCH;
1587         cpu_reg.mips_view_base = 0x8000000;
1588     
1589         fw.ver_major = bnx2_COM_b06FwReleaseMajor;
1590         fw.ver_minor = bnx2_COM_b06FwReleaseMinor;
1591         fw.ver_fix = bnx2_COM_b06FwReleaseFix;
1592         fw.start_addr = bnx2_COM_b06FwStartAddr;
1593
1594         fw.text_addr = bnx2_COM_b06FwTextAddr;
1595         fw.text_len = bnx2_COM_b06FwTextLen;
1596         fw.text_index = 0;
1597         fw.text = bnx2_COM_b06FwText;
1598
1599         fw.data_addr = bnx2_COM_b06FwDataAddr;
1600         fw.data_len = bnx2_COM_b06FwDataLen;
1601         fw.data_index = 0;
1602         fw.data = bnx2_COM_b06FwData;
1603
1604         fw.sbss_addr = bnx2_COM_b06FwSbssAddr;
1605         fw.sbss_len = bnx2_COM_b06FwSbssLen;
1606         fw.sbss_index = 0;
1607         fw.sbss = bnx2_COM_b06FwSbss;
1608
1609         fw.bss_addr = bnx2_COM_b06FwBssAddr;
1610         fw.bss_len = bnx2_COM_b06FwBssLen;
1611         fw.bss_index = 0;
1612         fw.bss = bnx2_COM_b06FwBss;
1613
1614         fw.rodata_addr = bnx2_COM_b06FwRodataAddr;
1615         fw.rodata_len = bnx2_COM_b06FwRodataLen;
1616         fw.rodata_index = 0;
1617         fw.rodata = bnx2_COM_b06FwRodata;
1618
1619         load_cpu_fw(bp, &cpu_reg, &fw);
1620
1621 }
1622
1623 static int
1624 bnx2_set_power_state_0(struct bnx2 *bp)
1625 {
1626         u16 pmcsr;
1627         u32 val;
1628
1629         pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
1630
1631         pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
1632                 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
1633                 PCI_PM_CTRL_PME_STATUS);
1634
1635         if (pmcsr & PCI_PM_CTRL_STATE_MASK)
1636                 /* delay required during transition out of D3hot */
1637                 mdelay(20);
1638
1639         val = REG_RD(bp, BNX2_EMAC_MODE);
1640         val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
1641         val &= ~BNX2_EMAC_MODE_MPKT;
1642         REG_WR(bp, BNX2_EMAC_MODE, val);
1643
1644         val = REG_RD(bp, BNX2_RPM_CONFIG);
1645         val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
1646         REG_WR(bp, BNX2_RPM_CONFIG, val);
1647                 
1648         return 0;
1649 }
1650
1651 static void
1652 bnx2_enable_nvram_access(struct bnx2 *bp)
1653 {
1654         u32 val;
1655
1656         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
1657         /* Enable both bits, even on read. */
1658         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE, 
1659                val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
1660 }
1661
1662 static void
1663 bnx2_disable_nvram_access(struct bnx2 *bp)
1664 {
1665         u32 val;
1666
1667         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
1668         /* Disable both bits, even after read. */
1669         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE, 
1670                 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
1671                         BNX2_NVM_ACCESS_ENABLE_WR_EN));
1672 }
1673
1674 static int
1675 bnx2_init_nvram(struct bnx2 *bp)
1676 {
1677         u32 val;
1678         int j, entry_count, rc;
1679         struct flash_spec *flash;
1680
1681         /* Determine the selected interface. */
1682         val = REG_RD(bp, BNX2_NVM_CFG1);
1683
1684         entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
1685
1686         rc = 0;
1687         if (val & 0x40000000) {
1688                 /* Flash interface has been reconfigured */
1689                 for (j = 0, flash = &flash_table[0]; j < entry_count;
1690                      j++, flash++) {
1691                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
1692                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
1693                                 bp->flash_info = flash;
1694                                 break;
1695                         }
1696                 }
1697         }
1698         else {
1699                 u32 mask;
1700                 /* Not yet been reconfigured */
1701
1702                 if (val & (1 << 23))
1703                         mask = FLASH_BACKUP_STRAP_MASK;
1704                 else
1705                         mask = FLASH_STRAP_MASK;
1706
1707                 for (j = 0, flash = &flash_table[0]; j < entry_count;
1708                         j++, flash++) {
1709
1710                         if ((val & mask) == (flash->strapping & mask)) {
1711                                 bp->flash_info = flash;
1712
1713                                 /* Enable access to flash interface */
1714                                 bnx2_enable_nvram_access(bp);
1715
1716                                 /* Reconfigure the flash interface */
1717                                 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
1718                                 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
1719                                 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
1720                                 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
1721
1722                                 /* Disable access to flash interface */
1723                                 bnx2_disable_nvram_access(bp);
1724
1725                                 break;
1726                         }
1727                 }
1728         } /* if (val & 0x40000000) */
1729
1730         if (j == entry_count) {
1731                 bp->flash_info = NULL;
1732                 printf("Unknown flash/EEPROM type.\n");
1733                 return -ENODEV;
1734         }
1735
1736         val = REG_RD_IND(bp, bp->shmem_base + BNX2_SHARED_HW_CFG_CONFIG2);
1737         val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
1738         if (val) {
1739                 bp->flash_size = val;
1740         }
1741         else {
1742                 bp->flash_size = bp->flash_info->total_size;
1743         }
1744
1745         return rc;
1746 }
1747
1748 static int
1749 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
1750 {
1751         u32 val;
1752         int i, rc = 0;
1753
1754         /* Wait for the current PCI transaction to complete before
1755          * issuing a reset. */
1756         REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
1757                BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
1758                BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
1759                BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
1760                BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
1761         val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
1762         udelay(5);
1763
1764
1765         /* Wait for the firmware to tell us it is ok to issue a reset. */
1766         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1);
1767
1768         /* Deposit a driver reset signature so the firmware knows that
1769          * this is a soft reset. */
1770         REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_RESET_SIGNATURE,
1771                    BNX2_DRV_RESET_SIGNATURE_MAGIC);
1772
1773         /* Do a dummy read to force the chip to complete all current transaction
1774          * before we issue a reset. */
1775         val = REG_RD(bp, BNX2_MISC_ID);
1776
1777         val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
1778               BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
1779               BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
1780
1781         /* Chip reset. */
1782         REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
1783
1784         if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
1785             (CHIP_ID(bp) == CHIP_ID_5706_A1))
1786                 mdelay(15);
1787
1788         /* Reset takes approximate 30 usec */
1789         for (i = 0; i < 10; i++) {
1790                 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
1791                 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
1792                             BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
1793                         break;
1794                 }
1795                 udelay(10);
1796         }
1797
1798         if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
1799                    BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
1800                 printf("Chip reset did not complete\n");
1801                 return -EBUSY;
1802         }
1803
1804         /* Make sure byte swapping is properly configured. */
1805         val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
1806         if (val != 0x01020304) {
1807                 printf("Chip not in correct endian mode\n");
1808                 return -ENODEV;
1809         }
1810
1811         /* Wait for the firmware to finish its initialization. */
1812         rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 0);
1813         if (rc) {
1814                 return rc;
1815         }
1816
1817         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
1818                 /* Adjust the voltage regular to two steps lower.  The default
1819                  * of this register is 0x0000000e. */
1820                 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
1821
1822                 /* Remove bad rbuf memory from the free pool. */
1823                 rc = bnx2_alloc_bad_rbuf(bp);
1824         }
1825
1826         return rc;
1827 }
1828
1829 static void
1830 bnx2_disable(struct nic *nic __unused)
1831 {
1832         struct bnx2* bp = &bnx2;
1833
1834         if (bp->regview) {
1835                 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_UNLOAD);
1836                 iounmap(bp->regview);
1837         }
1838 }
1839
1840 static int
1841 bnx2_init_chip(struct bnx2 *bp)
1842 {
1843         u32 val;
1844         int rc;
1845
1846         /* Make sure the interrupt is not active. */
1847         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1848
1849         val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
1850               BNX2_DMA_CONFIG_DATA_WORD_SWAP |
1851 #if __BYTE_ORDER ==  __BIG_ENDIAN
1852               BNX2_DMA_CONFIG_CNTL_BYTE_SWAP | 
1853 #endif
1854               BNX2_DMA_CONFIG_CNTL_WORD_SWAP | 
1855               DMA_READ_CHANS << 12 |
1856               DMA_WRITE_CHANS << 16;
1857
1858         val |= (0x2 << 20) | (1 << 11);
1859
1860         if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz == 133))
1861                 val |= (1 << 23);
1862
1863         if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
1864             (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & PCIX_FLAG))
1865                 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
1866
1867         REG_WR(bp, BNX2_DMA_CONFIG, val);
1868
1869         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
1870                 val = REG_RD(bp, BNX2_TDMA_CONFIG);
1871                 val |= BNX2_TDMA_CONFIG_ONE_DMA;
1872                 REG_WR(bp, BNX2_TDMA_CONFIG, val);
1873         }
1874
1875         if (bp->flags & PCIX_FLAG) {
1876                 u16 val16;
1877
1878                 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
1879                                      &val16);
1880                 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
1881                                       val16 & ~PCI_X_CMD_ERO);
1882         }
1883
1884         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
1885                BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
1886                BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
1887                BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
1888
1889         /* Initialize context mapping and zero out the quick contexts.  The
1890          * context block must have already been enabled. */
1891         bnx2_init_context(bp);
1892
1893         bnx2_init_nvram(bp);
1894         bnx2_init_cpus(bp);
1895
1896         bnx2_set_mac_addr(bp);
1897
1898         val = REG_RD(bp, BNX2_MQ_CONFIG);
1899         val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
1900         val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
1901         REG_WR(bp, BNX2_MQ_CONFIG, val);
1902
1903         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
1904         REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
1905         REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
1906
1907         val = (BCM_PAGE_BITS - 8) << 24;
1908         REG_WR(bp, BNX2_RV2P_CONFIG, val);
1909
1910         /* Configure page size. */
1911         val = REG_RD(bp, BNX2_TBDR_CONFIG);
1912         val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
1913         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
1914         REG_WR(bp, BNX2_TBDR_CONFIG, val);
1915
1916         val = bp->mac_addr[0] +
1917               (bp->mac_addr[1] << 8) +
1918               (bp->mac_addr[2] << 16) +
1919               bp->mac_addr[3] +
1920               (bp->mac_addr[4] << 8) +
1921               (bp->mac_addr[5] << 16);
1922         REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
1923
1924         /* Program the MTU.  Also include 4 bytes for CRC32. */
1925         val = ETH_MAX_MTU + ETH_HLEN + 4;
1926         if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
1927                 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
1928         REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
1929
1930         bp->last_status_idx = 0;
1931         bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
1932
1933         /* Set up how to generate a link change interrupt. */
1934         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
1935
1936         REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
1937                (u64) bp->status_blk_mapping & 0xffffffff);
1938         REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
1939
1940         REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
1941                (u64) bp->stats_blk_mapping & 0xffffffff);
1942         REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
1943                (u64) bp->stats_blk_mapping >> 32);
1944
1945         REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP, 
1946                (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
1947
1948         REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
1949                (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
1950
1951         REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
1952                (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
1953
1954         REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
1955
1956         REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
1957
1958         REG_WR(bp, BNX2_HC_COM_TICKS,
1959                (bp->com_ticks_int << 16) | bp->com_ticks);
1960
1961         REG_WR(bp, BNX2_HC_CMD_TICKS,
1962                (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
1963
1964         REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks & 0xffff00);
1965         REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8);  /* 3ms */
1966
1967         if (CHIP_ID(bp) == CHIP_ID_5706_A1)
1968                 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_COLLECT_STATS);
1969         else {
1970                 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_RX_TMR_MODE |
1971                        BNX2_HC_CONFIG_TX_TMR_MODE |
1972                        BNX2_HC_CONFIG_COLLECT_STATS);
1973         }
1974
1975         /* Clear internal stats counters. */
1976         REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
1977
1978         REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
1979
1980         if (REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_FEATURE) &
1981             BNX2_PORT_FEATURE_ASF_ENABLED)
1982                 bp->flags |= ASF_ENABLE_FLAG;
1983
1984         /* Initialize the receive filter. */
1985         bnx2_set_rx_mode(bp->nic);
1986
1987         rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
1988                           0);
1989
1990         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 0x5ffffff);
1991         REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
1992
1993         udelay(20);
1994
1995         bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
1996
1997         return rc;
1998 }
1999
2000 static void
2001 bnx2_init_tx_ring(struct bnx2 *bp)
2002 {
2003         struct tx_bd *txbd;
2004         u32 val;
2005
2006         txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
2007                 
2008         /* Etherboot lives below 4GB, so hi is always 0 */
2009         txbd->tx_bd_haddr_hi = 0;
2010         txbd->tx_bd_haddr_lo = bp->tx_desc_mapping;
2011
2012         bp->tx_prod = 0;
2013         bp->tx_cons = 0;
2014         bp->hw_tx_cons = 0;
2015         bp->tx_prod_bseq = 0;
2016         
2017         val = BNX2_L2CTX_TYPE_TYPE_L2;
2018         val |= BNX2_L2CTX_TYPE_SIZE_L2;
2019         CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TYPE, val);
2020
2021         val = BNX2_L2CTX_CMD_TYPE_TYPE_L2;
2022         val |= 8 << 16;
2023         CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_CMD_TYPE, val);
2024
2025         /* Etherboot lives below 4GB, so hi is always 0 */
2026         CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_HI, 0);
2027
2028         val = (u64) bp->tx_desc_mapping & 0xffffffff;
2029         CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_LO, val);
2030 }
2031
2032 static void
2033 bnx2_init_rx_ring(struct bnx2 *bp)
2034 {
2035         struct rx_bd *rxbd;
2036         int i;
2037         u16 prod, ring_prod;
2038         u32 val;
2039
2040         bp->rx_buf_use_size = RX_BUF_USE_SIZE;
2041         bp->rx_buf_size = RX_BUF_SIZE;
2042
2043         ring_prod = prod = bp->rx_prod = 0;
2044         bp->rx_cons = 0;
2045         bp->hw_rx_cons = 0;
2046         bp->rx_prod_bseq = 0;
2047
2048         memset(bnx2_bss.rx_buf, 0, sizeof(bnx2_bss.rx_buf));
2049                 
2050         rxbd = &bp->rx_desc_ring[0];
2051         for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
2052                 rxbd->rx_bd_len = bp->rx_buf_use_size;
2053                 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
2054         }
2055         rxbd->rx_bd_haddr_hi = 0;
2056         rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping & 0xffffffff;
2057
2058         val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
2059         val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
2060         val |= 0x02 << 8;
2061         CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_CTX_TYPE, val);
2062
2063         /* Etherboot doesn't use memory above 4GB, so this is always 0 */
2064         CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_HI, 0);
2065
2066         val = bp->rx_desc_mapping & 0xffffffff;
2067         CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val);
2068
2069         for (i = 0; i < bp->rx_ring_size; i++) {
2070                 rxbd = &bp->rx_desc_ring[RX_RING_IDX(ring_prod)];
2071                 rxbd->rx_bd_haddr_hi = 0;
2072                 rxbd->rx_bd_haddr_lo = virt_to_bus(&bnx2_bss.rx_buf[ring_prod][0]);
2073                 bp->rx_prod_bseq += bp->rx_buf_use_size;
2074                 prod = NEXT_RX_BD(prod);
2075                 ring_prod = RX_RING_IDX(prod);
2076         }
2077         bp->rx_prod = prod;
2078
2079         REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, bp->rx_prod);
2080
2081         REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
2082 }
2083
2084 static int
2085 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
2086 {
2087         int rc;
2088
2089         rc = bnx2_reset_chip(bp, reset_code);
2090         if (rc) {
2091                 return rc;
2092         }
2093
2094         bnx2_init_chip(bp);
2095         bnx2_init_tx_ring(bp);
2096         bnx2_init_rx_ring(bp);
2097         return 0;
2098 }
2099
2100 static int
2101 bnx2_init_nic(struct bnx2 *bp)
2102 {
2103         int rc;
2104
2105         if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
2106                 return rc;
2107
2108         bnx2_init_phy(bp);
2109         bnx2_set_link(bp);
2110         return 0;
2111 }
2112
2113 static int
2114 bnx2_init_board(struct pci_device *pdev, struct nic *nic)
2115 {
2116         unsigned long bnx2reg_base, bnx2reg_len;
2117         struct bnx2 *bp = &bnx2;
2118         int rc;
2119         u32 reg;
2120
2121         bp->flags = 0;
2122         bp->phy_flags = 0;
2123
2124         /* enable device (incl. PCI PM wakeup), and bus-mastering */
2125         adjust_pci_device(pdev);
2126
2127         nic->ioaddr = pdev->ioaddr & ~3;
2128         nic->irqno = 0;
2129
2130         rc = 0;
2131         bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
2132         if (bp->pm_cap == 0) {
2133                 printf("Cannot find power management capability, aborting.\n");
2134                 rc = -EIO;
2135                 goto err_out_disable;
2136         }
2137
2138         bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
2139         if (bp->pcix_cap == 0) {
2140                 printf("Cannot find PCIX capability, aborting.\n");
2141                 rc = -EIO;
2142                 goto err_out_disable;
2143         }
2144
2145         bp->pdev = pdev;
2146         bp->nic = nic;
2147
2148         bnx2reg_base = pci_bar_start(pdev, PCI_BASE_ADDRESS_0);
2149         bnx2reg_len = MB_GET_CID_ADDR(17);
2150
2151         bp->regview = ioremap(bnx2reg_base, bnx2reg_len);
2152
2153         if (!bp->regview) {
2154                 printf("Cannot map register space, aborting.\n");
2155                 rc = -EIO;
2156                 goto err_out_disable;
2157         }
2158
2159         /* Configure byte swap and enable write to the reg_window registers.
2160          * Rely on CPU to do target byte swapping on big endian systems
2161          * The chip's target access swapping will not swap all accesses
2162          */
2163         pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
2164                                BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
2165                                BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
2166
2167         bnx2_set_power_state_0(bp);
2168
2169         bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
2170
2171         /* Get bus information. */
2172         reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
2173         if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
2174                 u32 clkreg;
2175
2176                 bp->flags |= PCIX_FLAG;
2177
2178                 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
2179                 
2180                 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
2181                 switch (clkreg) {
2182                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
2183                         bp->bus_speed_mhz = 133;
2184                         break;
2185
2186                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
2187                         bp->bus_speed_mhz = 100;
2188                         break;
2189
2190                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
2191                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
2192                         bp->bus_speed_mhz = 66;
2193                         break;
2194
2195                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
2196                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
2197                         bp->bus_speed_mhz = 50;
2198                         break;
2199
2200                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
2201                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
2202                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
2203                         bp->bus_speed_mhz = 33;
2204                         break;
2205                 }
2206         }
2207         else {
2208                 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
2209                         bp->bus_speed_mhz = 66;
2210                 else
2211                         bp->bus_speed_mhz = 33;
2212         }
2213
2214         if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
2215                 bp->flags |= PCI_32BIT_FLAG;
2216
2217         /* 5706A0 may falsely detect SERR and PERR. */
2218         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2219                 reg = REG_RD(bp, PCI_COMMAND);
2220                 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
2221                 REG_WR(bp, PCI_COMMAND, reg);
2222         }
2223         else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
2224                 !(bp->flags & PCIX_FLAG)) {
2225
2226                 printf("5706 A1 can only be used in a PCIX bus, aborting.\n");
2227                 goto err_out_disable;
2228         }
2229
2230         bnx2_init_nvram(bp);
2231
2232         reg = REG_RD_IND(bp, BNX2_SHM_HDR_SIGNATURE);
2233
2234         if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
2235             BNX2_SHM_HDR_SIGNATURE_SIG)
2236                 bp->shmem_base = REG_RD_IND(bp, BNX2_SHM_HDR_ADDR_0);
2237         else
2238                 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
2239
2240         /* Get the permanent MAC address.  First we need to make sure the
2241          * firmware is actually running.
2242          */
2243         reg = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_SIGNATURE);
2244
2245         if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
2246             BNX2_DEV_INFO_SIGNATURE_MAGIC) {
2247                 printf("Firmware not running, aborting.\n");
2248                 rc = -ENODEV;
2249                 goto err_out_disable;
2250         }
2251
2252         bp->fw_ver = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_BC_REV);
2253
2254         reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_UPPER);
2255         bp->mac_addr[0] = (u8) (reg >> 8);
2256         bp->mac_addr[1] = (u8) reg;
2257
2258         reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_LOWER);
2259         bp->mac_addr[2] = (u8) (reg >> 24);
2260         bp->mac_addr[3] = (u8) (reg >> 16);
2261         bp->mac_addr[4] = (u8) (reg >> 8);
2262         bp->mac_addr[5] = (u8) reg;
2263
2264         bp->tx_ring_size = MAX_TX_DESC_CNT;
2265         bp->rx_ring_size = RX_BUF_CNT;
2266         bp->rx_max_ring_idx = MAX_RX_DESC_CNT;
2267
2268         bp->rx_offset = RX_OFFSET;
2269
2270         bp->tx_quick_cons_trip_int = 20;
2271         bp->tx_quick_cons_trip = 20;
2272         bp->tx_ticks_int = 80;
2273         bp->tx_ticks = 80;
2274                 
2275         bp->rx_quick_cons_trip_int = 6;
2276         bp->rx_quick_cons_trip = 6;
2277         bp->rx_ticks_int = 18;
2278         bp->rx_ticks = 18;
2279
2280         bp->stats_ticks = 1000000 & 0xffff00;
2281
2282         bp->phy_addr = 1;
2283
2284         /* No need for WOL support in Etherboot */
2285         bp->flags |= NO_WOL_FLAG;
2286
2287         /* Disable WOL support if we are running on a SERDES chip. */
2288         if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) {
2289                 bp->phy_flags |= PHY_SERDES_FLAG;
2290                 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
2291                         bp->phy_addr = 2;
2292                         reg = REG_RD_IND(bp, bp->shmem_base +
2293                                          BNX2_SHARED_HW_CFG_CONFIG);
2294                         if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
2295                                 bp->phy_flags |= PHY_2_5G_CAPABLE_FLAG;
2296                 }
2297         }
2298
2299         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2300                 bp->tx_quick_cons_trip_int =
2301                         bp->tx_quick_cons_trip;
2302                 bp->tx_ticks_int = bp->tx_ticks;
2303                 bp->rx_quick_cons_trip_int =
2304                         bp->rx_quick_cons_trip;
2305                 bp->rx_ticks_int = bp->rx_ticks;
2306                 bp->comp_prod_trip_int = bp->comp_prod_trip;
2307                 bp->com_ticks_int = bp->com_ticks;
2308                 bp->cmd_ticks_int = bp->cmd_ticks;
2309         }
2310
2311         bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
2312         bp->req_line_speed = 0;
2313         if (bp->phy_flags & PHY_SERDES_FLAG) {
2314                 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
2315
2316                 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG);
2317                 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
2318                 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
2319                         bp->autoneg = 0;
2320                         bp->req_line_speed = bp->line_speed = SPEED_1000;
2321                         bp->req_duplex = DUPLEX_FULL;
2322                 }
2323         }
2324         else {
2325                 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
2326         }
2327
2328         bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
2329
2330         /* Disable driver heartbeat checking */
2331         REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_PULSE_MB,
2332                         BNX2_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE);
2333         REG_RD_IND(bp, bp->shmem_base + BNX2_DRV_PULSE_MB);
2334
2335         return 0;
2336
2337 err_out_disable:
2338         bnx2_disable(nic);
2339
2340         return rc;
2341 }
2342
2343 static void
2344 bnx2_transmit(struct nic *nic, const char *dst_addr,
2345                 unsigned int type, unsigned int size, const char *packet)
2346 {
2347         /* Sometimes the nic will be behind by a frame.  Using two transmit
2348          * buffers prevents us from timing out in that case.
2349          */
2350         static struct eth_frame {
2351                 uint8_t  dst_addr[ETH_ALEN];
2352                 uint8_t  src_addr[ETH_ALEN];
2353                 uint16_t type;
2354                 uint8_t  data [ETH_FRAME_LEN - ETH_HLEN];
2355         } frame[2];
2356         static int frame_idx = 0;
2357         
2358         /* send the packet to destination */
2359         struct tx_bd *txbd;
2360         struct bnx2 *bp = &bnx2;
2361         u16 prod, ring_prod;
2362         u16 hw_cons;
2363         int i = 0;
2364
2365         prod = bp->tx_prod;
2366         ring_prod = TX_RING_IDX(prod);
2367         hw_cons = bp->status_blk->status_tx_quick_consumer_index0;
2368         if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
2369                 hw_cons++;
2370         }
2371
2372         while((hw_cons != prod) && (hw_cons != (PREV_TX_BD(prod)))) {
2373                 mdelay(10);     /* give the nic a chance */
2374                 //poll_interruptions();
2375                 if (++i > 500) { /* timeout 5s for transmit */
2376                         printf("transmit timed out\n");
2377                         bnx2_disable(bp->nic);
2378                         bnx2_init_board(bp->pdev, bp->nic);
2379                         return;
2380                 }
2381         }
2382         if (i != 0) {
2383                 printf("#");
2384         }
2385
2386         /* Copy the packet to the our local buffer */
2387         memcpy(&frame[frame_idx].dst_addr, dst_addr, ETH_ALEN);
2388         memcpy(&frame[frame_idx].src_addr, nic->node_addr, ETH_ALEN);
2389         frame[frame_idx].type = htons(type);
2390         memset(&frame[frame_idx].data, 0, sizeof(frame[frame_idx].data));
2391         memcpy(&frame[frame_idx].data, packet, size);
2392
2393         /* Setup the ring buffer entry to transmit */
2394         txbd = &bp->tx_desc_ring[ring_prod];
2395         txbd->tx_bd_haddr_hi = 0; /* Etherboot runs under 4GB */
2396         txbd->tx_bd_haddr_lo = virt_to_bus(&frame[frame_idx]);
2397         txbd->tx_bd_mss_nbytes = (size + ETH_HLEN);
2398         txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
2399
2400         /* Advance to the next entry */
2401         prod = NEXT_TX_BD(prod);
2402         frame_idx ^= 1;
2403
2404         bp->tx_prod_bseq += (size + ETH_HLEN);
2405
2406         REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, prod);
2407         REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq);
2408
2409         wmb();
2410
2411         bp->tx_prod = prod;
2412 }
2413
2414 static int
2415 bnx2_poll_link(struct bnx2 *bp)
2416 {
2417         u32 new_link_state, old_link_state, emac_status;
2418
2419         new_link_state = bp->status_blk->status_attn_bits &
2420                 STATUS_ATTN_BITS_LINK_STATE;
2421
2422         old_link_state = bp->status_blk->status_attn_bits_ack &
2423                 STATUS_ATTN_BITS_LINK_STATE;
2424
2425         if (!new_link_state && !old_link_state) {
2426                 /* For some reason the card doesn't always update the link
2427                  * status bits properly.  Kick the stupid thing and try again.
2428                  */
2429                 u32 bmsr;
2430
2431                 bnx2_read_phy(bp, MII_BMSR, &bmsr);
2432                 bnx2_read_phy(bp, MII_BMSR, &bmsr);
2433
2434                 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
2435                     (CHIP_NUM(bp) == CHIP_NUM_5706)) {
2436                         REG_RD(bp, BNX2_EMAC_STATUS);
2437                 }
2438
2439                 new_link_state = bp->status_blk->status_attn_bits &
2440                         STATUS_ATTN_BITS_LINK_STATE;
2441
2442                 old_link_state = bp->status_blk->status_attn_bits_ack &
2443                         STATUS_ATTN_BITS_LINK_STATE;
2444
2445                 /* Okay, for some reason the above doesn't work with some
2446                  * switches (like HP ProCurve). If the above doesn't work,
2447                  * check the MAC directly to see if we have a link.  Perhaps we
2448                  * should always check the MAC instead probing the MII.
2449                  */
2450                 if (!new_link_state && !old_link_state) {
2451                         emac_status = REG_RD(bp, BNX2_EMAC_STATUS);
2452                         if (emac_status & BNX2_EMAC_STATUS_LINK_CHANGE) {
2453                                 /* Acknowledge the link change */
2454                                 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
2455                         } else if (emac_status & BNX2_EMAC_STATUS_LINK) {
2456                                 new_link_state = !old_link_state;
2457                         }
2458                 }
2459
2460         }
2461
2462         if (new_link_state != old_link_state) {
2463                 if (new_link_state) {
2464                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD,
2465                                 STATUS_ATTN_BITS_LINK_STATE);
2466                 }
2467                 else {
2468                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD,
2469                                 STATUS_ATTN_BITS_LINK_STATE);
2470                 }
2471
2472                 bnx2_set_link(bp);
2473
2474                 /* This is needed to take care of transient status
2475                  * during link changes.
2476                  */
2477
2478                 REG_WR(bp, BNX2_HC_COMMAND,
2479                        bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
2480                 REG_RD(bp, BNX2_HC_COMMAND);
2481
2482         }
2483
2484         return bp->link_up;
2485 }
2486
2487 static int
2488 bnx2_poll(struct nic* nic, int retrieve)
2489 {
2490         struct bnx2 *bp = &bnx2;
2491         struct rx_bd *cons_bd, *prod_bd;
2492         u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
2493         struct l2_fhdr *rx_hdr;
2494         int result = 0;
2495         unsigned int len;
2496         unsigned char *data;
2497         u32 status;
2498         
2499 #if 0
2500         if ((bp->status_blk->status_idx == bp->last_status_idx) &&
2501             (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
2502              BNX2_PCICFG_MISC_STATUS_INTA_VALUE)) {
2503
2504                 bp->last_status_idx = bp->status_blk->status_idx;
2505                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2506                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2507                BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
2508                bp->last_status_idx);
2509                 return 0;
2510         }
2511 #endif
2512
2513         if ((bp->status_blk->status_rx_quick_consumer_index0 != bp->rx_cons) && !retrieve)
2514                 return 1;
2515
2516         if (bp->status_blk->status_rx_quick_consumer_index0 != bp->rx_cons) {
2517
2518                 hw_cons = bp->hw_rx_cons = bp->status_blk->status_rx_quick_consumer_index0;
2519                 if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT) {
2520                         hw_cons++;
2521                 }
2522                 sw_cons = bp->rx_cons;
2523                 sw_prod = bp->rx_prod;
2524
2525                 rmb();
2526                 if (sw_cons != hw_cons) {
2527
2528                         sw_ring_cons = RX_RING_IDX(sw_cons);
2529                         sw_ring_prod = RX_RING_IDX(sw_prod);
2530
2531                         data = bus_to_virt(bp->rx_desc_ring[sw_ring_cons].rx_bd_haddr_lo);
2532
2533                         rx_hdr = (struct l2_fhdr *)data;
2534                         len = rx_hdr->l2_fhdr_pkt_len - 4;
2535                         if ((len > (ETH_MAX_MTU + ETH_HLEN)) ||
2536                                 ((status = rx_hdr->l2_fhdr_status) &
2537                                 (L2_FHDR_ERRORS_BAD_CRC |
2538                                 L2_FHDR_ERRORS_PHY_DECODE |
2539                                 L2_FHDR_ERRORS_ALIGNMENT |
2540                                 L2_FHDR_ERRORS_TOO_SHORT |
2541                                 L2_FHDR_ERRORS_GIANT_FRAME))) {
2542                                 result = 0;
2543                         }
2544                         else
2545                         {
2546                                 nic->packetlen = len;
2547                                 memcpy(nic->packet, data + bp->rx_offset, len);
2548                                 result = 1;
2549                         }
2550
2551                         /* Reuse the buffer */
2552                         bp->rx_prod_bseq += bp->rx_buf_use_size;
2553                         if (sw_cons != sw_prod) {
2554                                 cons_bd = &bp->rx_desc_ring[sw_ring_cons];
2555                                 prod_bd = &bp->rx_desc_ring[sw_ring_prod];
2556                                 prod_bd->rx_bd_haddr_hi = 0; /* Etherboot runs under 4GB */
2557                                 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2558                         }
2559
2560                         sw_cons = NEXT_RX_BD(sw_cons);
2561                         sw_prod = NEXT_RX_BD(sw_prod);
2562
2563                 }
2564
2565                 bp->rx_cons = sw_cons;
2566                 bp->rx_prod = sw_prod;
2567
2568                 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, bp->rx_prod);
2569
2570                 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
2571
2572                 wmb();
2573
2574         }
2575
2576         bnx2_poll_link(bp);
2577
2578 #if 0
2579         bp->last_status_idx = bp->status_blk->status_idx;
2580         rmb();
2581
2582         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2583                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2584                BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
2585                bp->last_status_idx);
2586
2587         REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
2588 #endif
2589
2590         return result;
2591 }
2592
2593 static void
2594 bnx2_irq(struct nic *nic __unused, irq_action_t action __unused)
2595 {
2596         switch ( action ) {
2597                 case DISABLE: break;
2598                 case ENABLE: break;
2599                 case FORCE: break;
2600         }
2601 }
2602
2603 static struct nic_operations bnx2_operations = {
2604         .connect        = dummy_connect,
2605         .poll           = bnx2_poll,
2606         .transmit       = bnx2_transmit,
2607         .irq            = bnx2_irq,
2608 };
2609
2610 static int
2611 bnx2_probe(struct nic *nic, struct pci_device *pdev)
2612 {
2613         struct bnx2 *bp = &bnx2;
2614         int i, rc;
2615
2616         if (pdev == 0)
2617                 return 0;
2618
2619         memset(bp, 0, sizeof(*bp));
2620
2621         rc = bnx2_init_board(pdev, nic);
2622         if (rc < 0) {
2623                 return 0;
2624         }
2625
2626         /*
2627         nic->disable = bnx2_disable;
2628         nic->transmit = bnx2_transmit;
2629         nic->poll = bnx2_poll;
2630         nic->irq = bnx2_irq;
2631         */
2632         
2633         nic->nic_op     = &bnx2_operations;
2634
2635         memcpy(nic->node_addr, bp->mac_addr, ETH_ALEN);
2636         printf("Ethernet addr: %s\n", eth_ntoa( nic->node_addr ) );
2637         printf("Broadcom NetXtreme II (%c%d) PCI%s %s %dMHz\n",
2638                 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
2639                 ((CHIP_ID(bp) & 0x0ff0) >> 4),
2640                 ((bp->flags & PCIX_FLAG) ? "-X" : ""),
2641                 ((bp->flags & PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
2642                 bp->bus_speed_mhz);
2643
2644         bnx2_set_power_state_0(bp);
2645         bnx2_disable_int(bp);
2646
2647         bnx2_alloc_mem(bp);
2648
2649         rc = bnx2_init_nic(bp);
2650         if (rc) {
2651                 return 0;
2652         }
2653
2654         bnx2_poll_link(bp);
2655         for(i = 0; !bp->link_up && (i < VALID_LINK_TIMEOUT*100); i++) {
2656                 mdelay(1);
2657                 bnx2_poll_link(bp);
2658         }
2659 #if 1
2660         if (!bp->link_up){
2661                 printf("Valid link not established\n");
2662                 goto err_out_disable;
2663         }
2664 #endif
2665         
2666         return 1;
2667
2668 err_out_disable:
2669         bnx2_disable(nic);
2670         return 0;
2671 }
2672
2673 static struct pci_device_id bnx2_nics[] = {
2674         PCI_ROM(0x14e4, 0x164a, "bnx2-5706",        "Broadcom NetXtreme II BCM5706"),
2675         PCI_ROM(0x14e4, 0x164c, "bnx2-5708",        "Broadcom NetXtreme II BCM5708"),
2676         PCI_ROM(0x14e4, 0x16aa, "bnx2-5706S",       "Broadcom NetXtreme II BCM5706S"),
2677         PCI_ROM(0x14e4, 0x16ac, "bnx2-5708S",       "Broadcom NetXtreme II BCM5708S"),
2678 };
2679
2680 PCI_DRIVER ( bnx2_driver, bnx2_nics, PCI_NO_CLASS );
2681
2682 DRIVER ( "BNX2", nic_driver, pci_driver, bnx2_driver, bnx2_probe, bnx2_disable );
2683
2684 /*
2685 static struct pci_driver bnx2_driver __pci_driver = {
2686         .type     = NIC_DRIVER,
2687         .name     = "BNX2",              
2688         .probe    = bnx2_probe,
2689         .ids      = bnx2_nics,                  
2690         .id_count = sizeof(bnx2_nics)/sizeof(bnx2_nics[0]), 
2691         .class    = 0,    
2692 };
2693 */