Moved definition of __shared into compiler.h
[people/lynusvaz/gpxe.git] / src / drivers / net / tg3.c
1 /* $Id$
2  * tg3.c: Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001, 2002 Jeff Garzik (jgarzik@mandrakesoft.com)
6  * Copyright (C) 2003 Eric Biederman (ebiederman@lnxi.com)  [etherboot port]
7  */
8
9 /* 11-13-2003   timlegge        Fix Issue with NetGear GA302T 
10  * 11-18-2003   ebiederm        Generalize NetGear Fix to what the code was supposed to be.
11  * 01-06-2005   Alf (Frederic Olivie) Add Dell bcm 5751 (0x1677) support
12  */
13
14 #include "etherboot.h"
15 #include "nic.h"
16 #include "pci.h"
17 #include "timer.h"
18 #include "string.h"
19 #include "tg3.h"
20
21 #define SUPPORT_COPPER_PHY  1
22 #define SUPPORT_FIBER_PHY   1
23 #define SUPPORT_LINK_REPORT 1
24 #define SUPPORT_PARTNO_STR  1
25 #define SUPPORT_PHY_STR     1
26
27 static struct tg3 tg3;
28
29 /* Dummy defines for error handling */
30 #define EBUSY  1
31 #define ENODEV 2
32 #define EINVAL 3
33 #define ENOMEM 4
34
35
36 /* These numbers seem to be hard coded in the NIC firmware somehow.
37  * You can't change the ring sizes, but you can change where you place
38  * them in the NIC onboard memory.
39  */
40 #define TG3_RX_RING_SIZE                512
41 #define TG3_DEF_RX_RING_PENDING         20      /* RX_RING_PENDING seems to be o.k. at 20 and 200 */
42 #define TG3_RX_RCB_RING_SIZE    1024
43
44 /*      (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ? \
45          512 : 1024) */
46 #define TG3_TX_RING_SIZE                512
47 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
48
49 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_RING_SIZE)
50 #define TG3_RX_RCB_RING_BYTES   (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_RCB_RING_SIZE)
51
52 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * TG3_TX_RING_SIZE)
53 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
54 #define PREV_TX(N)              (((N) - 1) & (TG3_TX_RING_SIZE - 1))
55
56 #define RX_PKT_BUF_SZ           (1536 + 2 + 64)
57
58 struct eth_frame {
59         uint8_t  dst_addr[ETH_ALEN];
60         uint8_t  src_addr[ETH_ALEN];
61         uint16_t type;
62         uint8_t  data [ETH_FRAME_LEN - ETH_HLEN];
63 };
64
65 struct bss {
66         struct tg3_rx_buffer_desc rx_std[TG3_RX_RING_SIZE];
67         struct tg3_rx_buffer_desc rx_rcb[TG3_RX_RCB_RING_SIZE];
68         struct tg3_tx_buffer_desc tx_ring[TG3_TX_RING_SIZE];
69         struct tg3_hw_status      hw_status;
70         struct tg3_hw_stats       hw_stats;
71         unsigned char             rx_bufs[TG3_DEF_RX_RING_PENDING][RX_PKT_BUF_SZ];
72         struct eth_frame          tx_frame[2];
73 } tg3_bss __shared;
74
75 /**
76  * pci_save_state - save the PCI configuration space of a device before suspending
77  * @dev: - PCI device that we're dealing with
78  * @buffer: - buffer to hold config space context
79  *
80  * @buffer must be large enough to hold the entire PCI 2.2 config space 
81  * (>= 64 bytes).
82  */
83 static int pci_save_state(struct pci_device *dev, uint32_t *buffer)
84 {
85         int i;
86         for (i = 0; i < 16; i++)
87                 pci_read_config_dword(dev, i * 4,&buffer[i]);
88         return 0;
89 }
90
91 /** 
92  * pci_restore_state - Restore the saved state of a PCI device
93  * @dev: - PCI device that we're dealing with
94  * @buffer: - saved PCI config space
95  *
96  */
97 static int pci_restore_state(struct pci_device *dev, uint32_t *buffer)
98 {
99         int i;
100
101         for (i = 0; i < 16; i++)
102                 pci_write_config_dword(dev,i * 4, buffer[i]);
103         return 0;
104 }
105
106 static void tg3_write_indirect_reg32(uint32_t off, uint32_t val)
107 {
108         pci_write_config_dword(tg3.pdev, TG3PCI_REG_BASE_ADDR, off);
109         pci_write_config_dword(tg3.pdev, TG3PCI_REG_DATA, val);
110 }
111
112 #define tw32(reg,val)           tg3_write_indirect_reg32((reg),(val))
113 #define tw32_mailbox(reg, val)  writel(((val) & 0xffffffff), tg3.regs + (reg))
114 #define tw16(reg,val)           writew(((val) & 0xffff), tg3.regs + (reg))
115 #define tw8(reg,val)            writeb(((val) & 0xff), tg3.regs + (reg))
116 #define tr32(reg)               readl(tg3.regs + (reg))
117 #define tr16(reg)               readw(tg3.regs + (reg))
118 #define tr8(reg)                readb(tg3.regs + (reg))
119
120 static void tw32_carefully(uint32_t reg, uint32_t val)
121 {
122         tw32(reg, val);
123         tr32(reg);
124         udelay(100);
125 }
126
127 static void tw32_mailbox2(uint32_t reg, uint32_t val)
128 {
129         tw32_mailbox(reg, val);
130         tr32(reg);
131 }
132
133 static void tg3_write_mem(uint32_t off, uint32_t val)
134 {
135         pci_write_config_dword(tg3.pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
136         pci_write_config_dword(tg3.pdev, TG3PCI_MEM_WIN_DATA, val);
137
138         /* Always leave this as zero. */
139         pci_write_config_dword(tg3.pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
140 }
141
142 static void tg3_read_mem(uint32_t off, uint32_t *val)
143 {
144         pci_write_config_dword(tg3.pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
145         pci_read_config_dword(tg3.pdev, TG3PCI_MEM_WIN_DATA, val);
146
147         /* Always leave this as zero. */
148         pci_write_config_dword(tg3.pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
149 }
150
151 static void tg3_disable_ints(struct tg3 *tp)
152 {
153         tw32(TG3PCI_MISC_HOST_CTRL,
154              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
155         tw32_mailbox2(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
156 }
157
158 static void tg3_switch_clocks(struct tg3 *tp)
159 {
160         uint32_t orig_clock_ctrl, clock_ctrl;
161
162         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
163
164         orig_clock_ctrl = clock_ctrl;
165         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN | CLOCK_CTRL_CLKRUN_OENABLE | 0x1f);
166         tp->pci_clock_ctrl = clock_ctrl;
167         
168         if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) &&
169             (!((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
170                && (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) &&
171                 (orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE)!=0) {
172                 tw32_carefully(TG3PCI_CLOCK_CTRL, 
173                         clock_ctrl | (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK));
174                 tw32_carefully(TG3PCI_CLOCK_CTRL, 
175                         clock_ctrl | (CLOCK_CTRL_ALTCLK));
176         }
177         tw32_carefully(TG3PCI_CLOCK_CTRL, clock_ctrl);
178 }
179
180 #define PHY_BUSY_LOOPS  5000
181
182 static int tg3_readphy(struct tg3 *tp, int reg, uint32_t *val)
183 {
184         uint32_t frame_val;
185         int loops, ret;
186
187         tw32_carefully(MAC_MI_MODE, tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL);
188
189         *val = 0xffffffff;
190
191         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
192                       MI_COM_PHY_ADDR_MASK);
193         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
194                       MI_COM_REG_ADDR_MASK);
195         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
196         
197         tw32_carefully(MAC_MI_COM, frame_val);
198
199         loops = PHY_BUSY_LOOPS;
200         while (loops-- > 0) {
201                 udelay(10);
202                 frame_val = tr32(MAC_MI_COM);
203
204                 if ((frame_val & MI_COM_BUSY) == 0) {
205                         udelay(5);
206                         frame_val = tr32(MAC_MI_COM);
207                         break;
208                 }
209         }
210
211         ret = -EBUSY;
212         if (loops > 0) {
213                 *val = frame_val & MI_COM_DATA_MASK;
214                 ret = 0;
215         }
216
217         tw32_carefully(MAC_MI_MODE, tp->mi_mode);
218
219         return ret;
220 }
221
222 static int tg3_writephy(struct tg3 *tp, int reg, uint32_t val)
223 {
224         uint32_t frame_val;
225         int loops, ret;
226
227         tw32_carefully(MAC_MI_MODE, tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL);
228
229         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
230                       MI_COM_PHY_ADDR_MASK);
231         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
232                       MI_COM_REG_ADDR_MASK);
233         frame_val |= (val & MI_COM_DATA_MASK);
234         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
235         
236         tw32_carefully(MAC_MI_COM, frame_val);
237
238         loops = PHY_BUSY_LOOPS;
239         while (loops-- > 0) {
240                 udelay(10);
241                 frame_val = tr32(MAC_MI_COM);
242                 if ((frame_val & MI_COM_BUSY) == 0) {
243                         udelay(5);
244                         frame_val = tr32(MAC_MI_COM);
245                         break;
246                 }
247         }
248
249         ret = -EBUSY;
250         if (loops > 0)
251                 ret = 0;
252
253         tw32_carefully(MAC_MI_MODE, tp->mi_mode);
254
255         return ret;
256 }
257
258 static int tg3_writedsp(struct tg3 *tp, uint16_t addr, uint16_t val)
259 {
260         int err;
261         err  = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, addr);
262         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
263         return err;
264 }
265
266
267 static void tg3_phy_set_wirespeed(struct tg3 *tp)
268 {
269         uint32_t val;
270
271         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
272                 return;
273
274         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007);
275         tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
276         tg3_writephy(tp, MII_TG3_AUX_CTRL, (val | (1 << 15) | (1 << 4)));
277 }
278
279 static int tg3_bmcr_reset(struct tg3 *tp)
280 {
281         uint32_t phy_control;
282         int limit, err;
283
284         /* OK, reset it, and poll the BMCR_RESET bit until it
285          * clears or we time out.
286          */
287         phy_control = BMCR_RESET;
288         err = tg3_writephy(tp, MII_BMCR, phy_control);
289         if (err != 0)
290                 return -EBUSY;
291
292         limit = 5000;
293         while (limit--) {
294                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
295                 if (err != 0)
296                         return -EBUSY;
297
298                 if ((phy_control & BMCR_RESET) == 0) {
299                         udelay(40);
300                         break;
301                 }
302                 udelay(10);
303         }
304         if (limit <= 0)
305                 return -EBUSY;
306
307         return 0;
308 }
309
310 static int tg3_wait_macro_done(struct tg3 *tp)
311 {
312         int limit = 100;
313
314         while (limit--) {
315                 uint32_t tmp32;
316
317                 tg3_readphy(tp, 0x16, &tmp32);
318                 if ((tmp32 & 0x1000) == 0)
319                         break;
320         }
321         if (limit <= 0)
322                 return -EBUSY;
323
324         return 0;
325 }
326
327 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
328 {
329         static const uint32_t test_pat[4][6] = {
330         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
331         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
332         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
333         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
334         };
335         int chan;
336
337         for (chan = 0; chan < 4; chan++) {
338                 int i;
339
340                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
341                         (chan * 0x2000) | 0x0200);
342                 tg3_writephy(tp, 0x16, 0x0002);
343
344                 for (i = 0; i < 6; i++)
345                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
346                                 test_pat[chan][i]);
347
348                 tg3_writephy(tp, 0x16, 0x0202);
349                 if (tg3_wait_macro_done(tp)) {
350                         *resetp = 1;
351                         return -EBUSY;
352                 }
353
354                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
355                              (chan * 0x2000) | 0x0200);
356                 tg3_writephy(tp, 0x16, 0x0082);
357                 if (tg3_wait_macro_done(tp)) {
358                         *resetp = 1;
359                         return -EBUSY;
360                 }
361
362                 tg3_writephy(tp, 0x16, 0x0802);
363                 if (tg3_wait_macro_done(tp)) {
364                         *resetp = 1;
365                         return -EBUSY;
366                 }
367
368                 for (i = 0; i < 6; i += 2) {
369                         uint32_t low, high;
370
371                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low);
372                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high);
373                         if (tg3_wait_macro_done(tp)) {
374                                 *resetp = 1;
375                                 return -EBUSY;
376                         }
377                         low &= 0x7fff;
378                         high &= 0x000f;
379                         if (low != test_pat[chan][i] ||
380                             high != test_pat[chan][i+1]) {
381                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
382                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
383                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
384
385                                 return -EBUSY;
386                         }
387                 }
388         }
389
390         return 0;
391 }
392
393 static int tg3_phy_reset_chanpat(struct tg3 *tp)
394 {
395         int chan;
396
397         for (chan = 0; chan < 4; chan++) {
398                 int i;
399
400                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
401                              (chan * 0x2000) | 0x0200);
402                 tg3_writephy(tp, 0x16, 0x0002);
403                 for (i = 0; i < 6; i++)
404                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
405                 tg3_writephy(tp, 0x16, 0x0202);
406                 if (tg3_wait_macro_done(tp))
407                         return -EBUSY;
408         }
409
410         return 0;
411 }
412
413 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
414 {
415         uint32_t reg32, phy9_orig;
416         int retries, do_phy_reset, err;
417
418         retries = 10;
419         do_phy_reset = 1;
420         do {
421                 if (do_phy_reset) {
422                         err = tg3_bmcr_reset(tp);
423                         if (err)
424                                 return err;
425                         do_phy_reset = 0;
426                 }
427                 
428                 /* Disable transmitter and interrupt.  */
429                 tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32);
430                 reg32 |= 0x3000;
431                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
432
433                 /* Set full-duplex, 1000 mbps.  */
434                 tg3_writephy(tp, MII_BMCR,
435                         BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
436
437                 /* Set to master mode.  */
438                 tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig);
439                 tg3_writephy(tp, MII_TG3_CTRL,
440                         (MII_TG3_CTRL_AS_MASTER |
441                                 MII_TG3_CTRL_ENABLE_AS_MASTER));
442
443                 /* Enable SM_DSP_CLOCK and 6dB.  */
444                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
445
446                 /* Block the PHY control access.  */
447                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
448                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
449
450                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
451                 if (!err)
452                         break;
453         } while (--retries);
454
455         err = tg3_phy_reset_chanpat(tp);
456         if (err)
457                 return err;
458
459         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
460         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
461
462         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
463         tg3_writephy(tp, 0x16, 0x0000);
464
465         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
466
467         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
468
469         tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32);
470         reg32 &= ~0x3000;
471         tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
472
473         return err;
474 }
475
476 /* This will reset the tigon3 PHY if there is no valid
477  * link.
478  */
479 static int tg3_phy_reset(struct tg3 *tp)
480 {
481         uint32_t phy_status;
482         int err;
483
484         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
485         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
486         if (err != 0)
487                 return -EBUSY;
488
489         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) ||
490                 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
491                 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
492                 err = tg3_phy_reset_5703_4_5(tp);
493                 if (err)
494                         return err;
495                 goto out;
496         }
497         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
498           // Taken from Broadcom's source code
499           tg3_writephy(tp, 0x18, 0x0c00);
500           tg3_writephy(tp, 0x17, 0x000a);
501           tg3_writephy(tp, 0x15, 0x310b);
502           tg3_writephy(tp, 0x17, 0x201f);
503           tg3_writephy(tp, 0x15, 0x9506);
504           tg3_writephy(tp, 0x17, 0x401f);
505           tg3_writephy(tp, 0x15, 0x14e2);
506           tg3_writephy(tp, 0x18, 0x0400);
507         }
508         err = tg3_bmcr_reset(tp);
509         if (err)
510                 return err;
511  out:
512         tg3_phy_set_wirespeed(tp);
513         return 0;
514 }
515
516 static void tg3_set_power_state_0(struct tg3 *tp)
517 {
518         uint16_t power_control;
519         int pm = tp->pm_cap;
520
521         /* Make sure register accesses (indirect or otherwise)
522          * will function correctly.
523          */
524         pci_write_config_dword(tp->pdev,  TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
525
526         pci_read_config_word(tp->pdev, pm + PCI_PM_CTRL, &power_control);
527
528         power_control |= PCI_PM_CTRL_PME_STATUS;
529         power_control &= ~(PCI_PM_CTRL_STATE_MASK);
530         power_control |= 0;
531         pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
532
533         tw32_carefully(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
534
535         return;
536 }
537
538
539 #if SUPPORT_LINK_REPORT
540 static void tg3_link_report(struct tg3 *tp)
541 {
542         if (!tp->carrier_ok) {
543                 printf("Link is down.\n");
544         } else {
545                 printf("Link is up at %d Mbps, %s duplex. %s %s %s\n",
546                         (tp->link_config.active_speed == SPEED_1000 ?
547                                1000 :
548                         (tp->link_config.active_speed == SPEED_100 ?
549                                 100 : 10)),
550                         (tp->link_config.active_duplex == DUPLEX_FULL ?  
551                                 "full" : "half"),
552                         (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "TX" : "",
553                         (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "RX" : "",
554                         (tp->tg3_flags & (TG3_FLAG_TX_PAUSE |TG3_FLAG_RX_PAUSE)) ? "flow control" : "");
555         }
556 }
557 #else
558 #define tg3_link_report(tp)
559 #endif
560
561 static void tg3_setup_flow_control(struct tg3 *tp, uint32_t local_adv, uint32_t remote_adv)
562 {
563         uint32_t new_tg3_flags = 0;
564
565         if (local_adv & ADVERTISE_PAUSE_CAP) {
566                 if (local_adv & ADVERTISE_PAUSE_ASYM) {
567                         if (remote_adv & LPA_PAUSE_CAP)
568                                 new_tg3_flags |=
569                                         (TG3_FLAG_RX_PAUSE |
570                                          TG3_FLAG_TX_PAUSE);
571                         else if (remote_adv & LPA_PAUSE_ASYM)
572                                 new_tg3_flags |=
573                                         (TG3_FLAG_RX_PAUSE);
574                 } else {
575                         if (remote_adv & LPA_PAUSE_CAP)
576                                 new_tg3_flags |=
577                                         (TG3_FLAG_RX_PAUSE |
578                                          TG3_FLAG_TX_PAUSE);
579                 }
580         } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
581                 if ((remote_adv & LPA_PAUSE_CAP) &&
582                     (remote_adv & LPA_PAUSE_ASYM))
583                         new_tg3_flags |= TG3_FLAG_TX_PAUSE;
584         }
585
586         tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
587         tp->tg3_flags |= new_tg3_flags;
588
589         if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
590                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
591         else
592                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
593
594         if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
595                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
596         else
597                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
598 }
599
600 #if SUPPORT_COPPER_PHY
601 static void tg3_aux_stat_to_speed_duplex(
602         struct tg3 *tp __unused, uint32_t val, uint8_t *speed, uint8_t *duplex)
603 {
604         static const uint8_t map[] = {
605                 [0] = (SPEED_INVALID << 2) | DUPLEX_INVALID,
606                 [MII_TG3_AUX_STAT_10HALF >> 8]   = (SPEED_10 << 2) | DUPLEX_HALF,
607                 [MII_TG3_AUX_STAT_10FULL >> 8]   = (SPEED_10 << 2) | DUPLEX_FULL,
608                 [MII_TG3_AUX_STAT_100HALF >> 8]  = (SPEED_100 << 2) | DUPLEX_HALF,
609                 [MII_TG3_AUX_STAT_100_4 >> 8] = (SPEED_INVALID << 2) | DUPLEX_INVALID,
610                 [MII_TG3_AUX_STAT_100FULL >> 8]  = (SPEED_100 << 2) | DUPLEX_FULL,
611                 [MII_TG3_AUX_STAT_1000HALF >> 8] = (SPEED_1000 << 2) | DUPLEX_HALF,
612                 [MII_TG3_AUX_STAT_1000FULL >> 8] = (SPEED_1000 << 2) | DUPLEX_FULL,
613         };
614         uint8_t result;
615         result = map[(val & MII_TG3_AUX_STAT_SPDMASK) >> 8];
616         *speed = result >> 2;
617         *duplex = result & 3;
618 }
619
620 static int tg3_phy_copper_begin(struct tg3 *tp)
621 {
622         uint32_t new_adv;
623
624         tp->link_config.advertising =
625                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
626                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
627                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
628                         ADVERTISED_Autoneg | ADVERTISED_MII);
629         
630         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY) {
631                 tp->link_config.advertising &=
632                         ~(ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
633         }
634         
635         new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
636         if (tp->link_config.advertising & ADVERTISED_10baseT_Half) {
637                 new_adv |= ADVERTISE_10HALF;
638         }
639         if (tp->link_config.advertising & ADVERTISED_10baseT_Full) {
640                 new_adv |= ADVERTISE_10FULL;
641         }
642         if (tp->link_config.advertising & ADVERTISED_100baseT_Half) {
643                 new_adv |= ADVERTISE_100HALF;
644         }
645         if (tp->link_config.advertising & ADVERTISED_100baseT_Full) {
646                 new_adv |= ADVERTISE_100FULL;
647         }
648         tg3_writephy(tp, MII_ADVERTISE, new_adv);
649         
650         if (tp->link_config.advertising &
651                 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
652                 new_adv = 0;
653                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half) {
654                         new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
655                 }
656                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full) {
657                         new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
658                 }
659                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
660                         (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
661                                 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)) {
662                         new_adv |= (MII_TG3_CTRL_AS_MASTER |
663                                 MII_TG3_CTRL_ENABLE_AS_MASTER);
664                 }
665                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
666         } else {
667                 tg3_writephy(tp, MII_TG3_CTRL, 0);
668         }
669
670         tg3_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
671
672         return 0;
673 }
674
675 static int tg3_init_5401phy_dsp(struct tg3 *tp)
676 {
677         int err;
678
679         /* Turn off tap power management. */
680         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c20);
681         
682         err |= tg3_writedsp(tp, 0x0012, 0x1804);
683         err |= tg3_writedsp(tp, 0x0013, 0x1204);
684         err |= tg3_writedsp(tp, 0x8006, 0x0132);
685         err |= tg3_writedsp(tp, 0x8006, 0x0232);
686         err |= tg3_writedsp(tp, 0x201f, 0x0a20);
687
688         udelay(40);
689
690         return err;
691 }
692
693 static int tg3_setup_copper_phy(struct tg3 *tp)
694 {
695         int current_link_up;
696         uint32_t bmsr, dummy;
697         int i, err;
698
699         tw32_carefully(MAC_STATUS,
700                 (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED
701                  | MAC_STATUS_LNKSTATE_CHANGED));
702
703         tp->mi_mode = MAC_MI_MODE_BASE;
704         tw32_carefully(MAC_MI_MODE, tp->mi_mode);
705
706         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
707
708         /* Some third-party PHYs need to be reset on link going
709          * down.
710          */
711         if (    (       (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) ||
712                         (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
713                         (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)) &&
714                 (tp->carrier_ok)) {
715                 tg3_readphy(tp, MII_BMSR, &bmsr);
716                 tg3_readphy(tp, MII_BMSR, &bmsr);
717                 if (!(bmsr & BMSR_LSTATUS))
718                         tg3_phy_reset(tp);
719         }
720
721         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
722                 tg3_readphy(tp, MII_BMSR, &bmsr);
723                 tg3_readphy(tp, MII_BMSR, &bmsr);
724
725                 if (!(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
726                         bmsr = 0;
727
728                 if (!(bmsr & BMSR_LSTATUS)) {
729                         err = tg3_init_5401phy_dsp(tp);
730                         if (err)
731                                 return err;
732
733                         tg3_readphy(tp, MII_BMSR, &bmsr);
734                         for (i = 0; i < 1000; i++) {
735                                 udelay(10);
736                                 tg3_readphy(tp, MII_BMSR, &bmsr);
737                                 if (bmsr & BMSR_LSTATUS) {
738                                         udelay(40);
739                                         break;
740                                 }
741                         }
742
743                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
744                             !(bmsr & BMSR_LSTATUS) &&
745                             tp->link_config.active_speed == SPEED_1000) {
746                                 err = tg3_phy_reset(tp);
747                                 if (!err)
748                                         err = tg3_init_5401phy_dsp(tp);
749                                 if (err)
750                                         return err;
751                         }
752                 }
753         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
754                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
755                 /* 5701 {A0,B0} CRC bug workaround */
756                 tg3_writephy(tp, 0x15, 0x0a75);
757                 tg3_writephy(tp, 0x1c, 0x8c68);
758                 tg3_writephy(tp, 0x1c, 0x8d68);
759                 tg3_writephy(tp, 0x1c, 0x8c68);
760         }
761
762         /* Clear pending interrupts... */
763         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
764         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
765
766         tg3_writephy(tp, MII_TG3_IMASK, ~0);
767
768         if (tp->led_mode == led_mode_three_link)
769                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
770                              MII_TG3_EXT_CTRL_LNK3_LED_MODE);
771         else
772                 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
773
774         current_link_up = 0;
775
776         tg3_readphy(tp, MII_BMSR, &bmsr);
777         tg3_readphy(tp, MII_BMSR, &bmsr);
778
779         if (bmsr & BMSR_LSTATUS) {
780                 uint32_t aux_stat, bmcr;
781
782                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
783                 for (i = 0; i < 2000; i++) {
784                         udelay(10);
785                         tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
786                         if (aux_stat)
787                                 break;
788                 }
789
790                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
791                         &tp->link_config.active_speed,
792                         &tp->link_config.active_duplex);
793                 tg3_readphy(tp, MII_BMCR, &bmcr);
794                 tg3_readphy(tp, MII_BMCR, &bmcr);
795                 if (bmcr & BMCR_ANENABLE) {
796                         uint32_t gig_ctrl;
797                         
798                         current_link_up = 1;
799                         
800                         /* Force autoneg restart if we are exiting
801                          * low power mode.
802                          */
803                         tg3_readphy(tp, MII_TG3_CTRL, &gig_ctrl);
804                         if (!(gig_ctrl & (MII_TG3_CTRL_ADV_1000_HALF |
805                                       MII_TG3_CTRL_ADV_1000_FULL))) {
806                                 current_link_up = 0;
807                         }
808                 } else {
809                         current_link_up = 0;
810                 }
811         }
812
813         if (current_link_up == 1 &&
814                 (tp->link_config.active_duplex == DUPLEX_FULL)) {
815                 uint32_t local_adv, remote_adv;
816
817                 tg3_readphy(tp, MII_ADVERTISE, &local_adv);
818                 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
819
820                 tg3_readphy(tp, MII_LPA, &remote_adv);
821                 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
822
823                 /* If we are not advertising full pause capability,
824                  * something is wrong.  Bring the link down and reconfigure.
825                  */
826                 if (local_adv != ADVERTISE_PAUSE_CAP) {
827                         current_link_up = 0;
828                 } else {
829                         tg3_setup_flow_control(tp, local_adv, remote_adv);
830                 }
831         }
832
833         if (current_link_up == 0) {
834                 uint32_t tmp;
835
836                 tg3_phy_copper_begin(tp);
837
838                 tg3_readphy(tp, MII_BMSR, &tmp);
839                 tg3_readphy(tp, MII_BMSR, &tmp);
840                 if (tmp & BMSR_LSTATUS)
841                         current_link_up = 1;
842         }
843
844         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
845         if (current_link_up == 1) {
846                 if (tp->link_config.active_speed == SPEED_100 ||
847                     tp->link_config.active_speed == SPEED_10)
848                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
849                 else
850                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
851         } else
852                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
853
854         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
855         if (tp->link_config.active_duplex == DUPLEX_HALF)
856                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
857
858         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
859         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
860                 if ((tp->led_mode == led_mode_link10) ||
861                     (current_link_up == 1 &&
862                      tp->link_config.active_speed == SPEED_10))
863                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
864         } else {
865                 if (current_link_up == 1)
866                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
867                 tw32(MAC_LED_CTRL, LED_CTRL_PHY_MODE_1);
868         }
869
870         /* ??? Without this setting Netgear GA302T PHY does not
871          * ??? send/receive packets...
872          * With this other PHYs cannot bring up the link
873          */
874         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
875                 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
876                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
877                 tw32_carefully(MAC_MI_MODE, tp->mi_mode);
878         }
879
880         tw32_carefully(MAC_MODE, tp->mac_mode);
881
882         /* Link change polled. */
883         tw32_carefully(MAC_EVENT, 0);
884
885         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
886             current_link_up == 1 &&
887             tp->link_config.active_speed == SPEED_1000 &&
888             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
889              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
890                 udelay(120);
891                 tw32_carefully(MAC_STATUS,
892                         (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED));
893                 tg3_write_mem(
894                               NIC_SRAM_FIRMWARE_MBOX,
895                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
896         }
897
898         if (current_link_up != tp->carrier_ok) {
899                 tp->carrier_ok = current_link_up;
900                 tg3_link_report(tp);
901         }
902
903         return 0;
904 }
905 #else
906 #define tg3_setup_copper_phy(TP) (-EINVAL)
907 #endif /* SUPPORT_COPPER_PHY */
908
909 #if SUPPORT_FIBER_PHY
910 struct tg3_fiber_aneginfo {
911         int state;
912 #define ANEG_STATE_UNKNOWN              0
913 #define ANEG_STATE_AN_ENABLE            1
914 #define ANEG_STATE_RESTART_INIT         2
915 #define ANEG_STATE_RESTART              3
916 #define ANEG_STATE_DISABLE_LINK_OK      4
917 #define ANEG_STATE_ABILITY_DETECT_INIT  5
918 #define ANEG_STATE_ABILITY_DETECT       6
919 #define ANEG_STATE_ACK_DETECT_INIT      7
920 #define ANEG_STATE_ACK_DETECT           8
921 #define ANEG_STATE_COMPLETE_ACK_INIT    9
922 #define ANEG_STATE_COMPLETE_ACK         10
923 #define ANEG_STATE_IDLE_DETECT_INIT     11
924 #define ANEG_STATE_IDLE_DETECT          12
925 #define ANEG_STATE_LINK_OK              13
926 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
927 #define ANEG_STATE_NEXT_PAGE_WAIT       15
928
929         uint32_t flags;
930 #define MR_AN_ENABLE            0x00000001
931 #define MR_RESTART_AN           0x00000002
932 #define MR_AN_COMPLETE          0x00000004
933 #define MR_PAGE_RX              0x00000008
934 #define MR_NP_LOADED            0x00000010
935 #define MR_TOGGLE_TX            0x00000020
936 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
937 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
938 #define MR_LP_ADV_SYM_PAUSE     0x00000100
939 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
940 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
941 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
942 #define MR_LP_ADV_NEXT_PAGE     0x00001000
943 #define MR_TOGGLE_RX            0x00002000
944 #define MR_NP_RX                0x00004000
945
946 #define MR_LINK_OK              0x80000000
947
948         unsigned long link_time, cur_time;
949
950         uint32_t ability_match_cfg;
951         int ability_match_count;
952
953         char ability_match, idle_match, ack_match;
954
955         uint32_t txconfig, rxconfig;
956 #define ANEG_CFG_NP             0x00000080
957 #define ANEG_CFG_ACK            0x00000040
958 #define ANEG_CFG_RF2            0x00000020
959 #define ANEG_CFG_RF1            0x00000010
960 #define ANEG_CFG_PS2            0x00000001
961 #define ANEG_CFG_PS1            0x00008000
962 #define ANEG_CFG_HD             0x00004000
963 #define ANEG_CFG_FD             0x00002000
964 #define ANEG_CFG_INVAL          0x00001f06
965
966 };
967 #define ANEG_OK         0
968 #define ANEG_DONE       1
969 #define ANEG_TIMER_ENAB 2
970 #define ANEG_FAILED     -1
971
972 #define ANEG_STATE_SETTLE_TIME  10000
973
974 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
975                                    struct tg3_fiber_aneginfo *ap)
976 {
977         unsigned long delta;
978         uint32_t rx_cfg_reg;
979         int ret;
980
981         if (ap->state == ANEG_STATE_UNKNOWN) {
982                 ap->rxconfig = 0;
983                 ap->link_time = 0;
984                 ap->cur_time = 0;
985                 ap->ability_match_cfg = 0;
986                 ap->ability_match_count = 0;
987                 ap->ability_match = 0;
988                 ap->idle_match = 0;
989                 ap->ack_match = 0;
990         }
991         ap->cur_time++;
992
993         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
994                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
995
996                 if (rx_cfg_reg != ap->ability_match_cfg) {
997                         ap->ability_match_cfg = rx_cfg_reg;
998                         ap->ability_match = 0;
999                         ap->ability_match_count = 0;
1000                 } else {
1001                         if (++ap->ability_match_count > 1) {
1002                                 ap->ability_match = 1;
1003                                 ap->ability_match_cfg = rx_cfg_reg;
1004                         }
1005                 }
1006                 if (rx_cfg_reg & ANEG_CFG_ACK)
1007                         ap->ack_match = 1;
1008                 else
1009                         ap->ack_match = 0;
1010
1011                 ap->idle_match = 0;
1012         } else {
1013                 ap->idle_match = 1;
1014                 ap->ability_match_cfg = 0;
1015                 ap->ability_match_count = 0;
1016                 ap->ability_match = 0;
1017                 ap->ack_match = 0;
1018
1019                 rx_cfg_reg = 0;
1020         }
1021
1022         ap->rxconfig = rx_cfg_reg;
1023         ret = ANEG_OK;
1024
1025         switch(ap->state) {
1026         case ANEG_STATE_UNKNOWN:
1027                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
1028                         ap->state = ANEG_STATE_AN_ENABLE;
1029
1030                 /* fallthru */
1031         case ANEG_STATE_AN_ENABLE:
1032                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
1033                 if (ap->flags & MR_AN_ENABLE) {
1034                         ap->link_time = 0;
1035                         ap->cur_time = 0;
1036                         ap->ability_match_cfg = 0;
1037                         ap->ability_match_count = 0;
1038                         ap->ability_match = 0;
1039                         ap->idle_match = 0;
1040                         ap->ack_match = 0;
1041
1042                         ap->state = ANEG_STATE_RESTART_INIT;
1043                 } else {
1044                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
1045                 }
1046                 break;
1047
1048         case ANEG_STATE_RESTART_INIT:
1049                 ap->link_time = ap->cur_time;
1050                 ap->flags &= ~(MR_NP_LOADED);
1051                 ap->txconfig = 0;
1052                 tw32(MAC_TX_AUTO_NEG, 0);
1053                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1054                 tw32_carefully(MAC_MODE, tp->mac_mode);
1055
1056                 ret = ANEG_TIMER_ENAB;
1057                 ap->state = ANEG_STATE_RESTART;
1058
1059                 /* fallthru */
1060         case ANEG_STATE_RESTART:
1061                 delta = ap->cur_time - ap->link_time;
1062                 if (delta > ANEG_STATE_SETTLE_TIME) {
1063                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
1064                 } else {
1065                         ret = ANEG_TIMER_ENAB;
1066                 }
1067                 break;
1068
1069         case ANEG_STATE_DISABLE_LINK_OK:
1070                 ret = ANEG_DONE;
1071                 break;
1072
1073         case ANEG_STATE_ABILITY_DETECT_INIT:
1074                 ap->flags &= ~(MR_TOGGLE_TX);
1075                 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
1076                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
1077                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1078                 tw32_carefully(MAC_MODE, tp->mac_mode);
1079
1080                 ap->state = ANEG_STATE_ABILITY_DETECT;
1081                 break;
1082
1083         case ANEG_STATE_ABILITY_DETECT:
1084                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
1085                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
1086                 }
1087                 break;
1088
1089         case ANEG_STATE_ACK_DETECT_INIT:
1090                 ap->txconfig |= ANEG_CFG_ACK;
1091                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
1092                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1093                 tw32_carefully(MAC_MODE, tp->mac_mode);
1094
1095                 ap->state = ANEG_STATE_ACK_DETECT;
1096
1097                 /* fallthru */
1098         case ANEG_STATE_ACK_DETECT:
1099                 if (ap->ack_match != 0) {
1100                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
1101                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
1102                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
1103                         } else {
1104                                 ap->state = ANEG_STATE_AN_ENABLE;
1105                         }
1106                 } else if (ap->ability_match != 0 &&
1107                            ap->rxconfig == 0) {
1108                         ap->state = ANEG_STATE_AN_ENABLE;
1109                 }
1110                 break;
1111
1112         case ANEG_STATE_COMPLETE_ACK_INIT:
1113                 if (ap->rxconfig & ANEG_CFG_INVAL) {
1114                         ret = ANEG_FAILED;
1115                         break;
1116                 }
1117                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
1118                                MR_LP_ADV_HALF_DUPLEX |
1119                                MR_LP_ADV_SYM_PAUSE |
1120                                MR_LP_ADV_ASYM_PAUSE |
1121                                MR_LP_ADV_REMOTE_FAULT1 |
1122                                MR_LP_ADV_REMOTE_FAULT2 |
1123                                MR_LP_ADV_NEXT_PAGE |
1124                                MR_TOGGLE_RX |
1125                                MR_NP_RX);
1126                 if (ap->rxconfig & ANEG_CFG_FD)
1127                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
1128                 if (ap->rxconfig & ANEG_CFG_HD)
1129                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
1130                 if (ap->rxconfig & ANEG_CFG_PS1)
1131                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
1132                 if (ap->rxconfig & ANEG_CFG_PS2)
1133                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
1134                 if (ap->rxconfig & ANEG_CFG_RF1)
1135                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
1136                 if (ap->rxconfig & ANEG_CFG_RF2)
1137                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
1138                 if (ap->rxconfig & ANEG_CFG_NP)
1139                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
1140
1141                 ap->link_time = ap->cur_time;
1142
1143                 ap->flags ^= (MR_TOGGLE_TX);
1144                 if (ap->rxconfig & 0x0008)
1145                         ap->flags |= MR_TOGGLE_RX;
1146                 if (ap->rxconfig & ANEG_CFG_NP)
1147                         ap->flags |= MR_NP_RX;
1148                 ap->flags |= MR_PAGE_RX;
1149
1150                 ap->state = ANEG_STATE_COMPLETE_ACK;
1151                 ret = ANEG_TIMER_ENAB;
1152                 break;
1153
1154         case ANEG_STATE_COMPLETE_ACK:
1155                 if (ap->ability_match != 0 &&
1156                     ap->rxconfig == 0) {
1157                         ap->state = ANEG_STATE_AN_ENABLE;
1158                         break;
1159                 }
1160                 delta = ap->cur_time - ap->link_time;
1161                 if (delta > ANEG_STATE_SETTLE_TIME) {
1162                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
1163                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
1164                         } else {
1165                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
1166                                     !(ap->flags & MR_NP_RX)) {
1167                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
1168                                 } else {
1169                                         ret = ANEG_FAILED;
1170                                 }
1171                         }
1172                 }
1173                 break;
1174
1175         case ANEG_STATE_IDLE_DETECT_INIT:
1176                 ap->link_time = ap->cur_time;
1177                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
1178                 tw32_carefully(MAC_MODE, tp->mac_mode);
1179
1180                 ap->state = ANEG_STATE_IDLE_DETECT;
1181                 ret = ANEG_TIMER_ENAB;
1182                 break;
1183
1184         case ANEG_STATE_IDLE_DETECT:
1185                 if (ap->ability_match != 0 &&
1186                     ap->rxconfig == 0) {
1187                         ap->state = ANEG_STATE_AN_ENABLE;
1188                         break;
1189                 }
1190                 delta = ap->cur_time - ap->link_time;
1191                 if (delta > ANEG_STATE_SETTLE_TIME) {
1192                         /* XXX another gem from the Broadcom driver :( */
1193                         ap->state = ANEG_STATE_LINK_OK;
1194                 }
1195                 break;
1196
1197         case ANEG_STATE_LINK_OK:
1198                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
1199                 ret = ANEG_DONE;
1200                 break;
1201
1202         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
1203                 /* ??? unimplemented */
1204                 break;
1205
1206         case ANEG_STATE_NEXT_PAGE_WAIT:
1207                 /* ??? unimplemented */
1208                 break;
1209
1210         default:
1211                 ret = ANEG_FAILED;
1212                 break;
1213         };
1214
1215         return ret;
1216 }
1217
1218 static int tg3_setup_fiber_phy(struct tg3 *tp)
1219 {
1220         uint32_t orig_pause_cfg;
1221         uint16_t orig_active_speed;
1222         uint8_t orig_active_duplex;
1223         int current_link_up;
1224         int i;
1225
1226         orig_pause_cfg =
1227                 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
1228                                   TG3_FLAG_TX_PAUSE));
1229         orig_active_speed = tp->link_config.active_speed;
1230         orig_active_duplex = tp->link_config.active_duplex;
1231
1232         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
1233         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
1234         tw32_carefully(MAC_MODE, tp->mac_mode);
1235
1236         /* Reset when initting first time or we have a link. */
1237         if (!(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) ||
1238             (tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED)) {
1239                 /* Set PLL lock range. */
1240                 tg3_writephy(tp, 0x16, 0x8007);
1241
1242                 /* SW reset */
1243                 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
1244
1245                 /* Wait for reset to complete. */
1246                 mdelay(5);
1247
1248                 /* Config mode; select PMA/Ch 1 regs. */
1249                 tg3_writephy(tp, 0x10, 0x8411);
1250
1251                 /* Enable auto-lock and comdet, select txclk for tx. */
1252                 tg3_writephy(tp, 0x11, 0x0a10);
1253
1254                 tg3_writephy(tp, 0x18, 0x00a0);
1255                 tg3_writephy(tp, 0x16, 0x41ff);
1256
1257                 /* Assert and deassert POR. */
1258                 tg3_writephy(tp, 0x13, 0x0400);
1259                 udelay(40);
1260                 tg3_writephy(tp, 0x13, 0x0000);
1261
1262                 tg3_writephy(tp, 0x11, 0x0a50);
1263                 udelay(40);
1264                 tg3_writephy(tp, 0x11, 0x0a10);
1265
1266                 /* Wait for signal to stabilize */
1267                 mdelay(150);
1268
1269                 /* Deselect the channel register so we can read the PHYID
1270                  * later.
1271                  */
1272                 tg3_writephy(tp, 0x10, 0x8011);
1273         }
1274
1275         /* Disable link change interrupt.  */
1276         tw32_carefully(MAC_EVENT, 0);
1277
1278         current_link_up = 0;
1279         if (tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED) {
1280                 if (!(tp->tg3_flags & TG3_FLAG_GOT_SERDES_FLOWCTL)) {
1281                         struct tg3_fiber_aneginfo aninfo;
1282                         int status = ANEG_FAILED;
1283                         unsigned int tick;
1284                         uint32_t tmp;
1285
1286                         memset(&aninfo, 0, sizeof(aninfo));
1287                         aninfo.flags |= (MR_AN_ENABLE);
1288
1289                         tw32(MAC_TX_AUTO_NEG, 0);
1290
1291                         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
1292                         tw32_carefully(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
1293
1294                         tw32_carefully(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
1295
1296                         aninfo.state = ANEG_STATE_UNKNOWN;
1297                         aninfo.cur_time = 0;
1298                         tick = 0;
1299                         while (++tick < 195000) {
1300                                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
1301                                 if (status == ANEG_DONE ||
1302                                     status == ANEG_FAILED)
1303                                         break;
1304
1305                                 udelay(1);
1306                         }
1307
1308                         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
1309                         tw32_carefully(MAC_MODE, tp->mac_mode);
1310
1311                         if (status == ANEG_DONE &&
1312                             (aninfo.flags &
1313                              (MR_AN_COMPLETE | MR_LINK_OK |
1314                               MR_LP_ADV_FULL_DUPLEX))) {
1315                                 uint32_t local_adv, remote_adv;
1316
1317                                 local_adv = ADVERTISE_PAUSE_CAP;
1318                                 remote_adv = 0;
1319                                 if (aninfo.flags & MR_LP_ADV_SYM_PAUSE)
1320                                         remote_adv |= LPA_PAUSE_CAP;
1321                                 if (aninfo.flags & MR_LP_ADV_ASYM_PAUSE)
1322                                         remote_adv |= LPA_PAUSE_ASYM;
1323
1324                                 tg3_setup_flow_control(tp, local_adv, remote_adv);
1325
1326                                 tp->tg3_flags |=
1327                                         TG3_FLAG_GOT_SERDES_FLOWCTL;
1328                                 current_link_up = 1;
1329                         }
1330                         for (i = 0; i < 60; i++) {
1331                                 udelay(20);
1332                                 tw32_carefully(MAC_STATUS,
1333                                         (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED));
1334                                 if ((tr32(MAC_STATUS) &
1335                                      (MAC_STATUS_SYNC_CHANGED |
1336                                       MAC_STATUS_CFG_CHANGED)) == 0)
1337                                         break;
1338                         }
1339                         if (current_link_up == 0 &&
1340                             (tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED)) {
1341                                 current_link_up = 1;
1342                         }
1343                 } else {
1344                         /* Forcing 1000FD link up. */
1345                         current_link_up = 1;
1346                 }
1347         }
1348
1349         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1350         tw32_carefully(MAC_MODE, tp->mac_mode);
1351
1352         tp->hw_status->status =
1353                 (SD_STATUS_UPDATED |
1354                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
1355
1356         for (i = 0; i < 100; i++) {
1357                 udelay(20);
1358                 tw32_carefully(MAC_STATUS,
1359                         (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED));
1360                 if ((tr32(MAC_STATUS) &
1361                      (MAC_STATUS_SYNC_CHANGED |
1362                       MAC_STATUS_CFG_CHANGED)) == 0)
1363                         break;
1364         }
1365
1366         if ((tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED) == 0)
1367                 current_link_up = 0;
1368
1369         if (current_link_up == 1) {
1370                 tp->link_config.active_speed = SPEED_1000;
1371                 tp->link_config.active_duplex = DUPLEX_FULL;
1372         } else {
1373                 tp->link_config.active_speed = SPEED_INVALID;
1374                 tp->link_config.active_duplex = DUPLEX_INVALID;
1375         }
1376
1377         if (current_link_up != tp->carrier_ok) {
1378                 tp->carrier_ok = current_link_up;
1379                 tg3_link_report(tp);
1380         } else {
1381                 uint32_t now_pause_cfg =
1382                         tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
1383                                          TG3_FLAG_TX_PAUSE);
1384                 if (orig_pause_cfg != now_pause_cfg ||
1385                     orig_active_speed != tp->link_config.active_speed ||
1386                     orig_active_duplex != tp->link_config.active_duplex)
1387                         tg3_link_report(tp);
1388         }
1389
1390         if ((tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED) == 0) {
1391                 tw32_carefully(MAC_MODE, tp->mac_mode | MAC_MODE_LINK_POLARITY);
1392                 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
1393                         tw32_carefully(MAC_MODE, tp->mac_mode);
1394                 }
1395         }
1396
1397         return 0;
1398 }
1399 #else
1400 #define tg3_setup_fiber_phy(TP) (-EINVAL)
1401 #endif /* SUPPORT_FIBER_PHY */
1402
1403 static int tg3_setup_phy(struct tg3 *tp)
1404 {
1405         int err;
1406
1407         if (tp->phy_id == PHY_ID_SERDES) {
1408                 err = tg3_setup_fiber_phy(tp);
1409         } else {
1410                 err = tg3_setup_copper_phy(tp);
1411         }
1412
1413         if (tp->link_config.active_speed == SPEED_1000 &&
1414             tp->link_config.active_duplex == DUPLEX_HALF)
1415                 tw32(MAC_TX_LENGTHS,
1416                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1417                       (6 << TX_LENGTHS_IPG_SHIFT) |
1418                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1419         else
1420                 tw32(MAC_TX_LENGTHS,
1421                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1422                       (6 << TX_LENGTHS_IPG_SHIFT) |
1423                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1424
1425         return err;
1426 }
1427
1428
1429 #define MAX_WAIT_CNT 1000
1430
1431 /* To stop a block, clear the enable bit and poll till it
1432  * clears.  
1433  */
1434 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, uint32_t enable_bit)
1435 {
1436         unsigned int i;
1437         uint32_t val;
1438
1439         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1440                 switch(ofs) {
1441                 case RCVLSC_MODE:
1442                 case DMAC_MODE:
1443                 case MBFREE_MODE:
1444                 case BUFMGR_MODE:
1445                 case MEMARB_MODE:
1446                         /* We can't enable/disable these bits of the
1447                          * 5705, just say success.
1448                          */
1449                         return 0;
1450                 default:
1451                         break;
1452                 }
1453         }
1454         val = tr32(ofs);
1455         val &= ~enable_bit;
1456         tw32(ofs, val);
1457         tr32(ofs);
1458
1459         for (i = 0; i < MAX_WAIT_CNT; i++) {
1460                 udelay(100);
1461                 val = tr32(ofs);
1462                 if ((val & enable_bit) == 0)
1463                         break;
1464         }
1465
1466         if (i == MAX_WAIT_CNT) {
1467                 printf("tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
1468                        ofs, enable_bit);
1469                 return -ENODEV;
1470         }
1471
1472         return 0;
1473 }
1474
1475 static int tg3_abort_hw(struct tg3 *tp)
1476 {
1477         int i, err;
1478
1479         tg3_disable_ints(tp);
1480
1481         tp->rx_mode &= ~RX_MODE_ENABLE;
1482         tw32_carefully(MAC_RX_MODE, tp->rx_mode);
1483
1484         err  = tg3_stop_block(tp, RCVBDI_MODE,   RCVBDI_MODE_ENABLE);
1485         err |= tg3_stop_block(tp, RCVLPC_MODE,   RCVLPC_MODE_ENABLE);
1486         err |= tg3_stop_block(tp, RCVLSC_MODE,   RCVLSC_MODE_ENABLE);
1487         err |= tg3_stop_block(tp, RCVDBDI_MODE,  RCVDBDI_MODE_ENABLE);
1488         err |= tg3_stop_block(tp, RCVDCC_MODE,   RCVDCC_MODE_ENABLE);
1489         err |= tg3_stop_block(tp, RCVCC_MODE,    RCVCC_MODE_ENABLE);
1490
1491         err |= tg3_stop_block(tp, SNDBDS_MODE,   SNDBDS_MODE_ENABLE);
1492         err |= tg3_stop_block(tp, SNDBDI_MODE,   SNDBDI_MODE_ENABLE);
1493         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1494         err |= tg3_stop_block(tp, RDMAC_MODE,    RDMAC_MODE_ENABLE);
1495         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
1496         err |= tg3_stop_block(tp, SNDBDC_MODE,   SNDBDC_MODE_ENABLE);
1497         if (err)
1498                 goto out;
1499
1500         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
1501         tw32_carefully(MAC_MODE, tp->mac_mode);
1502
1503         tp->tx_mode &= ~TX_MODE_ENABLE;
1504         tw32_carefully(MAC_TX_MODE, tp->tx_mode);
1505
1506         for (i = 0; i < MAX_WAIT_CNT; i++) {
1507                 udelay(100);
1508                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
1509                         break;
1510         }
1511         if (i >= MAX_WAIT_CNT) {
1512                 printf("tg3_abort_hw timed out TX_MODE_ENABLE will not clear MAC_TX_MODE=%x\n",
1513                         tr32(MAC_TX_MODE));
1514                 return -ENODEV;
1515         }
1516
1517         err  = tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE);
1518         err |= tg3_stop_block(tp, WDMAC_MODE,  WDMAC_MODE_ENABLE);
1519         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE);
1520
1521         tw32(FTQ_RESET, 0xffffffff);
1522         tw32(FTQ_RESET, 0x00000000);
1523
1524         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE);
1525         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE);
1526         if (err)
1527                 goto out;
1528
1529         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
1530
1531 out:
1532         return err;
1533 }
1534
1535 static void tg3_chip_reset(struct tg3 *tp)
1536 {
1537         uint32_t val;
1538
1539         if (!(tp->tg3_flags2 & TG3_FLG2_SUN_5704)) {
1540                 /* Force NVRAM to settle.
1541                  * This deals with a chip bug which can result in EEPROM
1542                  * corruption.
1543                  */
1544                 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
1545                         int i;
1546         
1547                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
1548                         for (i = 0; i < 100000; i++) {
1549                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
1550                                         break;
1551                                 udelay(10);
1552                         }
1553                 }
1554         }
1555         /* In Etherboot we don't need to worry about the 5701
1556          * REG_WRITE_BUG because we do all register writes indirectly.
1557          */
1558
1559         // Alf: here patched
1560         /* do the reset */
1561         val = GRC_MISC_CFG_CORECLK_RESET;
1562         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
1563             || (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1564                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
1565         }
1566
1567         // Alf : Please VALIDATE THIS.
1568         // It is necessary in my case (5751) to prevent a reboot, but
1569         // I have no idea about a side effect on any other version.
1570         // It appears to be what's done in tigon3.c from Broadcom
1571         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
1572           tw32(GRC_MISC_CFG, 0x20000000) ;
1573           val |= 0x20000000 ;
1574         }
1575
1576         tw32(GRC_MISC_CFG, val);
1577
1578         /* Flush PCI posted writes.  The normal MMIO registers
1579          * are inaccessible at this time so this is the only
1580          * way to make this reliably.  I tried to use indirect
1581          * register read/write but this upset some 5701 variants.
1582          */
1583         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
1584
1585         udelay(120);
1586
1587         /* Re-enable indirect register accesses. */
1588         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
1589                                tp->misc_host_ctrl);
1590
1591         /* Set MAX PCI retry to zero. */
1592         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
1593         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
1594             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
1595                 val |= PCISTATE_RETRY_SAME_DMA;
1596         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
1597
1598         pci_restore_state(tp->pdev, tp->pci_cfg_state);
1599
1600         /* Make sure PCI-X relaxed ordering bit is clear. */
1601         pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
1602         val &= ~PCIX_CAPS_RELAXED_ORDERING;
1603         pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
1604
1605         tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
1606
1607         if (((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0) &&
1608                 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
1609                 tp->pci_clock_ctrl |=
1610                         (CLOCK_CTRL_FORCE_CLKRUN | CLOCK_CTRL_CLKRUN_OENABLE);
1611                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
1612         }
1613
1614         tw32(TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
1615 }
1616
1617 static void tg3_stop_fw(struct tg3 *tp)
1618 {
1619         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
1620                 uint32_t val;
1621                 int i;
1622
1623                 tg3_write_mem(NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1624                 val = tr32(GRC_RX_CPU_EVENT);
1625                 val |= (1 << 14);
1626                 tw32(GRC_RX_CPU_EVENT, val);
1627
1628                 /* Wait for RX cpu to ACK the event.  */
1629                 for (i = 0; i < 100; i++) {
1630                         if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
1631                                 break;
1632                         udelay(1);
1633                 }
1634         }
1635 }
1636
1637 static int tg3_restart_fw(struct tg3 *tp, uint32_t state)
1638 {
1639         uint32_t val;
1640         int i;
1641         
1642         tg3_write_mem(NIC_SRAM_FIRMWARE_MBOX, 
1643                 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1644         /* Wait for firmware initialization to complete. */
1645         for (i = 0; i < 100000; i++) {
1646                 tg3_read_mem(NIC_SRAM_FIRMWARE_MBOX, &val);
1647                 if (val == (uint32_t) ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1648                         break;
1649                 udelay(10);
1650         }
1651         if (i >= 100000 &&
1652                     !(tp->tg3_flags2 & TG3_FLG2_SUN_5704)) {
1653                 printf("Firmware will not restart magic=%x\n",
1654                         val);
1655                 return -ENODEV;
1656         }
1657         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1658           state = DRV_STATE_SUSPEND;
1659         }
1660
1661         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
1662             (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)) {
1663           // Enable PCIE bug fix
1664           tg3_read_mem(0x7c00, &val);
1665           tg3_write_mem(0x7c00, val | 0x02000000);
1666         }
1667         tg3_write_mem(NIC_SRAM_FW_DRV_STATE_MBOX, state);
1668         return 0;
1669 }
1670
1671 static int tg3_halt(struct tg3 *tp)
1672 {
1673         tg3_stop_fw(tp);
1674         tg3_abort_hw(tp);
1675         tg3_chip_reset(tp);
1676         return tg3_restart_fw(tp, DRV_STATE_UNLOAD);
1677 }
1678
1679 static void __tg3_set_mac_addr(struct tg3 *tp)
1680 {
1681         uint32_t addr_high, addr_low;
1682         int i;
1683
1684         addr_high = ((tp->nic->node_addr[0] << 8) |
1685                      tp->nic->node_addr[1]);
1686         addr_low = ((tp->nic->node_addr[2] << 24) |
1687                     (tp->nic->node_addr[3] << 16) |
1688                     (tp->nic->node_addr[4] <<  8) |
1689                     (tp->nic->node_addr[5] <<  0));
1690         for (i = 0; i < 4; i++) {
1691                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
1692                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
1693         }
1694
1695         if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
1696                 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
1697                 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705)) {
1698                 for(i = 0; i < 12; i++) {
1699                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
1700                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
1701                 }
1702         }
1703         addr_high = (tp->nic->node_addr[0] +
1704                      tp->nic->node_addr[1] +
1705                      tp->nic->node_addr[2] +
1706                      tp->nic->node_addr[3] +
1707                      tp->nic->node_addr[4] +
1708                      tp->nic->node_addr[5]) &
1709                 TX_BACKOFF_SEED_MASK;
1710         tw32(MAC_TX_BACKOFF_SEED, addr_high);
1711 }
1712
1713 static void tg3_set_bdinfo(struct tg3 *tp, uint32_t bdinfo_addr,
1714                            dma_addr_t mapping, uint32_t maxlen_flags,
1715                            uint32_t nic_addr)
1716 {
1717         tg3_write_mem((bdinfo_addr +
1718                        TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
1719                       ((uint64_t) mapping >> 32));
1720         tg3_write_mem((bdinfo_addr +
1721                        TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
1722                       ((uint64_t) mapping & 0xffffffff));
1723         tg3_write_mem((bdinfo_addr +
1724                        TG3_BDINFO_MAXLEN_FLAGS),
1725                        maxlen_flags);
1726         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
1727                 tg3_write_mem((bdinfo_addr + TG3_BDINFO_NIC_ADDR), nic_addr);
1728         }
1729 }
1730
1731
1732 static void tg3_init_rings(struct tg3 *tp)
1733 {
1734         unsigned i;
1735
1736         /* Zero out the tg3 variables */
1737         memset(&tg3_bss, 0, sizeof(tg3_bss));
1738         tp->rx_std    = &tg3_bss.rx_std[0];
1739         tp->rx_rcb    = &tg3_bss.rx_rcb[0];
1740         tp->tx_ring   = &tg3_bss.tx_ring[0];
1741         tp->hw_status = &tg3_bss.hw_status;
1742         tp->hw_stats  = &tg3_bss.hw_stats;
1743         tp->mac_mode  = 0;
1744
1745
1746         /* Initialize tx/rx rings for packet processing.
1747          *
1748          * The chip has been shut down and the driver detached from
1749          * the networking, so no interrupts or new tx packets will
1750          * end up in the driver.
1751          */
1752
1753         /* Initialize invariants of the rings, we only set this
1754          * stuff once.  This works because the card does not
1755          * write into the rx buffer posting rings.
1756          */
1757         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
1758                 struct tg3_rx_buffer_desc *rxd;
1759
1760                 rxd = &tp->rx_std[i];
1761                 rxd->idx_len = (RX_PKT_BUF_SZ - 2 - 64) << RXD_LEN_SHIFT;
1762                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
1763                 rxd->opaque = (RXD_OPAQUE_RING_STD | (i << RXD_OPAQUE_INDEX_SHIFT));
1764
1765                 /* Note where the receive buffer for the ring is placed */
1766                 rxd->addr_hi = 0;
1767                 rxd->addr_lo = virt_to_bus(
1768                         &tg3_bss.rx_bufs[i%TG3_DEF_RX_RING_PENDING][2]);
1769         }
1770 }
1771
1772 #define TG3_WRITE_SETTINGS(TABLE) \
1773 do { \
1774         const uint32_t *_table, *_end; \
1775         _table = TABLE; \
1776         _end = _table + sizeof(TABLE)/sizeof(TABLE[0]);  \
1777         for(; _table < _end; _table += 2) { \
1778                 tw32(_table[0], _table[1]); \
1779         } \
1780 } while(0)
1781
1782
1783 /* initialize/reset the tg3 */
1784 static int tg3_setup_hw(struct tg3 *tp)
1785 {
1786         uint32_t val, rdmac_mode;
1787         int i, err, limit;
1788
1789         /* Simply don't support setups with extremly buggy firmware in etherboot */
1790         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
1791                 printf("Error 5701_A0 firmware bug detected\n");
1792                 return -EINVAL;
1793         }
1794
1795         tg3_disable_ints(tp);
1796
1797         /* Originally this was all in tg3_init_hw */
1798
1799         /* Force the chip into D0. */
1800         tg3_set_power_state_0(tp);
1801
1802         tg3_switch_clocks(tp);
1803
1804         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
1805
1806         // This should go somewhere else
1807 #define T3_PCIE_CAPABILITY_ID_REG           0xD0
1808 #define T3_PCIE_CAPABILITY_ID               0x10
1809 #define T3_PCIE_CAPABILITY_REG              0xD2
1810
1811         /* Originally this was all in tg3_reset_hw */
1812
1813         tg3_stop_fw(tp);
1814
1815         /* No need to call tg3_abort_hw here, it is called before tg3_setup_hw. */
1816
1817         tg3_chip_reset(tp);
1818
1819         tw32(GRC_MODE, tp->grc_mode);  /* Redundant? */
1820
1821         err = tg3_restart_fw(tp, DRV_STATE_START);
1822         if (err)
1823                 return err;
1824
1825         if (tp->phy_id == PHY_ID_SERDES) {
1826                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
1827         }
1828         tw32_carefully(MAC_MODE, tp->mac_mode);
1829
1830
1831         /* This works around an issue with Athlon chipsets on
1832          * B3 tigon3 silicon.  This bit has no effect on any
1833          * other revision.
1834          * Alf: Except 5750 ! (which reboots)
1835          */
1836
1837         if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
1838           tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
1839         tw32_carefully(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
1840
1841         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
1842             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
1843                 val = tr32(TG3PCI_PCISTATE);
1844                 val |= PCISTATE_RETRY_SAME_DMA;
1845                 tw32(TG3PCI_PCISTATE, val);
1846         }
1847
1848         /* Descriptor ring init may make accesses to the
1849          * NIC SRAM area to setup the TX descriptors, so we
1850          * can only do this after the hardware has been
1851          * successfully reset.
1852          */
1853         tg3_init_rings(tp);
1854
1855         /* Clear statistics/status block in chip */
1856         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
1857                 for (i = NIC_SRAM_STATS_BLK;
1858                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
1859                      i += sizeof(uint32_t)) {
1860                         tg3_write_mem(i, 0);
1861                         udelay(40);
1862                 }
1863         }
1864
1865         /* This value is determined during the probe time DMA
1866          * engine test, tg3_setup_dma.
1867          */
1868         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
1869
1870         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
1871                           GRC_MODE_4X_NIC_SEND_RINGS |
1872                           GRC_MODE_NO_TX_PHDR_CSUM |
1873                           GRC_MODE_NO_RX_PHDR_CSUM);
1874         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
1875         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1876         tp->grc_mode |= GRC_MODE_NO_RX_PHDR_CSUM;
1877
1878         tw32(GRC_MODE,
1879                 tp->grc_mode | 
1880                 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
1881
1882         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
1883         tw32(GRC_MISC_CFG,
1884              (65 << GRC_MISC_CFG_PRESCALAR_SHIFT));
1885
1886         /* Initialize MBUF/DESC pool. */
1887         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
1888                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
1889                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
1890                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
1891                 else
1892                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
1893                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
1894                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
1895         }
1896         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE)) {
1897                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
1898                      tp->bufmgr_config.mbuf_read_dma_low_water);
1899                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
1900                      tp->bufmgr_config.mbuf_mac_rx_low_water);
1901                 tw32(BUFMGR_MB_HIGH_WATER,
1902                      tp->bufmgr_config.mbuf_high_water);
1903         } else {
1904                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
1905                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
1906                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
1907                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
1908                 tw32(BUFMGR_MB_HIGH_WATER,
1909                      tp->bufmgr_config.mbuf_high_water_jumbo);
1910         }
1911         tw32(BUFMGR_DMA_LOW_WATER,
1912              tp->bufmgr_config.dma_low_water);
1913         tw32(BUFMGR_DMA_HIGH_WATER,
1914              tp->bufmgr_config.dma_high_water);
1915
1916         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
1917         for (i = 0; i < 2000; i++) {
1918                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
1919                         break;
1920                 udelay(10);
1921         }
1922         if (i >= 2000) {
1923                 printf("tg3_setup_hw cannot enable BUFMGR\n");
1924                 return -ENODEV;
1925         }
1926
1927         tw32(FTQ_RESET, 0xffffffff);
1928         tw32(FTQ_RESET, 0x00000000);
1929         for (i = 0; i < 2000; i++) {
1930                 if (tr32(FTQ_RESET) == 0x00000000)
1931                         break;
1932                 udelay(10);
1933         }
1934         if (i >= 2000) {
1935                 printf("tg3_setup_hw cannot reset FTQ\n");
1936                 return -ENODEV;
1937         }
1938
1939         /* Initialize TG3_BDINFO's at:
1940          *  RCVDBDI_STD_BD:     standard eth size rx ring
1941          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
1942          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
1943          *
1944          * like so:
1945          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
1946          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
1947          *                              ring attribute flags
1948          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
1949          *
1950          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
1951          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
1952          *
1953          * ??? No space allocated for mini receive ring? :(
1954          *
1955          * The size of each ring is fixed in the firmware, but the location is
1956          * configurable.
1957          */
1958         {
1959                 static const uint32_t table_all[] = {
1960                         /* Setup replenish thresholds. */
1961                         RCVBDI_STD_THRESH, TG3_DEF_RX_RING_PENDING / 8,
1962
1963                         /* Etherboot lives below 4GB */
1964                         RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, 0,
1965                         RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR, NIC_SRAM_RX_BUFFER_DESC,
1966                 };
1967                 static const uint32_t table_not_5705[] = {
1968                         /* Buffer maximum length */
1969                         RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT,
1970                         
1971                         /* Disable the mini frame rx ring */
1972                         RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,      BDINFO_FLAGS_DISABLED,
1973                         
1974                         /* Disable the jumbo frame rx ring */
1975                         RCVBDI_JUMBO_THRESH, 0,
1976                         RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, BDINFO_FLAGS_DISABLED,
1977                         
1978                         
1979                 };
1980                 TG3_WRITE_SETTINGS(table_all);
1981                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, 
1982                         virt_to_bus(tp->rx_std));
1983                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1984                         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
1985                                 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
1986                 } else {
1987                         TG3_WRITE_SETTINGS(table_not_5705);
1988                 }
1989         }
1990
1991         
1992         /* There is only one send ring on 5705, no need to explicitly
1993          * disable the others.
1994          */
1995         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
1996                 /* Clear out send RCB ring in SRAM. */
1997                 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
1998                         tg3_write_mem(i + TG3_BDINFO_MAXLEN_FLAGS, BDINFO_FLAGS_DISABLED);
1999         }
2000
2001         tp->tx_prod = 0;
2002         tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
2003         tw32_mailbox2(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
2004
2005         tg3_set_bdinfo(tp,
2006                 NIC_SRAM_SEND_RCB,
2007                 virt_to_bus(tp->tx_ring),
2008                 (TG3_TX_RING_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT),
2009                 NIC_SRAM_TX_BUFFER_DESC);
2010
2011         /* There is only one receive return ring on 5705, no need to explicitly
2012          * disable the others.
2013          */
2014         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
2015                 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK; i += TG3_BDINFO_SIZE) {
2016                         tg3_write_mem(i + TG3_BDINFO_MAXLEN_FLAGS,
2017                                 BDINFO_FLAGS_DISABLED);
2018                 }
2019         }
2020
2021         tp->rx_rcb_ptr = 0;
2022         tw32_mailbox2(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
2023
2024         tg3_set_bdinfo(tp,
2025                 NIC_SRAM_RCV_RET_RCB,
2026                 virt_to_bus(tp->rx_rcb),
2027                 (TG3_RX_RCB_RING_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT),
2028                 0);
2029
2030         tp->rx_std_ptr = TG3_DEF_RX_RING_PENDING;
2031         tw32_mailbox2(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
2032                      tp->rx_std_ptr);
2033
2034         tw32_mailbox2(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW, 0);
2035
2036         /* Initialize MAC address and backoff seed. */
2037         __tg3_set_mac_addr(tp);
2038
2039         /* Calculate RDMAC_MODE setting early, we need it to determine
2040          * the RCVLPC_STATE_ENABLE mask.
2041          */
2042         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
2043                 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
2044                 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
2045                 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
2046                 RDMAC_MODE_LNGREAD_ENAB);
2047         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
2048                 rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
2049         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2050                 if (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
2051                         if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
2052                                 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
2053                                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
2054                         }
2055                 }
2056         }
2057
2058         /* Setup host coalescing engine. */
2059         tw32(HOSTCC_MODE, 0);
2060         for (i = 0; i < 2000; i++) {
2061                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
2062                         break;
2063                 udelay(10);
2064         }
2065
2066         tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
2067                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
2068         tw32_carefully(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
2069
2070         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
2071         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
2072                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
2073                                        GRC_LCLCTRL_GPIO_OUTPUT1);
2074         tw32_carefully(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
2075
2076         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
2077         tr32(MAILBOX_INTERRUPT_0);
2078
2079         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
2080                 tw32_carefully(DMAC_MODE, DMAC_MODE_ENABLE);
2081         }
2082
2083         val = ( WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
2084                 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
2085                 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
2086                 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
2087                 WDMAC_MODE_LNGREAD_ENAB);
2088         if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) &&
2089                 ((tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) != 0) &&
2090                 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
2091                 val |= WDMAC_MODE_RX_ACCEL;
2092         }
2093         tw32_carefully(WDMAC_MODE, val);
2094
2095         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
2096                 val = tr32(TG3PCI_X_CAPS);
2097                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
2098                         val &= PCIX_CAPS_BURST_MASK;
2099                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
2100                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2101                         val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
2102                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
2103                         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
2104                                 val |= (tp->split_mode_max_reqs <<
2105                                         PCIX_CAPS_SPLIT_SHIFT);
2106                 }
2107                 tw32(TG3PCI_X_CAPS, val);
2108         }
2109
2110         tw32_carefully(RDMAC_MODE, rdmac_mode);
2111         {
2112                 static const uint32_t table_all[] = {
2113                         /* MTU + ethernet header + FCS + optional VLAN tag */
2114                         MAC_RX_MTU_SIZE, ETH_MAX_MTU + ETH_HLEN + 8,
2115                         
2116                         /* The slot time is changed by tg3_setup_phy if we
2117                          * run at gigabit with half duplex.
2118                          */
2119                         MAC_TX_LENGTHS, 
2120                         (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2121                         (6 << TX_LENGTHS_IPG_SHIFT) |
2122                         (32 << TX_LENGTHS_SLOT_TIME_SHIFT),
2123                         
2124                         /* Receive rules. */
2125                         MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS,
2126                         RCVLPC_CONFIG, 0x0181,
2127                         
2128                         /* Receive/send statistics. */
2129                         RCVLPC_STATS_ENABLE, 0xffffff,
2130                         RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE,
2131                         SNDDATAI_STATSENAB, 0xffffff,
2132                         SNDDATAI_STATSCTRL, (SNDDATAI_SCTRL_ENABLE |SNDDATAI_SCTRL_FASTUPD),
2133                         
2134                         /* Host coalescing engine */
2135                         HOSTCC_RXCOL_TICKS, 0,
2136                         HOSTCC_TXCOL_TICKS, LOW_TXCOL_TICKS,
2137                         HOSTCC_RXMAX_FRAMES, 1,
2138                         HOSTCC_TXMAX_FRAMES, LOW_RXMAX_FRAMES,
2139                         HOSTCC_RXCOAL_MAXF_INT, 1,
2140                         HOSTCC_TXCOAL_MAXF_INT, 0,
2141                         
2142                         /* Status/statistics block address. */
2143                         /* Etherboot lives below 4GB, so HIGH == 0 */
2144                         HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, 0,
2145
2146                         /* No need to enable 32byte coalesce mode. */
2147                         HOSTCC_MODE, HOSTCC_MODE_ENABLE | 0,
2148                         
2149                         RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE,
2150                         RCVLPC_MODE, RCVLPC_MODE_ENABLE,
2151                         
2152                         RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE,
2153
2154                         SNDDATAC_MODE, SNDDATAC_MODE_ENABLE,
2155                         SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE,
2156                         RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB,
2157                         RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ,
2158                         SNDDATAI_MODE, SNDDATAI_MODE_ENABLE,
2159                         SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE,
2160                         SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE,
2161                         
2162                         /* Accept all multicast frames. */
2163                         MAC_HASH_REG_0, 0xffffffff,
2164                         MAC_HASH_REG_1, 0xffffffff,
2165                         MAC_HASH_REG_2, 0xffffffff,
2166                         MAC_HASH_REG_3, 0xffffffff,
2167                 };
2168                 static const uint32_t table_not_5705[] = {
2169                         /* Host coalescing engine */
2170                         HOSTCC_RXCOAL_TICK_INT, 0,
2171                         HOSTCC_TXCOAL_TICK_INT, 0,
2172
2173                         /* Status/statistics block address. */
2174                         /* Etherboot lives below 4GB, so HIGH == 0 */
2175                         HOSTCC_STAT_COAL_TICKS, DEFAULT_STAT_COAL_TICKS,
2176                         HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, 0,
2177                         HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK,
2178                         HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK,
2179
2180                         RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE,
2181
2182                         MBFREE_MODE, MBFREE_MODE_ENABLE,
2183                 };
2184                 TG3_WRITE_SETTINGS(table_all);
2185                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
2186                         virt_to_bus(tp->hw_stats));
2187                 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
2188                         virt_to_bus(tp->hw_status));
2189                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
2190                         TG3_WRITE_SETTINGS(table_not_5705);
2191                 }
2192         }
2193
2194         tp->tx_mode = TX_MODE_ENABLE;
2195         tw32_carefully(MAC_TX_MODE, tp->tx_mode);
2196
2197         tp->rx_mode = RX_MODE_ENABLE;
2198         tw32_carefully(MAC_RX_MODE, tp->rx_mode);
2199
2200         tp->mi_mode = MAC_MI_MODE_BASE;
2201         tw32_carefully(MAC_MI_MODE, tp->mi_mode);
2202
2203         tw32(MAC_LED_CTRL, 0);
2204         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2205         if (tp->phy_id == PHY_ID_SERDES) {
2206                 tw32_carefully(MAC_RX_MODE, RX_MODE_RESET);
2207         }
2208         tp->rx_mode |= RX_MODE_KEEP_VLAN_TAG; /* drop tagged vlan packets */
2209         tw32_carefully(MAC_RX_MODE, tp->rx_mode);
2210
2211         if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
2212                 tw32(MAC_SERDES_CFG, 0x616000);
2213
2214         /* Prevent chip from dropping frames when flow control
2215          * is enabled.
2216          */
2217         tw32(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
2218         tr32(MAC_LOW_WMARK_MAX_RX_FRAME);
2219
2220         err = tg3_setup_phy(tp);
2221
2222         /* Ignore CRC stats */
2223
2224         /* Initialize receive rules. */
2225         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
2226         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
2227         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
2228         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
2229
2230         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
2231             || (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750))
2232                 limit = 8;
2233         else
2234                 limit = 16;
2235         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
2236                 limit -= 4;
2237         switch (limit) {
2238         case 16:        tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
2239         case 15:        tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
2240         case 14:        tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
2241         case 13:        tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
2242         case 12:        tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
2243         case 11:        tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
2244         case 10:        tw32(MAC_RCV_RULE_9,  0);  tw32(MAC_RCV_VALUE_9,  0);
2245         case 9:         tw32(MAC_RCV_RULE_8,  0);  tw32(MAC_RCV_VALUE_8,  0);
2246         case 8:         tw32(MAC_RCV_RULE_7,  0);  tw32(MAC_RCV_VALUE_7,  0);
2247         case 7:         tw32(MAC_RCV_RULE_6,  0);  tw32(MAC_RCV_VALUE_6,  0);
2248         case 6:         tw32(MAC_RCV_RULE_5,  0);  tw32(MAC_RCV_VALUE_5,  0);
2249         case 5:         tw32(MAC_RCV_RULE_4,  0);  tw32(MAC_RCV_VALUE_4,  0);
2250         case 4:         /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
2251         case 3:         /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
2252         case 2:
2253         case 1:
2254         default:
2255                 break;
2256         };
2257
2258         return err;
2259 }
2260
2261
2262
2263 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
2264 static void tg3_nvram_init(struct tg3 *tp)
2265 {
2266         tw32(GRC_EEPROM_ADDR,
2267              (EEPROM_ADDR_FSM_RESET |
2268               (EEPROM_DEFAULT_CLOCK_PERIOD <<
2269                EEPROM_ADDR_CLKPERD_SHIFT)));
2270
2271         mdelay(1);
2272
2273         /* Enable seeprom accesses. */
2274         tw32_carefully(GRC_LOCAL_CTRL,
2275                 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
2276
2277         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2278             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2279                 uint32_t nvcfg1 = tr32(NVRAM_CFG1);
2280
2281                 tp->tg3_flags |= TG3_FLAG_NVRAM;
2282                 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
2283                         if (nvcfg1 & NVRAM_CFG1_BUFFERED_MODE)
2284                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
2285                 } else {
2286                         nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
2287                         tw32(NVRAM_CFG1, nvcfg1);
2288                 }
2289
2290         } else {
2291                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
2292         }
2293 }
2294
2295
2296 static int tg3_nvram_read_using_eeprom(
2297         struct tg3 *tp __unused, uint32_t offset, uint32_t *val)
2298 {
2299         uint32_t tmp;
2300         int i;
2301
2302         if (offset > EEPROM_ADDR_ADDR_MASK ||
2303                 (offset % 4) != 0) {
2304                 return -EINVAL;
2305         }
2306
2307         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2308                                         EEPROM_ADDR_DEVID_MASK |
2309                                         EEPROM_ADDR_READ);
2310         tw32(GRC_EEPROM_ADDR,
2311              tmp |
2312              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2313              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2314               EEPROM_ADDR_ADDR_MASK) |
2315              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2316
2317         for (i = 0; i < 10000; i++) {
2318                 tmp = tr32(GRC_EEPROM_ADDR);
2319
2320                 if (tmp & EEPROM_ADDR_COMPLETE)
2321                         break;
2322                 udelay(100);
2323         }
2324         if (!(tmp & EEPROM_ADDR_COMPLETE)) {
2325                 return -EBUSY;
2326         }
2327
2328         *val = tr32(GRC_EEPROM_DATA);
2329         return 0;
2330 }
2331
2332 static int tg3_nvram_read(struct tg3 *tp, uint32_t offset, uint32_t *val)
2333 {
2334         int i, saw_done_clear;
2335
2336         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2337                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2338
2339         if (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED)
2340                 offset = ((offset / NVRAM_BUFFERED_PAGE_SIZE) <<
2341                           NVRAM_BUFFERED_PAGE_POS) +
2342                         (offset % NVRAM_BUFFERED_PAGE_SIZE);
2343
2344         if (offset > NVRAM_ADDR_MSK)
2345                 return -EINVAL;
2346
2347         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2348         for (i = 0; i < 1000; i++) {
2349                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2350                         break;
2351                 udelay(20);
2352         }
2353
2354         tw32(NVRAM_ADDR, offset);
2355         tw32(NVRAM_CMD,
2356              NVRAM_CMD_RD | NVRAM_CMD_GO |
2357              NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2358
2359         /* Wait for done bit to clear then set again. */
2360         saw_done_clear = 0;
2361         for (i = 0; i < 1000; i++) {
2362                 udelay(10);
2363                 if (!saw_done_clear &&
2364                     !(tr32(NVRAM_CMD) & NVRAM_CMD_DONE))
2365                         saw_done_clear = 1;
2366                 else if (saw_done_clear &&
2367                          (tr32(NVRAM_CMD) & NVRAM_CMD_DONE))
2368                         break;
2369         }
2370         if (i >= 1000) {
2371                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2372                 return -EBUSY;
2373         }
2374
2375         *val = bswap_32(tr32(NVRAM_RDDATA));
2376         tw32(NVRAM_SWARB, 0x20);
2377
2378         return 0;
2379 }
2380
2381 struct subsys_tbl_ent {
2382         uint16_t subsys_vendor, subsys_devid;
2383         uint32_t phy_id;
2384 };
2385
2386 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
2387         /* Broadcom boards. */
2388         { 0x14e4, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
2389         { 0x14e4, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
2390         { 0x14e4, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
2391         { 0x14e4, 0x0003, PHY_ID_SERDES  }, /* BCM95700A9 */
2392         { 0x14e4, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
2393         { 0x14e4, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
2394         { 0x14e4, 0x0007, PHY_ID_SERDES  }, /* BCM95701A7 */
2395         { 0x14e4, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
2396         { 0x14e4, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
2397         { 0x14e4, 0x0009, PHY_ID_BCM5701 }, /* BCM95703Ax1 */
2398         { 0x14e4, 0x8009, PHY_ID_BCM5701 }, /* BCM95703Ax2 */
2399
2400         /* 3com boards. */
2401         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
2402         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
2403         /* { PCI_VENDOR_ID_3COM, 0x1002, PHY_ID_XXX },     3C996CT */
2404         /* { PCI_VENDOR_ID_3COM, 0x1003, PHY_ID_XXX },     3C997T */
2405         { PCI_VENDOR_ID_3COM, 0x1004, PHY_ID_SERDES  }, /* 3C996SX */
2406         /* { PCI_VENDOR_ID_3COM, 0x1005, PHY_ID_XXX },     3C997SZ */
2407         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
2408         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
2409
2410         /* DELL boards. */
2411         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
2412         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
2413         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
2414         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
2415         { PCI_VENDOR_ID_DELL, 0x0179, PHY_ID_BCM5751 }, /* EtherXpress */
2416
2417         /* Compaq boards. */
2418         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
2419         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
2420         { PCI_VENDOR_ID_COMPAQ, 0x007d, PHY_ID_SERDES  }, /* CHANGELING */
2421         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
2422         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }  /* NC7780_2 */
2423 };
2424
2425 static int tg3_phy_probe(struct tg3 *tp)
2426 {
2427         uint32_t eeprom_phy_id, hw_phy_id_1, hw_phy_id_2;
2428         uint32_t hw_phy_id, hw_phy_id_masked;
2429         enum phy_led_mode eeprom_led_mode;
2430         uint32_t val;
2431         unsigned i;
2432         int eeprom_signature_found, err;
2433
2434         tp->phy_id = PHY_ID_INVALID;
2435
2436         for (i = 0; i < sizeof(subsys_id_to_phy_id)/sizeof(subsys_id_to_phy_id[0]); i++) {
2437                 if ((subsys_id_to_phy_id[i].subsys_vendor == tp->subsystem_vendor) &&
2438                         (subsys_id_to_phy_id[i].subsys_devid == tp->subsystem_device)) {
2439                         tp->phy_id = subsys_id_to_phy_id[i].phy_id;
2440                         break;
2441                 }
2442         }
2443
2444         eeprom_phy_id = PHY_ID_INVALID;
2445         eeprom_led_mode = led_mode_auto;
2446         eeprom_signature_found = 0;
2447         tg3_read_mem(NIC_SRAM_DATA_SIG, &val);
2448         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
2449                 uint32_t nic_cfg;
2450
2451                 tg3_read_mem(NIC_SRAM_DATA_CFG, &nic_cfg);
2452                 tp->nic_sram_data_cfg = nic_cfg;
2453
2454                 eeprom_signature_found = 1;
2455
2456                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
2457                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER) {
2458                         eeprom_phy_id = PHY_ID_SERDES;
2459                 } else {
2460                         uint32_t nic_phy_id;
2461
2462                         tg3_read_mem(NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
2463                         if (nic_phy_id != 0) {
2464                                 uint32_t id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
2465                                 uint32_t id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
2466
2467                                 eeprom_phy_id  = (id1 >> 16) << 10;
2468                                 eeprom_phy_id |= (id2 & 0xfc00) << 16;
2469                                 eeprom_phy_id |= (id2 & 0x03ff) <<  0;
2470                         }
2471                 }
2472
2473                 switch (nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK) {
2474                 case NIC_SRAM_DATA_CFG_LED_TRIPLE_SPD:
2475                         eeprom_led_mode = led_mode_three_link;
2476                         break;
2477
2478                 case NIC_SRAM_DATA_CFG_LED_LINK_SPD:
2479                         eeprom_led_mode = led_mode_link10;
2480                         break;
2481
2482                 default:
2483                         eeprom_led_mode = led_mode_auto;
2484                         break;
2485                 };
2486                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) ||
2487                         (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
2488                         (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) &&
2489                         (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP)) {
2490                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
2491                 }
2492
2493                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE)
2494                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
2495                 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
2496                         tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
2497         }
2498
2499         /* Now read the physical PHY_ID from the chip and verify
2500          * that it is sane.  If it doesn't look good, we fall back
2501          * to either the hard-coded table based PHY_ID and failing
2502          * that the value found in the eeprom area.
2503          */
2504         err  = tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
2505         err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
2506
2507         hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
2508         hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
2509         hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
2510
2511         hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
2512
2513         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
2514                 tp->phy_id = hw_phy_id;
2515         } else {
2516                 /* phy_id currently holds the value found in the
2517                  * subsys_id_to_phy_id[] table or PHY_ID_INVALID
2518                  * if a match was not found there.
2519                  */
2520                 if (tp->phy_id == PHY_ID_INVALID) {
2521                         if (!eeprom_signature_found ||
2522                             !KNOWN_PHY_ID(eeprom_phy_id & PHY_ID_MASK))
2523                                 return -ENODEV;
2524                         tp->phy_id = eeprom_phy_id;
2525                 }
2526         }
2527
2528         err = tg3_phy_reset(tp);
2529         if (err)
2530                 return err;
2531
2532         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2533             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
2534                 uint32_t mii_tg3_ctrl;
2535                 
2536                 /* These chips, when reset, only advertise 10Mb
2537                  * capabilities.  Fix that.
2538                  */
2539                 err  = tg3_writephy(tp, MII_ADVERTISE,
2540                                     (ADVERTISE_CSMA |
2541                                      ADVERTISE_PAUSE_CAP |
2542                                      ADVERTISE_10HALF |
2543                                      ADVERTISE_10FULL |
2544                                      ADVERTISE_100HALF |
2545                                      ADVERTISE_100FULL));
2546                 mii_tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
2547                                 MII_TG3_CTRL_ADV_1000_FULL |
2548                                 MII_TG3_CTRL_AS_MASTER |
2549                                 MII_TG3_CTRL_ENABLE_AS_MASTER);
2550                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2551                         mii_tg3_ctrl = 0;
2552
2553                 err |= tg3_writephy(tp, MII_TG3_CTRL, mii_tg3_ctrl);
2554                 err |= tg3_writephy(tp, MII_BMCR,
2555                                     (BMCR_ANRESTART | BMCR_ANENABLE));
2556         }
2557
2558         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
2559                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2560                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2561                 tg3_writedsp(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
2562         }
2563
2564         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2565                 tg3_writephy(tp, 0x1c, 0x8d68);
2566                 tg3_writephy(tp, 0x1c, 0x8d68);
2567         }
2568
2569         /* Enable Ethernet@WireSpeed */
2570         tg3_phy_set_wirespeed(tp);
2571
2572         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
2573                 err = tg3_init_5401phy_dsp(tp);
2574         }
2575
2576         /* Determine the PHY led mode. 
2577          * Be careful if this gets set wrong it can result in an inability to 
2578          * establish a link.
2579          */
2580         if (tp->phy_id == PHY_ID_SERDES) {
2581                 tp->led_mode = led_mode_three_link;
2582         }
2583         else if (tp->subsystem_vendor == PCI_VENDOR_ID_DELL) {
2584                 tp->led_mode = led_mode_link10;
2585         } else {
2586                 tp->led_mode = led_mode_three_link;
2587                 if (eeprom_signature_found &&
2588                     eeprom_led_mode != led_mode_auto)
2589                         tp->led_mode = eeprom_led_mode;
2590         }
2591
2592         if (tp->phy_id == PHY_ID_SERDES)
2593                 tp->link_config.advertising =
2594                         (ADVERTISED_1000baseT_Half |
2595                          ADVERTISED_1000baseT_Full |
2596                          ADVERTISED_Autoneg |
2597                          ADVERTISED_FIBRE);
2598         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2599                 tp->link_config.advertising &=
2600                         ~(ADVERTISED_1000baseT_Half |
2601                           ADVERTISED_1000baseT_Full);
2602
2603         return err;
2604 }
2605
2606 #if SUPPORT_PARTNO_STR
2607 static void tg3_read_partno(struct tg3 *tp)
2608 {
2609         unsigned char vpd_data[256];
2610         int i;
2611
2612         for (i = 0; i < 256; i += 4) {
2613                 uint32_t tmp;
2614
2615                 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
2616                         goto out_not_found;
2617
2618                 vpd_data[i + 0] = ((tmp >>  0) & 0xff);
2619                 vpd_data[i + 1] = ((tmp >>  8) & 0xff);
2620                 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
2621                 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
2622         }
2623
2624         /* Now parse and find the part number. */
2625         for (i = 0; i < 256; ) {
2626                 unsigned char val = vpd_data[i];
2627                 int block_end;
2628
2629                 if (val == 0x82 || val == 0x91) {
2630                         i = (i + 3 +
2631                              (vpd_data[i + 1] +
2632                               (vpd_data[i + 2] << 8)));
2633                         continue;
2634                 }
2635
2636                 if (val != 0x90)
2637                         goto out_not_found;
2638
2639                 block_end = (i + 3 +
2640                              (vpd_data[i + 1] +
2641                               (vpd_data[i + 2] << 8)));
2642                 i += 3;
2643                 while (i < block_end) {
2644                         if (vpd_data[i + 0] == 'P' &&
2645                             vpd_data[i + 1] == 'N') {
2646                                 int partno_len = vpd_data[i + 2];
2647
2648                                 if (partno_len > 24)
2649                                         goto out_not_found;
2650
2651                                 memcpy(tp->board_part_number,
2652                                        &vpd_data[i + 3],
2653                                        partno_len);
2654
2655                                 /* Success. */
2656                                 return;
2657                         }
2658                 }
2659
2660                 /* Part number not found. */
2661                 goto out_not_found;
2662         }
2663
2664 out_not_found:
2665         memcpy(tp->board_part_number, "none", sizeof("none"));
2666 }
2667 #else
2668 #define tg3_read_partno(TP) ((TP)->board_part_number[0] = '\0')
2669 #endif
2670
2671 static int tg3_get_invariants(struct tg3 *tp)
2672 {
2673         uint32_t misc_ctrl_reg;
2674         uint32_t pci_state_reg, grc_misc_cfg;
2675         uint16_t pci_cmd;
2676         uint8_t  pci_latency;
2677         uint32_t val ;
2678         int err;
2679
2680         /* Read the subsystem vendor and device ids */
2681         pci_read_config_word(tp->pdev, PCI_SUBSYSTEM_VENDOR_ID, &tp->subsystem_vendor);
2682         pci_read_config_word(tp->pdev, PCI_SUBSYSTEM_ID, &tp->subsystem_device);
2683
2684         /* The sun_5704 code needs infrastructure etherboot does have
2685          * ignore it for now.
2686          */
2687
2688         /* If we have an AMD 762 or Intel ICH/ICH0 chipset, write
2689          * reordering to the mailbox registers done by the host
2690          * controller can cause major troubles.  We read back from
2691          * every mailbox register write to force the writes to be
2692          * posted to the chip in order.
2693          *
2694          * TG3_FLAG_MBOX_WRITE_REORDER has been forced on.
2695          */
2696
2697         /* Force memory write invalidate off.  If we leave it on,
2698          * then on 5700_BX chips we have to enable a workaround.
2699          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundry
2700          * to match the cacheline size.  The Broadcom driver have this
2701          * workaround but turns MWI off all the times so never uses
2702          * it.  This seems to suggest that the workaround is insufficient.
2703          */
2704         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
2705         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
2706         /* Also, force SERR#/PERR# in PCI command. */
2707         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
2708         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
2709
2710         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
2711          * has the register indirect write enable bit set before
2712          * we try to access any of the MMIO registers.  It is also
2713          * critical that the PCI-X hw workaround situation is decided
2714          * before that as well.
2715          */
2716         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, &misc_ctrl_reg);
2717
2718         tp->pci_chip_rev_id = (misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT);
2719
2720         /* Initialize misc host control in PCI block. */
2721         tp->misc_host_ctrl |= (misc_ctrl_reg &
2722                                MISC_HOST_CTRL_CHIPREV);
2723         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
2724                                tp->misc_host_ctrl);
2725
2726         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, &pci_latency);
2727         if (pci_latency < 64) {
2728                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, 64);
2729         }
2730
2731         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &pci_state_reg);
2732
2733         /* If this is a 5700 BX chipset, and we are in PCI-X
2734          * mode, enable register write workaround.
2735          *
2736          * The workaround is to use indirect register accesses
2737          * for all chip writes not to mailbox registers.
2738          *
2739          * In etherboot to simplify things we just always use this work around.
2740          */
2741         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
2742                 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
2743         }
2744         /* Back to back register writes can cause problems on the 5701,
2745          * the workaround is to read back all reg writes except those to
2746          * mailbox regs.
2747          * In etherboot we always use indirect register accesses so
2748          * we don't see this.
2749          */
2750
2751         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
2752                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
2753         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
2754                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
2755
2756         /* Chip-specific fixup from Broadcom driver */
2757         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
2758             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
2759                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
2760                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
2761         }
2762
2763         /* determine if it is PCIE system */
2764         // Alf : I have no idea what this is about...
2765         // But it's definitely usefull
2766         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
2767           val = tr32(TG3PCI_MSI_CAP_ID) ;
2768           if (((val >> 8) & 0xff) == T3_PCIE_CAPABILITY_ID_REG) {
2769             val = tr32(T3_PCIE_CAPABILITY_ID_REG) ;
2770             if ((val & 0xff) == T3_PCIE_CAPABILITY_ID) {
2771               tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS ;
2772             }
2773           }
2774         }
2775
2776         /* Force the chip into D0. */
2777         tg3_set_power_state_0(tp);
2778
2779         /* Etherboot does not ask the tg3 to do checksums */
2780         /* Etherboot does not ask the tg3 to do jumbo frames */
2781         /* Ehterboot does not ask the tg3 to use WakeOnLan. */
2782
2783         /* A few boards don't want Ethernet@WireSpeed phy feature */
2784         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
2785             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
2786                 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2787                         (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
2788                         (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1))) {
2789                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
2790         }
2791
2792         /* Avoid tagged irq status etherboot does not use irqs */
2793
2794         /* Only 5701 and later support tagged irq status mode.
2795          * Also, 5788 chips cannot use tagged irq status.
2796          *
2797          * However, since etherboot does not use irqs avoid tagged irqs
2798          * status  because the interrupt condition is more difficult to
2799          * fully clear in that mode.
2800          */
2801         
2802         /* Since some 5700_AX && 5700_BX have problems with 32BYTE
2803          * coalesce_mode, and the rest work fine anything set.
2804          * Don't enable HOST_CC_MODE_32BYTE in etherboot.
2805          */
2806
2807         /* Initialize MAC MI mode, polling disabled. */
2808         tw32_carefully(MAC_MI_MODE, tp->mi_mode);
2809
2810         /* Initialize data/descriptor byte/word swapping. */
2811         tw32(GRC_MODE, tp->grc_mode);
2812
2813         tg3_switch_clocks(tp);
2814
2815         /* Clear this out for sanity. */
2816         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
2817
2818         /* Etherboot does not need to check if the PCIX_TARGET_HWBUG
2819          * is needed.  It always uses it.
2820          */
2821         
2822         udelay(50);
2823         tg3_nvram_init(tp);
2824
2825         /* The TX descriptors will reside in main memory.
2826          */
2827
2828         /* See which board we are using.
2829          */
2830         grc_misc_cfg = tr32(GRC_MISC_CFG);
2831         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
2832
2833         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
2834             grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5704CIOBE) {
2835                 tp->tg3_flags |= TG3_FLAG_SPLIT_MODE;
2836                 tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ;
2837         }
2838
2839         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
2840             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
2841              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
2842                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
2843
2844 #define PCI_DEVICE_ID_TIGON3_5901       0x170d
2845 #define PCI_DEVICE_ID_TIGON3_5901_2     0x170e
2846
2847         /* these are limited to 10/100 only */
2848         if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) &&
2849                     ((grc_misc_cfg == 0x8000) || (grc_misc_cfg == 0x4000))) ||
2850                 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2851                         (tp->pdev->vendor_id == PCI_VENDOR_ID_BROADCOM) &&
2852                         ((tp->pdev->device_id == PCI_DEVICE_ID_TIGON3_5901) ||
2853                                 (tp->pdev->device_id == PCI_DEVICE_ID_TIGON3_5901_2)))) {
2854                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
2855         }
2856
2857         err = tg3_phy_probe(tp);
2858         if (err) {
2859                 printf("phy probe failed, err %d\n", err);
2860         }
2861
2862         tg3_read_partno(tp);
2863
2864
2865         /* 5700 BX chips need to have their TX producer index mailboxes
2866          * written twice to workaround a bug.
2867          * In etherboot we do this unconditionally to simplify things.
2868          */
2869
2870         /* 5700 chips can get confused if TX buffers straddle the
2871          * 4GB address boundary in some cases.
2872          * 
2873          * In etherboot we can ignore the problem as etherboot lives below 4GB.
2874          */
2875
2876         /* In etherboot wake-on-lan is unconditionally disabled */
2877         return err;
2878 }
2879
2880 static int  tg3_get_device_address(struct tg3 *tp)
2881 {
2882         struct nic *nic = tp->nic;
2883         uint32_t hi, lo, mac_offset;
2884
2885         if (PCI_FUNC(tp->pdev->busdevfn) == 0)
2886                 mac_offset = 0x7c;
2887         else
2888                 mac_offset = 0xcc;
2889
2890         /* First try to get it from MAC address mailbox. */
2891         tg3_read_mem(NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
2892         if ((hi >> 16) == 0x484b) {
2893                 nic->node_addr[0] = (hi >>  8) & 0xff;
2894                 nic->node_addr[1] = (hi >>  0) & 0xff;
2895
2896                 tg3_read_mem(NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
2897                 nic->node_addr[2] = (lo >> 24) & 0xff;
2898                 nic->node_addr[3] = (lo >> 16) & 0xff;
2899                 nic->node_addr[4] = (lo >>  8) & 0xff;
2900                 nic->node_addr[5] = (lo >>  0) & 0xff;
2901         }
2902         /* Next, try NVRAM. */
2903         else if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
2904                  !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
2905                 nic->node_addr[0] = ((hi >> 16) & 0xff);
2906                 nic->node_addr[1] = ((hi >> 24) & 0xff);
2907                 nic->node_addr[2] = ((lo >>  0) & 0xff);
2908                 nic->node_addr[3] = ((lo >>  8) & 0xff);
2909                 nic->node_addr[4] = ((lo >> 16) & 0xff);
2910                 nic->node_addr[5] = ((lo >> 24) & 0xff);
2911         }
2912         /* Finally just fetch it out of the MAC control regs. */
2913         else {
2914                 hi = tr32(MAC_ADDR_0_HIGH);
2915                 lo = tr32(MAC_ADDR_0_LOW);
2916
2917                 nic->node_addr[5] = lo & 0xff;
2918                 nic->node_addr[4] = (lo >> 8) & 0xff;
2919                 nic->node_addr[3] = (lo >> 16) & 0xff;
2920                 nic->node_addr[2] = (lo >> 24) & 0xff;
2921                 nic->node_addr[1] = hi & 0xff;
2922                 nic->node_addr[0] = (hi >> 8) & 0xff;
2923         }
2924
2925         return 0;
2926 }
2927
2928
2929 static int tg3_setup_dma(struct tg3 *tp)
2930 {
2931         tw32(TG3PCI_CLOCK_CTRL, 0);
2932
2933         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) == 0) {
2934                 tp->dma_rwctrl =
2935                         (0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
2936                         (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT) |
2937                         (0x7 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
2938                         (0x7 << DMA_RWCTRL_READ_WATER_SHIFT) |
2939                         (0x0f << DMA_RWCTRL_MIN_DMA_SHIFT);
2940                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2941                         tp->dma_rwctrl &= ~(DMA_RWCTRL_MIN_DMA << DMA_RWCTRL_MIN_DMA_SHIFT);
2942                 }
2943         } else {
2944                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
2945                         tp->dma_rwctrl =
2946                                 (0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
2947                                 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT) |
2948                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
2949                                 (0x7 << DMA_RWCTRL_READ_WATER_SHIFT) |
2950                                 (0x00 << DMA_RWCTRL_MIN_DMA_SHIFT);
2951                 else
2952                         tp->dma_rwctrl =
2953                                 (0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
2954                                 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT) |
2955                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
2956                                 (0x3 << DMA_RWCTRL_READ_WATER_SHIFT) |
2957                                 (0x0f << DMA_RWCTRL_MIN_DMA_SHIFT);
2958
2959                 /* Wheee, some more chip bugs... */
2960                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) ||
2961                         (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)) {
2962                         uint32_t ccval = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
2963
2964                         if ((ccval == 0x6) || (ccval == 0x7)) {
2965                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
2966                         }
2967                 }
2968         }
2969
2970         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) ||
2971                 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)) {
2972                 tp->dma_rwctrl &= ~(DMA_RWCTRL_MIN_DMA << DMA_RWCTRL_MIN_DMA_SHIFT);
2973         }
2974
2975         /*
2976           Alf : Tried that, but it does not work. Should be this way though :-(
2977         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
2978           tp->dma_rwctrl |= 0x001f0000;
2979         }
2980         */
2981         tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
2982
2983         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
2984
2985         return 0;
2986 }
2987
2988 static void tg3_init_link_config(struct tg3 *tp)
2989 {
2990         tp->link_config.advertising =
2991                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2992                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
2993                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
2994                  ADVERTISED_Autoneg | ADVERTISED_MII);
2995         tp->carrier_ok = 0;
2996         tp->link_config.active_speed = SPEED_INVALID;
2997         tp->link_config.active_duplex = DUPLEX_INVALID;
2998 }
2999
3000
3001 #if SUPPORT_PHY_STR
3002 static const char * tg3_phy_string(struct tg3 *tp)
3003 {
3004         switch (tp->phy_id & PHY_ID_MASK) {
3005         case PHY_ID_BCM5400:    return "5400";
3006         case PHY_ID_BCM5401:    return "5401";
3007         case PHY_ID_BCM5411:    return "5411";
3008         case PHY_ID_BCM5701:    return "5701";
3009         case PHY_ID_BCM5703:    return "5703";
3010         case PHY_ID_BCM5704:    return "5704";
3011         case PHY_ID_BCM5705:    return "5705";
3012         case PHY_ID_BCM5750:    return "5750";
3013         case PHY_ID_BCM5751:    return "5751"; 
3014         case PHY_ID_BCM8002:    return "8002/serdes";
3015         case PHY_ID_SERDES:     return "serdes";
3016         default:                return "unknown";
3017         };
3018 }
3019 #else
3020 #define tg3_phy_string(TP) "?"
3021 #endif
3022
3023
3024 static void tg3_poll_link(struct tg3 *tp)
3025 {
3026         uint32_t mac_stat;
3027
3028         mac_stat = tr32(MAC_STATUS);
3029         if (tp->phy_id == PHY_ID_SERDES) {
3030                 if (tp->carrier_ok?
3031                         (mac_stat & MAC_STATUS_LNKSTATE_CHANGED):
3032                         (mac_stat & MAC_STATUS_PCS_SYNCED)) {
3033                         tw32_carefully(MAC_MODE, tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK);
3034                         tw32_carefully(MAC_MODE, tp->mac_mode);
3035
3036                         tg3_setup_phy(tp);
3037                 }
3038         }
3039         else {
3040                 if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED) {
3041                         tg3_setup_phy(tp);
3042                 }
3043         }
3044 }
3045
3046 /**************************************************************************
3047 POLL - Wait for a frame
3048 ***************************************************************************/
3049 static void tg3_ack_irqs(struct tg3 *tp)
3050 {
3051         if (tp->hw_status->status & SD_STATUS_UPDATED) {
3052                 /*
3053                  * writing any value to intr-mbox-0 clears PCI INTA# and
3054                  * chip-internal interrupt pending events.
3055                  * writing non-zero to intr-mbox-0 additional tells the
3056                  * NIC to stop sending us irqs, engaging "in-intr-handler"
3057                  * event coalescing.
3058                  */
3059                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 
3060                         0x00000001);
3061                 /*
3062                  * Flush PCI write.  This also guarantees that our
3063                  * status block has been flushed to host memory.
3064                  */
3065                 tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
3066                 tp->hw_status->status &= ~SD_STATUS_UPDATED;
3067         }
3068 }
3069
3070 static int tg3_poll(struct nic *nic, int retrieve)
3071 {
3072         /* return true if there's an ethernet packet ready to read */
3073         /* nic->packet should contain data on return */
3074         /* nic->packetlen should contain length of data */
3075
3076         struct tg3 *tp = &tg3;
3077         int result;
3078
3079         result = 0;
3080
3081         if ( (tp->hw_status->idx[0].rx_producer != tp->rx_rcb_ptr) && !retrieve ) 
3082           return 1;
3083
3084         tg3_ack_irqs(tp);
3085
3086         if (tp->hw_status->idx[0].rx_producer != tp->rx_rcb_ptr) {
3087                 struct tg3_rx_buffer_desc *desc;
3088                 unsigned int len;
3089                 desc = &tp->rx_rcb[tp->rx_rcb_ptr];
3090                 if ((desc->opaque & RXD_OPAQUE_RING_MASK) == RXD_OPAQUE_RING_STD) {
3091                         len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3092                         
3093                         nic->packetlen = len;
3094                         memcpy(nic->packet, bus_to_virt(desc->addr_lo), len);
3095                         result = 1;
3096                 }
3097                 tp->rx_rcb_ptr = (tp->rx_rcb_ptr + 1) % TG3_RX_RCB_RING_SIZE;
3098                 
3099                 /* ACK the status ring */
3100                 tw32_mailbox2(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, tp->rx_rcb_ptr);
3101
3102                 /* Refill RX ring. */
3103                 if (result) {
3104                         tp->rx_std_ptr = (tp->rx_std_ptr + 1) % TG3_RX_RING_SIZE;
3105                         tw32_mailbox2(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW, tp->rx_std_ptr);
3106                 }
3107         }
3108         tg3_poll_link(tp);
3109         return result;
3110 }
3111
3112 /**************************************************************************
3113 TRANSMIT - Transmit a frame
3114 ***************************************************************************/
3115 #if 0
3116 static void tg3_set_txd(struct tg3 *tp, int entry,
3117         dma_addr_t mapping, int len, uint32_t flags,
3118         uint32_t mss_and_is_end)
3119 {
3120         struct tg3_tx_buffer_desc *txd =  &tp->tx_ring[entry];
3121         int is_end = (mss_and_is_end & 0x1);
3122         if (is_end) {
3123                 flags |= TXD_FLAG_END;
3124         }
3125
3126         txd->addr_hi   = 0;
3127         txd->addr_lo   = mapping & 0xffffffff;
3128         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3129         txd->vlan_tag  = 0 << TXD_VLAN_TAG_SHIFT;
3130 }
3131 #endif
3132
3133 static void tg3_transmit(struct nic *nic, const char *dst_addr,
3134         unsigned int type, unsigned int size, const char *packet)
3135 {
3136         static int frame_idx;
3137         struct eth_frame *frame;
3138         
3139         /* send the packet to destination */
3140         struct tg3_tx_buffer_desc *txd;
3141         struct tg3 *tp;
3142         uint32_t entry;
3143         int i;
3144
3145         /* Wait until there is a free packet frame */
3146         tp = &tg3;
3147         i = 0;
3148         entry = tp->tx_prod;
3149         while((tp->hw_status->idx[0].tx_consumer != entry) &&
3150                 (tp->hw_status->idx[0].tx_consumer != PREV_TX(entry))) {
3151                 mdelay(10);     /* give the nick a chance */
3152                 poll_interruptions();
3153                 if (++i > 500) { /* timeout 5s for transmit */
3154                         printf("transmit timed out\n");
3155                         tg3_halt(tp);
3156                         tg3_setup_hw(tp);
3157                         return;
3158                 }
3159         }
3160         if (i != 0) {
3161                 printf("#");
3162         }
3163         
3164         /* Copy the packet to the our local buffer */
3165         frame = &tg3_bss.tx_frame[frame_idx];
3166         memcpy(frame[frame_idx].dst_addr, dst_addr, ETH_ALEN);
3167         memcpy(frame[frame_idx].src_addr, nic->node_addr, ETH_ALEN);
3168         frame[frame_idx].type = htons(type);
3169         memset(frame[frame_idx].data, 0, sizeof(frame[frame_idx].data));
3170         memcpy(frame[frame_idx].data, packet, size);
3171
3172         /* Setup the ring buffer entry to transmit */
3173         txd            = &tp->tx_ring[entry];
3174         txd->addr_hi   = 0; /* Etherboot runs under 4GB */
3175         txd->addr_lo   = virt_to_bus(&frame[frame_idx]);
3176         txd->len_flags = ((size + ETH_HLEN) << TXD_LEN_SHIFT) | TXD_FLAG_END;
3177         txd->vlan_tag  = 0 << TXD_VLAN_TAG_SHIFT;
3178
3179         /* Advance to the next entry */
3180         entry = NEXT_TX(entry);
3181         frame_idx ^= 1;
3182
3183         /* Packets are ready, update Tx producer idx local and on card */
3184         tw32_mailbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3185         tw32_mailbox2((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3186         tp->tx_prod = entry;
3187 }
3188
3189 /**************************************************************************
3190 DISABLE - Turn off ethernet interface
3191 ***************************************************************************/
3192 static void tg3_disable ( struct nic *nic __unused ) {
3193         struct tg3 *tp = &tg3;
3194         /* put the card in its initial state */
3195         /* This function serves 3 purposes.
3196          * This disables DMA and interrupts so we don't receive
3197          *  unexpected packets or interrupts from the card after
3198          *  etherboot has finished. 
3199          * This frees resources so etherboot may use
3200          *  this driver on another interface
3201          * This allows etherboot to reinitialize the interface
3202          *  if something is something goes wrong.
3203          */
3204         tg3_halt(tp);
3205         tp->tg3_flags &= ~(TG3_FLAG_INIT_COMPLETE|TG3_FLAG_GOT_SERDES_FLOWCTL);
3206         tp->carrier_ok = 0;
3207         iounmap((void *)tp->regs);
3208 }
3209
3210 /**************************************************************************
3211 IRQ - Enable, Disable, or Force interrupts
3212 ***************************************************************************/
3213 static void tg3_irq(struct nic *nic __unused, irq_action_t action __unused)
3214 {
3215   switch ( action ) {
3216   case DISABLE :
3217     break;
3218   case ENABLE :
3219     break;
3220   case FORCE :
3221     break;
3222   }
3223 }
3224
3225 static struct nic_operations tg3_operations = {
3226         .connect        = dummy_connect,
3227         .poll           = tg3_poll,
3228         .transmit       = tg3_transmit,
3229         .irq            = tg3_irq,
3230
3231 };
3232
3233 /**************************************************************************
3234 PROBE - Look for an adapter, this routine's visible to the outside
3235 You should omit the last argument struct pci_device * for a non-PCI NIC
3236 ***************************************************************************/
3237 static int tg3_probe ( struct nic *nic, struct pci_device *pdev ) {
3238
3239         struct tg3 *tp = &tg3;
3240         unsigned long tg3reg_base, tg3reg_len;
3241         int i, err, pm_cap;
3242
3243         memset(tp, 0, sizeof(*tp));
3244
3245         adjust_pci_device(pdev);
3246
3247         pci_fill_nic ( nic, pdev );
3248         nic->irqno  = 0;
3249
3250         /* Find power-management capability. */
3251         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3252         if (pm_cap == 0) {
3253                 printf("Cannot find PowerManagement capability, aborting.\n");
3254                 return 0;
3255         }
3256         tg3reg_base = pci_bar_start(pdev, PCI_BASE_ADDRESS_0);
3257         if (tg3reg_base == -1UL) {
3258                 printf("Unuseable bar\n");
3259                 return 0;
3260         }
3261         tg3reg_len  = pci_bar_size(pdev,  PCI_BASE_ADDRESS_0);
3262
3263         tp->pdev       = pdev;
3264         tp->nic        = nic;
3265         tp->pm_cap     = pm_cap;
3266         tp->rx_mode    = 0;
3267         tp->tx_mode    = 0;
3268         tp->mi_mode    = MAC_MI_MODE_BASE;
3269         tp->tg3_flags  = 0 & ~TG3_FLAG_INIT_COMPLETE; 
3270         
3271         /* The word/byte swap controls here control register access byte
3272          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
3273          * setting below.
3274          */
3275         tp->misc_host_ctrl =
3276                 MISC_HOST_CTRL_MASK_PCI_INT |
3277                 MISC_HOST_CTRL_WORD_SWAP |
3278                 MISC_HOST_CTRL_INDIR_ACCESS |
3279                 MISC_HOST_CTRL_PCISTATE_RW;
3280
3281         /* The NONFRM (non-frame) byte/word swap controls take effect
3282          * on descriptor entries, anything which isn't packet data.
3283          *
3284          * The StrongARM chips on the board (one for tx, one for rx)
3285          * are running in big-endian mode.
3286          */
3287         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
3288                         GRC_MODE_WSWAP_NONFRM_DATA);
3289 #if __BYTE_ORDER == __BIG_ENDIAN
3290         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
3291 #endif
3292         tp->regs = (unsigned long) ioremap(tg3reg_base, tg3reg_len);
3293         if (tp->regs == 0UL) {
3294                 printf("Cannot map device registers, aborting\n");
3295                 return 0;
3296         }
3297
3298         tg3_init_link_config(tp);
3299
3300         err = tg3_get_invariants(tp);
3301         if (err) {
3302                 printf("Problem fetching invariants of chip, aborting.\n");
3303                 goto err_out_iounmap;
3304         }
3305
3306         err = tg3_get_device_address(tp);
3307         if (err) {
3308                 printf("Could not obtain valid ethernet address, aborting.\n");
3309                 goto err_out_iounmap;
3310         }
3311         printf("Ethernet addr: %!\n", nic->node_addr);
3312
3313         tg3_setup_dma(tp);
3314
3315         /* Now that we have fully setup the chip, save away a snapshot
3316          * of the PCI config space.  We need to restore this after
3317          * GRC_MISC_CFG core clock resets and some resume events.
3318          */
3319         pci_save_state(tp->pdev, tp->pci_cfg_state);
3320
3321         printf("Tigon3 [partno(%s) rev %hx PHY(%s)] (PCI%s:%s:%s)\n",
3322                 tp->board_part_number,
3323                 tp->pci_chip_rev_id,
3324                 tg3_phy_string(tp),
3325                 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "X" : ""),
3326                 ((tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED) ?
3327                         ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "133MHz" : "66MHz") :
3328                         ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "100MHz" : "33MHz")),
3329                 ((tp->tg3_flags & TG3_FLAG_PCI_32BIT) ? "32-bit" : "64-bit"));
3330
3331
3332         err = tg3_setup_hw(tp); 
3333         if (err) {
3334                 goto err_out_disable;
3335         } 
3336         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
3337
3338         /* Wait for a reasonable time for the link to come up */
3339         tg3_poll_link(tp);
3340         for(i = 0; !tp->carrier_ok && (i < VALID_LINK_TIMEOUT*100); i++) {
3341                 mdelay(1);
3342                 tg3_poll_link(tp);
3343         }
3344         if (!tp->carrier_ok){
3345                 printf("Valid link not established\n");
3346                 goto err_out_disable;
3347         }
3348
3349         nic->nic_op     = &tg3_operations;
3350         return 1;
3351
3352  err_out_iounmap:
3353         iounmap((void *)tp->regs);
3354         return 0;
3355  err_out_disable:
3356         tg3_disable(nic);
3357         return 0;
3358 }
3359
3360
3361 static struct pci_id tg3_nics[] = {
3362 PCI_ROM(0x14e4, 0x1644, "tg3-5700",        "Broadcom Tigon 3 5700"),
3363 PCI_ROM(0x14e4, 0x1645, "tg3-5701",        "Broadcom Tigon 3 5701"),
3364 PCI_ROM(0x14e4, 0x1646, "tg3-5702",        "Broadcom Tigon 3 5702"),
3365 PCI_ROM(0x14e4, 0x1647, "tg3-5703",        "Broadcom Tigon 3 5703"),
3366 PCI_ROM(0x14e4, 0x1648, "tg3-5704",        "Broadcom Tigon 3 5704"),
3367 PCI_ROM(0x14e4, 0x164d, "tg3-5702FE",      "Broadcom Tigon 3 5702FE"),
3368 PCI_ROM(0x14e4, 0x1653, "tg3-5705",        "Broadcom Tigon 3 5705"),
3369 PCI_ROM(0x14e4, 0x1654, "tg3-5705_2",      "Broadcom Tigon 3 5705_2"),
3370 PCI_ROM(0x14e4, 0x165d, "tg3-5705M",       "Broadcom Tigon 3 5705M"),
3371 PCI_ROM(0x14e4, 0x165e, "tg3-5705M_2",     "Broadcom Tigon 3 5705M_2"),
3372 PCI_ROM(0x14e4, 0x1677, "tg3-5751",        "Broadcom Tigon 3 5751"),
3373 PCI_ROM(0x14e4, 0x1696, "tg3-5782",        "Broadcom Tigon 3 5782"),
3374 PCI_ROM(0x14e4, 0x169c, "tg3-5788",        "Broadcom Tigon 3 5788"),
3375 PCI_ROM(0x14e4, 0x16a6, "tg3-5702X",       "Broadcom Tigon 3 5702X"),
3376 PCI_ROM(0x14e4, 0x16a7, "tg3-5703X",       "Broadcom Tigon 3 5703X"),
3377 PCI_ROM(0x14e4, 0x16a8, "tg3-5704S",       "Broadcom Tigon 3 5704S"),
3378 PCI_ROM(0x14e4, 0x16c6, "tg3-5702A3",      "Broadcom Tigon 3 5702A3"),
3379 PCI_ROM(0x14e4, 0x16c7, "tg3-5703A3",      "Broadcom Tigon 3 5703A3"),
3380 PCI_ROM(0x14e4, 0x170d, "tg3-5901",        "Broadcom Tigon 3 5901"),
3381 PCI_ROM(0x14e4, 0x170e, "tg3-5901_2",      "Broadcom Tigon 3 5901_2"),
3382 PCI_ROM(0x1148, 0x4400, "tg3-9DXX",        "Syskonnect 9DXX"),
3383 PCI_ROM(0x1148, 0x4500, "tg3-9MXX",        "Syskonnect 9MXX"),
3384 PCI_ROM(0x173b, 0x03e8, "tg3-ac1000",      "Altima AC1000"),
3385 PCI_ROM(0x173b, 0x03e9, "tg3-ac1001",      "Altima AC1001"),
3386 PCI_ROM(0x173b, 0x03ea, "tg3-ac9100",      "Altima AC9100"),
3387 PCI_ROM(0x173b, 0x03eb, "tg3-ac1003",      "Altima AC1003"),
3388 };
3389
3390 PCI_DRIVER ( tg3_driver, tg3_nics, PCI_NO_CLASS );
3391
3392 DRIVER ( "TG3", nic_driver, pci_driver, tg3_driver,
3393          tg3_probe, tg3_disable );