Merge from Etherboot 5.4
[people/lynusvaz/gpxe.git] / src / drivers / net / e1000.c
1 /**************************************************************************
2 Etherboot -  BOOTP/TFTP Bootstrap Program
3 Inter Pro 1000 for Etherboot
4 Drivers are port from Intel's Linux driver e1000-4.3.15
5
6 ***************************************************************************/
7 /*******************************************************************************
8
9   
10   Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
11   
12   This program is free software; you can redistribute it and/or modify it 
13   under the terms of the GNU General Public License as published by the Free 
14   Software Foundation; either version 2 of the License, or (at your option) 
15   any later version.
16   
17   This program is distributed in the hope that it will be useful, but WITHOUT 
18   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
19   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for 
20   more details.
21   
22   You should have received a copy of the GNU General Public License along with
23   this program; if not, write to the Free Software Foundation, Inc., 59 
24   Temple Place - Suite 330, Boston, MA  02111-1307, USA.
25   
26   The full GNU General Public License is included in this distribution in the
27   file called LICENSE.
28   
29   Contact Information:
30   Linux NICS <linux.nics@intel.com>
31   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
32
33 *******************************************************************************/
34 /*
35  *  Copyright (C) Archway Digital Solutions.
36  *
37  *  written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
38  *  2/9/2002
39  *
40  *  Copyright (C) Linux Networx.
41  *  Massive upgrade to work with the new intel gigabit NICs.
42  *  <ebiederman at lnxi dot com>
43  *
44  *  Support for 82541ei & 82547ei chips from Intel's Linux driver 5.1.13 added by
45  *  Georg Baum <gbaum@users.sf.net>, sponsored by PetaMem GmbH and linkLINE Communications, Inc.
46  *
47  *  01/2004: Updated to Linux driver 5.2.22 by Georg Baum <gbaum@users.sf.net>
48  */
49
50 /* to get some global routines like printf */
51 #include "etherboot.h"
52 /* to get the interface to the body of the program */
53 #include "nic.h"
54 /* to get the PCI support functions, if this is a PCI NIC */
55 #include "pci.h"
56 #include "timer.h"
57
58 typedef unsigned char *dma_addr_t;
59
60 typedef enum {
61         FALSE = 0,
62         TRUE = 1
63 } boolean_t;
64
65 #define DEBUG 0
66
67
68 /* Some pieces of code are disabled with #if 0 ... #endif.
69  * They are not deleted to show where the etherboot driver differs
70  * from the linux driver below the function level.
71  * Some member variables of the hw struct have been eliminated
72  * and the corresponding inplace checks inserted instead.
73  * Pieces such as LED handling that we definitely don't need are deleted.
74  *
75  * Please keep the function ordering so that it is easy to produce diffs
76  * against the linux driver.
77  *
78  * The following defines should not be needed normally,
79  * but may be helpful for debugging purposes. */
80
81 /* Define this if you want to program the transmission control register
82  * the way the Linux driver does it. */
83 #undef LINUX_DRIVER_TCTL
84
85 /* Define this to behave more like the Linux driver. */
86 #undef LINUX_DRIVER
87
88 #include "e1000_hw.h"
89
90 /* NIC specific static variables go here */
91 static struct nic_operations e1000_operations;
92 static struct pci_driver e1000_driver;
93
94 static struct e1000_hw hw;
95
96 struct {
97         char tx_pool[128 + 16];
98         char rx_pool[128 + 16];
99         char packet[2096];
100 } e1000_bufs __shared;
101
102 static struct e1000_tx_desc *tx_base;
103 static struct e1000_rx_desc *rx_base;
104
105 static int tx_tail;
106 static int rx_tail, rx_last;
107
108 /* Function forward declarations */
109 static int e1000_setup_link(struct e1000_hw *hw);
110 static int e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
111 static int e1000_setup_copper_link(struct e1000_hw *hw);
112 static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
113 static void e1000_config_collision_dist(struct e1000_hw *hw);
114 static int e1000_config_mac_to_phy(struct e1000_hw *hw);
115 static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
116 static int e1000_check_for_link(struct e1000_hw *hw);
117 static int e1000_wait_autoneg(struct e1000_hw *hw);
118 static void e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed, uint16_t *duplex);
119 static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
120 static int e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
121 static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data);
122 static int e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data);
123 static void e1000_phy_hw_reset(struct e1000_hw *hw);
124 static int e1000_phy_reset(struct e1000_hw *hw);
125 static int e1000_detect_gig_phy(struct e1000_hw *hw);
126 static int e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
127 static void e1000_init_rx_addrs(struct e1000_hw *hw);
128 static void e1000_clear_vfta(struct e1000_hw *hw);
129
130 /* Printing macros... */
131
132 #define E1000_ERR(args...) printf("e1000: " args)
133
134 #if DEBUG >= 3
135 #define E1000_DBG(args...) printf("e1000: " args)
136 #else
137 #define E1000_DBG(args...)
138 #endif
139
140 #define MSGOUT(S, A, B)     printk(S "\n", A, B)
141 #if DEBUG >= 2
142 #define DEBUGFUNC(F)        DEBUGOUT(F "\n");
143 #else
144 #define DEBUGFUNC(F)
145 #endif
146 #if DEBUG >= 1
147 #define DEBUGOUT(S) printf(S)
148 #define DEBUGOUT1(S,A) printf(S,A)
149 #define DEBUGOUT2(S,A,B) printf(S,A,B)
150 #define DEBUGOUT3(S,A,B,C) printf(S,A,B,C)
151 #define DEBUGOUT7(S,A,B,C,D,E,F,G) printf(S,A,B,C,D,E,F,G)
152 #else
153 #define DEBUGOUT(S)
154 #define DEBUGOUT1(S,A)
155 #define DEBUGOUT2(S,A,B)
156 #define DEBUGOUT3(S,A,B,C)
157 #define DEBUGOUT7(S,A,B,C,D,E,F,G)
158 #endif
159
160 #define E1000_WRITE_REG(a, reg, value) ( \
161     ((a)->mac_type >= e1000_82543) ? \
162         (writel((value), ((a)->hw_addr + E1000_##reg))) : \
163         (writel((value), ((a)->hw_addr + E1000_82542_##reg))))
164
165 #define E1000_READ_REG(a, reg) ( \
166     ((a)->mac_type >= e1000_82543) ? \
167         readl((a)->hw_addr + E1000_##reg) : \
168         readl((a)->hw_addr + E1000_82542_##reg))
169
170 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \
171     ((a)->mac_type >= e1000_82543) ? \
172         writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2))) : \
173         writel((value), ((a)->hw_addr + E1000_82542_##reg + ((offset) << 2))))
174
175 #define E1000_READ_REG_ARRAY(a, reg, offset) ( \
176     ((a)->mac_type >= e1000_82543) ? \
177         readl((a)->hw_addr + E1000_##reg + ((offset) << 2)) : \
178         readl((a)->hw_addr + E1000_82542_##reg + ((offset) << 2)))
179
180 #define E1000_WRITE_FLUSH(a) {uint32_t x; x = E1000_READ_REG(a, STATUS);}
181
182
183 /******************************************************************************
184  * Inline functions from e1000_main.c of the linux driver
185  ******************************************************************************/
186
187 #if 0
188 static inline uint32_t
189 e1000_io_read(struct e1000_hw *hw __unused, uint32_t port)
190 {
191         return inl(port);
192 }
193 #endif
194
195 static inline void
196 e1000_io_write(struct e1000_hw *hw __unused, uint32_t port, uint32_t value)
197 {
198         outl(value, port);
199 }
200
201 static inline void e1000_pci_set_mwi(struct e1000_hw *hw)
202 {
203         pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
204 }
205
206 static inline void e1000_pci_clear_mwi(struct e1000_hw *hw)
207 {
208         pci_write_config_word(hw->pdev, PCI_COMMAND,
209                               hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
210 }
211
212
213 /******************************************************************************
214  * Inline functions from e1000_hw.c of the linux driver
215  ******************************************************************************/
216
217 /******************************************************************************
218 * Writes a value to one of the devices registers using port I/O (as opposed to
219 * memory mapped I/O). Only 82544 and newer devices support port I/O. *
220 * hw - Struct containing variables accessed by shared code
221 * offset - offset to write to * value - value to write
222 *****************************************************************************/
223 static inline void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset,
224                                       uint32_t value){
225         e1000_io_write(hw, hw->io_base, offset);
226         e1000_io_write(hw, hw->io_base + 4, value);
227 }
228
229
230 /******************************************************************************
231  * Functions from e1000_hw.c of the linux driver
232  ******************************************************************************/
233
234 /******************************************************************************
235  * Set the phy type member in the hw struct.
236  *
237  * hw - Struct containing variables accessed by shared code
238  *****************************************************************************/
239 static int32_t
240 e1000_set_phy_type(struct e1000_hw *hw)
241 {
242         DEBUGFUNC("e1000_set_phy_type");
243
244         switch(hw->phy_id) {
245         case M88E1000_E_PHY_ID:
246         case M88E1000_I_PHY_ID:
247         case M88E1011_I_PHY_ID:
248                 hw->phy_type = e1000_phy_m88;
249                 break;
250         case IGP01E1000_I_PHY_ID:
251                 hw->phy_type = e1000_phy_igp;
252                 break;
253         default:
254                 /* Should never have loaded on this device */
255                 hw->phy_type = e1000_phy_undefined;
256                 return -E1000_ERR_PHY_TYPE;
257         }
258
259         return E1000_SUCCESS;
260 }
261
262 /******************************************************************************
263  * IGP phy init script - initializes the GbE PHY
264  *
265  * hw - Struct containing variables accessed by shared code
266  *****************************************************************************/
267 static void
268 e1000_phy_init_script(struct e1000_hw *hw)
269 {
270         DEBUGFUNC("e1000_phy_init_script");
271
272 #if 0
273         /* See e1000_sw_init() of the Linux driver */
274         if(hw->phy_init_script) {
275 #else
276         if((hw->mac_type == e1000_82541) ||
277            (hw->mac_type == e1000_82547) ||
278            (hw->mac_type == e1000_82541_rev_2) ||
279            (hw->mac_type == e1000_82547_rev_2)) {
280 #endif
281                 mdelay(20);
282
283                 e1000_write_phy_reg(hw,0x0000,0x0140);
284
285                 mdelay(5);
286
287                 if(hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547) {
288                         e1000_write_phy_reg(hw, 0x1F95, 0x0001);
289
290                         e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
291
292                         e1000_write_phy_reg(hw, 0x1F79, 0x0018);
293
294                         e1000_write_phy_reg(hw, 0x1F30, 0x1600);
295
296                         e1000_write_phy_reg(hw, 0x1F31, 0x0014);
297
298                         e1000_write_phy_reg(hw, 0x1F32, 0x161C);
299
300                         e1000_write_phy_reg(hw, 0x1F94, 0x0003);
301
302                         e1000_write_phy_reg(hw, 0x1F96, 0x003F);
303
304                         e1000_write_phy_reg(hw, 0x2010, 0x0008);
305                 } else {
306                         e1000_write_phy_reg(hw, 0x1F73, 0x0099);
307                 }
308
309                 e1000_write_phy_reg(hw, 0x0000, 0x3300);
310
311
312                 if(hw->mac_type == e1000_82547) {
313                         uint16_t fused, fine, coarse;
314
315                         /* Move to analog registers page */
316                         e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
317
318                         if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
319                                 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
320
321                                 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
322                                 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
323
324                                 if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
325                                         coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
326                                         fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
327                                 } else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
328                                         fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
329
330                                 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
331                                         (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
332                                         (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
333
334                                 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
335                                 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
336                                                 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
337                         }
338                 }
339         }
340 }
341
342 /******************************************************************************
343  * Set the mac type member in the hw struct.
344  * 
345  * hw - Struct containing variables accessed by shared code
346  *****************************************************************************/
347 static int
348 e1000_set_mac_type(struct e1000_hw *hw)
349 {
350         DEBUGFUNC("e1000_set_mac_type");
351
352         switch (hw->device_id) {
353         case E1000_DEV_ID_82542:
354                 switch (hw->revision_id) {
355                 case E1000_82542_2_0_REV_ID:
356                         hw->mac_type = e1000_82542_rev2_0;
357                         break;
358                 case E1000_82542_2_1_REV_ID:
359                         hw->mac_type = e1000_82542_rev2_1;
360                         break;
361                 default:
362                         /* Invalid 82542 revision ID */
363                         return -E1000_ERR_MAC_TYPE;
364                 }
365                 break;
366         case E1000_DEV_ID_82543GC_FIBER:
367         case E1000_DEV_ID_82543GC_COPPER:
368                 hw->mac_type = e1000_82543;
369                 break;
370         case E1000_DEV_ID_82544EI_COPPER:
371         case E1000_DEV_ID_82544EI_FIBER:
372         case E1000_DEV_ID_82544GC_COPPER:
373         case E1000_DEV_ID_82544GC_LOM:
374                 hw->mac_type = e1000_82544;
375                 break;
376         case E1000_DEV_ID_82540EM:
377         case E1000_DEV_ID_82540EM_LOM:
378         case E1000_DEV_ID_82540EP:
379         case E1000_DEV_ID_82540EP_LOM:
380         case E1000_DEV_ID_82540EP_LP:
381                 hw->mac_type = e1000_82540;
382                 break;
383         case E1000_DEV_ID_82545EM_COPPER:
384         case E1000_DEV_ID_82545EM_FIBER:
385                 hw->mac_type = e1000_82545;
386                 break;
387         case E1000_DEV_ID_82545GM_COPPER:
388         case E1000_DEV_ID_82545GM_FIBER:
389         case E1000_DEV_ID_82545GM_SERDES:
390                 hw->mac_type = e1000_82545_rev_3;
391                 break;
392         case E1000_DEV_ID_82546EB_COPPER:
393         case E1000_DEV_ID_82546EB_FIBER:
394         case E1000_DEV_ID_82546EB_QUAD_COPPER:
395                 hw->mac_type = e1000_82546;
396                 break;
397         case E1000_DEV_ID_82546GB_COPPER:
398         case E1000_DEV_ID_82546GB_FIBER:
399         case E1000_DEV_ID_82546GB_SERDES:
400                 hw->mac_type = e1000_82546_rev_3;
401                 break;
402         case E1000_DEV_ID_82541EI:
403         case E1000_DEV_ID_82541EI_MOBILE:
404                 hw->mac_type = e1000_82541;
405                 break;
406         case E1000_DEV_ID_82541ER:
407         case E1000_DEV_ID_82541GI:
408         case E1000_DEV_ID_82541GI_MOBILE:
409                 hw->mac_type = e1000_82541_rev_2;
410                 break;
411         case E1000_DEV_ID_82547EI:
412                 hw->mac_type = e1000_82547;
413                 break;
414         case E1000_DEV_ID_82547GI:
415                 hw->mac_type = e1000_82547_rev_2;
416                 break;
417         default:
418                 /* Should never have loaded on this device */
419                 return -E1000_ERR_MAC_TYPE;
420         }
421
422         return E1000_SUCCESS;
423 }
424
425 /*****************************************************************************
426  * Set media type and TBI compatibility.
427  *
428  * hw - Struct containing variables accessed by shared code
429  * **************************************************************************/
430 static void
431 e1000_set_media_type(struct e1000_hw *hw)
432 {
433         uint32_t status;
434
435         DEBUGFUNC("e1000_set_media_type");
436         
437         if(hw->mac_type != e1000_82543) {
438                 /* tbi_compatibility is only valid on 82543 */
439                 hw->tbi_compatibility_en = FALSE;
440         }
441
442         switch (hw->device_id) {
443                 case E1000_DEV_ID_82545GM_SERDES:
444                 case E1000_DEV_ID_82546GB_SERDES:
445                         hw->media_type = e1000_media_type_internal_serdes;
446                         break;
447                 default:
448                         if(hw->mac_type >= e1000_82543) {
449                                 status = E1000_READ_REG(hw, STATUS);
450                                 if(status & E1000_STATUS_TBIMODE) {
451                                         hw->media_type = e1000_media_type_fiber;
452                                         /* tbi_compatibility not valid on fiber */
453                                         hw->tbi_compatibility_en = FALSE;
454                                 } else {
455                                         hw->media_type = e1000_media_type_copper;
456                                 }
457                         } else {
458                                 /* This is an 82542 (fiber only) */
459                                 hw->media_type = e1000_media_type_fiber;
460                         }
461         }
462 }
463
464 /******************************************************************************
465  * Reset the transmit and receive units; mask and clear all interrupts.
466  *
467  * hw - Struct containing variables accessed by shared code
468  *****************************************************************************/
469 static void
470 e1000_reset_hw(struct e1000_hw *hw)
471 {
472         uint32_t ctrl;
473         uint32_t ctrl_ext;
474         uint32_t icr;
475         uint32_t manc;
476         
477         DEBUGFUNC("e1000_reset_hw");
478         
479         /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
480         if(hw->mac_type == e1000_82542_rev2_0) {
481                 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
482                 e1000_pci_clear_mwi(hw);
483         }
484
485         /* Clear interrupt mask to stop board from generating interrupts */
486         DEBUGOUT("Masking off all interrupts\n");
487         E1000_WRITE_REG(hw, IMC, 0xffffffff);
488         
489         /* Disable the Transmit and Receive units.  Then delay to allow
490          * any pending transactions to complete before we hit the MAC with
491          * the global reset.
492          */
493         E1000_WRITE_REG(hw, RCTL, 0);
494         E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
495         E1000_WRITE_FLUSH(hw);
496
497         /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
498         hw->tbi_compatibility_on = FALSE;
499
500         /* Delay to allow any outstanding PCI transactions to complete before
501          * resetting the device
502          */ 
503         mdelay(10);
504
505         ctrl = E1000_READ_REG(hw, CTRL);
506
507         /* Must reset the PHY before resetting the MAC */
508         if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
509                 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
510                 mdelay(5);
511         }
512
513         /* Issue a global reset to the MAC.  This will reset the chip's
514          * transmit, receive, DMA, and link units.  It will not effect
515          * the current PCI configuration.  The global reset bit is self-
516          * clearing, and should clear within a microsecond.
517          */
518         DEBUGOUT("Issuing a global reset to MAC\n");
519
520         switch(hw->mac_type) {
521                 case e1000_82544:
522                 case e1000_82540:
523                 case e1000_82545:
524                 case e1000_82546:
525                 case e1000_82541:
526                 case e1000_82541_rev_2:
527                         /* These controllers can't ack the 64-bit write when issuing the
528                          * reset, so use IO-mapping as a workaround to issue the reset */
529                         E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
530                         break;
531                 case e1000_82545_rev_3:
532                 case e1000_82546_rev_3:
533                         /* Reset is performed on a shadow of the control register */
534                         E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
535                         break;
536                 default:
537                         E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
538                         break;
539         }
540
541         /* After MAC reset, force reload of EEPROM to restore power-on settings to
542          * device.  Later controllers reload the EEPROM automatically, so just wait
543          * for reload to complete.
544          */
545         switch(hw->mac_type) {
546                 case e1000_82542_rev2_0:
547                 case e1000_82542_rev2_1:
548                 case e1000_82543:
549                 case e1000_82544:
550                         /* Wait for reset to complete */
551                         udelay(10);
552                         ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
553                         ctrl_ext |= E1000_CTRL_EXT_EE_RST;
554                         E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
555                         E1000_WRITE_FLUSH(hw);
556                         /* Wait for EEPROM reload */
557                         mdelay(2);
558                         break;
559                 case e1000_82541:
560                 case e1000_82541_rev_2:
561                 case e1000_82547:
562                 case e1000_82547_rev_2:
563                         /* Wait for EEPROM reload */
564                         mdelay(20);
565                         break;
566                 default:
567                         /* Wait for EEPROM reload (it happens automatically) */
568                         mdelay(5);
569                         break;
570         }
571
572         /* Disable HW ARPs on ASF enabled adapters */
573         if(hw->mac_type >= e1000_82540) {
574                 manc = E1000_READ_REG(hw, MANC);
575                 manc &= ~(E1000_MANC_ARP_EN);
576                 E1000_WRITE_REG(hw, MANC, manc);
577         }
578
579         if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
580                 e1000_phy_init_script(hw);
581         }
582
583         /* Clear interrupt mask to stop board from generating interrupts */
584         DEBUGOUT("Masking off all interrupts\n");
585         E1000_WRITE_REG(hw, IMC, 0xffffffff);
586         
587         /* Clear any pending interrupt events. */
588         icr = E1000_READ_REG(hw, ICR);
589
590         /* If MWI was previously enabled, reenable it. */
591         if(hw->mac_type == e1000_82542_rev2_0) {
592 #ifdef LINUX_DRIVER
593                 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
594 #endif
595                         e1000_pci_set_mwi(hw);
596         }
597 }
598
599 /******************************************************************************
600  * Performs basic configuration of the adapter.
601  *
602  * hw - Struct containing variables accessed by shared code
603  * 
604  * Assumes that the controller has previously been reset and is in a 
605  * post-reset uninitialized state. Initializes the receive address registers,
606  * multicast table, and VLAN filter table. Calls routines to setup link
607  * configuration and flow control settings. Clears all on-chip counters. Leaves
608  * the transmit and receive units disabled and uninitialized.
609  *****************************************************************************/
610 static int
611 e1000_init_hw(struct e1000_hw *hw)
612 {
613         uint32_t ctrl, status;
614         uint32_t i;
615         int32_t ret_val;
616         uint16_t pcix_cmd_word;
617         uint16_t pcix_stat_hi_word;
618         uint16_t cmd_mmrbc;
619         uint16_t stat_mmrbc;
620         e1000_bus_type bus_type = e1000_bus_type_unknown;
621
622         DEBUGFUNC("e1000_init_hw");
623
624         /* Set the media type and TBI compatibility */
625         e1000_set_media_type(hw);
626
627         /* Disabling VLAN filtering. */
628         DEBUGOUT("Initializing the IEEE VLAN\n");
629         E1000_WRITE_REG(hw, VET, 0);
630         
631         e1000_clear_vfta(hw);
632         
633         /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
634         if(hw->mac_type == e1000_82542_rev2_0) {
635                 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
636                 e1000_pci_clear_mwi(hw);
637                 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
638                 E1000_WRITE_FLUSH(hw);
639                 mdelay(5);
640         }
641         
642         /* Setup the receive address. This involves initializing all of the Receive
643          * Address Registers (RARs 0 - 15).
644          */
645         e1000_init_rx_addrs(hw);
646         
647         /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
648         if(hw->mac_type == e1000_82542_rev2_0) {
649                 E1000_WRITE_REG(hw, RCTL, 0);
650                 E1000_WRITE_FLUSH(hw);
651                 mdelay(1);
652 #ifdef LINUX_DRIVER
653                 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
654 #endif
655                         e1000_pci_set_mwi(hw);
656         }
657         
658         /* Zero out the Multicast HASH table */
659         DEBUGOUT("Zeroing the MTA\n");
660         for(i = 0; i < E1000_MC_TBL_SIZE; i++)
661                 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
662         
663 #if 0
664         /* Set the PCI priority bit correctly in the CTRL register.  This
665          * determines if the adapter gives priority to receives, or if it
666          * gives equal priority to transmits and receives.
667          */
668         if(hw->dma_fairness) {
669                 ctrl = E1000_READ_REG(hw, CTRL);
670                 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
671         }
672 #endif
673
674         switch(hw->mac_type) {
675                 case e1000_82545_rev_3:
676                 case e1000_82546_rev_3:
677                         break;
678                 default:
679                         if (hw->mac_type >= e1000_82543) {
680                                 /* See e1000_get_bus_info() of the Linux driver */
681                                 status = E1000_READ_REG(hw, STATUS);
682                                 bus_type = (status & E1000_STATUS_PCIX_MODE) ?
683                                         e1000_bus_type_pcix : e1000_bus_type_pci;
684                         }
685
686                         /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
687                         if(bus_type == e1000_bus_type_pcix) {
688                                 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
689                                 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
690                                 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
691                                         PCIX_COMMAND_MMRBC_SHIFT;
692                                 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
693                                         PCIX_STATUS_HI_MMRBC_SHIFT;
694                                 if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
695                                         stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
696                                 if(cmd_mmrbc > stat_mmrbc) {
697                                         pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
698                                         pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
699                                         pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER, pcix_cmd_word);
700                                 }
701                         }
702                         break;
703         }
704
705         /* Call a subroutine to configure the link and setup flow control. */
706         ret_val = e1000_setup_link(hw);
707         
708         /* Set the transmit descriptor write-back policy */
709         if(hw->mac_type > e1000_82544) {
710                 ctrl = E1000_READ_REG(hw, TXDCTL);
711                 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
712                 E1000_WRITE_REG(hw, TXDCTL, ctrl);
713         }
714
715 #if 0
716         /* Clear all of the statistics registers (clear on read).  It is
717          * important that we do this after we have tried to establish link
718          * because the symbol error count will increment wildly if there
719          * is no link.
720          */
721         e1000_clear_hw_cntrs(hw);
722 #endif
723
724         return ret_val;
725 }
726
727 /******************************************************************************
728  * Adjust SERDES output amplitude based on EEPROM setting.
729  *
730  * hw - Struct containing variables accessed by shared code.
731  *****************************************************************************/
732 static int32_t
733 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
734 {
735         uint16_t eeprom_data;
736         int32_t  ret_val;
737
738         DEBUGFUNC("e1000_adjust_serdes_amplitude");
739
740         if(hw->media_type != e1000_media_type_internal_serdes)
741                 return E1000_SUCCESS;
742
743         switch(hw->mac_type) {
744                 case e1000_82545_rev_3:
745                 case e1000_82546_rev_3:
746                         break;
747                 default:
748                         return E1000_SUCCESS;
749         }
750
751         if ((ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,
752                                         &eeprom_data))) {
753                 return ret_val;
754         }
755
756         if(eeprom_data != EEPROM_RESERVED_WORD) {
757                 /* Adjust SERDES output amplitude only. */
758                 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
759                 if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL,
760                                                   eeprom_data)))
761                         return ret_val;
762         }
763
764         return E1000_SUCCESS;
765 }
766                                                                    
767 /******************************************************************************
768  * Configures flow control and link settings.
769  * 
770  * hw - Struct containing variables accessed by shared code
771  * 
772  * Determines which flow control settings to use. Calls the apropriate media-
773  * specific link configuration function. Configures the flow control settings.
774  * Assuming the adapter has a valid link partner, a valid link should be
775  * established. Assumes the hardware has previously been reset and the 
776  * transmitter and receiver are not enabled.
777  *****************************************************************************/
778 static int
779 e1000_setup_link(struct e1000_hw *hw)
780 {
781         uint32_t ctrl_ext;
782         int32_t ret_val;
783         uint16_t eeprom_data;
784
785         DEBUGFUNC("e1000_setup_link");
786         
787         /* Read and store word 0x0F of the EEPROM. This word contains bits
788          * that determine the hardware's default PAUSE (flow control) mode,
789          * a bit that determines whether the HW defaults to enabling or
790          * disabling auto-negotiation, and the direction of the
791          * SW defined pins. If there is no SW over-ride of the flow
792          * control setting, then the variable hw->fc will
793          * be initialized based on a value in the EEPROM.
794          */
795         if(e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data) < 0) {
796                 DEBUGOUT("EEPROM Read Error\n");
797                 return -E1000_ERR_EEPROM;
798         }
799         
800         if(hw->fc == e1000_fc_default) {
801                 if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
802                         hw->fc = e1000_fc_none;
803                 else if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 
804                         EEPROM_WORD0F_ASM_DIR)
805                         hw->fc = e1000_fc_tx_pause;
806                 else
807                         hw->fc = e1000_fc_full;
808         }
809         
810         /* We want to save off the original Flow Control configuration just
811          * in case we get disconnected and then reconnected into a different
812          * hub or switch with different Flow Control capabilities.
813          */
814         if(hw->mac_type == e1000_82542_rev2_0)
815                 hw->fc &= (~e1000_fc_tx_pause);
816
817 #if 0
818         /* See e1000_sw_init() of the Linux driver */
819         if((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
820 #else
821         if((hw->mac_type < e1000_82543) && (hw->mac_type >= e1000_82543))
822 #endif
823                 hw->fc &= (~e1000_fc_rx_pause);
824         
825 #if 0
826         hw->original_fc = hw->fc;
827 #endif
828
829         DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
830         
831         /* Take the 4 bits from EEPROM word 0x0F that determine the initial
832          * polarity value for the SW controlled pins, and setup the
833          * Extended Device Control reg with that info.
834          * This is needed because one of the SW controlled pins is used for
835          * signal detection.  So this should be done before e1000_setup_pcs_link()
836          * or e1000_phy_setup() is called.
837          */
838         if(hw->mac_type == e1000_82543) {
839                 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 
840                         SWDPIO__EXT_SHIFT);
841                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
842         }
843         
844         /* Call the necessary subroutine to configure the link. */
845         ret_val = (hw->media_type == e1000_media_type_copper) ?
846                 e1000_setup_copper_link(hw) :
847                 e1000_setup_fiber_serdes_link(hw);
848         if (ret_val < 0) {
849                 return ret_val;
850         }
851         
852         /* Initialize the flow control address, type, and PAUSE timer
853          * registers to their default values.  This is done even if flow
854          * control is disabled, because it does not hurt anything to
855          * initialize these registers.
856          */
857         DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
858         
859         E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
860         E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
861         E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
862 #if 0
863         E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
864 #else
865         E1000_WRITE_REG(hw, FCTTV, FC_DEFAULT_TX_TIMER);
866 #endif
867         
868         /* Set the flow control receive threshold registers.  Normally,
869          * these registers will be set to a default threshold that may be
870          * adjusted later by the driver's runtime code.  However, if the
871          * ability to transmit pause frames in not enabled, then these
872          * registers will be set to 0. 
873          */
874         if(!(hw->fc & e1000_fc_tx_pause)) {
875                 E1000_WRITE_REG(hw, FCRTL, 0);
876                 E1000_WRITE_REG(hw, FCRTH, 0);
877         } else {
878                 /* We need to set up the Receive Threshold high and low water marks
879                  * as well as (optionally) enabling the transmission of XON frames.
880                  */
881 #if 0
882                 if(hw->fc_send_xon) {
883                         E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
884                         E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
885                 } else {
886                         E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
887                         E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
888                 }
889 #else
890                 E1000_WRITE_REG(hw, FCRTL, (FC_DEFAULT_LO_THRESH | E1000_FCRTL_XONE));
891                 E1000_WRITE_REG(hw, FCRTH, FC_DEFAULT_HI_THRESH);
892 #endif
893         }
894         return ret_val;
895 }
896
897 /******************************************************************************
898  * Sets up link for a fiber based or serdes based adapter
899  *
900  * hw - Struct containing variables accessed by shared code
901  *
902  * Manipulates Physical Coding Sublayer functions in order to configure
903  * link. Assumes the hardware has been previously reset and the transmitter
904  * and receiver are not enabled.
905  *****************************************************************************/
906 static int
907 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
908 {
909         uint32_t ctrl;
910         uint32_t status;
911         uint32_t txcw = 0;
912         uint32_t i;
913         uint32_t signal = 0;
914         int32_t ret_val;
915
916         DEBUGFUNC("e1000_setup_fiber_serdes_link");
917
918         /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be 
919          * set when the optics detect a signal. On older adapters, it will be 
920          * cleared when there is a signal.  This applies to fiber media only.
921          * If we're on serdes media, adjust the output amplitude to value set in
922          * the EEPROM.
923          */
924         ctrl = E1000_READ_REG(hw, CTRL);
925         if(hw->media_type == e1000_media_type_fiber)
926                 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
927
928         if((ret_val = e1000_adjust_serdes_amplitude(hw)))
929                 return ret_val;
930
931         /* Take the link out of reset */
932         ctrl &= ~(E1000_CTRL_LRST);
933
934 #if 0
935         /* Adjust VCO speed to improve BER performance */
936         if((ret_val = e1000_set_vco_speed(hw)))
937                 return ret_val;
938 #endif
939
940         e1000_config_collision_dist(hw);
941         
942         /* Check for a software override of the flow control settings, and setup
943          * the device accordingly.  If auto-negotiation is enabled, then software
944          * will have to set the "PAUSE" bits to the correct value in the Tranmsit
945          * Config Word Register (TXCW) and re-start auto-negotiation.  However, if
946          * auto-negotiation is disabled, then software will have to manually 
947          * configure the two flow control enable bits in the CTRL register.
948          *
949          * The possible values of the "fc" parameter are:
950          *      0:  Flow control is completely disabled
951          *      1:  Rx flow control is enabled (we can receive pause frames, but 
952          *          not send pause frames).
953          *      2:  Tx flow control is enabled (we can send pause frames but we do
954          *          not support receiving pause frames).
955          *      3:  Both Rx and TX flow control (symmetric) are enabled.
956          */
957         switch (hw->fc) {
958         case e1000_fc_none:
959                 /* Flow control is completely disabled by a software over-ride. */
960                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
961                 break;
962         case e1000_fc_rx_pause:
963                 /* RX Flow control is enabled and TX Flow control is disabled by a 
964                  * software over-ride. Since there really isn't a way to advertise 
965                  * that we are capable of RX Pause ONLY, we will advertise that we
966                  * support both symmetric and asymmetric RX PAUSE. Later, we will
967                  *  disable the adapter's ability to send PAUSE frames.
968                  */
969                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
970                 break;
971         case e1000_fc_tx_pause:
972                 /* TX Flow control is enabled, and RX Flow control is disabled, by a 
973                  * software over-ride.
974                  */
975                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
976                 break;
977         case e1000_fc_full:
978                 /* Flow control (both RX and TX) is enabled by a software over-ride. */
979                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
980                 break;
981         default:
982                 DEBUGOUT("Flow control param set incorrectly\n");
983                 return -E1000_ERR_CONFIG;
984                 break;
985         }
986         
987         /* Since auto-negotiation is enabled, take the link out of reset (the link
988          * will be in reset, because we previously reset the chip). This will
989          * restart auto-negotiation.  If auto-neogtiation is successful then the
990          * link-up status bit will be set and the flow control enable bits (RFCE
991          * and TFCE) will be set according to their negotiated value.
992          */
993         DEBUGOUT("Auto-negotiation enabled\n");
994         
995         E1000_WRITE_REG(hw, TXCW, txcw);
996         E1000_WRITE_REG(hw, CTRL, ctrl);
997         E1000_WRITE_FLUSH(hw);
998         
999         hw->txcw = txcw;
1000         mdelay(1);
1001         
1002         /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
1003          * indication in the Device Status Register.  Time-out if a link isn't 
1004          * seen in 500 milliseconds seconds (Auto-negotiation should complete in 
1005          * less than 500 milliseconds even if the other end is doing it in SW).
1006          * For internal serdes, we just assume a signal is present, then poll.
1007          */
1008         if(hw->media_type == e1000_media_type_internal_serdes ||
1009            (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
1010                 DEBUGOUT("Looking for Link\n");
1011                 for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
1012                         mdelay(10);
1013                         status = E1000_READ_REG(hw, STATUS);
1014                         if(status & E1000_STATUS_LU) break;
1015                 }
1016                 if(i == (LINK_UP_TIMEOUT / 10)) {
1017                         DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1018                         hw->autoneg_failed = 1;
1019                         /* AutoNeg failed to achieve a link, so we'll call 
1020                          * e1000_check_for_link. This routine will force the link up if
1021                          * we detect a signal. This will allow us to communicate with
1022                          * non-autonegotiating link partners.
1023                          */
1024                         if((ret_val = e1000_check_for_link(hw))) {
1025                                 DEBUGOUT("Error while checking for link\n");
1026                                 return ret_val;
1027                         }
1028                         hw->autoneg_failed = 0;
1029                 } else {
1030                         hw->autoneg_failed = 0;
1031                         DEBUGOUT("Valid Link Found\n");
1032                 }
1033         } else {
1034                 DEBUGOUT("No Signal Detected\n");
1035         }
1036         return E1000_SUCCESS;
1037 }
1038
1039 /******************************************************************************
1040 * Detects which PHY is present and the speed and duplex
1041 *
1042 * hw - Struct containing variables accessed by shared code
1043 ******************************************************************************/
1044 static int
1045 e1000_setup_copper_link(struct e1000_hw *hw)
1046 {
1047         uint32_t ctrl;
1048         int32_t ret_val;
1049         uint16_t i;
1050         uint16_t phy_data;
1051         
1052         DEBUGFUNC("e1000_setup_copper_link");
1053         
1054         ctrl = E1000_READ_REG(hw, CTRL);
1055         /* With 82543, we need to force speed and duplex on the MAC equal to what
1056          * the PHY speed and duplex configuration is. In addition, we need to
1057          * perform a hardware reset on the PHY to take it out of reset.
1058          */
1059         if(hw->mac_type > e1000_82543) {
1060                 ctrl |= E1000_CTRL_SLU;
1061                 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1062                 E1000_WRITE_REG(hw, CTRL, ctrl);
1063         } else {
1064                 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1065                 E1000_WRITE_REG(hw, CTRL, ctrl);
1066                 e1000_phy_hw_reset(hw);
1067         }
1068         
1069         /* Make sure we have a valid PHY */
1070         if((ret_val = e1000_detect_gig_phy(hw))) {
1071                 DEBUGOUT("Error, did not detect valid phy.\n");
1072                 return ret_val;
1073         }
1074         DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
1075
1076         if(hw->mac_type <= e1000_82543 ||
1077            hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1078 #if 0
1079            hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
1080                 hw->phy_reset_disable = FALSE;
1081
1082         if(!hw->phy_reset_disable) {
1083 #else
1084            hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) {
1085 #endif
1086         if (hw->phy_type == e1000_phy_igp) {
1087
1088                 if((ret_val = e1000_phy_reset(hw))) {
1089                         DEBUGOUT("Error Resetting the PHY\n");
1090                         return ret_val;
1091                 }
1092
1093                 /* Wait 10ms for MAC to configure PHY from eeprom settings */
1094                 mdelay(15);
1095
1096 #if 0
1097                 /* disable lplu d3 during driver init */
1098                 if((ret_val = e1000_set_d3_lplu_state(hw, FALSE))) {
1099                         DEBUGOUT("Error Disabling LPLU D3\n");
1100                         return ret_val;
1101                 }
1102
1103                 /* Configure mdi-mdix settings */
1104                 if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
1105                                                  &phy_data)))
1106                         return ret_val;
1107
1108                 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1109                         hw->dsp_config_state = e1000_dsp_config_disabled;
1110                         /* Force MDI for IGP B-0 PHY */
1111                         phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX |
1112                                       IGP01E1000_PSCR_FORCE_MDI_MDIX);
1113                         hw->mdix = 1;
1114
1115                 } else {
1116                         hw->dsp_config_state = e1000_dsp_config_enabled;
1117                         phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1118
1119                         switch (hw->mdix) {
1120                         case 1:
1121                                 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1122                                 break;
1123                         case 2:
1124                                 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1125                                 break;
1126                         case 0:
1127                         default:
1128                                 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1129                                 break;
1130                         }
1131                 }
1132                 if((ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
1133                                                   phy_data)))
1134                         return ret_val;
1135
1136                 /* set auto-master slave resolution settings */
1137                 e1000_ms_type phy_ms_setting = hw->master_slave;
1138
1139                 if(hw->ffe_config_state == e1000_ffe_config_active)
1140                         hw->ffe_config_state = e1000_ffe_config_enabled;
1141
1142                 if(hw->dsp_config_state == e1000_dsp_config_activated)
1143                         hw->dsp_config_state = e1000_dsp_config_enabled;
1144 #endif
1145
1146                 /* when autonegotiation advertisment is only 1000Mbps then we
1147                  * should disable SmartSpeed and enable Auto MasterSlave
1148                  * resolution as hardware default. */
1149                 if(hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1150                         /* Disable SmartSpeed */
1151                         if((ret_val = e1000_read_phy_reg(hw,
1152                                                          IGP01E1000_PHY_PORT_CONFIG,
1153                                                          &phy_data)))
1154                                 return ret_val;
1155                         phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1156                         if((ret_val = e1000_write_phy_reg(hw,
1157                                                           IGP01E1000_PHY_PORT_CONFIG,
1158                                                           phy_data)))
1159                                 return ret_val;
1160                         /* Set auto Master/Slave resolution process */
1161                         if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
1162                                                          &phy_data)))
1163                                 return ret_val;
1164                         phy_data &= ~CR_1000T_MS_ENABLE;
1165                         if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
1166                                                           phy_data)))
1167                                 return ret_val;
1168                 }
1169
1170                 if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
1171                                                  &phy_data)))
1172                         return ret_val;
1173
1174 #if 0
1175                 /* load defaults for future use */
1176                 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1177                                             ((phy_data & CR_1000T_MS_VALUE) ?
1178                                              e1000_ms_force_master :
1179                                              e1000_ms_force_slave) :
1180                                              e1000_ms_auto;
1181
1182                 switch (phy_ms_setting) {
1183                 case e1000_ms_force_master:
1184                         phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1185                         break;
1186                 case e1000_ms_force_slave:
1187                         phy_data |= CR_1000T_MS_ENABLE;
1188                         phy_data &= ~(CR_1000T_MS_VALUE);
1189                         break;
1190                 case e1000_ms_auto:
1191                         phy_data &= ~CR_1000T_MS_ENABLE;
1192                 default:
1193                         break;
1194                 }
1195 #endif
1196
1197                 if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
1198                                                   phy_data)))
1199                         return ret_val;
1200         } else {
1201                 /* Enable CRS on TX. This must be set for half-duplex operation. */
1202                 if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1203                                                  &phy_data)))
1204                         return ret_val;
1205
1206                 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1207
1208                 /* Options:
1209                  *   MDI/MDI-X = 0 (default)
1210                  *   0 - Auto for all speeds
1211                  *   1 - MDI mode
1212                  *   2 - MDI-X mode
1213                  *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1214                  */
1215 #if 0
1216                 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1217
1218                 switch (hw->mdix) {
1219                 case 1:
1220                         phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1221                         break;
1222                 case 2:
1223                         phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1224                         break;
1225                 case 3:
1226                         phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1227                         break;
1228                 case 0:
1229                 default:
1230 #endif
1231                         phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1232 #if 0
1233                         break;
1234                 }
1235 #endif
1236
1237                 /* Options:
1238                  *   disable_polarity_correction = 0 (default)
1239                  *       Automatic Correction for Reversed Cable Polarity
1240                  *   0 - Disabled
1241                  *   1 - Enabled
1242                  */
1243                 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1244                 if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1245                                                   phy_data)))
1246                         return ret_val;
1247
1248                 /* Force TX_CLK in the Extended PHY Specific Control Register
1249                  * to 25MHz clock.
1250                  */
1251                 if((ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1252                                                  &phy_data)))
1253                         return ret_val;
1254
1255                 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1256
1257 #ifdef LINUX_DRIVER
1258                 if (hw->phy_revision < M88E1011_I_REV_4) {
1259 #endif
1260                         /* Configure Master and Slave downshift values */
1261                         phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1262                                 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1263                         phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1264                                 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1265                         if((ret_val = e1000_write_phy_reg(hw,
1266                                                           M88E1000_EXT_PHY_SPEC_CTRL,
1267                                                           phy_data)))
1268                                 return ret_val;
1269                 }
1270         
1271                 /* SW Reset the PHY so all changes take effect */
1272                 if((ret_val = e1000_phy_reset(hw))) {
1273                         DEBUGOUT("Error Resetting the PHY\n");
1274                         return ret_val;
1275 #ifdef LINUX_DRIVER
1276                 }
1277 #endif
1278         }
1279         
1280         /* Options:
1281          *   autoneg = 1 (default)
1282          *      PHY will advertise value(s) parsed from
1283          *      autoneg_advertised and fc
1284          *   autoneg = 0
1285          *      PHY will be set to 10H, 10F, 100H, or 100F
1286          *      depending on value parsed from forced_speed_duplex.
1287          */
1288         
1289         /* Is autoneg enabled?  This is enabled by default or by software
1290          * override.  If so, call e1000_phy_setup_autoneg routine to parse the
1291          * autoneg_advertised and fc options. If autoneg is NOT enabled, then
1292          * the user should have provided a speed/duplex override.  If so, then
1293          * call e1000_phy_force_speed_duplex to parse and set this up.
1294          */
1295         /* Perform some bounds checking on the hw->autoneg_advertised
1296          * parameter.  If this variable is zero, then set it to the default.
1297          */
1298         hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1299         
1300         /* If autoneg_advertised is zero, we assume it was not defaulted
1301          * by the calling code so we set to advertise full capability.
1302          */
1303         if(hw->autoneg_advertised == 0)
1304                 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1305         
1306         DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1307         if((ret_val = e1000_phy_setup_autoneg(hw))) {
1308                 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1309                 return ret_val;
1310         }
1311         DEBUGOUT("Restarting Auto-Neg\n");
1312         
1313         /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1314          * the Auto Neg Restart bit in the PHY control register.
1315          */
1316         if((ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data)))
1317                 return ret_val;
1318
1319         phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1320         if((ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data)))
1321                 return ret_val;
1322
1323 #if 0   
1324         /* Does the user want to wait for Auto-Neg to complete here, or
1325          * check at a later time (for example, callback routine).
1326          */
1327         if(hw->wait_autoneg_complete) {
1328                 if((ret_val = e1000_wait_autoneg(hw))) {
1329                         DEBUGOUT("Error while waiting for autoneg to complete\n");
1330                         return ret_val;
1331                 }
1332         }
1333 #else
1334         /* If we do not wait for autonegotiation to complete I 
1335          * do not see a valid link status.
1336          */
1337         if((ret_val = e1000_wait_autoneg(hw))) {
1338                 DEBUGOUT("Error while waiting for autoneg to complete\n");
1339                 return ret_val;
1340         }
1341 #endif
1342         } /* !hw->phy_reset_disable */
1343         
1344         /* Check link status. Wait up to 100 microseconds for link to become
1345          * valid.
1346          */
1347         for(i = 0; i < 10; i++) {
1348                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
1349                         return ret_val;
1350                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
1351                         return ret_val;
1352
1353                 if(phy_data & MII_SR_LINK_STATUS) {
1354                         /* We have link, so we need to finish the config process:
1355                          *   1) Set up the MAC to the current PHY speed/duplex
1356                          *      if we are on 82543.  If we
1357                          *      are on newer silicon, we only need to configure
1358                          *      collision distance in the Transmit Control Register.
1359                          *   2) Set up flow control on the MAC to that established with
1360                          *      the link partner.
1361                          */
1362                         if(hw->mac_type >= e1000_82544) {
1363                                 e1000_config_collision_dist(hw);
1364                         } else {
1365                                 if((ret_val = e1000_config_mac_to_phy(hw))) {
1366                                         DEBUGOUT("Error configuring MAC to PHY settings\n");
1367                                         return ret_val;
1368                                 }
1369                         }
1370                         if((ret_val = e1000_config_fc_after_link_up(hw))) {
1371                                 DEBUGOUT("Error Configuring Flow Control\n");
1372                                 return ret_val;
1373                         }
1374 #if 0
1375                         if(hw->phy_type == e1000_phy_igp) {
1376                                 if((ret_val = e1000_config_dsp_after_link_change(hw, TRUE))) {
1377                                         DEBUGOUT("Error Configuring DSP after link up\n");
1378                                         return ret_val;
1379                                 }
1380                         }
1381 #endif
1382                         DEBUGOUT("Valid link established!!!\n");
1383                         return E1000_SUCCESS;
1384                 }
1385                 udelay(10);
1386         }
1387         
1388         DEBUGOUT("Unable to establish link!!!\n");
1389         return -E1000_ERR_NOLINK;
1390 }
1391
1392 /******************************************************************************
1393 * Configures PHY autoneg and flow control advertisement settings
1394 *
1395 * hw - Struct containing variables accessed by shared code
1396 ******************************************************************************/
1397 static int
1398 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1399 {
1400         int32_t ret_val;
1401         uint16_t mii_autoneg_adv_reg;
1402         uint16_t mii_1000t_ctrl_reg;
1403
1404         DEBUGFUNC("e1000_phy_setup_autoneg");
1405         
1406         /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1407         if((ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
1408                                          &mii_autoneg_adv_reg)))
1409                 return ret_val;
1410
1411         /* Read the MII 1000Base-T Control Register (Address 9). */
1412         if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg)))
1413                 return ret_val;
1414
1415         /* Need to parse both autoneg_advertised and fc and set up
1416          * the appropriate PHY registers.  First we will parse for
1417          * autoneg_advertised software override.  Since we can advertise
1418          * a plethora of combinations, we need to check each bit
1419          * individually.
1420          */
1421         
1422         /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1423          * Advertisement Register (Address 4) and the 1000 mb speed bits in
1424          * the  1000Base-T Control Register (Address 9).
1425          */
1426         mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
1427         mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1428
1429         DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
1430
1431         /* Do we want to advertise 10 Mb Half Duplex? */
1432         if(hw->autoneg_advertised & ADVERTISE_10_HALF) {
1433                 DEBUGOUT("Advertise 10mb Half duplex\n");
1434                 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1435         }
1436
1437         /* Do we want to advertise 10 Mb Full Duplex? */
1438         if(hw->autoneg_advertised & ADVERTISE_10_FULL) {
1439                 DEBUGOUT("Advertise 10mb Full duplex\n");
1440                 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1441         }
1442
1443         /* Do we want to advertise 100 Mb Half Duplex? */
1444         if(hw->autoneg_advertised & ADVERTISE_100_HALF) {
1445                 DEBUGOUT("Advertise 100mb Half duplex\n");
1446                 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1447         }
1448
1449         /* Do we want to advertise 100 Mb Full Duplex? */
1450         if(hw->autoneg_advertised & ADVERTISE_100_FULL) {
1451                 DEBUGOUT("Advertise 100mb Full duplex\n");
1452                 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1453         }
1454
1455         /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1456         if(hw->autoneg_advertised & ADVERTISE_1000_HALF) {
1457                 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
1458         }
1459
1460         /* Do we want to advertise 1000 Mb Full Duplex? */
1461         if(hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1462                 DEBUGOUT("Advertise 1000mb Full duplex\n");
1463                 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1464         }
1465
1466         /* Check for a software override of the flow control settings, and
1467          * setup the PHY advertisement registers accordingly.  If
1468          * auto-negotiation is enabled, then software will have to set the
1469          * "PAUSE" bits to the correct value in the Auto-Negotiation
1470          * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
1471          *
1472          * The possible values of the "fc" parameter are:
1473          *      0:  Flow control is completely disabled
1474          *      1:  Rx flow control is enabled (we can receive pause frames
1475          *          but not send pause frames).
1476          *      2:  Tx flow control is enabled (we can send pause frames
1477          *          but we do not support receiving pause frames).
1478          *      3:  Both Rx and TX flow control (symmetric) are enabled.
1479          *  other:  No software override.  The flow control configuration
1480          *          in the EEPROM is used.
1481          */
1482         switch (hw->fc) {
1483         case e1000_fc_none: /* 0 */
1484                 /* Flow control (RX & TX) is completely disabled by a
1485                  * software over-ride.
1486                  */
1487                 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1488                 break;
1489         case e1000_fc_rx_pause: /* 1 */
1490                 /* RX Flow control is enabled, and TX Flow control is
1491                  * disabled, by a software over-ride.
1492                  */
1493                 /* Since there really isn't a way to advertise that we are
1494                  * capable of RX Pause ONLY, we will advertise that we
1495                  * support both symmetric and asymmetric RX PAUSE.  Later
1496                  * (in e1000_config_fc_after_link_up) we will disable the
1497                  *hw's ability to send PAUSE frames.
1498                  */
1499                 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1500                 break;
1501         case e1000_fc_tx_pause: /* 2 */
1502                 /* TX Flow control is enabled, and RX Flow control is
1503                  * disabled, by a software over-ride.
1504                  */
1505                 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1506                 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1507                 break;
1508         case e1000_fc_full: /* 3 */
1509                 /* Flow control (both RX and TX) is enabled by a software
1510                  * over-ride.
1511                  */
1512                 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1513                 break;
1514         default:
1515                 DEBUGOUT("Flow control param set incorrectly\n");
1516                 return -E1000_ERR_CONFIG;
1517         }
1518
1519         if((ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV,
1520                                mii_autoneg_adv_reg)))
1521                 return ret_val;
1522
1523         DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1524
1525         if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg)))
1526                 return ret_val;
1527
1528         return E1000_SUCCESS;
1529 }
1530
1531 /******************************************************************************
1532 * Sets the collision distance in the Transmit Control register
1533 *
1534 * hw - Struct containing variables accessed by shared code
1535 *
1536 * Link should have been established previously. Reads the speed and duplex
1537 * information from the Device Status register.
1538 ******************************************************************************/
1539 static void
1540 e1000_config_collision_dist(struct e1000_hw *hw)
1541 {
1542         uint32_t tctl;
1543
1544         tctl = E1000_READ_REG(hw, TCTL);
1545         
1546         tctl &= ~E1000_TCTL_COLD;
1547         tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
1548         
1549         E1000_WRITE_REG(hw, TCTL, tctl);
1550         E1000_WRITE_FLUSH(hw);
1551 }
1552
1553 /******************************************************************************
1554 * Sets MAC speed and duplex settings to reflect the those in the PHY
1555 *
1556 * hw - Struct containing variables accessed by shared code
1557 * mii_reg - data to write to the MII control register
1558 *
1559 * The contents of the PHY register containing the needed information need to
1560 * be passed in.
1561 ******************************************************************************/
1562 static int
1563 e1000_config_mac_to_phy(struct e1000_hw *hw)
1564 {
1565         uint32_t ctrl;
1566         int32_t ret_val;
1567         uint16_t phy_data;
1568
1569         DEBUGFUNC("e1000_config_mac_to_phy");
1570
1571         /* Read the Device Control Register and set the bits to Force Speed
1572          * and Duplex.
1573          */
1574         ctrl = E1000_READ_REG(hw, CTRL);
1575         ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1576         ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
1577
1578         /* Set up duplex in the Device Control and Transmit Control
1579          * registers depending on negotiated values.
1580          */
1581         if (hw->phy_type == e1000_phy_igp) {
1582                 if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
1583                                                  &phy_data)))
1584                         return ret_val;
1585
1586                 if(phy_data & IGP01E1000_PSSR_FULL_DUPLEX) ctrl |= E1000_CTRL_FD;
1587                 else ctrl &= ~E1000_CTRL_FD;
1588
1589                 e1000_config_collision_dist(hw);
1590
1591                 /* Set up speed in the Device Control register depending on
1592                  * negotiated values.
1593                  */
1594                 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
1595                    IGP01E1000_PSSR_SPEED_1000MBPS)
1596                         ctrl |= E1000_CTRL_SPD_1000;
1597                 else if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
1598                         IGP01E1000_PSSR_SPEED_100MBPS)
1599                         ctrl |= E1000_CTRL_SPD_100;
1600         } else {
1601                 if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
1602                                                  &phy_data)))
1603                         return ret_val;
1604                 
1605                 if(phy_data & M88E1000_PSSR_DPLX) ctrl |= E1000_CTRL_FD;
1606                 else ctrl &= ~E1000_CTRL_FD;
1607
1608                 e1000_config_collision_dist(hw);
1609
1610                 /* Set up speed in the Device Control register depending on
1611                  * negotiated values.
1612                  */
1613                 if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1614                         ctrl |= E1000_CTRL_SPD_1000;
1615                 else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
1616                         ctrl |= E1000_CTRL_SPD_100;
1617         }
1618         /* Write the configured values back to the Device Control Reg. */
1619         E1000_WRITE_REG(hw, CTRL, ctrl);
1620         return E1000_SUCCESS;
1621 }
1622
1623 /******************************************************************************
1624  * Forces the MAC's flow control settings.
1625  * 
1626  * hw - Struct containing variables accessed by shared code
1627  *
1628  * Sets the TFCE and RFCE bits in the device control register to reflect
1629  * the adapter settings. TFCE and RFCE need to be explicitly set by
1630  * software when a Copper PHY is used because autonegotiation is managed
1631  * by the PHY rather than the MAC. Software must also configure these
1632  * bits when link is forced on a fiber connection.
1633  *****************************************************************************/
1634 static int
1635 e1000_force_mac_fc(struct e1000_hw *hw)
1636 {
1637         uint32_t ctrl;
1638         
1639         DEBUGFUNC("e1000_force_mac_fc");
1640         
1641         /* Get the current configuration of the Device Control Register */
1642         ctrl = E1000_READ_REG(hw, CTRL);
1643         
1644         /* Because we didn't get link via the internal auto-negotiation
1645          * mechanism (we either forced link or we got link via PHY
1646          * auto-neg), we have to manually enable/disable transmit an
1647          * receive flow control.
1648          *
1649          * The "Case" statement below enables/disable flow control
1650          * according to the "hw->fc" parameter.
1651          *
1652          * The possible values of the "fc" parameter are:
1653          *      0:  Flow control is completely disabled
1654          *      1:  Rx flow control is enabled (we can receive pause
1655          *          frames but not send pause frames).
1656          *      2:  Tx flow control is enabled (we can send pause frames
1657          *          frames but we do not receive pause frames).
1658          *      3:  Both Rx and TX flow control (symmetric) is enabled.
1659          *  other:  No other values should be possible at this point.
1660          */
1661         
1662         switch (hw->fc) {
1663         case e1000_fc_none:
1664                 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1665                 break;
1666         case e1000_fc_rx_pause:
1667                 ctrl &= (~E1000_CTRL_TFCE);
1668                 ctrl |= E1000_CTRL_RFCE;
1669                 break;
1670         case e1000_fc_tx_pause:
1671                 ctrl &= (~E1000_CTRL_RFCE);
1672                 ctrl |= E1000_CTRL_TFCE;
1673                 break;
1674         case e1000_fc_full:
1675                 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1676                 break;
1677         default:
1678                 DEBUGOUT("Flow control param set incorrectly\n");
1679                 return -E1000_ERR_CONFIG;
1680         }
1681         
1682         /* Disable TX Flow Control for 82542 (rev 2.0) */
1683         if(hw->mac_type == e1000_82542_rev2_0)
1684                 ctrl &= (~E1000_CTRL_TFCE);
1685         
1686         E1000_WRITE_REG(hw, CTRL, ctrl);
1687         return E1000_SUCCESS;
1688 }
1689
1690 /******************************************************************************
1691  * Configures flow control settings after link is established
1692  * 
1693  * hw - Struct containing variables accessed by shared code
1694  *
1695  * Should be called immediately after a valid link has been established.
1696  * Forces MAC flow control settings if link was forced. When in MII/GMII mode
1697  * and autonegotiation is enabled, the MAC flow control settings will be set
1698  * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
1699  * and RFCE bits will be automaticaly set to the negotiated flow control mode.
1700  *****************************************************************************/
1701 static int
1702 e1000_config_fc_after_link_up(struct e1000_hw *hw)
1703 {
1704         int32_t ret_val;
1705         uint16_t mii_status_reg;
1706         uint16_t mii_nway_adv_reg;
1707         uint16_t mii_nway_lp_ability_reg;
1708         uint16_t speed;
1709         uint16_t duplex;
1710         
1711         DEBUGFUNC("e1000_config_fc_after_link_up");
1712         
1713         /* Check for the case where we have fiber media and auto-neg failed
1714          * so we had to force link.  In this case, we need to force the
1715          * configuration of the MAC to match the "fc" parameter.
1716          */
1717         if(((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
1718            ((hw->media_type == e1000_media_type_internal_serdes) && (hw->autoneg_failed))) { 
1719                 if((ret_val = e1000_force_mac_fc(hw))) {
1720                         DEBUGOUT("Error forcing flow control settings\n");
1721                         return ret_val;
1722                 }
1723         }
1724         
1725         /* Check for the case where we have copper media and auto-neg is
1726          * enabled.  In this case, we need to check and see if Auto-Neg
1727          * has completed, and if so, how the PHY and link partner has
1728          * flow control configured.
1729          */
1730         if(hw->media_type == e1000_media_type_copper) {
1731                 /* Read the MII Status Register and check to see if AutoNeg
1732                  * has completed.  We read this twice because this reg has
1733                  * some "sticky" (latched) bits.
1734                  */
1735                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
1736                         return ret_val;
1737                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
1738                         return ret_val;
1739                 
1740                 if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
1741                         /* The AutoNeg process has completed, so we now need to
1742                          * read both the Auto Negotiation Advertisement Register
1743                          * (Address 4) and the Auto_Negotiation Base Page Ability
1744                          * Register (Address 5) to determine how flow control was
1745                          * negotiated.
1746                          */
1747                         if((ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
1748                                                          &mii_nway_adv_reg)))
1749                                 return ret_val;
1750                         if((ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
1751                                                          &mii_nway_lp_ability_reg)))
1752                                 return ret_val;
1753
1754                         /* Two bits in the Auto Negotiation Advertisement Register
1755                          * (Address 4) and two bits in the Auto Negotiation Base
1756                          * Page Ability Register (Address 5) determine flow control
1757                          * for both the PHY and the link partner.  The following
1758                          * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1759                          * 1999, describes these PAUSE resolution bits and how flow
1760                          * control is determined based upon these settings.
1761                          * NOTE:  DC = Don't Care
1762                          *
1763                          *   LOCAL DEVICE  |   LINK PARTNER
1764                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1765                          *-------|---------|-------|---------|--------------------
1766                          *   0   |    0    |  DC   |   DC    | e1000_fc_none
1767                          *   0   |    1    |   0   |   DC    | e1000_fc_none
1768                          *   0   |    1    |   1   |    0    | e1000_fc_none
1769                          *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
1770                          *   1   |    0    |   0   |   DC    | e1000_fc_none
1771                          *   1   |   DC    |   1   |   DC    | e1000_fc_full
1772                          *   1   |    1    |   0   |    0    | e1000_fc_none
1773                          *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
1774                          *
1775                          */
1776                         /* Are both PAUSE bits set to 1?  If so, this implies
1777                          * Symmetric Flow Control is enabled at both ends.  The
1778                          * ASM_DIR bits are irrelevant per the spec.
1779                          *
1780                          * For Symmetric Flow Control:
1781                          *
1782                          *   LOCAL DEVICE  |   LINK PARTNER
1783                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1784                          *-------|---------|-------|---------|--------------------
1785                          *   1   |   DC    |   1   |   DC    | e1000_fc_full
1786                          *
1787                          */
1788                         if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1789                                 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1790                                 /* Now we need to check if the user selected RX ONLY
1791                                  * of pause frames.  In this case, we had to advertise
1792                                  * FULL flow control because we could not advertise RX
1793                                  * ONLY. Hence, we must now check to see if we need to
1794                                  * turn OFF  the TRANSMISSION of PAUSE frames.
1795                                  */
1796 #if 0
1797                                 if(hw->original_fc == e1000_fc_full) {
1798                                         hw->fc = e1000_fc_full;
1799 #else
1800                                 if(hw->fc == e1000_fc_full) {
1801 #endif
1802                                         DEBUGOUT("Flow Control = FULL.\r\n");
1803                                 } else {
1804                                         hw->fc = e1000_fc_rx_pause;
1805                                         DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1806                                 }
1807                         }
1808                         /* For receiving PAUSE frames ONLY.
1809                          *
1810                          *   LOCAL DEVICE  |   LINK PARTNER
1811                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1812                          *-------|---------|-------|---------|--------------------
1813                          *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
1814                          *
1815                          */
1816                         else if(!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1817                                 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1818                                 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1819                                 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1820                                 hw->fc = e1000_fc_tx_pause;
1821                                 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n");
1822                         }
1823                         /* For transmitting PAUSE frames ONLY.
1824                          *
1825                          *   LOCAL DEVICE  |   LINK PARTNER
1826                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1827                          *-------|---------|-------|---------|--------------------
1828                          *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
1829                          *
1830                          */
1831                         else if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1832                                 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1833                                 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1834                                 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1835                                 hw->fc = e1000_fc_rx_pause;
1836                                 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1837                         }
1838                         /* Per the IEEE spec, at this point flow control should be
1839                          * disabled.  However, we want to consider that we could
1840                          * be connected to a legacy switch that doesn't advertise
1841                          * desired flow control, but can be forced on the link
1842                          * partner.  So if we advertised no flow control, that is
1843                          * what we will resolve to.  If we advertised some kind of
1844                          * receive capability (Rx Pause Only or Full Flow Control)
1845                          * and the link partner advertised none, we will configure
1846                          * ourselves to enable Rx Flow Control only.  We can do
1847                          * this safely for two reasons:  If the link partner really
1848                          * didn't want flow control enabled, and we enable Rx, no
1849                          * harm done since we won't be receiving any PAUSE frames
1850                          * anyway.  If the intent on the link partner was to have
1851                          * flow control enabled, then by us enabling RX only, we
1852                          * can at least receive pause frames and process them.
1853                          * This is a good idea because in most cases, since we are
1854                          * predominantly a server NIC, more times than not we will
1855                          * be asked to delay transmission of packets than asking
1856                          * our link partner to pause transmission of frames.
1857                          */
1858 #if 0
1859                         else if(hw->original_fc == e1000_fc_none ||
1860                                 hw->original_fc == e1000_fc_tx_pause) {
1861 #else
1862                         else if(hw->fc == e1000_fc_none)
1863                                 DEBUGOUT("Flow Control = NONE.\r\n");
1864                         else if(hw->fc == e1000_fc_tx_pause) {
1865 #endif
1866                                 hw->fc = e1000_fc_none;
1867                                 DEBUGOUT("Flow Control = NONE.\r\n");
1868                         } else {
1869                                 hw->fc = e1000_fc_rx_pause;
1870                                 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1871                         }
1872                         
1873                         /* Now we need to do one last check...  If we auto-
1874                          * negotiated to HALF DUPLEX, flow control should not be
1875                          * enabled per IEEE 802.3 spec.
1876                          */
1877                         e1000_get_speed_and_duplex(hw, &speed, &duplex);
1878                         
1879                         if(duplex == HALF_DUPLEX)
1880                                 hw->fc = e1000_fc_none;
1881                         
1882                         /* Now we call a subroutine to actually force the MAC
1883                          * controller to use the correct flow control settings.
1884                          */
1885                         if((ret_val = e1000_force_mac_fc(hw))) {
1886                                 DEBUGOUT("Error forcing flow control settings\n");
1887                                 return ret_val;
1888                         }
1889                 } else {
1890                         DEBUGOUT("Copper PHY and Auto Neg has not completed.\r\n");
1891                 }
1892         }
1893         return E1000_SUCCESS;
1894 }
1895
1896 /******************************************************************************
1897  * Checks to see if the link status of the hardware has changed.
1898  *
1899  * hw - Struct containing variables accessed by shared code
1900  *
1901  * Called by any function that needs to check the link status of the adapter.
1902  *****************************************************************************/
1903 static int
1904 e1000_check_for_link(struct e1000_hw *hw)
1905 {
1906         uint32_t rxcw;
1907         uint32_t ctrl;
1908         uint32_t status;
1909         uint32_t rctl;
1910         uint32_t signal = 0;
1911         int32_t ret_val;
1912         uint16_t phy_data;
1913         uint16_t lp_capability;
1914         
1915         DEBUGFUNC("e1000_check_for_link");
1916         
1917         /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be 
1918          * set when the optics detect a signal. On older adapters, it will be 
1919          * cleared when there is a signal.  This applies to fiber media only.
1920          */
1921         if(hw->media_type == e1000_media_type_fiber)
1922                 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
1923
1924         ctrl = E1000_READ_REG(hw, CTRL);
1925         status = E1000_READ_REG(hw, STATUS);
1926         rxcw = E1000_READ_REG(hw, RXCW);
1927         
1928         /* If we have a copper PHY then we only want to go out to the PHY
1929          * registers to see if Auto-Neg has completed and/or if our link
1930          * status has changed.  The get_link_status flag will be set if we
1931          * receive a Link Status Change interrupt or we have Rx Sequence
1932          * Errors.
1933          */
1934 #if 0
1935         if((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
1936 #else
1937         if(hw->media_type == e1000_media_type_copper) {
1938 #endif
1939                 /* First we want to see if the MII Status Register reports
1940                  * link.  If so, then we want to get the current speed/duplex
1941                  * of the PHY.
1942                  * Read the register twice since the link bit is sticky.
1943                  */
1944                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
1945                         return ret_val;
1946                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
1947                         return ret_val;
1948                 
1949                 if(phy_data & MII_SR_LINK_STATUS) {
1950 #if 0
1951                         hw->get_link_status = FALSE;
1952 #endif
1953                 } else {
1954                         /* No link detected */
1955                         return -E1000_ERR_NOLINK;
1956                 }
1957
1958                 /* We have a M88E1000 PHY and Auto-Neg is enabled.  If we
1959                  * have Si on board that is 82544 or newer, Auto
1960                  * Speed Detection takes care of MAC speed/duplex
1961                  * configuration.  So we only need to configure Collision
1962                  * Distance in the MAC.  Otherwise, we need to force
1963                  * speed/duplex on the MAC to the current PHY speed/duplex
1964                  * settings.
1965                  */
1966                 if(hw->mac_type >= e1000_82544)
1967                         e1000_config_collision_dist(hw);
1968                 else {
1969                         if((ret_val = e1000_config_mac_to_phy(hw))) {
1970                                 DEBUGOUT("Error configuring MAC to PHY settings\n");
1971                                 return ret_val;
1972                         }
1973                 }
1974                 
1975                 /* Configure Flow Control now that Auto-Neg has completed. First, we 
1976                  * need to restore the desired flow control settings because we may
1977                  * have had to re-autoneg with a different link partner.
1978                  */
1979                 if((ret_val = e1000_config_fc_after_link_up(hw))) {
1980                         DEBUGOUT("Error configuring flow control\n");
1981                         return ret_val;
1982                 }
1983                 
1984                 /* At this point we know that we are on copper and we have
1985                  * auto-negotiated link.  These are conditions for checking the link
1986                  * parter capability register.  We use the link partner capability to
1987                  * determine if TBI Compatibility needs to be turned on or off.  If
1988                  * the link partner advertises any speed in addition to Gigabit, then
1989                  * we assume that they are GMII-based, and TBI compatibility is not
1990                  * needed. If no other speeds are advertised, we assume the link
1991                  * partner is TBI-based, and we turn on TBI Compatibility.
1992                  */
1993                 if(hw->tbi_compatibility_en) {
1994                         if((ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
1995                                                          &lp_capability)))
1996                                 return ret_val;
1997                         if(lp_capability & (NWAY_LPAR_10T_HD_CAPS |
1998                                 NWAY_LPAR_10T_FD_CAPS |
1999                                 NWAY_LPAR_100TX_HD_CAPS |
2000                                 NWAY_LPAR_100TX_FD_CAPS |
2001                                 NWAY_LPAR_100T4_CAPS)) {
2002                                 /* If our link partner advertises anything in addition to 
2003                                  * gigabit, we do not need to enable TBI compatibility.
2004                                  */
2005                                 if(hw->tbi_compatibility_on) {
2006                                         /* If we previously were in the mode, turn it off. */
2007                                         rctl = E1000_READ_REG(hw, RCTL);
2008                                         rctl &= ~E1000_RCTL_SBP;
2009                                         E1000_WRITE_REG(hw, RCTL, rctl);
2010                                         hw->tbi_compatibility_on = FALSE;
2011                                 }
2012                         } else {
2013                                 /* If TBI compatibility is was previously off, turn it on. For
2014                                  * compatibility with a TBI link partner, we will store bad
2015                                  * packets. Some frames have an additional byte on the end and
2016                                  * will look like CRC errors to to the hardware.
2017                                  */
2018                                 if(!hw->tbi_compatibility_on) {
2019                                         hw->tbi_compatibility_on = TRUE;
2020                                         rctl = E1000_READ_REG(hw, RCTL);
2021                                         rctl |= E1000_RCTL_SBP;
2022                                         E1000_WRITE_REG(hw, RCTL, rctl);
2023                                 }
2024                         }
2025                 }
2026         }
2027         /* If we don't have link (auto-negotiation failed or link partner cannot
2028          * auto-negotiate), the cable is plugged in (we have signal), and our
2029          * link partner is not trying to auto-negotiate with us (we are receiving
2030          * idles or data), we need to force link up. We also need to give
2031          * auto-negotiation time to complete, in case the cable was just plugged
2032          * in. The autoneg_failed flag does this.
2033          */
2034         else if((((hw->media_type == e1000_media_type_fiber) &&
2035                 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
2036                 (hw->media_type == e1000_media_type_internal_serdes)) &&
2037                 (!(status & E1000_STATUS_LU)) &&
2038                 (!(rxcw & E1000_RXCW_C))) {
2039                 if(hw->autoneg_failed == 0) {
2040                         hw->autoneg_failed = 1;
2041                         return 0;
2042                 }
2043                 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
2044                 
2045                 /* Disable auto-negotiation in the TXCW register */
2046                 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
2047                 
2048                 /* Force link-up and also force full-duplex. */
2049                 ctrl = E1000_READ_REG(hw, CTRL);
2050                 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
2051                 E1000_WRITE_REG(hw, CTRL, ctrl);
2052                 
2053                 /* Configure Flow Control after forcing link up. */
2054                 if((ret_val = e1000_config_fc_after_link_up(hw))) {
2055                         DEBUGOUT("Error configuring flow control\n");
2056                         return ret_val;
2057                 }
2058         }
2059         /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
2060          * auto-negotiation in the TXCW register and disable forced link in the
2061          * Device Control register in an attempt to auto-negotiate with our link
2062          * partner.
2063          */
2064         else if(((hw->media_type == e1000_media_type_fiber)  ||
2065                  (hw->media_type == e1000_media_type_internal_serdes)) &&
2066                 (ctrl & E1000_CTRL_SLU) &&
2067                 (rxcw & E1000_RXCW_C)) {
2068                 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
2069                 E1000_WRITE_REG(hw, TXCW, hw->txcw);
2070                 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
2071         }
2072 #if 0
2073         /* If we force link for non-auto-negotiation switch, check link status
2074          * based on MAC synchronization for internal serdes media type.
2075          */
2076         else if((hw->media_type == e1000_media_type_internal_serdes) &&
2077                         !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
2078                 /* SYNCH bit and IV bit are sticky. */
2079                 udelay(10);
2080                 if(E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
2081                         if(!(rxcw & E1000_RXCW_IV)) {
2082                                 hw->serdes_link_down = FALSE;
2083                                 DEBUGOUT("SERDES: Link is up.\n");
2084                         }
2085                 } else {
2086                         hw->serdes_link_down = TRUE;
2087                         DEBUGOUT("SERDES: Link is down.\n");
2088                 }
2089         }
2090 #endif
2091         return E1000_SUCCESS;
2092 }
2093
2094 /******************************************************************************
2095  * Detects the current speed and duplex settings of the hardware.
2096  *
2097  * hw - Struct containing variables accessed by shared code
2098  * speed - Speed of the connection
2099  * duplex - Duplex setting of the connection
2100  *****************************************************************************/
2101 static void 
2102 e1000_get_speed_and_duplex(struct e1000_hw *hw,
2103                            uint16_t *speed,
2104                            uint16_t *duplex)
2105 {
2106         uint32_t status;
2107         
2108         DEBUGFUNC("e1000_get_speed_and_duplex");
2109         
2110         if(hw->mac_type >= e1000_82543) {
2111                 status = E1000_READ_REG(hw, STATUS);
2112                 if(status & E1000_STATUS_SPEED_1000) {
2113                         *speed = SPEED_1000;
2114                         DEBUGOUT("1000 Mbs, ");
2115                 } else if(status & E1000_STATUS_SPEED_100) {
2116                         *speed = SPEED_100;
2117                         DEBUGOUT("100 Mbs, ");
2118                 } else {
2119                         *speed = SPEED_10;
2120                         DEBUGOUT("10 Mbs, ");
2121                 }
2122                 
2123                 if(status & E1000_STATUS_FD) {
2124                         *duplex = FULL_DUPLEX;
2125                         DEBUGOUT("Full Duplex\r\n");
2126                 } else {
2127                         *duplex = HALF_DUPLEX;
2128                         DEBUGOUT(" Half Duplex\r\n");
2129                 }
2130         } else {
2131                 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
2132                 *speed = SPEED_1000;
2133                 *duplex = FULL_DUPLEX;
2134         }
2135 }
2136
2137 /******************************************************************************
2138 * Blocks until autoneg completes or times out (~4.5 seconds)
2139 *
2140 * hw - Struct containing variables accessed by shared code
2141 ******************************************************************************/
2142 static int
2143 e1000_wait_autoneg(struct e1000_hw *hw)
2144 {
2145         int32_t ret_val;
2146         uint16_t i;
2147         uint16_t phy_data;
2148         
2149         DEBUGFUNC("e1000_wait_autoneg");
2150         DEBUGOUT("Waiting for Auto-Neg to complete.\n");
2151         
2152         /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2153         for(i = PHY_AUTO_NEG_TIME; i > 0; i--) {
2154                 /* Read the MII Status Register and wait for Auto-Neg
2155                  * Complete bit to be set.
2156                  */
2157                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2158                         return ret_val;
2159                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2160                         return ret_val;
2161                 if(phy_data & MII_SR_AUTONEG_COMPLETE) {
2162                         DEBUGOUT("Auto-Neg complete.\n");
2163                         return E1000_SUCCESS;
2164                 }
2165                 mdelay(100);
2166         }
2167         DEBUGOUT("Auto-Neg timedout.\n");
2168         return -E1000_ERR_TIMEOUT;
2169 }
2170
2171 /******************************************************************************
2172 * Raises the Management Data Clock
2173 *
2174 * hw - Struct containing variables accessed by shared code
2175 * ctrl - Device control register's current value
2176 ******************************************************************************/
2177 static void
2178 e1000_raise_mdi_clk(struct e1000_hw *hw,
2179                     uint32_t *ctrl)
2180 {
2181         /* Raise the clock input to the Management Data Clock (by setting the MDC
2182          * bit), and then delay 10 microseconds.
2183          */
2184         E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
2185         E1000_WRITE_FLUSH(hw);
2186         udelay(10);
2187 }
2188
2189 /******************************************************************************
2190 * Lowers the Management Data Clock
2191 *
2192 * hw - Struct containing variables accessed by shared code
2193 * ctrl - Device control register's current value
2194 ******************************************************************************/
2195 static void
2196 e1000_lower_mdi_clk(struct e1000_hw *hw,
2197                     uint32_t *ctrl)
2198 {
2199         /* Lower the clock input to the Management Data Clock (by clearing the MDC
2200          * bit), and then delay 10 microseconds.
2201          */
2202         E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
2203         E1000_WRITE_FLUSH(hw);
2204         udelay(10);
2205 }
2206
2207 /******************************************************************************
2208 * Shifts data bits out to the PHY
2209 *
2210 * hw - Struct containing variables accessed by shared code
2211 * data - Data to send out to the PHY
2212 * count - Number of bits to shift out
2213 *
2214 * Bits are shifted out in MSB to LSB order.
2215 ******************************************************************************/
2216 static void
2217 e1000_shift_out_mdi_bits(struct e1000_hw *hw,
2218                          uint32_t data,
2219                          uint16_t count)
2220 {
2221         uint32_t ctrl;
2222         uint32_t mask;
2223
2224         /* We need to shift "count" number of bits out to the PHY. So, the value
2225          * in the "data" parameter will be shifted out to the PHY one bit at a 
2226          * time. In order to do this, "data" must be broken down into bits.
2227          */
2228         mask = 0x01;
2229         mask <<= (count - 1);
2230         
2231         ctrl = E1000_READ_REG(hw, CTRL);
2232         
2233         /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
2234         ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
2235         
2236         while(mask) {
2237                 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
2238                  * then raising and lowering the Management Data Clock. A "0" is
2239                  * shifted out to the PHY by setting the MDIO bit to "0" and then
2240                  * raising and lowering the clock.
2241                  */
2242                 if(data & mask) ctrl |= E1000_CTRL_MDIO;
2243                 else ctrl &= ~E1000_CTRL_MDIO;
2244                 
2245                 E1000_WRITE_REG(hw, CTRL, ctrl);
2246                 E1000_WRITE_FLUSH(hw);
2247                 
2248                 udelay(10);
2249
2250                 e1000_raise_mdi_clk(hw, &ctrl);
2251                 e1000_lower_mdi_clk(hw, &ctrl);
2252
2253                 mask = mask >> 1;
2254         }
2255 }
2256
2257 /******************************************************************************
2258 * Shifts data bits in from the PHY
2259 *
2260 * hw - Struct containing variables accessed by shared code
2261 *
2262 * Bits are shifted in in MSB to LSB order. 
2263 ******************************************************************************/
2264 static uint16_t
2265 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
2266 {
2267         uint32_t ctrl;
2268         uint16_t data = 0;
2269         uint8_t i;
2270
2271         /* In order to read a register from the PHY, we need to shift in a total
2272          * of 18 bits from the PHY. The first two bit (turnaround) times are used
2273          * to avoid contention on the MDIO pin when a read operation is performed.
2274          * These two bits are ignored by us and thrown away. Bits are "shifted in"
2275          * by raising the input to the Management Data Clock (setting the MDC bit),
2276          * and then reading the value of the MDIO bit.
2277          */ 
2278         ctrl = E1000_READ_REG(hw, CTRL);
2279         
2280         /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
2281         ctrl &= ~E1000_CTRL_MDIO_DIR;
2282         ctrl &= ~E1000_CTRL_MDIO;
2283         
2284         E1000_WRITE_REG(hw, CTRL, ctrl);
2285         E1000_WRITE_FLUSH(hw);
2286         
2287         /* Raise and Lower the clock before reading in the data. This accounts for
2288          * the turnaround bits. The first clock occurred when we clocked out the
2289          * last bit of the Register Address.
2290          */
2291         e1000_raise_mdi_clk(hw, &ctrl);
2292         e1000_lower_mdi_clk(hw, &ctrl);
2293         
2294         for(data = 0, i = 0; i < 16; i++) {
2295                 data = data << 1;
2296                 e1000_raise_mdi_clk(hw, &ctrl);
2297                 ctrl = E1000_READ_REG(hw, CTRL);
2298                 /* Check to see if we shifted in a "1". */
2299                 if(ctrl & E1000_CTRL_MDIO) data |= 1;
2300                 e1000_lower_mdi_clk(hw, &ctrl);
2301         }
2302         
2303         e1000_raise_mdi_clk(hw, &ctrl);
2304         e1000_lower_mdi_clk(hw, &ctrl);
2305         
2306         return data;
2307 }
2308
2309 /*****************************************************************************
2310 * Reads the value from a PHY register, if the value is on a specific non zero
2311 * page, sets the page first.
2312 *
2313 * hw - Struct containing variables accessed by shared code
2314 * reg_addr - address of the PHY register to read
2315 ******************************************************************************/
2316 static int
2317 e1000_read_phy_reg(struct e1000_hw *hw,
2318                    uint32_t reg_addr,
2319                    uint16_t *phy_data)
2320 {
2321         uint32_t ret_val;
2322
2323         DEBUGFUNC("e1000_read_phy_reg");
2324
2325         if(hw->phy_type == e1000_phy_igp &&
2326            (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2327                 if((ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2328                                                      (uint16_t)reg_addr)))
2329                         return ret_val;
2330         }
2331
2332         ret_val = e1000_read_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr,
2333                                         phy_data);
2334
2335         return ret_val;
2336 }
2337
2338 static int
2339 e1000_read_phy_reg_ex(struct e1000_hw *hw,
2340                       uint32_t reg_addr,
2341                       uint16_t *phy_data)
2342 {
2343         uint32_t i;
2344         uint32_t mdic = 0;
2345         const uint32_t phy_addr = 1;
2346
2347         DEBUGFUNC("e1000_read_phy_reg_ex");
2348         
2349         if(reg_addr > MAX_PHY_REG_ADDRESS) {
2350                 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2351                 return -E1000_ERR_PARAM;
2352         }
2353         
2354         if(hw->mac_type > e1000_82543) {
2355                 /* Set up Op-code, Phy Address, and register address in the MDI
2356                  * Control register.  The MAC will take care of interfacing with the
2357                  * PHY to retrieve the desired data.
2358                  */
2359                 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
2360                         (phy_addr << E1000_MDIC_PHY_SHIFT) | 
2361                         (E1000_MDIC_OP_READ));
2362                 
2363                 E1000_WRITE_REG(hw, MDIC, mdic);
2364
2365                 /* Poll the ready bit to see if the MDI read completed */
2366                 for(i = 0; i < 64; i++) {
2367                         udelay(50);
2368                         mdic = E1000_READ_REG(hw, MDIC);
2369                         if(mdic & E1000_MDIC_READY) break;
2370                 }
2371                 if(!(mdic & E1000_MDIC_READY)) {
2372                         DEBUGOUT("MDI Read did not complete\n");
2373                         return -E1000_ERR_PHY;
2374                 }
2375                 if(mdic & E1000_MDIC_ERROR) {
2376                         DEBUGOUT("MDI Error\n");
2377                         return -E1000_ERR_PHY;
2378                 }
2379                 *phy_data = (uint16_t) mdic;
2380         } else {
2381                 /* We must first send a preamble through the MDIO pin to signal the
2382                  * beginning of an MII instruction.  This is done by sending 32
2383                  * consecutive "1" bits.
2384                  */
2385                 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2386                 
2387                 /* Now combine the next few fields that are required for a read
2388                  * operation.  We use this method instead of calling the
2389                  * e1000_shift_out_mdi_bits routine five different times. The format of
2390                  * a MII read instruction consists of a shift out of 14 bits and is
2391                  * defined as follows:
2392                  *    <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
2393                  * followed by a shift in of 18 bits.  This first two bits shifted in
2394                  * are TurnAround bits used to avoid contention on the MDIO pin when a
2395                  * READ operation is performed.  These two bits are thrown away
2396                  * followed by a shift in of 16 bits which contains the desired data.
2397                  */
2398                 mdic = ((reg_addr) | (phy_addr << 5) | 
2399                         (PHY_OP_READ << 10) | (PHY_SOF << 12));
2400                 
2401                 e1000_shift_out_mdi_bits(hw, mdic, 14);
2402                 
2403                 /* Now that we've shifted out the read command to the MII, we need to
2404                  * "shift in" the 16-bit value (18 total bits) of the requested PHY
2405                  * register address.
2406                  */
2407                 *phy_data = e1000_shift_in_mdi_bits(hw);
2408         }
2409         return E1000_SUCCESS;
2410 }
2411
2412 /******************************************************************************
2413 * Writes a value to a PHY register
2414 *
2415 * hw - Struct containing variables accessed by shared code
2416 * reg_addr - address of the PHY register to write
2417 * data - data to write to the PHY
2418 ******************************************************************************/
2419 static int 
2420 e1000_write_phy_reg(struct e1000_hw *hw,
2421                     uint32_t reg_addr,
2422                     uint16_t phy_data)
2423 {
2424         uint32_t ret_val;
2425
2426         DEBUGFUNC("e1000_write_phy_reg");
2427
2428         if(hw->phy_type == e1000_phy_igp &&
2429            (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2430                 if((ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2431                                                      (uint16_t)reg_addr)))
2432                         return ret_val;
2433         }
2434
2435         ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr,
2436                                          phy_data);
2437
2438         return ret_val;
2439 }
2440
2441 static int
2442 e1000_write_phy_reg_ex(struct e1000_hw *hw,
2443                        uint32_t reg_addr,
2444                        uint16_t phy_data)
2445 {
2446         uint32_t i;
2447         uint32_t mdic = 0;
2448         const uint32_t phy_addr = 1;
2449         
2450         DEBUGFUNC("e1000_write_phy_reg_ex");
2451         
2452         if(reg_addr > MAX_PHY_REG_ADDRESS) {
2453                 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2454                 return -E1000_ERR_PARAM;
2455         }
2456         
2457         if(hw->mac_type > e1000_82543) {
2458                 /* Set up Op-code, Phy Address, register address, and data intended
2459                  * for the PHY register in the MDI Control register.  The MAC will take
2460                  * care of interfacing with the PHY to send the desired data.
2461                  */
2462                 mdic = (((uint32_t) phy_data) |
2463                         (reg_addr << E1000_MDIC_REG_SHIFT) |
2464                         (phy_addr << E1000_MDIC_PHY_SHIFT) | 
2465                         (E1000_MDIC_OP_WRITE));
2466                 
2467                 E1000_WRITE_REG(hw, MDIC, mdic);
2468                 
2469                 /* Poll the ready bit to see if the MDI read completed */
2470                 for(i = 0; i < 640; i++) {
2471                         udelay(5);
2472                         mdic = E1000_READ_REG(hw, MDIC);
2473                         if(mdic & E1000_MDIC_READY) break;
2474                 }
2475                 if(!(mdic & E1000_MDIC_READY)) {
2476                         DEBUGOUT("MDI Write did not complete\n");
2477                         return -E1000_ERR_PHY;
2478                 }
2479         } else {
2480                 /* We'll need to use the SW defined pins to shift the write command
2481                  * out to the PHY. We first send a preamble to the PHY to signal the
2482                  * beginning of the MII instruction.  This is done by sending 32 
2483                  * consecutive "1" bits.
2484                  */
2485                 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2486                 
2487                 /* Now combine the remaining required fields that will indicate a 
2488                  * write operation. We use this method instead of calling the
2489                  * e1000_shift_out_mdi_bits routine for each field in the command. The
2490                  * format of a MII write instruction is as follows:
2491                  * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
2492                  */
2493                 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
2494                         (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
2495                 mdic <<= 16;
2496                 mdic |= (uint32_t) phy_data;
2497                 
2498                 e1000_shift_out_mdi_bits(hw, mdic, 32);
2499         }
2500
2501         return E1000_SUCCESS;
2502 }
2503
2504 /******************************************************************************
2505 * Returns the PHY to the power-on reset state
2506 *
2507 * hw - Struct containing variables accessed by shared code
2508 ******************************************************************************/
2509 static void
2510 e1000_phy_hw_reset(struct e1000_hw *hw)
2511 {
2512         uint32_t ctrl, ctrl_ext;
2513
2514         DEBUGFUNC("e1000_phy_hw_reset");
2515         
2516         DEBUGOUT("Resetting Phy...\n");
2517         
2518         if(hw->mac_type > e1000_82543) {
2519                 /* Read the device control register and assert the E1000_CTRL_PHY_RST
2520                  * bit. Then, take it out of reset.
2521                  */
2522                 ctrl = E1000_READ_REG(hw, CTRL);
2523                 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
2524                 E1000_WRITE_FLUSH(hw);
2525                 mdelay(10);
2526                 E1000_WRITE_REG(hw, CTRL, ctrl);
2527                 E1000_WRITE_FLUSH(hw);
2528         } else {
2529                 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
2530                  * bit to put the PHY into reset. Then, take it out of reset.
2531                  */
2532                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
2533                 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
2534                 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
2535                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2536                 E1000_WRITE_FLUSH(hw);
2537                 mdelay(10);
2538                 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
2539                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2540                 E1000_WRITE_FLUSH(hw);
2541         }
2542         udelay(150);
2543 }
2544
2545 /******************************************************************************
2546 * Resets the PHY
2547 *
2548 * hw - Struct containing variables accessed by shared code
2549 *
2550 * Sets bit 15 of the MII Control regiser
2551 ******************************************************************************/
2552 static int 
2553 e1000_phy_reset(struct e1000_hw *hw)
2554 {
2555         int32_t ret_val;
2556         uint16_t phy_data;
2557
2558         DEBUGFUNC("e1000_phy_reset");
2559
2560         if(hw->mac_type != e1000_82541_rev_2) {
2561                 if((ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data)))
2562                         return ret_val;
2563                 
2564                 phy_data |= MII_CR_RESET;
2565                 if((ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data)))
2566                         return ret_val;
2567                 
2568                 udelay(1);
2569         } else e1000_phy_hw_reset(hw);
2570
2571         if(hw->phy_type == e1000_phy_igp)
2572                 e1000_phy_init_script(hw);
2573
2574         return E1000_SUCCESS;
2575 }
2576
2577 /******************************************************************************
2578 * Probes the expected PHY address for known PHY IDs
2579 *
2580 * hw - Struct containing variables accessed by shared code
2581 ******************************************************************************/
2582 static int
2583 e1000_detect_gig_phy(struct e1000_hw *hw)
2584 {
2585         int32_t phy_init_status, ret_val;
2586         uint16_t phy_id_high, phy_id_low;
2587         boolean_t match = FALSE;
2588
2589         DEBUGFUNC("e1000_detect_gig_phy");
2590         
2591         /* Read the PHY ID Registers to identify which PHY is onboard. */
2592         if((ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high)))
2593                 return ret_val;
2594
2595         hw->phy_id = (uint32_t) (phy_id_high << 16);
2596         udelay(20);
2597         if((ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low)))
2598                 return ret_val;
2599         
2600         hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
2601 #ifdef LINUX_DRIVER
2602         hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
2603 #endif
2604         
2605         switch(hw->mac_type) {
2606         case e1000_82543:
2607                 if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
2608                 break;
2609         case e1000_82544:
2610                 if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
2611                 break;
2612         case e1000_82540:
2613         case e1000_82545:
2614         case e1000_82545_rev_3:
2615         case e1000_82546:
2616         case e1000_82546_rev_3:
2617                 if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
2618                 break;
2619         case e1000_82541:
2620         case e1000_82541_rev_2:
2621         case e1000_82547:
2622         case e1000_82547_rev_2:
2623                 if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
2624                 break;
2625         default:
2626                 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
2627                 return -E1000_ERR_CONFIG;
2628         }
2629         phy_init_status = e1000_set_phy_type(hw);
2630
2631         if ((match) && (phy_init_status == E1000_SUCCESS)) {
2632                 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
2633                 return E1000_SUCCESS;
2634         }
2635         DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
2636         return -E1000_ERR_PHY;
2637 }
2638
2639 /******************************************************************************
2640  * Sets up eeprom variables in the hw struct.  Must be called after mac_type
2641  * is configured.
2642  *
2643  * hw - Struct containing variables accessed by shared code
2644  *****************************************************************************/
2645 static void
2646 e1000_init_eeprom_params(struct e1000_hw *hw)
2647 {
2648         struct e1000_eeprom_info *eeprom = &hw->eeprom;
2649         uint32_t eecd = E1000_READ_REG(hw, EECD);
2650         uint16_t eeprom_size;
2651
2652         DEBUGFUNC("e1000_init_eeprom_params");
2653
2654         switch (hw->mac_type) {
2655         case e1000_82542_rev2_0:
2656         case e1000_82542_rev2_1:
2657         case e1000_82543:
2658         case e1000_82544:
2659                 eeprom->type = e1000_eeprom_microwire;
2660                 eeprom->word_size = 64;
2661                 eeprom->opcode_bits = 3;
2662                 eeprom->address_bits = 6;
2663                 eeprom->delay_usec = 50;
2664                 break;
2665         case e1000_82540:
2666         case e1000_82545:
2667         case e1000_82545_rev_3:
2668         case e1000_82546:
2669         case e1000_82546_rev_3:
2670                 eeprom->type = e1000_eeprom_microwire;
2671                 eeprom->opcode_bits = 3;
2672                 eeprom->delay_usec = 50;
2673                 if(eecd & E1000_EECD_SIZE) {
2674                         eeprom->word_size = 256;
2675                         eeprom->address_bits = 8;
2676                 } else {
2677                         eeprom->word_size = 64;
2678                         eeprom->address_bits = 6;
2679                 }
2680                 break;
2681         case e1000_82541:
2682         case e1000_82541_rev_2:
2683         case e1000_82547:
2684         case e1000_82547_rev_2:
2685                 if (eecd & E1000_EECD_TYPE) {
2686                         eeprom->type = e1000_eeprom_spi;
2687                         if (eecd & E1000_EECD_ADDR_BITS) {
2688                                 eeprom->page_size = 32;
2689                                 eeprom->address_bits = 16;
2690                         } else {
2691                                 eeprom->page_size = 8;
2692                                 eeprom->address_bits = 8;
2693                         }
2694                 } else {
2695                         eeprom->type = e1000_eeprom_microwire;
2696                         eeprom->opcode_bits = 3;
2697                         eeprom->delay_usec = 50;
2698                         if (eecd & E1000_EECD_ADDR_BITS) {
2699                                 eeprom->word_size = 256;
2700                                 eeprom->address_bits = 8;
2701                         } else {
2702                                 eeprom->word_size = 64;
2703                                 eeprom->address_bits = 6;
2704                         }
2705                 }
2706                 break;
2707         default:
2708                 eeprom->type = e1000_eeprom_spi;
2709                 if (eecd & E1000_EECD_ADDR_BITS) {
2710                         eeprom->page_size = 32;
2711                         eeprom->address_bits = 16;
2712                 } else {
2713                         eeprom->page_size = 8;
2714                         eeprom->address_bits = 8;
2715                 }
2716                 break;
2717         }
2718
2719         if (eeprom->type == e1000_eeprom_spi) {
2720                 eeprom->opcode_bits = 8;
2721                 eeprom->delay_usec = 1;
2722                 eeprom->word_size = 64;
2723                 if (e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size) == 0) {
2724                         eeprom_size &= EEPROM_SIZE_MASK;
2725
2726                         switch (eeprom_size) {
2727                         case EEPROM_SIZE_16KB:
2728                                 eeprom->word_size = 8192;
2729                                 break;
2730                         case EEPROM_SIZE_8KB:
2731                                 eeprom->word_size = 4096;
2732                                 break;
2733                         case EEPROM_SIZE_4KB:
2734                                 eeprom->word_size = 2048;
2735                                 break;
2736                         case EEPROM_SIZE_2KB:
2737                                 eeprom->word_size = 1024;
2738                                 break;
2739                         case EEPROM_SIZE_1KB:
2740                                 eeprom->word_size = 512;
2741                                 break;
2742                         case EEPROM_SIZE_512B:
2743                                 eeprom->word_size = 256;
2744                                 break;
2745                         case EEPROM_SIZE_128B:
2746                         default:
2747                                 break;
2748                         }
2749                 }
2750         }
2751 }
2752
2753 /******************************************************************************
2754  * Raises the EEPROM's clock input.
2755  *
2756  * hw - Struct containing variables accessed by shared code
2757  * eecd - EECD's current value
2758  *****************************************************************************/
2759 static void
2760 e1000_raise_ee_clk(struct e1000_hw *hw,
2761                    uint32_t *eecd)
2762 {
2763         /* Raise the clock input to the EEPROM (by setting the SK bit), and then
2764          * wait <delay> microseconds.
2765          */
2766         *eecd = *eecd | E1000_EECD_SK;
2767         E1000_WRITE_REG(hw, EECD, *eecd);
2768         E1000_WRITE_FLUSH(hw);
2769         udelay(hw->eeprom.delay_usec);
2770 }
2771
2772 /******************************************************************************
2773  * Lowers the EEPROM's clock input.
2774  *
2775  * hw - Struct containing variables accessed by shared code 
2776  * eecd - EECD's current value
2777  *****************************************************************************/
2778 static void
2779 e1000_lower_ee_clk(struct e1000_hw *hw,
2780                    uint32_t *eecd)
2781 {
2782         /* Lower the clock input to the EEPROM (by clearing the SK bit), and then 
2783          * wait 50 microseconds. 
2784          */
2785         *eecd = *eecd & ~E1000_EECD_SK;
2786         E1000_WRITE_REG(hw, EECD, *eecd);
2787         E1000_WRITE_FLUSH(hw);
2788         udelay(hw->eeprom.delay_usec);
2789 }
2790
2791 /******************************************************************************
2792  * Shift data bits out to the EEPROM.
2793  *
2794  * hw - Struct containing variables accessed by shared code
2795  * data - data to send to the EEPROM
2796  * count - number of bits to shift out
2797  *****************************************************************************/
2798 static void
2799 e1000_shift_out_ee_bits(struct e1000_hw *hw,
2800                         uint16_t data,
2801                         uint16_t count)
2802 {
2803         struct e1000_eeprom_info *eeprom = &hw->eeprom;
2804         uint32_t eecd;
2805         uint32_t mask;
2806         
2807         /* We need to shift "count" bits out to the EEPROM. So, value in the
2808          * "data" parameter will be shifted out to the EEPROM one bit at a time.
2809          * In order to do this, "data" must be broken down into bits. 
2810          */
2811         mask = 0x01 << (count - 1);
2812         eecd = E1000_READ_REG(hw, EECD);
2813         if (eeprom->type == e1000_eeprom_microwire) {
2814                 eecd &= ~E1000_EECD_DO;
2815         } else if (eeprom->type == e1000_eeprom_spi) {
2816                 eecd |= E1000_EECD_DO;
2817         }
2818         do {
2819                 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
2820                  * and then raising and then lowering the clock (the SK bit controls
2821                  * the clock input to the EEPROM).  A "0" is shifted out to the EEPROM
2822                  * by setting "DI" to "0" and then raising and then lowering the clock.
2823                  */
2824                 eecd &= ~E1000_EECD_DI;
2825                 
2826                 if(data & mask)
2827                         eecd |= E1000_EECD_DI;
2828                 
2829                 E1000_WRITE_REG(hw, EECD, eecd);
2830                 E1000_WRITE_FLUSH(hw);
2831                 
2832                 udelay(eeprom->delay_usec);
2833                 
2834                 e1000_raise_ee_clk(hw, &eecd);
2835                 e1000_lower_ee_clk(hw, &eecd);
2836                 
2837                 mask = mask >> 1;
2838                 
2839         } while(mask);
2840
2841         /* We leave the "DI" bit set to "0" when we leave this routine. */
2842         eecd &= ~E1000_EECD_DI;
2843         E1000_WRITE_REG(hw, EECD, eecd);
2844 }
2845
2846 /******************************************************************************
2847  * Shift data bits in from the EEPROM
2848  *
2849  * hw - Struct containing variables accessed by shared code
2850  *****************************************************************************/
2851 static uint16_t
2852 e1000_shift_in_ee_bits(struct e1000_hw *hw,
2853                        uint16_t count)
2854 {
2855         uint32_t eecd;
2856         uint32_t i;
2857         uint16_t data;
2858         
2859         /* In order to read a register from the EEPROM, we need to shift 'count' 
2860          * bits in from the EEPROM. Bits are "shifted in" by raising the clock
2861          * input to the EEPROM (setting the SK bit), and then reading the value of
2862          * the "DO" bit.  During this "shifting in" process the "DI" bit should
2863          * always be clear.
2864          */
2865         
2866         eecd = E1000_READ_REG(hw, EECD);
2867         
2868         eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
2869         data = 0;
2870         
2871         for(i = 0; i < count; i++) {
2872                 data = data << 1;
2873                 e1000_raise_ee_clk(hw, &eecd);
2874                 
2875                 eecd = E1000_READ_REG(hw, EECD);
2876                 
2877                 eecd &= ~(E1000_EECD_DI);
2878                 if(eecd & E1000_EECD_DO)
2879                         data |= 1;
2880                 
2881                 e1000_lower_ee_clk(hw, &eecd);
2882         }
2883         
2884         return data;
2885 }
2886
2887 /******************************************************************************
2888  * Prepares EEPROM for access
2889  *
2890  * hw - Struct containing variables accessed by shared code
2891  *
2892  * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 
2893  * function should be called before issuing a command to the EEPROM.
2894  *****************************************************************************/
2895 static int32_t
2896 e1000_acquire_eeprom(struct e1000_hw *hw)
2897 {
2898         struct e1000_eeprom_info *eeprom = &hw->eeprom;
2899         uint32_t eecd, i=0;
2900
2901         eecd = E1000_READ_REG(hw, EECD);
2902
2903         /* Request EEPROM Access */
2904         if(hw->mac_type > e1000_82544) {
2905                 eecd |= E1000_EECD_REQ;
2906                 E1000_WRITE_REG(hw, EECD, eecd);
2907                 eecd = E1000_READ_REG(hw, EECD);
2908                 while((!(eecd & E1000_EECD_GNT)) &&
2909                       (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
2910                         i++;
2911                         udelay(5);
2912                         eecd = E1000_READ_REG(hw, EECD);
2913                 }
2914                 if(!(eecd & E1000_EECD_GNT)) {
2915                         eecd &= ~E1000_EECD_REQ;
2916                         E1000_WRITE_REG(hw, EECD, eecd);
2917                         DEBUGOUT("Could not acquire EEPROM grant\n");
2918                         return -E1000_ERR_EEPROM;
2919                 }
2920         }
2921
2922         /* Setup EEPROM for Read/Write */
2923
2924         if (eeprom->type == e1000_eeprom_microwire) {
2925                 /* Clear SK and DI */
2926                 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
2927                 E1000_WRITE_REG(hw, EECD, eecd);
2928
2929                 /* Set CS */
2930                 eecd |= E1000_EECD_CS;
2931                 E1000_WRITE_REG(hw, EECD, eecd);
2932         } else if (eeprom->type == e1000_eeprom_spi) {
2933                 /* Clear SK and CS */
2934                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
2935                 E1000_WRITE_REG(hw, EECD, eecd);
2936                 udelay(1);
2937         }
2938
2939         return E1000_SUCCESS;
2940 }
2941
2942 /******************************************************************************
2943  * Returns EEPROM to a "standby" state
2944  * 
2945  * hw - Struct containing variables accessed by shared code
2946  *****************************************************************************/
2947 static void
2948 e1000_standby_eeprom(struct e1000_hw *hw)
2949 {
2950         struct e1000_eeprom_info *eeprom = &hw->eeprom;
2951         uint32_t eecd;
2952         
2953         eecd = E1000_READ_REG(hw, EECD);
2954
2955         if(eeprom->type == e1000_eeprom_microwire) {
2956
2957                 /* Deselect EEPROM */
2958                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
2959                 E1000_WRITE_REG(hw, EECD, eecd);
2960                 E1000_WRITE_FLUSH(hw);
2961                 udelay(eeprom->delay_usec);
2962         
2963                 /* Clock high */
2964                 eecd |= E1000_EECD_SK;
2965                 E1000_WRITE_REG(hw, EECD, eecd);
2966                 E1000_WRITE_FLUSH(hw);
2967                 udelay(eeprom->delay_usec);
2968         
2969                 /* Select EEPROM */
2970                 eecd |= E1000_EECD_CS;
2971                 E1000_WRITE_REG(hw, EECD, eecd);
2972                 E1000_WRITE_FLUSH(hw);
2973                 udelay(eeprom->delay_usec);
2974
2975                 /* Clock low */
2976                 eecd &= ~E1000_EECD_SK;
2977                 E1000_WRITE_REG(hw, EECD, eecd);
2978                 E1000_WRITE_FLUSH(hw);
2979                 udelay(eeprom->delay_usec);
2980         } else if(eeprom->type == e1000_eeprom_spi) {
2981                 /* Toggle CS to flush commands */
2982                 eecd |= E1000_EECD_CS;
2983                 E1000_WRITE_REG(hw, EECD, eecd);
2984                 E1000_WRITE_FLUSH(hw);
2985                 udelay(eeprom->delay_usec);
2986                 eecd &= ~E1000_EECD_CS;
2987                 E1000_WRITE_REG(hw, EECD, eecd);
2988                 E1000_WRITE_FLUSH(hw);
2989                 udelay(eeprom->delay_usec);
2990         }
2991 }
2992
2993 /******************************************************************************
2994  * Terminates a command by inverting the EEPROM's chip select pin
2995  *
2996  * hw - Struct containing variables accessed by shared code
2997  *****************************************************************************/
2998 static void
2999 e1000_release_eeprom(struct e1000_hw *hw)
3000 {
3001         uint32_t eecd;
3002
3003         eecd = E1000_READ_REG(hw, EECD);
3004
3005         if (hw->eeprom.type == e1000_eeprom_spi) {
3006                 eecd |= E1000_EECD_CS;  /* Pull CS high */
3007                 eecd &= ~E1000_EECD_SK; /* Lower SCK */
3008
3009                 E1000_WRITE_REG(hw, EECD, eecd);
3010
3011                 udelay(hw->eeprom.delay_usec);
3012         } else if(hw->eeprom.type == e1000_eeprom_microwire) {
3013                 /* cleanup eeprom */
3014
3015                 /* CS on Microwire is active-high */
3016                 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
3017
3018                 E1000_WRITE_REG(hw, EECD, eecd);
3019
3020                 /* Rising edge of clock */
3021                 eecd |= E1000_EECD_SK;
3022                 E1000_WRITE_REG(hw, EECD, eecd);
3023                 E1000_WRITE_FLUSH(hw);
3024                 udelay(hw->eeprom.delay_usec);
3025
3026                 /* Falling edge of clock */
3027                 eecd &= ~E1000_EECD_SK;
3028                 E1000_WRITE_REG(hw, EECD, eecd);
3029                 E1000_WRITE_FLUSH(hw);
3030                 udelay(hw->eeprom.delay_usec);
3031         }
3032
3033         /* Stop requesting EEPROM access */
3034         if(hw->mac_type > e1000_82544) {
3035                 eecd &= ~E1000_EECD_REQ;
3036                 E1000_WRITE_REG(hw, EECD, eecd);
3037         }
3038 }
3039
3040 /******************************************************************************
3041  * Reads a 16 bit word from the EEPROM.
3042  *
3043  * hw - Struct containing variables accessed by shared code
3044  *****************************************************************************/
3045 static int32_t
3046 e1000_spi_eeprom_ready(struct e1000_hw *hw)
3047 {
3048         uint16_t retry_count = 0;
3049         uint8_t spi_stat_reg;
3050
3051         /* Read "Status Register" repeatedly until the LSB is cleared.  The
3052          * EEPROM will signal that the command has been completed by clearing
3053          * bit 0 of the internal status register.  If it's not cleared within
3054          * 5 milliseconds, then error out.
3055          */
3056         retry_count = 0;
3057         do {
3058                 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
3059                 hw->eeprom.opcode_bits);
3060                 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
3061                 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
3062                         break;
3063
3064                 udelay(5);
3065                 retry_count += 5;
3066
3067         } while(retry_count < EEPROM_MAX_RETRY_SPI);
3068
3069         /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
3070          * only 0-5mSec on 5V devices)
3071          */
3072         if(retry_count >= EEPROM_MAX_RETRY_SPI) {
3073                 DEBUGOUT("SPI EEPROM Status error\n");
3074                 return -E1000_ERR_EEPROM;
3075         }
3076
3077         return E1000_SUCCESS;
3078 }
3079
3080 /******************************************************************************
3081  * Reads a 16 bit word from the EEPROM.
3082  *
3083  * hw - Struct containing variables accessed by shared code
3084  * offset - offset of  word in the EEPROM to read
3085  * data - word read from the EEPROM
3086  * words - number of words to read
3087  *****************************************************************************/
3088 static int
3089 e1000_read_eeprom(struct e1000_hw *hw,
3090                   uint16_t offset,
3091                   uint16_t words,
3092                   uint16_t *data)
3093 {
3094         struct e1000_eeprom_info *eeprom = &hw->eeprom;
3095         uint32_t i = 0;
3096         
3097         DEBUGFUNC("e1000_read_eeprom");
3098
3099         /* A check for invalid values:  offset too large, too many words, and not
3100          * enough words.
3101          */
3102         if((offset > eeprom->word_size) || (words > eeprom->word_size - offset) ||
3103            (words == 0)) {
3104                 DEBUGOUT("\"words\" parameter out of bounds\n");
3105                 return -E1000_ERR_EEPROM;
3106         }
3107
3108         /*  Prepare the EEPROM for reading  */
3109         if(e1000_acquire_eeprom(hw) != E1000_SUCCESS)
3110                 return -E1000_ERR_EEPROM;
3111
3112         if(eeprom->type == e1000_eeprom_spi) {
3113                 uint16_t word_in;
3114                 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
3115
3116                 if(e1000_spi_eeprom_ready(hw)) {
3117                         e1000_release_eeprom(hw);
3118                         return -E1000_ERR_EEPROM;
3119                 }
3120
3121                 e1000_standby_eeprom(hw);
3122
3123                 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
3124                 if((eeprom->address_bits == 8) && (offset >= 128))
3125                         read_opcode |= EEPROM_A8_OPCODE_SPI;
3126
3127                 /* Send the READ command (opcode + addr)  */
3128                 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
3129                 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
3130
3131                 /* Read the data.  The address of the eeprom internally increments with
3132                  * each byte (spi) being read, saving on the overhead of eeprom setup
3133                  * and tear-down.  The address counter will roll over if reading beyond
3134                  * the size of the eeprom, thus allowing the entire memory to be read
3135                  * starting from any offset. */
3136                 for (i = 0; i < words; i++) {
3137                         word_in = e1000_shift_in_ee_bits(hw, 16);
3138                         data[i] = (word_in >> 8) | (word_in << 8);
3139                 }
3140         } else if(eeprom->type == e1000_eeprom_microwire) {
3141                 for (i = 0; i < words; i++) {
3142                         /*  Send the READ command (opcode + addr)  */
3143                         e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
3144                                                 eeprom->opcode_bits);
3145                         e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
3146                                                 eeprom->address_bits);
3147
3148                         /* Read the data.  For microwire, each word requires the overhead
3149                          * of eeprom setup and tear-down. */
3150                         data[i] = e1000_shift_in_ee_bits(hw, 16);
3151                         e1000_standby_eeprom(hw);
3152                 }
3153         }
3154
3155         /* End this read operation */
3156         e1000_release_eeprom(hw);
3157
3158         return E1000_SUCCESS;
3159 }
3160
3161 /******************************************************************************
3162  * Verifies that the EEPROM has a valid checksum
3163  * 
3164  * hw - Struct containing variables accessed by shared code
3165  *
3166  * Reads the first 64 16 bit words of the EEPROM and sums the values read.
3167  * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
3168  * valid.
3169  *****************************************************************************/
3170 static int
3171 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
3172 {
3173         uint16_t checksum = 0;
3174         uint16_t i, eeprom_data;
3175
3176         DEBUGFUNC("e1000_validate_eeprom_checksum");
3177
3178         for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
3179                 if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3180                         DEBUGOUT("EEPROM Read Error\n");
3181                         return -E1000_ERR_EEPROM;
3182                 }
3183                 checksum += eeprom_data;
3184         }
3185         
3186         if(checksum == (uint16_t) EEPROM_SUM)
3187                 return E1000_SUCCESS;
3188         else {
3189                 DEBUGOUT("EEPROM Checksum Invalid\n");    
3190                 return -E1000_ERR_EEPROM;
3191         }
3192 }
3193
3194 /******************************************************************************
3195  * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
3196  * second function of dual function devices
3197  *
3198  * hw - Struct containing variables accessed by shared code
3199  *****************************************************************************/
3200 static int 
3201 e1000_read_mac_addr(struct e1000_hw *hw)
3202 {
3203         uint16_t offset;
3204         uint16_t eeprom_data;
3205         int i;
3206
3207         DEBUGFUNC("e1000_read_mac_addr");
3208
3209         for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
3210                 offset = i >> 1;
3211                 if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
3212                         DEBUGOUT("EEPROM Read Error\n");
3213                         return -E1000_ERR_EEPROM;
3214                 }
3215                 hw->mac_addr[i] = eeprom_data & 0xff;
3216                 hw->mac_addr[i+1] = (eeprom_data >> 8) & 0xff;
3217         }
3218         if(((hw->mac_type == e1000_82546) || (hw->mac_type == e1000_82546_rev_3)) &&
3219                 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1))
3220                 /* Invert the last bit if this is the second device */
3221                 hw->mac_addr[5] ^= 1;
3222         return E1000_SUCCESS;
3223 }
3224
3225 /******************************************************************************
3226  * Initializes receive address filters.
3227  *
3228  * hw - Struct containing variables accessed by shared code 
3229  *
3230  * Places the MAC address in receive address register 0 and clears the rest
3231  * of the receive addresss registers. Clears the multicast table. Assumes
3232  * the receiver is in reset when the routine is called.
3233  *****************************************************************************/
3234 static void
3235 e1000_init_rx_addrs(struct e1000_hw *hw)
3236 {
3237         uint32_t i;
3238         uint32_t addr_low;
3239         uint32_t addr_high;
3240         
3241         DEBUGFUNC("e1000_init_rx_addrs");
3242         
3243         /* Setup the receive address. */
3244         DEBUGOUT("Programming MAC Address into RAR[0]\n");
3245         addr_low = (hw->mac_addr[0] |
3246                 (hw->mac_addr[1] << 8) |
3247                 (hw->mac_addr[2] << 16) | (hw->mac_addr[3] << 24));
3248         
3249         addr_high = (hw->mac_addr[4] |
3250                 (hw->mac_addr[5] << 8) | E1000_RAH_AV);
3251         
3252         E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
3253         E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
3254         
3255         /* Zero out the other 15 receive addresses. */
3256         DEBUGOUT("Clearing RAR[1-15]\n");
3257         for(i = 1; i < E1000_RAR_ENTRIES; i++) {
3258                 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
3259                 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
3260         }
3261 }
3262
3263 /******************************************************************************
3264  * Clears the VLAN filer table
3265  *
3266  * hw - Struct containing variables accessed by shared code
3267  *****************************************************************************/
3268 static void
3269 e1000_clear_vfta(struct e1000_hw *hw)
3270 {
3271         uint32_t offset;
3272     
3273         for(offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
3274                 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
3275 }
3276
3277
3278 /******************************************************************************
3279  * Functions from e1000_main.c of the linux driver
3280  ******************************************************************************/
3281
3282 /**
3283  * e1000_reset - Reset the adapter
3284  */
3285
3286 static int
3287 e1000_reset(struct e1000_hw *hw)
3288 {
3289         uint32_t pba;
3290         /* Repartition Pba for greater than 9k mtu
3291          * To take effect CTRL.RST is required.
3292          */
3293
3294         if(hw->mac_type < e1000_82547) {
3295                 pba = E1000_PBA_48K;
3296         } else {
3297                 pba = E1000_PBA_30K;
3298         }
3299         E1000_WRITE_REG(hw, PBA, pba);
3300
3301         /* flow control settings */
3302 #if 0
3303         hw->fc_high_water = FC_DEFAULT_HI_THRESH;
3304         hw->fc_low_water = FC_DEFAULT_LO_THRESH;
3305         hw->fc_pause_time = FC_DEFAULT_TX_TIMER;
3306         hw->fc_send_xon = 1;
3307         hw->fc = hw->original_fc;
3308 #endif
3309         
3310         e1000_reset_hw(hw);
3311         if(hw->mac_type >= e1000_82544)
3312                 E1000_WRITE_REG(hw, WUC, 0);
3313         return e1000_init_hw(hw);
3314 }
3315
3316 /**
3317  * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
3318  * @adapter: board private structure to initialize
3319  *
3320  * e1000_sw_init initializes the Adapter private data structure.
3321  * Fields are initialized based on PCI device information and
3322  * OS network device settings (MTU size).
3323  **/
3324
3325 static int 
3326 e1000_sw_init(struct pci_device *pdev, struct e1000_hw *hw)
3327 {
3328         int result;
3329
3330         /* PCI config space info */
3331         pci_read_config_word(pdev, PCI_VENDOR_ID, &hw->vendor_id);
3332         pci_read_config_word(pdev, PCI_DEVICE_ID, &hw->device_id);
3333         pci_read_config_byte(pdev, PCI_REVISION, &hw->revision_id);
3334 #if 0
3335         pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID,
3336                              &hw->subsystem_vendor_id);
3337         pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
3338 #endif
3339
3340         pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
3341
3342         /* identify the MAC */
3343
3344         result = e1000_set_mac_type(hw);
3345         if (result) {
3346                 E1000_ERR("Unknown MAC Type\n");
3347                 return result;
3348         }
3349
3350         /* initialize eeprom parameters */
3351
3352         e1000_init_eeprom_params(hw);
3353
3354 #if 0
3355         if((hw->mac_type == e1000_82541) ||
3356            (hw->mac_type == e1000_82547) ||
3357            (hw->mac_type == e1000_82541_rev_2) ||
3358            (hw->mac_type == e1000_82547_rev_2))
3359                 hw->phy_init_script = 1;
3360 #endif
3361
3362         e1000_set_media_type(hw);
3363
3364 #if 0
3365         if(hw->mac_type < e1000_82543)
3366                 hw->report_tx_early = 0;
3367         else
3368                 hw->report_tx_early = 1;
3369
3370         hw->wait_autoneg_complete = FALSE;
3371 #endif
3372         hw->tbi_compatibility_en = TRUE;
3373 #if 0
3374         hw->adaptive_ifs = TRUE;
3375
3376         /* Copper options */
3377
3378         if(hw->media_type == e1000_media_type_copper) {
3379                 hw->mdix = AUTO_ALL_MODES;
3380                 hw->disable_polarity_correction = FALSE;
3381                 hw->master_slave = E1000_MASTER_SLAVE;
3382         }
3383 #endif
3384         return E1000_SUCCESS;
3385 }
3386
3387
3388 /******************************************************************************
3389  * Functions not present in the linux driver