[pci] Add driver_data field to struct pci_device_id
[people/lynusvaz/gpxe.git] / src / drivers / net / tlan.c
1 /**************************************************************************
2 *
3 *    tlan.c -- Etherboot device driver for the Texas Instruments ThunderLAN
4 *    Written 2003-2003 by Timothy Legge <tlegge@rogers.com>
5 *
6 *    This program is free software; you can redistribute it and/or modify
7 *    it under the terms of the GNU General Public License as published by
8 *    the Free Software Foundation; either version 2 of the License, or
9 *    (at your option) any later version.
10 *
11 *    This program is distributed in the hope that it will be useful,
12 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
13 *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14 *    GNU General Public License for more details.
15 *
16 *    You should have received a copy of the GNU General Public License
17 *    along with this program; if not, write to the Free Software
18 *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 *
20 *    Portions of this code based on:
21 *       lan.c: Linux ThunderLan Driver:
22 *
23 *       by James Banks
24 *
25 *       (C) 1997-1998 Caldera, Inc.
26 *       (C) 1998 James Banks
27 *       (C) 1999-2001 Torben Mathiasen
28 *       (C) 2002 Samuel Chessman
29 *
30 *    REVISION HISTORY:
31 *    ================
32 *    v1.0       07-08-2003      timlegge        Initial not quite working version
33 *    v1.1       07-27-2003      timlegge        Sync 5.0 and 5.1 versions
34 *    v1.2       08-19-2003      timlegge        Implement Multicast Support
35 *    v1.3       08-23-2003      timlegge        Fix the transmit Function
36 *    v1.4       01-17-2004      timlegge        Initial driver output cleanup    
37 *    
38 *    Indent Options: indent -kr -i8
39 ***************************************************************************/
40
41 #include "etherboot.h"
42 #include "nic.h"
43 #include <gpxe/pci.h>
44 #include <gpxe/ethernet.h>
45 #include "tlan.h"
46
47 #define drv_version "v1.4"
48 #define drv_date "01-17-2004"
49
50 /* NIC specific static variables go here */
51 #define HZ 100
52 #define TX_TIME_OUT       (6*HZ)
53
54 /* Condensed operations for readability. */
55 #define virt_to_le32desc(addr)  cpu_to_le32(virt_to_bus(addr))
56 #define le32desc_to_virt(addr)  bus_to_virt(le32_to_cpu(addr))
57
58 static void TLan_ResetLists(struct nic *nic __unused);
59 static void TLan_ResetAdapter(struct nic *nic __unused);
60 static void TLan_FinishReset(struct nic *nic __unused);
61
62 static void TLan_EeSendStart(u16);
63 static int TLan_EeSendByte(u16, u8, int);
64 static void TLan_EeReceiveByte(u16, u8 *, int);
65 static int TLan_EeReadByte(u16 io_base, u8, u8 *);
66
67 static void TLan_PhyDetect(struct nic *nic);
68 static void TLan_PhyPowerDown(struct nic *nic);
69 static void TLan_PhyPowerUp(struct nic *nic);
70
71
72 static void TLan_SetMac(struct nic *nic __unused, int areg, unsigned char *mac);
73
74 static void TLan_PhyReset(struct nic *nic);
75 static void TLan_PhyStartLink(struct nic *nic);
76 static void TLan_PhyFinishAutoNeg(struct nic *nic);
77
78 #ifdef MONITOR
79 static void TLan_PhyMonitor(struct nic *nic);
80 #endif
81
82
83 static void refill_rx(struct nic *nic __unused);
84
85 static int TLan_MiiReadReg(struct nic *nic __unused, u16, u16, u16 *);
86 static void TLan_MiiSendData(u16, u32, unsigned);
87 static void TLan_MiiSync(u16);
88 static void TLan_MiiWriteReg(struct nic *nic __unused, u16, u16, u16);
89
90
91 static const char *media[] = {
92         "10BaseT-HD ", "10BaseT-FD ", "100baseTx-HD ",
93         "100baseTx-FD", "100baseT4", 0
94 };
95
96 /* This much match tlan_pci_tbl[]!  */
97 enum tlan_nics {
98         NETEL10 = 0, NETEL100 = 1, NETFLEX3I = 2, THUNDER = 3, NETFLEX3B =
99             4, NETEL100PI = 5,
100         NETEL100D = 6, NETEL100I = 7, OC2183 = 8, OC2325 = 9, OC2326 =
101             10, NETELLIGENT_10_100_WS_5100 = 11,
102         NETELLIGENT_10_T2 = 12
103 };
104
105 struct pci_id_info {
106         const char *name;
107         int nic_id;
108         struct match_info {
109                 u32 pci, pci_mask, subsystem, subsystem_mask;
110                 u32 revision, revision_mask;    /* Only 8 bits. */
111         } id;
112         u32 flags;
113         u16 addrOfs;            /* Address Offset */
114 };
115
116 static const struct pci_id_info tlan_pci_tbl[] = {
117         {"Compaq Netelligent 10 T PCI UTP", NETEL10,
118          {0xae340e11, 0xffffffff, 0, 0, 0, 0},
119          TLAN_ADAPTER_ACTIVITY_LED, 0x83},
120         {"Compaq Netelligent 10/100 TX PCI UTP", NETEL100,
121          {0xae320e11, 0xffffffff, 0, 0, 0, 0},
122          TLAN_ADAPTER_ACTIVITY_LED, 0x83},
123         {"Compaq Integrated NetFlex-3/P", NETFLEX3I,
124          {0xae350e11, 0xffffffff, 0, 0, 0, 0},
125          TLAN_ADAPTER_NONE, 0x83},
126         {"Compaq NetFlex-3/P", THUNDER,
127          {0xf1300e11, 0xffffffff, 0, 0, 0, 0},
128          TLAN_ADAPTER_UNMANAGED_PHY | TLAN_ADAPTER_BIT_RATE_PHY, 0x83},
129         {"Compaq NetFlex-3/P", NETFLEX3B,
130          {0xf1500e11, 0xffffffff, 0, 0, 0, 0},
131          TLAN_ADAPTER_NONE, 0x83},
132         {"Compaq Netelligent Integrated 10/100 TX UTP", NETEL100PI,
133          {0xae430e11, 0xffffffff, 0, 0, 0, 0},
134          TLAN_ADAPTER_ACTIVITY_LED, 0x83},
135         {"Compaq Netelligent Dual 10/100 TX PCI UTP", NETEL100D,
136          {0xae400e11, 0xffffffff, 0, 0, 0, 0},
137          TLAN_ADAPTER_NONE, 0x83},
138         {"Compaq Netelligent 10/100 TX Embedded UTP", NETEL100I,
139          {0xb0110e11, 0xffffffff, 0, 0, 0, 0},
140          TLAN_ADAPTER_NONE, 0x83},
141         {"Olicom OC-2183/2185", OC2183,
142          {0x0013108d, 0xffffffff, 0, 0, 0, 0},
143          TLAN_ADAPTER_USE_INTERN_10, 0x83},
144         {"Olicom OC-2325", OC2325,
145          {0x0012108d, 0xffffffff, 0, 0, 0, 0},
146          TLAN_ADAPTER_UNMANAGED_PHY, 0xF8},
147         {"Olicom OC-2326", OC2326,
148          {0x0014108d, 0xffffffff, 0, 0, 0, 0},
149          TLAN_ADAPTER_USE_INTERN_10, 0xF8},
150         {"Compaq Netelligent 10/100 TX UTP", NETELLIGENT_10_100_WS_5100,
151          {0xb0300e11, 0xffffffff, 0, 0, 0, 0},
152          TLAN_ADAPTER_ACTIVITY_LED, 0x83},
153         {"Compaq Netelligent 10 T/2 PCI UTP/Coax", NETELLIGENT_10_T2,
154          {0xb0120e11, 0xffffffff, 0, 0, 0, 0},
155          TLAN_ADAPTER_NONE, 0x83},
156         {"Compaq NetFlex-3/E", 0,       /* EISA card */
157          {0, 0, 0, 0, 0, 0},
158          TLAN_ADAPTER_ACTIVITY_LED | TLAN_ADAPTER_UNMANAGED_PHY |
159          TLAN_ADAPTER_BIT_RATE_PHY, 0x83},
160         {"Compaq NetFlex-3/E", 0,       /* EISA card */
161          {0, 0, 0, 0, 0, 0},
162          TLAN_ADAPTER_ACTIVITY_LED, 0x83},
163         {0, 0,
164          {0, 0, 0, 0, 0, 0},
165          0, 0},
166 };
167
168 struct TLanList {
169         u32 forward;
170         u16 cStat;
171         u16 frameSize;
172         struct {
173                 u32 count;
174                 u32 address;
175         } buffer[TLAN_BUFFERS_PER_LIST];
176 };
177
178 struct {
179         struct TLanList tx_ring[TLAN_NUM_TX_LISTS];
180         unsigned char txb[TLAN_MAX_FRAME_SIZE * TLAN_NUM_TX_LISTS];
181         struct TLanList rx_ring[TLAN_NUM_RX_LISTS];
182         unsigned char rxb[TLAN_MAX_FRAME_SIZE * TLAN_NUM_RX_LISTS];
183 } tlan_buffers __shared;
184 #define tx_ring tlan_buffers.tx_ring
185 #define txb tlan_buffers.txb
186 #define rx_ring tlan_buffers.rx_ring
187 #define rxb tlan_buffers.rxb
188
189 typedef u8 TLanBuffer[TLAN_MAX_FRAME_SIZE];
190
191 static int chip_idx;
192
193 /*****************************************************************
194 * TLAN Private Information Structure
195 *
196 ****************************************************************/
197 static struct tlan_private {
198         unsigned short vendor_id;       /* PCI Vendor code */
199         unsigned short dev_id;  /* PCI Device code */
200         const char *nic_name;
201         unsigned int cur_rx, dirty_rx;  /* Producer/consumer ring indicies */
202         unsigned rx_buf_sz;     /* Based on mtu + Slack */
203         struct TLanList *txList;
204         u32 txHead;
205         u32 txInProgress;
206         u32 txTail;
207         int eoc;
208         u32 phyOnline;
209         u32 aui;
210         u32 duplex;
211         u32 phy[2];
212         u32 phyNum;
213         u32 speed;
214         u8 tlanRev;
215         u8 tlanFullDuplex;
216         u8 link;
217         u8 neg_be_verbose;
218 } TLanPrivateInfo;
219
220 static struct tlan_private *priv;
221
222 static u32 BASE;
223
224 /***************************************************************
225 *       TLan_ResetLists
226 *
227 *       Returns:
228 *               Nothing
229 *       Parms:
230 *               dev     The device structure with the list
231 *                       stuctures to be reset.
232 *
233 *       This routine sets the variables associated with managing
234 *       the TLAN lists to their initial values.
235 *
236 **************************************************************/
237
238 static void TLan_ResetLists(struct nic *nic __unused)
239 {
240
241         int i;
242         struct TLanList *list;
243         priv->txHead = 0;
244         priv->txTail = 0;
245
246         for (i = 0; i < TLAN_NUM_TX_LISTS; i++) {
247                 list = &tx_ring[i];
248                 list->cStat = TLAN_CSTAT_UNUSED;
249                 list->buffer[0].address = virt_to_bus(txb + 
250                                 (i * TLAN_MAX_FRAME_SIZE)); 
251                 list->buffer[2].count = 0;
252                 list->buffer[2].address = 0;
253                 list->buffer[9].address = 0;
254         }
255
256         priv->cur_rx = 0;
257         priv->rx_buf_sz = (TLAN_MAX_FRAME_SIZE);
258 //      priv->rx_head_desc = &rx_ring[0];
259
260         /* Initialize all the Rx descriptors */
261         for (i = 0; i < TLAN_NUM_RX_LISTS; i++) {
262                 rx_ring[i].forward = virt_to_le32desc(&rx_ring[i + 1]);
263                 rx_ring[i].cStat = TLAN_CSTAT_READY;
264                 rx_ring[i].frameSize = TLAN_MAX_FRAME_SIZE;
265                 rx_ring[i].buffer[0].count =
266                     TLAN_MAX_FRAME_SIZE | TLAN_LAST_BUFFER;
267                 rx_ring[i].buffer[0].address =
268                     virt_to_le32desc(&rxb[i * TLAN_MAX_FRAME_SIZE]);
269                 rx_ring[i].buffer[1].count = 0;
270                 rx_ring[i].buffer[1].address = 0;
271         }
272
273         /* Mark the last entry as wrapping the ring */
274         rx_ring[i - 1].forward = virt_to_le32desc(&rx_ring[0]);
275         priv->dirty_rx = (unsigned int) (i - TLAN_NUM_RX_LISTS);
276
277 } /* TLan_ResetLists */
278
279 /***************************************************************
280 *       TLan_Reset
281 *
282 *       Returns:
283 *               0
284 *       Parms:
285 *               dev     Pointer to device structure of adapter
286 *                       to be reset.
287 *
288 *       This function resets the adapter and it's physical
289 *       device.  See Chap. 3, pp. 9-10 of the "ThunderLAN
290 *       Programmer's Guide" for details.  The routine tries to
291 *       implement what is detailed there, though adjustments
292 *       have been made.
293 *
294 **************************************************************/
295
296 void TLan_ResetAdapter(struct nic *nic __unused)
297 {
298         int i;
299         u32 addr;
300         u32 data;
301         u8 data8;
302
303         priv->tlanFullDuplex = FALSE;
304         priv->phyOnline = 0;
305 /*  1.  Assert reset bit. */
306
307         data = inl(BASE + TLAN_HOST_CMD);
308         data |= TLAN_HC_AD_RST;
309         outl(data, BASE + TLAN_HOST_CMD);
310
311         udelay(1000);
312
313 /*  2.  Turn off interrupts. ( Probably isn't necessary ) */
314
315         data = inl(BASE + TLAN_HOST_CMD);
316         data |= TLAN_HC_INT_OFF;
317         outl(data, BASE + TLAN_HOST_CMD);
318 /*  3.  Clear AREGs and HASHs. */
319
320         for (i = TLAN_AREG_0; i <= TLAN_HASH_2; i += 4) {
321                 TLan_DioWrite32(BASE, (u16) i, 0);
322         }
323
324 /*  4.  Setup NetConfig register. */
325
326         data =
327             TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN | TLAN_NET_CFG_PHY_EN;
328         TLan_DioWrite16(BASE, TLAN_NET_CONFIG, (u16) data);
329
330 /*  5.  Load Ld_Tmr and Ld_Thr in HOST_CMD. */
331
332         outl(TLAN_HC_LD_TMR | 0x3f, BASE + TLAN_HOST_CMD);
333         outl(TLAN_HC_LD_THR | 0x0, BASE + TLAN_HOST_CMD);
334
335 /*  6.  Unreset the MII by setting NMRST (in NetSio) to 1. */
336
337         outw(TLAN_NET_SIO, BASE + TLAN_DIO_ADR);
338         addr = BASE + TLAN_DIO_DATA + TLAN_NET_SIO;
339         TLan_SetBit(TLAN_NET_SIO_NMRST, addr);
340
341 /*  7.  Setup the remaining registers. */
342
343         if (priv->tlanRev >= 0x30) {
344                 data8 = TLAN_ID_TX_EOC | TLAN_ID_RX_EOC;
345                 TLan_DioWrite8(BASE, TLAN_INT_DIS, data8);
346         }
347         TLan_PhyDetect(nic);
348         data = TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN;
349
350         if (tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_BIT_RATE_PHY) {
351                 data |= TLAN_NET_CFG_BIT;
352                 if (priv->aui == 1) {
353                         TLan_DioWrite8(BASE, TLAN_ACOMMIT, 0x0a);
354                 } else if (priv->duplex == TLAN_DUPLEX_FULL) {
355                         TLan_DioWrite8(BASE, TLAN_ACOMMIT, 0x00);
356                         priv->tlanFullDuplex = TRUE;
357                 } else {
358                         TLan_DioWrite8(BASE, TLAN_ACOMMIT, 0x08);
359                 }
360         }
361
362         if (priv->phyNum == 0) {
363                 data |= TLAN_NET_CFG_PHY_EN;
364         }
365         TLan_DioWrite16(BASE, TLAN_NET_CONFIG, (u16) data);
366
367         if (tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_UNMANAGED_PHY) {
368                 TLan_FinishReset(nic);
369         } else {
370                 TLan_PhyPowerDown(nic);
371         }
372
373 }       /* TLan_ResetAdapter */
374
375 void TLan_FinishReset(struct nic *nic)
376 {
377
378         u8 data;
379         u32 phy;
380         u8 sio;
381         u16 status;
382         u16 partner;
383         u16 tlphy_ctl;
384         u16 tlphy_par;
385         u16 tlphy_id1, tlphy_id2;
386         int i;
387
388         phy = priv->phy[priv->phyNum];
389
390         data = TLAN_NET_CMD_NRESET | TLAN_NET_CMD_NWRAP;
391         if (priv->tlanFullDuplex) {
392                 data |= TLAN_NET_CMD_DUPLEX;
393         }
394         TLan_DioWrite8(BASE, TLAN_NET_CMD, data);
395         data = TLAN_NET_MASK_MASK4 | TLAN_NET_MASK_MASK5;
396         if (priv->phyNum == 0) {
397                 data |= TLAN_NET_MASK_MASK7;
398         }
399         TLan_DioWrite8(BASE, TLAN_NET_MASK, data);
400         TLan_DioWrite16(BASE, TLAN_MAX_RX, ((1536) + 7) & ~7);
401         TLan_MiiReadReg(nic, phy, MII_GEN_ID_HI, &tlphy_id1);
402         TLan_MiiReadReg(nic, phy, MII_GEN_ID_LO, &tlphy_id2);
403
404         if ((tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_UNMANAGED_PHY)
405             || (priv->aui)) {
406                 status = MII_GS_LINK;
407                 DBG ( "TLAN:  %s: Link forced.\n", priv->nic_name );
408         } else {
409                 TLan_MiiReadReg(nic, phy, MII_GEN_STS, &status);
410                 udelay(1000);
411                 TLan_MiiReadReg(nic, phy, MII_GEN_STS, &status);
412                 if ((status & MII_GS_LINK) &&   /* We only support link info on Nat.Sem. PHY's */
413                     (tlphy_id1 == NAT_SEM_ID1)
414                     && (tlphy_id2 == NAT_SEM_ID2)) {
415                         TLan_MiiReadReg(nic, phy, MII_AN_LPA, &partner);
416                         TLan_MiiReadReg(nic, phy, TLAN_TLPHY_PAR,
417                                         &tlphy_par);
418
419                         DBG ( "TLAN: %s: Link active with ",
420                                priv->nic_name );
421                         if (!(tlphy_par & TLAN_PHY_AN_EN_STAT)) {
422                                 DBG ( "forced 10%sMbps %s-Duplex\n",
423                                        tlphy_par & TLAN_PHY_SPEED_100 ? ""
424                                        : "0",
425                                        tlphy_par & TLAN_PHY_DUPLEX_FULL ?
426                                        "Full" : "Half" );
427                         } else {
428                                 DBG 
429                                     ( "AutoNegotiation enabled, at 10%sMbps %s-Duplex\n",
430                                      tlphy_par & TLAN_PHY_SPEED_100 ? "" :
431                                      "0",
432                                      tlphy_par & TLAN_PHY_DUPLEX_FULL ?
433                                      "Full" : "Half" );
434                                 DBG ( "TLAN: Partner capability: " );
435                                 for (i = 5; i <= 10; i++)
436                                         if (partner & (1 << i)) {
437                                                 DBG ( "%s", media[i - 5] );
438                                         }
439                                 DBG ( "\n" );
440                         }
441
442                         TLan_DioWrite8(BASE, TLAN_LED_REG, TLAN_LED_LINK);
443 #ifdef MONITOR
444                         /* We have link beat..for now anyway */
445                         priv->link = 1;
446                         /*Enabling link beat monitoring */
447                         /* TLan_SetTimer( nic, (10*HZ), TLAN_TIMER_LINK_BEAT ); */
448                         mdelay(10000);
449                         TLan_PhyMonitor(nic);
450 #endif
451                 } else if (status & MII_GS_LINK) {
452                         DBG ( "TLAN: %s: Link active\n", priv->nic_name );
453                         TLan_DioWrite8(BASE, TLAN_LED_REG, TLAN_LED_LINK);
454                 }
455         }
456
457         if (priv->phyNum == 0) {
458                 TLan_MiiReadReg(nic, phy, TLAN_TLPHY_CTL, &tlphy_ctl);
459                 tlphy_ctl |= TLAN_TC_INTEN;
460                 TLan_MiiWriteReg(nic, phy, TLAN_TLPHY_CTL, tlphy_ctl);
461                 sio = TLan_DioRead8(BASE, TLAN_NET_SIO);
462                 sio |= TLAN_NET_SIO_MINTEN;
463                 TLan_DioWrite8(BASE, TLAN_NET_SIO, sio);
464         }
465
466         if (status & MII_GS_LINK) {
467                 TLan_SetMac(nic, 0, nic->node_addr);
468                 priv->phyOnline = 1;
469                 outb((TLAN_HC_INT_ON >> 8), BASE + TLAN_HOST_CMD + 1);
470                 outl(virt_to_bus(&rx_ring), BASE + TLAN_CH_PARM);
471                 outl(TLAN_HC_GO | TLAN_HC_RT, BASE + TLAN_HOST_CMD);
472         } else {
473                 DBG 
474                     ( "TLAN: %s: Link inactive, will retry in 10 secs...\n",
475                      priv->nic_name );
476                 /* TLan_SetTimer( nic, (10*HZ), TLAN_TIMER_FINISH_RESET ); */
477                 mdelay(10000);
478                 TLan_FinishReset(nic);
479                 return;
480
481         }
482
483 }       /* TLan_FinishReset */
484
485 /**************************************************************************
486 POLL - Wait for a frame
487 ***************************************************************************/
488 static int tlan_poll(struct nic *nic, int retrieve)
489 {
490         /* return true if there's an ethernet packet ready to read */
491         /* nic->packet should contain data on return */
492         /* nic->packetlen should contain length of data */
493         u32 framesize;
494         u32 host_cmd = 0;
495         u32 ack = 1;
496         int eoc = 0;
497         int entry = priv->cur_rx % TLAN_NUM_RX_LISTS;
498         u16 tmpCStat = le32_to_cpu(rx_ring[entry].cStat);
499         u16 host_int = inw(BASE + TLAN_HOST_INT);
500
501         if ((tmpCStat & TLAN_CSTAT_FRM_CMP) && !retrieve)
502           return 1;
503
504         outw(host_int, BASE + TLAN_HOST_INT);
505
506         if (!(tmpCStat & TLAN_CSTAT_FRM_CMP))
507                 return 0;
508
509         /* printf("PI-1: 0x%hX\n", host_int); */
510         if (tmpCStat & TLAN_CSTAT_EOC)
511                 eoc = 1;
512
513         framesize = rx_ring[entry].frameSize;
514
515         nic->packetlen = framesize;
516
517         DBG ( ".%d.", (unsigned int) framesize ); 
518      
519         memcpy(nic->packet, rxb +
520                (priv->cur_rx * TLAN_MAX_FRAME_SIZE), nic->packetlen);
521
522         rx_ring[entry].cStat = 0;
523
524         DBG ( "%d", entry );  
525
526         entry = (entry + 1) % TLAN_NUM_RX_LISTS;
527         priv->cur_rx = entry;
528         if (eoc) {
529                 if ((rx_ring[entry].cStat & TLAN_CSTAT_READY) ==
530                     TLAN_CSTAT_READY) {
531                         ack |= TLAN_HC_GO | TLAN_HC_RT;
532                         host_cmd = TLAN_HC_ACK | ack | 0x001C0000;
533                         outl(host_cmd, BASE + TLAN_HOST_CMD);
534                 }
535         } else {
536                 host_cmd = TLAN_HC_ACK | ack | (0x000C0000);
537                 outl(host_cmd, BASE + TLAN_HOST_CMD);
538                 
539                 DBG ( "AC: 0x%hX\n", inw(BASE + TLAN_CH_PARM) ); 
540                 DBG ( "PI-2: 0x%hX\n", inw(BASE + TLAN_HOST_INT) );
541         }
542         refill_rx(nic);
543         return (1);             /* initially as this is called to flush the input */
544 }
545
546 static void refill_rx(struct nic *nic __unused)
547 {
548         int entry = 0;
549
550         for (;
551              (priv->cur_rx - priv->dirty_rx +
552               TLAN_NUM_RX_LISTS) % TLAN_NUM_RX_LISTS > 0;
553              priv->dirty_rx = (priv->dirty_rx + 1) % TLAN_NUM_RX_LISTS) {
554                 entry = priv->dirty_rx % TLAN_NUM_TX_LISTS;
555                 rx_ring[entry].frameSize = TLAN_MAX_FRAME_SIZE;
556                 rx_ring[entry].cStat = TLAN_CSTAT_READY;
557         }
558
559 }
560
561 /**************************************************************************
562 TRANSMIT - Transmit a frame
563 ***************************************************************************/
564 static void tlan_transmit(struct nic *nic, const char *d,       /* Destination */
565                           unsigned int t,       /* Type */
566                           unsigned int s,       /* size */
567                           const char *p)
568 {                               /* Packet */
569         u16 nstype;
570         u32 to;
571         struct TLanList *tail_list;
572         struct TLanList *head_list;
573         u8 *tail_buffer;
574         u32 ack = 0;
575         u32 host_cmd;
576         int eoc = 0;
577         u16 tmpCStat;
578         u16 host_int = inw(BASE + TLAN_HOST_INT);
579
580         int entry = 0;
581
582         DBG ( "INT0-0x%hX\n", host_int );
583
584         if (!priv->phyOnline) {
585                 printf("TRANSMIT:  %s PHY is not ready\n", priv->nic_name);
586                 return;
587         }
588
589         tail_list = priv->txList + priv->txTail;
590
591         if (tail_list->cStat != TLAN_CSTAT_UNUSED) {
592                 printf("TRANSMIT: %s is busy (Head=%p Tail=%x)\n",
593                        priv->nic_name, priv->txList, (unsigned int) priv->txTail);
594                 tx_ring[entry].cStat = TLAN_CSTAT_UNUSED;
595 //              priv->txBusyCount++;
596                 return;
597         }
598
599         tail_list->forward = 0;
600
601         tail_buffer = txb + (priv->txTail * TLAN_MAX_FRAME_SIZE);
602
603         /* send the packet to destination */
604         memcpy(tail_buffer, d, ETH_ALEN);
605         memcpy(tail_buffer + ETH_ALEN, nic->node_addr, ETH_ALEN);
606         nstype = htons((u16) t);
607         memcpy(tail_buffer + 2 * ETH_ALEN, (u8 *) & nstype, 2);
608         memcpy(tail_buffer + ETH_HLEN, p, s);
609
610         s += ETH_HLEN;
611         s &= 0x0FFF;
612         while (s < ETH_ZLEN)
613                 tail_buffer[s++] = '\0';
614
615         /*=====================================================*/
616         /* Receive
617          * 0000 0000 0001 1100
618          * 0000 0000 0000 1100
619          * 0000 0000 0000 0011 = 0x0003
620          *
621          * 0000 0000 0000 0000 0000 0000 0000 0011
622          * 0000 0000 0000 1100 0000 0000 0000 0000 = 0x000C0000
623          *
624          * Transmit
625          * 0000 0000 0001 1100
626          * 0000 0000 0000 0100
627          * 0000 0000 0000 0001 = 0x0001
628          *
629          * 0000 0000 0000 0000 0000 0000 0000 0001
630          * 0000 0000 0000 0100 0000 0000 0000 0000 = 0x00040000
631          * */
632
633         /* Setup the transmit descriptor */
634         tail_list->frameSize = (u16) s;
635         tail_list->buffer[0].count = TLAN_LAST_BUFFER | (u32) s;
636         tail_list->buffer[1].count = 0;
637         tail_list->buffer[1].address = 0;
638
639         tail_list->cStat = TLAN_CSTAT_READY;
640
641         DBG ( "INT1-0x%hX\n", inw(BASE + TLAN_HOST_INT) );
642
643         if (!priv->txInProgress) {
644                 priv->txInProgress = 1;
645                 outl(virt_to_le32desc(tail_list), BASE + TLAN_CH_PARM);
646                 outl(TLAN_HC_GO, BASE + TLAN_HOST_CMD);
647         } else {
648                 if (priv->txTail == 0) {
649                         DBG ( "Out buffer\n" );
650                         (priv->txList + (TLAN_NUM_TX_LISTS - 1))->forward =
651                             virt_to_le32desc(tail_list);
652                 } else {
653                         DBG ( "Fix this \n" );
654                         (priv->txList + (priv->txTail - 1))->forward =
655                             virt_to_le32desc(tail_list);
656                 }
657         }
658         
659         CIRC_INC(priv->txTail, TLAN_NUM_TX_LISTS);
660
661         DBG ( "INT2-0x%hX\n", inw(BASE + TLAN_HOST_INT) );
662
663         to = currticks() + TX_TIME_OUT;
664         while ((tail_list->cStat == TLAN_CSTAT_READY) && currticks() < to);
665
666         head_list = priv->txList + priv->txHead;
667         while (((tmpCStat = head_list->cStat) & TLAN_CSTAT_FRM_CMP) 
668                         && (ack < 255)) {
669                 ack++;
670                 if(tmpCStat & TLAN_CSTAT_EOC)
671                         eoc =1;
672                 head_list->cStat = TLAN_CSTAT_UNUSED;
673                 CIRC_INC(priv->txHead, TLAN_NUM_TX_LISTS);
674                 head_list = priv->txList + priv->txHead;
675                 
676         }
677         if(!ack)
678                 printf("Incomplete TX Frame\n");
679
680         if(eoc) {
681                 head_list = priv->txList + priv->txHead;
682                 if ((head_list->cStat & TLAN_CSTAT_READY) == TLAN_CSTAT_READY) {
683                         outl(virt_to_le32desc(head_list), BASE + TLAN_CH_PARM);
684                         ack |= TLAN_HC_GO;
685                 } else {
686                         priv->txInProgress = 0;
687                 }
688         }
689         if(ack) {
690                 host_cmd = TLAN_HC_ACK | ack;
691                 outl(host_cmd, BASE + TLAN_HOST_CMD);
692         }
693         
694         if(priv->tlanRev < 0x30 ) {
695                 ack = 1;
696                 head_list = priv->txList + priv->txHead;
697                 if ((head_list->cStat & TLAN_CSTAT_READY) == TLAN_CSTAT_READY) {
698                         outl(virt_to_le32desc(head_list), BASE + TLAN_CH_PARM);
699                         ack |= TLAN_HC_GO;
700                 } else {
701                         priv->txInProgress = 0;
702                 }
703                 host_cmd = TLAN_HC_ACK | ack | 0x00140000;
704                 outl(host_cmd, BASE + TLAN_HOST_CMD);
705                 
706         }
707                         
708         if (currticks() >= to) {
709                 printf("TX Time Out");
710         }
711 }
712
713 /**************************************************************************
714 DISABLE - Turn off ethernet interface
715 ***************************************************************************/
716 static void tlan_disable ( struct nic *nic __unused ) {
717         /* put the card in its initial state */
718         /* This function serves 3 purposes.
719          * This disables DMA and interrupts so we don't receive
720          *  unexpected packets or interrupts from the card after
721          *  etherboot has finished.
722          * This frees resources so etherboot may use
723          *  this driver on another interface
724          * This allows etherboot to reinitialize the interface
725          *  if something is something goes wrong.
726          *
727          */
728         outl(TLAN_HC_AD_RST, BASE + TLAN_HOST_CMD);
729 }
730
731 /**************************************************************************
732 IRQ - Enable, Disable, or Force interrupts
733 ***************************************************************************/
734 static void tlan_irq(struct nic *nic __unused, irq_action_t action __unused)
735 {
736   switch ( action ) {
737   case DISABLE :
738     break;
739   case ENABLE :
740     break;
741   case FORCE :
742     break;
743   }
744 }
745
746 static struct nic_operations tlan_operations = {
747         .connect        = dummy_connect,
748         .poll           = tlan_poll,
749         .transmit       = tlan_transmit,
750         .irq            = tlan_irq,
751
752 };
753
754 static void TLan_SetMulticastList(struct nic *nic) {
755         int i;
756         u8 tmp;
757
758         /* !IFF_PROMISC */
759         tmp = TLan_DioRead8(BASE, TLAN_NET_CMD);
760         TLan_DioWrite8(BASE, TLAN_NET_CMD, tmp & ~TLAN_NET_CMD_CAF);
761
762         /* IFF_ALLMULTI */
763         for(i = 0; i< 3; i++)
764                 TLan_SetMac(nic, i + 1, NULL);
765         TLan_DioWrite32(BASE, TLAN_HASH_1, 0xFFFFFFFF);
766         TLan_DioWrite32(BASE, TLAN_HASH_2, 0xFFFFFFFF);
767
768         
769 }
770 /**************************************************************************
771 PROBE - Look for an adapter, this routine's visible to the outside
772 ***************************************************************************/
773
774 #define board_found 1
775 #define valid_link 0
776 static int tlan_probe ( struct nic *nic, struct pci_device *pci ) {
777
778         u16 data = 0;
779         int err;
780         int i;
781
782         if (pci->ioaddr == 0)
783                 return 0;
784
785         nic->irqno  = 0;
786         nic->ioaddr = pci->ioaddr;
787
788         BASE = pci->ioaddr;
789
790         /* Set nic as PCI bus master */
791         adjust_pci_device(pci);
792         
793         /* Point to private storage */
794         priv = &TLanPrivateInfo;
795
796         /* Figure out which chip we're dealing with */
797         i = 0;
798         chip_idx = -1;
799         while (tlan_pci_tbl[i].name) {
800                 if ((((u32) pci->device << 16) | pci->vendor) ==
801                     (tlan_pci_tbl[i].id.pci & 0xffffffff)) {
802                         chip_idx = i;
803                         break;
804                 }
805                 i++;
806         }
807
808         priv->vendor_id = pci->vendor;
809         priv->dev_id = pci->device;
810         priv->nic_name = pci->driver_name;
811         priv->eoc = 0;
812
813         err = 0;
814         for (i = 0; i < 6; i++)
815                 err |= TLan_EeReadByte(BASE,
816                                        (u8) tlan_pci_tbl[chip_idx].
817                                        addrOfs + i,
818                                        (u8 *) & nic->node_addr[i]);
819         if (err) {
820             printf ( "TLAN: %s: Error reading MAC from eeprom: %d\n",
821                     pci->driver_name, err);
822         } else {
823             DBG ( "%s: %s at ioaddr %#lX, ", 
824                   pci->driver_name, eth_ntoa ( nic->node_addr ), pci->ioaddr );
825         }
826
827         priv->tlanRev = TLan_DioRead8(BASE, TLAN_DEF_REVISION);
828         printf("revision: 0x%hX\n", priv->tlanRev);
829
830         TLan_ResetLists(nic);
831         TLan_ResetAdapter(nic);
832
833         data = inl(BASE + TLAN_HOST_CMD);
834         data |= TLAN_HC_INT_OFF;
835         outw(data, BASE + TLAN_HOST_CMD);
836
837         TLan_SetMulticastList(nic);
838         udelay(100); 
839         priv->txList = tx_ring;
840
841 /*      if (board_found && valid_link)
842         {*/
843         /* point to NIC specific routines */
844         nic->nic_op     = &tlan_operations;
845         return 1;
846 }
847
848
849 /*****************************************************************************
850 ******************************************************************************
851
852         ThunderLAN Driver Eeprom routines
853
854         The Compaq Netelligent 10 and 10/100 cards use a Microchip 24C02A
855         EEPROM.  These functions are based on information in Microchip's
856         data sheet.  I don't know how well this functions will work with
857         other EEPROMs.
858
859 ******************************************************************************
860 *****************************************************************************/
861
862
863 /***************************************************************
864 *       TLan_EeSendStart
865 *
866 *       Returns:
867 *               Nothing
868 *       Parms:
869 *               io_base         The IO port base address for the
870 *                               TLAN device with the EEPROM to
871 *                               use.
872 *
873 *       This function sends a start cycle to an EEPROM attached
874 *       to a TLAN chip.
875 *
876 **************************************************************/
877
878 void TLan_EeSendStart(u16 io_base)
879 {
880         u16 sio;
881
882         outw(TLAN_NET_SIO, io_base + TLAN_DIO_ADR);
883         sio = io_base + TLAN_DIO_DATA + TLAN_NET_SIO;
884
885         TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
886         TLan_SetBit(TLAN_NET_SIO_EDATA, sio);
887         TLan_SetBit(TLAN_NET_SIO_ETXEN, sio);
888         TLan_ClearBit(TLAN_NET_SIO_EDATA, sio);
889         TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
890
891 }       /* TLan_EeSendStart */
892
893 /***************************************************************
894 *       TLan_EeSendByte
895 *
896 *       Returns:
897 *               If the correct ack was received, 0, otherwise 1
898 *       Parms:  io_base         The IO port base address for the
899 *                               TLAN device with the EEPROM to
900 *                               use.
901 *               data            The 8 bits of information to
902 *                               send to the EEPROM.
903 *               stop            If TLAN_EEPROM_STOP is passed, a
904 *                               stop cycle is sent after the
905 *                               byte is sent after the ack is
906 *                               read.
907 *
908 *       This function sends a byte on the serial EEPROM line,
909 *       driving the clock to send each bit. The function then
910 *       reverses transmission direction and reads an acknowledge
911 *       bit.
912 *
913 **************************************************************/
914
915 int TLan_EeSendByte(u16 io_base, u8 data, int stop)
916 {
917         int err;
918         u8 place;
919         u16 sio;
920
921         outw(TLAN_NET_SIO, io_base + TLAN_DIO_ADR);
922         sio = io_base + TLAN_DIO_DATA + TLAN_NET_SIO;
923
924         /* Assume clock is low, tx is enabled; */
925         for (place = 0x80; place != 0; place >>= 1) {
926                 if (place & data)
927                         TLan_SetBit(TLAN_NET_SIO_EDATA, sio);
928                 else
929                         TLan_ClearBit(TLAN_NET_SIO_EDATA, sio);
930                 TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
931                 TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
932         }
933         TLan_ClearBit(TLAN_NET_SIO_ETXEN, sio);
934         TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
935         err = TLan_GetBit(TLAN_NET_SIO_EDATA, sio);
936         TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
937         TLan_SetBit(TLAN_NET_SIO_ETXEN, sio);
938
939         if ((!err) && stop) {
940                 TLan_ClearBit(TLAN_NET_SIO_EDATA, sio); /* STOP, raise data while clock is high */
941                 TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
942                 TLan_SetBit(TLAN_NET_SIO_EDATA, sio);
943         }
944
945         return (err);
946
947 }       /* TLan_EeSendByte */
948
949 /***************************************************************
950 *       TLan_EeReceiveByte
951 *
952 *       Returns:
953 *               Nothing
954 *       Parms:
955 *               io_base         The IO port base address for the
956 *                               TLAN device with the EEPROM to
957 *                               use.
958 *               data            An address to a char to hold the
959 *                               data sent from the EEPROM.
960 *               stop            If TLAN_EEPROM_STOP is passed, a
961 *                               stop cycle is sent after the
962 *                               byte is received, and no ack is
963 *                               sent.
964 *
965 *       This function receives 8 bits of data from the EEPROM
966 *       over the serial link.  It then sends and ack bit, or no
967 *       ack and a stop bit.  This function is used to retrieve
968 *       data after the address of a byte in the EEPROM has been
969 *       sent.
970 *
971 **************************************************************/
972
973 void TLan_EeReceiveByte(u16 io_base, u8 * data, int stop)
974 {
975         u8 place;
976         u16 sio;
977
978         outw(TLAN_NET_SIO, io_base + TLAN_DIO_ADR);
979         sio = io_base + TLAN_DIO_DATA + TLAN_NET_SIO;
980         *data = 0;
981
982         /* Assume clock is low, tx is enabled; */
983         TLan_ClearBit(TLAN_NET_SIO_ETXEN, sio);
984         for (place = 0x80; place; place >>= 1) {
985                 TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
986                 if (TLan_GetBit(TLAN_NET_SIO_EDATA, sio))
987                         *data |= place;
988                 TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
989         }
990
991         TLan_SetBit(TLAN_NET_SIO_ETXEN, sio);
992         if (!stop) {
993                 TLan_ClearBit(TLAN_NET_SIO_EDATA, sio); /* Ack = 0 */
994                 TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
995                 TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
996         } else {
997                 TLan_SetBit(TLAN_NET_SIO_EDATA, sio);   /* No ack = 1 (?) */
998                 TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
999                 TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
1000                 TLan_ClearBit(TLAN_NET_SIO_EDATA, sio); /* STOP, raise data while clock is high */
1001                 TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
1002                 TLan_SetBit(TLAN_NET_SIO_EDATA, sio);
1003         }
1004
1005 }       /* TLan_EeReceiveByte */
1006
1007 /***************************************************************
1008 *       TLan_EeReadByte
1009 *
1010 *       Returns:
1011 *               No error = 0, else, the stage at which the error
1012 *               occurred.
1013 *       Parms:
1014 *               io_base         The IO port base address for the
1015 *                               TLAN device with the EEPROM to
1016 *                               use.
1017 *               ee_addr         The address of the byte in the
1018 *                               EEPROM whose contents are to be
1019 *                               retrieved.
1020 *               data            An address to a char to hold the
1021 *                               data obtained from the EEPROM.
1022 *
1023 *       This function reads a byte of information from an byte
1024 *       cell in the EEPROM.
1025 *
1026 **************************************************************/
1027
1028 int TLan_EeReadByte(u16 io_base, u8 ee_addr, u8 * data)
1029 {
1030         int err;
1031         int ret = 0;
1032
1033
1034         TLan_EeSendStart(io_base);
1035         err = TLan_EeSendByte(io_base, 0xA0, TLAN_EEPROM_ACK);
1036         if (err) {
1037                 ret = 1;
1038                 goto fail;
1039         }
1040         err = TLan_EeSendByte(io_base, ee_addr, TLAN_EEPROM_ACK);
1041         if (err) {
1042                 ret = 2;
1043                 goto fail;
1044         }
1045         TLan_EeSendStart(io_base);
1046         err = TLan_EeSendByte(io_base, 0xA1, TLAN_EEPROM_ACK);
1047         if (err) {
1048                 ret = 3;
1049                 goto fail;
1050         }
1051         TLan_EeReceiveByte(io_base, data, TLAN_EEPROM_STOP);
1052       fail:
1053
1054         return ret;
1055
1056 }       /* TLan_EeReadByte */
1057
1058
1059 /*****************************************************************************
1060 ******************************************************************************
1061
1062 ThunderLAN Driver MII Routines
1063
1064 These routines are based on the information in Chap. 2 of the
1065 "ThunderLAN Programmer's Guide", pp. 15-24.
1066
1067 ******************************************************************************
1068 *****************************************************************************/
1069
1070
1071 /***************************************************************
1072 *       TLan_MiiReadReg
1073 *
1074 *       Returns:
1075 *               0       if ack received ok
1076 *               1       otherwise.
1077 *
1078 *       Parms:
1079 *               dev             The device structure containing
1080 *                               The io address and interrupt count
1081 *                               for this device.
1082 *               phy             The address of the PHY to be queried.
1083 *               reg             The register whose contents are to be
1084 *                               retreived.
1085 *               val             A pointer to a variable to store the
1086 *                               retrieved value.
1087 *
1088 *       This function uses the TLAN's MII bus to retreive the contents
1089 *       of a given register on a PHY.  It sends the appropriate info
1090 *       and then reads the 16-bit register value from the MII bus via
1091 *       the TLAN SIO register.
1092 *
1093 **************************************************************/
1094
1095 int TLan_MiiReadReg(struct nic *nic __unused, u16 phy, u16 reg, u16 * val)
1096 {
1097         u8 nack;
1098         u16 sio, tmp;
1099         u32 i;
1100         int err;
1101         int minten;
1102
1103         err = FALSE;
1104         outw(TLAN_NET_SIO, BASE + TLAN_DIO_ADR);
1105         sio = BASE + TLAN_DIO_DATA + TLAN_NET_SIO;
1106
1107         TLan_MiiSync(BASE);
1108
1109         minten = TLan_GetBit(TLAN_NET_SIO_MINTEN, sio);
1110         if (minten)
1111                 TLan_ClearBit(TLAN_NET_SIO_MINTEN, sio);
1112
1113         TLan_MiiSendData(BASE, 0x1, 2); /* Start ( 01b ) */
1114         TLan_MiiSendData(BASE, 0x2, 2); /* Read  ( 10b ) */
1115         TLan_MiiSendData(BASE, phy, 5); /* Device #      */
1116         TLan_MiiSendData(BASE, reg, 5); /* Register #    */
1117
1118
1119         TLan_ClearBit(TLAN_NET_SIO_MTXEN, sio); /* Change direction */
1120
1121         TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);  /* Clock Idle bit */
1122         TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1123         TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);  /* Wait 300ns */
1124
1125         nack = TLan_GetBit(TLAN_NET_SIO_MDATA, sio);    /* Check for ACK */
1126         TLan_SetBit(TLAN_NET_SIO_MCLK, sio);    /* Finish ACK */
1127         if (nack) {             /* No ACK, so fake it */
1128                 for (i = 0; i < 16; i++) {
1129                         TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
1130                         TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1131                 }
1132                 tmp = 0xffff;
1133                 err = TRUE;
1134         } else {                /* ACK, so read data */
1135                 for (tmp = 0, i = 0x8000; i; i >>= 1) {
1136                         TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
1137                         if (TLan_GetBit(TLAN_NET_SIO_MDATA, sio))
1138                                 tmp |= i;
1139                         TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1140                 }
1141         }
1142
1143
1144         TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);  /* Idle cycle */
1145         TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1146
1147         if (minten)
1148                 TLan_SetBit(TLAN_NET_SIO_MINTEN, sio);
1149
1150         *val = tmp;
1151
1152         return err;
1153
1154 }                               /* TLan_MiiReadReg */
1155
1156 /***************************************************************
1157 *       TLan_MiiSendData
1158 *
1159 *       Returns:
1160 *               Nothing
1161 *       Parms:
1162 *               base_port       The base IO port of the adapter in
1163 *                               question.
1164 *               dev             The address of the PHY to be queried.
1165 *               data            The value to be placed on the MII bus.
1166 *               num_bits        The number of bits in data that are to
1167 *                               be placed on the MII bus.
1168 *
1169 *       This function sends on sequence of bits on the MII
1170 *       configuration bus.
1171 *
1172 **************************************************************/
1173
1174 void TLan_MiiSendData(u16 base_port, u32 data, unsigned num_bits)
1175 {
1176         u16 sio;
1177         u32 i;
1178
1179         if (num_bits == 0)
1180                 return;
1181
1182         outw(TLAN_NET_SIO, base_port + TLAN_DIO_ADR);
1183         sio = base_port + TLAN_DIO_DATA + TLAN_NET_SIO;
1184         TLan_SetBit(TLAN_NET_SIO_MTXEN, sio);
1185
1186         for (i = (0x1 << (num_bits - 1)); i; i >>= 1) {
1187                 TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
1188                 (void) TLan_GetBit(TLAN_NET_SIO_MCLK, sio);
1189                 if (data & i)
1190                         TLan_SetBit(TLAN_NET_SIO_MDATA, sio);
1191                 else
1192                         TLan_ClearBit(TLAN_NET_SIO_MDATA, sio);
1193                 TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1194                 (void) TLan_GetBit(TLAN_NET_SIO_MCLK, sio);
1195         }
1196
1197 }                               /* TLan_MiiSendData */
1198
1199 /***************************************************************
1200 *       TLan_MiiSync
1201 *
1202 *       Returns:
1203 *               Nothing
1204 *       Parms:
1205 *               base_port       The base IO port of the adapter in
1206 *                               question.
1207 *
1208 *       This functions syncs all PHYs in terms of the MII configuration
1209 *       bus.
1210 *
1211 **************************************************************/
1212
1213 void TLan_MiiSync(u16 base_port)
1214 {
1215         int i;
1216         u16 sio;
1217
1218         outw(TLAN_NET_SIO, base_port + TLAN_DIO_ADR);
1219         sio = base_port + TLAN_DIO_DATA + TLAN_NET_SIO;
1220
1221         TLan_ClearBit(TLAN_NET_SIO_MTXEN, sio);
1222         for (i = 0; i < 32; i++) {
1223                 TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
1224                 TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1225         }
1226
1227 }                               /* TLan_MiiSync */
1228
1229 /***************************************************************
1230 *       TLan_MiiWriteReg
1231 *
1232 *       Returns:
1233 *               Nothing
1234 *       Parms:
1235 *               dev             The device structure for the device
1236 *                               to write to.
1237 *               phy             The address of the PHY to be written to.
1238 *               reg             The register whose contents are to be
1239 *                               written.
1240 *               val             The value to be written to the register.
1241 *
1242 *       This function uses the TLAN's MII bus to write the contents of a
1243 *       given register on a PHY.  It sends the appropriate info and then
1244 *       writes the 16-bit register value from the MII configuration bus
1245 *       via the TLAN SIO register.
1246 *
1247 **************************************************************/
1248
1249 void TLan_MiiWriteReg(struct nic *nic __unused, u16 phy, u16 reg, u16 val)
1250 {
1251         u16 sio;
1252         int minten;
1253
1254         outw(TLAN_NET_SIO, BASE + TLAN_DIO_ADR);
1255         sio = BASE + TLAN_DIO_DATA + TLAN_NET_SIO;
1256
1257         TLan_MiiSync(BASE);
1258
1259         minten = TLan_GetBit(TLAN_NET_SIO_MINTEN, sio);
1260         if (minten)
1261                 TLan_ClearBit(TLAN_NET_SIO_MINTEN, sio);
1262
1263         TLan_MiiSendData(BASE, 0x1, 2); /* Start ( 01b ) */
1264         TLan_MiiSendData(BASE, 0x1, 2); /* Write ( 01b ) */
1265         TLan_MiiSendData(BASE, phy, 5); /* Device #      */
1266         TLan_MiiSendData(BASE, reg, 5); /* Register #    */
1267
1268         TLan_MiiSendData(BASE, 0x2, 2); /* Send ACK */
1269         TLan_MiiSendData(BASE, val, 16);        /* Send Data */
1270
1271         TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);  /* Idle cycle */
1272         TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1273
1274         if (minten)
1275                 TLan_SetBit(TLAN_NET_SIO_MINTEN, sio);
1276
1277
1278 }                               /* TLan_MiiWriteReg */
1279
1280 /***************************************************************
1281 *       TLan_SetMac
1282 *
1283 *       Returns:
1284 *               Nothing
1285 *       Parms:
1286 *               dev     Pointer to device structure of adapter
1287 *                       on which to change the AREG.
1288 *               areg    The AREG to set the address in (0 - 3).
1289 *               mac     A pointer to an array of chars.  Each
1290 *                       element stores one byte of the address.
1291 *                       IE, it isn't in ascii.
1292 *
1293 *       This function transfers a MAC address to one of the
1294 *       TLAN AREGs (address registers).  The TLAN chip locks
1295 *       the register on writing to offset 0 and unlocks the
1296 *       register after writing to offset 5.  If NULL is passed
1297 *       in mac, then the AREG is filled with 0's.
1298 *
1299 **************************************************************/
1300
1301 void TLan_SetMac(struct nic *nic __unused, int areg, unsigned char *mac)
1302 {
1303         int i;
1304
1305         areg *= 6;
1306
1307         if (mac != NULL) {
1308                 for (i = 0; i < 6; i++)
1309                         TLan_DioWrite8(BASE, TLAN_AREG_0 + areg + i,
1310                                        mac[i]);
1311         } else {
1312                 for (i = 0; i < 6; i++)
1313                         TLan_DioWrite8(BASE, TLAN_AREG_0 + areg + i, 0);
1314         }
1315
1316 }                               /* TLan_SetMac */
1317
1318 /*********************************************************************
1319 *       TLan_PhyDetect
1320 *
1321 *       Returns:
1322 *               Nothing
1323 *       Parms:
1324 *               dev     A pointer to the device structure of the adapter
1325 *                       for which the PHY needs determined.
1326 *
1327 *       So far I've found that adapters which have external PHYs
1328 *       may also use the internal PHY for part of the functionality.
1329 *       (eg, AUI/Thinnet).  This function finds out if this TLAN
1330 *       chip has an internal PHY, and then finds the first external
1331 *       PHY (starting from address 0) if it exists).
1332 *
1333 ********************************************************************/
1334
1335 void TLan_PhyDetect(struct nic *nic)
1336 {
1337         u16 control;
1338         u16 hi;
1339         u16 lo;
1340         u32 phy;
1341
1342         if (tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_UNMANAGED_PHY) {
1343                 priv->phyNum = 0xFFFF;
1344                 return;
1345         }
1346
1347         TLan_MiiReadReg(nic, TLAN_PHY_MAX_ADDR, MII_GEN_ID_HI, &hi);
1348
1349         if (hi != 0xFFFF) {
1350                 priv->phy[0] = TLAN_PHY_MAX_ADDR;
1351         } else {
1352                 priv->phy[0] = TLAN_PHY_NONE;
1353         }
1354
1355         priv->phy[1] = TLAN_PHY_NONE;
1356         for (phy = 0; phy <= TLAN_PHY_MAX_ADDR; phy++) {
1357                 TLan_MiiReadReg(nic, phy, MII_GEN_CTL, &control);
1358                 TLan_MiiReadReg(nic, phy, MII_GEN_ID_HI, &hi);
1359                 TLan_MiiReadReg(nic, phy, MII_GEN_ID_LO, &lo);
1360                 if ((control != 0xFFFF) || (hi != 0xFFFF)
1361                     || (lo != 0xFFFF)) {
1362                         printf("PHY found at %hX %hX %hX %hX\n", 
1363                                (unsigned int) phy, control, hi, lo);
1364                         if ((priv->phy[1] == TLAN_PHY_NONE)
1365                             && (phy != TLAN_PHY_MAX_ADDR)) {
1366                                 priv->phy[1] = phy;
1367                         }
1368                 }
1369         }
1370
1371         if (priv->phy[1] != TLAN_PHY_NONE) {
1372                 priv->phyNum = 1;
1373         } else if (priv->phy[0] != TLAN_PHY_NONE) {
1374                 priv->phyNum = 0;
1375         } else {
1376                 printf
1377                     ("TLAN:  Cannot initialize device, no PHY was found!\n");
1378         }
1379
1380 }                               /* TLan_PhyDetect */
1381
1382 void TLan_PhyPowerDown(struct nic *nic)
1383 {
1384
1385         u16 value;
1386         DBG ( "%s: Powering down PHY(s).\n", priv->nic_name );
1387         value = MII_GC_PDOWN | MII_GC_LOOPBK | MII_GC_ISOLATE;
1388         TLan_MiiSync(BASE);
1389         TLan_MiiWriteReg(nic, priv->phy[priv->phyNum], MII_GEN_CTL, value);
1390         if ((priv->phyNum == 0) && (priv->phy[1] != TLAN_PHY_NONE)
1391             &&
1392             (!(tlan_pci_tbl[chip_idx].
1393                flags & TLAN_ADAPTER_USE_INTERN_10))) {
1394                 TLan_MiiSync(BASE);
1395                 TLan_MiiWriteReg(nic, priv->phy[1], MII_GEN_CTL, value);
1396         }
1397
1398         /* Wait for 50 ms and powerup
1399          * This is abitrary.  It is intended to make sure the
1400          * tranceiver settles.
1401          */
1402         /* TLan_SetTimer( dev, (HZ/20), TLAN_TIMER_PHY_PUP ); */
1403         mdelay(50);
1404         TLan_PhyPowerUp(nic);
1405
1406 }                               /* TLan_PhyPowerDown */
1407
1408
1409 void TLan_PhyPowerUp(struct nic *nic)
1410 {
1411         u16 value;
1412
1413         DBG ( "%s: Powering up PHY.\n", priv->nic_name );
1414         TLan_MiiSync(BASE);
1415         value = MII_GC_LOOPBK;
1416         TLan_MiiWriteReg(nic, priv->phy[priv->phyNum], MII_GEN_CTL, value);
1417         TLan_MiiSync(BASE);
1418         /* Wait for 500 ms and reset the
1419          * tranceiver.  The TLAN docs say both 50 ms and
1420          * 500 ms, so do the longer, just in case.
1421          */
1422         mdelay(500);
1423         TLan_PhyReset(nic);
1424         /* TLan_SetTimer( dev, (HZ/20), TLAN_TIMER_PHY_RESET ); */
1425
1426 }                               /* TLan_PhyPowerUp */
1427
1428 void TLan_PhyReset(struct nic *nic)
1429 {
1430         u16 phy;
1431         u16 value;
1432
1433         phy = priv->phy[priv->phyNum];
1434
1435         DBG ( "%s: Reseting PHY.\n", priv->nic_name );
1436         TLan_MiiSync(BASE);
1437         value = MII_GC_LOOPBK | MII_GC_RESET;
1438         TLan_MiiWriteReg(nic, phy, MII_GEN_CTL, value);
1439         TLan_MiiReadReg(nic, phy, MII_GEN_CTL, &value);
1440         while (value & MII_GC_RESET) {
1441                 TLan_MiiReadReg(nic, phy, MII_GEN_CTL, &value);
1442         }
1443
1444         /* Wait for 500 ms and initialize.
1445          * I don't remember why I wait this long.
1446          * I've changed this to 50ms, as it seems long enough.
1447          */
1448         /* TLan_SetTimer( dev, (HZ/20), TLAN_TIMER_PHY_START_LINK ); */
1449         mdelay(50);
1450         TLan_PhyStartLink(nic);
1451
1452 }                               /* TLan_PhyReset */
1453
1454
1455 void TLan_PhyStartLink(struct nic *nic)
1456 {
1457
1458         u16 ability;
1459         u16 control;
1460         u16 data;
1461         u16 phy;
1462         u16 status;
1463         u16 tctl;
1464
1465         phy = priv->phy[priv->phyNum];
1466         DBG ( "%s: Trying to activate link.\n", priv->nic_name );
1467         TLan_MiiReadReg(nic, phy, MII_GEN_STS, &status);
1468         TLan_MiiReadReg(nic, phy, MII_GEN_STS, &ability);
1469
1470         if ((status & MII_GS_AUTONEG) && (!priv->aui)) {
1471                 ability = status >> 11;
1472                 if (priv->speed == TLAN_SPEED_10 &&
1473                     priv->duplex == TLAN_DUPLEX_HALF) {
1474                         TLan_MiiWriteReg(nic, phy, MII_GEN_CTL, 0x0000);
1475                 } else if (priv->speed == TLAN_SPEED_10 &&
1476                            priv->duplex == TLAN_DUPLEX_FULL) {
1477                         priv->tlanFullDuplex = TRUE;
1478                         TLan_MiiWriteReg(nic, phy, MII_GEN_CTL, 0x0100);
1479                 } else if (priv->speed == TLAN_SPEED_100 &&
1480                            priv->duplex == TLAN_DUPLEX_HALF) {
1481                         TLan_MiiWriteReg(nic, phy, MII_GEN_CTL, 0x2000);
1482                 } else if (priv->speed == TLAN_SPEED_100 &&
1483                            priv->duplex == TLAN_DUPLEX_FULL) {
1484                         priv->tlanFullDuplex = TRUE;
1485                         TLan_MiiWriteReg(nic, phy, MII_GEN_CTL, 0x2100);
1486                 } else {
1487
1488                         /* Set Auto-Neg advertisement */
1489                         TLan_MiiWriteReg(nic, phy, MII_AN_ADV,
1490                                          (ability << 5) | 1);
1491                         /* Enablee Auto-Neg */
1492                         TLan_MiiWriteReg(nic, phy, MII_GEN_CTL, 0x1000);
1493                         /* Restart Auto-Neg */
1494                         TLan_MiiWriteReg(nic, phy, MII_GEN_CTL, 0x1200);
1495                         /* Wait for 4 sec for autonegotiation
1496                          * to complete.  The max spec time is less than this
1497                          * but the card need additional time to start AN.
1498                          * .5 sec should be plenty extra.
1499                          */
1500                         DBG ( "TLAN: %s: Starting autonegotiation.\n",
1501                                priv->nic_name );
1502                         mdelay(4000);
1503                         TLan_PhyFinishAutoNeg(nic);
1504                         /* TLan_SetTimer( dev, (2*HZ), TLAN_TIMER_PHY_FINISH_AN ); */
1505                         return;
1506                 }
1507
1508         }
1509
1510         if ((priv->aui) && (priv->phyNum != 0)) {
1511                 priv->phyNum = 0;
1512                 data =
1513                     TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN |
1514                     TLAN_NET_CFG_PHY_EN;
1515                 TLan_DioWrite16(BASE, TLAN_NET_CONFIG, data);
1516                 mdelay(50);
1517                 /* TLan_SetTimer( dev, (40*HZ/1000), TLAN_TIMER_PHY_PDOWN ); */
1518                 TLan_PhyPowerDown(nic);
1519                 return;
1520         } else if (priv->phyNum == 0) {
1521                 control = 0;
1522                 TLan_MiiReadReg(nic, phy, TLAN_TLPHY_CTL, &tctl);
1523                 if (priv->aui) {
1524                         tctl |= TLAN_TC_AUISEL;
1525                 } else {
1526                         tctl &= ~TLAN_TC_AUISEL;
1527                         if (priv->duplex == TLAN_DUPLEX_FULL) {
1528                                 control |= MII_GC_DUPLEX;
1529                                 priv->tlanFullDuplex = TRUE;
1530                         }
1531                         if (priv->speed == TLAN_SPEED_100) {
1532                                 control |= MII_GC_SPEEDSEL;
1533                         }
1534                 }
1535                 TLan_MiiWriteReg(nic, phy, MII_GEN_CTL, control);
1536                 TLan_MiiWriteReg(nic, phy, TLAN_TLPHY_CTL, tctl);
1537         }
1538
1539         /* Wait for 2 sec to give the tranceiver time
1540          * to establish link.
1541          */
1542         /* TLan_SetTimer( dev, (4*HZ), TLAN_TIMER_FINISH_RESET ); */
1543         mdelay(2000);
1544         TLan_FinishReset(nic);
1545
1546 }                               /* TLan_PhyStartLink */
1547
1548 void TLan_PhyFinishAutoNeg(struct nic *nic)
1549 {
1550
1551         u16 an_adv;
1552         u16 an_lpa;
1553         u16 data;
1554         u16 mode;
1555         u16 phy;
1556         u16 status;
1557
1558         phy = priv->phy[priv->phyNum];
1559
1560         TLan_MiiReadReg(nic, phy, MII_GEN_STS, &status);
1561         udelay(1000);
1562         TLan_MiiReadReg(nic, phy, MII_GEN_STS, &status);
1563
1564         if (!(status & MII_GS_AUTOCMPLT)) {
1565                 /* Wait for 8 sec to give the process
1566                  * more time.  Perhaps we should fail after a while.
1567                  */
1568                 if (!priv->neg_be_verbose++) {
1569                         printf
1570                             ("TLAN:  Giving autonegotiation more time.\n");
1571                         printf
1572                             ("TLAN:  Please check that your adapter has\n");
1573                         printf
1574                             ("TLAN:  been properly connected to a HUB or Switch.\n");
1575                         printf
1576                             ("TLAN:  Trying to establish link in the background...\n");
1577                 }
1578                 mdelay(8000);
1579                 TLan_PhyFinishAutoNeg(nic);
1580                 /* TLan_SetTimer( dev, (8*HZ), TLAN_TIMER_PHY_FINISH_AN ); */
1581                 return;
1582         }
1583
1584         DBG ( "TLAN: %s: Autonegotiation complete.\n", priv->nic_name );
1585         TLan_MiiReadReg(nic, phy, MII_AN_ADV, &an_adv);
1586         TLan_MiiReadReg(nic, phy, MII_AN_LPA, &an_lpa);
1587         mode = an_adv & an_lpa & 0x03E0;
1588         if (mode & 0x0100) {
1589                 printf("Full Duplex\n");
1590                 priv->tlanFullDuplex = TRUE;
1591         } else if (!(mode & 0x0080) && (mode & 0x0040)) {
1592                 priv->tlanFullDuplex = TRUE;
1593                 printf("Full Duplex\n");
1594         }
1595
1596         if ((!(mode & 0x0180))
1597             && (tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_USE_INTERN_10)
1598             && (priv->phyNum != 0)) {
1599                 priv->phyNum = 0;
1600                 data =
1601                     TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN |
1602                     TLAN_NET_CFG_PHY_EN;
1603                 TLan_DioWrite16(BASE, TLAN_NET_CONFIG, data);
1604                 /* TLan_SetTimer( nic, (400*HZ/1000), TLAN_TIMER_PHY_PDOWN ); */
1605                 mdelay(400);
1606                 TLan_PhyPowerDown(nic);
1607                 return;
1608         }
1609
1610         if (priv->phyNum == 0) {
1611                 if ((priv->duplex == TLAN_DUPLEX_FULL)
1612                     || (an_adv & an_lpa & 0x0040)) {
1613                         TLan_MiiWriteReg(nic, phy, MII_GEN_CTL,
1614                                          MII_GC_AUTOENB | MII_GC_DUPLEX);
1615                         DBG 
1616                             ( "TLAN:  Starting internal PHY with FULL-DUPLEX\n" );
1617                 } else {
1618                         TLan_MiiWriteReg(nic, phy, MII_GEN_CTL,
1619                                          MII_GC_AUTOENB);
1620                         DBG 
1621                             ( "TLAN:  Starting internal PHY with HALF-DUPLEX\n" );
1622                 }
1623         }
1624
1625         /* Wait for 100 ms.  No reason in partiticular.
1626          */
1627         /* TLan_SetTimer( dev, (HZ/10), TLAN_TIMER_FINISH_RESET ); */
1628         mdelay(100);
1629         TLan_FinishReset(nic);
1630
1631 }                               /* TLan_PhyFinishAutoNeg */
1632
1633 #ifdef MONITOR
1634
1635 /*********************************************************************
1636 *
1637 *      TLan_phyMonitor
1638 *
1639 *      Returns:
1640 *              None
1641 *
1642 *      Params:
1643 *              dev             The device structure of this device.
1644 *
1645 *
1646 *      This function monitors PHY condition by reading the status
1647 *      register via the MII bus. This can be used to give info
1648 *      about link changes (up/down), and possible switch to alternate
1649 *      media.
1650 *
1651 ********************************************************************/
1652
1653 void TLan_PhyMonitor(struct net_device *dev)
1654 {
1655         TLanPrivateInfo *priv = dev->priv;
1656         u16 phy;
1657         u16 phy_status;
1658
1659         phy = priv->phy[priv->phyNum];
1660
1661         /* Get PHY status register */
1662         TLan_MiiReadReg(nic, phy, MII_GEN_STS, &phy_status);
1663
1664         /* Check if link has been lost */
1665         if (!(phy_status & MII_GS_LINK)) {
1666                 if (priv->link) {
1667                         priv->link = 0;
1668                         printf("TLAN: %s has lost link\n", priv->nic_name);
1669                         priv->flags &= ~IFF_RUNNING;
1670                         mdelay(2000);
1671                         TLan_PhyMonitor(nic);
1672                         /* TLan_SetTimer( dev, (2*HZ), TLAN_TIMER_LINK_BEAT ); */
1673                         return;
1674                 }
1675         }
1676
1677         /* Link restablished? */
1678         if ((phy_status & MII_GS_LINK) && !priv->link) {
1679                 priv->link = 1;
1680                 printf("TLAN: %s has reestablished link\n",
1681                        priv->nic_name);
1682                 priv->flags |= IFF_RUNNING;
1683         }
1684
1685         /* Setup a new monitor */
1686         /* TLan_SetTimer( dev, (2*HZ), TLAN_TIMER_LINK_BEAT ); */
1687         mdelay(2000);
1688         TLan_PhyMonitor(nic);
1689 }
1690
1691 #endif                          /* MONITOR */
1692
1693 static struct pci_device_id tlan_nics[] = {
1694         PCI_ROM(0x0e11, 0xae34, "netel10", "Compaq Netelligent 10 T PCI UTP", 0),
1695         PCI_ROM(0x0e11, 0xae32, "netel100","Compaq Netelligent 10/100 TX PCI UTP", 0),
1696         PCI_ROM(0x0e11, 0xae35, "netflex3i", "Compaq Integrated NetFlex-3/P", 0),
1697         PCI_ROM(0x0e11, 0xf130, "thunder", "Compaq NetFlex-3/P", 0),
1698         PCI_ROM(0x0e11, 0xf150, "netflex3b", "Compaq NetFlex-3/P", 0),
1699         PCI_ROM(0x0e11, 0xae43, "netel100pi", "Compaq Netelligent Integrated 10/100 TX UTP", 0),
1700         PCI_ROM(0x0e11, 0xae40, "netel100d", "Compaq Netelligent Dual 10/100 TX PCI UTP", 0),
1701         PCI_ROM(0x0e11, 0xb011, "netel100i", "Compaq Netelligent 10/100 TX Embedded UTP", 0),
1702         PCI_ROM(0x108d, 0x0013, "oc2183", "Olicom OC-2183/2185", 0),
1703         PCI_ROM(0x108d, 0x0012, "oc2325", "Olicom OC-2325", 0),
1704         PCI_ROM(0x108d, 0x0014, "oc2326", "Olicom OC-2326", 0),
1705         PCI_ROM(0x0e11, 0xb030, "netelligent_10_100_ws_5100", "Compaq Netelligent 10/100 TX UTP", 0),
1706         PCI_ROM(0x0e11, 0xb012, "netelligent_10_t2", "Compaq Netelligent 10 T/2 PCI UTP/Coax", 0),
1707 };
1708
1709 PCI_DRIVER ( tlan_driver, tlan_nics, PCI_NO_CLASS );
1710
1711 DRIVER ( "TLAN/PCI", nic_driver, pci_driver, tlan_driver,
1712          tlan_probe, tlan_disable );
1713
1714 /*
1715  * Local variables:
1716  *  c-basic-offset: 8
1717  *  c-indent-level: 8
1718  *  tab-width: 8
1719  * End:
1720  */