make RTL8169_READ_GMII_REG, RTL8169_WRITE_GMII_REG static
[people/indolent/gpxe.git/.git] / src / drivers / net / r8169.c
1 /**************************************************************************
2 *    r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit
3 *    Written 2003 by Timothy Legge <tlegge@rogers.com>
4 *
5 *    This program is free software; you can redistribute it and/or modify
6 *    it under the terms of the GNU General Public License as published by
7 *    the Free Software Foundation; either version 2 of the License, or
8 *    (at your option) any later version.
9 *
10 *    This program is distributed in the hope that it will be useful,
11 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
12 *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13 *    GNU General Public License for more details.
14 *
15 *    You should have received a copy of the GNU General Public License
16 *    along with this program; if not, write to the Free Software
17 *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 *
19 *    Portions of this code based on:
20 *       r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver 
21 *               for Linux kernel 2.4.x.
22 *
23 *    Written 2002 ShuChen <shuchen@realtek.com.tw>
24 *         See Linux Driver for full information
25 *       
26 *    Linux Driver Versions: 
27 *       1.27a, 10.02.2002
28 *       RTL8169_VERSION "2.2"   <2004/08/09>
29
30 *    Thanks to:
31 *       Jean Chen of RealTek Semiconductor Corp. for
32 *       providing the evaluation NIC used to develop 
33 *       this driver.  RealTek's support for Etherboot 
34 *       is appreciated.
35 *       
36 *    REVISION HISTORY:
37 *    ================
38 *
39 *    v1.0       11-26-2003      timlegge        Initial port of Linux driver
40 *    v1.5       01-17-2004      timlegge        Initial driver output cleanup
41 *    v1.6       03-27-2004      timlegge        Additional Cleanup
42 *    v1.7       11-22-2005      timlegge        Update to RealTek Driver Version 2.2
43 *    
44 *    Indent Options: indent -kr -i8
45 ***************************************************************************/
46
47 #include "etherboot.h"
48 #include "nic.h"
49 #include <gpxe/pci.h>
50 #include <gpxe/ethernet.h>
51 #include "timer.h"
52
53 #define drv_version "v1.6"
54 #define drv_date "03-27-2004"
55
56 #define HZ 1000
57
58 static u32 ioaddr;
59
60 /* Condensed operations for readability. */
61 #define virt_to_le32desc(addr)  cpu_to_le32(virt_to_bus(addr))
62 #define le32desc_to_virt(addr)  bus_to_virt(le32_to_cpu(addr))
63
64 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
65
66 #undef RTL8169_DEBUG
67 #undef RTL8169_JUMBO_FRAME_SUPPORT
68 #undef RTL8169_HW_FLOW_CONTROL_SUPPORT
69
70
71 #undef RTL8169_IOCTL_SUPPORT
72 #undef RTL8169_DYNAMIC_CONTROL
73 #define RTL8169_USE_IO
74
75
76 #ifdef RTL8169_DEBUG
77
78 #if 0
79 #define assert(expr) \
80                if(!(expr)) { printk( "Assertion failed! %s,%s,%s,line=%d\n", #expr,__FILE__,__FUNCTION__,__LINE__); }
81 #endif
82
83 #define DBG_PRINTF( fmt, args...)   printk("r8169: " fmt, ## args);
84
85 #else
86
87 #if 0
88 #define assert(expr) do {} while (0)
89 #endif
90
91 #define DBG_PRINTF( fmt, args...)   ;
92
93 #endif                          // end of #ifdef RTL8169_DEBUG
94
95 /* media options 
96         _10_Half = 0x01,
97         _10_Full = 0x02,
98         _100_Half = 0x04,
99         _100_Full = 0x08,
100         _1000_Full = 0x10,
101 */
102 static int media = -1;
103
104 #if 0
105 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
106 static int max_interrupt_work = 20;
107 #endif
108
109 #if 0
110 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
111    The RTL chips use a 64 element hash table based on the Ethernet CRC.  */
112 static int multicast_filter_limit = 32;
113 #endif
114
115 /* MAC address length*/
116 #define MAC_ADDR_LEN    6
117
118 /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/
119 #define MAX_ETH_FRAME_SIZE      1536
120
121 #define TX_FIFO_THRESH 256      /* In bytes */
122
123 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer.  */
124 #define RX_DMA_BURST    7       /* Maximum PCI burst, '6' is 1024 */
125 #define TX_DMA_BURST    7       /* Maximum PCI burst, '6' is 1024 */
126 #define ETTh                0x3F        /* 0x3F means NO threshold */
127
128 #define EarlyTxThld     0x3F    /* 0x3F means NO early transmit */
129 #define RxPacketMaxSize 0x0800  /* Maximum size supported is 16K-1 */
130 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
131
132 #define NUM_TX_DESC     1       /* Number of Tx descriptor registers */
133 #define NUM_RX_DESC     4       /* Number of Rx descriptor registers */
134 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
135
136 #define RTL_MIN_IO_SIZE 0x80
137 #define TX_TIMEOUT  (6*HZ)
138
139 #define RTL8169_TIMER_EXPIRE_TIME 100   //100
140
141 #define ETH_HDR_LEN         14
142 #define DEFAULT_MTU         1500
143 #define DEFAULT_RX_BUF_LEN  1536
144
145
146 #ifdef RTL8169_JUMBO_FRAME_SUPPORT
147 #define MAX_JUMBO_FRAME_MTU    ( 10000 )
148 #define MAX_RX_SKBDATA_SIZE    ( MAX_JUMBO_FRAME_MTU + ETH_HDR_LEN )
149 #else
150 #define MAX_RX_SKBDATA_SIZE 1600
151 #endif                          //end #ifdef RTL8169_JUMBO_FRAME_SUPPORT
152
153 #ifdef RTL8169_USE_IO
154 #define RTL_W8(reg, val8)   outb ((val8), ioaddr + (reg))
155 #define RTL_W16(reg, val16) outw ((val16), ioaddr + (reg))
156 #define RTL_W32(reg, val32) outl ((val32), ioaddr + (reg))
157 #define RTL_R8(reg)         inb (ioaddr + (reg))
158 #define RTL_R16(reg)        inw (ioaddr + (reg))
159 #define RTL_R32(reg)        ((unsigned long) inl (ioaddr + (reg)))
160 #else
161 /* write/read MMIO register */
162 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
163 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
164 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
165 #define RTL_R8(reg)             readb (ioaddr + (reg))
166 #define RTL_R16(reg)            readw (ioaddr + (reg))
167 #define RTL_R32(reg)            ((unsigned long) readl (ioaddr + (reg)))
168 #endif
169
170 #define MCFG_METHOD_1           0x01
171 #define MCFG_METHOD_2           0x02
172 #define MCFG_METHOD_3           0x03
173 #define MCFG_METHOD_4           0x04
174
175 #define PCFG_METHOD_1           0x01    //PHY Reg 0x03 bit0-3 == 0x0000
176 #define PCFG_METHOD_2           0x02    //PHY Reg 0x03 bit0-3 == 0x0001
177 #define PCFG_METHOD_3           0x03    //PHY Reg 0x03 bit0-3 == 0x0002
178
179 static struct {
180         const char *name;
181         u8 mcfg;                /* depend on RTL8169 docs */
182         u32 RxConfigMask;       /* should clear the bits supported by this chip */
183 } rtl_chip_info[] = {
184         {
185         "RTL-8169", MCFG_METHOD_1, 0xff7e1880,}, {
186         "RTL8169s/8110s", MCFG_METHOD_2, 0xff7e1880}, {
187 "RTL8169s/8110s", MCFG_METHOD_3, 0xff7e1880},};
188
189 enum RTL8169_registers {
190         MAC0 = 0x0,             /* Ethernet hardware address. */
191         MAR0 = 0x8,             /* Multicast filter. */
192         TxDescStartAddr = 0x20,
193         TxHDescStartAddr = 0x28,
194         FLASH = 0x30,
195         ERSR = 0x36,
196         ChipCmd = 0x37,
197         TxPoll = 0x38,
198         IntrMask = 0x3C,
199         IntrStatus = 0x3E,
200         TxConfig = 0x40,
201         RxConfig = 0x44,
202         RxMissed = 0x4C,
203         Cfg9346 = 0x50,
204         Config0 = 0x51,
205         Config1 = 0x52,
206         Config2 = 0x53,
207         Config3 = 0x54,
208         Config4 = 0x55,
209         Config5 = 0x56,
210         MultiIntr = 0x5C,
211         PHYAR = 0x60,
212         TBICSR = 0x64,
213         TBI_ANAR = 0x68,
214         TBI_LPAR = 0x6A,
215         PHYstatus = 0x6C,
216         RxMaxSize = 0xDA,
217         CPlusCmd = 0xE0,
218         RxDescStartAddr = 0xE4,
219         ETThReg = 0xEC,
220         FuncEvent = 0xF0,
221         FuncEventMask = 0xF4,
222         FuncPresetState = 0xF8,
223         FuncForceEvent = 0xFC,
224 };
225
226 enum RTL8169_register_content {
227         /*InterruptStatusBits */
228         SYSErr = 0x8000,
229         PCSTimeout = 0x4000,
230         SWInt = 0x0100,
231         TxDescUnavail = 0x80,
232         RxFIFOOver = 0x40,
233         LinkChg = 0x20,
234         RxOverflow = 0x10,
235         TxErr = 0x08,
236         TxOK = 0x04,
237         RxErr = 0x02,
238         RxOK = 0x01,
239
240         /*RxStatusDesc */
241         RxRES = 0x00200000,
242         RxCRC = 0x00080000,
243         RxRUNT = 0x00100000,
244         RxRWT = 0x00400000,
245
246         /*ChipCmdBits */
247         CmdReset = 0x10,
248         CmdRxEnb = 0x08,
249         CmdTxEnb = 0x04,
250         RxBufEmpty = 0x01,
251
252         /*Cfg9346Bits */
253         Cfg9346_Lock = 0x00,
254         Cfg9346_Unlock = 0xC0,
255
256         /*rx_mode_bits */
257         AcceptErr = 0x20,
258         AcceptRunt = 0x10,
259         AcceptBroadcast = 0x08,
260         AcceptMulticast = 0x04,
261         AcceptMyPhys = 0x02,
262         AcceptAllPhys = 0x01,
263
264         /*RxConfigBits */
265         RxCfgFIFOShift = 13,
266         RxCfgDMAShift = 8,
267
268         /*TxConfigBits */
269         TxInterFrameGapShift = 24,
270         TxDMAShift = 8,         /* DMA burst value (0-7) is shift this many bits */
271
272         /*rtl8169_PHYstatus */
273         TBI_Enable = 0x80,
274         TxFlowCtrl = 0x40,
275         RxFlowCtrl = 0x20,
276         _1000bpsF = 0x10,
277         _100bps = 0x08,
278         _10bps = 0x04,
279         LinkStatus = 0x02,
280         FullDup = 0x01,
281
282         /*GIGABIT_PHY_registers */
283         PHY_CTRL_REG = 0,
284         PHY_STAT_REG = 1,
285         PHY_AUTO_NEGO_REG = 4,
286         PHY_1000_CTRL_REG = 9,
287
288         /*GIGABIT_PHY_REG_BIT */
289         PHY_Restart_Auto_Nego = 0x0200,
290         PHY_Enable_Auto_Nego = 0x1000,
291
292         /* PHY_STAT_REG = 1; */
293         PHY_Auto_Neco_Comp = 0x0020,
294
295         /* PHY_AUTO_NEGO_REG = 4; */
296         PHY_Cap_10_Half = 0x0020,
297         PHY_Cap_10_Full = 0x0040,
298         PHY_Cap_100_Half = 0x0080,
299         PHY_Cap_100_Full = 0x0100,
300
301         /* PHY_1000_CTRL_REG = 9; */
302         PHY_Cap_1000_Full = 0x0200,
303         PHY_Cap_1000_Half = 0x0100,
304
305         PHY_Cap_PAUSE = 0x0400,
306         PHY_Cap_ASYM_PAUSE = 0x0800,
307
308         PHY_Cap_Null = 0x0,
309
310         /*_MediaType*/
311         _10_Half = 0x01,
312         _10_Full = 0x02,
313         _100_Half = 0x04,
314         _100_Full = 0x08,
315         _1000_Full = 0x10,
316
317         /*_TBICSRBit*/
318         TBILinkOK = 0x02000000,
319 };
320
321 enum _DescStatusBit {
322         OWNbit = 0x80000000,
323         EORbit = 0x40000000,
324         FSbit = 0x20000000,
325         LSbit = 0x10000000,
326 };
327
328 struct TxDesc {
329         u32 status;
330         u32 vlan_tag;
331         u32 buf_addr;
332         u32 buf_Haddr;
333 };
334
335 struct RxDesc {
336         u32 status;
337         u32 vlan_tag;
338         u32 buf_addr;
339         u32 buf_Haddr;
340 };
341
342 /* The descriptors for this card are required to be aligned on 256
343  * byte boundaries.  As the align attribute does not do more than 16
344  * bytes of alignment it requires some extra steps.  Add 256 to the
345  * size of the array and the init_ring adjusts the alignment.
346  *
347  * UPDATE: This is no longer true; we can request arbitrary alignment.
348  */
349
350 /* Define the TX and RX Descriptors and Buffers */
351 #define __align_256 __attribute__ (( aligned ( 256 ) ))
352 struct {
353         struct TxDesc tx_ring[NUM_TX_DESC] __align_256;
354         unsigned char txb[NUM_TX_DESC * RX_BUF_SIZE];
355         struct RxDesc rx_ring[NUM_RX_DESC] __align_256;
356         unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE];
357 } r8169_bufs __shared;
358 #define tx_ring r8169_bufs.tx_ring
359 #define rx_ring r8169_bufs.rx_ring
360 #define txb r8169_bufs.txb
361 #define rxb r8169_bufs.rxb
362
363 static struct rtl8169_private {
364         void *mmio_addr;        /* memory map physical address */
365         int chipset;
366         int pcfg;
367         int mcfg;
368         unsigned long cur_rx;   /* Index into the Rx descriptor buffer of next Rx pkt. */
369         unsigned long cur_tx;   /* Index into the Tx descriptor buffer of next Rx pkt. */
370         struct TxDesc *TxDescArray;     /* Index of 256-alignment Tx Descriptor buffer */
371         struct RxDesc *RxDescArray;     /* Index of 256-alignment Rx Descriptor buffer */
372         unsigned char *RxBufferRing[NUM_RX_DESC];       /* Index of Rx Buffer array */
373         unsigned char *Tx_skbuff[NUM_TX_DESC];
374 } tpx;
375
376 static struct rtl8169_private *tpc;
377
378 static const u16 rtl8169_intr_mask =
379     LinkChg | RxOverflow | RxFIFOOver | TxErr | TxOK | RxErr | RxOK;
380 static const unsigned int rtl8169_rx_config =
381     (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift) |
382     0x0000000E;
383
384 static void rtl8169_hw_PHY_config(struct nic *nic __unused);
385 //static void rtl8169_hw_PHY_reset(struct net_device *dev);
386
387 #define RTL8169_WRITE_GMII_REG_BIT( ioaddr, reg, bitnum, bitval )\
388 { \
389        int val; \
390        if( bitval == 1 ){ val = ( RTL8169_READ_GMII_REG( ioaddr, reg ) | (bitval<<bitnum) ) & 0xffff ; } \
391        else{ val = ( RTL8169_READ_GMII_REG( ioaddr, reg ) & (~(0x0001<<bitnum)) ) & 0xffff ; } \
392        RTL8169_WRITE_GMII_REG( ioaddr, reg, val ); \
393  }
394
395 //=================================================================
396 //      PHYAR
397 //      bit             Symbol
398 //      31              Flag
399 //      30-21   reserved
400 //      20-16   5-bit GMII/MII register address
401 //      15-0    16-bit GMII/MII register data
402 //=================================================================
403 static void RTL8169_WRITE_GMII_REG(unsigned long ioaddr, int RegAddr, int value)
404 {
405         int i;
406
407         RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
408         udelay(1000);
409
410         for (i = 2000; i > 0; i--) {
411                 // Check if the RTL8169 has completed writing to the specified MII register
412                 if (!(RTL_R32(PHYAR) & 0x80000000)) {
413                         break;
414                 } else {
415                         udelay(100);
416                 }               // end of if( ! (RTL_R32(PHYAR)&0x80000000) )
417         }                       // end of for() loop
418 }
419
420 //=================================================================
421 static int RTL8169_READ_GMII_REG(unsigned long ioaddr, int RegAddr)
422 {
423         int i, value = -1;
424
425         RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
426         udelay(1000);
427
428         for (i = 2000; i > 0; i--) {
429                 // Check if the RTL8169 has completed retrieving data from the specified MII register
430                 if (RTL_R32(PHYAR) & 0x80000000) {
431                         value = (int) (RTL_R32(PHYAR) & 0xFFFF);
432                         break;
433                 } else {
434                         udelay(100);
435                 }               // end of if( RTL_R32(PHYAR) & 0x80000000 )
436         }                       // end of for() loop
437         return value;
438 }
439
440
441 #if 0
442 static void mdio_write(int RegAddr, int value)
443 {
444         int i;
445
446         RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
447         udelay(1000);
448
449         for (i = 2000; i > 0; i--) {
450                 /* Check if the RTL8169 has completed writing to the specified MII register */
451                 if (!(RTL_R32(PHYAR) & 0x80000000)) {
452                         break;
453                 } else {
454                         udelay(100);
455                 }
456         }
457 }
458
459 static int mdio_read(int RegAddr)
460 {
461         int i, value = -1;
462
463         RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
464         udelay(1000);
465
466         for (i = 2000; i > 0; i--) {
467                 /* Check if the RTL8169 has completed retrieving data from the specified MII register */
468                 if (RTL_R32(PHYAR) & 0x80000000) {
469                         value = (int) (RTL_R32(PHYAR) & 0xFFFF);
470                         break;
471                 } else {
472                         udelay(100);
473                 }
474         }
475         return value;
476 }
477 #endif
478
479 #define IORESOURCE_MEM 0x00000200
480
481 static int rtl8169_init_board(struct pci_device *pdev)
482 {
483         int i;
484 //      unsigned long mmio_end, mmio_flags
485         unsigned long mmio_start, mmio_len;
486
487         adjust_pci_device(pdev);
488
489         mmio_start = pci_bar_start(pdev, PCI_BASE_ADDRESS_1);
490 //       mmio_end = pci_resource_end (pdev, 1);
491 //       mmio_flags = pci_resource_flags (pdev, PCI_BASE_ADDRESS_1);
492         mmio_len = pci_bar_size(pdev, PCI_BASE_ADDRESS_1);
493
494         // make sure PCI base addr 1 is MMIO
495 //     if (!(mmio_flags & IORESOURCE_MEM)) {
496 //             printf ("region #1 not an MMIO resource, aborting\n");
497 //             return 0;
498 //     }
499
500         // check for weird/broken PCI region reporting
501         if (mmio_len < RTL_MIN_IO_SIZE) {
502                 printf("Invalid PCI region size(s), aborting\n");
503                 return 0;
504         }
505 #ifdef RTL8169_USE_IO
506         ioaddr = pci_bar_start(pdev, PCI_BASE_ADDRESS_0);
507 #else
508         // ioremap MMIO region
509         ioaddr = (unsigned long) ioremap(mmio_start, mmio_len);
510         if (ioaddr == 0) {
511                 printk("cannot remap MMIO, aborting\n");
512                 return 0;
513         }
514 #endif
515
516         tpc->mmio_addr = &ioaddr;
517         /* Soft reset the chip. */
518         RTL_W8(ChipCmd, CmdReset);
519
520         /* Check that the chip has finished the reset. */
521         for (i = 1000; i > 0; i--)
522                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
523                         break;
524                 else
525                         udelay(10);
526         // identify config method
527         {
528                 unsigned long val32 = (RTL_R32(TxConfig) & 0x7c800000);
529                 if (val32 == (0x1 << 28)) {
530                         tpc->mcfg = MCFG_METHOD_4;
531                 } else if (val32 == (0x1 << 26)) {
532                         tpc->mcfg = MCFG_METHOD_3;
533                 } else if (val32 == (0x1 << 23)) {
534                         tpc->mcfg = MCFG_METHOD_2;
535                 } else if (val32 == 0x00000000) {
536                         tpc->mcfg = MCFG_METHOD_1;
537                 } else {
538                         tpc->mcfg = MCFG_METHOD_1;
539                 }
540         }
541         {
542                 unsigned char val8 =
543                     (unsigned char) (RTL8169_READ_GMII_REG(ioaddr, 3) &
544                                      0x000f);
545                 if (val8 == 0x00) {
546                         tpc->pcfg = PCFG_METHOD_1;
547                 } else if (val8 == 0x01) {
548                         tpc->pcfg = PCFG_METHOD_2;
549                 } else if (val8 == 0x02) {
550                         tpc->pcfg = PCFG_METHOD_3;
551                 } else {
552                         tpc->pcfg = PCFG_METHOD_3;
553                 }
554         }
555
556         /* identify chip attached to board */
557
558         for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--)
559                 if (tpc->mcfg == rtl_chip_info[i].mcfg) {
560                         tpc->chipset = i;
561                         goto match;
562                 }
563         /* if unknown chip, assume array element #0, original RTL-8169 in this case */
564         DBG ( "PCI device: unknown chip version, assuming RTL-8169\n" );
565         DBG ( "PCI device: TxConfig = %#lX\n", ( unsigned long ) RTL_R32 ( TxConfig ) );
566
567         tpc->chipset = 0;
568         return 1;
569
570       match:
571         return 0;
572
573 }
574
575 /**************************************************************************
576 IRQ - Wait for a frame
577 ***************************************************************************/
578 static void r8169_irq(struct nic *nic __unused, irq_action_t action)
579 {
580         int intr_status = 0;
581         int interested = RxOverflow | RxFIFOOver | RxErr | RxOK;
582
583         switch (action) {
584         case DISABLE:
585         case ENABLE:
586                 intr_status = RTL_R16(IntrStatus);
587                 /* h/w no longer present (hotplug?) or major error, 
588                    bail */
589                 if (intr_status == 0xFFFF)
590                         break;
591                 
592                 intr_status = intr_status & ~interested;
593                 if (action == ENABLE)
594                         intr_status = intr_status | interested;
595                 RTL_W16(IntrMask, intr_status);
596                 break;
597         case FORCE:
598                 RTL_W8(TxPoll, (RTL_R8(TxPoll) | 0x01));
599                 break;
600         }
601 }
602
603 /**************************************************************************
604 POLL - Wait for a frame
605 ***************************************************************************/
606 static int r8169_poll(struct nic *nic, int retreive)
607 {
608         /* return true if there's an ethernet packet ready to read */
609         /* nic->packet should contain data on return */
610         /* nic->packetlen should contain length of data */
611         int cur_rx;
612         unsigned int intr_status = 0;
613         cur_rx = tpc->cur_rx;
614         if ((tpc->RxDescArray[cur_rx].status & OWNbit) == 0) {
615                 /* There is a packet ready */
616                 if (!retreive)
617                         return 1;
618                 intr_status = RTL_R16(IntrStatus);
619                 /* h/w no longer present (hotplug?) or major error,
620                    bail */
621                 if (intr_status == 0xFFFF)
622                         return 0;
623                 RTL_W16(IntrStatus, intr_status &
624                         ~(RxFIFOOver | RxOverflow | RxOK));
625
626                 if (!(tpc->RxDescArray[cur_rx].status & RxRES)) {
627                         nic->packetlen = (int) (tpc->RxDescArray[cur_rx].
628                                                 status & 0x00001FFF) - 4;
629                         memcpy(nic->packet, tpc->RxBufferRing[cur_rx],
630                                nic->packetlen);
631                         if (cur_rx == NUM_RX_DESC - 1)
632                                 tpc->RxDescArray[cur_rx].status =
633                                     (OWNbit | EORbit) + RX_BUF_SIZE;
634                         else
635                                 tpc->RxDescArray[cur_rx].status =
636                                     OWNbit + RX_BUF_SIZE;
637                         tpc->RxDescArray[cur_rx].buf_addr =
638                             virt_to_bus(tpc->RxBufferRing[cur_rx]);
639                 } else
640                         printf("Error Rx");
641                 /* FIXME: shouldn't I reset the status on an error */
642                 cur_rx = (cur_rx + 1) % NUM_RX_DESC;
643                 tpc->cur_rx = cur_rx;
644                 RTL_W16(IntrStatus, intr_status &
645                         (RxFIFOOver | RxOverflow | RxOK));
646
647                 return 1;
648
649         }
650         tpc->cur_rx = cur_rx;
651         /* FIXME: There is no reason to do this as cur_rx did not change */
652
653         return (0);             /* initially as this is called to flush the input */
654
655 }
656
657 /**************************************************************************
658 TRANSMIT - Transmit a frame
659 ***************************************************************************/
660 static void r8169_transmit(struct nic *nic, const char *d,      /* Destination */
661                            unsigned int t,      /* Type */
662                            unsigned int s,      /* size */
663                            const char *p)
664 {                               /* Packet */
665         /* send the packet to destination */
666
667         u16 nstype;
668         u32 to;
669         u8 *ptxb;
670         int entry = tpc->cur_tx % NUM_TX_DESC;
671
672         /* point to the current txb incase multiple tx_rings are used */
673         ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE];
674         memcpy(ptxb, d, ETH_ALEN);
675         memcpy(ptxb + ETH_ALEN, nic->node_addr, ETH_ALEN);
676         nstype = htons((u16) t);
677         memcpy(ptxb + 2 * ETH_ALEN, (u8 *) & nstype, 2);
678         memcpy(ptxb + ETH_HLEN, p, s);
679         s += ETH_HLEN;
680         s &= 0x0FFF;
681         while (s < ETH_ZLEN)
682                 ptxb[s++] = '\0';
683
684         tpc->TxDescArray[entry].buf_addr = virt_to_bus(ptxb);
685         if (entry != (NUM_TX_DESC - 1))
686                 tpc->TxDescArray[entry].status =
687                     (OWNbit | FSbit | LSbit) | ((s > ETH_ZLEN) ? s :
688                                                 ETH_ZLEN);
689         else
690                 tpc->TxDescArray[entry].status =
691                     (OWNbit | EORbit | FSbit | LSbit) | ((s > ETH_ZLEN) ? s
692                                                          : ETH_ZLEN);
693         RTL_W8(TxPoll, 0x40);   /* set polling bit */
694
695         tpc->cur_tx++;
696         to = currticks() + TX_TIMEOUT;
697         while ((tpc->TxDescArray[entry].status & OWNbit) && (currticks() < to));        /* wait */
698
699         if (currticks() >= to) {
700                 printf("TX Time Out");
701         }
702 }
703
704 static void rtl8169_set_rx_mode(struct nic *nic __unused)
705 {
706         u32 mc_filter[2];       /* Multicast hash filter */
707         int rx_mode;
708         u32 tmp = 0;
709
710         /* IFF_ALLMULTI */
711         /* Too many to filter perfectly -- accept all multicasts. */
712         rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
713         mc_filter[1] = mc_filter[0] = 0xffffffff;
714
715         tmp =
716             rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) &
717                                            rtl_chip_info[tpc->chipset].
718                                            RxConfigMask);
719
720         RTL_W32(RxConfig, tmp);
721         RTL_W32(MAR0 + 0, mc_filter[0]);
722         RTL_W32(MAR0 + 4, mc_filter[1]);
723 }
724 static void rtl8169_hw_start(struct nic *nic)
725 {
726         u32 i;
727
728         /* Soft reset the chip. */
729         RTL_W8(ChipCmd, CmdReset);
730
731         /* Check that the chip has finished the reset. */
732         for (i = 1000; i > 0; i--) {
733                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
734                         break;
735                 else
736                         udelay(10);
737         }
738
739         RTL_W8(Cfg9346, Cfg9346_Unlock);
740         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
741         RTL_W8(ETThReg, ETTh);
742
743         /* For gigabit rtl8169 */
744         RTL_W16(RxMaxSize, RxPacketMaxSize);
745
746         /* Set Rx Config register */
747         i = rtl8169_rx_config | (RTL_R32(RxConfig) &
748                                  rtl_chip_info[tpc->chipset].RxConfigMask);
749         RTL_W32(RxConfig, i);
750
751         /* Set DMA burst size and Interframe Gap Time */
752         RTL_W32(TxConfig,
753                 (TX_DMA_BURST << TxDMAShift) | (InterFrameGap <<
754                                                 TxInterFrameGapShift));
755
756
757         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd));
758
759         if (tpc->mcfg == MCFG_METHOD_2 || tpc->mcfg == MCFG_METHOD_3) {
760                 RTL_W16(CPlusCmd,
761                         (RTL_R16(CPlusCmd) | (1 << 14) | (1 << 3)));
762                 DBG_PRINTF
763                     ("Set MAC Reg C+CR Offset 0xE0: bit-3 and bit-14\n");
764         } else {
765                 RTL_W16(CPlusCmd, (RTL_R16(CPlusCmd) | (1 << 3)));
766                 DBG_PRINTF("Set MAC Reg C+CR Offset 0xE0: bit-3.\n");
767         }
768
769         {
770                 //RTL_W16(0xE2, 0x1517);
771                 //RTL_W16(0xE2, 0x152a);
772                 //RTL_W16(0xE2, 0x282a);
773                 RTL_W16(0xE2, 0x0000);
774         }
775
776
777
778         tpc->cur_rx = 0;
779
780         RTL_W32(TxDescStartAddr, virt_to_le32desc(tpc->TxDescArray));
781         RTL_W32(RxDescStartAddr, virt_to_le32desc(tpc->RxDescArray));
782         RTL_W8(Cfg9346, Cfg9346_Lock);
783         udelay(10);
784
785         RTL_W32(RxMissed, 0);
786
787         rtl8169_set_rx_mode(nic);
788
789         /* no early-rx interrupts */
790         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
791
792         RTL_W16(IntrMask, rtl8169_intr_mask);
793
794 }
795
796 static void rtl8169_init_ring(struct nic *nic __unused)
797 {
798         int i;
799
800         tpc->cur_rx = 0;
801         tpc->cur_tx = 0;
802         memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc));
803         memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc));
804
805         for (i = 0; i < NUM_TX_DESC; i++) {
806                 tpc->Tx_skbuff[i] = &txb[i];
807         }
808
809         for (i = 0; i < NUM_RX_DESC; i++) {
810                 if (i == (NUM_RX_DESC - 1))
811                         tpc->RxDescArray[i].status =
812                             (OWNbit | EORbit) | RX_BUF_SIZE;
813                 else
814                         tpc->RxDescArray[i].status = OWNbit | RX_BUF_SIZE;
815
816                 tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE];
817                 tpc->RxDescArray[i].buf_addr =
818                     virt_to_bus(tpc->RxBufferRing[i]);
819         }
820 }
821
822 /**************************************************************************
823 RESET - Finish setting up the ethernet interface
824 ***************************************************************************/
825 static void r8169_reset(struct nic *nic)
826 {
827         int i;
828
829         tpc->TxDescArray = tx_ring;
830         tpc->RxDescArray = rx_ring;
831
832         rtl8169_init_ring(nic);
833         rtl8169_hw_start(nic);
834         /* Construct a perfect filter frame with the mac address as first match
835          * and broadcast for all others */
836         for (i = 0; i < 192; i++)
837                 txb[i] = 0xFF;
838
839         txb[0] = nic->node_addr[0];
840         txb[1] = nic->node_addr[1];
841         txb[2] = nic->node_addr[2];
842         txb[3] = nic->node_addr[3];
843         txb[4] = nic->node_addr[4];
844         txb[5] = nic->node_addr[5];
845 }
846
847 /**************************************************************************
848 DISABLE - Turn off ethernet interface
849 ***************************************************************************/
850 static void r8169_disable ( struct nic *nic __unused ) {
851         int i;
852         /* Stop the chip's Tx and Rx DMA processes. */
853         RTL_W8(ChipCmd, 0x00);
854
855         /* Disable interrupts by clearing the interrupt mask. */
856         RTL_W16(IntrMask, 0x0000);
857
858         RTL_W32(RxMissed, 0);
859
860         tpc->TxDescArray = NULL;
861         tpc->RxDescArray = NULL;
862         for (i = 0; i < NUM_RX_DESC; i++) {
863                 tpc->RxBufferRing[i] = NULL;
864         }
865 }
866
867 static struct nic_operations r8169_operations = {
868         .connect        = dummy_connect,
869         .poll           = r8169_poll,
870         .transmit       = r8169_transmit,
871         .irq            = r8169_irq,
872
873 };
874
875 static struct pci_device_id r8169_nics[] = {
876         PCI_ROM(0x10ec, 0x8169, "r8169", "RealTek RTL8169 Gigabit Ethernet"),
877         PCI_ROM(0x16ec, 0x0116, "usr-r8169", "US Robotics RTL8169 Gigabit Ethernet"),
878         PCI_ROM(0x1186, 0x4300, "dlink-r8169", "D-Link RTL8169 Gigabit Ethernet"),
879 };
880
881 PCI_DRIVER ( r8169_driver, r8169_nics, PCI_NO_CLASS );
882
883 /**************************************************************************
884 PROBE - Look for an adapter, this routine's visible to the outside
885 ***************************************************************************/
886
887 #define board_found 1
888 #define valid_link 0
889 static int r8169_probe ( struct nic *nic, struct pci_device *pci ) {
890
891         static int board_idx = -1;
892         static int printed_version = 0;
893         int i, rc;
894         int option = -1, Cap10_100 = 0, Cap1000 = 0;
895
896         printf ( "r8169.c: Found %s, Vendor=%hX Device=%hX\n",
897                pci->driver_name, pci->vendor, pci->device );
898
899         board_idx++;
900
901         printed_version = 1;
902
903         /* point to private storage */
904         tpc = &tpx;
905
906         rc = rtl8169_init_board(pci);   /* Return code is meaningless */
907
908         /* Get MAC address.  FIXME: read EEPROM */
909         for (i = 0; i < MAC_ADDR_LEN; i++)
910                 nic->node_addr[i] = RTL_R8(MAC0 + i);
911
912         DBG ( "%s: Identified chip type is '%s'.\n", pci->driver_name,
913                  rtl_chip_info[tpc->chipset].name );
914
915         /* Print out some hardware info */
916         DBG ( "%s: %s at IOAddr %#hX, ", pci->driver_name, eth_ntoa ( nic->node_addr ),
917               (unsigned int) ioaddr );
918
919         /* Config PHY */
920         rtl8169_hw_PHY_config(nic);
921
922         DBG_PRINTF("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
923         RTL_W8(0x82, 0x01);
924
925         if (tpc->mcfg < MCFG_METHOD_3) {
926                 DBG_PRINTF("Set PCI Latency=0x40\n");
927                 pci_write_config_byte(pci, PCI_LATENCY_TIMER, 0x40);
928         }
929
930         if (tpc->mcfg == MCFG_METHOD_2) {
931                 DBG_PRINTF("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
932                 RTL_W8(0x82, 0x01);
933                 DBG_PRINTF("Set PHY Reg 0x0bh = 0x00h\n");
934                 RTL8169_WRITE_GMII_REG(ioaddr, 0x0b, 0x0000);   //w 0x0b 15 0 0
935         }
936
937         /* if TBI is not endbled */
938         if (!(RTL_R8(PHYstatus) & TBI_Enable)) {
939                 int val = RTL8169_READ_GMII_REG(ioaddr, PHY_AUTO_NEGO_REG);
940
941 #ifdef RTL8169_HW_FLOW_CONTROL_SUPPORT
942                 val |= PHY_Cap_PAUSE | PHY_Cap_ASYM_PAUSE;
943 #endif                          //end #define RTL8169_HW_FLOW_CONTROL_SUPPORT
944
945                 option = media;
946                 /* Force RTL8169 in 10/100/1000 Full/Half mode. */
947                 if (option > 0) {
948                         printf(" Force-mode Enabled.\n");
949                         Cap10_100 = 0, Cap1000 = 0;
950                         switch (option) {
951                         case _10_Half:
952                                 Cap10_100 = PHY_Cap_10_Half;
953                                 Cap1000 = PHY_Cap_Null;
954                                 break;
955                         case _10_Full:
956                                 Cap10_100 = PHY_Cap_10_Full;
957                                 Cap1000 = PHY_Cap_Null;
958                                 break;
959                         case _100_Half:
960                                 Cap10_100 = PHY_Cap_100_Half;
961                                 Cap1000 = PHY_Cap_Null;
962                                 break;
963                         case _100_Full:
964                                 Cap10_100 = PHY_Cap_100_Full;
965                                 Cap1000 = PHY_Cap_Null;
966                                 break;
967                         case _1000_Full:
968                                 Cap10_100 = PHY_Cap_Null;
969                                 Cap1000 = PHY_Cap_1000_Full;
970                                 break;
971                         default:
972                                 break;
973                         }
974                         RTL8169_WRITE_GMII_REG(ioaddr, PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0xC1F));   //leave PHY_AUTO_NEGO_REG bit4:0 unchanged
975                         RTL8169_WRITE_GMII_REG(ioaddr, PHY_1000_CTRL_REG,
976                                                Cap1000);
977                 } else {
978                         DBG ( "%s: Auto-negotiation Enabled.\n",  pci->driver_name );
979
980                         // enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged
981                         RTL8169_WRITE_GMII_REG(ioaddr, PHY_AUTO_NEGO_REG,
982                                                PHY_Cap_10_Half |
983                                                PHY_Cap_10_Full |
984                                                PHY_Cap_100_Half |
985                                                PHY_Cap_100_Full | (val &
986                                                                    0xC1F));
987
988                         // enable 1000 Full Mode
989 //                     RTL8169_WRITE_GMII_REG( ioaddr, PHY_1000_CTRL_REG, PHY_Cap_1000_Full );
990                         RTL8169_WRITE_GMII_REG(ioaddr, PHY_1000_CTRL_REG, PHY_Cap_1000_Full | PHY_Cap_1000_Half);       //rtl8168
991
992                 }               // end of if( option > 0 )
993
994                 // Enable auto-negotiation and restart auto-nigotiation
995                 RTL8169_WRITE_GMII_REG(ioaddr, PHY_CTRL_REG,
996                                        PHY_Enable_Auto_Nego |
997                                        PHY_Restart_Auto_Nego);
998                 udelay(100);
999
1000                 // wait for auto-negotiation process
1001                 for (i = 10000; i > 0; i--) {
1002                         //check if auto-negotiation complete
1003                         if (RTL8169_READ_GMII_REG(ioaddr, PHY_STAT_REG) &
1004                             PHY_Auto_Neco_Comp) {
1005                                 udelay(100);
1006                                 option = RTL_R8(PHYstatus);
1007                                 if (option & _1000bpsF) {
1008                                         printf
1009                                             ("1000Mbps Full-duplex operation.\n");
1010                                 } else {
1011                                         printf
1012                                             ("%sMbps %s-duplex operation.\n",
1013                                              (option & _100bps) ? "100" :
1014                                              "10",
1015                                              (option & FullDup) ? "Full" :
1016                                              "Half");
1017                                 }
1018                                 break;
1019                         } else {
1020                                 udelay(100);
1021                         }       // end of if( RTL8169_READ_GMII_REG(ioaddr, 1) & 0x20 )
1022                 }               // end for-loop to wait for auto-negotiation process
1023
1024
1025         } else {
1026                 udelay(100);
1027                 printf
1028                     ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n",
1029                      pci->driver_name,
1030                      (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed");
1031
1032         }
1033
1034         r8169_reset(nic);
1035         /* point to NIC specific routines */
1036         nic->nic_op     = &r8169_operations;
1037         pci_fill_nic ( nic, pci );
1038         nic->irqno = pci->irq;
1039         nic->ioaddr = ioaddr;
1040         return 1;
1041
1042 }
1043
1044 //======================================================================================================
1045 /*
1046 static void rtl8169_hw_PHY_reset(struct nic *nic __unused)
1047 {
1048         int val, phy_reset_expiretime = 50;
1049         struct rtl8169_private *priv = dev->priv;
1050         unsigned long ioaddr = priv->ioaddr;
1051
1052         DBG_PRINTF("%s: Reset RTL8169s PHY\n", dev->name);
1053
1054         val = ( RTL8169_READ_GMII_REG( ioaddr, 0 ) | 0x8000 ) & 0xffff;
1055         RTL8169_WRITE_GMII_REG( ioaddr, 0, val );
1056
1057         do //waiting for phy reset
1058         {
1059                 if( RTL8169_READ_GMII_REG( ioaddr, 0 ) & 0x8000 ){
1060                         phy_reset_expiretime --;
1061                         udelay(100);
1062                 }
1063                 else{
1064                         break;
1065                 }
1066         }while( phy_reset_expiretime >= 0 );
1067
1068         assert( phy_reset_expiretime > 0 );
1069 }
1070
1071 */
1072
1073 //======================================================================================================
1074 static void rtl8169_hw_PHY_config(struct nic *nic __unused)
1075 {
1076
1077         DBG_PRINTF("priv->mcfg=%d, priv->pcfg=%d\n", tpc->mcfg, tpc->pcfg);
1078
1079         if (tpc->mcfg == MCFG_METHOD_4) {
1080 /*
1081                 RTL8169_WRITE_GMII_REG( (unsigned long)ioaddr, 0x1F, 0x0001 );
1082                 RTL8169_WRITE_GMII_REG( (unsigned long)ioaddr, 0x1b, 0x841e );
1083                 RTL8169_WRITE_GMII_REG( (unsigned long)ioaddr, 0x0e, 0x7bfb );
1084                 RTL8169_WRITE_GMII_REG( (unsigned long)ioaddr, 0x09, 0x273a );
1085 */
1086
1087                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x1F,
1088                                        0x0002);
1089                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x01,
1090                                        0x90D0);
1091                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x1F,
1092                                        0x0000);
1093         } else if ((tpc->mcfg == MCFG_METHOD_2)
1094                    || (tpc->mcfg == MCFG_METHOD_3)) {
1095                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x1F,
1096                                        0x0001);
1097                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x15,
1098                                        0x1000);
1099                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x18,
1100                                        0x65C7);
1101                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1102                                        0x0000);
1103                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x03,
1104                                        0x00A1);
1105                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x02,
1106                                        0x0008);
1107                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x01,
1108                                        0x1020);
1109                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x00,
1110                                        0x1000);
1111                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1112                                        0x0800);
1113                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1114                                        0x0000);
1115                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1116                                        0x7000);
1117                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x03,
1118                                        0xFF41);
1119                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x02,
1120                                        0xDE60);
1121                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x01,
1122                                        0x0140);
1123                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x00,
1124                                        0x0077);
1125                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1126                                        0x7800);
1127                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1128                                        0x7000);
1129                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1130                                        0xA000);
1131                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x03,
1132                                        0xDF01);
1133                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x02,
1134                                        0xDF20);
1135                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x01,
1136                                        0xFF95);
1137                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x00,
1138                                        0xFA00);
1139                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1140                                        0xA800);
1141                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1142                                        0xA000);
1143                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1144                                        0xB000);
1145                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x03,
1146                                        0xFF41);
1147                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x02,
1148                                        0xDE20);
1149                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x01,
1150                                        0x0140);
1151                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x00,
1152                                        0x00BB);
1153                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1154                                        0xB800);
1155                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1156                                        0xB000);
1157                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1158                                        0xF000);
1159                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x03,
1160                                        0xDF01);
1161                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x02,
1162                                        0xDF20);
1163                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x01,
1164                                        0xFF95);
1165                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x00,
1166                                        0xBF00);
1167                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1168                                        0xF800);
1169                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1170                                        0xF000);
1171                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1172                                        0x0000);
1173                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x1F,
1174                                        0x0000);
1175                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x0B,
1176                                        0x0000);
1177         } else {
1178                 DBG_PRINTF("tpc->mcfg=%d. Discard hw PHY config.\n",
1179                           tpc->mcfg);
1180         }
1181 }
1182
1183 DRIVER ( "r8169/PCI", nic_driver, pci_driver, r8169_driver,
1184          r8169_probe, r8169_disable );