Include errno.h in the few drivers which use it, rather than in nic.h
[people/holger/gpxe.git] / src / drivers / net / bnx2.c
1 /* bnx2.c: Broadcom NX2 network driver.
2  *
3  * Copyright (c) 2004, 2005, 2006 Broadcom Corporation
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation.
8  *
9  * Written by: Michael Chan  (mchan@broadcom.com)
10  *
11  * Etherboot port by Ryan Jackson (rjackson@lnxi.com), based on driver
12  * version 1.4.40 from linux 2.6.17
13  */
14
15
16 #include "etherboot.h"
17 #include "nic.h"
18 #include <errno.h>
19 #include <gpxe/pci.h>
20 #include <gpxe/ethernet.h>
21 #include "timer.h"
22 #include "string.h"
23 #include "bnx2.h"
24 #include "bnx2_fw.h"
25
26 #if 0
27 /* Dummy defines for error handling */
28 #define EBUSY  1
29 #define ENODEV 2
30 #define EINVAL 3
31 #define ENOMEM 4
32 #define EIO    5
33 #endif
34
35 /* The bnx2 seems to be picky about the alignment of the receive buffers
36  * and possibly the status block.
37  */
38 static struct bss {
39         struct tx_bd tx_desc_ring[TX_DESC_CNT];
40         struct rx_bd rx_desc_ring[RX_DESC_CNT];
41         unsigned char rx_buf[RX_BUF_CNT][RX_BUF_SIZE];
42         struct status_block status_blk;
43         struct statistics_block stats_blk;
44 } bnx2_bss;
45
46 struct bnx2 bnx2;
47
48 static struct flash_spec flash_table[] =
49 {
50         /* Slow EEPROM */
51         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
52          1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
53          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
54          "EEPROM - slow"},
55         /* Expansion entry 0001 */
56         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
57          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
58          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
59          "Entry 0001"},
60         /* Saifun SA25F010 (non-buffered flash) */
61         /* strap, cfg1, & write1 need updates */
62         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
63          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
64          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
65          "Non-buffered flash (128kB)"},
66         /* Saifun SA25F020 (non-buffered flash) */
67         /* strap, cfg1, & write1 need updates */
68         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
69          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
70          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
71          "Non-buffered flash (256kB)"},
72         /* Expansion entry 0100 */
73         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
74          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
75          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
76          "Entry 0100"},
77         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
78         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,        
79          0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
80          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
81          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
82         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
83         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
84          0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
85          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
86          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
87         /* Saifun SA25F005 (non-buffered flash) */
88         /* strap, cfg1, & write1 need updates */
89         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
90          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
91          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
92          "Non-buffered flash (64kB)"},
93         /* Fast EEPROM */
94         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
95          1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
96          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
97          "EEPROM - fast"},
98         /* Expansion entry 1001 */
99         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
100          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
101          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
102          "Entry 1001"},
103         /* Expansion entry 1010 */
104         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
105          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
106          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
107          "Entry 1010"},
108         /* ATMEL AT45DB011B (buffered flash) */
109         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
110          1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
111          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
112          "Buffered flash (128kB)"},
113         /* Expansion entry 1100 */
114         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
115          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
116          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
117          "Entry 1100"},
118         /* Expansion entry 1101 */
119         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
120          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
121          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
122          "Entry 1101"},
123         /* Ateml Expansion entry 1110 */
124         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
125          1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
126          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
127          "Entry 1110 (Atmel)"},
128         /* ATMEL AT45DB021B (buffered flash) */
129         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
130          1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
131          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
132          "Buffered flash (256kB)"},
133 };
134
135 static u32
136 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
137 {
138         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
139         return (REG_RD(bp, BNX2_PCICFG_REG_WINDOW));
140 }
141
142 static void
143 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
144 {
145         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
146         REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
147 }
148
149 static void
150 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
151 {
152         offset += cid_addr;
153         REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
154         REG_WR(bp, BNX2_CTX_DATA, val);
155 }
156
157 static int
158 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
159 {
160         u32 val1;
161         int i, ret;
162
163         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
164                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
165                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
166
167                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
168                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
169
170                 udelay(40);
171         }
172
173         val1 = (bp->phy_addr << 21) | (reg << 16) |
174                 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
175                 BNX2_EMAC_MDIO_COMM_START_BUSY;
176         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
177
178         for (i = 0; i < 50; i++) {
179                 udelay(10);
180
181                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
182                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
183                         udelay(5);
184
185                         val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
186                         val1 &= BNX2_EMAC_MDIO_COMM_DATA;
187
188                         break;
189                 }
190         }
191
192         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
193                 *val = 0x0;
194                 ret = -EBUSY;
195         }
196         else {
197                 *val = val1;
198                 ret = 0;
199         }
200
201         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
202                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
203                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
204
205                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
206                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
207
208                 udelay(40);
209         }
210
211         return ret;
212 }
213
214 static int
215 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
216 {
217         u32 val1;
218         int i, ret;
219
220         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
221                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
222                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
223
224                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
225                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
226
227                 udelay(40);
228         }
229
230         val1 = (bp->phy_addr << 21) | (reg << 16) | val |
231                 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
232                 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
233         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
234     
235         for (i = 0; i < 50; i++) {
236                 udelay(10);
237
238                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
239                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
240                         udelay(5);
241                         break;
242                 }
243         }
244
245         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
246                 ret = -EBUSY;
247         else
248                 ret = 0;
249
250         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
251                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
252                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
253
254                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
255                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
256
257                 udelay(40);
258         }
259
260         return ret;
261 }
262
263 static void
264 bnx2_disable_int(struct bnx2 *bp)
265 {
266         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
267                BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
268         REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
269
270 }
271
272 static int
273 bnx2_alloc_mem(struct bnx2 *bp)
274 {
275         bp->tx_desc_ring = bnx2_bss.tx_desc_ring;
276         bp->tx_desc_mapping = virt_to_bus(bp->tx_desc_ring);
277
278         bp->rx_desc_ring = bnx2_bss.rx_desc_ring;
279         memset(bp->rx_desc_ring, 0, sizeof(struct rx_bd) * RX_DESC_CNT);
280         bp->rx_desc_mapping = virt_to_bus(bp->rx_desc_ring);
281
282         memset(&bnx2_bss.status_blk, 0, sizeof(struct status_block));
283         bp->status_blk = &bnx2_bss.status_blk;
284         bp->status_blk_mapping = virt_to_bus(&bnx2_bss.status_blk);
285
286         bp->stats_blk = &bnx2_bss.stats_blk;
287         memset(&bnx2_bss.stats_blk, 0, sizeof(struct statistics_block));
288         bp->stats_blk_mapping = virt_to_bus(&bnx2_bss.stats_blk);
289
290         return 0;
291 }
292
293 static void
294 bnx2_report_fw_link(struct bnx2 *bp)
295 {
296         u32 fw_link_status = 0;
297
298         if (bp->link_up) {
299                 u32 bmsr;
300
301                 switch (bp->line_speed) {
302                 case SPEED_10:
303                         if (bp->duplex == DUPLEX_HALF)
304                                 fw_link_status = BNX2_LINK_STATUS_10HALF;
305                         else
306                                 fw_link_status = BNX2_LINK_STATUS_10FULL;
307                         break;
308                 case SPEED_100:
309                         if (bp->duplex == DUPLEX_HALF)
310                                 fw_link_status = BNX2_LINK_STATUS_100HALF;
311                         else
312                                 fw_link_status = BNX2_LINK_STATUS_100FULL;
313                         break;
314                 case SPEED_1000:
315                         if (bp->duplex == DUPLEX_HALF)
316                                 fw_link_status = BNX2_LINK_STATUS_1000HALF;
317                         else
318                                 fw_link_status = BNX2_LINK_STATUS_1000FULL;
319                         break;
320                 case SPEED_2500:
321                         if (bp->duplex == DUPLEX_HALF)
322                                 fw_link_status = BNX2_LINK_STATUS_2500HALF;
323                         else
324                                 fw_link_status = BNX2_LINK_STATUS_2500FULL;
325                         break;
326                 }
327
328                 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
329
330                 if (bp->autoneg) {
331                         fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
332
333                         bnx2_read_phy(bp, MII_BMSR, &bmsr);
334                         bnx2_read_phy(bp, MII_BMSR, &bmsr);
335
336                         if (!(bmsr & BMSR_ANEGCOMPLETE) ||
337                             bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)
338                                 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
339                         else
340                                 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
341                 }
342         }
343         else
344                 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
345
346         REG_WR_IND(bp, bp->shmem_base + BNX2_LINK_STATUS, fw_link_status);
347 }
348
349 static void
350 bnx2_report_link(struct bnx2 *bp)
351 {
352         if (bp->link_up) {
353                 printf("NIC Link is Up, ");
354
355                 printf("%d Mbps ", bp->line_speed);
356
357                 if (bp->duplex == DUPLEX_FULL)
358                         printf("full duplex");
359                 else
360                         printf("half duplex");
361
362                 if (bp->flow_ctrl) {
363                         if (bp->flow_ctrl & FLOW_CTRL_RX) {
364                                 printf(", receive ");
365                                 if (bp->flow_ctrl & FLOW_CTRL_TX)
366                                         printf("& transmit ");
367                         }
368                         else {
369                                 printf(", transmit ");
370                         }
371                         printf("flow control ON");
372                 }
373                 printf("\n");
374         }
375         else {
376                 printf("NIC Link is Down\n");
377         }
378
379         bnx2_report_fw_link(bp);
380 }
381
382 static void
383 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
384 {
385         u32 local_adv, remote_adv;
386
387         bp->flow_ctrl = 0;
388         if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) != 
389                 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
390
391                 if (bp->duplex == DUPLEX_FULL) {
392                         bp->flow_ctrl = bp->req_flow_ctrl;
393                 }
394                 return;
395         }
396
397         if (bp->duplex != DUPLEX_FULL) {
398                 return;
399         }
400
401         if ((bp->phy_flags & PHY_SERDES_FLAG) &&
402             (CHIP_NUM(bp) == CHIP_NUM_5708)) {
403                 u32 val;
404
405                 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
406                 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
407                         bp->flow_ctrl |= FLOW_CTRL_TX;
408                 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
409                         bp->flow_ctrl |= FLOW_CTRL_RX;
410                 return;
411         }
412
413         bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
414         bnx2_read_phy(bp, MII_LPA, &remote_adv);
415
416         if (bp->phy_flags & PHY_SERDES_FLAG) {
417                 u32 new_local_adv = 0;
418                 u32 new_remote_adv = 0;
419
420                 if (local_adv & ADVERTISE_1000XPAUSE)
421                         new_local_adv |= ADVERTISE_PAUSE_CAP;
422                 if (local_adv & ADVERTISE_1000XPSE_ASYM)
423                         new_local_adv |= ADVERTISE_PAUSE_ASYM;
424                 if (remote_adv & ADVERTISE_1000XPAUSE)
425                         new_remote_adv |= ADVERTISE_PAUSE_CAP;
426                 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
427                         new_remote_adv |= ADVERTISE_PAUSE_ASYM;
428
429                 local_adv = new_local_adv;
430                 remote_adv = new_remote_adv;
431         }
432
433         /* See Table 28B-3 of 802.3ab-1999 spec. */
434         if (local_adv & ADVERTISE_PAUSE_CAP) {
435                 if(local_adv & ADVERTISE_PAUSE_ASYM) {
436                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
437                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
438                         }
439                         else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
440                                 bp->flow_ctrl = FLOW_CTRL_RX;
441                         }
442                 }
443                 else {
444                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
445                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
446                         }
447                 }
448         }
449         else if (local_adv & ADVERTISE_PAUSE_ASYM) {
450                 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
451                         (remote_adv & ADVERTISE_PAUSE_ASYM)) {
452
453                         bp->flow_ctrl = FLOW_CTRL_TX;
454                 }
455         }
456 }
457
458 static int
459 bnx2_5708s_linkup(struct bnx2 *bp)
460 {
461         u32 val;
462
463         bp->link_up = 1;
464         bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
465         switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
466                 case BCM5708S_1000X_STAT1_SPEED_10:
467                         bp->line_speed = SPEED_10;
468                         break;
469                 case BCM5708S_1000X_STAT1_SPEED_100:
470                         bp->line_speed = SPEED_100;
471                         break;
472                 case BCM5708S_1000X_STAT1_SPEED_1G:
473                         bp->line_speed = SPEED_1000;
474                         break;
475                 case BCM5708S_1000X_STAT1_SPEED_2G5:
476                         bp->line_speed = SPEED_2500;
477                         break;
478         }
479         if (val & BCM5708S_1000X_STAT1_FD)
480                 bp->duplex = DUPLEX_FULL;
481         else
482                 bp->duplex = DUPLEX_HALF;
483
484         return 0;
485 }
486
487 static int
488 bnx2_5706s_linkup(struct bnx2 *bp)
489 {
490         u32 bmcr, local_adv, remote_adv, common;
491
492         bp->link_up = 1;
493         bp->line_speed = SPEED_1000;
494
495         bnx2_read_phy(bp, MII_BMCR, &bmcr);
496         if (bmcr & BMCR_FULLDPLX) {
497                 bp->duplex = DUPLEX_FULL;
498         }
499         else {
500                 bp->duplex = DUPLEX_HALF;
501         }
502
503         if (!(bmcr & BMCR_ANENABLE)) {
504                 return 0;
505         }
506
507         bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
508         bnx2_read_phy(bp, MII_LPA, &remote_adv);
509
510         common = local_adv & remote_adv;
511         if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
512
513                 if (common & ADVERTISE_1000XFULL) {
514                         bp->duplex = DUPLEX_FULL;
515                 }
516                 else {
517                         bp->duplex = DUPLEX_HALF;
518                 }
519         }
520
521         return 0;
522 }
523
524 static int
525 bnx2_copper_linkup(struct bnx2 *bp)
526 {
527         u32 bmcr;
528
529         bnx2_read_phy(bp, MII_BMCR, &bmcr);
530         if (bmcr & BMCR_ANENABLE) {
531                 u32 local_adv, remote_adv, common;
532
533                 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
534                 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
535
536                 common = local_adv & (remote_adv >> 2);
537                 if (common & ADVERTISE_1000FULL) {
538                         bp->line_speed = SPEED_1000;
539                         bp->duplex = DUPLEX_FULL;
540                 }
541                 else if (common & ADVERTISE_1000HALF) {
542                         bp->line_speed = SPEED_1000;
543                         bp->duplex = DUPLEX_HALF;
544                 }
545                 else {
546                         bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
547                         bnx2_read_phy(bp, MII_LPA, &remote_adv);
548
549                         common = local_adv & remote_adv;
550                         if (common & ADVERTISE_100FULL) {
551                                 bp->line_speed = SPEED_100;
552                                 bp->duplex = DUPLEX_FULL;
553                         }
554                         else if (common & ADVERTISE_100HALF) {
555                                 bp->line_speed = SPEED_100;
556                                 bp->duplex = DUPLEX_HALF;
557                         }
558                         else if (common & ADVERTISE_10FULL) {
559                                 bp->line_speed = SPEED_10;
560                                 bp->duplex = DUPLEX_FULL;
561                         }
562                         else if (common & ADVERTISE_10HALF) {
563                                 bp->line_speed = SPEED_10;
564                                 bp->duplex = DUPLEX_HALF;
565                         }
566                         else {
567                                 bp->line_speed = 0;
568                                 bp->link_up = 0;
569                         }
570                 }
571         }
572         else {
573                 if (bmcr & BMCR_SPEED100) {
574                         bp->line_speed = SPEED_100;
575                 }
576                 else {
577                         bp->line_speed = SPEED_10;
578                 }
579                 if (bmcr & BMCR_FULLDPLX) {
580                         bp->duplex = DUPLEX_FULL;
581                 }
582                 else {
583                         bp->duplex = DUPLEX_HALF;
584                 }
585         }
586
587         return 0;
588 }
589
590 static int
591 bnx2_set_mac_link(struct bnx2 *bp)
592 {
593         u32 val;
594
595         REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
596         if (bp->link_up && (bp->line_speed == SPEED_1000) &&
597                 (bp->duplex == DUPLEX_HALF)) {
598                 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
599         }
600
601         /* Configure the EMAC mode register. */
602         val = REG_RD(bp, BNX2_EMAC_MODE);
603
604         val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
605                 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
606                 BNX2_EMAC_MODE_25G);
607
608         if (bp->link_up) {
609                 switch (bp->line_speed) {
610                         case SPEED_10:
611                                 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
612                                         val |= BNX2_EMAC_MODE_PORT_MII_10;
613                                         break;
614                                 }
615                                 /* fall through */
616                         case SPEED_100:
617                                 val |= BNX2_EMAC_MODE_PORT_MII;
618                                 break;
619                         case SPEED_2500:
620                                 val |= BNX2_EMAC_MODE_25G;
621                                 /* fall through */
622                         case SPEED_1000:
623                                 val |= BNX2_EMAC_MODE_PORT_GMII;
624                                 break;
625                 }
626         }
627         else {
628                 val |= BNX2_EMAC_MODE_PORT_GMII;
629         }
630
631         /* Set the MAC to operate in the appropriate duplex mode. */
632         if (bp->duplex == DUPLEX_HALF)
633                 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
634         REG_WR(bp, BNX2_EMAC_MODE, val);
635
636         /* Enable/disable rx PAUSE. */
637         bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
638
639         if (bp->flow_ctrl & FLOW_CTRL_RX)
640                 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
641         REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
642
643         /* Enable/disable tx PAUSE. */
644         val = REG_RD(bp, BNX2_EMAC_TX_MODE);
645         val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
646
647         if (bp->flow_ctrl & FLOW_CTRL_TX)
648                 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
649         REG_WR(bp, BNX2_EMAC_TX_MODE, val);
650
651         /* Acknowledge the interrupt. */
652         REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
653
654         return 0;
655 }
656
657 static int
658 bnx2_set_link(struct bnx2 *bp)
659 {
660         u32 bmsr;
661         u8 link_up;
662
663         if (bp->loopback == MAC_LOOPBACK) {
664                 bp->link_up = 1;
665                 return 0;
666         }
667
668         link_up = bp->link_up;
669
670         bnx2_read_phy(bp, MII_BMSR, &bmsr);
671         bnx2_read_phy(bp, MII_BMSR, &bmsr);
672
673         if ((bp->phy_flags & PHY_SERDES_FLAG) &&
674             (CHIP_NUM(bp) == CHIP_NUM_5706)) {
675                 u32 val;
676
677                 val = REG_RD(bp, BNX2_EMAC_STATUS);
678                 if (val & BNX2_EMAC_STATUS_LINK)
679                         bmsr |= BMSR_LSTATUS;
680                 else
681                         bmsr &= ~BMSR_LSTATUS;
682         }
683
684         if (bmsr & BMSR_LSTATUS) {
685                 bp->link_up = 1;
686
687                 if (bp->phy_flags & PHY_SERDES_FLAG) {
688                         if (CHIP_NUM(bp) == CHIP_NUM_5706)
689                                 bnx2_5706s_linkup(bp);
690                         else if (CHIP_NUM(bp) == CHIP_NUM_5708)
691                                 bnx2_5708s_linkup(bp);
692                 }
693                 else {
694                         bnx2_copper_linkup(bp);
695                 }
696                 bnx2_resolve_flow_ctrl(bp);
697         }
698         else {
699                 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
700                         (bp->autoneg & AUTONEG_SPEED)) {
701
702                         u32 bmcr;
703
704                         bnx2_read_phy(bp, MII_BMCR, &bmcr);
705                         if (!(bmcr & BMCR_ANENABLE)) {
706                                 bnx2_write_phy(bp, MII_BMCR, bmcr |
707                                         BMCR_ANENABLE);
708                         }
709                 }
710                 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
711                 bp->link_up = 0;
712         }
713
714         if (bp->link_up != link_up) {
715                 bnx2_report_link(bp);
716         }
717
718         bnx2_set_mac_link(bp);
719
720         return 0;
721 }
722
723 static int
724 bnx2_reset_phy(struct bnx2 *bp)
725 {
726         int i;
727         u32 reg;
728
729         bnx2_write_phy(bp, MII_BMCR, BMCR_RESET);
730
731 #define PHY_RESET_MAX_WAIT 100
732         for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
733                 udelay(10);
734
735                 bnx2_read_phy(bp, MII_BMCR, &reg);
736                 if (!(reg & BMCR_RESET)) {
737                         udelay(20);
738                         break;
739                 }
740         }
741         if (i == PHY_RESET_MAX_WAIT) {
742                 return -EBUSY;
743         }
744         return 0;
745 }
746
747 static u32
748 bnx2_phy_get_pause_adv(struct bnx2 *bp)
749 {
750         u32 adv = 0;
751
752         if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
753                 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
754
755                 if (bp->phy_flags & PHY_SERDES_FLAG) {
756                         adv = ADVERTISE_1000XPAUSE;
757                 }
758                 else {
759                         adv = ADVERTISE_PAUSE_CAP;
760                 }
761         }
762         else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
763                 if (bp->phy_flags & PHY_SERDES_FLAG) {
764                         adv = ADVERTISE_1000XPSE_ASYM;
765                 }
766                 else {
767                         adv = ADVERTISE_PAUSE_ASYM;
768                 }
769         }
770         else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
771                 if (bp->phy_flags & PHY_SERDES_FLAG) {
772                         adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
773                 }
774                 else {
775                         adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
776                 }
777         }
778         return adv;
779 }
780
781 static int
782 bnx2_setup_serdes_phy(struct bnx2 *bp)
783 {
784         u32 adv, bmcr, up1;
785         u32 new_adv = 0;
786
787         if (!(bp->autoneg & AUTONEG_SPEED)) {
788                 u32 new_bmcr;
789                 int force_link_down = 0;
790
791                 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
792                         bnx2_read_phy(bp, BCM5708S_UP1, &up1);
793                         if (up1 & BCM5708S_UP1_2G5) {
794                                 up1 &= ~BCM5708S_UP1_2G5;
795                                 bnx2_write_phy(bp, BCM5708S_UP1, up1);
796                                 force_link_down = 1;
797                         }
798                 }
799
800                 bnx2_read_phy(bp, MII_ADVERTISE, &adv);
801                 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
802
803                 bnx2_read_phy(bp, MII_BMCR, &bmcr);
804                 new_bmcr = bmcr & ~BMCR_ANENABLE;
805                 new_bmcr |= BMCR_SPEED1000;
806                 if (bp->req_duplex == DUPLEX_FULL) {
807                         adv |= ADVERTISE_1000XFULL;
808                         new_bmcr |= BMCR_FULLDPLX;
809                 }
810                 else {
811                         adv |= ADVERTISE_1000XHALF;
812                         new_bmcr &= ~BMCR_FULLDPLX;
813                 }
814                 if ((new_bmcr != bmcr) || (force_link_down)) {
815                         /* Force a link down visible on the other side */
816                         if (bp->link_up) {
817                                 bnx2_write_phy(bp, MII_ADVERTISE, adv &
818                                                ~(ADVERTISE_1000XFULL |
819                                                  ADVERTISE_1000XHALF));
820                                 bnx2_write_phy(bp, MII_BMCR, bmcr |
821                                         BMCR_ANRESTART | BMCR_ANENABLE);
822
823                                 bp->link_up = 0;
824                                 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
825                         }
826                         bnx2_write_phy(bp, MII_ADVERTISE, adv);
827                         bnx2_write_phy(bp, MII_BMCR, new_bmcr);
828                 }
829                 return 0;
830         }
831
832         if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
833                 bnx2_read_phy(bp, BCM5708S_UP1, &up1);
834                 up1 |= BCM5708S_UP1_2G5;
835                 bnx2_write_phy(bp, BCM5708S_UP1, up1);
836         }
837
838         if (bp->advertising & ADVERTISED_1000baseT_Full)
839                 new_adv |= ADVERTISE_1000XFULL;
840
841         new_adv |= bnx2_phy_get_pause_adv(bp);
842
843         bnx2_read_phy(bp, MII_ADVERTISE, &adv);
844         bnx2_read_phy(bp, MII_BMCR, &bmcr);
845
846         bp->serdes_an_pending = 0;
847         if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
848                 /* Force a link down visible on the other side */
849                 if (bp->link_up) {
850                         int i;
851
852                         bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
853                         for (i = 0; i < 110; i++) {
854                                 udelay(100);
855                         }
856                 }
857
858                 bnx2_write_phy(bp, MII_ADVERTISE, new_adv);
859                 bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART |
860                         BMCR_ANENABLE);
861 #if 0
862                 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
863                         /* Speed up link-up time when the link partner
864                          * does not autonegotiate which is very common
865                          * in blade servers. Some blade servers use
866                          * IPMI for kerboard input and it's important
867                          * to minimize link disruptions. Autoneg. involves
868                          * exchanging base pages plus 3 next pages and
869                          * normally completes in about 120 msec.
870                          */
871                         bp->current_interval = SERDES_AN_TIMEOUT;
872                         bp->serdes_an_pending = 1;
873                         mod_timer(&bp->timer, jiffies + bp->current_interval);
874                 }
875 #endif
876         }
877
878         return 0;
879 }
880
881 #define ETHTOOL_ALL_FIBRE_SPEED                                         \
882         (ADVERTISED_1000baseT_Full)
883
884 #define ETHTOOL_ALL_COPPER_SPEED                                        \
885         (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |            \
886         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |           \
887         ADVERTISED_1000baseT_Full)
888
889 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
890         ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
891         
892 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
893
894 static int
895 bnx2_setup_copper_phy(struct bnx2 *bp)
896 {
897         u32 bmcr;
898         u32 new_bmcr;
899
900         bnx2_read_phy(bp, MII_BMCR, &bmcr);
901
902         if (bp->autoneg & AUTONEG_SPEED) {
903                 u32 adv_reg, adv1000_reg;
904                 u32 new_adv_reg = 0;
905                 u32 new_adv1000_reg = 0;
906
907                 bnx2_read_phy(bp, MII_ADVERTISE, &adv_reg);
908                 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
909                         ADVERTISE_PAUSE_ASYM);
910
911                 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
912                 adv1000_reg &= PHY_ALL_1000_SPEED;
913
914                 if (bp->advertising & ADVERTISED_10baseT_Half)
915                         new_adv_reg |= ADVERTISE_10HALF;
916                 if (bp->advertising & ADVERTISED_10baseT_Full)
917                         new_adv_reg |= ADVERTISE_10FULL;
918                 if (bp->advertising & ADVERTISED_100baseT_Half)
919                         new_adv_reg |= ADVERTISE_100HALF;
920                 if (bp->advertising & ADVERTISED_100baseT_Full)
921                         new_adv_reg |= ADVERTISE_100FULL;
922                 if (bp->advertising & ADVERTISED_1000baseT_Full)
923                         new_adv1000_reg |= ADVERTISE_1000FULL;
924                 
925                 new_adv_reg |= ADVERTISE_CSMA;
926
927                 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
928
929                 if ((adv1000_reg != new_adv1000_reg) ||
930                         (adv_reg != new_adv_reg) ||
931                         ((bmcr & BMCR_ANENABLE) == 0)) {
932
933                         bnx2_write_phy(bp, MII_ADVERTISE, new_adv_reg);
934                         bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
935                         bnx2_write_phy(bp, MII_BMCR, BMCR_ANRESTART |
936                                 BMCR_ANENABLE);
937                 }
938                 else if (bp->link_up) {
939                         /* Flow ctrl may have changed from auto to forced */
940                         /* or vice-versa. */
941
942                         bnx2_resolve_flow_ctrl(bp);
943                         bnx2_set_mac_link(bp);
944                 }
945                 return 0;
946         }
947
948         new_bmcr = 0;
949         if (bp->req_line_speed == SPEED_100) {
950                 new_bmcr |= BMCR_SPEED100;
951         }
952         if (bp->req_duplex == DUPLEX_FULL) {
953                 new_bmcr |= BMCR_FULLDPLX;
954         }
955         if (new_bmcr != bmcr) {
956                 u32 bmsr;
957                 int i = 0;
958
959                 bnx2_read_phy(bp, MII_BMSR, &bmsr);
960                 bnx2_read_phy(bp, MII_BMSR, &bmsr);
961                 
962                 if (bmsr & BMSR_LSTATUS) {
963                         /* Force link down */
964                         bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
965                         do {
966                                 udelay(100);
967                                 bnx2_read_phy(bp, MII_BMSR, &bmsr);
968                                 bnx2_read_phy(bp, MII_BMSR, &bmsr);
969                                 i++;
970                         } while ((bmsr & BMSR_LSTATUS) && (i < 620));
971                 }
972
973                 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
974
975                 /* Normally, the new speed is setup after the link has
976                  * gone down and up again. In some cases, link will not go
977                  * down so we need to set up the new speed here.
978                  */
979                 if (bmsr & BMSR_LSTATUS) {
980                         bp->line_speed = bp->req_line_speed;
981                         bp->duplex = bp->req_duplex;
982                         bnx2_resolve_flow_ctrl(bp);
983                         bnx2_set_mac_link(bp);
984                 }
985         }
986         return 0;
987 }
988
989 static int
990 bnx2_setup_phy(struct bnx2 *bp)
991 {
992         if (bp->loopback == MAC_LOOPBACK)
993                 return 0;
994
995         if (bp->phy_flags & PHY_SERDES_FLAG) {
996                 return (bnx2_setup_serdes_phy(bp));
997         }
998         else {
999                 return (bnx2_setup_copper_phy(bp));
1000         }
1001 }
1002
1003 static int
1004 bnx2_init_5708s_phy(struct bnx2 *bp)
1005 {
1006         u32 val;
1007
1008         bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
1009         bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
1010         bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1011
1012         bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
1013         val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
1014         bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
1015
1016         bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
1017         val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
1018         bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
1019
1020         if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
1021                 bnx2_read_phy(bp, BCM5708S_UP1, &val);
1022                 val |= BCM5708S_UP1_2G5;
1023                 bnx2_write_phy(bp, BCM5708S_UP1, val);
1024         }
1025
1026         if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
1027             (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
1028             (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
1029                 /* increase tx signal amplitude */
1030                 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1031                                BCM5708S_BLK_ADDR_TX_MISC);
1032                 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
1033                 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
1034                 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
1035                 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1036         }
1037
1038         val = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG) &
1039               BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
1040
1041         if (val) {
1042                 u32 is_backplane;
1043
1044                 is_backplane = REG_RD_IND(bp, bp->shmem_base +
1045                                           BNX2_SHARED_HW_CFG_CONFIG);
1046                 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
1047                         bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1048                                        BCM5708S_BLK_ADDR_TX_MISC);
1049                         bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
1050                         bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1051                                        BCM5708S_BLK_ADDR_DIG);
1052                 }
1053         }
1054         return 0;
1055 }
1056
1057 static int
1058 bnx2_init_5706s_phy(struct bnx2 *bp)
1059 {
1060         u32 val;
1061
1062         bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
1063
1064         if (CHIP_NUM(bp) == CHIP_NUM_5706) {
1065                 REG_WR(bp, BNX2_MISC_UNUSED0, 0x300);
1066         }
1067
1068
1069         bnx2_write_phy(bp, 0x18, 0x7);
1070         bnx2_read_phy(bp, 0x18, &val);
1071         bnx2_write_phy(bp, 0x18, val & ~0x4007);
1072
1073         bnx2_write_phy(bp, 0x1c, 0x6c00);
1074         bnx2_read_phy(bp, 0x1c, &val);
1075         bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
1076
1077         return 0;
1078 }
1079
1080 static int
1081 bnx2_init_copper_phy(struct bnx2 *bp)
1082 {
1083         u32 val;
1084
1085         bp->phy_flags |= PHY_CRC_FIX_FLAG;
1086
1087         if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
1088                 bnx2_write_phy(bp, 0x18, 0x0c00);
1089                 bnx2_write_phy(bp, 0x17, 0x000a);
1090                 bnx2_write_phy(bp, 0x15, 0x310b);
1091                 bnx2_write_phy(bp, 0x17, 0x201f);
1092                 bnx2_write_phy(bp, 0x15, 0x9506);
1093                 bnx2_write_phy(bp, 0x17, 0x401f);
1094                 bnx2_write_phy(bp, 0x15, 0x14e2);
1095                 bnx2_write_phy(bp, 0x18, 0x0400);
1096         }
1097
1098         bnx2_write_phy(bp, 0x18, 0x7);
1099         bnx2_read_phy(bp, 0x18, &val);
1100         bnx2_write_phy(bp, 0x18, val & ~0x4007);
1101
1102         bnx2_read_phy(bp, 0x10, &val);
1103         bnx2_write_phy(bp, 0x10, val & ~0x1);
1104
1105         /* ethernet@wirespeed */
1106         bnx2_write_phy(bp, 0x18, 0x7007);
1107         bnx2_read_phy(bp, 0x18, &val);
1108         bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
1109         return 0;
1110 }
1111
1112 static int
1113 bnx2_init_phy(struct bnx2 *bp)
1114 {
1115         u32 val;
1116         int rc = 0;
1117
1118         bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG;
1119         bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG;
1120
1121         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
1122
1123         bnx2_reset_phy(bp);
1124
1125         bnx2_read_phy(bp, MII_PHYSID1, &val);
1126         bp->phy_id = val << 16;
1127         bnx2_read_phy(bp, MII_PHYSID2, &val);
1128         bp->phy_id |= val & 0xffff;
1129
1130         if (bp->phy_flags & PHY_SERDES_FLAG) {
1131                 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1132                         rc = bnx2_init_5706s_phy(bp);
1133                 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1134                         rc = bnx2_init_5708s_phy(bp);
1135         }
1136         else {
1137                 rc = bnx2_init_copper_phy(bp);
1138         }
1139
1140         bnx2_setup_phy(bp);
1141
1142         return rc;
1143 }
1144
1145 static int
1146 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
1147 {
1148         int i;
1149         u32 val;
1150
1151         bp->fw_wr_seq++;
1152         msg_data |= bp->fw_wr_seq;
1153
1154         REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
1155
1156         /* wait for an acknowledgement. */
1157         for (i = 0; i < (FW_ACK_TIME_OUT_MS / 50); i++) {
1158                 mdelay(50);
1159
1160                 val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_MB);
1161
1162                 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
1163                         break;
1164         }
1165         if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
1166                 return 0;
1167
1168         /* If we timed out, inform the firmware that this is the case. */
1169         if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
1170                 if (!silent)
1171                   printf("fw sync timeout, reset code = %x\n", (unsigned int) msg_data);
1172
1173                 msg_data &= ~BNX2_DRV_MSG_CODE;
1174                 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
1175
1176                 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
1177
1178                 return -EBUSY;
1179         }
1180
1181         if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
1182                 return -EIO;
1183
1184         return 0;
1185 }
1186
1187 static void
1188 bnx2_init_context(struct bnx2 *bp)
1189 {
1190         u32 vcid;
1191
1192         vcid = 96;
1193         while (vcid) {
1194                 u32 vcid_addr, pcid_addr, offset;
1195
1196                 vcid--;
1197
1198                 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
1199                         u32 new_vcid;
1200
1201                         vcid_addr = GET_PCID_ADDR(vcid);
1202                         if (vcid & 0x8) {
1203                                 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
1204                         }
1205                         else {
1206                                 new_vcid = vcid;
1207                         }
1208                         pcid_addr = GET_PCID_ADDR(new_vcid);
1209                 }
1210                 else {
1211                         vcid_addr = GET_CID_ADDR(vcid);
1212                         pcid_addr = vcid_addr;
1213                 }
1214
1215                 REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00);
1216                 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1217
1218                 /* Zero out the context. */
1219                 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) {
1220                         CTX_WR(bp, 0x00, offset, 0);
1221                 }
1222
1223                 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
1224                 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1225         }
1226 }
1227
1228 static int
1229 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
1230 {
1231         u16 good_mbuf[512];
1232         u32 good_mbuf_cnt;
1233         u32 val;
1234
1235         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
1236                 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
1237
1238         good_mbuf_cnt = 0;
1239
1240         /* Allocate a bunch of mbufs and save the good ones in an array. */
1241         val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1242         while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
1243                 REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ);
1244
1245                 val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC);
1246
1247                 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
1248
1249                 /* The addresses with Bit 9 set are bad memory blocks. */
1250                 if (!(val & (1 << 9))) {
1251                         good_mbuf[good_mbuf_cnt] = (u16) val;
1252                         good_mbuf_cnt++;
1253                 }
1254
1255                 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1256         }
1257
1258         /* Free the good ones back to the mbuf pool thus discarding
1259          * all the bad ones. */
1260         while (good_mbuf_cnt) {
1261                 good_mbuf_cnt--;
1262
1263                 val = good_mbuf[good_mbuf_cnt];
1264                 val = (val << 9) | val | 1;
1265
1266                 REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val);
1267         }
1268         return 0;
1269 }
1270
1271 static void
1272 bnx2_set_mac_addr(struct bnx2 *bp) 
1273 {
1274         u32 val;
1275         u8 *mac_addr = bp->nic->node_addr;
1276
1277         val = (mac_addr[0] << 8) | mac_addr[1];
1278
1279         REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
1280
1281         val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 
1282                 (mac_addr[4] << 8) | mac_addr[5];
1283
1284         REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
1285 }
1286
1287 static void
1288 bnx2_set_rx_mode(struct nic *nic __unused)
1289 {
1290         struct bnx2 *bp = &bnx2;
1291         u32 rx_mode, sort_mode;
1292         int i;
1293
1294         rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
1295                                   BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
1296         sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
1297
1298         if (!(bp->flags & ASF_ENABLE_FLAG)) {
1299                 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
1300         }
1301
1302         /* Accept all multicasts */
1303         for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
1304                 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
1305                        0xffffffff);
1306         }
1307         sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
1308
1309         if (rx_mode != bp->rx_mode) {
1310                 bp->rx_mode = rx_mode;
1311                 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
1312         }
1313
1314         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
1315         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
1316         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
1317 }
1318
1319 static void
1320 load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len, u32 rv2p_proc)
1321 {
1322         unsigned int i;
1323         u32 val;
1324
1325
1326         for (i = 0; i < rv2p_code_len; i += 8) {
1327                 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, *rv2p_code);
1328                 rv2p_code++;
1329                 REG_WR(bp, BNX2_RV2P_INSTR_LOW, *rv2p_code);
1330                 rv2p_code++;
1331
1332                 if (rv2p_proc == RV2P_PROC1) {
1333                         val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
1334                         REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
1335                 }
1336                 else {
1337                         val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
1338                         REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
1339                 }
1340         }
1341
1342         /* Reset the processor, un-stall is done later. */
1343         if (rv2p_proc == RV2P_PROC1) {
1344                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
1345         }
1346         else {
1347                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
1348         }
1349 }
1350
1351 static void
1352 load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
1353 {
1354         u32 offset;
1355         u32 val;
1356
1357         /* Halt the CPU. */
1358         val = REG_RD_IND(bp, cpu_reg->mode);
1359         val |= cpu_reg->mode_value_halt;
1360         REG_WR_IND(bp, cpu_reg->mode, val);
1361         REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
1362
1363         /* Load the Text area. */
1364         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
1365         if (fw->text) {
1366                 unsigned int j;
1367
1368                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
1369                         REG_WR_IND(bp, offset, fw->text[j]);
1370                 }
1371         }
1372
1373         /* Load the Data area. */
1374         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
1375         if (fw->data) {
1376                 unsigned int j;
1377
1378                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
1379                         REG_WR_IND(bp, offset, fw->data[j]);
1380                 }
1381         }
1382
1383         /* Load the SBSS area. */
1384         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
1385         if (fw->sbss) {
1386                 unsigned int j;
1387
1388                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
1389                         REG_WR_IND(bp, offset, fw->sbss[j]);
1390                 }
1391         }
1392
1393         /* Load the BSS area. */
1394         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
1395         if (fw->bss) {
1396                 unsigned int j;
1397
1398                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
1399                         REG_WR_IND(bp, offset, fw->bss[j]);
1400                 }
1401         }
1402
1403         /* Load the Read-Only area. */
1404         offset = cpu_reg->spad_base +
1405                 (fw->rodata_addr - cpu_reg->mips_view_base);
1406         if (fw->rodata) {
1407                 unsigned int j;
1408
1409                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
1410                         REG_WR_IND(bp, offset, fw->rodata[j]);
1411                 }
1412         }
1413
1414         /* Clear the pre-fetch instruction. */
1415         REG_WR_IND(bp, cpu_reg->inst, 0);
1416         REG_WR_IND(bp, cpu_reg->pc, fw->start_addr);
1417
1418         /* Start the CPU. */
1419         val = REG_RD_IND(bp, cpu_reg->mode);
1420         val &= ~cpu_reg->mode_value_halt;
1421         REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
1422         REG_WR_IND(bp, cpu_reg->mode, val);
1423 }
1424
1425 static void
1426 bnx2_init_cpus(struct bnx2 *bp)
1427 {
1428         struct cpu_reg cpu_reg;
1429         struct fw_info fw;
1430
1431         /* Unfortunately, it looks like we need to load the firmware
1432          * before the card will work properly.  That means this driver
1433          * will be huge by Etherboot standards (approx. 50K compressed).
1434          */
1435
1436         /* Initialize the RV2P processor. */
1437         load_rv2p_fw(bp, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1), RV2P_PROC1);
1438         load_rv2p_fw(bp, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2), RV2P_PROC2);
1439
1440         /* Initialize the RX Processor. */
1441         cpu_reg.mode = BNX2_RXP_CPU_MODE;
1442         cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
1443         cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
1444         cpu_reg.state = BNX2_RXP_CPU_STATE;
1445         cpu_reg.state_value_clear = 0xffffff;
1446         cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
1447         cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
1448         cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
1449         cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
1450         cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
1451         cpu_reg.spad_base = BNX2_RXP_SCRATCH;
1452         cpu_reg.mips_view_base = 0x8000000;
1453
1454         fw.ver_major = bnx2_RXP_b06FwReleaseMajor;
1455         fw.ver_minor = bnx2_RXP_b06FwReleaseMinor;
1456         fw.ver_fix = bnx2_RXP_b06FwReleaseFix;
1457         fw.start_addr = bnx2_RXP_b06FwStartAddr;
1458
1459         fw.text_addr = bnx2_RXP_b06FwTextAddr;
1460         fw.text_len = bnx2_RXP_b06FwTextLen;
1461         fw.text_index = 0;
1462         fw.text = bnx2_RXP_b06FwText;
1463
1464         fw.data_addr = bnx2_RXP_b06FwDataAddr;
1465         fw.data_len = bnx2_RXP_b06FwDataLen;
1466         fw.data_index = 0;
1467         fw.data = bnx2_RXP_b06FwData;
1468
1469         fw.sbss_addr = bnx2_RXP_b06FwSbssAddr;
1470         fw.sbss_len = bnx2_RXP_b06FwSbssLen;
1471         fw.sbss_index = 0;
1472         fw.sbss = bnx2_RXP_b06FwSbss;
1473
1474         fw.bss_addr = bnx2_RXP_b06FwBssAddr;
1475         fw.bss_len = bnx2_RXP_b06FwBssLen;
1476         fw.bss_index = 0;
1477         fw.bss = bnx2_RXP_b06FwBss;
1478
1479         fw.rodata_addr = bnx2_RXP_b06FwRodataAddr;
1480         fw.rodata_len = bnx2_RXP_b06FwRodataLen;
1481         fw.rodata_index = 0;
1482         fw.rodata = bnx2_RXP_b06FwRodata;
1483
1484         load_cpu_fw(bp, &cpu_reg, &fw);
1485
1486         /* Initialize the TX Processor. */
1487         cpu_reg.mode = BNX2_TXP_CPU_MODE;
1488         cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
1489         cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
1490         cpu_reg.state = BNX2_TXP_CPU_STATE;
1491         cpu_reg.state_value_clear = 0xffffff;
1492         cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
1493         cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
1494         cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
1495         cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
1496         cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
1497         cpu_reg.spad_base = BNX2_TXP_SCRATCH;
1498         cpu_reg.mips_view_base = 0x8000000;
1499     
1500         fw.ver_major = bnx2_TXP_b06FwReleaseMajor;
1501         fw.ver_minor = bnx2_TXP_b06FwReleaseMinor;
1502         fw.ver_fix = bnx2_TXP_b06FwReleaseFix;
1503         fw.start_addr = bnx2_TXP_b06FwStartAddr;
1504
1505         fw.text_addr = bnx2_TXP_b06FwTextAddr;
1506         fw.text_len = bnx2_TXP_b06FwTextLen;
1507         fw.text_index = 0;
1508         fw.text = bnx2_TXP_b06FwText;
1509
1510         fw.data_addr = bnx2_TXP_b06FwDataAddr;
1511         fw.data_len = bnx2_TXP_b06FwDataLen;
1512         fw.data_index = 0;
1513         fw.data = bnx2_TXP_b06FwData;
1514
1515         fw.sbss_addr = bnx2_TXP_b06FwSbssAddr;
1516         fw.sbss_len = bnx2_TXP_b06FwSbssLen;
1517         fw.sbss_index = 0;
1518         fw.sbss = bnx2_TXP_b06FwSbss;
1519
1520         fw.bss_addr = bnx2_TXP_b06FwBssAddr;
1521         fw.bss_len = bnx2_TXP_b06FwBssLen;
1522         fw.bss_index = 0;
1523         fw.bss = bnx2_TXP_b06FwBss;
1524
1525         fw.rodata_addr = bnx2_TXP_b06FwRodataAddr;
1526         fw.rodata_len = bnx2_TXP_b06FwRodataLen;
1527         fw.rodata_index = 0;
1528         fw.rodata = bnx2_TXP_b06FwRodata;
1529
1530         load_cpu_fw(bp, &cpu_reg, &fw);
1531
1532         /* Initialize the TX Patch-up Processor. */
1533         cpu_reg.mode = BNX2_TPAT_CPU_MODE;
1534         cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
1535         cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
1536         cpu_reg.state = BNX2_TPAT_CPU_STATE;
1537         cpu_reg.state_value_clear = 0xffffff;
1538         cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
1539         cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
1540         cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
1541         cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
1542         cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
1543         cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
1544         cpu_reg.mips_view_base = 0x8000000;
1545     
1546         fw.ver_major = bnx2_TPAT_b06FwReleaseMajor;
1547         fw.ver_minor = bnx2_TPAT_b06FwReleaseMinor;
1548         fw.ver_fix = bnx2_TPAT_b06FwReleaseFix;
1549         fw.start_addr = bnx2_TPAT_b06FwStartAddr;
1550
1551         fw.text_addr = bnx2_TPAT_b06FwTextAddr;
1552         fw.text_len = bnx2_TPAT_b06FwTextLen;
1553         fw.text_index = 0;
1554         fw.text = bnx2_TPAT_b06FwText;
1555
1556         fw.data_addr = bnx2_TPAT_b06FwDataAddr;
1557         fw.data_len = bnx2_TPAT_b06FwDataLen;
1558         fw.data_index = 0;
1559         fw.data = bnx2_TPAT_b06FwData;
1560
1561         fw.sbss_addr = bnx2_TPAT_b06FwSbssAddr;
1562         fw.sbss_len = bnx2_TPAT_b06FwSbssLen;
1563         fw.sbss_index = 0;
1564         fw.sbss = bnx2_TPAT_b06FwSbss;
1565
1566         fw.bss_addr = bnx2_TPAT_b06FwBssAddr;
1567         fw.bss_len = bnx2_TPAT_b06FwBssLen;
1568         fw.bss_index = 0;
1569         fw.bss = bnx2_TPAT_b06FwBss;
1570
1571         fw.rodata_addr = bnx2_TPAT_b06FwRodataAddr;
1572         fw.rodata_len = bnx2_TPAT_b06FwRodataLen;
1573         fw.rodata_index = 0;
1574         fw.rodata = bnx2_TPAT_b06FwRodata;
1575
1576         load_cpu_fw(bp, &cpu_reg, &fw);
1577
1578         /* Initialize the Completion Processor. */
1579         cpu_reg.mode = BNX2_COM_CPU_MODE;
1580         cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
1581         cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
1582         cpu_reg.state = BNX2_COM_CPU_STATE;
1583         cpu_reg.state_value_clear = 0xffffff;
1584         cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
1585         cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
1586         cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
1587         cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
1588         cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
1589         cpu_reg.spad_base = BNX2_COM_SCRATCH;
1590         cpu_reg.mips_view_base = 0x8000000;
1591     
1592         fw.ver_major = bnx2_COM_b06FwReleaseMajor;
1593         fw.ver_minor = bnx2_COM_b06FwReleaseMinor;
1594         fw.ver_fix = bnx2_COM_b06FwReleaseFix;
1595         fw.start_addr = bnx2_COM_b06FwStartAddr;
1596
1597         fw.text_addr = bnx2_COM_b06FwTextAddr;
1598         fw.text_len = bnx2_COM_b06FwTextLen;
1599         fw.text_index = 0;
1600         fw.text = bnx2_COM_b06FwText;
1601
1602         fw.data_addr = bnx2_COM_b06FwDataAddr;
1603         fw.data_len = bnx2_COM_b06FwDataLen;
1604         fw.data_index = 0;
1605         fw.data = bnx2_COM_b06FwData;
1606
1607         fw.sbss_addr = bnx2_COM_b06FwSbssAddr;
1608         fw.sbss_len = bnx2_COM_b06FwSbssLen;
1609         fw.sbss_index = 0;
1610         fw.sbss = bnx2_COM_b06FwSbss;
1611
1612         fw.bss_addr = bnx2_COM_b06FwBssAddr;
1613         fw.bss_len = bnx2_COM_b06FwBssLen;
1614         fw.bss_index = 0;
1615         fw.bss = bnx2_COM_b06FwBss;
1616
1617         fw.rodata_addr = bnx2_COM_b06FwRodataAddr;
1618         fw.rodata_len = bnx2_COM_b06FwRodataLen;
1619         fw.rodata_index = 0;
1620         fw.rodata = bnx2_COM_b06FwRodata;
1621
1622         load_cpu_fw(bp, &cpu_reg, &fw);
1623
1624 }
1625
1626 static int
1627 bnx2_set_power_state_0(struct bnx2 *bp)
1628 {
1629         u16 pmcsr;
1630         u32 val;
1631
1632         pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
1633
1634         pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
1635                 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
1636                 PCI_PM_CTRL_PME_STATUS);
1637
1638         if (pmcsr & PCI_PM_CTRL_STATE_MASK)
1639                 /* delay required during transition out of D3hot */
1640                 mdelay(20);
1641
1642         val = REG_RD(bp, BNX2_EMAC_MODE);
1643         val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
1644         val &= ~BNX2_EMAC_MODE_MPKT;
1645         REG_WR(bp, BNX2_EMAC_MODE, val);
1646
1647         val = REG_RD(bp, BNX2_RPM_CONFIG);
1648         val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
1649         REG_WR(bp, BNX2_RPM_CONFIG, val);
1650                 
1651         return 0;
1652 }
1653
1654 static void
1655 bnx2_enable_nvram_access(struct bnx2 *bp)
1656 {
1657         u32 val;
1658
1659         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
1660         /* Enable both bits, even on read. */
1661         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE, 
1662                val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
1663 }
1664
1665 static void
1666 bnx2_disable_nvram_access(struct bnx2 *bp)
1667 {
1668         u32 val;
1669
1670         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
1671         /* Disable both bits, even after read. */
1672         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE, 
1673                 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
1674                         BNX2_NVM_ACCESS_ENABLE_WR_EN));
1675 }
1676
1677 static int
1678 bnx2_init_nvram(struct bnx2 *bp)
1679 {
1680         u32 val;
1681         int j, entry_count, rc;
1682         struct flash_spec *flash;
1683
1684         /* Determine the selected interface. */
1685         val = REG_RD(bp, BNX2_NVM_CFG1);
1686
1687         entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
1688
1689         rc = 0;
1690         if (val & 0x40000000) {
1691                 /* Flash interface has been reconfigured */
1692                 for (j = 0, flash = &flash_table[0]; j < entry_count;
1693                      j++, flash++) {
1694                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
1695                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
1696                                 bp->flash_info = flash;
1697                                 break;
1698                         }
1699                 }
1700         }
1701         else {
1702                 u32 mask;
1703                 /* Not yet been reconfigured */
1704
1705                 if (val & (1 << 23))
1706                         mask = FLASH_BACKUP_STRAP_MASK;
1707                 else
1708                         mask = FLASH_STRAP_MASK;
1709
1710                 for (j = 0, flash = &flash_table[0]; j < entry_count;
1711                         j++, flash++) {
1712
1713                         if ((val & mask) == (flash->strapping & mask)) {
1714                                 bp->flash_info = flash;
1715
1716                                 /* Enable access to flash interface */
1717                                 bnx2_enable_nvram_access(bp);
1718
1719                                 /* Reconfigure the flash interface */
1720                                 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
1721                                 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
1722                                 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
1723                                 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
1724
1725                                 /* Disable access to flash interface */
1726                                 bnx2_disable_nvram_access(bp);
1727
1728                                 break;
1729                         }
1730                 }
1731         } /* if (val & 0x40000000) */
1732
1733         if (j == entry_count) {
1734                 bp->flash_info = NULL;
1735                 printf("Unknown flash/EEPROM type.\n");
1736                 return -ENODEV;
1737         }
1738
1739         val = REG_RD_IND(bp, bp->shmem_base + BNX2_SHARED_HW_CFG_CONFIG2);
1740         val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
1741         if (val) {
1742                 bp->flash_size = val;
1743         }
1744         else {
1745                 bp->flash_size = bp->flash_info->total_size;
1746         }
1747
1748         return rc;
1749 }
1750
1751 static int
1752 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
1753 {
1754         u32 val;
1755         int i, rc = 0;
1756
1757         /* Wait for the current PCI transaction to complete before
1758          * issuing a reset. */
1759         REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
1760                BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
1761                BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
1762                BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
1763                BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
1764         val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
1765         udelay(5);
1766
1767
1768         /* Wait for the firmware to tell us it is ok to issue a reset. */
1769         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1);
1770
1771         /* Deposit a driver reset signature so the firmware knows that
1772          * this is a soft reset. */
1773         REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_RESET_SIGNATURE,
1774                    BNX2_DRV_RESET_SIGNATURE_MAGIC);
1775
1776         /* Do a dummy read to force the chip to complete all current transaction
1777          * before we issue a reset. */
1778         val = REG_RD(bp, BNX2_MISC_ID);
1779
1780         val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
1781               BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
1782               BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
1783
1784         /* Chip reset. */
1785         REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
1786
1787         if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
1788             (CHIP_ID(bp) == CHIP_ID_5706_A1))
1789                 mdelay(15);
1790
1791         /* Reset takes approximate 30 usec */
1792         for (i = 0; i < 10; i++) {
1793                 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
1794                 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
1795                             BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
1796                         break;
1797                 }
1798                 udelay(10);
1799         }
1800
1801         if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
1802                    BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
1803                 printf("Chip reset did not complete\n");
1804                 return -EBUSY;
1805         }
1806
1807         /* Make sure byte swapping is properly configured. */
1808         val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
1809         if (val != 0x01020304) {
1810                 printf("Chip not in correct endian mode\n");
1811                 return -ENODEV;
1812         }
1813
1814         /* Wait for the firmware to finish its initialization. */
1815         rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 0);
1816         if (rc) {
1817                 return rc;
1818         }
1819
1820         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
1821                 /* Adjust the voltage regular to two steps lower.  The default
1822                  * of this register is 0x0000000e. */
1823                 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
1824
1825                 /* Remove bad rbuf memory from the free pool. */
1826                 rc = bnx2_alloc_bad_rbuf(bp);
1827         }
1828
1829         return rc;
1830 }
1831
1832 static void
1833 bnx2_disable(struct nic *nic __unused)
1834 {
1835         struct bnx2* bp = &bnx2;
1836
1837         if (bp->regview) {
1838                 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_UNLOAD);
1839                 iounmap(bp->regview);
1840         }
1841 }
1842
1843 static int
1844 bnx2_init_chip(struct bnx2 *bp)
1845 {
1846         u32 val;
1847         int rc;
1848
1849         /* Make sure the interrupt is not active. */
1850         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1851
1852         val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
1853               BNX2_DMA_CONFIG_DATA_WORD_SWAP |
1854 #if __BYTE_ORDER ==  __BIG_ENDIAN
1855               BNX2_DMA_CONFIG_CNTL_BYTE_SWAP | 
1856 #endif
1857               BNX2_DMA_CONFIG_CNTL_WORD_SWAP | 
1858               DMA_READ_CHANS << 12 |
1859               DMA_WRITE_CHANS << 16;
1860
1861         val |= (0x2 << 20) | (1 << 11);
1862
1863         if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz == 133))
1864                 val |= (1 << 23);
1865
1866         if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
1867             (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & PCIX_FLAG))
1868                 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
1869
1870         REG_WR(bp, BNX2_DMA_CONFIG, val);
1871
1872         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
1873                 val = REG_RD(bp, BNX2_TDMA_CONFIG);
1874                 val |= BNX2_TDMA_CONFIG_ONE_DMA;
1875                 REG_WR(bp, BNX2_TDMA_CONFIG, val);
1876         }
1877
1878         if (bp->flags & PCIX_FLAG) {
1879                 u16 val16;
1880
1881                 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
1882                                      &val16);
1883                 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
1884                                       val16 & ~PCI_X_CMD_ERO);
1885         }
1886
1887         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
1888                BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
1889                BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
1890                BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
1891
1892         /* Initialize context mapping and zero out the quick contexts.  The
1893          * context block must have already been enabled. */
1894         bnx2_init_context(bp);
1895
1896         bnx2_init_nvram(bp);
1897         bnx2_init_cpus(bp);
1898
1899         bnx2_set_mac_addr(bp);
1900
1901         val = REG_RD(bp, BNX2_MQ_CONFIG);
1902         val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
1903         val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
1904         REG_WR(bp, BNX2_MQ_CONFIG, val);
1905
1906         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
1907         REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
1908         REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
1909
1910         val = (BCM_PAGE_BITS - 8) << 24;
1911         REG_WR(bp, BNX2_RV2P_CONFIG, val);
1912
1913         /* Configure page size. */
1914         val = REG_RD(bp, BNX2_TBDR_CONFIG);
1915         val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
1916         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
1917         REG_WR(bp, BNX2_TBDR_CONFIG, val);
1918
1919         val = bp->mac_addr[0] +
1920               (bp->mac_addr[1] << 8) +
1921               (bp->mac_addr[2] << 16) +
1922               bp->mac_addr[3] +
1923               (bp->mac_addr[4] << 8) +
1924               (bp->mac_addr[5] << 16);
1925         REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
1926
1927         /* Program the MTU.  Also include 4 bytes for CRC32. */
1928         val = ETH_MAX_MTU + ETH_HLEN + 4;
1929         if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
1930                 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
1931         REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
1932
1933         bp->last_status_idx = 0;
1934         bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
1935
1936         /* Set up how to generate a link change interrupt. */
1937         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
1938
1939         REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
1940                (u64) bp->status_blk_mapping & 0xffffffff);
1941         REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
1942
1943         REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
1944                (u64) bp->stats_blk_mapping & 0xffffffff);
1945         REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
1946                (u64) bp->stats_blk_mapping >> 32);
1947
1948         REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP, 
1949                (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
1950
1951         REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
1952                (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
1953
1954         REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
1955                (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
1956
1957         REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
1958
1959         REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
1960
1961         REG_WR(bp, BNX2_HC_COM_TICKS,
1962                (bp->com_ticks_int << 16) | bp->com_ticks);
1963
1964         REG_WR(bp, BNX2_HC_CMD_TICKS,
1965                (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
1966
1967         REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks & 0xffff00);
1968         REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8);  /* 3ms */
1969
1970         if (CHIP_ID(bp) == CHIP_ID_5706_A1)
1971                 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_COLLECT_STATS);
1972         else {
1973                 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_RX_TMR_MODE |
1974                        BNX2_HC_CONFIG_TX_TMR_MODE |
1975                        BNX2_HC_CONFIG_COLLECT_STATS);
1976         }
1977
1978         /* Clear internal stats counters. */
1979         REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
1980
1981         REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
1982
1983         if (REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_FEATURE) &
1984             BNX2_PORT_FEATURE_ASF_ENABLED)
1985                 bp->flags |= ASF_ENABLE_FLAG;
1986
1987         /* Initialize the receive filter. */
1988         bnx2_set_rx_mode(bp->nic);
1989
1990         rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
1991                           0);
1992
1993         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 0x5ffffff);
1994         REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
1995
1996         udelay(20);
1997
1998         bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
1999
2000         return rc;
2001 }
2002
2003 static void
2004 bnx2_init_tx_ring(struct bnx2 *bp)
2005 {
2006         struct tx_bd *txbd;
2007         u32 val;
2008
2009         txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
2010                 
2011         /* Etherboot lives below 4GB, so hi is always 0 */
2012         txbd->tx_bd_haddr_hi = 0;
2013         txbd->tx_bd_haddr_lo = bp->tx_desc_mapping;
2014
2015         bp->tx_prod = 0;
2016         bp->tx_cons = 0;
2017         bp->hw_tx_cons = 0;
2018         bp->tx_prod_bseq = 0;
2019         
2020         val = BNX2_L2CTX_TYPE_TYPE_L2;
2021         val |= BNX2_L2CTX_TYPE_SIZE_L2;
2022         CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TYPE, val);
2023
2024         val = BNX2_L2CTX_CMD_TYPE_TYPE_L2;
2025         val |= 8 << 16;
2026         CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_CMD_TYPE, val);
2027
2028         /* Etherboot lives below 4GB, so hi is always 0 */
2029         CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_HI, 0);
2030
2031         val = (u64) bp->tx_desc_mapping & 0xffffffff;
2032         CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_LO, val);
2033 }
2034
2035 static void
2036 bnx2_init_rx_ring(struct bnx2 *bp)
2037 {
2038         struct rx_bd *rxbd;
2039         unsigned int i;
2040         u16 prod, ring_prod;
2041         u32 val;
2042
2043         bp->rx_buf_use_size = RX_BUF_USE_SIZE;
2044         bp->rx_buf_size = RX_BUF_SIZE;
2045
2046         ring_prod = prod = bp->rx_prod = 0;
2047         bp->rx_cons = 0;
2048         bp->hw_rx_cons = 0;
2049         bp->rx_prod_bseq = 0;
2050
2051         memset(bnx2_bss.rx_buf, 0, sizeof(bnx2_bss.rx_buf));
2052                 
2053         rxbd = &bp->rx_desc_ring[0];
2054         for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
2055                 rxbd->rx_bd_len = bp->rx_buf_use_size;
2056                 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
2057         }
2058         rxbd->rx_bd_haddr_hi = 0;
2059         rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping & 0xffffffff;
2060
2061         val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
2062         val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
2063         val |= 0x02 << 8;
2064         CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_CTX_TYPE, val);
2065
2066         /* Etherboot doesn't use memory above 4GB, so this is always 0 */
2067         CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_HI, 0);
2068
2069         val = bp->rx_desc_mapping & 0xffffffff;
2070         CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val);
2071
2072         for (i = 0; (int) i < bp->rx_ring_size; i++) {
2073                 rxbd = &bp->rx_desc_ring[RX_RING_IDX(ring_prod)];
2074                 rxbd->rx_bd_haddr_hi = 0;
2075                 rxbd->rx_bd_haddr_lo = virt_to_bus(&bnx2_bss.rx_buf[ring_prod][0]);
2076                 bp->rx_prod_bseq += bp->rx_buf_use_size;
2077                 prod = NEXT_RX_BD(prod);
2078                 ring_prod = RX_RING_IDX(prod);
2079         }
2080         bp->rx_prod = prod;
2081
2082         REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, bp->rx_prod);
2083
2084         REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
2085 }
2086
2087 static int
2088 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
2089 {
2090         int rc;
2091
2092         rc = bnx2_reset_chip(bp, reset_code);
2093         if (rc) {
2094                 return rc;
2095         }
2096
2097         bnx2_init_chip(bp);
2098         bnx2_init_tx_ring(bp);
2099         bnx2_init_rx_ring(bp);
2100         return 0;
2101 }
2102
2103 static int
2104 bnx2_init_nic(struct bnx2 *bp)
2105 {
2106         int rc;
2107
2108         if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
2109                 return rc;
2110
2111         bnx2_init_phy(bp);
2112         bnx2_set_link(bp);
2113         return 0;
2114 }
2115
2116 static int
2117 bnx2_init_board(struct pci_device *pdev, struct nic *nic)
2118 {
2119         unsigned long bnx2reg_base, bnx2reg_len;
2120         struct bnx2 *bp = &bnx2;
2121         int rc;
2122         u32 reg;
2123
2124         bp->flags = 0;
2125         bp->phy_flags = 0;
2126
2127         /* enable device (incl. PCI PM wakeup), and bus-mastering */
2128         adjust_pci_device(pdev);
2129
2130         nic->ioaddr = pdev->ioaddr & ~3;
2131         nic->irqno = 0;
2132
2133         rc = 0;
2134         bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
2135         if (bp->pm_cap == 0) {
2136                 printf("Cannot find power management capability, aborting.\n");
2137                 rc = -EIO;
2138                 goto err_out_disable;
2139         }
2140
2141         bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
2142         if (bp->pcix_cap == 0) {
2143                 printf("Cannot find PCIX capability, aborting.\n");
2144                 rc = -EIO;
2145                 goto err_out_disable;
2146         }
2147
2148         bp->pdev = pdev;
2149         bp->nic = nic;
2150
2151         bnx2reg_base = pci_bar_start(pdev, PCI_BASE_ADDRESS_0);
2152         bnx2reg_len = MB_GET_CID_ADDR(17);
2153
2154         bp->regview = ioremap(bnx2reg_base, bnx2reg_len);
2155
2156         if (!bp->regview) {
2157                 printf("Cannot map register space, aborting.\n");
2158                 rc = -EIO;
2159                 goto err_out_disable;
2160         }
2161
2162         /* Configure byte swap and enable write to the reg_window registers.
2163          * Rely on CPU to do target byte swapping on big endian systems
2164          * The chip's target access swapping will not swap all accesses
2165          */
2166         pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
2167                                BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
2168                                BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
2169
2170         bnx2_set_power_state_0(bp);
2171
2172         bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
2173
2174         /* Get bus information. */
2175         reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
2176         if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
2177                 u32 clkreg;
2178
2179                 bp->flags |= PCIX_FLAG;
2180
2181                 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
2182                 
2183                 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
2184                 switch (clkreg) {
2185                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
2186                         bp->bus_speed_mhz = 133;
2187                         break;
2188
2189                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
2190                         bp->bus_speed_mhz = 100;
2191                         break;
2192
2193                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
2194                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
2195                         bp->bus_speed_mhz = 66;
2196                         break;
2197
2198                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
2199                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
2200                         bp->bus_speed_mhz = 50;
2201                         break;
2202
2203                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
2204                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
2205                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
2206                         bp->bus_speed_mhz = 33;
2207                         break;
2208                 }
2209         }
2210         else {
2211                 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
2212                         bp->bus_speed_mhz = 66;
2213                 else
2214                         bp->bus_speed_mhz = 33;
2215         }
2216
2217         if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
2218                 bp->flags |= PCI_32BIT_FLAG;
2219
2220         /* 5706A0 may falsely detect SERR and PERR. */
2221         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2222                 reg = REG_RD(bp, PCI_COMMAND);
2223                 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
2224                 REG_WR(bp, PCI_COMMAND, reg);
2225         }
2226         else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
2227                 !(bp->flags & PCIX_FLAG)) {
2228
2229                 printf("5706 A1 can only be used in a PCIX bus, aborting.\n");
2230                 goto err_out_disable;
2231         }
2232
2233         bnx2_init_nvram(bp);
2234
2235         reg = REG_RD_IND(bp, BNX2_SHM_HDR_SIGNATURE);
2236
2237         if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
2238             BNX2_SHM_HDR_SIGNATURE_SIG)
2239                 bp->shmem_base = REG_RD_IND(bp, BNX2_SHM_HDR_ADDR_0);
2240         else
2241                 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
2242
2243         /* Get the permanent MAC address.  First we need to make sure the
2244          * firmware is actually running.
2245          */
2246         reg = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_SIGNATURE);
2247
2248         if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
2249             BNX2_DEV_INFO_SIGNATURE_MAGIC) {
2250                 printf("Firmware not running, aborting.\n");
2251                 rc = -ENODEV;
2252                 goto err_out_disable;
2253         }
2254
2255         bp->fw_ver = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_BC_REV);
2256
2257         reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_UPPER);
2258         bp->mac_addr[0] = (u8) (reg >> 8);
2259         bp->mac_addr[1] = (u8) reg;
2260
2261         reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_LOWER);
2262         bp->mac_addr[2] = (u8) (reg >> 24);
2263         bp->mac_addr[3] = (u8) (reg >> 16);
2264         bp->mac_addr[4] = (u8) (reg >> 8);
2265         bp->mac_addr[5] = (u8) reg;
2266
2267         bp->tx_ring_size = MAX_TX_DESC_CNT;
2268         bp->rx_ring_size = RX_BUF_CNT;
2269         bp->rx_max_ring_idx = MAX_RX_DESC_CNT;
2270
2271         bp->rx_offset = RX_OFFSET;
2272
2273         bp->tx_quick_cons_trip_int = 20;
2274         bp->tx_quick_cons_trip = 20;
2275         bp->tx_ticks_int = 80;
2276         bp->tx_ticks = 80;
2277                 
2278         bp->rx_quick_cons_trip_int = 6;
2279         bp->rx_quick_cons_trip = 6;
2280         bp->rx_ticks_int = 18;
2281         bp->rx_ticks = 18;
2282
2283         bp->stats_ticks = 1000000 & 0xffff00;
2284
2285         bp->phy_addr = 1;
2286
2287         /* No need for WOL support in Etherboot */
2288         bp->flags |= NO_WOL_FLAG;
2289
2290         /* Disable WOL support if we are running on a SERDES chip. */
2291         if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) {
2292                 bp->phy_flags |= PHY_SERDES_FLAG;
2293                 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
2294                         bp->phy_addr = 2;
2295                         reg = REG_RD_IND(bp, bp->shmem_base +
2296                                          BNX2_SHARED_HW_CFG_CONFIG);
2297                         if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
2298                                 bp->phy_flags |= PHY_2_5G_CAPABLE_FLAG;
2299                 }
2300         }
2301
2302         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2303                 bp->tx_quick_cons_trip_int =
2304                         bp->tx_quick_cons_trip;
2305                 bp->tx_ticks_int = bp->tx_ticks;
2306                 bp->rx_quick_cons_trip_int =
2307                         bp->rx_quick_cons_trip;
2308                 bp->rx_ticks_int = bp->rx_ticks;
2309                 bp->comp_prod_trip_int = bp->comp_prod_trip;
2310                 bp->com_ticks_int = bp->com_ticks;
2311                 bp->cmd_ticks_int = bp->cmd_ticks;
2312         }
2313
2314         bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
2315         bp->req_line_speed = 0;
2316         if (bp->phy_flags & PHY_SERDES_FLAG) {
2317                 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
2318
2319                 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG);
2320                 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
2321                 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
2322                         bp->autoneg = 0;
2323                         bp->req_line_speed = bp->line_speed = SPEED_1000;
2324                         bp->req_duplex = DUPLEX_FULL;
2325                 }
2326         }
2327         else {
2328                 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
2329         }
2330
2331         bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
2332
2333         /* Disable driver heartbeat checking */
2334         REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_PULSE_MB,
2335                         BNX2_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE);
2336         REG_RD_IND(bp, bp->shmem_base + BNX2_DRV_PULSE_MB);
2337
2338         return 0;
2339
2340 err_out_disable:
2341         bnx2_disable(nic);
2342
2343         return rc;
2344 }
2345
2346 static void
2347 bnx2_transmit(struct nic *nic, const char *dst_addr,
2348                 unsigned int type, unsigned int size, const char *packet)
2349 {
2350         /* Sometimes the nic will be behind by a frame.  Using two transmit
2351          * buffers prevents us from timing out in that case.
2352          */
2353         static struct eth_frame {
2354                 uint8_t  dst_addr[ETH_ALEN];
2355                 uint8_t  src_addr[ETH_ALEN];
2356                 uint16_t type;
2357                 uint8_t  data [ETH_FRAME_LEN - ETH_HLEN];
2358         } frame[2];
2359         static int frame_idx = 0;
2360         
2361         /* send the packet to destination */
2362         struct tx_bd *txbd;
2363         struct bnx2 *bp = &bnx2;
2364         u16 prod, ring_prod;
2365         u16 hw_cons;
2366         int i = 0;
2367
2368         prod = bp->tx_prod;
2369         ring_prod = TX_RING_IDX(prod);
2370         hw_cons = bp->status_blk->status_tx_quick_consumer_index0;
2371         if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
2372                 hw_cons++;
2373         }
2374
2375         while((hw_cons != prod) && (hw_cons != (PREV_TX_BD(prod)))) {
2376                 mdelay(10);     /* give the nic a chance */
2377                 //poll_interruptions();
2378                 if (++i > 500) { /* timeout 5s for transmit */
2379                         printf("transmit timed out\n");
2380                         bnx2_disable(bp->nic);
2381                         bnx2_init_board(bp->pdev, bp->nic);
2382                         return;
2383                 }
2384         }
2385         if (i != 0) {
2386                 printf("#");
2387         }
2388
2389         /* Copy the packet to the our local buffer */
2390         memcpy(&frame[frame_idx].dst_addr, dst_addr, ETH_ALEN);
2391         memcpy(&frame[frame_idx].src_addr, nic->node_addr, ETH_ALEN);
2392         frame[frame_idx].type = htons(type);
2393         memset(&frame[frame_idx].data, 0, sizeof(frame[frame_idx].data));
2394         memcpy(&frame[frame_idx].data, packet, size);
2395
2396         /* Setup the ring buffer entry to transmit */
2397         txbd = &bp->tx_desc_ring[ring_prod];
2398         txbd->tx_bd_haddr_hi = 0; /* Etherboot runs under 4GB */
2399         txbd->tx_bd_haddr_lo = virt_to_bus(&frame[frame_idx]);
2400         txbd->tx_bd_mss_nbytes = (size + ETH_HLEN);
2401         txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
2402
2403         /* Advance to the next entry */
2404         prod = NEXT_TX_BD(prod);
2405         frame_idx ^= 1;
2406
2407         bp->tx_prod_bseq += (size + ETH_HLEN);
2408
2409         REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, prod);
2410         REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq);
2411
2412         wmb();
2413
2414         bp->tx_prod = prod;
2415 }
2416
2417 static int
2418 bnx2_poll_link(struct bnx2 *bp)
2419 {
2420         u32 new_link_state, old_link_state, emac_status;
2421
2422         new_link_state = bp->status_blk->status_attn_bits &
2423                 STATUS_ATTN_BITS_LINK_STATE;
2424
2425         old_link_state = bp->status_blk->status_attn_bits_ack &
2426                 STATUS_ATTN_BITS_LINK_STATE;
2427
2428         if (!new_link_state && !old_link_state) {
2429                 /* For some reason the card doesn't always update the link
2430                  * status bits properly.  Kick the stupid thing and try again.
2431                  */
2432                 u32 bmsr;
2433
2434                 bnx2_read_phy(bp, MII_BMSR, &bmsr);
2435                 bnx2_read_phy(bp, MII_BMSR, &bmsr);
2436
2437                 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
2438                     (CHIP_NUM(bp) == CHIP_NUM_5706)) {
2439                         REG_RD(bp, BNX2_EMAC_STATUS);
2440                 }
2441
2442                 new_link_state = bp->status_blk->status_attn_bits &
2443                         STATUS_ATTN_BITS_LINK_STATE;
2444
2445                 old_link_state = bp->status_blk->status_attn_bits_ack &
2446                         STATUS_ATTN_BITS_LINK_STATE;
2447
2448                 /* Okay, for some reason the above doesn't work with some
2449                  * switches (like HP ProCurve). If the above doesn't work,
2450                  * check the MAC directly to see if we have a link.  Perhaps we
2451                  * should always check the MAC instead probing the MII.
2452                  */
2453                 if (!new_link_state && !old_link_state) {
2454                         emac_status = REG_RD(bp, BNX2_EMAC_STATUS);
2455                         if (emac_status & BNX2_EMAC_STATUS_LINK_CHANGE) {
2456                                 /* Acknowledge the link change */
2457                                 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
2458                         } else if (emac_status & BNX2_EMAC_STATUS_LINK) {
2459                                 new_link_state = !old_link_state;
2460                         }
2461                 }
2462
2463         }
2464
2465         if (new_link_state != old_link_state) {
2466                 if (new_link_state) {
2467                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD,
2468                                 STATUS_ATTN_BITS_LINK_STATE);
2469                 }
2470                 else {
2471                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD,
2472                                 STATUS_ATTN_BITS_LINK_STATE);
2473                 }
2474
2475                 bnx2_set_link(bp);
2476
2477                 /* This is needed to take care of transient status
2478                  * during link changes.
2479                  */
2480
2481                 REG_WR(bp, BNX2_HC_COMMAND,
2482                        bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
2483                 REG_RD(bp, BNX2_HC_COMMAND);
2484
2485         }
2486
2487         return bp->link_up;
2488 }
2489
2490 static int
2491 bnx2_poll(struct nic* nic, int retrieve)
2492 {
2493         struct bnx2 *bp = &bnx2;
2494         struct rx_bd *cons_bd, *prod_bd;
2495         u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
2496         struct l2_fhdr *rx_hdr;
2497         int result = 0;
2498         unsigned int len;
2499         unsigned char *data;
2500         u32 status;
2501         
2502 #if 0
2503         if ((bp->status_blk->status_idx == bp->last_status_idx) &&
2504             (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
2505              BNX2_PCICFG_MISC_STATUS_INTA_VALUE)) {
2506
2507                 bp->last_status_idx = bp->status_blk->status_idx;
2508                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2509                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2510                BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
2511                bp->last_status_idx);
2512                 return 0;
2513         }
2514 #endif
2515
2516         if ((bp->status_blk->status_rx_quick_consumer_index0 != bp->rx_cons) && !retrieve)
2517                 return 1;
2518
2519         if (bp->status_blk->status_rx_quick_consumer_index0 != bp->rx_cons) {
2520
2521                 hw_cons = bp->hw_rx_cons = bp->status_blk->status_rx_quick_consumer_index0;
2522                 if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT) {
2523                         hw_cons++;
2524                 }
2525                 sw_cons = bp->rx_cons;
2526                 sw_prod = bp->rx_prod;
2527
2528                 rmb();
2529                 if (sw_cons != hw_cons) {
2530
2531                         sw_ring_cons = RX_RING_IDX(sw_cons);
2532                         sw_ring_prod = RX_RING_IDX(sw_prod);
2533
2534                         data = bus_to_virt(bp->rx_desc_ring[sw_ring_cons].rx_bd_haddr_lo);
2535
2536                         rx_hdr = (struct l2_fhdr *)data;
2537                         len = rx_hdr->l2_fhdr_pkt_len - 4;
2538                         if ((len > (ETH_MAX_MTU + ETH_HLEN)) ||
2539                                 ((status = rx_hdr->l2_fhdr_status) &
2540                                 (L2_FHDR_ERRORS_BAD_CRC |
2541                                 L2_FHDR_ERRORS_PHY_DECODE |
2542                                 L2_FHDR_ERRORS_ALIGNMENT |
2543                                 L2_FHDR_ERRORS_TOO_SHORT |
2544                                 L2_FHDR_ERRORS_GIANT_FRAME))) {
2545                                 result = 0;
2546                         }
2547                         else
2548                         {
2549                                 nic->packetlen = len;
2550                                 memcpy(nic->packet, data + bp->rx_offset, len);
2551                                 result = 1;
2552                         }
2553
2554                         /* Reuse the buffer */
2555                         bp->rx_prod_bseq += bp->rx_buf_use_size;
2556                         if (sw_cons != sw_prod) {
2557                                 cons_bd = &bp->rx_desc_ring[sw_ring_cons];
2558                                 prod_bd = &bp->rx_desc_ring[sw_ring_prod];
2559                                 prod_bd->rx_bd_haddr_hi = 0; /* Etherboot runs under 4GB */
2560                                 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2561                         }
2562
2563                         sw_cons = NEXT_RX_BD(sw_cons);
2564                         sw_prod = NEXT_RX_BD(sw_prod);
2565
2566                 }
2567
2568                 bp->rx_cons = sw_cons;
2569                 bp->rx_prod = sw_prod;
2570
2571                 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, bp->rx_prod);
2572
2573                 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
2574
2575                 wmb();
2576
2577         }
2578
2579         bnx2_poll_link(bp);
2580
2581 #if 0
2582         bp->last_status_idx = bp->status_blk->status_idx;
2583         rmb();
2584
2585         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2586                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2587                BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
2588                bp->last_status_idx);
2589
2590         REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
2591 #endif
2592
2593         return result;
2594 }
2595
2596 static void
2597 bnx2_irq(struct nic *nic __unused, irq_action_t action __unused)
2598 {
2599         switch ( action ) {
2600                 case DISABLE: break;
2601                 case ENABLE: break;
2602                 case FORCE: break;
2603         }
2604 }
2605
2606 static struct nic_operations bnx2_operations = {
2607         .connect        = dummy_connect,
2608         .poll           = bnx2_poll,
2609         .transmit       = bnx2_transmit,
2610         .irq            = bnx2_irq,
2611 };
2612
2613 static int
2614 bnx2_probe(struct nic *nic, struct pci_device *pdev)
2615 {
2616         struct bnx2 *bp = &bnx2;
2617         int i, rc;
2618
2619         if (pdev == 0)
2620                 return 0;
2621
2622         memset(bp, 0, sizeof(*bp));
2623
2624         rc = bnx2_init_board(pdev, nic);
2625         if (rc < 0) {
2626                 return 0;
2627         }
2628
2629         /*
2630         nic->disable = bnx2_disable;
2631         nic->transmit = bnx2_transmit;
2632         nic->poll = bnx2_poll;
2633         nic->irq = bnx2_irq;
2634         */
2635         
2636         nic->nic_op     = &bnx2_operations;
2637
2638         memcpy(nic->node_addr, bp->mac_addr, ETH_ALEN);
2639         printf("Ethernet addr: %s\n", eth_ntoa( nic->node_addr ) );
2640         printf("Broadcom NetXtreme II (%c%d) PCI%s %s %dMHz\n",
2641                 (int) ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
2642                 (int) ((CHIP_ID(bp) & 0x0ff0) >> 4),
2643                 ((bp->flags & PCIX_FLAG) ? "-X" : ""),
2644                 ((bp->flags & PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
2645                 bp->bus_speed_mhz);
2646
2647         bnx2_set_power_state_0(bp);
2648         bnx2_disable_int(bp);
2649
2650         bnx2_alloc_mem(bp);
2651
2652         rc = bnx2_init_nic(bp);
2653         if (rc) {
2654                 return 0;
2655         }
2656
2657         bnx2_poll_link(bp);
2658         for(i = 0; !bp->link_up && (i < VALID_LINK_TIMEOUT*100); i++) {
2659                 mdelay(1);
2660                 bnx2_poll_link(bp);
2661         }
2662 #if 1
2663         if (!bp->link_up){
2664                 printf("Valid link not established\n");
2665                 goto err_out_disable;
2666         }
2667 #endif
2668         
2669         return 1;
2670
2671 err_out_disable:
2672         bnx2_disable(nic);
2673         return 0;
2674 }
2675
2676 static struct pci_device_id bnx2_nics[] = {
2677         PCI_ROM(0x14e4, 0x164a, "bnx2-5706",        "Broadcom NetXtreme II BCM5706"),
2678         PCI_ROM(0x14e4, 0x164c, "bnx2-5708",        "Broadcom NetXtreme II BCM5708"),
2679         PCI_ROM(0x14e4, 0x16aa, "bnx2-5706S",       "Broadcom NetXtreme II BCM5706S"),
2680         PCI_ROM(0x14e4, 0x16ac, "bnx2-5708S",       "Broadcom NetXtreme II BCM5708S"),
2681 };
2682
2683 PCI_DRIVER ( bnx2_driver, bnx2_nics, PCI_NO_CLASS );
2684
2685 DRIVER ( "BNX2", nic_driver, pci_driver, bnx2_driver, bnx2_probe, bnx2_disable );
2686
2687 /*
2688 static struct pci_driver bnx2_driver __pci_driver = {
2689         .type     = NIC_DRIVER,
2690         .name     = "BNX2",              
2691         .probe    = bnx2_probe,
2692         .ids      = bnx2_nics,                  
2693         .id_count = sizeof(bnx2_nics)/sizeof(bnx2_nics[0]), 
2694         .class    = 0,    
2695 };
2696 */