i86: correct and clean up the sign- and zero-extend patterns.
authorH. Peter Anvin <hpa@zytor.com>
Mon, 13 Aug 2007 20:54:19 +0000 (13:54 -0700)
committerH. Peter Anvin <hpa@zytor.com>
Mon, 13 Aug 2007 21:03:27 +0000 (14:03 -0700)
Use cwde instead of cwd since we now use 32-bit registers;
use alternatives instead of an expand, and provide SI->QI
patterns.

gcc/config/i86/i86.md

index fecbd95..e4c9e1b 100644 (file)
 ;;
 ;; sign extension
 ;;
-
-
-(define_expand "extendqihi2"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "")
-       (sign_extend:HI
-         (match_operand:QI 1 "general_operand" "")))]
-  ""
-  "
-{
-  /* Don't generate memory->memory moves, go through a register */
-  if ((reload_in_progress | reload_completed) == 0
-      && GET_CODE (operands[0]) == MEM
-      && GET_CODE (operands[1]) == MEM)
-    {
-      operands[1] = force_reg (QImode, operands[1]);
-    }
-}
-  "
-  )
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=a")
+(define_insn "extendqihi2"
+  [(set (match_operand:HI 0 "register_operand" "=a,r")
        (sign_extend:HI
-         (match_operand:QI 1 "register_operand" "0")))]
-  ""
-  "cbw"
-  )
-
-(define_insn ""
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
-    (sign_extend:HI
-      (match_operand:QI 1 "nonimmediate_operand" "r,rm")))]
+         (match_operand:QI 1 "nonimmediate_operand" "0,qm")))]
   ""
-  "movsx       %0,%1")
+  "@
+   cbw
+   movsx       %0,%1")
 
-(define_expand "extendhisi2"
-  [(set (match_operand:SI 0 "general_operand" "")
+(define_insn "extendhisi2"
+  [(set (match_operand:SI 0 "register_operand" "=a,r")
     (sign_extend:SI
-      (match_operand:HI 1 "general_operand" "")))]
+      (match_operand:HI 1 "nonimmediate_operand" "0,rm")))]
   ""
-  "
-{
-  /* Don't generate memory->memory moves, go through a register */
-  if ((reload_in_progress | reload_completed) == 0
-      && GET_CODE (operands[0]) == MEM
-      && GET_CODE (operands[1]) == MEM)
-    {
-      operands[1] = force_reg (HImode, operands[1]);
-    }
-}
-  "
-  )
+  "@
+   cwde
+   movsx       %0,%1")
 
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=a")
+(define_insn "extendqisi2"
+  [(set (match_operand:SI 0 "register_operand" "=r")
     (sign_extend:SI
-      (match_operand:HI 1 "register_operand" "0")))]
-  ""
-  "cwd"
-  )
-
-(define_insn ""
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
-    (sign_extend:SI
-      (match_operand:HI 1 "general_operand" "r,rm")))]
+      (match_operand:QI 1 "nonimmediate_operand" "qm")))]
   ""
   "movsx       %0,%1")
 
 
-
 ;;
 ;; zero extension
 ;;
-
-
-(define_expand "zero_extendqihi2"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "")
-       (zero_extend:HI
-         (match_operand:QI 1 "general_operand" "")))]
-  ""
-  "
-{
-  /* Don't generate memory->memory moves, go through a register */
-  if ((reload_in_progress | reload_completed) == 0
-      && GET_CODE (operands[0]) == MEM
-      && GET_CODE (operands[1]) == MEM)
-    {
-      operands[1] = force_reg (QImode, operands[1]);
-    }
-}
-  "
-  )
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=q")
-       (zero_extend:HI
-         (match_operand:QI 1 "register_operand" "0")))]
-  ""
-  "xor %H0,%H0"
-  )
-
-(define_insn ""
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m")
+(define_insn "zero_extendqihi2"
+  [(set (match_operand:HI 0 "register_operand" "=q,r,!r")
     (zero_extend:HI
-      (match_operand:QI 1 "general_operand" "r,m,r")))]
+      (match_operand:QI 1 "nonimmediate_operand" "0,qm,0")))]
   ""
-  "movzx       %0,%1")
+  "@
+   xor %H0,%H0
+   movzx       %0,%1
+   and %0,0xff")
 
-(define_expand "zero_extendhisi2"
-  [(set (match_operand:SI 0 "general_operand" "")
+(define_insn "zero_extendhisi2"
+  [(set (match_operand:SI 0 "register_operand" "=r")
     (zero_extend:SI
-      (match_operand:HI 1 "general_operand" "")))]
+      (match_operand:HI 1 "nonimmediate_operand" "rm")))]
   ""
-  "
-{
-  /* Don't generate memory->memory moves, go through a register */
-  if ((reload_in_progress | reload_completed) == 0
-      && GET_CODE (operands[0]) == MEM
-      && GET_CODE (operands[1]) == MEM)
-    {
-      operands[1] = force_reg (HImode, operands[1]);
-    }
-}
-  "
-  )
+  "movzx       %0,%1")
 
-(define_insn ""
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
+(define_insn "zero_extendqisi2"
+  [(set (match_operand:SI 0 "register_operand" "=r,!r")
     (zero_extend:SI
-      (match_operand:HI 1 "general_operand" "r,rm")))]
+      (match_operand:QI 1 "nonimmediate_operand" "qm,0")))]
   ""
-  "movzx       %0,%1")
+  "@
+   movzx       %0,%1
+   and         %0,0xff")
 
 ;; lea instructions
 ;;