[e1000e] Add e1000e driver
authorMarty Connor <mdc@etherboot.org>
Wed, 17 Mar 2010 07:18:46 +0000 (03:18 -0400)
committerMarty Connor <mdc@etherboot.org>
Wed, 17 Mar 2010 07:18:46 +0000 (03:18 -0400)
This commit adds an e1000e driver based on Intel source code
available at:

    http://sourceforge.net/projects/e1000/

which is upstream source for the Linux kernel e1000 drivers, and
should support many PCIe e1000 variants.

Signed-off-by: Marty Connor <mdc@etherboot.org>
22 files changed:
src/Makefile
src/drivers/net/e1000e/e1000e.c [new file with mode: 0644]
src/drivers/net/e1000e/e1000e.h [new file with mode: 0644]
src/drivers/net/e1000e/e1000e_80003es2lan.c [new file with mode: 0644]
src/drivers/net/e1000e/e1000e_80003es2lan.h [new file with mode: 0644]
src/drivers/net/e1000e/e1000e_82571.c [new file with mode: 0644]
src/drivers/net/e1000e/e1000e_82571.h [new file with mode: 0644]
src/drivers/net/e1000e/e1000e_defines.h [new file with mode: 0644]
src/drivers/net/e1000e/e1000e_hw.h [new file with mode: 0644]
src/drivers/net/e1000e/e1000e_ich8lan.c [new file with mode: 0644]
src/drivers/net/e1000e/e1000e_ich8lan.h [new file with mode: 0644]
src/drivers/net/e1000e/e1000e_mac.c [new file with mode: 0644]
src/drivers/net/e1000e/e1000e_mac.h [new file with mode: 0644]
src/drivers/net/e1000e/e1000e_main.c [new file with mode: 0644]
src/drivers/net/e1000e/e1000e_manage.c [new file with mode: 0644]
src/drivers/net/e1000e/e1000e_manage.h [new file with mode: 0644]
src/drivers/net/e1000e/e1000e_nvm.c [new file with mode: 0644]
src/drivers/net/e1000e/e1000e_nvm.h [new file with mode: 0644]
src/drivers/net/e1000e/e1000e_phy.c [new file with mode: 0644]
src/drivers/net/e1000e/e1000e_phy.h [new file with mode: 0644]
src/drivers/net/e1000e/e1000e_regs.h [new file with mode: 0644]
src/include/gpxe/errfile.h

index ff5cb7d..49844eb 100644 (file)
@@ -59,6 +59,7 @@ SRCDIRS               += image
 SRCDIRS                += drivers/bus
 SRCDIRS                += drivers/net
 SRCDIRS                += drivers/net/e1000
+SRCDIRS                += drivers/net/e1000e
 SRCDIRS                += drivers/net/phantom
 SRCDIRS                += drivers/net/rtl818x
 SRCDIRS                += drivers/net/ath5k
diff --git a/src/drivers/net/e1000e/e1000e.c b/src/drivers/net/e1000e/e1000e.c
new file mode 100644 (file)
index 0000000..b7318b7
--- /dev/null
@@ -0,0 +1,34 @@
+/*******************************************************************************
+
+  Intel PRO/1000 Linux driver
+  Copyright(c) 1999 - 2008 Intel Corporation.
+
+  This program is free software; you can redistribute it and/or modify it
+  under the terms and conditions of the GNU General Public License,
+  version 2, as published by the Free Software Foundation.
+
+  This program is distributed in the hope it will be useful, but WITHOUT
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+  more details.
+
+  You should have received a copy of the GNU General Public License along with
+  this program; if not, write to the Free Software Foundation, Inc.,
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+
+  The full GNU General Public License is included in this distribution in
+  the file called "COPYING".
+
+  Contact Information:
+  Linux NICS <linux.nics@intel.com>
+  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+
+*******************************************************************************/
+
+FILE_LICENCE ( GPL2_ONLY );
+
+REQUIRE_OBJECT(e1000e_main);
+REQUIRE_OBJECT(e1000e_80003es2lan);
+REQUIRE_OBJECT(e1000e_82571);
+REQUIRE_OBJECT(e1000e_ich8lan);
diff --git a/src/drivers/net/e1000e/e1000e.h b/src/drivers/net/e1000e/e1000e.h
new file mode 100644 (file)
index 0000000..c057350
--- /dev/null
@@ -0,0 +1,533 @@
+/*******************************************************************************
+
+  Intel PRO/1000 Linux driver
+  Copyright(c) 1999 - 2009 Intel Corporation.
+
+  This program is free software; you can redistribute it and/or modify it
+  under the terms and conditions of the GNU General Public License,
+  version 2, as published by the Free Software Foundation.
+
+  This program is distributed in the hope it will be useful, but WITHOUT
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+  more details.
+
+  You should have received a copy of the GNU General Public License along with
+  this program; if not, write to the Free Software Foundation, Inc.,
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+
+  The full GNU General Public License is included in this distribution in
+  the file called "COPYING".
+
+  Contact Information:
+  Linux NICS <linux.nics@intel.com>
+  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+
+*******************************************************************************/
+
+FILE_LICENCE ( GPL2_OR_LATER );
+
+/* Linux PRO/1000 Ethernet Driver main header file */
+
+#ifndef _E1000E_H_
+#define _E1000E_H_
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <unistd.h>
+#include <gpxe/io.h>
+#include <errno.h>
+#include <byteswap.h>
+#include <gpxe/pci.h>
+#include <gpxe/malloc.h>
+#include <gpxe/if_ether.h>
+#include <gpxe/ethernet.h>
+#include <gpxe/iobuf.h>
+#include <gpxe/netdevice.h>
+
+/* Begin OS Dependencies */
+
+#define u8         unsigned char
+#define bool       boolean_t
+#define dma_addr_t unsigned long
+#define __le16     uint16_t
+#define __le32     uint32_t
+#define __le64     uint64_t
+
+#define __iomem
+
+#define msleep(x) mdelay(x)
+
+#define ETH_FCS_LEN 4
+
+typedef int spinlock_t;
+typedef enum {
+    false = 0,
+    true = 1
+} boolean_t;
+
+/* End OS Dependencies */
+
+#include "e1000e_hw.h"
+
+#define E1000_TX_FLAGS_CSUM            0x00000001
+#define E1000_TX_FLAGS_VLAN            0x00000002
+#define E1000_TX_FLAGS_TSO             0x00000004
+#define E1000_TX_FLAGS_IPV4            0x00000008
+#define E1000_TX_FLAGS_VLAN_MASK       0xffff0000
+#define E1000_TX_FLAGS_VLAN_SHIFT      16
+
+#define E1000_MAX_PER_TXD      8192
+#define E1000_MAX_TXD_PWR      12
+
+#define MINIMUM_DHCP_PACKET_SIZE 282
+
+struct e1000_info;
+
+#define e_dbg(arg...) if (0) { printf (arg); };
+
+#ifdef CONFIG_E1000E_MSIX
+/* Interrupt modes, as used by the IntMode paramter */
+#define E1000E_INT_MODE_LEGACY         0
+#define E1000E_INT_MODE_MSI            1
+#define E1000E_INT_MODE_MSIX           2
+
+#endif /* CONFIG_E1000E_MSIX */
+#ifndef CONFIG_E1000E_NAPI
+#define E1000_MAX_INTR 10
+
+#endif /* CONFIG_E1000E_NAPI */
+/* Tx/Rx descriptor defines */
+#define E1000_DEFAULT_TXD              256
+#define E1000_MAX_TXD                  4096
+#define E1000_MIN_TXD                  64
+
+#define E1000_DEFAULT_RXD              256
+#define E1000_MAX_RXD                  4096
+#define E1000_MIN_RXD                  64
+
+#define E1000_MIN_ITR_USECS            10 /* 100000 irq/sec */
+#define E1000_MAX_ITR_USECS            10000 /* 100    irq/sec */
+
+/* Early Receive defines */
+#define E1000_ERT_2048                 0x100
+
+#define E1000_FC_PAUSE_TIME            0x0680 /* 858 usec */
+
+/* How many Tx Descriptors do we need to call netif_wake_queue ? */
+/* How many Rx Buffers do we bundle into one write to the hardware ? */
+#define E1000_RX_BUFFER_WRITE          16 /* Must be power of 2 */
+
+#define AUTO_ALL_MODES                 0
+#define E1000_EEPROM_APME              0x0400
+
+#define E1000_MNG_VLAN_NONE            (-1)
+
+/* Number of packet split data buffers (not including the header buffer) */
+#define PS_PAGE_BUFFERS                        (MAX_PS_BUFFERS - 1)
+
+#define MAXIMUM_ETHERNET_VLAN_SIZE     1522
+
+#define DEFAULT_JUMBO                  9234
+
+enum e1000_boards {
+       board_82571,
+       board_82572,
+       board_82573,
+       board_82574,
+       board_80003es2lan,
+       board_ich8lan,
+       board_ich9lan,
+       board_ich10lan,
+       board_pchlan,
+       board_82583,
+};
+
+/* board specific private data structure */
+struct e1000_adapter {
+       const struct e1000_info *ei;
+
+       /* OS defined structs */
+       struct net_device *netdev;
+       struct pci_device *pdev;
+       struct net_device_stats net_stats;
+
+       /* structs defined in e1000_hw.h */
+       struct e1000_hw hw;
+
+       struct e1000_phy_info phy_info;
+
+       u32 wol;
+       u32 pba;
+       u32 max_hw_frame_size;
+
+       bool fc_autoneg;
+
+       unsigned int flags;
+       unsigned int flags2;
+
+#define NUM_TX_DESC    8
+#define NUM_RX_DESC    8
+
+       struct io_buffer *tx_iobuf[NUM_TX_DESC];
+       struct io_buffer *rx_iobuf[NUM_RX_DESC];
+
+       struct e1000_tx_desc *tx_base;
+       struct e1000_rx_desc *rx_base;
+
+       uint32_t tx_ring_size;
+       uint32_t rx_ring_size;
+
+       uint32_t tx_head;
+       uint32_t tx_tail;
+       uint32_t tx_fill_ctr;
+
+       uint32_t rx_curr;
+
+       uint32_t ioaddr;
+       uint32_t irqno;
+
+        uint32_t tx_int_delay;
+        uint32_t tx_abs_int_delay;
+        uint32_t txd_cmd;
+};
+
+struct e1000_info {
+       enum e1000_mac_type     mac;
+       unsigned int            flags;
+       unsigned int            flags2;
+       u32                     pba;
+       u32                     max_hw_frame_size;
+       s32                     (*get_variants)(struct e1000_adapter *);
+       void                    (*init_ops)(struct e1000_hw *);
+};
+
+/* hardware capability, feature, and workaround flags */
+#define FLAG_HAS_AMT                      (1 << 0)
+#define FLAG_HAS_FLASH                    (1 << 1)
+#define FLAG_HAS_HW_VLAN_FILTER           (1 << 2)
+#define FLAG_HAS_WOL                      (1 << 3)
+#define FLAG_HAS_ERT                      (1 << 4)
+#define FLAG_HAS_CTRLEXT_ON_LOAD          (1 << 5)
+#define FLAG_HAS_SWSM_ON_LOAD             (1 << 6)
+#define FLAG_HAS_JUMBO_FRAMES             (1 << 7)
+#define FLAG_IS_ICH                       (1 << 9)
+#ifdef CONFIG_E1000E_MSIX
+#define FLAG_HAS_MSIX                     (1 << 10)
+#endif
+#define FLAG_HAS_SMART_POWER_DOWN         (1 << 11)
+#define FLAG_IS_QUAD_PORT_A               (1 << 12)
+#define FLAG_IS_QUAD_PORT                 (1 << 13)
+#define FLAG_TIPG_MEDIUM_FOR_80003ESLAN   (1 << 14)
+#define FLAG_APME_IN_WUC                  (1 << 15)
+#define FLAG_APME_IN_CTRL3                (1 << 16)
+#define FLAG_APME_CHECK_PORT_B            (1 << 17)
+#define FLAG_DISABLE_FC_PAUSE_TIME        (1 << 18)
+#define FLAG_NO_WAKE_UCAST                (1 << 19)
+#define FLAG_MNG_PT_ENABLED               (1 << 20)
+#define FLAG_RESET_OVERWRITES_LAA         (1 << 21)
+#define FLAG_TARC_SPEED_MODE_BIT          (1 << 22)
+#define FLAG_TARC_SET_BIT_ZERO            (1 << 23)
+#define FLAG_RX_NEEDS_RESTART             (1 << 24)
+#define FLAG_LSC_GIG_SPEED_DROP           (1 << 25)
+#define FLAG_SMART_POWER_DOWN             (1 << 26)
+#define FLAG_MSI_ENABLED                  (1 << 27)
+#define FLAG_RX_CSUM_ENABLED              (1 << 28)
+#define FLAG_TSO_FORCE                    (1 << 29)
+#define FLAG_RX_RESTART_NOW               (1 << 30)
+#define FLAG_MSI_TEST_FAILED              (1 << 31)
+
+/* CRC Stripping defines */
+#define FLAG2_CRC_STRIPPING               (1 << 0)
+#define FLAG2_HAS_PHY_WAKEUP              (1 << 1)
+
+#define E1000_RX_DESC_PS(R, i)     \
+       (&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
+#define E1000_GET_DESC(R, i, type)     (&(((struct type *)((R).desc))[i]))
+#define E1000_RX_DESC(R, i)            E1000_GET_DESC(R, i, e1000_rx_desc)
+#define E1000_TX_DESC(R, i)            E1000_GET_DESC(R, i, e1000_tx_desc)
+#define E1000_CONTEXT_DESC(R, i)       E1000_GET_DESC(R, i, e1000_context_desc)
+
+enum e1000_state_t {
+       __E1000E_TESTING,
+       __E1000E_RESETTING,
+       __E1000E_DOWN
+};
+
+enum latency_range {
+       lowest_latency = 0,
+       low_latency = 1,
+       bulk_latency = 2,
+       latency_invalid = 255
+};
+
+extern void e1000e_check_options(struct e1000_adapter *adapter);
+
+extern void e1000e_reset(struct e1000_adapter *adapter);
+extern void e1000e_power_up_phy(struct e1000_adapter *adapter);
+
+extern void e1000e_init_function_pointers_82571(struct e1000_hw *hw)
+                                               __attribute__((weak));
+extern void e1000e_init_function_pointers_80003es2lan(struct e1000_hw *hw)
+                                               __attribute__((weak));
+extern void e1000e_init_function_pointers_ich8lan(struct e1000_hw *hw)
+                                               __attribute__((weak));
+
+extern int e1000e_probe(struct pci_device *pdev,
+                      const struct pci_device_id *id __unused);
+
+extern void e1000e_remove(struct pci_device *pdev);
+
+extern s32 e1000e_read_pba_num(struct e1000_hw *hw, u32 *pba_num);
+
+static inline s32 e1000e_commit_phy(struct e1000_hw *hw)
+{
+       if (hw->phy.ops.commit)
+               return hw->phy.ops.commit(hw);
+
+       return 0;
+}
+
+extern bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw);
+
+extern bool e1000e_get_laa_state_82571(struct e1000_hw *hw);
+extern void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state);
+
+extern void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
+                                                bool state);
+extern void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
+extern void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
+extern void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw);
+
+extern s32 e1000e_check_for_copper_link(struct e1000_hw *hw);
+extern s32 e1000e_check_for_fiber_link(struct e1000_hw *hw);
+extern s32 e1000e_check_for_serdes_link(struct e1000_hw *hw);
+extern s32 e1000e_cleanup_led_generic(struct e1000_hw *hw);
+extern s32 e1000e_led_on_generic(struct e1000_hw *hw);
+extern s32 e1000e_led_off_generic(struct e1000_hw *hw);
+extern s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw);
+extern s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex);
+extern s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex);
+extern s32 e1000e_disable_pcie_master(struct e1000_hw *hw);
+extern s32 e1000e_get_auto_rd_done(struct e1000_hw *hw);
+extern s32 e1000e_id_led_init(struct e1000_hw *hw);
+extern void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw);
+extern s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw);
+extern s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw);
+extern s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw);
+extern s32 e1000e_setup_link(struct e1000_hw *hw);
+static inline void e1000e_clear_vfta(struct e1000_hw *hw)
+{
+       hw->mac.ops.clear_vfta(hw);
+}
+extern void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count);
+extern void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
+                                              u8 *mc_addr_list,
+                                              u32 mc_addr_count);
+extern void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index);
+extern s32 e1000e_set_fc_watermarks(struct e1000_hw *hw);
+extern void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop);
+extern s32 e1000e_get_hw_semaphore(struct e1000_hw *hw);
+extern s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data);
+extern void e1000e_config_collision_dist(struct e1000_hw *hw);
+extern s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw);
+extern s32 e1000e_force_mac_fc(struct e1000_hw *hw);
+extern s32 e1000e_blink_led(struct e1000_hw *hw);
+extern void e1000e_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value);
+static inline void e1000e_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
+{
+       if (hw->mac.ops.write_vfta)
+               hw->mac.ops.write_vfta(hw, offset, value);
+}
+extern void e1000e_reset_adaptive(struct e1000_hw *hw);
+extern void e1000e_update_adaptive(struct e1000_hw *hw);
+
+extern s32 e1000e_setup_copper_link(struct e1000_hw *hw);
+extern void e1000e_put_hw_semaphore(struct e1000_hw *hw);
+extern s32 e1000e_check_reset_block_generic(struct e1000_hw *hw);
+#if 0
+extern s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw);
+#endif
+#if 0
+extern s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw);
+#endif
+extern s32 e1000e_get_phy_info_igp(struct e1000_hw *hw);
+extern s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
+extern s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw);
+extern s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active);
+extern s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
+extern s32 e1000e_phy_sw_reset(struct e1000_hw *hw);
+#if 0
+extern s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw);
+#endif
+extern s32 e1000e_get_cfg_done(struct e1000_hw *hw);
+#if 0
+extern s32 e1000e_get_cable_length_m88(struct e1000_hw *hw);
+#endif
+extern s32 e1000e_get_phy_info_m88(struct e1000_hw *hw);
+extern s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
+extern s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
+extern enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id);
+extern s32 e1000e_determine_phy_address(struct e1000_hw *hw);
+extern s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);
+extern s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data);
+#if 0
+extern void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
+#endif
+extern s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data);
+extern s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data);
+extern s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
+                              u32 usec_interval, bool *success);
+extern s32 e1000e_phy_reset_dsp(struct e1000_hw *hw);
+extern s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
+extern s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
+extern s32 e1000e_check_downshift(struct e1000_hw *hw);
+
+static inline s32 e1000e_phy_hw_reset(struct e1000_hw *hw)
+{
+       if (hw->phy.ops.reset)
+               return hw->phy.ops.reset(hw);
+
+       return 0;
+}
+
+static inline s32 e1000e_check_reset_block(struct e1000_hw *hw)
+{
+       if (hw->phy.ops.check_reset_block)
+               return hw->phy.ops.check_reset_block(hw);
+
+       return 0;
+}
+
+static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data)
+{
+       if (hw->phy.ops.read_reg)
+               return hw->phy.ops.read_reg(hw, offset, data);
+
+       return 0;
+}
+
+static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data)
+{
+       if (hw->phy.ops.write_reg)
+               return hw->phy.ops.write_reg(hw, offset, data);
+
+       return 0;
+}
+
+#if 0
+static inline s32 e1000e_get_cable_length(struct e1000_hw *hw)
+{
+       if (hw->phy.ops.get_cable_length)
+               return hw->phy.ops.get_cable_length(hw);
+
+       return 0;
+}
+#endif
+
+extern s32 e1000e_acquire_nvm(struct e1000_hw *hw);
+extern s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
+extern s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw);
+extern s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg);
+extern s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
+extern s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw);
+extern void e1000e_release_nvm(struct e1000_hw *hw);
+
+static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw)
+{
+       if (hw->mac.ops.read_mac_addr)
+               return hw->mac.ops.read_mac_addr(hw);
+
+       return e1000e_read_mac_addr_generic(hw);
+}
+
+static inline s32 e1000e_validate_nvm_checksum(struct e1000_hw *hw)
+{
+       return hw->nvm.ops.validate(hw);
+}
+
+static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw)
+{
+       return hw->nvm.ops.update(hw);
+}
+
+static inline s32 e1000e_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
+{
+       return hw->nvm.ops.read(hw, offset, words, data);
+}
+
+static inline s32 e1000e_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
+{
+       return hw->nvm.ops.write(hw, offset, words, data);
+}
+
+static inline s32 e1000e_get_phy_info(struct e1000_hw *hw)
+{
+       if (hw->phy.ops.get_info)
+               return hw->phy.ops.get_info(hw);
+
+       return 0;
+}
+
+extern bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw);
+#if 0
+extern s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length);
+#endif
+
+static inline u32 __er32(struct e1000_hw *hw, unsigned long reg)
+{
+       return readl(hw->hw_addr + reg);
+}
+
+static inline void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)
+{
+       writel(val, hw->hw_addr + reg);
+}
+
+#define er32(reg)      __er32(hw, E1000_##reg)
+#define ew32(reg, val) __ew32(hw, E1000_##reg, (val))
+#define e1e_flush()    er32(STATUS)
+
+#define E1000_WRITE_REG(a, reg, value)  \
+    writel((value), ((a)->hw_addr + reg))
+
+#define E1000_READ_REG(a, reg) (readl((a)->hw_addr + reg))
+
+#define E1000_WRITE_REG_ARRAY(a, reg, offset, value)  \
+    writel((value), ((a)->hw_addr + reg + ((offset) << 2)))
+
+#define E1000_READ_REG_ARRAY(a, reg, offset) ( \
+    readl((a)->hw_addr + reg + ((offset) << 2)))
+
+#define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY
+#define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY
+
+static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
+{
+       return readw(hw->flash_address + reg);
+}
+
+static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
+{
+       return readl(hw->flash_address + reg);
+}
+
+static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
+{
+       writew(val, hw->flash_address + reg);
+}
+
+static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
+{
+       writel(val, hw->flash_address + reg);
+}
+
+#define er16flash(reg)         __er16flash(hw, (reg))
+#define er32flash(reg)         __er32flash(hw, (reg))
+#define ew16flash(reg, val)    __ew16flash(hw, (reg), (val))
+#define ew32flash(reg, val)    __ew32flash(hw, (reg), (val))
+
+#endif /* _E1000E_H_ */
diff --git a/src/drivers/net/e1000e/e1000e_80003es2lan.c b/src/drivers/net/e1000e/e1000e_80003es2lan.c
new file mode 100644 (file)
index 0000000..a9ebc77
--- /dev/null
@@ -0,0 +1,1533 @@
+/*******************************************************************************
+
+  Intel PRO/1000 Linux driver
+  Copyright(c) 1999 - 2009 Intel Corporation.
+
+  This program is free software; you can redistribute it and/or modify it
+  under the terms and conditions of the GNU General Public License,
+  version 2, as published by the Free Software Foundation.
+
+  This program is distributed in the hope it will be useful, but WITHOUT
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+  more details.
+
+  You should have received a copy of the GNU General Public License along with
+  this program; if not, write to the Free Software Foundation, Inc.,
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+
+  The full GNU General Public License is included in this distribution in
+  the file called "COPYING".
+
+  Contact Information:
+  Linux NICS <linux.nics@intel.com>
+  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+
+*******************************************************************************/
+
+FILE_LICENCE ( GPL2_OR_LATER );
+
+/*
+ * 80003ES2LAN Gigabit Ethernet Controller (Copper)
+ * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
+ */
+
+#include "e1000e.h"
+
+static s32  e1000e_init_phy_params_80003es2lan(struct e1000_hw *hw);
+static s32  e1000e_init_nvm_params_80003es2lan(struct e1000_hw *hw);
+static s32  e1000e_init_mac_params_80003es2lan(struct e1000_hw *hw);
+static s32  e1000e_acquire_phy_80003es2lan(struct e1000_hw *hw);
+static void e1000e_release_phy_80003es2lan(struct e1000_hw *hw);
+static s32  e1000e_acquire_nvm_80003es2lan(struct e1000_hw *hw);
+static void e1000e_release_nvm_80003es2lan(struct e1000_hw *hw);
+static s32  e1000e_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
+                                                   u32 offset,
+                                                   u16 *data);
+static s32  e1000e_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
+                                                    u32 offset,
+                                                    u16 data);
+static s32  e1000e_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
+                                        u16 words, u16 *data);
+static s32  e1000e_get_cfg_done_80003es2lan(struct e1000_hw *hw);
+#if 0
+static s32  e1000e_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw);
+#endif
+#if 0
+static s32  e1000e_get_cable_length_80003es2lan(struct e1000_hw *hw);
+#endif
+static s32  e1000e_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
+                                               u16 *duplex);
+static s32  e1000e_reset_hw_80003es2lan(struct e1000_hw *hw);
+static s32  e1000e_init_hw_80003es2lan(struct e1000_hw *hw);
+static s32  e1000e_setup_copper_link_80003es2lan(struct e1000_hw *hw);
+static void e1000e_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
+static s32  e1000e_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
+static s32  e1000e_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
+static s32  e1000e_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
+static s32  e1000e_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);
+static s32  e1000e_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
+                                            u16 *data);
+static s32  e1000e_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
+                                             u16 data);
+static s32  e1000e_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw);
+static void e1000e_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
+static void e1000e_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
+static s32  e1000e_read_mac_addr_80003es2lan(struct e1000_hw *hw);
+static void e1000e_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
+
+#if 0
+/*
+ * A table for the GG82563 cable length where the range is defined
+ * with a lower bound at "index" and the upper bound at
+ * "index + 5".
+ */
+static const u16 e1000_gg82563_cable_length_table[] =
+         { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
+#define GG82563_CABLE_LENGTH_TABLE_SIZE \
+                (sizeof(e1000_gg82563_cable_length_table) / \
+                 sizeof(e1000_gg82563_cable_length_table[0]))
+#endif
+
+/**
+ *  e1000e_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
+ *  @hw: pointer to the HW structure
+ **/
+static s32 e1000e_init_phy_params_80003es2lan(struct e1000_hw *hw)
+{
+       struct e1000_phy_info *phy = &hw->phy;
+       s32 ret_val = E1000_SUCCESS;
+
+       if (hw->phy.media_type != e1000_media_type_copper) {
+               phy->type        = e1000_phy_none;
+               goto out;
+       } else {
+               phy->ops.power_up = e1000e_power_up_phy_copper;
+               phy->ops.power_down = e1000e_power_down_phy_copper_80003es2lan;
+       }
+
+       phy->addr                = 1;
+       phy->autoneg_mask        = AUTONEG_ADVERTISE_SPEED_DEFAULT;
+       phy->reset_delay_us      = 100;
+       phy->type                = e1000_phy_gg82563;
+
+       phy->ops.acquire            = e1000e_acquire_phy_80003es2lan;
+       phy->ops.check_polarity     = e1000e_check_polarity_m88;
+       phy->ops.check_reset_block  = e1000e_check_reset_block_generic;
+       phy->ops.commit             = e1000e_phy_sw_reset;
+       phy->ops.get_cfg_done       = e1000e_get_cfg_done_80003es2lan;
+       phy->ops.get_info           = e1000e_get_phy_info_m88;
+       phy->ops.release            = e1000e_release_phy_80003es2lan;
+       phy->ops.reset              = e1000e_phy_hw_reset_generic;
+       phy->ops.set_d3_lplu_state  = e1000e_set_d3_lplu_state;
+#if 0
+       phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_80003es2lan;
+#endif
+#if 0
+       phy->ops.get_cable_length   = e1000e_get_cable_length_80003es2lan;
+#endif
+       phy->ops.read_reg           = e1000e_read_phy_reg_gg82563_80003es2lan;
+       phy->ops.write_reg          = e1000e_write_phy_reg_gg82563_80003es2lan;
+
+       phy->ops.cfg_on_link_up    = e1000e_cfg_on_link_up_80003es2lan;
+
+       /* This can only be done after all function pointers are setup. */
+       ret_val = e1000e_get_phy_id(hw);
+
+       /* Verify phy id */
+       if (phy->id != GG82563_E_PHY_ID) {
+               ret_val = -E1000_ERR_PHY;
+               goto out;
+       }
+
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000e_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
+ *  @hw: pointer to the HW structure
+ **/
+static s32 e1000e_init_nvm_params_80003es2lan(struct e1000_hw *hw)
+{
+       struct e1000_nvm_info *nvm = &hw->nvm;
+       u32 eecd = er32(EECD);
+       u16 size;
+
+       nvm->opcode_bits        = 8;
+       nvm->delay_usec         = 1;
+       switch (nvm->override) {
+       case e1000_nvm_override_spi_large:
+               nvm->page_size    = 32;
+               nvm->address_bits = 16;
+               break;
+       case e1000_nvm_override_spi_small:
+               nvm->page_size    = 8;
+               nvm->address_bits = 8;
+               break;
+       default:
+               nvm->page_size    = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
+               nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
+               break;
+       }
+
+       nvm->type               = e1000_nvm_eeprom_spi;
+
+       size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
+                         E1000_EECD_SIZE_EX_SHIFT);
+
+       /*
+        * Added to a constant, "size" becomes the left-shift value
+        * for setting word_size.
+        */
+       size += NVM_WORD_SIZE_BASE_SHIFT;
+
+       /* EEPROM access above 16k is unsupported */
+       if (size > 14)
+               size = 14;
+       nvm->word_size  = 1 << size;
+
+       /* Function Pointers */
+       nvm->ops.acquire           = e1000e_acquire_nvm_80003es2lan;
+       nvm->ops.read              = e1000e_read_nvm_eerd;
+       nvm->ops.release           = e1000e_release_nvm_80003es2lan;
+       nvm->ops.update            = e1000e_update_nvm_checksum_generic;
+       nvm->ops.valid_led_default = e1000e_valid_led_default;
+       nvm->ops.validate          = e1000e_validate_nvm_checksum_generic;
+       nvm->ops.write             = e1000e_write_nvm_80003es2lan;
+
+       return E1000_SUCCESS;
+}
+
+/**
+ *  e1000e_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
+ *  @hw: pointer to the HW structure
+ **/
+static s32 e1000e_init_mac_params_80003es2lan(struct e1000_hw *hw)
+{
+       struct e1000_mac_info *mac = &hw->mac;
+       s32 ret_val = E1000_SUCCESS;
+
+       /* Set media type */
+       switch (hw->device_id) {
+       case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
+               hw->phy.media_type = e1000_media_type_internal_serdes;
+               break;
+       default:
+               hw->phy.media_type = e1000_media_type_copper;
+               break;
+       }
+
+       /* Set mta register count */
+       mac->mta_reg_count = 128;
+       /* Set rar entry count */
+       mac->rar_entry_count = E1000_RAR_ENTRIES;
+       /* Set if part includes ASF firmware */
+       mac->asf_firmware_present = true;
+       /* Set if manageability features are enabled. */
+       mac->arc_subsystem_valid =
+               (er32(FWSM) & E1000_FWSM_MODE_MASK)
+                       ? true : false;
+
+       /* Function pointers */
+
+       /* bus type/speed/width */
+       mac->ops.get_bus_info = e1000e_get_bus_info_pcie;
+       /* reset */
+       mac->ops.reset_hw = e1000e_reset_hw_80003es2lan;
+       /* hw initialization */
+       mac->ops.init_hw = e1000e_init_hw_80003es2lan;
+       /* link setup */
+       mac->ops.setup_link = e1000e_setup_link;
+       /* physical interface link setup */
+       mac->ops.setup_physical_interface =
+               (hw->phy.media_type == e1000_media_type_copper)
+                       ? e1000e_setup_copper_link_80003es2lan
+                       : e1000e_setup_fiber_serdes_link;
+       /* check for link */
+       switch (hw->phy.media_type) {
+       case e1000_media_type_copper:
+               mac->ops.check_for_link = e1000e_check_for_copper_link;
+               break;
+       case e1000_media_type_fiber:
+               mac->ops.check_for_link = e1000e_check_for_fiber_link;
+               break;
+       case e1000_media_type_internal_serdes:
+               mac->ops.check_for_link = e1000e_check_for_serdes_link;
+               break;
+       default:
+               ret_val = -E1000_ERR_CONFIG;
+               goto out;
+               break;
+       }
+       /* check management mode */
+#if 0
+       mac->ops.check_mng_mode = e1000e_check_mng_mode_generic;
+#endif
+       /* multicast address update */
+       mac->ops.update_mc_addr_list = e1000e_update_mc_addr_list_generic;
+       /* writing VFTA */
+       mac->ops.write_vfta = e1000e_write_vfta_generic;
+       /* clearing VFTA */
+       mac->ops.clear_vfta = e1000e_clear_vfta_generic;
+       /* setting MTA */
+       mac->ops.mta_set = e1000e_mta_set_generic;
+       /* read mac address */
+       mac->ops.read_mac_addr = e1000e_read_mac_addr_80003es2lan;
+       /* ID LED init */
+       mac->ops.id_led_init = e1000e_id_led_init;
+       /* blink LED */
+       mac->ops.blink_led = e1000e_blink_led;
+       /* setup LED */
+       mac->ops.setup_led = e1000e_setup_led_generic;
+       /* cleanup LED */
+       mac->ops.cleanup_led = e1000e_cleanup_led_generic;
+       /* turn on/off LED */
+       mac->ops.led_on = e1000e_led_on_generic;
+       mac->ops.led_off = e1000e_led_off_generic;
+       /* clear hardware counters */
+       mac->ops.clear_hw_cntrs = e1000e_clear_hw_cntrs_80003es2lan;
+       /* link info */
+       mac->ops.get_link_up_info = e1000e_get_link_up_info_80003es2lan;
+
+       /* set lan id for port to determine which phy lock to use */
+       hw->mac.ops.set_lan_id(hw);
+
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000e_init_function_pointers_80003es2lan - Init ESB2 func ptrs.
+ *  @hw: pointer to the HW structure
+ *
+ *  Called to initialize all function pointers and parameters.
+ **/
+void e1000e_init_function_pointers_80003es2lan(struct e1000_hw *hw)
+{
+       e1000e_init_mac_ops_generic(hw);
+       e1000e_init_nvm_ops_generic(hw);
+       hw->mac.ops.init_params = e1000e_init_mac_params_80003es2lan;
+       hw->nvm.ops.init_params = e1000e_init_nvm_params_80003es2lan;
+       hw->phy.ops.init_params = e1000e_init_phy_params_80003es2lan;
+}
+
+/**
+ *  e1000e_acquire_phy_80003es2lan - Acquire rights to access PHY
+ *  @hw: pointer to the HW structure
+ *
+ *  A wrapper to acquire access rights to the correct PHY.
+ **/
+static s32 e1000e_acquire_phy_80003es2lan(struct e1000_hw *hw)
+{
+       u16 mask;
+
+       mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
+       return e1000e_acquire_swfw_sync_80003es2lan(hw, mask);
+}
+
+/**
+ *  e1000e_release_phy_80003es2lan - Release rights to access PHY
+ *  @hw: pointer to the HW structure
+ *
+ *  A wrapper to release access rights to the correct PHY.
+ **/
+static void e1000e_release_phy_80003es2lan(struct e1000_hw *hw)
+{
+       u16 mask;
+
+       mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
+       e1000e_release_swfw_sync_80003es2lan(hw, mask);
+}
+
+/**
+ *  e1000e_acquire_mac_csr_80003es2lan - Acquire rights to access Kumeran register
+ *  @hw: pointer to the HW structure
+ *
+ *  Acquire the semaphore to access the Kumeran interface.
+ *
+ **/
+static s32 e1000e_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
+{
+       u16 mask;
+
+       mask = E1000_SWFW_CSR_SM;
+
+       return e1000e_acquire_swfw_sync_80003es2lan(hw, mask);
+}
+
+/**
+ *  e1000e_release_mac_csr_80003es2lan - Release rights to access Kumeran Register
+ *  @hw: pointer to the HW structure
+ *
+ *  Release the semaphore used to access the Kumeran interface
+ **/
+static void e1000e_release_mac_csr_80003es2lan(struct e1000_hw *hw)
+{
+       u16 mask;
+
+       mask = E1000_SWFW_CSR_SM;
+
+       e1000e_release_swfw_sync_80003es2lan(hw, mask);
+}
+
+/**
+ *  e1000e_acquire_nvm_80003es2lan - Acquire rights to access NVM
+ *  @hw: pointer to the HW structure
+ *
+ *  Acquire the semaphore to access the EEPROM.
+ **/
+static s32 e1000e_acquire_nvm_80003es2lan(struct e1000_hw *hw)
+{
+       s32 ret_val;
+
+       ret_val = e1000e_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
+       if (ret_val)
+               goto out;
+
+       ret_val = e1000e_acquire_nvm(hw);
+
+       if (ret_val)
+               e1000e_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
+
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000e_release_nvm_80003es2lan - Relinquish rights to access NVM
+ *  @hw: pointer to the HW structure
+ *
+ *  Release the semaphore used to access the EEPROM.
+ **/
+static void e1000e_release_nvm_80003es2lan(struct e1000_hw *hw)
+{
+       e1000e_release_nvm(hw);
+       e1000e_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
+}
+
+/**
+ *  e1000e_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
+ *  @hw: pointer to the HW structure
+ *  @mask: specifies which semaphore to acquire
+ *
+ *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
+ *  will also specify which port we're acquiring the lock for.
+ **/
+static s32 e1000e_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
+{
+       u32 swfw_sync;
+       u32 swmask = mask;
+       u32 fwmask = mask << 16;
+       s32 ret_val = E1000_SUCCESS;
+       s32 i = 0, timeout = 50;
+
+       while (i < timeout) {
+               if (e1000e_get_hw_semaphore(hw)) {
+                       ret_val = -E1000_ERR_SWFW_SYNC;
+                       goto out;
+               }
+
+               swfw_sync = er32(SW_FW_SYNC);
+               if (!(swfw_sync & (fwmask | swmask)))
+                       break;
+
+               /*
+                * Firmware currently using resource (fwmask)
+                * or other software thread using resource (swmask)
+                */
+               e1000e_put_hw_semaphore(hw);
+               mdelay(5);
+               i++;
+       }
+
+       if (i == timeout) {
+               e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
+               ret_val = -E1000_ERR_SWFW_SYNC;
+               goto out;
+       }
+
+       swfw_sync |= swmask;
+       ew32(SW_FW_SYNC, swfw_sync);
+
+       e1000e_put_hw_semaphore(hw);
+
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000e_release_swfw_sync_80003es2lan - Release SW/FW semaphore
+ *  @hw: pointer to the HW structure
+ *  @mask: specifies which semaphore to acquire
+ *
+ *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
+ *  will also specify which port we're releasing the lock for.
+ **/
+static void e1000e_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
+{
+       u32 swfw_sync;
+
+       while (e1000e_get_hw_semaphore(hw) != E1000_SUCCESS)
+               ; /* Empty */
+
+       swfw_sync = er32(SW_FW_SYNC);
+       swfw_sync &= ~mask;
+       ew32(SW_FW_SYNC, swfw_sync);
+
+       e1000e_put_hw_semaphore(hw);
+}
+
+/**
+ *  e1000e_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
+ *  @hw: pointer to the HW structure
+ *  @offset: offset of the register to read
+ *  @data: pointer to the data returned from the operation
+ *
+ *  Read the GG82563 PHY register.
+ **/
+static s32 e1000e_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
+                                                  u32 offset, u16 *data)
+{
+       s32 ret_val;
+       u32 page_select;
+       u16 temp;
+
+       ret_val = e1000e_acquire_phy_80003es2lan(hw);
+       if (ret_val)
+               goto out;
+
+       /* Select Configuration Page */
+       if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
+               page_select = GG82563_PHY_PAGE_SELECT;
+       } else {
+               /*
+                * Use Alternative Page Select register to access
+                * registers 30 and 31
+                */
+               page_select = GG82563_PHY_PAGE_SELECT_ALT;
+       }
+
+       temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
+       ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
+       if (ret_val) {
+               e1000e_release_phy_80003es2lan(hw);
+               goto out;
+       }
+
+       if (hw->dev_spec._80003es2lan.mdic_wa_enable == true) {
+               /*
+                * The "ready" bit in the MDIC register may be incorrectly set
+                * before the device has completed the "Page Select" MDI
+                * transaction.  So we wait 200us after each MDI command...
+                */
+               udelay(200);
+
+               /* ...and verify the command was successful. */
+               ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
+
+               if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
+                       ret_val = -E1000_ERR_PHY;
+                       e1000e_release_phy_80003es2lan(hw);
+                       goto out;
+               }
+
+               udelay(200);
+
+               ret_val = e1000e_read_phy_reg_mdic(hw,
+                                                 MAX_PHY_REG_ADDRESS & offset,
+                                                 data);
+
+               udelay(200);
+       } else
+               ret_val = e1000e_read_phy_reg_mdic(hw,
+                                                 MAX_PHY_REG_ADDRESS & offset,
+                                                 data);
+
+       e1000e_release_phy_80003es2lan(hw);
+
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000e_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
+ *  @hw: pointer to the HW structure
+ *  @offset: offset of the register to read
+ *  @data: value to write to the register
+ *
+ *  Write to the GG82563 PHY register.
+ **/
+static s32 e1000e_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
+                                                   u32 offset, u16 data)
+{
+       s32 ret_val;
+       u32 page_select;
+       u16 temp;
+
+       ret_val = e1000e_acquire_phy_80003es2lan(hw);
+       if (ret_val)
+               goto out;
+
+       /* Select Configuration Page */
+       if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
+               page_select = GG82563_PHY_PAGE_SELECT;
+       } else {
+               /*
+                * Use Alternative Page Select register to access
+                * registers 30 and 31
+                */
+               page_select = GG82563_PHY_PAGE_SELECT_ALT;
+       }
+
+       temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
+       ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
+       if (ret_val) {
+               e1000e_release_phy_80003es2lan(hw);
+               goto out;
+       }
+
+       if (hw->dev_spec._80003es2lan.mdic_wa_enable == true) {
+               /*
+                * The "ready" bit in the MDIC register may be incorrectly set
+                * before the device has completed the "Page Select" MDI
+                * transaction.  So we wait 200us after each MDI command...
+                */
+               udelay(200);
+
+               /* ...and verify the command was successful. */
+               ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
+
+               if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
+                       ret_val = -E1000_ERR_PHY;
+                       e1000e_release_phy_80003es2lan(hw);
+                       goto out;
+               }
+
+               udelay(200);
+
+               ret_val = e1000e_write_phy_reg_mdic(hw,
+                                                 MAX_PHY_REG_ADDRESS & offset,
+                                                 data);
+
+               udelay(200);
+       } else
+               ret_val = e1000e_write_phy_reg_mdic(hw,
+                                                 MAX_PHY_REG_ADDRESS & offset,
+               data);
+
+       e1000e_release_phy_80003es2lan(hw);
+
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000e_write_nvm_80003es2lan - Write to ESB2 NVM
+ *  @hw: pointer to the HW structure
+ *  @offset: offset of the register to read
+ *  @words: number of words to write
+ *  @data: buffer of data to write to the NVM
+ *
+ *  Write "words" of data to the ESB2 NVM.
+ **/
+static s32 e1000e_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
+                            u16 words, u16 *data)
+{
+       return e1000e_write_nvm_spi(hw, offset, words, data);
+}
+
+/**
+ *  e1000e_get_cfg_done_80003es2lan - Wait for configuration to complete
+ *  @hw: pointer to the HW structure
+ *
+ *  Wait a specific amount of time for manageability processes to complete.
+ *  This is a function pointer entry point called by the phy module.
+ **/
+static s32 e1000e_get_cfg_done_80003es2lan(struct e1000_hw *hw)
+{
+       s32 timeout = PHY_CFG_TIMEOUT;
+       s32 ret_val = E1000_SUCCESS;
+       u32 mask = E1000_NVM_CFG_DONE_PORT_0;
+
+       if (hw->bus.func == 1)
+               mask = E1000_NVM_CFG_DONE_PORT_1;
+
+       while (timeout) {
+               if (er32(EEMNGCTL) & mask)
+                       break;
+               msleep(1);
+               timeout--;
+       }
+       if (!timeout) {
+               e_dbg("MNG configuration cycle has not completed.\n");
+               ret_val = -E1000_ERR_RESET;
+               goto out;
+       }
+
+out:
+       return ret_val;
+}
+#if 0
+/**
+ *  e1000e_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
+ *  @hw: pointer to the HW structure
+ *
+ *  Force the speed and duplex settings onto the PHY.  This is a
+ *  function pointer entry point called by the phy module.
+ **/
+static s32 e1000e_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
+{
+       s32 ret_val = E1000_SUCCESS;
+       u16 phy_data;
+       bool link;
+
+       if (!(hw->phy.ops.read_reg))
+               goto out;
+
+       /*
+        * Clear Auto-Crossover to force MDI manually.  M88E1000 requires MDI
+        * forced whenever speed and duplex are forced.
+        */
+       ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
+       if (ret_val)
+               goto out;
+
+       phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
+       ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data);
+       if (ret_val)
+               goto out;
+
+       e_dbg("GG82563 PSCR: %X\n", phy_data);
+
+       ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
+       if (ret_val)
+               goto out;
+
+       e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
+
+       /* Reset the phy to commit changes. */
+       phy_data |= MII_CR_RESET;
+
+       ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
+       if (ret_val)
+               goto out;
+
+       udelay(1);
+
+       if (hw->phy.autoneg_wait_to_complete) {
+               e_dbg("Waiting for forced speed/duplex link "
+                        "on GG82563 phy.\n");
+
+               ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
+                                                    100000, &link);
+               if (ret_val)
+                       goto out;
+
+               if (!link) {
+                       /*
+                        * We didn't get link.
+                        * Reset the DSP and cross our fingers.
+                        */
+                       ret_val = e1000e_phy_reset_dsp(hw);
+                       if (ret_val)
+                               goto out;
+               }
+
+               /* Try once more */
+               ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
+                                                    100000, &link);
+               if (ret_val)
+                       goto out;
+       }
+
+       ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
+       if (ret_val)
+               goto out;
+
+       /*
+        * Resetting the phy means we need to verify the TX_CLK corresponds
+        * to the link speed.  10Mbps -> 2.5MHz, else 25MHz.
+        */
+       phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
+       if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
+               phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
+       else
+               phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
+
+       /*
+        * In addition, we must re-enable CRS on Tx for both half and full
+        * duplex.
+        */
+       phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
+       ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
+
+out:
+       return ret_val;
+}
+#endif
+
+#if 0
+/**
+ *  e1000e_get_cable_length_80003es2lan - Set approximate cable length
+ *  @hw: pointer to the HW structure
+ *
+ *  Find the approximate cable length as measured by the GG82563 PHY.
+ *  This is a function pointer entry point called by the phy module.
+ **/
+static s32 e1000e_get_cable_length_80003es2lan(struct e1000_hw *hw)
+{
+       struct e1000_phy_info *phy = &hw->phy;
+       s32 ret_val = E1000_SUCCESS;
+       u16 phy_data, index;
+
+       if (!(hw->phy.ops.read_reg))
+               goto out;
+
+       ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
+       if (ret_val)
+               goto out;
+
+       index = phy_data & GG82563_DSPD_CABLE_LENGTH;
+
+       if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5) {
+               ret_val = -E1000_ERR_PHY;
+               goto out;
+       }
+
+       phy->min_cable_length = e1000_gg82563_cable_length_table[index];
+       phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];
+
+       phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
+
+out:
+       return ret_val;
+}
+#endif
+
+/**
+ *  e1000e_get_link_up_info_80003es2lan - Report speed and duplex
+ *  @hw: pointer to the HW structure
+ *  @speed: pointer to speed buffer
+ *  @duplex: pointer to duplex buffer
+ *
+ *  Retrieve the current speed and duplex configuration.
+ **/
+static s32 e1000e_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
+                                              u16 *duplex)
+{
+       s32 ret_val;
+
+       if (hw->phy.media_type == e1000_media_type_copper) {
+               ret_val = e1000e_get_speed_and_duplex_copper(hw,
+                                                                   speed,
+                                                                   duplex);
+               hw->phy.ops.cfg_on_link_up(hw);
+       } else {
+               ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw,
+                                                                 speed,
+                                                                 duplex);
+       }
+
+       return ret_val;
+}
+
+/**
+ *  e1000e_reset_hw_80003es2lan - Reset the ESB2 controller
+ *  @hw: pointer to the HW structure
+ *
+ *  Perform a global reset to the ESB2 controller.
+ **/
+static s32 e1000e_reset_hw_80003es2lan(struct e1000_hw *hw)
+{
+       u32 ctrl, icr;
+       s32 ret_val;
+
+       /*
+        * Prevent the PCI-E bus from sticking if there is no TLP connection
+        * on the last TLP read/write transaction when MAC is reset.
+        */
+       ret_val = e1000e_disable_pcie_master(hw);
+       if (ret_val)
+               e_dbg("PCI-E Master disable polling has failed.\n");
+
+       e_dbg("Masking off all interrupts\n");
+       ew32(IMC, 0xffffffff);
+
+       ew32(RCTL, 0);
+       ew32(TCTL, E1000_TCTL_PSP);
+       e1e_flush();
+
+       msleep(10);
+
+       ctrl = er32(CTRL);
+
+       ret_val = e1000e_acquire_phy_80003es2lan(hw);
+       e_dbg("Issuing a global reset to MAC\n");
+       ew32(CTRL, ctrl | E1000_CTRL_RST);
+       e1000e_release_phy_80003es2lan(hw);
+
+       ret_val = e1000e_get_auto_rd_done(hw);
+       if (ret_val)
+               /* We don't want to continue accessing MAC registers. */
+               goto out;
+
+       /* Clear any pending interrupt events. */
+       ew32(IMC, 0xffffffff);
+       icr = er32(ICR);
+
+       ret_val = e1000e_check_alt_mac_addr_generic(hw);
+
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000e_init_hw_80003es2lan - Initialize the ESB2 controller
+ *  @hw: pointer to the HW structure
+ *
+ *  Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
+ **/
+static s32 e1000e_init_hw_80003es2lan(struct e1000_hw *hw)
+{
+       struct e1000_mac_info *mac = &hw->mac;
+       u32 reg_data;
+       s32 ret_val;
+       u16 i;
+
+       e1000e_initialize_hw_bits_80003es2lan(hw);
+
+       /* Initialize identification LED */
+       ret_val = mac->ops.id_led_init(hw);
+       if (ret_val) {
+               e_dbg("Error initializing identification LED\n");
+               /* This is not fatal and we should not stop init due to this */
+       }
+
+       /* Disabling VLAN filtering */
+       e_dbg("Initializing the IEEE VLAN\n");
+       e1000e_clear_vfta(hw);
+
+       /* Setup the receive address. */
+       e1000e_init_rx_addrs(hw, mac->rar_entry_count);
+
+       /* Zero out the Multicast HASH table */
+       e_dbg("Zeroing the MTA\n");
+       for (i = 0; i < mac->mta_reg_count; i++)
+               E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
+
+       /* Setup link and flow control */
+       ret_val = mac->ops.setup_link(hw);
+
+       /* Set the transmit descriptor write-back policy */
+       reg_data = er32(TXDCTL(0));
+       reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
+                  E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
+       ew32(TXDCTL(0), reg_data);
+
+       /* ...for both queues. */
+       reg_data = er32(TXDCTL(1));
+       reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
+                  E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
+       ew32(TXDCTL(1), reg_data);
+
+       /* Enable retransmit on late collisions */
+       reg_data = er32(TCTL);
+       reg_data |= E1000_TCTL_RTLC;
+       ew32(TCTL, reg_data);
+
+       /* Configure Gigabit Carry Extend Padding */
+       reg_data = er32(TCTL_EXT);
+       reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
+       reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
+       ew32(TCTL_EXT, reg_data);
+
+       /* Configure Transmit Inter-Packet Gap */
+       reg_data = er32(TIPG);
+       reg_data &= ~E1000_TIPG_IPGT_MASK;
+       reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
+       ew32(TIPG, reg_data);
+
+       reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
+       reg_data &= ~0x00100000;
+       E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
+
+       /* default to true to enable the MDIC W/A */
+       hw->dev_spec._80003es2lan.mdic_wa_enable = true;
+
+       ret_val = e1000e_read_kmrn_reg_80003es2lan(hw,
+                                     E1000_KMRNCTRLSTA_OFFSET >>
+                                     E1000_KMRNCTRLSTA_OFFSET_SHIFT,
+                                     &i);
+       if (!ret_val) {
+               if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
+                    E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
+                       hw->dev_spec._80003es2lan.mdic_wa_enable = false;
+       }
+
+       /*
+        * Clear all of the statistics registers (clear on read).  It is
+        * important that we do this after we have tried to establish link
+        * because the symbol error count will increment wildly if there
+        * is no link.
+        */
+       e1000e_clear_hw_cntrs_80003es2lan(hw);
+
+       return ret_val;
+}
+
+/**
+ *  e1000e_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
+ *  @hw: pointer to the HW structure
+ *
+ *  Initializes required hardware-dependent bits needed for normal operation.
+ **/
+static void e1000e_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
+{
+       u32 reg;
+
+       /* Transmit Descriptor Control 0 */
+       reg = er32(TXDCTL(0));
+       reg |= (1 << 22);
+       ew32(TXDCTL(0), reg);
+
+       /* Transmit Descriptor Control 1 */
+       reg = er32(TXDCTL(1));
+       reg |= (1 << 22);
+       ew32(TXDCTL(1), reg);
+
+       /* Transmit Arbitration Control 0 */
+       reg = er32(TARC(0));
+       reg &= ~(0xF << 27); /* 30:27 */
+       if (hw->phy.media_type != e1000_media_type_copper)
+               reg &= ~(1 << 20);
+       ew32(TARC(0), reg);
+
+       /* Transmit Arbitration Control 1 */
+       reg = er32(TARC(1));
+       if (er32(TCTL) & E1000_TCTL_MULR)
+               reg &= ~(1 << 28);
+       else
+               reg |= (1 << 28);
+       ew32(TARC(1), reg);
+
+       return;
+}
+
+/**
+ *  e1000e_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
+ *  @hw: pointer to the HW structure
+ *
+ *  Setup some GG82563 PHY registers for obtaining link
+ **/
+static s32 e1000e_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
+{
+       struct e1000_phy_info *phy = &hw->phy;
+       s32 ret_val;
+       u32 ctrl_ext;
+       u16 data;
+
+       if (!phy->reset_disable) {
+               ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL,
+                                            &data);
+               if (ret_val)
+                       goto out;
+
+               data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
+               /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
+               data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
+
+               ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL,
+                                             data);
+               if (ret_val)
+                       goto out;
+
+               /*
+                * Options:
+                *   MDI/MDI-X = 0 (default)
+                *   0 - Auto for all speeds
+                *   1 - MDI mode
+                *   2 - MDI-X mode
+                *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
+                */
+               ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data);
+               if (ret_val)
+                       goto out;
+
+               data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
+
+               switch (phy->mdix) {
+               case 1:
+                       data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
+                       break;
+               case 2:
+                       data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
+                       break;
+               case 0:
+               default:
+                       data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
+                       break;
+               }
+
+               /*
+                * Options:
+                *   disable_polarity_correction = 0 (default)
+                *       Automatic Correction for Reversed Cable Polarity
+                *   0 - Disabled
+                *   1 - Enabled
+                */
+               data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
+               if (phy->disable_polarity_correction)
+                       data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
+
+               ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data);
+               if (ret_val)
+                       goto out;
+
+               /* SW Reset the PHY so all changes take effect */
+               ret_val = e1000e_commit_phy(hw);
+               if (ret_val) {
+                       e_dbg("Error Resetting the PHY\n");
+                       goto out;
+               }
+
+       }
+
+       /* Bypass Rx and Tx FIFO's */
+       ret_val = e1000e_write_kmrn_reg_80003es2lan(hw,
+                                       E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
+                                       E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
+                                       E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
+       if (ret_val)
+               goto out;
+
+       ret_val = e1000e_read_kmrn_reg_80003es2lan(hw,
+                                     E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
+                                     &data);
+       if (ret_val)
+               goto out;
+       data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
+       ret_val = e1000e_write_kmrn_reg_80003es2lan(hw,
+                                      E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
+                                      data);
+       if (ret_val)
+               goto out;
+
+       ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data);
+       if (ret_val)
+               goto out;
+
+       data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
+       ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data);
+       if (ret_val)
+               goto out;
+
+       ctrl_ext = er32(CTRL_EXT);
+       ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
+       ew32(CTRL_EXT, ctrl_ext);
+
+       ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
+       if (ret_val)
+               goto out;
+
+       /*
+        * Do not init these registers when the HW is in IAMT mode, since the
+        * firmware will have already initialized them.  We only initialize
+        * them if the HW is not in IAMT mode.
+        */
+       if (!(hw->mac.ops.check_mng_mode(hw))) {
+               /* Enable Electrical Idle on the PHY */
+               data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
+               ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL,
+                                               data);
+               if (ret_val)
+                       goto out;
+
+               ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL,
+                                              &data);
+               if (ret_val)
+                       goto out;
+
+               data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
+               ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL,
+                                               data);
+               if (ret_val)
+                       goto out;
+       }
+
+       /*
+        * Workaround: Disable padding in Kumeran interface in the MAC
+        * and in the PHY to avoid CRC errors.
+        */
+       ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);
+       if (ret_val)
+               goto out;
+
+       data |= GG82563_ICR_DIS_PADDING;
+       ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data);
+       if (ret_val)
+               goto out;
+
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000e_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
+ *  @hw: pointer to the HW structure
+ *
+ *  Essentially a wrapper for setting up all things "copper" related.
+ *  This is a function pointer entry point called by the mac module.
+ **/
+static s32 e1000e_setup_copper_link_80003es2lan(struct e1000_hw *hw)
+{
+       u32 ctrl;
+       s32 ret_val;
+       u16 reg_data;
+
+       ctrl = er32(CTRL);
+       ctrl |= E1000_CTRL_SLU;
+       ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
+       ew32(CTRL, ctrl);
+
+       /*
+        * Set the mac to wait the maximum time between each
+        * iteration and increase the max iterations when
+        * polling the phy; this fixes erroneous timeouts at 10Mbps.
+        */
+       ret_val = e1000e_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
+                                                  0xFFFF);
+       if (ret_val)
+               goto out;
+       ret_val = e1000e_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
+                                                 &reg_data);
+       if (ret_val)
+               goto out;
+       reg_data |= 0x3F;
+       ret_val = e1000e_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
+                                                  reg_data);
+       if (ret_val)
+               goto out;
+       ret_val = e1000e_read_kmrn_reg_80003es2lan(hw,
+                                     E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
+                                     &reg_data);
+       if (ret_val)
+               goto out;
+       reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
+       ret_val = e1000e_write_kmrn_reg_80003es2lan(hw,
+                                      E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
+                                      reg_data);
+       if (ret_val)
+               goto out;
+
+       ret_val = e1000e_copper_link_setup_gg82563_80003es2lan(hw);
+       if (ret_val)
+               goto out;
+
+       ret_val = e1000e_setup_copper_link(hw);
+
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000e_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
+ *  @hw: pointer to the HW structure
+ *  @duplex: current duplex setting
+ *
+ *  Configure the KMRN interface by applying last minute quirks for
+ *  10/100 operation.
+ **/
+static s32 e1000e_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
+{
+       s32 ret_val = E1000_SUCCESS;
+       u16 speed;
+       u16 duplex;
+
+       if (hw->phy.media_type == e1000_media_type_copper) {
+               ret_val = e1000e_get_speed_and_duplex_copper(hw,
+                                                                   &speed,
+                                                                   &duplex);
+               if (ret_val)
+                       goto out;
+
+               if (speed == SPEED_1000)
+                       ret_val = e1000e_cfg_kmrn_1000_80003es2lan(hw);
+               else
+                       ret_val = e1000e_cfg_kmrn_10_100_80003es2lan(hw, duplex);
+       }
+
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000e_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
+ *  @hw: pointer to the HW structure
+ *  @duplex: current duplex setting
+ *
+ *  Configure the KMRN interface by applying last minute quirks for
+ *  10/100 operation.
+ **/
+static s32 e1000e_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
+{
+       s32 ret_val = E1000_SUCCESS;
+       u32 tipg;
+       u32 i = 0;
+       u16 reg_data, reg_data2;
+
+       reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
+       ret_val = e1000e_write_kmrn_reg_80003es2lan(hw,
+                                      E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
+                                      reg_data);
+       if (ret_val)
+               goto out;
+
+       /* Configure Transmit Inter-Packet Gap */
+       tipg = er32(TIPG);
+       tipg &= ~E1000_TIPG_IPGT_MASK;
+       tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
+       ew32(TIPG, tipg);
+
+
+       do {
+               ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL,
+                                              &reg_data);
+               if (ret_val)
+                       goto out;
+
+               ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL,
+                                              &reg_data2);
+               if (ret_val)
+                       goto out;
+               i++;
+       } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
+
+       if (duplex == HALF_DUPLEX)
+               reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
+       else
+               reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
+
+       ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
+
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000e_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
+ *  @hw: pointer to the HW structure
+ *
+ *  Configure the KMRN interface by applying last minute quirks for
+ *  gigabit operation.
+ **/
+static s32 e1000e_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
+{
+       s32 ret_val = E1000_SUCCESS;
+       u16 reg_data, reg_data2;
+       u32 tipg;
+       u32 i = 0;
+
+       reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
+       ret_val = e1000e_write_kmrn_reg_80003es2lan(hw,
+                                      E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
+                                      reg_data);
+       if (ret_val)
+               goto out;
+
+       /* Configure Transmit Inter-Packet Gap */
+       tipg = er32(TIPG);
+       tipg &= ~E1000_TIPG_IPGT_MASK;
+       tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
+       ew32(TIPG, tipg);
+
+
+       do {
+               ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL,
+                                              &reg_data);
+               if (ret_val)
+                       goto out;
+
+               ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL,
+                                              &reg_data2);
+               if (ret_val)
+                       goto out;
+               i++;
+       } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
+
+       reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
+       ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
+
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000e_read_kmrn_reg_80003es2lan - Read kumeran register
+ *  @hw: pointer to the HW structure
+ *  @offset: register offset to be read
+ *  @data: pointer to the read data
+ *
+ *  Acquire semaphore, then read the PHY register at offset
+ *  using the kumeran interface.  The information retrieved is stored in data.
+ *  Release the semaphore before exiting.
+ **/
+static s32 e1000e_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
+                                           u16 *data)
+{
+       u32 kmrnctrlsta;
+       s32 ret_val = E1000_SUCCESS;
+
+       ret_val = e1000e_acquire_mac_csr_80003es2lan(hw);
+       if (ret_val)
+               goto out;
+
+       kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
+                      E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
+       ew32(KMRNCTRLSTA, kmrnctrlsta);
+
+       udelay(2);
+
+       kmrnctrlsta = er32(KMRNCTRLSTA);
+       *data = (u16)kmrnctrlsta;
+
+       e1000e_release_mac_csr_80003es2lan(hw);
+
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000e_write_kmrn_reg_80003es2lan - Write kumeran register
+ *  @hw: pointer to the HW structure
+ *  @offset: register offset to write to
+ *  @data: data to write at register offset
+ *
+ *  Acquire semaphore, then write the data to PHY register
+ *  at the offset using the kumeran interface.  Release semaphore
+ *  before exiting.
+ **/
+static s32 e1000e_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
+                                            u16 data)
+{
+       u32 kmrnctrlsta;
+       s32 ret_val = E1000_SUCCESS;
+
+       ret_val = e1000e_acquire_mac_csr_80003es2lan(hw);
+       if (ret_val)
+               goto out;
+
+       kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
+                      E1000_KMRNCTRLSTA_OFFSET) | data;
+       ew32(KMRNCTRLSTA, kmrnctrlsta);
+
+       udelay(2);
+
+       e1000e_release_mac_csr_80003es2lan(hw);
+
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000e_read_mac_addr_80003es2lan - Read device MAC address
+ *  @hw: pointer to the HW structure
+ **/
+static s32 e1000e_read_mac_addr_80003es2lan(struct e1000_hw *hw)
+{
+       s32 ret_val = E1000_SUCCESS;
+
+       /*
+        * If there's an alternate MAC address place it in RAR0
+        * so that it will override the Si installed default perm
+        * address.
+        */
+       ret_val = e1000e_check_alt_mac_addr_generic(hw);
+       if (ret_val)
+               goto out;
+
+       ret_val = e1000e_read_mac_addr_generic(hw);
+
+out:
+       return ret_val;
+}
+
+/**
+ * e1000e_power_down_phy_copper_80003es2lan - Remove link during PHY power down
+ * @hw: pointer to the HW structure
+ *
+ * In the case of a PHY power down to save power, or to turn off link during a
+ * driver unload, or wake on lan is not enabled, remove the link.
+ **/
+static void e1000e_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
+{
+       /* If the management interface is not enabled, then power down */
+       if (!(hw->mac.ops.check_mng_mode(hw) ||
+             e1000e_check_reset_block(hw)))
+             e1000e_power_down_phy_copper(hw);
+
+       return;
+}
+
+/**
+ *  e1000e_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
+ *  @hw: pointer to the HW structure
+ *
+ *  Clears the hardware counters by reading the counter registers.
+ **/
+static void e1000e_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw __unused)
+{
+#if 0
+       e1000e_clear_hw_cntrs_base(hw);
+
+       er32(PRC64);
+       er32(PRC127);
+       er32(PRC255);
+       er32(PRC511);
+       er32(PRC1023);
+       er32(PRC1522);
+       er32(PTC64);
+       er32(PTC127);
+       er32(PTC255);
+       er32(PTC511);
+       er32(PTC1023);
+       er32(PTC1522);
+
+       er32(ALGNERRC);
+       er32(RXERRC);
+       er32(TNCRS);
+       er32(CEXTERR);
+       er32(TSCTC);
+       er32(TSCTFC);
+
+       er32(MGTPRC);
+       er32(MGTPDC);
+       er32(MGTPTC);
+
+       er32(IAC);
+       er32(ICRXOC);
+
+       er32(ICRXPTC);
+       er32(ICRXATC);
+       er32(ICTXPTC);
+       er32(ICTXATC);
+       er32(ICTXQEC);
+       er32(ICTXQMTC);
+       er32(ICRXDMTC);
+#endif
+}
+
+static struct pci_device_id e1000e_80003es2lan_nics[] = {
+     PCI_ROM(0x8086, 0x1096, "E1000_DEV_ID_80003ES2LAN_COPPER_DPT", "E1000_DEV_ID_80003ES2LAN_COPPER_DPT", board_80003es2lan),
+     PCI_ROM(0x8086, 0x10BA, "E1000_DEV_ID_80003ES2LAN_COPPER_SPT", "E1000_DEV_ID_80003ES2LAN_COPPER_SPT", board_80003es2lan),
+     PCI_ROM(0x8086, 0x1098, "E1000_DEV_ID_80003ES2LAN_SERDES_DPT", "E1000_DEV_ID_80003ES2LAN_SERDES_DPT", board_80003es2lan),
+     PCI_ROM(0x8086, 0x10BB, "E1000_DEV_ID_80003ES2LAN_SERDES_SPT", "E1000_DEV_ID_80003ES2LAN_SERDES_SPT", board_80003es2lan),
+};
+
+struct pci_driver e1000e_80003es2lan_driver __pci_driver = {
+       .ids = e1000e_80003es2lan_nics,
+       .id_count = (sizeof (e1000e_80003es2lan_nics) / sizeof (e1000e_80003es2lan_nics[0])),
+       .probe = e1000e_probe,
+       .remove = e1000e_remove,
+};
diff --git a/src/drivers/net/e1000e/e1000e_80003es2lan.h b/src/drivers/net/e1000e/e1000e_80003es2lan.h
new file mode 100644 (file)
index 0000000..93430a1
--- /dev/null
@@ -0,0 +1,100 @@
+/*******************************************************************************
+
+  Intel PRO/1000 Linux driver
+  Copyright(c) 1999 - 2009 Intel Corporation.
+
+  This program is free software; you can redistribute it and/or modify it
+  under the terms and conditions of the GNU General Public License,
+  version 2, as published by the Free Software Foundation.
+
+  This program is distributed in the hope it will be useful, but WITHOUT
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+  more details.
+
+  You should have received a copy of the GNU General Public License along with
+  this program; if not, write to the Free Software Foundation, Inc.,
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+
+  The full GNU General Public License is included in this distribution in
+  the file called "COPYING".
+
+  Contact Information:
+  Linux NICS <linux.nics@intel.com>
+  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+
+*******************************************************************************/
+
+FILE_LICENCE ( GPL2_OR_LATER );
+
+#ifndef _E1000E_80003ES2LAN_H_
+#define _E1000E_80003ES2LAN_H_
+
+#define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL       0x00
+#define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL        0x02
+#define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL         0x10
+#define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE  0x1F
+
+#define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS    0x0008
+#define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS    0x0800
+#define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING   0x0010
+
+#define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
+#define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT   0x0000
+#define E1000_KMRNCTRLSTA_OPMODE_E_IDLE          0x2000
+
+#define E1000_KMRNCTRLSTA_OPMODE_MASK            0x000C
+#define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO     0x0004
+
+#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
+#define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN        0x00010000
+
+#define DEFAULT_TIPG_IPGT_1000_80003ES2LAN       0x8
+#define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN     0x9
+
+/* GG82563 PHY Specific Status Register (Page 0, Register 16 */
+#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE  0x0002 /* 1=Reversal Disabled */
+#define GG82563_PSCR_CROSSOVER_MODE_MASK        0x0060
+#define GG82563_PSCR_CROSSOVER_MODE_MDI         0x0000 /* 00=Manual MDI */
+#define GG82563_PSCR_CROSSOVER_MODE_MDIX        0x0020 /* 01=Manual MDIX */
+#define GG82563_PSCR_CROSSOVER_MODE_AUTO        0x0060 /* 11=Auto crossover */
+
+/* PHY Specific Control Register 2 (Page 0, Register 26) */
+#define GG82563_PSCR2_REVERSE_AUTO_NEG          0x2000
+                                               /* 1=Reverse Auto-Negotiation */
+
+/* MAC Specific Control Register (Page 2, Register 21) */
+/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
+#define GG82563_MSCR_TX_CLK_MASK                0x0007
+#define GG82563_MSCR_TX_CLK_10MBPS_2_5          0x0004
+#define GG82563_MSCR_TX_CLK_100MBPS_25          0x0005
+#define GG82563_MSCR_TX_CLK_1000MBPS_2_5        0x0006
+#define GG82563_MSCR_TX_CLK_1000MBPS_25         0x0007
+
+#define GG82563_MSCR_ASSERT_CRS_ON_TX           0x0010 /* 1=Assert */
+
+/* DSP Distance Register (Page 5, Register 26) */
+/*
+ * 0 = <50M
+ * 1 = 50-80M
+ * 2 = 80-100M
+ * 3 = 110-140M
+ * 4 = >140M
+ */
+#define GG82563_DSPD_CABLE_LENGTH               0x0007
+
+/* Kumeran Mode Control Register (Page 193, Register 16) */
+#define GG82563_KMCR_PASS_FALSE_CARRIER         0x0800
+
+/* Max number of times Kumeran read/write should be validated */
+#define GG82563_MAX_KMRN_RETRY                  0x5
+
+/* Power Management Control Register (Page 193, Register 20) */
+#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE     0x0001
+                                          /* 1=Enable SERDES Electrical Idle */
+
+/* In-Band Control Register (Page 194, Register 18) */
+#define GG82563_ICR_DIS_PADDING                 0x0010 /* Disable Padding */
+
+#endif
diff --git a/src/drivers/net/e1000e/e1000e_82571.c b/src/drivers/net/e1000e/e1000e_82571.c
new file mode 100644 (file)
index 0000000..840e29b
--- /dev/null
@@ -0,0 +1,1818 @@
+/*******************************************************************************
+
+  Intel PRO/1000 Linux driver
+  Copyright(c) 1999 - 2009 Intel Corporation.
+
+  This program is free software; you can redistribute it and/or modify it
+  under the terms and conditions of the GNU General Public License,
+  version 2, as published by the Free Software Foundation.
+
+  This program is distributed in the hope it will be useful, but WITHOUT
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+  more details.
+
+  You should have received a copy of the GNU General Public License along with
+  this program; if not, write to the Free Software Foundation, Inc.,
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+
+  The full GNU General Public License is included in this distribution in
+  the file called "COPYING".
+
+  Contact Information:
+  Linux NICS <linux.nics@intel.com>
+  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+
+*******************************************************************************/
+
+FILE_LICENCE ( GPL2_OR_LATER );
+
+/*
+ * 82571EB Gigabit Ethernet Controller
+ * 82571EB Gigabit Ethernet Controller (Copper)
+ * 82571EB Gigabit Ethernet Controller (Fiber)
+ * 82571EB Dual Port Gigabit Mezzanine Adapter
+ * 82571EB Quad Port Gigabit Mezzanine Adapter
+ * 82571PT Gigabit PT Quad Port Server ExpressModule
+ * 82572EI Gigabit Ethernet Controller (Copper)
+ * 82572EI Gigabit Ethernet Controller (Fiber)
+ * 82572EI Gigabit Ethernet Controller
+ * 82573V Gigabit Ethernet Controller (Copper)
+ * 82573E Gigabit Ethernet Controller (Copper)
+ * 82573L Gigabit Ethernet Controller
+ * 82574L Gigabit Network Connection
+ * 82574L Gigabit Network Connection
+ * 82583V Gigabit Network Connection
+ */
+
+#include "e1000e.h"
+
+static s32  e1000e_init_phy_params_82571(struct e1000_hw *hw);
+static s32  e1000e_init_nvm_params_82571(struct e1000_hw *hw);
+static s32  e1000e_init_mac_params_82571(struct e1000_hw *hw);
+static s32  e1000e_acquire_nvm_82571(struct e1000_hw *hw);
+static void e1000e_release_nvm_82571(struct e1000_hw *hw);
+static s32  e1000e_write_nvm_82571(struct e1000_hw *hw, u16 offset,
+                                  u16 words, u16 *data);
+static s32  e1000e_update_nvm_checksum_82571(struct e1000_hw *hw);
+static s32  e1000e_validate_nvm_checksum_82571(struct e1000_hw *hw);
+static s32  e1000e_get_cfg_done_82571(struct e1000_hw *hw);
+static s32  e1000e_set_d0_lplu_state_82571(struct e1000_hw *hw,
+                                          bool active);
+static s32  e1000e_reset_hw_82571(struct e1000_hw *hw);
+static s32  e1000e_init_hw_82571(struct e1000_hw *hw);
+static void e1000e_clear_vfta_82571(struct e1000_hw *hw);
+#if 0
+static bool e1000e_check_mng_mode_82574(struct e1000_hw *hw);
+#endif
+static s32  e1000e_led_on_82574(struct e1000_hw *hw);
+static s32  e1000e_setup_link_82571(struct e1000_hw *hw);
+static s32  e1000e_setup_copper_link_82571(struct e1000_hw *hw);
+static s32  e1000e_check_for_serdes_link_82571(struct e1000_hw *hw);
+static s32  e1000e_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
+static s32  e1000e_valid_led_default_82571(struct e1000_hw *hw, u16 *data);
+static void e1000e_clear_hw_cntrs_82571(struct e1000_hw *hw);
+static s32  e1000e_get_hw_semaphore_82571(struct e1000_hw *hw);
+static s32  e1000e_fix_nvm_checksum_82571(struct e1000_hw *hw);
+static s32  e1000e_get_phy_id_82571(struct e1000_hw *hw);
+static void e1000e_put_hw_semaphore_82571(struct e1000_hw *hw);
+static void e1000e_initialize_hw_bits_82571(struct e1000_hw *hw);
+static s32  e1000e_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
+                                       u16 words, u16 *data);
+static s32  e1000e_read_mac_addr_82571(struct e1000_hw *hw);
+static void e1000e_power_down_phy_copper_82571(struct e1000_hw *hw);
+
+/**
+ *  e1000e_init_phy_params_82571 - Init PHY func ptrs.
+ *  @hw: pointer to the HW structure
+ **/
+static s32 e1000e_init_phy_params_82571(struct e1000_hw *hw)
+{
+       struct e1000_phy_info *phy = &hw->phy;
+       s32 ret_val = E1000_SUCCESS;
+
+       if (hw->phy.media_type != e1000_media_type_copper) {
+               phy->type = e1000_phy_none;
+               goto out;
+       }
+
+       phy->addr                        = 1;
+       phy->autoneg_mask                = AUTONEG_ADVERTISE_SPEED_DEFAULT;
+       phy->reset_delay_us              = 100;
+
+       phy->ops.acquire                 = e1000e_get_hw_semaphore_82571;
+       phy->ops.check_polarity          = e1000e_check_polarity_igp;
+       phy->ops.check_reset_block       = e1000e_check_reset_block_generic;
+       phy->ops.release                 = e1000e_put_hw_semaphore_82571;
+       phy->ops.reset                   = e1000e_phy_hw_reset_generic;
+       phy->ops.set_d0_lplu_state       = e1000e_set_d0_lplu_state_82571;
+       phy->ops.set_d3_lplu_state       = e1000e_set_d3_lplu_state;
+       phy->ops.power_up                = e1000e_power_up_phy_copper;
+       phy->ops.power_down              = e1000e_power_down_phy_copper_82571;
+
+       switch (hw->mac.type) {
+       case e1000_82571:
+       case e1000_82572:
+               phy->type                   = e1000_phy_igp_2;
+               phy->ops.get_cfg_done       = e1000e_get_cfg_done_82571;
+               phy->ops.get_info           = e1000e_get_phy_info_igp;
+#if 0
+               phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
+#endif
+#if 0
+               phy->ops.get_cable_length   = e1000e_get_cable_length_igp_2;
+#endif
+               phy->ops.read_reg           = e1000e_read_phy_reg_igp;
+               phy->ops.write_reg          = e1000e_write_phy_reg_igp;
+
+               /* This uses above function pointers */
+               ret_val = e1000e_get_phy_id_82571(hw);
+
+               /* Verify PHY ID */
+               if (phy->id != IGP01E1000_I_PHY_ID) {
+                       ret_val = -E1000_ERR_PHY;
+                       goto out;
+               }
+               break;
+       case e1000_82573:
+               phy->type                   = e1000_phy_m88;
+               phy->ops.get_cfg_done       = e1000e_get_cfg_done;
+               phy->ops.get_info           = e1000e_get_phy_info_m88;
+               phy->ops.commit             = e1000e_phy_sw_reset;
+#if 0
+               phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
+#endif
+#if 0
+               phy->ops.get_cable_length   = e1000e_get_cable_length_m88;
+#endif
+               phy->ops.read_reg           = e1000e_read_phy_reg_m88;
+               phy->ops.write_reg          = e1000e_write_phy_reg_m88;
+
+               /* This uses above function pointers */
+               ret_val = e1000e_get_phy_id_82571(hw);
+
+               /* Verify PHY ID */
+               if (phy->id != M88E1111_I_PHY_ID) {
+                       ret_val = -E1000_ERR_PHY;
+                       e_dbg("PHY ID unknown: type = 0x%08x\n", phy->id);
+                       goto out;
+               }
+               break;
+       case e1000_82583:
+       case e1000_82574:
+               phy->type                   = e1000_phy_bm;
+               phy->ops.get_cfg_done       = e1000e_get_cfg_done;
+               phy->ops.get_info           = e1000e_get_phy_info_m88;
+               phy->ops.commit             = e1000e_phy_sw_reset;
+#if 0
+               phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
+#endif
+#if 0
+               phy->ops.get_cable_length   = e1000e_get_cable_length_m88;
+#endif
+               phy->ops.read_reg           = e1000e_read_phy_reg_bm2;
+               phy->ops.write_reg          = e1000e_write_phy_reg_bm2;
+
+               /* This uses above function pointers */
+               ret_val = e1000e_get_phy_id_82571(hw);
+               /* Verify PHY ID */
+               if (phy->id != BME1000_E_PHY_ID_R2) {
+                       ret_val = -E1000_ERR_PHY;
+                       e_dbg("PHY ID unknown: type = 0x%08x\n", phy->id);
+                       goto out;
+               }
+               break;
+       default:
+               ret_val = -E1000_ERR_PHY;
+               goto out;
+               break;
+       }
+
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000e_init_nvm_params_82571 - Init NVM func ptrs.
+ *  @hw: pointer to the HW structure
+ **/
+static s32 e1000e_init_nvm_params_82571(struct e1000_hw *hw)
+{
+       struct e1000_nvm_info *nvm = &hw->nvm;
+       u32 eecd = er32(EECD);
+       u16 size;
+
+       nvm->opcode_bits = 8;
+       nvm->delay_usec = 1;
+       switch (nvm->override) {
+       case e1000_nvm_override_spi_large:
+               nvm->page_size = 32;
+               nvm->address_bits = 16;
+               break;
+       case e1000_nvm_override_spi_small:
+               nvm->page_size = 8;
+               nvm->address_bits = 8;
+               break;
+       default:
+               nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
+               nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
+               break;
+       }
+
+       switch (hw->mac.type) {
+       case e1000_82573:
+       case e1000_82574:
+       case e1000_82583:
+               if (((eecd >> 15) & 0x3) == 0x3) {
+                       nvm->type = e1000_nvm_flash_hw;
+                       nvm->word_size = 2048;
+                       /*
+                        * Autonomous Flash update bit must be cleared due
+                        * to Flash update issue.
+                        */
+                       eecd &= ~E1000_EECD_AUPDEN;
+                       ew32(EECD, eecd);
+                       break;
+               }
+               /* Fall Through */
+       default:
+               nvm->type = e1000_nvm_eeprom_spi;
+               size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
+                                 E1000_EECD_SIZE_EX_SHIFT);
+               /*
+                * Added to a constant, "size" becomes the left-shift value
+                * for setting word_size.
+                */
+               size += NVM_WORD_SIZE_BASE_SHIFT;
+
+               /* EEPROM access above 16k is unsupported */
+               if (size > 14)
+                       size = 14;
+               nvm->word_size  = 1 << size;
+               break;
+       }
+
+       /* Function Pointers */
+       nvm->ops.acquire       = e1000e_acquire_nvm_82571;
+       nvm->ops.read          = e1000e_read_nvm_eerd;
+       nvm->ops.release       = e1000e_release_nvm_82571;
+       nvm->ops.update        = e1000e_update_nvm_checksum_82571;
+       nvm->ops.validate      = e1000e_validate_nvm_checksum_82571;
+       nvm->ops.valid_led_default = e1000e_valid_led_default_82571;
+       nvm->ops.write         = e1000e_write_nvm_82571;
+
+       return E1000_SUCCESS;
+}
+
+/**
+ *  e1000e_init_mac_params_82571 - Init MAC func ptrs.
+ *  @hw: pointer to the HW structure
+ **/
+static s32 e1000e_init_mac_params_82571(struct e1000_hw *hw)
+{
+       struct e1000_mac_info *mac = &hw->mac;
+       s32 ret_val = E1000_SUCCESS;
+       u32 swsm = 0;
+       u32 swsm2 = 0;
+       bool force_clear_smbi = false;
+
+       /* Set media type */
+       switch (hw->device_id) {
+       case E1000_DEV_ID_82571EB_FIBER:
+       case E1000_DEV_ID_82572EI_FIBER:
+       case E1000_DEV_ID_82571EB_QUAD_FIBER:
+               hw->phy.media_type = e1000_media_type_fiber;
+               break;
+       case E1000_DEV_ID_82571EB_SERDES:
+       case E1000_DEV_ID_82571EB_SERDES_DUAL:
+       case E1000_DEV_ID_82571EB_SERDES_QUAD:
+       case E1000_DEV_ID_82572EI_SERDES:
+               hw->phy.media_type = e1000_media_type_internal_serdes;
+               break;
+       default:
+               hw->phy.media_type = e1000_media_type_copper;
+               break;
+       }
+
+       /* Set mta register count */
+       mac->mta_reg_count = 128;
+       /* Set rar entry count */
+       mac->rar_entry_count = E1000_RAR_ENTRIES;
+       /* Set if part includes ASF firmware */
+       mac->asf_firmware_present = true;
+       /* Set if manageability features are enabled. */
+       mac->arc_subsystem_valid =
+               (er32(FWSM) & E1000_FWSM_MODE_MASK)
+                       ? true : false;
+
+       /* Function pointers */
+
+       /* bus type/speed/width */
+       mac->ops.get_bus_info = e1000e_get_bus_info_pcie;
+       /* function id */
+       switch (hw->mac.type) {
+       case e1000_82573:
+       case e1000_82574:
+       case e1000_82583:
+               mac->ops.set_lan_id = e1000e_set_lan_id_single_port;
+               break;
+       default:
+               break;
+       }
+       /* reset */
+       mac->ops.reset_hw = e1000e_reset_hw_82571;
+       /* hw initialization */
+       mac->ops.init_hw = e1000e_init_hw_82571;
+       /* link setup */
+       mac->ops.setup_link = e1000e_setup_link_82571;
+       /* physical interface link setup */
+       mac->ops.setup_physical_interface =
+               (hw->phy.media_type == e1000_media_type_copper)
+                       ? e1000e_setup_copper_link_82571
+                       : e1000e_setup_fiber_serdes_link_82571;
+       /* check for link */
+       switch (hw->phy.media_type) {
+       case e1000_media_type_copper:
+               mac->ops.check_for_link = e1000e_check_for_copper_link;
+               break;
+       case e1000_media_type_fiber:
+               mac->ops.check_for_link = e1000e_check_for_fiber_link;
+               break;
+       case e1000_media_type_internal_serdes:
+               mac->ops.check_for_link = e1000e_check_for_serdes_link_82571;
+               break;
+       default:
+               ret_val = -E1000_ERR_CONFIG;
+               goto out;
+               break;
+       }
+       /* check management mode */
+#if 0
+       switch (hw->mac.type) {
+       case e1000_82574:
+       case e1000_82583:
+               mac->ops.check_mng_mode = e1000e_check_mng_mode_82574;
+               break;
+       default:
+               mac->ops.check_mng_mode = e1000e_check_mng_mode_generic;
+               break;
+       }
+#endif
+       /* multicast address update */
+       mac->ops.update_mc_addr_list = e1000e_update_mc_addr_list_generic;
+       /* writing VFTA */
+       mac->ops.write_vfta = e1000e_write_vfta_generic;
+       /* clearing VFTA */
+       mac->ops.clear_vfta = e1000e_clear_vfta_82571;
+       /* setting MTA */
+       mac->ops.mta_set = e1000e_mta_set_generic;
+       /* read mac address */
+       mac->ops.read_mac_addr = e1000e_read_mac_addr_82571;
+       /* ID LED init */
+       mac->ops.id_led_init = e1000e_id_led_init;
+       /* blink LED */
+       mac->ops.blink_led = e1000e_blink_led;
+       /* setup LED */
+       mac->ops.setup_led = e1000e_setup_led_generic;
+       /* cleanup LED */
+       mac->ops.cleanup_led = e1000e_cleanup_led_generic;
+       /* turn on/off LED */
+       switch (hw->mac.type) {
+       case e1000_82574:
+       case e1000_82583:
+               mac->ops.led_on = e1000e_led_on_82574;
+               break;
+       default:
+               mac->ops.led_on = e1000e_led_on_generic;
+               break;
+       }
+       mac->ops.led_off = e1000e_led_off_generic;
+       /* clear hardware counters */
+       mac->ops.clear_hw_cntrs = e1000e_clear_hw_cntrs_82571;
+       /* link info */
+       mac->ops.get_link_up_info =
+               (hw->phy.media_type == e1000_media_type_copper)
+                       ? e1000e_get_speed_and_duplex_copper
+                       : e1000e_get_speed_and_duplex_fiber_serdes;
+
+       /*
+        * Ensure that the inter-port SWSM.SMBI lock bit is clear before
+        * first NVM or PHY acess. This should be done for single-port
+        * devices, and for one port only on dual-port devices so that
+        * for those devices we can still use the SMBI lock to synchronize
+        * inter-port accesses to the PHY & NVM.
+        */
+       switch (hw->mac.type) {
+       case e1000_82571:
+       case e1000_82572:
+               swsm2 = er32(SWSM2);
+
+               if (!(swsm2 & E1000_SWSM2_LOCK)) {
+                       /* Only do this for the first interface on this card */
+                       ew32(SWSM2,
+                           swsm2 | E1000_SWSM2_LOCK);
+                       force_clear_smbi = true;
+               } else
+                       force_clear_smbi = false;
+               break;
+       default:
+               force_clear_smbi = true;
+               break;
+       }
+
+       if (force_clear_smbi) {
+               /* Make sure SWSM.SMBI is clear */
+               swsm = er32(SWSM);
+               if (swsm & E1000_SWSM_SMBI) {
+                       /* This bit should not be set on a first interface, and
+                        * indicates that the bootagent or EFI code has
+                        * improperly left this bit enabled
+                        */
+                       e_dbg("Please update your 82571 Bootagent\n");
+               }
+               ew32(SWSM, swsm & ~E1000_SWSM_SMBI);
+       }
+
+       /*
+        * Initialze device specific counter of SMBI acquisition
+        * timeouts.
+        */
+        hw->dev_spec._82571.smb_counter = 0;
+
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000e_init_function_pointers_82571 - Init func ptrs.
+ *  @hw: pointer to the HW structure
+ *
+ *  Called to initialize all function pointers and parameters.
+ **/
+void e1000e_init_function_pointers_82571(struct e1000_hw *hw)
+{
+       e1000e_init_mac_ops_generic(hw);
+       e1000e_init_nvm_ops_generic(hw);
+       hw->mac.ops.init_params = e1000e_init_mac_params_82571;
+       hw->nvm.ops.init_params = e1000e_init_nvm_params_82571;
+       hw->phy.ops.init_params = e1000e_init_phy_params_82571;
+}
+
+/**
+ *  e1000e_get_phy_id_82571 - Retrieve the PHY ID and revision
+ *  @hw: pointer to the HW structure
+ *
+ *  Reads the PHY registers and stores the PHY ID and possibly the PHY
+ *  revision in the hardware structure.
+ **/
+static s32 e1000e_get_phy_id_82571(struct e1000_hw *hw)
+{
+       struct e1000_phy_info *phy = &hw->phy;
+       s32 ret_val = E1000_SUCCESS;
+       u16 phy_id = 0;
+
+       switch (hw->mac.type) {
+       case e1000_82571:
+       case e1000_82572:
+               /*
+                * The 82571 firmware may still be configuring the PHY.
+                * In this case, we cannot access the PHY until the
+                * configuration is done.  So we explicitly set the
+                * PHY ID.
+                */
+               phy->id = IGP01E1000_I_PHY_ID;
+               break;
+       case e1000_82573:
+               ret_val = e1000e_get_phy_id(hw);
+               break;
+       case e1000_82574:
+       case e1000_82583:
+               ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);
+               if (ret_val)
+                       goto out;
+
+               phy->id = (u32)(phy_id << 16);
+               udelay(20);
+               ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);
+               if (ret_val)
+                       goto out;
+
+               phy->id |= (u32)(phy_id);
+               phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
+               break;
+       default:
+               ret_val = -E1000_ERR_PHY;
+               break;
+       }
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000e_get_hw_semaphore_82571 - Acquire hardware semaphore
+ *  @hw: pointer to the HW structure
+ *
+ *  Acquire the HW semaphore to access the PHY or NVM
+ **/
+s32 e1000e_get_hw_semaphore_82571(struct e1000_hw *hw)
+{
+       u32 swsm;
+       s32 ret_val = E1000_SUCCESS;
+       s32 sw_timeout = hw->nvm.word_size + 1;
+       s32 fw_timeout = hw->nvm.word_size + 1;
+       s32 i = 0;
+
+       /*
+        * If we have timedout 3 times on trying to acquire
+        * the inter-port SMBI semaphore, there is old code
+        * operating on the other port, and it is not
+        * releasing SMBI. Modify the number of times that
+        * we try for the semaphore to interwork with this
+        * older code.
+        */
+       if (hw->dev_spec._82571.smb_counter > 2)
+               sw_timeout = 1;
+
+       /* Get the SW semaphore */
+       while (i < sw_timeout) {
+               swsm = er32(SWSM);
+               if (!(swsm & E1000_SWSM_SMBI))
+                       break;
+
+               udelay(50);
+               i++;
+       }
+
+       if (i == sw_timeout) {
+               e_dbg("Driver can't access device - SMBI bit is set.\n");
+               hw->dev_spec._82571.smb_counter++;
+       }
+       /* Get the FW semaphore. */
+       for (i = 0; i < fw_timeout; i++) {
+               swsm = er32(SWSM);
+               ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
+
+               /* Semaphore acquired if bit latched */
+               if (er32(SWSM) & E1000_SWSM_SWESMBI)
+                       break;
+
+               udelay(50);
+       }
+
+       if (i == fw_timeout) {
+               /* Release semaphores */
+               e1000e_put_hw_semaphore_82571(hw);
+               e_dbg("Driver can't access the NVM\n");
+               ret_val = -E1000_ERR_NVM;
+               goto out;
+       }
+
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000e_put_hw_semaphore_82571 - Release hardware semaphore
+ *  @hw: pointer to the HW structure
+ *
+ *  Release hardware semaphore used to access the PHY or NVM
+ **/
+void e1000e_put_hw_semaphore_82571(struct e1000_hw *hw)
+{
+       u32 swsm;
+
+       swsm = er32(SWSM);
+       swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
+       ew32(SWSM, swsm);
+}
+
+/**
+ *  e1000e_acquire_nvm_82571 - Request for access to the EEPROM
+ *  @hw: pointer to the HW structure
+ *
+ *  To gain access to the EEPROM, first we must obtain a hardware semaphore.
+ *  Then for non-82573 hardware, set the EEPROM access request bit and wait
+ *  for EEPROM access grant bit.  If the access grant bit is not set, release
+ *  hardware semaphore.
+ **/
+static s32 e1000e_acquire_nvm_82571(struct e1000_hw *hw)
+{
+       s32 ret_val;
+
+       ret_val = e1000e_get_hw_semaphore_82571(hw);
+       if (ret_val)
+               goto out;
+
+       switch (hw->mac.type) {
+       case e1000_82574:
+       case e1000_82583:
+       case e1000_82573:
+               break;
+       default:
+               ret_val = e1000e_acquire_nvm(hw);
+               break;
+       }
+
+       if (ret_val)
+               e1000e_put_hw_semaphore_82571(hw);
+
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000e_release_nvm_82571 - Release exclusive access to EEPROM
+ *  @hw: pointer to the HW structure
+ *
+ *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
+ **/
+static void e1000e_release_nvm_82571(struct e1000_hw *hw)
+{
+       e1000e_release_nvm(hw);
+       e1000e_put_hw_semaphore_82571(hw);
+}
+
+/**
+ *  e1000e_write_nvm_82571 - Write to EEPROM using appropriate interface
+ *  @hw: pointer to the HW structure
+ *  @offset: offset within the EEPROM to be written to
+ *  @words: number of words to write
+ *  @data: 16 bit word(s) to be written to the EEPROM
+ *
+ *  For non-82573 silicon, write data to EEPROM at offset using SPI interface.
+ *
+ *  If e1000e_update_nvm_checksum is not called after this function, the
+ *  EEPROM will most likely contain an invalid checksum.
+ **/
+static s32 e1000e_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
+                                 u16 *data)
+{
+       s32 ret_val = E1000_SUCCESS;
+
+       switch (hw->mac.type) {
+       case e1000_82573:
+       case e1000_82574:
+       case e1000_82583:
+               ret_val = e1000e_write_nvm_eewr_82571(hw, offset, words, data);
+               break;
+       case e1000_82571:
+       case e1000_82572:
+               ret_val = e1000e_write_nvm_spi(hw, offset, words, data);
+               break;
+       default:
+               ret_val = -E1000_ERR_NVM;
+               break;
+       }
+
+       return ret_val;
+}
+
+/**
+ *  e1000e_update_nvm_checksum_82571 - Update EEPROM checksum
+ *  @hw: pointer to the HW structure
+ *
+ *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
+ *  up to the checksum.  Then calculates the EEPROM checksum and writes the
+ *  value to the EEPROM.
+ **/
+static s32 e1000e_update_nvm_checksum_82571(struct e1000_hw *hw)
+{
+       u32 eecd;
+       s32 ret_val;
+       u16 i;
+
+       ret_val = e1000e_update_nvm_checksum_generic(hw);
+       if (ret_val)
+               goto out;
+
+       /*
+        * If our nvm is an EEPROM, then we're done
+        * otherwise, commit the checksum to the flash NVM.
+        */
+       if (hw->nvm.type != e1000_nvm_flash_hw)
+               goto out;
+
+       /* Check for pending operations. */
+       for (i = 0; i < E1000_FLASH_UPDATES; i++) {
+               msleep(1);
+               if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
+                       break;
+       }
+
+       if (i == E1000_FLASH_UPDATES) {
+               ret_val = -E1000_ERR_NVM;
+               goto out;
+       }
+
+       /* Reset the firmware if using STM opcode. */
+       if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) {
+               /*
+                * The enabling of and the actual reset must be done
+                * in two write cycles.
+                */
+               ew32(HICR, E1000_HICR_FW_RESET_ENABLE);
+               e1e_flush();
+               ew32(HICR, E1000_HICR_FW_RESET);
+       }
+
+       /* Commit the write to flash */
+       eecd = er32(EECD) | E1000_EECD_FLUPD;
+       ew32(EECD, eecd);
+
+       for (i = 0; i < E1000_FLASH_UPDATES; i++) {
+               msleep(1);
+               if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
+                       break;
+       }
+
+       if (i == E1000_FLASH_UPDATES) {
+               ret_val = -E1000_ERR_NVM;
+               goto out;
+       }
+
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000e_validate_nvm_checksum_82571 - Validate EEPROM checksum
+ *  @hw: pointer to the HW structure
+ *
+ *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
+ *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
+ **/
+static s32 e1000e_validate_nvm_checksum_82571(struct e1000_hw *hw)
+{
+       if (hw->nvm.type == e1000_nvm_flash_hw)
+               e1000e_fix_nvm_checksum_82571(hw);
+
+       return e1000e_validate_nvm_checksum_generic(hw);
+}
+
+/**
+ *  e1000e_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
+ *  @hw: pointer to the HW structure
+ *  @offset: offset within the EEPROM to be written to
+ *  @words: number of words to write
+ *  @data: 16 bit word(s) to be written to the EEPROM
+ *
+ *  After checking for invalid values, poll the EEPROM to ensure the previous
+ *  command has completed before trying to write the next word.  After write
+ *  poll for completion.
+ *
+ *  If e1000e_update_nvm_checksum is not called after this function, the
+ *  EEPROM will most likely contain an invalid checksum.
+ **/
+static s32 e1000e_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
+                                      u16 words, u16 *data)
+{
+       struct e1000_nvm_info *nvm = &hw->nvm;
+       u32 i, eewr = 0;
+       s32 ret_val = 0;
+
+       /*
+        * A check for invalid values:  offset too large, too many words,
+        * and not enough words.
+        */
+       if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
+           (words == 0)) {
+               e_dbg("nvm parameter(s) out of bounds\n");
+               ret_val = -E1000_ERR_NVM;
+               goto out;
+       }
+
+       for (i = 0; i < words; i++) {
+               eewr = (data[i] << E1000_NVM_RW_REG_DATA) |
+                      ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |
+                      E1000_NVM_RW_REG_START;
+
+               ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
+               if (ret_val)
+                       break;
+
+               ew32(EEWR, eewr);
+
+               ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
+               if (ret_val)
+                       break;
+       }
+
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000e_get_cfg_done_82571 - Poll for configuration done
+ *  @hw: pointer to the HW structure
+ *
+ *  Reads the management control register for the config done bit to be set.
+ **/
+static s32 e1000e_get_cfg_done_82571(struct e1000_hw *hw)
+{
+       s32 timeout = PHY_CFG_TIMEOUT;
+       s32 ret_val = E1000_SUCCESS;
+
+       while (timeout) {
+               if (er32(EEMNGCTL) & E1000_NVM_CFG_DONE_PORT_0)
+                       break;
+               msleep(1);
+               timeout--;
+       }
+       if (!timeout) {
+               e_dbg("MNG configuration cycle has not completed.\n");
+               ret_val = -E1000_ERR_RESET;
+               goto out;
+       }
+
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000e_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
+ *  @hw: pointer to the HW structure
+ *  @active: true to enable LPLU, false to disable
+ *
+ *  Sets the LPLU D0 state according to the active flag.  When activating LPLU
+ *  this function also disables smart speed and vice versa.  LPLU will not be
+ *  activated unless the device autonegotiation advertisement meets standards
+ *  of either 10 or 10/100 or 10/100/1000 at all duplexes.  This is a function
+ *  pointer entry point only called by PHY setup routines.
+ **/
+static s32 e1000e_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
+{
+       struct e1000_phy_info *phy = &hw->phy;
+       s32 ret_val = E1000_SUCCESS;
+       u16 data;
+
+       if (!(phy->ops.read_reg))
+               goto out;
+
+       ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
+       if (ret_val)
+               goto out;
+
+       if (active) {
+               data |= IGP02E1000_PM_D0_LPLU;
+               ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT,
+                                            data);
+               if (ret_val)
+                       goto out;
+
+               /* When LPLU is enabled, we should disable SmartSpeed */
+               ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
+                                           &data);
+               data &= ~IGP01E1000_PSCFR_SMART_SPEED;
+               ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
+                                            data);
+               if (ret_val)
+                       goto out;
+       } else {
+               data &= ~IGP02E1000_PM_D0_LPLU;
+               ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT,
+                                            data);
+               /*
+                * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
+                * during Dx states where the power conservation is most
+                * important.  During driver activity we should enable
+                * SmartSpeed, so performance is maintained.
+                */
+               if (phy->smart_speed == e1000_smart_speed_on) {
+                       ret_val = e1e_rphy(hw,
+                                                   IGP01E1000_PHY_PORT_CONFIG,
+                                                   &data);
+                       if (ret_val)
+                               goto out;
+
+                       data |= IGP01E1000_PSCFR_SMART_SPEED;
+                       ret_val = e1e_wphy(hw,
+                                                    IGP01E1000_PHY_PORT_CONFIG,
+                                                    data);
+                       if (ret_val)
+                               goto out;
+               } else if (phy->smart_speed == e1000_smart_speed_off) {
+                       ret_val = e1e_rphy(hw,
+                                                   IGP01E1000_PHY_PORT_CONFIG,
+                                                   &data);
+                       if (ret_val)
+                               goto out;
+
+                       data &= ~IGP01E1000_PSCFR_SMART_SPEED;
+                       ret_val = e1e_wphy(hw,
+                                                    IGP01E1000_PHY_PORT_CONFIG,
+                                                    data);
+                       if (ret_val)
+                               goto out;
+               }
+       }
+
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000e_reset_hw_82571 - Reset hardware
+ *  @hw: pointer to the HW structure
+ *
+ *  This resets the hardware into a known state.
+ **/
+static s32 e1000e_reset_hw_82571(struct e1000_hw *hw)
+{
+       u32 ctrl, extcnf_ctrl, ctrl_ext, icr;
+       s32 ret_val;
+       u16 i = 0;
+
+       /*
+        * Prevent the PCI-E bus from sticking if there is no TLP connection
+        * on the last TLP read/write transaction when MAC is reset.
+        */
+       ret_val = e1000e_disable_pcie_master(hw);
+       if (ret_val)
+               e_dbg("PCI-E Master disable polling has failed.\n");
+
+       e_dbg("Masking off all interrupts\n");
+       ew32(IMC, 0xffffffff);
+
+       ew32(RCTL, 0);
+       ew32(TCTL, E1000_TCTL_PSP);
+       e1e_flush();
+
+       msleep(10);
+
+       /*
+        * Must acquire the MDIO ownership before MAC reset.
+        * Ownership defaults to firmware after a reset.
+        */
+       switch (hw->mac.type) {
+       case e1000_82574:
+       case e1000_82583:
+       case e1000_82573:
+               extcnf_ctrl = er32(EXTCNF_CTRL);
+               extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
+
+               do {
+                       ew32(EXTCNF_CTRL, extcnf_ctrl);
+                       extcnf_ctrl = er32(EXTCNF_CTRL);
+
+                       if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
+                               break;
+
+                       extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
+
+                       msleep(2);
+                       i++;
+               } while (i < MDIO_OWNERSHIP_TIMEOUT);
+               break;
+       default:
+               break;
+       }
+
+       ctrl = er32(CTRL);
+
+       e_dbg("Issuing a global reset to MAC\n");
+       ew32(CTRL, ctrl | E1000_CTRL_RST);
+
+       if (hw->nvm.type == e1000_nvm_flash_hw) {
+               udelay(10);
+               ctrl_ext = er32(CTRL_EXT);
+               ctrl_ext |= E1000_CTRL_EXT_EE_RST;
+               ew32(CTRL_EXT, ctrl_ext);
+               e1e_flush();
+       }
+
+       ret_val = e1000e_get_auto_rd_done(hw);
+       if (ret_val)
+               /* We don't want to continue accessing MAC registers. */
+               goto out;
+
+       /*
+        * Phy configuration from NVM just starts after EECD_AUTO_RD is set.
+        * Need to wait for Phy configuration completion before accessing
+        * NVM and Phy.
+        */
+
+       switch (hw->mac.type) {
+       case e1000_82574:
+       case e1000_82583:
+       case e1000_82573:
+               msleep(25);
+               break;
+       default:
+               break;
+       }
+
+       /* Clear any pending interrupt events. */
+       ew32(IMC, 0xffffffff);
+       icr = er32(ICR);
+
+       /* Install any alternate MAC address into RAR0 */
+       ret_val = e1000e_check_alt_mac_addr_generic(hw);
+       if (ret_val)
+               goto out;
+
+       e1000e_set_laa_state_82571(hw, true);
+
+       /* Reinitialize the 82571 serdes link state machine */
+       if (hw->phy.media_type == e1000_media_type_internal_serdes)
+               hw->mac.serdes_link_state = e1000_serdes_link_down;
+
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000e_init_hw_82571 - Initialize hardware
+ *  @hw: pointer to the HW structure
+ *
+ *  This inits the hardware readying it for operation.
+ **/
+static s32 e1000e_init_hw_82571(struct e1000_hw *hw)
+{
+       struct e1000_mac_info *mac = &hw->mac;
+       u32 reg_data;
+       s32 ret_val;
+       u16 i, rar_count = mac->rar_entry_count;
+
+       e1000e_initialize_hw_bits_82571(hw);
+
+       /* Initialize identification LED */
+       ret_val = mac->ops.id_led_init(hw);
+       if (ret_val) {
+               e_dbg("Error initializing identification LED\n");
+               /* This is not fatal and we should not stop init due to this */
+       }
+
+       /* Disabling VLAN filtering */
+       e_dbg("Initializing the IEEE VLAN\n");
+       e1000e_clear_vfta(hw);
+
+       /* Setup the receive address. */
+       /*
+        * If, however, a locally administered address was assigned to the
+        * 82571, we must reserve a RAR for it to work around an issue where
+        * resetting one port will reload the MAC on the other port.
+        */
+       if (e1000e_get_laa_state_82571(hw))
+               rar_count--;
+       e1000e_init_rx_addrs(hw, rar_count);
+
+       /* Zero out the Multicast HASH table */
+       e_dbg("Zeroing the MTA\n");
+       for (i = 0; i < mac->mta_reg_count; i++)
+               E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
+
+       /* Setup link and flow control */
+       ret_val = mac->ops.setup_link(hw);
+
+       /* Set the transmit descriptor write-back policy */
+       reg_data = er32(TXDCTL(0));
+       reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
+                  E1000_TXDCTL_FULL_TX_DESC_WB |
+                  E1000_TXDCTL_COUNT_DESC;
+       ew32(TXDCTL(0), reg_data);
+
+       /* ...for both queues. */
+       switch (mac->type) {
+       case e1000_82574:
+       case e1000_82583:
+       case e1000_82573:
+#if 0
+               e1000e_enable_tx_pkt_filtering(hw);
+#endif
+               reg_data = er32(GCR);
+               reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
+               ew32(GCR, reg_data);
+               break;
+       default:
+               reg_data = er32(TXDCTL(1));
+               reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
+                                       E1000_TXDCTL_FULL_TX_DESC_WB |
+                                       E1000_TXDCTL_COUNT_DESC;
+               ew32(TXDCTL(1), reg_data);
+               break;
+       }
+
+       /*
+        * Clear all of the statistics registers (clear on read).  It is
+        * important that we do this after we have tried to establish link
+        * because the symbol error count will increment wildly if there
+        * is no link.
+        */
+       e1000e_clear_hw_cntrs_82571(hw);
+
+       return ret_val;
+}
+
+/**
+ *  e1000e_initialize_hw_bits_82571 - Initialize hardware-dependent bits
+ *  @hw: pointer to the HW structure
+ *
+ *  Initializes required hardware-dependent bits needed for normal operation.
+ **/
+static void e1000e_initialize_hw_bits_82571(struct e1000_hw *hw)
+{
+       u32 reg;
+
+       /* Transmit Descriptor Control 0 */
+       reg = er32(TXDCTL(0));
+       reg |= (1 << 22);
+       ew32(TXDCTL(0), reg);
+
+       /* Transmit Descriptor Control 1 */
+       reg = er32(TXDCTL(1));
+       reg |= (1 << 22);
+       ew32(TXDCTL(1), reg);
+
+       /* Transmit Arbitration Control 0 */
+       reg = er32(TARC(0));
+       reg &= ~(0xF << 27); /* 30:27 */
+       switch (hw->mac.type) {
+       case e1000_82571:
+       case e1000_82572:
+               reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
+               break;
+       default:
+               break;
+       }
+       ew32(TARC(0), reg);
+
+       /* Transmit Arbitration Control 1 */
+       reg = er32(TARC(1));
+       switch (hw->mac.type) {
+       case e1000_82571:
+       case e1000_82572:
+               reg &= ~((1 << 29) | (1 << 30));
+               reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
+               if (er32(TCTL) & E1000_TCTL_MULR)
+                       reg &= ~(1 << 28);
+               else
+                       reg |= (1 << 28);
+               ew32(TARC(1), reg);
+               break;
+       default:
+               break;
+       }
+
+       /* Device Control */
+
+       switch (hw->mac.type) {
+       case e1000_82574:
+       case e1000_82583:
+       case e1000_82573:
+               reg = er32(CTRL);
+               reg &= ~(1 << 29);
+               ew32(CTRL, reg);
+               break;
+       default:
+               break;
+       }
+
+       /* Extended Device Control */
+       switch (hw->mac.type) {
+       case e1000_82574:
+       case e1000_82583:
+       case e1000_82573:
+               reg = er32(CTRL_EXT);
+               reg &= ~(1 << 23);
+               reg |= (1 << 22);
+               ew32(CTRL_EXT, reg);
+               break;
+       default:
+               break;
+       }
+
+
+       if (hw->mac.type == e1000_82571) {
+               reg = er32(PBA_ECC);
+               reg |= E1000_PBA_ECC_CORR_EN;
+               ew32(PBA_ECC, reg);
+       }
+
+       /*
+        * Workaround for hardware errata.
+        * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
+        */
+
+       if ((hw->mac.type == e1000_82571) ||
+          (hw->mac.type == e1000_82572)) {
+               reg = er32(CTRL_EXT);
+               reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
+               ew32(CTRL_EXT, reg);
+       }
+
+       /* PCI-Ex Control Registers */
+
+       switch (hw->mac.type) {
+       case e1000_82574:
+       case e1000_82583:
+               reg = er32(GCR);
+               reg |= (1 << 22);
+               ew32(GCR, reg);
+               /*
+                * Workaround for hardware errata.
+                * apply workaround for hardware errata documented in errata
+                * docs Fixes issue where some error prone or unreliable PCIe
+                * completions are occurring, particularly with ASPM enabled.
+                * Without fix, issue can cause tx timeouts.
+                */
+               reg = er32(GCR2);
+               reg |= 1;
+               ew32(GCR2, reg);
+               break;
+       default:
+               break;
+       }
+       return;
+}
+
+/**
+ *  e1000e_clear_vfta_82571 - Clear VLAN filter table
+ *  @hw: pointer to the HW structure
+ *
+ *  Clears the register array which contains the VLAN filter table by
+ *  setting all the values to 0.
+ **/
+static void e1000e_clear_vfta_82571(struct e1000_hw *hw)
+{
+       u32 offset;
+       u32 vfta_value = 0;
+       u32 vfta_offset = 0;
+       u32 vfta_bit_in_reg = 0;
+
+       switch (hw->mac.type) {
+       case e1000_82574:
+       case e1000_82583:
+       case e1000_82573:
+               if (hw->mng_cookie.vlan_id != 0) {
+                       /*
+                       *The VFTA is a 4096b bit-field, each identifying
+                       *a single VLAN ID.  The following operations
+                       *determine which 32b entry (i.e. offset) into the
+                       *array we want to set the VLAN ID (i.e. bit) of
+                       *the manageability unit.
+                       */
+                       vfta_offset = (hw->mng_cookie.vlan_id >>
+                               E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK;
+                       vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
+                               E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
+               }
+
+               for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
+                       /*
+                       *If the offset we want to clear is the same offset of
+                       *the manageability VLAN ID, then clear all bits except
+                       *that of the manageability unit
+                       */
+                       vfta_value = (offset == vfta_offset) ?
+                                                       vfta_bit_in_reg : 0;
+                       E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset,
+                               vfta_value);
+                       e1e_flush();
+               }
+               break;
+       default:
+               break;
+       }
+}
+
+#if 0
+/**
+ *  e1000e_check_mng_mode_82574 - Check manageability is enabled
+ *  @hw: pointer to the HW structure
+ *
+ *  Reads the NVM Initialization Control Word 2 and returns true
+ *  (>0) if any manageability is enabled, else false (0).
+ **/
+static bool e1000e_check_mng_mode_82574(struct e1000_hw *hw)
+{
+       u16 data;
+
+       e1000e_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
+       return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
+}
+#endif
+
+/**
+ *  e1000e_led_on_82574 - Turn LED on
+ *  @hw: pointer to the HW structure
+ *
+ *  Turn LED on.
+ **/
+static s32 e1000e_led_on_82574(struct e1000_hw *hw __unused)
+{
+#if 0
+       u32 ctrl;
+       u32 i;
+
+       ctrl = hw->mac.ledctl_mode2;
+       if (!(E1000_STATUS_LU & er32(STATUS))) {
+               /*
+                * If no link, then turn LED on by setting the invert bit
+                * for each LED that's "on" (0x0E) in ledctl_mode2.
+                */
+               for (i = 0; i < 4; i++)
+                       if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
+                           E1000_LEDCTL_MODE_LED_ON)
+                               ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
+       }
+       ew32(LEDCTL, ctrl);
+#endif
+       return E1000_SUCCESS;
+}
+
+/**
+ *  e1000e_setup_link_82571 - Setup flow control and link settings
+ *  @hw: pointer to the HW structure
+ *
+ *  Determines which flow control settings to use, then configures flow
+ *  control.  Calls the appropriate media-specific link configuration
+ *  function.  Assuming the adapter has a valid link partner, a valid link
+ *  should be established.  Assumes the hardware has previously been reset
+ *  and the transmitter and receiver are not enabled.
+ **/
+static s32 e1000e_setup_link_82571(struct e1000_hw *hw)
+{
+       /*
+        * 82573 does not have a word in the NVM to determine
+        * the default flow control setting, so we explicitly
+        * set it to full.
+        */
+       switch (hw->mac.type) {
+       case e1000_82574:
+       case e1000_82583:
+       case e1000_82573:
+               if (hw->fc.requested_mode == e1000_fc_default)
+                       hw->fc.requested_mode = e1000_fc_full;
+               break;
+       default:
+               break;
+       }
+       return e1000e_setup_link(hw);
+}
+
+/**
+ *  e1000e_setup_copper_link_82571 - Configure copper link settings
+ *  @hw: pointer to the HW structure
+ *
+ *  Configures the link for auto-neg or forced speed and duplex.  Then we check
+ *  for link, once link is established calls to configure collision distance
+ *  and flow control are called.
+ **/
+static s32 e1000e_setup_copper_link_82571(struct e1000_hw *hw)
+{
+       u32 ctrl;
+       s32  ret_val;
+
+       ctrl = er32(CTRL);
+       ctrl |= E1000_CTRL_SLU;
+       ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
+       ew32(CTRL, ctrl);
+
+       switch (hw->phy.type) {
+       case e1000_phy_m88:
+       case e1000_phy_bm:
+               ret_val = e1000e_copper_link_setup_m88(hw);
+               break;
+       case e1000_phy_igp_2:
+               ret_val = e1000e_copper_link_setup_igp(hw);
+               break;
+       default:
+               ret_val = -E1000_ERR_PHY;
+               break;
+       }
+
+       if (ret_val)
+               goto out;
+
+       ret_val = e1000e_setup_copper_link(hw);
+
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000e_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
+ *  @hw: pointer to the HW structure
+ *
+ *  Configures collision distance and flow control for fiber and serdes links.
+ *  Upon successful setup, poll for link.
+ **/
+static s32 e1000e_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
+{
+       switch (hw->mac.type) {
+       case e1000_82571:
+       case e1000_82572:
+               /*
+                * If SerDes loopback mode is entered, there is no form
+                * of reset to take the adapter out of that mode.  So we
+                * have to explicitly take the adapter out of loopback
+                * mode.  This prevents drivers from twiddling their thumbs
+                * if another tool failed to take it out of loopback mode.
+                */
+               ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
+               break;
+       default:
+               break;
+       }
+
+       return e1000e_setup_fiber_serdes_link(hw);
+}
+
+/**
+ *  e1000e_check_for_serdes_link_82571 - Check for link (Serdes)
+ *  @hw: pointer to the HW structure
+ *
+ *  Reports the link state as up or down.
+ *
+ *  If autonegotiation is supported by the link partner, the link state is
+ *  determined by the result of autongotiation. This is the most likely case.
+ *  If autonegotiation is not supported by the link partner, and the link
+ *  has a valid signal, force the link up.
+ *
+ *  The link state is represented internally here by 4 states:
+ *
+ *  1) down
+ *  2) autoneg_progress
+ *  3) autoneg_complete (the link sucessfully autonegotiated)
+ *  4) forced_up (the link has been forced up, it did not autonegotiate)
+ *
+ **/
+s32 e1000e_check_for_serdes_link_82571(struct e1000_hw *hw)
+{
+       struct e1000_mac_info *mac = &hw->mac;
+       u32 rxcw;
+       u32 ctrl;
+       u32 status;
+       s32 ret_val = E1000_SUCCESS;
+
+       ctrl = er32(CTRL);
+       status = er32(STATUS);
+       rxcw = er32(RXCW);
+
+       if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
+
+               /* Receiver is synchronized with no invalid bits.  */
+               switch (mac->serdes_link_state) {
+               case e1000_serdes_link_autoneg_complete:
+                       if (!(status & E1000_STATUS_LU)) {
+                               /*
+                                * We have lost link, retry autoneg before
+                                * reporting link failure
+                                */
+                               mac->serdes_link_state =
+                                   e1000_serdes_link_autoneg_progress;
+                               mac->serdes_has_link = false;
+                               e_dbg("AN_UP     -> AN_PROG\n");
+                       }
+               break;
+
+               case e1000_serdes_link_forced_up:
+                       /*
+                        * If we are receiving /C/ ordered sets, re-enable
+                        * auto-negotiation in the TXCW register and disable
+                        * forced link in the Device Control register in an
+                        * attempt to auto-negotiate with our link partner.
+                        */
+                       if (rxcw & E1000_RXCW_C) {
+                               /* Enable autoneg, and unforce link up */
+                               ew32(TXCW, mac->txcw);
+                               ew32(CTRL,
+                                   (ctrl & ~E1000_CTRL_SLU));
+                               mac->serdes_link_state =
+                                   e1000_serdes_link_autoneg_progress;
+                               mac->serdes_has_link = false;
+                               e_dbg("FORCED_UP -> AN_PROG\n");
+                       }
+                       break;
+
+               case e1000_serdes_link_autoneg_progress:
+                       if (rxcw & E1000_RXCW_C) {
+                               /* We received /C/ ordered sets, meaning the
+                                * link partner has autonegotiated, and we can
+                                * trust the Link Up (LU) status bit
+                                */
+                               if (status & E1000_STATUS_LU) {
+                                       mac->serdes_link_state =
+                                           e1000_serdes_link_autoneg_complete;
+                                       e_dbg("AN_PROG   -> AN_UP\n");
+                                       mac->serdes_has_link = true;
+                               } else {
+                                       /* Autoneg completed, but failed */
+                                       mac->serdes_link_state =
+                                           e1000_serdes_link_down;
+                                       e_dbg("AN_PROG   -> DOWN\n");
+                               }
+                       } else {
+                               /* The link partner did not autoneg.
+                                * Force link up and full duplex, and change
+                                * state to forced.
+                                */
+                               ew32(TXCW,
+                               (mac->txcw & ~E1000_TXCW_ANE));
+                               ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
+                               ew32(CTRL, ctrl);
+
+                               /* Configure Flow Control after link up. */
+                               ret_val =
+                                   e1000e_config_fc_after_link_up(hw);
+                               if (ret_val) {
+                                       e_dbg("Error config flow control\n");
+                                       break;
+                               }
+                               mac->serdes_link_state =
+                               e1000_serdes_link_forced_up;
+                               mac->serdes_has_link = true;
+                               e_dbg("AN_PROG   -> FORCED_UP\n");
+                       }
+                       break;
+
+               case e1000_serdes_link_down:
+               default:
+                       /* The link was down but the receiver has now gained
+                        * valid sync, so lets see if we can bring the link
+                        * up. */
+                       ew32(TXCW, mac->txcw);
+                       ew32(CTRL,
+                           (ctrl & ~E1000_CTRL_SLU));
+                       mac->serdes_link_state =
+                           e1000_serdes_link_autoneg_progress;
+                       e_dbg("DOWN      -> AN_PROG\n");
+                       break;
+               }
+       } else {
+               if (!(rxcw & E1000_RXCW_SYNCH)) {
+                       mac->serdes_has_link = false;
+                       mac->serdes_link_state = e1000_serdes_link_down;
+                       e_dbg("ANYSTATE  -> DOWN\n");
+               } else {
+                       /*
+                        * We have sync, and can tolerate one
+                        * invalid (IV) codeword before declaring
+                        * link down, so reread to look again
+                        */
+                       udelay(10);
+                       rxcw = er32(RXCW);
+                       if (rxcw & E1000_RXCW_IV) {
+                               mac->serdes_link_state = e1000_serdes_link_down;
+                               mac->serdes_has_link = false;
+                               e_dbg("ANYSTATE  -> DOWN\n");
+                       }
+               }
+       }
+
+       return ret_val;
+}
+
+/**
+ *  e1000e_valid_led_default_82571 - Verify a valid default LED config
+ *  @hw: pointer to the HW structure
+ *  @data: pointer to the NVM (EEPROM)
+ *
+ *  Read the EEPROM for the current default LED configuration.  If the
+ *  LED configuration is not valid, set to a valid LED configuration.
+ **/
+static s32 e1000e_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
+{
+       s32 ret_val;
+
+       ret_val = e1000e_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
+       if (ret_val) {
+               e_dbg("NVM Read Error\n");
+               goto out;
+       }
+
+       switch (hw->mac.type) {
+       case e1000_82574:
+       case e1000_82583:
+       case e1000_82573:
+               if(*data == ID_LED_RESERVED_F746)
+                       *data = ID_LED_DEFAULT_82573;
+               break;
+       default:
+               if (*data == ID_LED_RESERVED_0000 ||
+                       *data == ID_LED_RESERVED_FFFF)
+                       *data = ID_LED_DEFAULT;
+               break;
+       }
+
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000e_get_laa_state_82571 - Get locally administered address state
+ *  @hw: pointer to the HW structure
+ *
+ *  Retrieve and return the current locally administered address state.
+ **/
+bool e1000e_get_laa_state_82571(struct e1000_hw *hw)
+{
+       if (hw->mac.type != e1000_82571)
+               return false;
+
+       return hw->dev_spec._82571.laa_is_present;
+}
+
+/**
+ *  e1000e_set_laa_state_82571 - Set locally administered address state
+ *  @hw: pointer to the HW structure
+ *  @state: enable/disable locally administered address
+ *
+ *  Enable/Disable the current locally administered address state.
+ **/
+void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state)
+{
+       if (hw->mac.type != e1000_82571)
+               return;
+
+       hw->dev_spec._82571.laa_is_present = state;
+
+       /* If workaround is activated... */
+       if (state)
+               /*
+                * Hold a copy of the LAA in RAR[14] This is done so that
+                * between the time RAR[0] gets clobbered and the time it
+                * gets fixed, the actual LAA is in one of the RARs and no
+                * incoming packets directed to this port are dropped.
+                * Eventually the LAA will be in RAR[0] and RAR[14].
+                */
+               e1000e_rar_set(hw, hw->mac.addr,
+                                     hw->mac.rar_entry_count - 1);
+       return;
+}
+
+/**
+ *  e1000e_fix_nvm_checksum_82571 - Fix EEPROM checksum
+ *  @hw: pointer to the HW structure
+ *
+ *  Verifies that the EEPROM has completed the update.  After updating the
+ *  EEPROM, we need to check bit 15 in work 0x23 for the checksum fix.  If
+ *  the checksum fix is not implemented, we need to set the bit and update
+ *  the checksum.  Otherwise, if bit 15 is set and the checksum is incorrect,
+ *  we need to return bad checksum.
+ **/
+static s32 e1000e_fix_nvm_checksum_82571(struct e1000_hw *hw)
+{
+       struct e1000_nvm_info *nvm = &hw->nvm;
+       s32 ret_val = E1000_SUCCESS;
+       u16 data;
+
+       if (nvm->type != e1000_nvm_flash_hw)
+               goto out;
+
+       /*
+        * Check bit 4 of word 10h.  If it is 0, firmware is done updating
+        * 10h-12h.  Checksum may need to be fixed.
+        */
+       ret_val = e1000e_read_nvm(hw, 0x10, 1, &data);
+       if (ret_val)
+               goto out;
+
+       if (!(data & 0x10)) {
+               /*
+                * Read 0x23 and check bit 15.  This bit is a 1
+                * when the checksum has already been fixed.  If
+                * the checksum is still wrong and this bit is a
+                * 1, we need to return bad checksum.  Otherwise,
+                * we need to set this bit to a 1 and update the
+                * checksum.
+                */
+               ret_val = e1000e_read_nvm(hw, 0x23, 1, &data);
+               if (ret_val)
+                       goto out;
+
+               if (!(data & 0x8000)) {
+                       data |= 0x8000;
+                       ret_val = e1000e_write_nvm(hw, 0x23, 1, &data);
+                       if (ret_val)
+                               goto out;
+                       ret_val = e1000e_update_nvm_checksum(hw);
+               }
+       }
+
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000e_read_mac_addr_82571 - Read device MAC address
+ *  @hw: pointer to the HW structure
+ **/
+static s32 e1000e_read_mac_addr_82571(struct e1000_hw *hw)
+{
+       s32 ret_val = E1000_SUCCESS;
+
+       /*
+        * If there's an alternate MAC address place it in RAR0
+        * so that it will override the Si installed default perm
+        * address.
+        */
+       ret_val = e1000e_check_alt_mac_addr_generic(hw);
+       if (ret_val)
+               goto out;
+
+       ret_val = e1000e_read_mac_addr_generic(hw);
+
+out:
+       return ret_val;
+}
+
+/**
+ * e1000e_power_down_phy_copper_82571 - Remove link during PHY power down
+ * @hw: pointer to the HW structure
+ *
+ * In the case of a PHY power down to save power, or to turn off link during a
+ * driver unload, or wake on lan is not enabled, remove the link.
+ **/
+static void e1000e_power_down_phy_copper_82571(struct e1000_hw *hw)
+{
+       struct e1000_phy_info *phy = &hw->phy;
+       struct e1000_mac_info *mac = &hw->mac;
+
+       if (!(phy->ops.check_reset_block))
+               return;
+
+       /* If the management interface is not enabled, then power down */
+       if (!(mac->ops.check_mng_mode(hw) || e1000e_check_reset_block(hw)))
+               e1000e_power_down_phy_copper(hw);
+
+       return;
+}
+
+/**
+ *  e1000e_clear_hw_cntrs_82571 - Clear device specific hardware counters
+ *  @hw: pointer to the HW structure
+ *
+ *  Clears the hardware counters by reading the counter registers.
+ **/
+static void e1000e_clear_hw_cntrs_82571(struct e1000_hw *hw __unused)
+{
+#if 0
+       e1000e_clear_hw_cntrs_base(hw);
+
+       er32(PRC64);
+       er32(PRC127);
+       er32(PRC255);
+       er32(PRC511);
+       er32(PRC1023);
+       er32(PRC1522);
+       er32(PTC64);
+       er32(PTC127);
+       er32(PTC255);
+       er32(PTC511);
+       er32(PTC1023);
+       er32(PTC1522);
+
+       er32(ALGNERRC);
+       er32(RXERRC);
+       er32(TNCRS);
+       er32(CEXTERR);
+       er32(TSCTC);
+       er32(TSCTFC);
+
+       er32(MGTPRC);
+       er32(MGTPDC);
+       er32(MGTPTC);
+
+       er32(IAC);
+       er32(ICRXOC);
+
+       er32(ICRXPTC);
+       er32(ICRXATC);
+       er32(ICTXPTC);
+       er32(ICTXATC);
+       er32(ICTXQEC);
+       er32(ICTXQMTC);
+       er32(ICRXDMTC);
+#endif
+}
+
+static struct pci_device_id e1000e_82571_nics[] = {
+     PCI_ROM(0x8086, 0x105E, "E1000_DEV_ID_82571EB_COPPER", "E1000_DEV_ID_82571EB_COPPER", board_82571),
+     PCI_ROM(0x8086, 0x105F, "E1000_DEV_ID_82571EB_FIBER", "E1000_DEV_ID_82571EB_FIBER", board_82571),
+     PCI_ROM(0x8086, 0x10A4, "E1000_DEV_ID_82571EB_QUAD_COPPER", "E1000_DEV_ID_82571EB_QUAD_COPPER", board_82571),
+     PCI_ROM(0x8086, 0x10BC, "E1000_DEV_ID_82571EB_QUAD_COPPER_LP", "E1000_DEV_ID_82571EB_QUAD_COPPER_LP", board_82571),
+     PCI_ROM(0x8086, 0x10A5, "E1000_DEV_ID_82571EB_QUAD_FIBER", "E1000_DEV_ID_82571EB_QUAD_FIBER", board_82571),
+     PCI_ROM(0x8086, 0x1060, "E1000_DEV_ID_82571EB_SERDES", "E1000_DEV_ID_82571EB_SERDES", board_82571),
+     PCI_ROM(0x8086, 0x10D9, "E1000_DEV_ID_82571EB_SERDES_DUAL", "E1000_DEV_ID_82571EB_SERDES_DUAL", board_82571),
+     PCI_ROM(0x8086, 0x10DA, "E1000_DEV_ID_82571EB_SERDES_QUAD", "E1000_DEV_ID_82571EB_SERDES_QUAD", board_82571),
+     PCI_ROM(0x8086, 0x10D5, "E1000_DEV_ID_82571PT_QUAD_COPPER", "E1000_DEV_ID_82571PT_QUAD_COPPER", board_82571),
+     PCI_ROM(0x8086, 0x10B9, "E1000_DEV_ID_82572EI", "E1000_DEV_ID_82572EI", board_82572),
+     PCI_ROM(0x8086, 0x107D, "E1000_DEV_ID_82572EI_COPPER", "E1000_DEV_ID_82572EI_COPPER", board_82572),
+     PCI_ROM(0x8086, 0x107E, "E1000_DEV_ID_82572EI_FIBER", "E1000_DEV_ID_82572EI_FIBER", board_82572),
+     PCI_ROM(0x8086, 0x107F, "E1000_DEV_ID_82572EI_SERDES", "E1000_DEV_ID_82572EI_SERDES", board_82572),
+     PCI_ROM(0x8086, 0x108B, "E1000_DEV_ID_82573E", "E1000_DEV_ID_82573E", board_82573),
+     PCI_ROM(0x8086, 0x108C, "E1000_DEV_ID_82573E_IAMT", "E1000_DEV_ID_82573E_IAMT", board_82573),
+     PCI_ROM(0x8086, 0x109A, "E1000_DEV_ID_82573L", "E1000_DEV_ID_82573L", board_82573),
+     PCI_ROM(0x8086, 0x10D3, "E1000_DEV_ID_82574L", "E1000_DEV_ID_82574L", board_82574),
+     PCI_ROM(0x8086, 0x10F6, "E1000_DEV_ID_82574LA", "E1000_DEV_ID_82574LA", board_82574),
+     PCI_ROM(0x8086, 0x150C, "E1000_DEV_ID_82583V", "E1000_DEV_ID_82583V", board_82583),
+};
+
+struct pci_driver e1000e_82571_driver __pci_driver = {
+       .ids = e1000e_82571_nics,
+       .id_count = (sizeof (e1000e_82571_nics) / sizeof (e1000e_82571_nics[0])),
+       .probe = e1000e_probe,
+       .remove = e1000e_remove,
+};
diff --git a/src/drivers/net/e1000e/e1000e_82571.h b/src/drivers/net/e1000e/e1000e_82571.h
new file mode 100644 (file)
index 0000000..c645e25
--- /dev/null
@@ -0,0 +1,55 @@
+/*******************************************************************************
+
+  Intel PRO/1000 Linux driver
+  Copyright(c) 1999 - 2009 Intel Corporation.
+
+  This program is free software; you can redistribute it and/or modify it
+  under the terms and conditions of the GNU General Public License,
+  version 2, as published by the Free Software Foundation.
+
+  This program is distributed in the hope it will be useful, but WITHOUT
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+  more details.
+
+  You should have received a copy of the GNU General Public License along with
+  this program; if not, write to the Free Software Foundation, Inc.,
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+
+  The full GNU General Public License is included in this distribution in
+  the file called "COPYING".
+
+  Contact Information:
+  Linux NICS <linux.nics@intel.com>
+  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+
+*******************************************************************************/
+
+FILE_LICENCE ( GPL2_OR_LATER );
+
+#ifndef _E1000E_82571_H_
+#define _E1000E_82571_H_
+
+#define ID_LED_RESERVED_F746 0xF746
+#define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \
+                              (ID_LED_OFF1_ON2  <<  8) | \
+                              (ID_LED_DEF1_DEF2 <<  4) | \
+                              (ID_LED_DEF1_DEF2))
+
+#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
+
+/* Intr Throttling - RW */
+#define E1000_EITR_82574(_n)    (0x000E8 + (0x4 * (_n)))
+
+#define E1000_EIAC_82574        0x000DC /* Ext. Interrupt Auto Clear - RW */
+#define E1000_EIAC_MASK_82574   0x01F00000
+
+#define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */
+
+#define E1000_RXCFGL    0x0B634 /* TimeSync Rx EtherType & Msg Type Reg - RW */
+
+bool e1000e_get_laa_state_82571(struct e1000_hw *hw);
+void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state);
+
+#endif
diff --git a/src/drivers/net/e1000e/e1000e_defines.h b/src/drivers/net/e1000e/e1000e_defines.h
new file mode 100644 (file)
index 0000000..da135d9
--- /dev/null
@@ -0,0 +1,1469 @@
+/*******************************************************************************
+
+  Intel PRO/1000 Linux driver
+  Copyright(c) 1999 - 2009 Intel Corporation.
+
+  This program is free software; you can redistribute it and/or modify it
+  under the terms and conditions of the GNU General Public License,
+  version 2, as published by the Free Software Foundation.
+
+  This program is distributed in the hope it will be useful, but WITHOUT
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+  more details.
+
+  You should have received a copy of the GNU General Public License along with
+  this program; if not, write to the Free Software Foundation, Inc.,
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+
+  The full GNU General Public License is included in this distribution in
+  the file called "COPYING".
+
+  Contact Information:
+  Linux NICS <linux.nics@intel.com>
+  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+
+*******************************************************************************/
+
+FILE_LICENCE ( GPL2_OR_LATER );
+
+#ifndef _E1000E_DEFINES_H_
+#define _E1000E_DEFINES_H_
+
+/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
+#define REQ_TX_DESCRIPTOR_MULTIPLE  8
+#define REQ_RX_DESCRIPTOR_MULTIPLE  8
+
+/* Definitions for power management and wakeup registers */
+/* Wake Up Control */
+#define E1000_WUC_APME       0x00000001 /* APM Enable */
+#define E1000_WUC_PME_EN     0x00000002 /* PME Enable */
+#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
+#define E1000_WUC_APMPME     0x00000008 /* Assert PME on APM Wakeup */
+#define E1000_WUC_LSCWE      0x00000010 /* Link Status wake up enable */
+#define E1000_WUC_LSCWO      0x00000020 /* Link Status wake up override */
+#define E1000_WUC_SPM        0x80000000 /* Enable SPM */
+#define E1000_WUC_PHY_WAKE   0x00000100 /* if PHY supports wakeup */
+
+/* Wake Up Filter Control */
+#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
+#define E1000_WUFC_MAG  0x00000002 /* Magic Packet Wakeup Enable */
+#define E1000_WUFC_EX   0x00000004 /* Directed Exact Wakeup Enable */
+#define E1000_WUFC_MC   0x00000008 /* Directed Multicast Wakeup Enable */
+#define E1000_WUFC_BC   0x00000010 /* Broadcast Wakeup Enable */
+#define E1000_WUFC_ARP  0x00000020 /* ARP Request Packet Wakeup Enable */
+#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
+#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
+#define E1000_WUFC_IGNORE_TCO_PHY 0x00000800 /* Ignore WakeOn TCO packets */
+#define E1000_WUFC_FLX0_PHY      0x00001000 /* Flexible Filter 0 Enable */
+#define E1000_WUFC_FLX1_PHY      0x00002000 /* Flexible Filter 1 Enable */
+#define E1000_WUFC_FLX2_PHY      0x00004000 /* Flexible Filter 2 Enable */
+#define E1000_WUFC_FLX3_PHY      0x00008000 /* Flexible Filter 3 Enable */
+#define E1000_WUFC_FLX4_PHY      0x00000200 /* Flexible Filter 4 Enable */
+#define E1000_WUFC_FLX5_PHY      0x00000400 /* Flexible Filter 5 Enable */
+#define E1000_WUFC_IGNORE_TCO   0x00008000 /* Ignore WakeOn TCO packets */
+#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
+#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
+#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
+#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
+#define E1000_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */
+#define E1000_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */
+#define E1000_WUFC_ALL_FILTERS_PHY_4 0x0000F0FF /*Mask for all wakeup filters*/
+#define E1000_WUFC_FLX_OFFSET_PHY 12 /* Offset to the Flexible Filters bits */
+#define E1000_WUFC_FLX_FILTERS_PHY_4 0x0000F000 /*Mask for 4 flexible filters*/
+#define E1000_WUFC_ALL_FILTERS_PHY_6 0x0000F6FF /*Mask for 6 wakeup filters */
+#define E1000_WUFC_FLX_FILTERS_PHY_6 0x0000F600 /*Mask for 6 flexible filters*/
+#define E1000_WUFC_ALL_FILTERS  0x000F00FF /* Mask for all wakeup filters */
+#define E1000_WUFC_ALL_FILTERS_6  0x003F00FF /* Mask for all 6 wakeup filters*/
+#define E1000_WUFC_FLX_OFFSET   16 /* Offset to the Flexible Filters bits */
+#define E1000_WUFC_FLX_FILTERS  0x000F0000 /*Mask for the 4 flexible filters */
+#define E1000_WUFC_FLX_FILTERS_6  0x003F0000 /* Mask for 6 flexible filters */
+
+/* Wake Up Status */
+#define E1000_WUS_LNKC         E1000_WUFC_LNKC
+#define E1000_WUS_MAG          E1000_WUFC_MAG
+#define E1000_WUS_EX           E1000_WUFC_EX
+#define E1000_WUS_MC           E1000_WUFC_MC
+#define E1000_WUS_BC           E1000_WUFC_BC
+#define E1000_WUS_ARP          E1000_WUFC_ARP
+#define E1000_WUS_IPV4         E1000_WUFC_IPV4
+#define E1000_WUS_IPV6         E1000_WUFC_IPV6
+#define E1000_WUS_FLX0_PHY      E1000_WUFC_FLX0_PHY
+#define E1000_WUS_FLX1_PHY      E1000_WUFC_FLX1_PHY
+#define E1000_WUS_FLX2_PHY      E1000_WUFC_FLX2_PHY
+#define E1000_WUS_FLX3_PHY      E1000_WUFC_FLX3_PHY
+#define E1000_WUS_FLX_FILTERS_PHY_4        E1000_WUFC_FLX_FILTERS_PHY_4
+#define E1000_WUS_FLX0         E1000_WUFC_FLX0
+#define E1000_WUS_FLX1         E1000_WUFC_FLX1
+#define E1000_WUS_FLX2         E1000_WUFC_FLX2
+#define E1000_WUS_FLX3         E1000_WUFC_FLX3
+#define E1000_WUS_FLX4         E1000_WUFC_FLX4
+#define E1000_WUS_FLX5         E1000_WUFC_FLX5
+#define E1000_WUS_FLX4_PHY         E1000_WUFC_FLX4_PHY
+#define E1000_WUS_FLX5_PHY         E1000_WUFC_FLX5_PHY
+#define E1000_WUS_FLX_FILTERS  E1000_WUFC_FLX_FILTERS
+#define E1000_WUS_FLX_FILTERS_6  E1000_WUFC_FLX_FILTERS_6
+#define E1000_WUS_FLX_FILTERS_PHY_6  E1000_WUFC_FLX_FILTERS_PHY_6
+
+/* Wake Up Packet Length */
+#define E1000_WUPL_LENGTH_MASK 0x0FFF   /* Only the lower 12 bits are valid */
+
+/* Four Flexible Filters are supported */
+#define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
+/* Six Flexible Filters are supported */
+#define E1000_FLEXIBLE_FILTER_COUNT_MAX_6   6
+
+/* Each Flexible Filter is at most 128 (0x80) bytes in length */
+#define E1000_FLEXIBLE_FILTER_SIZE_MAX  128
+
+#define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
+#define E1000_FFLT_SIZE_6 E1000_FLEXIBLE_FILTER_COUNT_MAX_6
+#define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
+#define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
+
+/* Extended Device Control */
+#define E1000_CTRL_EXT_GPI0_EN   0x00000001 /* Maps SDP4 to GPI0 */
+#define E1000_CTRL_EXT_GPI1_EN   0x00000002 /* Maps SDP5 to GPI1 */
+#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
+#define E1000_CTRL_EXT_GPI2_EN   0x00000004 /* Maps SDP6 to GPI2 */
+#define E1000_CTRL_EXT_GPI3_EN   0x00000008 /* Maps SDP7 to GPI3 */
+/* Reserved (bits 4,5) in >= 82575 */
+#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Definable Pin 4 */
+#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Definable Pin 5 */
+#define E1000_CTRL_EXT_PHY_INT   E1000_CTRL_EXT_SDP5_DATA
+#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Definable Pin 6 */
+#define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Definable Pin 3 */
+/* SDP 4/5 (bits 8,9) are reserved in >= 82575 */
+#define E1000_CTRL_EXT_SDP4_DIR  0x00000100 /* Direction of SDP4 0=in 1=out */
+#define E1000_CTRL_EXT_SDP5_DIR  0x00000200 /* Direction of SDP5 0=in 1=out */
+#define E1000_CTRL_EXT_SDP6_DIR  0x00000400 /* Direction of SDP6 0=in 1=out */
+#define E1000_CTRL_EXT_SDP3_DIR  0x00000800 /* Direction of SDP3 0=in 1=out */
+#define E1000_CTRL_EXT_ASDCHK    0x00001000 /* Initiate an ASD sequence */
+#define E1000_CTRL_EXT_EE_RST    0x00002000 /* Reinitialize from EEPROM */
+#define E1000_CTRL_EXT_IPS       0x00004000 /* Invert Power State */
+#define E1000_CTRL_EXT_SPD_BYPS  0x00008000 /* Speed Select Bypass */
+#define E1000_CTRL_EXT_RO_DIS    0x00020000 /* Relaxed Ordering disable */
+#define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clock Gating */
+#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
+#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
+#define E1000_CTRL_EXT_LINK_MODE_TBI  0x00C00000
+#define E1000_CTRL_EXT_LINK_MODE_KMRN    0x00000000
+#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES  0x00C00000
+#define E1000_CTRL_EXT_LINK_MODE_PCIX_SERDES  0x00800000
+#define E1000_CTRL_EXT_LINK_MODE_SGMII   0x00800000
+#define E1000_CTRL_EXT_EIAME          0x01000000
+#define E1000_CTRL_EXT_IRCA           0x00000001
+#define E1000_CTRL_EXT_WR_WMARK_MASK  0x03000000
+#define E1000_CTRL_EXT_WR_WMARK_256   0x00000000
+#define E1000_CTRL_EXT_WR_WMARK_320   0x01000000
+#define E1000_CTRL_EXT_WR_WMARK_384   0x02000000
+#define E1000_CTRL_EXT_WR_WMARK_448   0x03000000
+#define E1000_CTRL_EXT_CANC           0x04000000 /* Int delay cancellation */
+#define E1000_CTRL_EXT_DRV_LOAD       0x10000000 /* Driver loaded bit for FW */
+/* IAME enable bit (27) was removed in >= 82575 */
+#define E1000_CTRL_EXT_IAME          0x08000000 /* Int acknowledge Auto-mask */
+#define E1000_CRTL_EXT_PB_PAREN       0x01000000 /* packet buffer parity error
+                                                  * detection enabled */
+#define E1000_CTRL_EXT_DF_PAREN       0x02000000 /* descriptor FIFO parity
+                                                  * error detection enable */
+#define E1000_CTRL_EXT_GHOST_PAREN    0x40000000
+#define E1000_CTRL_EXT_PBA_CLR        0x80000000 /* PBA Clear */
+#define E1000_CTRL_EXT_LSECCK         0x00001000
+#define E1000_CTRL_EXT_PHYPDEN        0x00100000
+#define E1000_I2CCMD_REG_ADDR_SHIFT   16
+#define E1000_I2CCMD_REG_ADDR         0x00FF0000
+#define E1000_I2CCMD_PHY_ADDR_SHIFT   24
+#define E1000_I2CCMD_PHY_ADDR         0x07000000
+#define E1000_I2CCMD_OPCODE_READ      0x08000000
+#define E1000_I2CCMD_OPCODE_WRITE     0x00000000
+#define E1000_I2CCMD_RESET            0x10000000
+#define E1000_I2CCMD_READY            0x20000000
+#define E1000_I2CCMD_INTERRUPT_ENA    0x40000000
+#define E1000_I2CCMD_ERROR            0x80000000
+#define E1000_MAX_SGMII_PHY_REG_ADDR  255
+#define E1000_I2CCMD_PHY_TIMEOUT      200
+
+/* Receive Descriptor bit definitions */
+#define E1000_RXD_STAT_DD       0x01    /* Descriptor Done */
+#define E1000_RXD_STAT_EOP      0x02    /* End of Packet */
+#define E1000_RXD_STAT_IXSM     0x04    /* Ignore checksum */
+#define E1000_RXD_STAT_VP       0x08    /* IEEE VLAN Packet */
+#define E1000_RXD_STAT_UDPCS    0x10    /* UDP xsum calculated */
+#define E1000_RXD_STAT_TCPCS    0x20    /* TCP xsum calculated */
+#define E1000_RXD_STAT_IPCS     0x40    /* IP xsum calculated */
+#define E1000_RXD_STAT_PIF      0x80    /* passed in-exact filter */
+#define E1000_RXD_STAT_CRCV     0x100   /* Speculative CRC Valid */
+#define E1000_RXD_STAT_IPIDV    0x200   /* IP identification valid */
+#define E1000_RXD_STAT_UDPV     0x400   /* Valid UDP checksum */
+#define E1000_RXD_STAT_DYNINT   0x800   /* Pkt caused INT via DYNINT */
+#define E1000_RXD_STAT_ACK      0x8000  /* ACK Packet indication */
+#define E1000_RXD_ERR_CE        0x01    /* CRC Error */
+#define E1000_RXD_ERR_SE        0x02    /* Symbol Error */
+#define E1000_RXD_ERR_SEQ       0x04    /* Sequence Error */
+#define E1000_RXD_ERR_CXE       0x10    /* Carrier Extension Error */
+#define E1000_RXD_ERR_TCPE      0x20    /* TCP/UDP Checksum Error */
+#define E1000_RXD_ERR_IPE       0x40    /* IP Checksum Error */
+#define E1000_RXD_ERR_RXE       0x80    /* Rx Data Error */
+#define E1000_RXD_SPC_VLAN_MASK 0x0FFF  /* VLAN ID is in lower 12 bits */
+#define E1000_RXD_SPC_PRI_MASK  0xE000  /* Priority is in upper 3 bits */
+#define E1000_RXD_SPC_PRI_SHIFT 13
+#define E1000_RXD_SPC_CFI_MASK  0x1000  /* CFI is bit 12 */
+#define E1000_RXD_SPC_CFI_SHIFT 12
+
+#define E1000_RXDEXT_STATERR_CE    0x01000000
+#define E1000_RXDEXT_STATERR_SE    0x02000000
+#define E1000_RXDEXT_STATERR_SEQ   0x04000000
+#define E1000_RXDEXT_STATERR_CXE   0x10000000
+#define E1000_RXDEXT_STATERR_TCPE  0x20000000
+#define E1000_RXDEXT_STATERR_IPE   0x40000000
+#define E1000_RXDEXT_STATERR_RXE   0x80000000
+
+#define E1000_RXDEXT_LSECH                0x01000000
+#define E1000_RXDEXT_LSECE_MASK           0x60000000
+#define E1000_RXDEXT_LSECE_NO_ERROR       0x00000000
+#define E1000_RXDEXT_LSECE_NO_SA_MATCH    0x20000000
+#define E1000_RXDEXT_LSECE_REPLAY_DETECT  0x40000000
+#define E1000_RXDEXT_LSECE_BAD_SIG        0x60000000
+
+/* mask to determine if packets should be dropped due to frame errors */
+#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
+    E1000_RXD_ERR_CE  |                \
+    E1000_RXD_ERR_SE  |                \
+    E1000_RXD_ERR_SEQ |                \
+    E1000_RXD_ERR_CXE |                \
+    E1000_RXD_ERR_RXE)
+
+/* Same mask, but for extended and packet split descriptors */
+#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
+    E1000_RXDEXT_STATERR_CE  |            \
+    E1000_RXDEXT_STATERR_SE  |            \
+    E1000_RXDEXT_STATERR_SEQ |            \
+    E1000_RXDEXT_STATERR_CXE |            \
+    E1000_RXDEXT_STATERR_RXE)
+
+#define E1000_MRQC_ENABLE_MASK                 0x00000007
+#define E1000_MRQC_ENABLE_RSS_2Q               0x00000001
+#define E1000_MRQC_ENABLE_RSS_INT              0x00000004
+#define E1000_MRQC_RSS_FIELD_MASK              0xFFFF0000
+#define E1000_MRQC_RSS_FIELD_IPV4_TCP          0x00010000
+#define E1000_MRQC_RSS_FIELD_IPV4              0x00020000
+#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX       0x00040000
+#define E1000_MRQC_RSS_FIELD_IPV6_EX           0x00080000
+#define E1000_MRQC_RSS_FIELD_IPV6              0x00100000
+#define E1000_MRQC_RSS_FIELD_IPV6_TCP          0x00200000
+
+#define E1000_RXDPS_HDRSTAT_HDRSP              0x00008000
+#define E1000_RXDPS_HDRSTAT_HDRLEN_MASK        0x000003FF
+
+/* Management Control */
+#define E1000_MANC_SMBUS_EN      0x00000001 /* SMBus Enabled - RO */
+#define E1000_MANC_ASF_EN        0x00000002 /* ASF Enabled - RO */
+#define E1000_MANC_R_ON_FORCE    0x00000004 /* Reset on Force TCO - RO */
+#define E1000_MANC_RMCP_EN       0x00000100 /* Enable RCMP 026Fh Filtering */
+#define E1000_MANC_0298_EN       0x00000200 /* Enable RCMP 0298h Filtering */
+#define E1000_MANC_IPV4_EN       0x00000400 /* Enable IPv4 */
+#define E1000_MANC_IPV6_EN       0x00000800 /* Enable IPv6 */
+#define E1000_MANC_SNAP_EN       0x00001000 /* Accept LLC/SNAP */
+#define E1000_MANC_ARP_EN        0x00002000 /* Enable ARP Request Filtering */
+/* Enable Neighbor Discovery Filtering */
+#define E1000_MANC_NEIGHBOR_EN   0x00004000
+#define E1000_MANC_ARP_RES_EN    0x00008000 /* Enable ARP response Filtering */
+#define E1000_MANC_TCO_RESET     0x00010000 /* TCO Reset Occurred */
+#define E1000_MANC_RCV_TCO_EN    0x00020000 /* Receive TCO Packets Enabled */
+#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
+#define E1000_MANC_RCV_ALL       0x00080000 /* Receive All Enabled */
+#define E1000_MANC_BLK_PHY_RST_ON_IDE   0x00040000 /* Block phy resets */
+/* Enable MAC address filtering */
+#define E1000_MANC_EN_MAC_ADDR_FILTER   0x00100000
+/* Enable MNG packets to host memory */
+#define E1000_MANC_EN_MNG2HOST   0x00200000
+/* Enable IP address filtering */
+#define E1000_MANC_EN_IP_ADDR_FILTER    0x00400000
+#define E1000_MANC_EN_XSUM_FILTER   0x00800000 /* Enable checksum filtering */
+#define E1000_MANC_BR_EN            0x01000000 /* Enable broadcast filtering */
+#define E1000_MANC_SMB_REQ       0x01000000 /* SMBus Request */
+#define E1000_MANC_SMB_GNT       0x02000000 /* SMBus Grant */
+#define E1000_MANC_SMB_CLK_IN    0x04000000 /* SMBus Clock In */
+#define E1000_MANC_SMB_DATA_IN   0x08000000 /* SMBus Data In */
+#define E1000_MANC_SMB_DATA_OUT  0x10000000 /* SMBus Data Out */
+#define E1000_MANC_SMB_CLK_OUT   0x20000000 /* SMBus Clock Out */
+
+#define E1000_MANC_SMB_DATA_OUT_SHIFT  28 /* SMBus Data Out Shift */
+#define E1000_MANC_SMB_CLK_OUT_SHIFT   29 /* SMBus Clock Out Shift */
+
+/* Receive Control */
+#define E1000_RCTL_RST            0x00000001    /* Software reset */
+#define E1000_RCTL_EN             0x00000002    /* enable */
+#define E1000_RCTL_SBP            0x00000004    /* store bad packet */
+#define E1000_RCTL_UPE            0x00000008    /* unicast promisc enable */
+#define E1000_RCTL_MPE            0x00000010    /* multicast promisc enable */
+#define E1000_RCTL_LPE            0x00000020    /* long packet enable */
+#define E1000_RCTL_LBM_NO         0x00000000    /* no loopback mode */
+#define E1000_RCTL_LBM_MAC        0x00000040    /* MAC loopback mode */
+#define E1000_RCTL_LBM_SLP        0x00000080    /* serial link loopback mode */
+#define E1000_RCTL_LBM_TCVR       0x000000C0    /* tcvr loopback mode */
+#define E1000_RCTL_DTYP_MASK      0x00000C00    /* Descriptor type mask */
+#define E1000_RCTL_DTYP_PS        0x00000400    /* Packet Split descriptor */
+#define E1000_RCTL_RDMTS_HALF     0x00000000    /* rx desc min thresh size */
+#define E1000_RCTL_RDMTS_QUAT     0x00000100    /* rx desc min thresh size */
+#define E1000_RCTL_RDMTS_EIGTH    0x00000200    /* rx desc min thresh size */
+#define E1000_RCTL_MO_SHIFT       12            /* multicast offset shift */
+#define E1000_RCTL_MO_0           0x00000000    /* multicast offset 11:0 */
+#define E1000_RCTL_MO_1           0x00001000    /* multicast offset 12:1 */
+#define E1000_RCTL_MO_2           0x00002000    /* multicast offset 13:2 */
+#define E1000_RCTL_MO_3           0x00003000    /* multicast offset 15:4 */
+#define E1000_RCTL_MDR            0x00004000    /* multicast desc ring 0 */
+#define E1000_RCTL_BAM            0x00008000    /* broadcast enable */
+/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
+#define E1000_RCTL_SZ_2048        0x00000000    /* rx buffer size 2048 */
+#define E1000_RCTL_SZ_1024        0x00010000    /* rx buffer size 1024 */
+#define E1000_RCTL_SZ_512         0x00020000    /* rx buffer size 512 */
+#define E1000_RCTL_SZ_256         0x00030000    /* rx buffer size 256 */
+/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
+#define E1000_RCTL_SZ_16384       0x00010000    /* rx buffer size 16384 */
+#define E1000_RCTL_SZ_8192        0x00020000    /* rx buffer size 8192 */
+#define E1000_RCTL_SZ_4096        0x00030000    /* rx buffer size 4096 */
+#define E1000_RCTL_VFE            0x00040000    /* vlan filter enable */
+#define E1000_RCTL_CFIEN          0x00080000    /* canonical form enable */
+#define E1000_RCTL_CFI            0x00100000    /* canonical form indicator */
+#define E1000_RCTL_DPF            0x00400000    /* discard pause frames */
+#define E1000_RCTL_PMCF           0x00800000    /* pass MAC control frames */
+#define E1000_RCTL_BSEX           0x02000000    /* Buffer size extension */
+#define E1000_RCTL_SECRC          0x04000000    /* Strip Ethernet CRC */
+#define E1000_RCTL_FLXBUF_MASK    0x78000000    /* Flexible buffer size */
+#define E1000_RCTL_FLXBUF_SHIFT   27            /* Flexible buffer shift */
+
+/*
+ * Use byte values for the following shift parameters
+ * Usage:
+ *     psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
+ *                  E1000_PSRCTL_BSIZE0_MASK) |
+ *                ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
+ *                  E1000_PSRCTL_BSIZE1_MASK) |
+ *                ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
+ *                  E1000_PSRCTL_BSIZE2_MASK) |
+ *                ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
+ *                  E1000_PSRCTL_BSIZE3_MASK))
+ * where value0 = [128..16256],  default=256
+ *       value1 = [1024..64512], default=4096
+ *       value2 = [0..64512],    default=4096
+ *       value3 = [0..64512],    default=0
+ */
+
+#define E1000_PSRCTL_BSIZE0_MASK   0x0000007F
+#define E1000_PSRCTL_BSIZE1_MASK   0x00003F00
+#define E1000_PSRCTL_BSIZE2_MASK   0x003F0000
+#define E1000_PSRCTL_BSIZE3_MASK   0x3F000000
+
+#define E1000_PSRCTL_BSIZE0_SHIFT  7            /* Shift _right_ 7 */
+#define E1000_PSRCTL_BSIZE1_SHIFT  2            /* Shift _right_ 2 */
+#define E1000_PSRCTL_BSIZE2_SHIFT  6            /* Shift _left_ 6 */
+#define E1000_PSRCTL_BSIZE3_SHIFT 14            /* Shift _left_ 14 */
+
+/* SWFW_SYNC Definitions */
+#define E1000_SWFW_EEP_SM   0x01
+#define E1000_SWFW_PHY0_SM  0x02
+#define E1000_SWFW_PHY1_SM  0x04
+#define E1000_SWFW_CSR_SM   0x08
+
+/* FACTPS Definitions */
+#define E1000_FACTPS_LFS    0x40000000  /* LAN Function Select */
+/* Device Control */
+#define E1000_CTRL_FD       0x00000001  /* Full duplex.0=half; 1=full */
+#define E1000_CTRL_BEM      0x00000002  /* Endian Mode.0=little,1=big */
+#define E1000_CTRL_PRIOR    0x00000004  /* Priority on PCI. 0=rx,1=fair */
+#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master reqs */
+#define E1000_CTRL_LRST     0x00000008  /* Link reset. 0=normal,1=reset */
+#define E1000_CTRL_TME      0x00000010  /* Test mode. 0=normal,1=test */
+#define E1000_CTRL_SLE      0x00000020  /* Serial Link on 0=dis,1=en */
+#define E1000_CTRL_ASDE     0x00000020  /* Auto-speed detect enable */
+#define E1000_CTRL_SLU      0x00000040  /* Set link up (Force Link) */
+#define E1000_CTRL_ILOS     0x00000080  /* Invert Loss-Of Signal */
+#define E1000_CTRL_SPD_SEL  0x00000300  /* Speed Select Mask */
+#define E1000_CTRL_SPD_10   0x00000000  /* Force 10Mb */
+#define E1000_CTRL_SPD_100  0x00000100  /* Force 100Mb */
+#define E1000_CTRL_SPD_1000 0x00000200  /* Force 1Gb */
+#define E1000_CTRL_BEM32    0x00000400  /* Big Endian 32 mode */
+#define E1000_CTRL_FRCSPD   0x00000800  /* Force Speed */
+#define E1000_CTRL_FRCDPX   0x00001000  /* Force Duplex */
+#define E1000_CTRL_D_UD_EN  0x00002000  /* Dock/Undock enable */
+#define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock
+                                             * indication in SDP[0] */
+#define E1000_CTRL_FORCE_PHY_RESET 0x00008000 /* Reset both PHY ports, through
+                                               * PHYRST_N pin */
+#define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from external
+                                           * LINK_0 and LINK_1 pins */
+#define E1000_CTRL_SWDPIN0  0x00040000  /* SWDPIN 0 value */
+#define E1000_CTRL_SWDPIN1  0x00080000  /* SWDPIN 1 value */
+#define E1000_CTRL_SWDPIN2  0x00100000  /* SWDPIN 2 value */
+#define E1000_CTRL_SWDPIN3  0x00200000  /* SWDPIN 3 value */
+#define E1000_CTRL_SWDPIO0  0x00400000  /* SWDPIN 0 Input or output */
+#define E1000_CTRL_SWDPIO1  0x00800000  /* SWDPIN 1 input or output */
+#define E1000_CTRL_SWDPIO2  0x01000000  /* SWDPIN 2 input or output */
+#define E1000_CTRL_SWDPIO3  0x02000000  /* SWDPIN 3 input or output */
+#define E1000_CTRL_RST      0x04000000  /* Global reset */
+#define E1000_CTRL_RFCE     0x08000000  /* Receive Flow Control enable */
+#define E1000_CTRL_TFCE     0x10000000  /* Transmit flow control enable */
+#define E1000_CTRL_RTE      0x20000000  /* Routing tag enable */
+#define E1000_CTRL_VME      0x40000000  /* IEEE VLAN mode enable */
+#define E1000_CTRL_PHY_RST  0x80000000  /* PHY Reset */
+#define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to ME */
+#define E1000_CTRL_I2C_ENA  0x02000000  /* I2C enable */
+
+/*
+ * Bit definitions for the Management Data IO (MDIO) and Management Data
+ * Clock (MDC) pins in the Device Control Register.
+ */
+#define E1000_CTRL_PHY_RESET_DIR  E1000_CTRL_SWDPIO0
+#define E1000_CTRL_PHY_RESET      E1000_CTRL_SWDPIN0
+#define E1000_CTRL_MDIO_DIR       E1000_CTRL_SWDPIO2
+#define E1000_CTRL_MDIO           E1000_CTRL_SWDPIN2
+#define E1000_CTRL_MDC_DIR        E1000_CTRL_SWDPIO3
+#define E1000_CTRL_MDC            E1000_CTRL_SWDPIN3
+#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
+#define E1000_CTRL_PHY_RESET4     E1000_CTRL_EXT_SDP4_DATA
+
+#define E1000_CONNSW_ENRGSRC             0x4
+#define E1000_PCS_CFG_PCS_EN             8
+#define E1000_PCS_LCTL_FLV_LINK_UP       1
+#define E1000_PCS_LCTL_FSV_10            0
+#define E1000_PCS_LCTL_FSV_100           2
+#define E1000_PCS_LCTL_FSV_1000          4
+#define E1000_PCS_LCTL_FDV_FULL          8
+#define E1000_PCS_LCTL_FSD               0x10
+#define E1000_PCS_LCTL_FORCE_LINK        0x20
+#define E1000_PCS_LCTL_LOW_LINK_LATCH    0x40
+#define E1000_PCS_LCTL_FORCE_FCTRL       0x80
+#define E1000_PCS_LCTL_AN_ENABLE         0x10000
+#define E1000_PCS_LCTL_AN_RESTART        0x20000
+#define E1000_PCS_LCTL_AN_TIMEOUT        0x40000
+#define E1000_PCS_LCTL_AN_SGMII_BYPASS   0x80000
+#define E1000_PCS_LCTL_AN_SGMII_TRIGGER  0x100000
+#define E1000_PCS_LCTL_FAST_LINK_TIMER   0x1000000
+#define E1000_PCS_LCTL_LINK_OK_FIX       0x2000000
+#define E1000_PCS_LCTL_CRS_ON_NI         0x4000000
+#define E1000_ENABLE_SERDES_LOOPBACK     0x0410
+
+#define E1000_PCS_LSTS_LINK_OK           1
+#define E1000_PCS_LSTS_SPEED_10          0
+#define E1000_PCS_LSTS_SPEED_100         2
+#define E1000_PCS_LSTS_SPEED_1000        4
+#define E1000_PCS_LSTS_DUPLEX_FULL       8
+#define E1000_PCS_LSTS_SYNK_OK           0x10
+#define E1000_PCS_LSTS_AN_COMPLETE       0x10000
+#define E1000_PCS_LSTS_AN_PAGE_RX        0x20000
+#define E1000_PCS_LSTS_AN_TIMED_OUT      0x40000
+#define E1000_PCS_LSTS_AN_REMOTE_FAULT   0x80000
+#define E1000_PCS_LSTS_AN_ERROR_RWS      0x100000
+
+/* Device Status */
+#define E1000_STATUS_FD         0x00000001      /* Full duplex.0=half,1=full */
+#define E1000_STATUS_LU         0x00000002      /* Link up.0=no,1=link */
+#define E1000_STATUS_FUNC_MASK  0x0000000C      /* PCI Function Mask */
+#define E1000_STATUS_FUNC_SHIFT 2
+#define E1000_STATUS_FUNC_0     0x00000000      /* Function 0 */
+#define E1000_STATUS_FUNC_1     0x00000004      /* Function 1 */
+#define E1000_STATUS_TXOFF      0x00000010      /* transmission paused */
+#define E1000_STATUS_TBIMODE    0x00000020      /* TBI mode */
+#define E1000_STATUS_SPEED_MASK 0x000000C0
+#define E1000_STATUS_SPEED_10   0x00000000      /* Speed 10Mb/s */
+#define E1000_STATUS_SPEED_100  0x00000040      /* Speed 100Mb/s */
+#define E1000_STATUS_SPEED_1000 0x00000080      /* Speed 1000Mb/s */
+#define E1000_STATUS_LAN_INIT_DONE 0x00000200  /* Lan Init Completion by NVM */
+#define E1000_STATUS_ASDV       0x00000300      /* Auto speed detect value */
+#define E1000_STATUS_PHYRA      0x00000400      /* PHY Reset Asserted */
+#define E1000_STATUS_DOCK_CI    0x00000800      /* Change in Dock/Undock state.
+                                                 * Clear on write '0'. */
+#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Master request status */
+#define E1000_STATUS_MTXCKOK    0x00000400      /* MTX clock running OK */
+#define E1000_STATUS_PCI66      0x00000800      /* In 66Mhz slot */
+#define E1000_STATUS_BUS64      0x00001000      /* In 64 bit slot */
+#define E1000_STATUS_PCIX_MODE  0x00002000      /* PCI-X mode */
+#define E1000_STATUS_PCIX_SPEED 0x0000C000      /* PCI-X bus speed */
+#define E1000_STATUS_BMC_SKU_0  0x00100000 /* BMC USB redirect disabled */
+#define E1000_STATUS_BMC_SKU_1  0x00200000 /* BMC SRAM disabled */
+#define E1000_STATUS_BMC_SKU_2  0x00400000 /* BMC SDRAM disabled */
+#define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */
+#define E1000_STATUS_BMC_LITE   0x01000000 /* BMC external code execution
+                                            * disabled */
+#define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */
+#define E1000_STATUS_FUSE_8       0x04000000
+#define E1000_STATUS_FUSE_9       0x08000000
+#define E1000_STATUS_SERDES0_DIS  0x10000000 /* SERDES disabled on port 0 */
+#define E1000_STATUS_SERDES1_DIS  0x20000000 /* SERDES disabled on port 1 */
+
+/* Constants used to interpret the masked PCI-X bus speed. */
+#define E1000_STATUS_PCIX_SPEED_66  0x00000000 /* PCI-X bus speed 50-66 MHz */
+#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */
+#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /*PCI-X bus speed 100-133 MHz*/
+
+#define SPEED_10    10
+#define SPEED_100   100
+#define SPEED_1000  1000
+#define HALF_DUPLEX 1
+#define FULL_DUPLEX 2
+
+#define PHY_FORCE_TIME   20
+
+#define ADVERTISE_10_HALF                 0x0001
+#define ADVERTISE_10_FULL                 0x0002
+#define ADVERTISE_100_HALF                0x0004
+#define ADVERTISE_100_FULL                0x0008
+#define ADVERTISE_1000_HALF               0x0010 /* Not used, just FYI */
+#define ADVERTISE_1000_FULL               0x0020
+
+/* 1000/H is not supported, nor spec-compliant. */
+#define E1000_ALL_SPEED_DUPLEX  (ADVERTISE_10_HALF |   ADVERTISE_10_FULL | \
+                                ADVERTISE_100_HALF |  ADVERTISE_100_FULL | \
+                                                     ADVERTISE_1000_FULL)
+#define E1000_ALL_NOT_GIG       (ADVERTISE_10_HALF |   ADVERTISE_10_FULL | \
+                                ADVERTISE_100_HALF |  ADVERTISE_100_FULL)
+#define E1000_ALL_100_SPEED    (ADVERTISE_100_HALF |  ADVERTISE_100_FULL)
+#define E1000_ALL_10_SPEED      (ADVERTISE_10_HALF |   ADVERTISE_10_FULL)
+#define E1000_ALL_FULL_DUPLEX   (ADVERTISE_10_FULL |  ADVERTISE_100_FULL | \
+                                                     ADVERTISE_1000_FULL)
+#define E1000_ALL_HALF_DUPLEX   (ADVERTISE_10_HALF |  ADVERTISE_100_HALF)
+
+#define AUTONEG_ADVERTISE_SPEED_DEFAULT   E1000_ALL_SPEED_DUPLEX
+
+/* LED Control */
+#define E1000_PHY_LED0_MODE_MASK          0x00000007
+#define E1000_PHY_LED0_IVRT               0x00000008
+#define E1000_PHY_LED0_BLINK              0x00000010
+#define E1000_PHY_LED0_MASK               0x0000001F
+
+#define E1000_LEDCTL_LED0_MODE_MASK       0x0000000F
+#define E1000_LEDCTL_LED0_MODE_SHIFT      0
+#define E1000_LEDCTL_LED0_BLINK_RATE      0x00000020
+#define E1000_LEDCTL_LED0_IVRT            0x00000040
+#define E1000_LEDCTL_LED0_BLINK           0x00000080
+#define E1000_LEDCTL_LED1_MODE_MASK       0x00000F00
+#define E1000_LEDCTL_LED1_MODE_SHIFT      8
+#define E1000_LEDCTL_LED1_BLINK_RATE      0x00002000
+#define E1000_LEDCTL_LED1_IVRT            0x00004000
+#define E1000_LEDCTL_LED1_BLINK           0x00008000
+#define E1000_LEDCTL_LED2_MODE_MASK       0x000F0000
+#define E1000_LEDCTL_LED2_MODE_SHIFT      16
+#define E1000_LEDCTL_LED2_BLINK_RATE      0x00200000
+#define E1000_LEDCTL_LED2_IVRT            0x00400000
+#define E1000_LEDCTL_LED2_BLINK           0x00800000
+#define E1000_LEDCTL_LED3_MODE_MASK       0x0F000000
+#define E1000_LEDCTL_LED3_MODE_SHIFT      24
+#define E1000_LEDCTL_LED3_BLINK_RATE      0x20000000
+#define E1000_LEDCTL_LED3_IVRT            0x40000000
+#define E1000_LEDCTL_LED3_BLINK           0x80000000
+
+#define E1000_LEDCTL_MODE_LINK_10_1000  0x0
+#define E1000_LEDCTL_MODE_LINK_100_1000 0x1
+#define E1000_LEDCTL_MODE_LINK_UP       0x2
+#define E1000_LEDCTL_MODE_ACTIVITY      0x3
+#define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
+#define E1000_LEDCTL_MODE_LINK_10       0x5
+#define E1000_LEDCTL_MODE_LINK_100      0x6
+#define E1000_LEDCTL_MODE_LINK_1000     0x7
+#define E1000_LEDCTL_MODE_PCIX_MODE     0x8
+#define E1000_LEDCTL_MODE_FULL_DUPLEX   0x9
+#define E1000_LEDCTL_MODE_COLLISION     0xA
+#define E1000_LEDCTL_MODE_BUS_SPEED     0xB
+#define E1000_LEDCTL_MODE_BUS_SIZE      0xC
+#define E1000_LEDCTL_MODE_PAUSED        0xD
+#define E1000_LEDCTL_MODE_LED_ON        0xE
+#define E1000_LEDCTL_MODE_LED_OFF       0xF
+
+/* Transmit Descriptor bit definitions */
+#define E1000_TXD_DTYP_D     0x00100000 /* Data Descriptor */
+#define E1000_TXD_DTYP_C     0x00000000 /* Context Descriptor */
+#define E1000_TXD_POPTS_SHIFT 8         /* POPTS shift */
+#define E1000_TXD_POPTS_IXSM 0x01       /* Insert IP checksum */
+#define E1000_TXD_POPTS_TXSM 0x02       /* Insert TCP/UDP checksum */
+#define E1000_TXD_CMD_EOP    0x01000000 /* End of Packet */
+#define E1000_TXD_CMD_IFCS   0x02000000 /* Insert FCS (Ethernet CRC) */
+#define E1000_TXD_CMD_IC     0x04000000 /* Insert Checksum */
+#define E1000_TXD_CMD_RS     0x08000000 /* Report Status */
+#define E1000_TXD_CMD_RPS    0x10000000 /* Report Packet Sent */
+#define E1000_TXD_CMD_DEXT   0x20000000 /* Descriptor extension (0 = legacy) */
+#define E1000_TXD_CMD_VLE    0x40000000 /* Add VLAN tag */
+#define E1000_TXD_CMD_IDE    0x80000000 /* Enable Tidv register */
+#define E1000_TXD_STAT_DD    0x00000001 /* Descriptor Done */
+#define E1000_TXD_STAT_EC    0x00000002 /* Excess Collisions */
+#define E1000_TXD_STAT_LC    0x00000004 /* Late Collisions */
+#define E1000_TXD_STAT_TU    0x00000008 /* Transmit underrun */
+#define E1000_TXD_CMD_TCP    0x01000000 /* TCP packet */
+#define E1000_TXD_CMD_IP     0x02000000 /* IP packet */
+#define E1000_TXD_CMD_TSE    0x04000000 /* TCP Seg enable */
+#define E1000_TXD_STAT_TC    0x00000004 /* Tx Underrun */
+/* Extended desc bits for Linksec and timesync */
+#define E1000_TXD_CMD_LINKSEC     0x10000000 /* Apply LinkSec on packet */
+#define E1000_TXD_EXTCMD_TSTAMP   0x00000010 /* IEEE1588 Timestamp packet */
+
+/* Transmit Control */
+#define E1000_TCTL_RST    0x00000001    /* software reset */
+#define E1000_TCTL_EN     0x00000002    /* enable tx */
+#define E1000_TCTL_BCE    0x00000004    /* busy check enable */
+#define E1000_TCTL_PSP    0x00000008    /* pad short packets */
+#define E1000_TCTL_CT     0x00000ff0    /* collision threshold */
+#define E1000_TCTL_COLD   0x003ff000    /* collision distance */
+#define E1000_TCTL_SWXOFF 0x00400000    /* SW Xoff transmission */
+#define E1000_TCTL_PBE    0x00800000    /* Packet Burst Enable */
+#define E1000_TCTL_RTLC   0x01000000    /* Re-transmit on late collision */
+#define E1000_TCTL_NRTU   0x02000000    /* No Re-transmit on underrun */
+#define E1000_TCTL_MULR   0x10000000    /* Multiple request support */
+
+/* Transmit Arbitration Count */
+#define E1000_TARC0_ENABLE     0x00000400   /* Enable Tx Queue 0 */
+
+/* SerDes Control */
+#define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
+
+/* Receive Checksum Control */
+#define E1000_RXCSUM_PCSS_MASK 0x000000FF   /* Packet Checksum Start */
+#define E1000_RXCSUM_IPOFL     0x00000100   /* IPv4 checksum offload */
+#define E1000_RXCSUM_TUOFL     0x00000200   /* TCP / UDP checksum offload */
+#define E1000_RXCSUM_IPV6OFL   0x00000400   /* IPv6 checksum offload */
+#define E1000_RXCSUM_CRCOFL    0x00000800   /* CRC32 offload enable */
+#define E1000_RXCSUM_IPPCSE    0x00001000   /* IP payload checksum enable */
+#define E1000_RXCSUM_PCSD      0x00002000   /* packet checksum disabled */
+
+/* Header split receive */
+#define E1000_RFCTL_ISCSI_DIS           0x00000001
+#define E1000_RFCTL_ISCSI_DWC_MASK      0x0000003E
+#define E1000_RFCTL_ISCSI_DWC_SHIFT     1
+#define E1000_RFCTL_NFSW_DIS            0x00000040
+#define E1000_RFCTL_NFSR_DIS            0x00000080
+#define E1000_RFCTL_NFS_VER_MASK        0x00000300
+#define E1000_RFCTL_NFS_VER_SHIFT       8
+#define E1000_RFCTL_IPV6_DIS            0x00000400
+#define E1000_RFCTL_IPV6_XSUM_DIS       0x00000800
+#define E1000_RFCTL_ACK_DIS             0x00001000
+#define E1000_RFCTL_ACKD_DIS            0x00002000
+#define E1000_RFCTL_IPFRSP_DIS          0x00004000
+#define E1000_RFCTL_EXTEN               0x00008000
+#define E1000_RFCTL_IPV6_EX_DIS         0x00010000
+#define E1000_RFCTL_NEW_IPV6_EXT_DIS    0x00020000
+#define E1000_RFCTL_LEF                 0x00040000
+
+/* Collision related configuration parameters */
+#define E1000_COLLISION_THRESHOLD       15
+#define E1000_CT_SHIFT                  4
+#define E1000_COLLISION_DISTANCE        63
+#define E1000_COLD_SHIFT                12
+
+/* Default values for the transmit IPG register */
+#define DEFAULT_82543_TIPG_IPGT_FIBER  9
+#define DEFAULT_82543_TIPG_IPGT_COPPER 8
+
+#define E1000_TIPG_IPGT_MASK  0x000003FF
+#define E1000_TIPG_IPGR1_MASK 0x000FFC00
+#define E1000_TIPG_IPGR2_MASK 0x3FF00000
+
+#define DEFAULT_82543_TIPG_IPGR1 8
+#define E1000_TIPG_IPGR1_SHIFT  10
+
+#define DEFAULT_82543_TIPG_IPGR2 6
+#define DEFAULT_80003ES2LAN_TIPG_IPGR2 7
+#define E1000_TIPG_IPGR2_SHIFT  20
+
+/* Ethertype field values */
+#define ETHERNET_IEEE_VLAN_TYPE 0x8100  /* 802.3ac packet */
+
+#define ETHERNET_FCS_SIZE       4
+#define MAX_JUMBO_FRAME_SIZE    0x3F00
+
+/* Extended Configuration Control and Size */
+#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP      0x00000020
+#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE       0x00000001
+#define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE       0x00000008
+#define E1000_EXTCNF_CTRL_SWFLAG                 0x00000020
+#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK   0x00FF0000
+#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT          16
+#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK   0x0FFF0000
+#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT          16
+
+#define E1000_PHY_CTRL_SPD_EN             0x00000001
+#define E1000_PHY_CTRL_D0A_LPLU           0x00000002
+#define E1000_PHY_CTRL_NOND0A_LPLU        0x00000004
+#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
+#define E1000_PHY_CTRL_GBE_DISABLE        0x00000040
+
+#define E1000_KABGTXD_BGSQLBIAS           0x00050000
+
+/* PBA constants */
+#define E1000_PBA_6K  0x0006    /* 6KB */
+#define E1000_PBA_8K  0x0008    /* 8KB */
+#define E1000_PBA_10K 0x000A    /* 10KB */
+#define E1000_PBA_12K 0x000C    /* 12KB */
+#define E1000_PBA_14K 0x000E    /* 14KB */
+#define E1000_PBA_16K 0x0010    /* 16KB */
+#define E1000_PBA_18K 0x0012
+#define E1000_PBA_20K 0x0014
+#define E1000_PBA_22K 0x0016
+#define E1000_PBA_24K 0x0018
+#define E1000_PBA_26K 0x001A
+#define E1000_PBA_30K 0x001E
+#define E1000_PBA_32K 0x0020
+#define E1000_PBA_34K 0x0022
+#define E1000_PBA_35K 0x0023
+#define E1000_PBA_38K 0x0026
+#define E1000_PBA_40K 0x0028
+#define E1000_PBA_48K 0x0030    /* 48KB */
+#define E1000_PBA_64K 0x0040    /* 64KB */
+
+#define E1000_PBS_16K E1000_PBA_16K
+#define E1000_PBS_24K E1000_PBA_24K
+
+#define IFS_MAX       80
+#define IFS_MIN       40
+#define IFS_RATIO     4
+#define IFS_STEP      10
+#define MIN_NUM_XMITS 1000
+
+/* SW Semaphore Register */
+#define E1000_SWSM_SMBI         0x00000001 /* Driver Semaphore bit */
+#define E1000_SWSM_SWESMBI      0x00000002 /* FW Semaphore bit */
+#define E1000_SWSM_WMNG         0x00000004 /* Wake MNG Clock */
+#define E1000_SWSM_DRV_LOAD     0x00000008 /* Driver Loaded Bit */
+
+#define E1000_SWSM2_LOCK        0x00000002 /* Secondary driver semaphore bit */
+
+/* Interrupt Cause Read */
+#define E1000_ICR_TXDW          0x00000001 /* Transmit desc written back */
+#define E1000_ICR_TXQE          0x00000002 /* Transmit Queue empty */
+#define E1000_ICR_LSC           0x00000004 /* Link Status Change */
+#define E1000_ICR_RXSEQ         0x00000008 /* rx sequence error */
+#define E1000_ICR_RXDMT0        0x00000010 /* rx desc min. threshold (0) */
+#define E1000_ICR_RXO           0x00000040 /* rx overrun */
+#define E1000_ICR_RXT0          0x00000080 /* rx timer intr (ring 0) */
+#define E1000_ICR_VMMB          0x00000100 /* VM MB event */
+#define E1000_ICR_MDAC          0x00000200 /* MDIO access complete */
+#define E1000_ICR_RXCFG         0x00000400 /* Rx /c/ ordered set */
+#define E1000_ICR_GPI_EN0       0x00000800 /* GP Int 0 */
+#define E1000_ICR_GPI_EN1       0x00001000 /* GP Int 1 */
+#define E1000_ICR_GPI_EN2       0x00002000 /* GP Int 2 */
+#define E1000_ICR_GPI_EN3       0x00004000 /* GP Int 3 */
+#define E1000_ICR_TXD_LOW       0x00008000
+#define E1000_ICR_SRPD          0x00010000
+#define E1000_ICR_ACK           0x00020000 /* Receive Ack frame */
+#define E1000_ICR_MNG           0x00040000 /* Manageability event */
+#define E1000_ICR_DOCK          0x00080000 /* Dock/Undock */
+#define E1000_ICR_INT_ASSERTED  0x80000000 /* If this bit asserted, the driver
+                                            * should claim the interrupt */
+#define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* Q0 Rx desc FIFO parity error */
+#define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* Q0 Tx desc FIFO parity error */
+#define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity err */
+#define E1000_ICR_PB_PAR        0x00800000 /* packet buffer parity error */
+#define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* Q1 Rx desc FIFO parity error */
+#define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* Q1 Tx desc FIFO parity error */
+#define E1000_ICR_ALL_PARITY    0x03F00000 /* all parity error bits */
+#define E1000_ICR_DSW           0x00000020 /* FW changed the status of DISSW
+                                            * bit in the FWSM */
+#define E1000_ICR_PHYINT        0x00001000 /* LAN connected device generates
+                                            * an interrupt */
+#define E1000_ICR_DOUTSYNC      0x10000000 /* NIC DMA out of sync */
+#define E1000_ICR_EPRST         0x00100000 /* ME hardware reset occurs */
+#define E1000_ICR_RXQ0          0x00100000 /* Rx Queue 0 Interrupt */
+#define E1000_ICR_RXQ1          0x00200000 /* Rx Queue 1 Interrupt */
+#define E1000_ICR_TXQ0          0x00400000 /* Tx Queue 0 Interrupt */
+#define E1000_ICR_TXQ1          0x00800000 /* Tx Queue 1 Interrupt */
+#define E1000_ICR_OTHER         0x01000000 /* Other Interrupts */
+
+/* PBA ECC Register */
+#define E1000_PBA_ECC_COUNTER_MASK  0xFFF00000 /* ECC counter mask */
+#define E1000_PBA_ECC_COUNTER_SHIFT 20         /* ECC counter shift value */
+#define E1000_PBA_ECC_CORR_EN      0x00000001 /* Enable ECC error correction */
+#define E1000_PBA_ECC_STAT_CLR      0x00000002 /* Clear ECC error counter */
+#define E1000_PBA_ECC_INT_EN     0x00000004 /* Enable ICR bit 5 on ECC error */
+
+/*
+ * This defines the bits that are set in the Interrupt Mask
+ * Set/Read Register.  Each bit is documented below:
+ *   o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
+ *   o RXSEQ  = Receive Sequence Error
+ */
+#define POLL_IMS_ENABLE_MASK ( \
+    E1000_IMS_RXDMT0 |    \
+    E1000_IMS_RXSEQ)
+
+/*
+ * This defines the bits that are set in the Interrupt Mask
+ * Set/Read Register.  Each bit is documented below:
+ *   o RXT0   = Receiver Timer Interrupt (ring 0)
+ *   o TXDW   = Transmit Descriptor Written Back
+ *   o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
+ *   o RXSEQ  = Receive Sequence Error
+ *   o LSC    = Link Status Change
+ */
+#define IMS_ENABLE_MASK ( \
+    E1000_IMS_RXT0   |    \
+    E1000_IMS_TXDW   |    \
+    E1000_IMS_RXDMT0 |    \
+    E1000_IMS_RXSEQ  |    \
+    E1000_IMS_LSC)
+
+/* Interrupt Mask Set */
+#define E1000_IMS_TXDW      E1000_ICR_TXDW      /* Tx desc written back */
+#define E1000_IMS_TXQE      E1000_ICR_TXQE      /* Transmit Queue empty */
+#define E1000_IMS_LSC       E1000_ICR_LSC       /* Link Status Change */
+#define E1000_IMS_VMMB      E1000_ICR_VMMB      /* Mail box activity */
+#define E1000_IMS_RXSEQ     E1000_ICR_RXSEQ     /* rx sequence error */
+#define E1000_IMS_RXDMT0    E1000_ICR_RXDMT0    /* rx desc min. threshold */
+#define E1000_IMS_RXO       E1000_ICR_RXO       /* rx overrun */
+#define E1000_IMS_RXT0      E1000_ICR_RXT0      /* rx timer intr */
+#define E1000_IMS_MDAC      E1000_ICR_MDAC      /* MDIO access complete */
+#define E1000_IMS_RXCFG     E1000_ICR_RXCFG     /* Rx /c/ ordered set */
+#define E1000_IMS_GPI_EN0   E1000_ICR_GPI_EN0   /* GP Int 0 */
+#define E1000_IMS_GPI_EN1   E1000_ICR_GPI_EN1   /* GP Int 1 */
+#define E1000_IMS_GPI_EN2   E1000_ICR_GPI_EN2   /* GP Int 2 */
+#define E1000_IMS_GPI_EN3   E1000_ICR_GPI_EN3   /* GP Int 3 */
+#define E1000_IMS_TXD_LOW   E1000_ICR_TXD_LOW
+#define E1000_IMS_SRPD      E1000_ICR_SRPD
+#define E1000_IMS_ACK       E1000_ICR_ACK       /* Receive Ack frame */
+#define E1000_IMS_MNG       E1000_ICR_MNG       /* Manageability event */
+#define E1000_IMS_DOCK      E1000_ICR_DOCK      /* Dock/Undock */
+#define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* Q0 Rx desc FIFO
+                                                         * parity error */
+#define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* Q0 Tx desc FIFO
+                                                         * parity error */
+#define E1000_IMS_HOST_ARB_PAR  E1000_ICR_HOST_ARB_PAR  /* host arb read buffer
+                                                         * parity error */
+#define E1000_IMS_PB_PAR        E1000_ICR_PB_PAR        /* packet buffer parity
+                                                         * error */
+#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* Q1 Rx desc FIFO
+                                                         * parity error */
+#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* Q1 Tx desc FIFO
+                                                         * parity error */
+#define E1000_IMS_DSW       E1000_ICR_DSW
+#define E1000_IMS_PHYINT    E1000_ICR_PHYINT
+#define E1000_IMS_DOUTSYNC  E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
+#define E1000_IMS_EPRST     E1000_ICR_EPRST
+#define E1000_IMS_RXQ0          E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */
+#define E1000_IMS_RXQ1          E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */
+#define E1000_IMS_TXQ0          E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */
+#define E1000_IMS_TXQ1          E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */
+#define E1000_IMS_OTHER         E1000_ICR_OTHER /* Other Interrupts */
+
+/* Interrupt Cause Set */
+#define E1000_ICS_TXDW      E1000_ICR_TXDW      /* Tx desc written back */
+#define E1000_ICS_TXQE      E1000_ICR_TXQE      /* Transmit Queue empty */
+#define E1000_ICS_LSC       E1000_ICR_LSC       /* Link Status Change */
+#define E1000_ICS_RXSEQ     E1000_ICR_RXSEQ     /* rx sequence error */
+#define E1000_ICS_RXDMT0    E1000_ICR_RXDMT0    /* rx desc min. threshold */
+#define E1000_ICS_RXO       E1000_ICR_RXO       /* rx overrun */
+#define E1000_ICS_RXT0      E1000_ICR_RXT0      /* rx timer intr */
+#define E1000_ICS_MDAC      E1000_ICR_MDAC      /* MDIO access complete */
+#define E1000_ICS_RXCFG     E1000_ICR_RXCFG     /* Rx /c/ ordered set */
+#define E1000_ICS_GPI_EN0   E1000_ICR_GPI_EN0   /* GP Int 0 */
+#define E1000_ICS_GPI_EN1   E1000_ICR_GPI_EN1   /* GP Int 1 */
+#define E1000_ICS_GPI_EN2   E1000_ICR_GPI_EN2   /* GP Int 2 */
+#define E1000_ICS_GPI_EN3   E1000_ICR_GPI_EN3   /* GP Int 3 */
+#define E1000_ICS_TXD_LOW   E1000_ICR_TXD_LOW
+#define E1000_ICS_SRPD      E1000_ICR_SRPD
+#define E1000_ICS_ACK       E1000_ICR_ACK       /* Receive Ack frame */
+#define E1000_ICS_MNG       E1000_ICR_MNG       /* Manageability event */
+#define E1000_ICS_DOCK      E1000_ICR_DOCK      /* Dock/Undock */
+#define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* Q0 Rx desc FIFO
+                                                         * parity error */
+#define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* Q0 Tx desc FIFO
+                                                         * parity error */
+#define E1000_ICS_HOST_ARB_PAR  E1000_ICR_HOST_ARB_PAR  /* host arb read buffer
+                                                         * parity error */
+#define E1000_ICS_PB_PAR        E1000_ICR_PB_PAR        /* packet buffer parity
+                                                         * error */
+#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* Q1 Rx desc FIFO
+                                                         * parity error */
+#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* Q1 Tx desc FIFO
+                                                         * parity error */
+#define E1000_ICS_DSW       E1000_ICR_DSW
+#define E1000_ICS_DOUTSYNC  E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
+#define E1000_ICS_PHYINT    E1000_ICR_PHYINT
+#define E1000_ICS_EPRST     E1000_ICR_EPRST
+
+/* Transmit Descriptor Control */
+#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
+#define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */
+#define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */
+#define E1000_TXDCTL_GRAN    0x01000000 /* TXDCTL Granularity */
+#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
+#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
+#define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */
+/* Enable the counting of descriptors still to be processed. */
+#define E1000_TXDCTL_COUNT_DESC 0x00400000
+
+/* Flow Control Constants */
+#define FLOW_CONTROL_ADDRESS_LOW  0x00C28001
+#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
+#define FLOW_CONTROL_TYPE         0x8808
+
+/* 802.1q VLAN Packet Size */
+#define VLAN_TAG_SIZE              4    /* 802.3ac tag (not DMA'd) */
+#define E1000_VLAN_FILTER_TBL_SIZE 128  /* VLAN Filter Table (4096 bits) */
+
+/* Receive Address */
+/*
+ * Number of high/low register pairs in the RAR. The RAR (Receive Address
+ * Registers) holds the directed and multicast addresses that we monitor.
+ * Technically, we have 16 spots.  However, we reserve one of these spots
+ * (RAR[15]) for our directed address used by controllers with
+ * manageability enabled, allowing us room for 15 multicast addresses.
+ */
+#define E1000_RAR_ENTRIES     15
+#define E1000_RAH_AV  0x80000000        /* Receive descriptor valid */
+#define E1000_RAL_MAC_ADDR_LEN 4
+#define E1000_RAH_MAC_ADDR_LEN 2
+#define E1000_RAH_POOL_MASK 0x03FC0000
+#define E1000_RAH_POOL_1 0x00040000
+
+/* Error Codes */
+#define E1000_SUCCESS      0
+#define E1000_ERR_NVM      1
+#define E1000_ERR_PHY      2
+#define E1000_ERR_CONFIG   3
+#define E1000_ERR_PARAM    4
+#define E1000_ERR_MAC_INIT 5
+#define E1000_ERR_PHY_TYPE 6
+#define E1000_ERR_RESET   9
+#define E1000_ERR_MASTER_REQUESTS_PENDING 10
+#define E1000_ERR_HOST_INTERFACE_COMMAND 11
+#define E1000_BLK_PHY_RESET   12
+#define E1000_ERR_SWFW_SYNC 13
+#define E1000_NOT_IMPLEMENTED 14
+#define E1000_ERR_MBX      15
+
+/* Loop limit on how long we wait for auto-negotiation to complete */
+#define FIBER_LINK_UP_LIMIT               50
+#define COPPER_LINK_UP_LIMIT              10
+#define PHY_AUTO_NEG_LIMIT                45
+#define PHY_FORCE_LIMIT                   20
+/* Number of 100 microseconds we wait for PCI Express master disable */
+#define MASTER_DISABLE_TIMEOUT      800
+/* Number of milliseconds we wait for PHY configuration done after MAC reset */
+#define PHY_CFG_TIMEOUT             100
+/* Number of 2 milliseconds we wait for acquiring MDIO ownership. */
+#define MDIO_OWNERSHIP_TIMEOUT      10
+/* Number of milliseconds for NVM auto read done after MAC reset. */
+#define AUTO_READ_DONE_TIMEOUT      10
+
+/* Flow Control */
+#define E1000_FCRTH_RTH  0x0000FFF8     /* Mask Bits[15:3] for RTH */
+#define E1000_FCRTH_XFCE 0x80000000     /* External Flow Control Enable */
+#define E1000_FCRTL_RTL  0x0000FFF8     /* Mask Bits[15:3] for RTL */
+#define E1000_FCRTL_XONE 0x80000000     /* Enable XON frame transmission */
+
+/* Transmit Configuration Word */
+#define E1000_TXCW_FD         0x00000020        /* TXCW full duplex */
+#define E1000_TXCW_HD         0x00000040        /* TXCW half duplex */
+#define E1000_TXCW_PAUSE      0x00000080        /* TXCW sym pause request */
+#define E1000_TXCW_ASM_DIR    0x00000100        /* TXCW astm pause direction */
+#define E1000_TXCW_PAUSE_MASK 0x00000180        /* TXCW pause request mask */
+#define E1000_TXCW_RF         0x00003000        /* TXCW remote fault */
+#define E1000_TXCW_NP         0x00008000        /* TXCW next page */
+#define E1000_TXCW_CW         0x0000ffff        /* TxConfigWord mask */
+#define E1000_TXCW_TXC        0x40000000        /* Transmit Config control */
+#define E1000_TXCW_ANE        0x80000000        /* Auto-neg enable */
+
+/* Receive Configuration Word */
+#define E1000_RXCW_CW         0x0000ffff        /* RxConfigWord mask */
+#define E1000_RXCW_NC         0x04000000        /* Receive config no carrier */
+#define E1000_RXCW_IV         0x08000000        /* Receive config invalid */
+#define E1000_RXCW_CC         0x10000000        /* Receive config change */
+#define E1000_RXCW_C          0x20000000        /* Receive config */
+#define E1000_RXCW_SYNCH      0x40000000        /* Receive config synch */
+#define E1000_RXCW_ANC        0x80000000        /* Auto-neg complete */
+
+
+/* PCI Express Control */
+#define E1000_GCR_RXD_NO_SNOOP          0x00000001
+#define E1000_GCR_RXDSCW_NO_SNOOP       0x00000002
+#define E1000_GCR_RXDSCR_NO_SNOOP       0x00000004
+#define E1000_GCR_TXD_NO_SNOOP          0x00000008
+#define E1000_GCR_TXDSCW_NO_SNOOP       0x00000010
+#define E1000_GCR_TXDSCR_NO_SNOOP       0x00000020
+#define E1000_GCR_CMPL_TMOUT_MASK       0x0000F000
+#define E1000_GCR_CMPL_TMOUT_10ms       0x00001000
+#define E1000_GCR_CMPL_TMOUT_RESEND     0x00010000
+#define E1000_GCR_CAP_VER2              0x00040000
+
+#define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP         | \
+                           E1000_GCR_RXDSCW_NO_SNOOP      | \
+                           E1000_GCR_RXDSCR_NO_SNOOP      | \
+                           E1000_GCR_TXD_NO_SNOOP         | \
+                           E1000_GCR_TXDSCW_NO_SNOOP      | \
+                           E1000_GCR_TXDSCR_NO_SNOOP)
+
+/* PHY Control Register */
+#define MII_CR_SPEED_SELECT_MSB 0x0040  /* bits 6,13: 10=1000, 01=100, 00=10 */
+#define MII_CR_COLL_TEST_ENABLE 0x0080  /* Collision test enable */
+#define MII_CR_FULL_DUPLEX      0x0100  /* FDX =1, half duplex =0 */
+#define MII_CR_RESTART_AUTO_NEG 0x0200  /* Restart auto negotiation */
+#define MII_CR_ISOLATE          0x0400  /* Isolate PHY from MII */
+#define MII_CR_POWER_DOWN       0x0800  /* Power down */
+#define MII_CR_AUTO_NEG_EN      0x1000  /* Auto Neg Enable */
+#define MII_CR_SPEED_SELECT_LSB 0x2000  /* bits 6,13: 10=1000, 01=100, 00=10 */
+#define MII_CR_LOOPBACK         0x4000  /* 0 = normal, 1 = loopback */
+#define MII_CR_RESET            0x8000  /* 0 = normal, 1 = PHY reset */
+#define MII_CR_SPEED_1000       0x0040
+#define MII_CR_SPEED_100        0x2000
+#define MII_CR_SPEED_10         0x0000
+
+/* PHY Status Register */
+#define MII_SR_EXTENDED_CAPS     0x0001 /* Extended register capabilities */
+#define MII_SR_JABBER_DETECT     0x0002 /* Jabber Detected */
+#define MII_SR_LINK_STATUS       0x0004 /* Link Status 1 = link */
+#define MII_SR_AUTONEG_CAPS      0x0008 /* Auto Neg Capable */
+#define MII_SR_REMOTE_FAULT      0x0010 /* Remote Fault Detect */
+#define MII_SR_AUTONEG_COMPLETE  0x0020 /* Auto Neg Complete */
+#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
+#define MII_SR_EXTENDED_STATUS   0x0100 /* Ext. status info in Reg 0x0F */
+#define MII_SR_100T2_HD_CAPS     0x0200 /* 100T2 Half Duplex Capable */
+#define MII_SR_100T2_FD_CAPS     0x0400 /* 100T2 Full Duplex Capable */
+#define MII_SR_10T_HD_CAPS       0x0800 /* 10T   Half Duplex Capable */
+#define MII_SR_10T_FD_CAPS       0x1000 /* 10T   Full Duplex Capable */
+#define MII_SR_100X_HD_CAPS      0x2000 /* 100X  Half Duplex Capable */
+#define MII_SR_100X_FD_CAPS      0x4000 /* 100X  Full Duplex Capable */
+#define MII_SR_100T4_CAPS        0x8000 /* 100T4 Capable */
+
+/* Autoneg Advertisement Register */
+#define NWAY_AR_SELECTOR_FIELD   0x0001   /* indicates IEEE 802.3 CSMA/CD */
+#define NWAY_AR_10T_HD_CAPS      0x0020   /* 10T   Half Duplex Capable */
+#define NWAY_AR_10T_FD_CAPS      0x0040   /* 10T   Full Duplex Capable */
+#define NWAY_AR_100TX_HD_CAPS    0x0080   /* 100TX Half Duplex Capable */
+#define NWAY_AR_100TX_FD_CAPS    0x0100   /* 100TX Full Duplex Capable */
+#define NWAY_AR_100T4_CAPS       0x0200   /* 100T4 Capable */
+#define NWAY_AR_PAUSE            0x0400   /* Pause operation desired */
+#define NWAY_AR_ASM_DIR          0x0800   /* Asymmetric Pause Direction bit */
+#define NWAY_AR_REMOTE_FAULT     0x2000   /* Remote Fault detected */
+#define NWAY_AR_NEXT_PAGE        0x8000   /* Next Page ability supported */
+
+/* Link Partner Ability Register (Base Page) */
+#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
+#define NWAY_LPAR_10T_HD_CAPS    0x0020 /* LP is 10T   Half Duplex Capable */
+#define NWAY_LPAR_10T_FD_CAPS    0x0040 /* LP is 10T   Full Duplex Capable */
+#define NWAY_LPAR_100TX_HD_CAPS  0x0080 /* LP is 100TX Half Duplex Capable */
+#define NWAY_LPAR_100TX_FD_CAPS  0x0100 /* LP is 100TX Full Duplex Capable */
+#define NWAY_LPAR_100T4_CAPS     0x0200 /* LP is 100T4 Capable */
+#define NWAY_LPAR_PAUSE          0x0400 /* LP Pause operation desired */
+#define NWAY_LPAR_ASM_DIR        0x0800 /* LP Asymmetric Pause Direction bit */
+#define NWAY_LPAR_REMOTE_FAULT   0x2000 /* LP has detected Remote Fault */
+#define NWAY_LPAR_ACKNOWLEDGE    0x4000 /* LP has rx'd link code word */
+#define NWAY_LPAR_NEXT_PAGE      0x8000 /* Next Page ability supported */
+
+/* Autoneg Expansion Register */
+#define NWAY_ER_LP_NWAY_CAPS      0x0001 /* LP has Auto Neg Capability */
+#define NWAY_ER_PAGE_RXD          0x0002 /* LP is 10T   Half Duplex Capable */
+#define NWAY_ER_NEXT_PAGE_CAPS    0x0004 /* LP is 10T   Full Duplex Capable */
+#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
+#define NWAY_ER_PAR_DETECT_FAULT  0x0010 /* LP is 100TX Full Duplex Capable */
+
+/* 1000BASE-T Control Register */
+#define CR_1000T_ASYM_PAUSE      0x0080 /* Advertise asymmetric pause bit */
+#define CR_1000T_HD_CAPS         0x0100 /* Advertise 1000T HD capability */
+#define CR_1000T_FD_CAPS         0x0200 /* Advertise 1000T FD capability  */
+#define CR_1000T_REPEATER_DTE    0x0400 /* 1=Repeater/switch device port */
+                                        /* 0=DTE device */
+#define CR_1000T_MS_VALUE        0x0800 /* 1=Configure PHY as Master */
+                                        /* 0=Configure PHY as Slave */
+#define CR_1000T_MS_ENABLE      0x1000 /* 1=Master/Slave manual config value */
+                                        /* 0=Automatic Master/Slave config */
+#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
+#define CR_1000T_TEST_MODE_1     0x2000 /* Transmit Waveform test */
+#define CR_1000T_TEST_MODE_2     0x4000 /* Master Transmit Jitter test */
+#define CR_1000T_TEST_MODE_3     0x6000 /* Slave Transmit Jitter test */
+#define CR_1000T_TEST_MODE_4     0x8000 /* Transmitter Distortion test */
+
+/* 1000BASE-T Status Register */
+#define SR_1000T_IDLE_ERROR_CNT   0x00FF /* Num idle errors since last read */
+#define SR_1000T_ASYM_PAUSE_DIR  0x0100 /* LP asymmetric pause direction bit */
+#define SR_1000T_LP_HD_CAPS       0x0400 /* LP is 1000T HD capable */
+#define SR_1000T_LP_FD_CAPS       0x0800 /* LP is 1000T FD capable */
+#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
+#define SR_1000T_LOCAL_RX_STATUS  0x2000 /* Local receiver OK */
+#define SR_1000T_MS_CONFIG_RES    0x4000 /* 1=Local Tx is Master, 0=Slave */
+#define SR_1000T_MS_CONFIG_FAULT  0x8000 /* Master/Slave config fault */
+
+#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5
+
+/* PHY 1000 MII Register/Bit Definitions */
+/* PHY Registers defined by IEEE */
+#define PHY_CONTROL      0x00 /* Control Register */
+#define PHY_STATUS       0x01 /* Status Register */
+#define PHY_ID1          0x02 /* Phy Id Reg (word 1) */
+#define PHY_ID2          0x03 /* Phy Id Reg (word 2) */
+#define PHY_AUTONEG_ADV  0x04 /* Autoneg Advertisement */
+#define PHY_LP_ABILITY   0x05 /* Link Partner Ability (Base Page) */
+#define PHY_AUTONEG_EXP  0x06 /* Autoneg Expansion Reg */
+#define PHY_NEXT_PAGE_TX 0x07 /* Next Page Tx */
+#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
+#define PHY_1000T_CTRL   0x09 /* 1000Base-T Control Reg */
+#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
+#define PHY_EXT_STATUS   0x0F /* Extended Status Reg */
+
+#define PHY_CONTROL_LB   0x4000 /* PHY Loopback bit */
+
+/* NVM Control */
+#define E1000_EECD_SK        0x00000001 /* NVM Clock */
+#define E1000_EECD_CS        0x00000002 /* NVM Chip Select */
+#define E1000_EECD_DI        0x00000004 /* NVM Data In */
+#define E1000_EECD_DO        0x00000008 /* NVM Data Out */
+#define E1000_EECD_FWE_MASK  0x00000030
+#define E1000_EECD_FWE_DIS   0x00000010 /* Disable FLASH writes */
+#define E1000_EECD_FWE_EN    0x00000020 /* Enable FLASH writes */
+#define E1000_EECD_FWE_SHIFT 4
+#define E1000_EECD_REQ       0x00000040 /* NVM Access Request */
+#define E1000_EECD_GNT       0x00000080 /* NVM Access Grant */
+#define E1000_EECD_PRES      0x00000100 /* NVM Present */
+#define E1000_EECD_SIZE      0x00000200 /* NVM Size (0=64 word 1=256 word) */
+/* NVM Addressing bits based on type 0=small, 1=large */
+#define E1000_EECD_ADDR_BITS 0x00000400
+#define E1000_EECD_TYPE      0x00002000 /* NVM Type (1-SPI, 0-Microwire) */
+#define E1000_NVM_GRANT_ATTEMPTS   1000 /* NVM # attempts to gain grant */
+#define E1000_EECD_AUTO_RD          0x00000200  /* NVM Auto Read done */
+#define E1000_EECD_SIZE_EX_MASK     0x00007800  /* NVM Size */
+#define E1000_EECD_SIZE_EX_SHIFT     11
+#define E1000_EECD_NVADDS    0x00018000 /* NVM Address Size */
+#define E1000_EECD_SELSHAD   0x00020000 /* Select Shadow RAM */
+#define E1000_EECD_INITSRAM  0x00040000 /* Initialize Shadow RAM */
+#define E1000_EECD_FLUPD     0x00080000 /* Update FLASH */
+#define E1000_EECD_AUPDEN    0x00100000 /* Enable Autonomous FLASH update */
+#define E1000_EECD_SHADV     0x00200000 /* Shadow RAM Data Valid */
+#define E1000_EECD_SEC1VAL   0x00400000 /* Sector One Valid */
+#define E1000_EECD_SECVAL_SHIFT      22
+#define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES)
+
+#define E1000_NVM_SWDPIN0   0x0001   /* SWDPIN 0 NVM Value */
+#define E1000_NVM_LED_LOGIC 0x0020   /* Led Logic Word */
+#define E1000_NVM_RW_REG_DATA   16  /* Offset to data in NVM read/write regs */
+#define E1000_NVM_RW_REG_DONE   2    /* Offset to READ/WRITE done bit */
+#define E1000_NVM_RW_REG_START  1    /* Start operation */
+#define E1000_NVM_RW_ADDR_SHIFT 2    /* Shift to the address bits */
+#define E1000_NVM_POLL_WRITE    1    /* Flag for polling for write complete */
+#define E1000_NVM_POLL_READ     0    /* Flag for polling for read complete */
+#define E1000_FLASH_UPDATES  2000
+
+/* NVM Word Offsets */
+#define NVM_COMPAT                 0x0003
+#define NVM_ID_LED_SETTINGS        0x0004
+#define NVM_VERSION                0x0005
+#define NVM_SERDES_AMPLITUDE       0x0006 /* SERDES output amplitude */
+#define NVM_PHY_CLASS_WORD         0x0007
+#define NVM_INIT_CONTROL1_REG      0x000A
+#define NVM_INIT_CONTROL2_REG      0x000F
+#define NVM_SWDEF_PINS_CTRL_PORT_1 0x0010
+#define NVM_INIT_CONTROL3_PORT_B   0x0014
+#define NVM_INIT_3GIO_3            0x001A
+#define NVM_SWDEF_PINS_CTRL_PORT_0 0x0020
+#define NVM_INIT_CONTROL3_PORT_A   0x0024
+#define NVM_CFG                    0x0012
+#define NVM_FLASH_VERSION          0x0032
+#define NVM_ALT_MAC_ADDR_PTR       0x0037
+#define NVM_CHECKSUM_REG           0x003F
+
+#define E1000_NVM_CFG_DONE_PORT_0  0x040000 /* MNG config cycle done */
+#define E1000_NVM_CFG_DONE_PORT_1  0x080000 /* ...for second port */
+
+/* Mask bits for fields in Word 0x0f of the NVM */
+#define NVM_WORD0F_PAUSE_MASK       0x3000
+#define NVM_WORD0F_PAUSE            0x1000
+#define NVM_WORD0F_ASM_DIR          0x2000
+#define NVM_WORD0F_ANE              0x0800
+#define NVM_WORD0F_SWPDIO_EXT_MASK  0x00F0
+#define NVM_WORD0F_LPLU             0x0001
+
+/* Mask bits for fields in Word 0x1a of the NVM */
+#define NVM_WORD1A_ASPM_MASK  0x000C
+
+/* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
+#define NVM_SUM                    0xBABA
+
+#define NVM_MAC_ADDR_OFFSET        0
+#define NVM_PBA_OFFSET_0           8
+#define NVM_PBA_OFFSET_1           9
+#define NVM_RESERVED_WORD          0xFFFF
+#define NVM_PHY_CLASS_A            0x8000
+#define NVM_SERDES_AMPLITUDE_MASK  0x000F
+#define NVM_SIZE_MASK              0x1C00
+#define NVM_SIZE_SHIFT             10
+#define NVM_WORD_SIZE_BASE_SHIFT   6
+#define NVM_SWDPIO_EXT_SHIFT       4
+
+/* NVM Commands - SPI */
+#define NVM_MAX_RETRY_SPI          5000 /* Max wait of 5ms, for RDY signal */
+#define NVM_READ_OPCODE_SPI        0x03 /* NVM read opcode */
+#define NVM_WRITE_OPCODE_SPI       0x02 /* NVM write opcode */
+#define NVM_A8_OPCODE_SPI          0x08 /* opcode bit-3 = address bit-8 */
+#define NVM_WREN_OPCODE_SPI        0x06 /* NVM set Write Enable latch */
+#define NVM_WRDI_OPCODE_SPI        0x04 /* NVM reset Write Enable latch */
+#define NVM_RDSR_OPCODE_SPI        0x05 /* NVM read Status register */
+#define NVM_WRSR_OPCODE_SPI        0x01 /* NVM write Status register */
+
+/* SPI NVM Status Register */
+#define NVM_STATUS_RDY_SPI         0x01
+#define NVM_STATUS_WEN_SPI         0x02
+#define NVM_STATUS_BP0_SPI         0x04
+#define NVM_STATUS_BP1_SPI         0x08
+#define NVM_STATUS_WPEN_SPI        0x80
+
+/* Word definitions for ID LED Settings */
+#define ID_LED_RESERVED_0000 0x0000
+#define ID_LED_RESERVED_FFFF 0xFFFF
+#define ID_LED_DEFAULT       ((ID_LED_OFF1_ON2  << 12) | \
+                              (ID_LED_OFF1_OFF2 <<  8) | \
+                              (ID_LED_DEF1_DEF2 <<  4) | \
+                              (ID_LED_DEF1_DEF2))
+#define ID_LED_DEF1_DEF2     0x1
+#define ID_LED_DEF1_ON2      0x2
+#define ID_LED_DEF1_OFF2     0x3
+#define ID_LED_ON1_DEF2      0x4
+#define ID_LED_ON1_ON2       0x5
+#define ID_LED_ON1_OFF2      0x6
+#define ID_LED_OFF1_DEF2     0x7
+#define ID_LED_OFF1_ON2      0x8
+#define ID_LED_OFF1_OFF2     0x9
+
+#define IGP_ACTIVITY_LED_MASK   0xFFFFF0FF
+#define IGP_ACTIVITY_LED_ENABLE 0x0300
+#define IGP_LED3_MODE           0x07000000
+
+/* PCI/PCI-X/PCI-EX Config space */
+#define PCI_HEADER_TYPE_REGISTER     0x0E
+#define PCIE_LINK_STATUS             0x12
+#define PCIE_DEVICE_CONTROL2         0x28
+
+#define PCI_HEADER_TYPE_MULTIFUNC    0x80
+#define PCIE_LINK_WIDTH_MASK         0x3F0
+#define PCIE_LINK_WIDTH_SHIFT        4
+#define PCIE_DEVICE_CONTROL2_16ms    0x0005
+
+#ifndef ETH_ADDR_LEN
+#define ETH_ADDR_LEN                 6
+#endif
+
+#define PHY_REVISION_MASK      0xFFFFFFF0
+#define MAX_PHY_REG_ADDRESS    0x1F  /* 5 bit address bus (0-0x1F) */
+#define MAX_PHY_MULTI_PAGE_REG 0xF
+
+/* Bit definitions for valid PHY IDs. */
+/*
+ * I = Integrated
+ * E = External
+ */
+#define M88E1000_E_PHY_ID    0x01410C50
+#define M88E1000_I_PHY_ID    0x01410C30
+#define M88E1011_I_PHY_ID    0x01410C20
+#define IGP01E1000_I_PHY_ID  0x02A80380
+#define M88E1011_I_REV_4     0x04
+#define M88E1111_I_PHY_ID    0x01410CC0
+#define GG82563_E_PHY_ID     0x01410CA0
+#define IGP03E1000_E_PHY_ID  0x02A80390
+#define IFE_E_PHY_ID         0x02A80330
+#define IFE_PLUS_E_PHY_ID    0x02A80320
+#define IFE_C_E_PHY_ID       0x02A80310
+#define BME1000_E_PHY_ID     0x01410CB0
+#define BME1000_E_PHY_ID_R2  0x01410CB1
+#define I82577_E_PHY_ID 0x01540050
+#define I82578_E_PHY_ID 0x004DD040
+#define M88_VENDOR           0x0141
+
+/* M88E1000 Specific Registers */
+#define M88E1000_PHY_SPEC_CTRL     0x10  /* PHY Specific Control Register */
+#define M88E1000_PHY_SPEC_STATUS   0x11  /* PHY Specific Status Register */
+#define M88E1000_INT_ENABLE        0x12  /* Interrupt Enable Register */
+#define M88E1000_INT_STATUS        0x13  /* Interrupt Status Register */
+#define M88E1000_EXT_PHY_SPEC_CTRL 0x14  /* Extended PHY Specific Control */
+#define M88E1000_RX_ERR_CNTR       0x15  /* Receive Error Counter */
+
+#define M88E1000_PHY_EXT_CTRL      0x1A  /* PHY extend control register */
+#define M88E1000_PHY_PAGE_SELECT   0x1D  /* Reg 29 for page number setting */
+#define M88E1000_PHY_GEN_CONTROL   0x1E  /* Its meaning depends on reg 29 */
+#define M88E1000_PHY_VCO_REG_BIT8  0x100 /* Bits 8 & 11 are adjusted for */
+#define M88E1000_PHY_VCO_REG_BIT11 0x800    /* improved BER performance */
+
+/* M88E1000 PHY Specific Control Register */
+#define M88E1000_PSCR_JABBER_DISABLE    0x0001 /* 1=Jabber Function disabled */
+#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reverse enabled */
+#define M88E1000_PSCR_SQE_TEST          0x0004 /* 1=SQE Test enabled */
+/* 1=CLK125 low, 0=CLK125 toggling */
+#define M88E1000_PSCR_CLK125_DISABLE    0x0010
+#define M88E1000_PSCR_MDI_MANUAL_MODE  0x0000 /* MDI Crossover Mode bits 6:5 */
+                                               /* Manual MDI configuration */
+#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020  /* Manual MDIX configuration */
+/* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
+#define M88E1000_PSCR_AUTO_X_1000T     0x0040
+/* Auto crossover enabled all speeds */
+#define M88E1000_PSCR_AUTO_X_MODE      0x0060
+/*
+ * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold
+ * 0=Normal 10BASE-T Rx Threshold
+ */
+#define M88E1000_PSCR_EN_10BT_EXT_DIST 0x0080
+/* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */
+#define M88E1000_PSCR_MII_5BIT_ENABLE      0x0100
+#define M88E1000_PSCR_SCRAMBLER_DISABLE    0x0200 /* 1=Scrambler disable */
+#define M88E1000_PSCR_FORCE_LINK_GOOD      0x0400 /* 1=Force link good */
+#define M88E1000_PSCR_ASSERT_CRS_ON_TX     0x0800 /* 1=Assert CRS on Tx */
+
+/* M88E1000 PHY Specific Status Register */
+#define M88E1000_PSSR_JABBER             0x0001 /* 1=Jabber */
+#define M88E1000_PSSR_REV_POLARITY       0x0002 /* 1=Polarity reversed */
+#define M88E1000_PSSR_DOWNSHIFT          0x0020 /* 1=Downshifted */
+#define M88E1000_PSSR_MDIX               0x0040 /* 1=MDIX; 0=MDI */
+/*
+ * 0 = <50M
+ * 1 = 50-80M
+ * 2 = 80-110M
+ * 3 = 110-140M
+ * 4 = >140M
+ */
+#define M88E1000_PSSR_CABLE_LENGTH       0x0380
+#define M88E1000_PSSR_LINK               0x0400 /* 1=Link up, 0=Link down */
+#define M88E1000_PSSR_SPD_DPLX_RESOLVED  0x0800 /* 1=Speed & Duplex resolved */
+#define M88E1000_PSSR_PAGE_RCVD          0x1000 /* 1=Page received */
+#define M88E1000_PSSR_DPLX               0x2000 /* 1=Duplex 0=Half Duplex */
+#define M88E1000_PSSR_SPEED              0xC000 /* Speed, bits 14:15 */
+#define M88E1000_PSSR_10MBS              0x0000 /* 00=10Mbs */
+#define M88E1000_PSSR_100MBS             0x4000 /* 01=100Mbs */
+#define M88E1000_PSSR_1000MBS            0x8000 /* 10=1000Mbs */
+
+#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
+
+/* M88E1000 Extended PHY Specific Control Register */
+#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
+/*
+ * 1 = Lost lock detect enabled.
+ * Will assert lost lock and bring
+ * link down if idle not seen
+ * within 1ms in 1000BASE-T
+ */
+#define M88E1000_EPSCR_DOWN_NO_IDLE   0x8000
+/*
+ * Number of times we will attempt to autonegotiate before downshifting if we
+ * are the master
+ */
+#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
+#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X   0x0000
+#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X   0x0400
+#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X   0x0800
+#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X   0x0C00
+/*
+ * Number of times we will attempt to autonegotiate before downshifting if we
+ * are the slave
+ */
+#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK  0x0300
+#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS   0x0000
+#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X    0x0100
+#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X    0x0200
+#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X    0x0300
+#define M88E1000_EPSCR_TX_CLK_2_5     0x0060 /* 2.5 MHz TX_CLK */
+#define M88E1000_EPSCR_TX_CLK_25      0x0070 /* 25  MHz TX_CLK */
+#define M88E1000_EPSCR_TX_CLK_0       0x0000 /* NO  TX_CLK */
+
+/* M88EC018 Rev 2 specific DownShift settings */
+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK  0x0E00
+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X    0x0000
+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X    0x0200
+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X    0x0400
+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X    0x0600
+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X    0x0800
+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X    0x0A00
+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X    0x0C00
+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X    0x0E00
+
+#define I82578_EPSCR_DOWNSHIFT_ENABLE          0x0020
+#define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK    0x001C
+
+/* BME1000 PHY Specific Control Register */
+#define BME1000_PSCR_ENABLE_DOWNSHIFT   0x0800 /* 1 = enable downshift */
+
+/*
+ * Bits...
+ * 15-5: page
+ * 4-0: register offset
+ */
+#define GG82563_PAGE_SHIFT        5
+#define GG82563_REG(page, reg)    \
+        (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
+#define GG82563_MIN_ALT_REG       30
+
+/* GG82563 Specific Registers */
+#define GG82563_PHY_SPEC_CTRL           \
+        GG82563_REG(0, 16) /* PHY Specific Control */
+#define GG82563_PHY_SPEC_STATUS         \
+        GG82563_REG(0, 17) /* PHY Specific Status */
+#define GG82563_PHY_INT_ENABLE          \
+        GG82563_REG(0, 18) /* Interrupt Enable */
+#define GG82563_PHY_SPEC_STATUS_2       \
+        GG82563_REG(0, 19) /* PHY Specific Status 2 */
+#define GG82563_PHY_RX_ERR_CNTR         \
+        GG82563_REG(0, 21) /* Receive Error Counter */
+#define GG82563_PHY_PAGE_SELECT         \
+        GG82563_REG(0, 22) /* Page Select */
+#define GG82563_PHY_SPEC_CTRL_2         \
+        GG82563_REG(0, 26) /* PHY Specific Control 2 */
+#define GG82563_PHY_PAGE_SELECT_ALT     \
+        GG82563_REG(0, 29) /* Alternate Page Select */
+#define GG82563_PHY_TEST_CLK_CTRL       \
+        GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */
+
+#define GG82563_PHY_MAC_SPEC_CTRL       \
+        GG82563_REG(2, 21) /* MAC Specific Control Register */
+#define GG82563_PHY_MAC_SPEC_CTRL_2     \
+        GG82563_REG(2, 26) /* MAC Specific Control 2 */
+
+#define GG82563_PHY_DSP_DISTANCE    \
+        GG82563_REG(5, 26) /* DSP Distance */
+
+/* Page 193 - Port Control Registers */
+#define GG82563_PHY_KMRN_MODE_CTRL   \
+        GG82563_REG(193, 16) /* Kumeran Mode Control */
+#define GG82563_PHY_PORT_RESET          \
+        GG82563_REG(193, 17) /* Port Reset */
+#define GG82563_PHY_REVISION_ID         \
+        GG82563_REG(193, 18) /* Revision ID */
+#define GG82563_PHY_DEVICE_ID           \
+        GG82563_REG(193, 19) /* Device ID */
+#define GG82563_PHY_PWR_MGMT_CTRL       \
+        GG82563_REG(193, 20) /* Power Management Control */
+#define GG82563_PHY_RATE_ADAPT_CTRL     \
+        GG82563_REG(193, 25) /* Rate Adaptation Control */
+
+/* Page 194 - KMRN Registers */
+#define GG82563_PHY_KMRN_FIFO_CTRL_STAT \
+        GG82563_REG(194, 16) /* FIFO's Control/Status */
+#define GG82563_PHY_KMRN_CTRL           \
+        GG82563_REG(194, 17) /* Control */
+#define GG82563_PHY_INBAND_CTRL         \
+        GG82563_REG(194, 18) /* Inband Control */
+#define GG82563_PHY_KMRN_DIAGNOSTIC     \
+        GG82563_REG(194, 19) /* Diagnostic */
+#define GG82563_PHY_ACK_TIMEOUTS        \
+        GG82563_REG(194, 20) /* Acknowledge Timeouts */
+#define GG82563_PHY_ADV_ABILITY         \
+        GG82563_REG(194, 21) /* Advertised Ability */
+#define GG82563_PHY_LINK_PARTNER_ADV_ABILITY \
+        GG82563_REG(194, 23) /* Link Partner Advertised Ability */
+#define GG82563_PHY_ADV_NEXT_PAGE       \
+        GG82563_REG(194, 24) /* Advertised Next Page */
+#define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE \
+        GG82563_REG(194, 25) /* Link Partner Advertised Next page */
+#define GG82563_PHY_KMRN_MISC           \
+        GG82563_REG(194, 26) /* Misc. */
+
+/* MDI Control */
+#define E1000_MDIC_DATA_MASK 0x0000FFFF
+#define E1000_MDIC_REG_MASK  0x001F0000
+#define E1000_MDIC_REG_SHIFT 16
+#define E1000_MDIC_PHY_MASK  0x03E00000
+#define E1000_MDIC_PHY_SHIFT 21
+#define E1000_MDIC_OP_WRITE  0x04000000
+#define E1000_MDIC_OP_READ   0x08000000
+#define E1000_MDIC_READY     0x10000000
+#define E1000_MDIC_INT_EN    0x20000000
+#define E1000_MDIC_ERROR     0x40000000
+
+/* SerDes Control */
+#define E1000_GEN_CTL_READY             0x80000000
+#define E1000_GEN_CTL_ADDRESS_SHIFT     8
+#define E1000_GEN_POLL_TIMEOUT          640
+
+
+
+#endif /* _E1000E_DEFINES_H_ */
diff --git a/src/drivers/net/e1000e/e1000e_hw.h b/src/drivers/net/e1000e/e1000e_hw.h
new file mode 100644 (file)
index 0000000..03ed35c
--- /dev/null
@@ -0,0 +1,719 @@
+/*******************************************************************************
+
+  Intel PRO/1000 Linux driver
+  Copyright(c) 1999 - 2009 Intel Corporation.
+
+  This program is free software; you can redistribute it and/or modify it
+  under the terms and conditions of the GNU General Public License,
+  version 2, as published by the Free Software Foundation.
+
+  This program is distributed in the hope it will be useful, but WITHOUT
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+  more details.
+
+  You should have received a copy of the GNU General Public License along with
+  this program; if not, write to the Free Software Foundation, Inc.,
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+
+  The full GNU General Public License is included in this distribution in
+  the file called "COPYING".
+
+  Contact Information:
+  Linux NICS <linux.nics@intel.com>
+  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+
+*******************************************************************************/
+
+FILE_LICENCE ( GPL2_OR_LATER );
+
+#ifndef _E1000E_HW_H_
+#define _E1000E_HW_H_
+
+#include "e1000e_regs.h"
+#include "e1000e_defines.h"
+
+struct e1000_hw;
+
+#define E1000_DEV_ID_82571EB_COPPER           0x105E
+#define E1000_DEV_ID_82571EB_FIBER            0x105F
+#define E1000_DEV_ID_82571EB_SERDES           0x1060
+#define E1000_DEV_ID_82571EB_SERDES_DUAL      0x10D9
+#define E1000_DEV_ID_82571EB_SERDES_QUAD      0x10DA
+#define E1000_DEV_ID_82571EB_QUAD_COPPER      0x10A4
+#define E1000_DEV_ID_82571PT_QUAD_COPPER      0x10D5
+#define E1000_DEV_ID_82571EB_QUAD_FIBER       0x10A5
+#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP   0x10BC
+#define E1000_DEV_ID_82572EI_COPPER           0x107D
+#define E1000_DEV_ID_82572EI_FIBER            0x107E
+#define E1000_DEV_ID_82572EI_SERDES           0x107F
+#define E1000_DEV_ID_82572EI                  0x10B9
+#define E1000_DEV_ID_82573E                   0x108B
+#define E1000_DEV_ID_82573E_IAMT              0x108C
+#define E1000_DEV_ID_82573L                   0x109A
+#define E1000_DEV_ID_82574L                   0x10D3
+#define E1000_DEV_ID_82574LA                  0x10F6
+#define E1000_DEV_ID_82583V                   0x150C
+#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT   0x1096
+#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT   0x1098
+#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT   0x10BA
+#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT   0x10BB
+#define E1000_DEV_ID_ICH8_82567V_3            0x1501
+#define E1000_DEV_ID_ICH8_IGP_M_AMT           0x1049
+#define E1000_DEV_ID_ICH8_IGP_AMT             0x104A
+#define E1000_DEV_ID_ICH8_IGP_C               0x104B
+#define E1000_DEV_ID_ICH8_IFE                 0x104C
+#define E1000_DEV_ID_ICH8_IFE_GT              0x10C4
+#define E1000_DEV_ID_ICH8_IFE_G               0x10C5
+#define E1000_DEV_ID_ICH8_IGP_M               0x104D
+#define E1000_DEV_ID_ICH9_IGP_M               0x10BF
+#define E1000_DEV_ID_ICH9_IGP_M_AMT           0x10F5
+#define E1000_DEV_ID_ICH9_IGP_M_V             0x10CB
+#define E1000_DEV_ID_ICH9_IGP_AMT             0x10BD
+#define E1000_DEV_ID_ICH9_BM                  0x10E5
+#define E1000_DEV_ID_ICH9_IGP_C               0x294C
+#define E1000_DEV_ID_ICH9_IFE                 0x10C0
+#define E1000_DEV_ID_ICH9_IFE_GT              0x10C3
+#define E1000_DEV_ID_ICH9_IFE_G               0x10C2
+#define E1000_DEV_ID_ICH10_R_BM_LM            0x10CC
+#define E1000_DEV_ID_ICH10_R_BM_LF            0x10CD
+#define E1000_DEV_ID_ICH10_R_BM_V             0x10CE
+#define E1000_DEV_ID_ICH10_D_BM_LM            0x10DE
+#define E1000_DEV_ID_ICH10_D_BM_LF            0x10DF
+#define E1000_DEV_ID_PCH_M_HV_LM              0x10EA
+#define E1000_DEV_ID_PCH_M_HV_LC              0x10EB
+#define E1000_DEV_ID_PCH_D_HV_DM              0x10EF
+#define E1000_DEV_ID_PCH_D_HV_DC              0x10F0
+#define E1000_REVISION_0 0
+#define E1000_REVISION_1 1
+#define E1000_REVISION_2 2
+#define E1000_REVISION_3 3
+#define E1000_REVISION_4 4
+
+#define E1000_FUNC_0     0
+#define E1000_FUNC_1     1
+
+#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0   0
+#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1   3
+
+enum e1000_mac_type {
+       e1000_undefined = 0,
+       e1000_82571,
+       e1000_82572,
+       e1000_82573,
+       e1000_82574,
+       e1000_82583,
+       e1000_80003es2lan,
+       e1000_ich8lan,
+       e1000_ich9lan,
+       e1000_ich10lan,
+       e1000_pchlan,
+       e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
+};
+
+enum e1000_media_type {
+       e1000_media_type_unknown = 0,
+       e1000_media_type_copper = 1,
+       e1000_media_type_fiber = 2,
+       e1000_media_type_internal_serdes = 3,
+       e1000_num_media_types
+};
+
+enum e1000_nvm_type {
+       e1000_nvm_unknown = 0,
+       e1000_nvm_none,
+       e1000_nvm_eeprom_spi,
+       e1000_nvm_flash_hw,
+       e1000_nvm_flash_sw
+};
+
+enum e1000_nvm_override {
+       e1000_nvm_override_none = 0,
+       e1000_nvm_override_spi_small,
+       e1000_nvm_override_spi_large,
+};
+
+enum e1000_phy_type {
+       e1000_phy_unknown = 0,
+       e1000_phy_none,
+       e1000_phy_m88,
+       e1000_phy_igp,
+       e1000_phy_igp_2,
+       e1000_phy_gg82563,
+       e1000_phy_igp_3,
+       e1000_phy_ife,
+       e1000_phy_bm,
+       e1000_phy_82578,
+       e1000_phy_82577,
+};
+
+enum e1000_bus_type {
+       e1000_bus_type_unknown = 0,
+       e1000_bus_type_pci,
+       e1000_bus_type_pcix,
+       e1000_bus_type_pci_express,
+       e1000_bus_type_reserved
+};
+
+enum e1000_bus_speed {
+       e1000_bus_speed_unknown = 0,
+       e1000_bus_speed_33,
+       e1000_bus_speed_66,
+       e1000_bus_speed_100,
+       e1000_bus_speed_120,
+       e1000_bus_speed_133,
+       e1000_bus_speed_2500,
+       e1000_bus_speed_5000,
+       e1000_bus_speed_reserved
+};
+
+enum e1000_bus_width {
+       e1000_bus_width_unknown = 0,
+       e1000_bus_width_pcie_x1,
+       e1000_bus_width_pcie_x2,
+       e1000_bus_width_pcie_x4 = 4,
+       e1000_bus_width_pcie_x8 = 8,
+       e1000_bus_width_32,
+       e1000_bus_width_64,
+       e1000_bus_width_reserved
+};
+
+enum e1000_1000t_rx_status {
+       e1000_1000t_rx_status_not_ok = 0,
+       e1000_1000t_rx_status_ok,
+       e1000_1000t_rx_status_undefined = 0xFF
+};
+
+enum e1000_rev_polarity {
+       e1000_rev_polarity_normal = 0,
+       e1000_rev_polarity_reversed,
+       e1000_rev_polarity_undefined = 0xFF
+};
+
+enum e1000_fc_mode {
+       e1000_fc_none = 0,
+       e1000_fc_rx_pause,
+       e1000_fc_tx_pause,
+       e1000_fc_full,
+       e1000_fc_default = 0xFF
+};
+
+enum e1000_ms_type {
+       e1000_ms_hw_default = 0,
+       e1000_ms_force_master,
+       e1000_ms_force_slave,
+       e1000_ms_auto
+};
+
+enum e1000_smart_speed {
+       e1000_smart_speed_default = 0,
+       e1000_smart_speed_on,
+       e1000_smart_speed_off
+};
+
+enum e1000_serdes_link_state {
+       e1000_serdes_link_down = 0,
+       e1000_serdes_link_autoneg_progress,
+       e1000_serdes_link_autoneg_complete,
+       e1000_serdes_link_forced_up
+};
+
+/* Receive Descriptor */
+struct e1000_rx_desc {
+       __le64 buffer_addr; /* Address of the descriptor's data buffer */
+       __le16 length;      /* Length of data DMAed into data buffer */
+       __le16 csum;        /* Packet checksum */
+       u8  status;         /* Descriptor status */
+       u8  errors;         /* Descriptor Errors */
+       __le16 special;
+};
+
+/* Receive Descriptor - Extended */
+union e1000_rx_desc_extended {
+       struct {
+               __le64 buffer_addr;
+               __le64 reserved;
+       } read;
+       struct {
+               struct {
+                       __le32 mrq;           /* Multiple Rx Queues */
+                       union {
+                               __le32 rss;         /* RSS Hash */
+                               struct {
+                                       __le16 ip_id;  /* IP id */
+                                       __le16 csum;   /* Packet Checksum */
+                               } csum_ip;
+                       } hi_dword;
+               } lower;
+               struct {
+                       __le32 status_error;  /* ext status/error */
+                       __le16 length;
+                       __le16 vlan;          /* VLAN tag */
+               } upper;
+       } wb;  /* writeback */
+};
+
+#define MAX_PS_BUFFERS 4
+/* Receive Descriptor - Packet Split */
+union e1000_rx_desc_packet_split {
+       struct {
+               /* one buffer for protocol header(s), three data buffers */
+               __le64 buffer_addr[MAX_PS_BUFFERS];
+       } read;
+       struct {
+               struct {
+                       __le32 mrq;           /* Multiple Rx Queues */
+                       union {
+                               __le32 rss;           /* RSS Hash */
+                               struct {
+                                       __le16 ip_id;    /* IP id */
+                                       __le16 csum;     /* Packet Checksum */
+                               } csum_ip;
+                       } hi_dword;
+               } lower;
+               struct {
+                       __le32 status_error;  /* ext status/error */
+                       __le16 length0;       /* length of buffer 0 */
+                       __le16 vlan;          /* VLAN tag */
+               } middle;
+               struct {
+                       __le16 header_status;
+                       __le16 length[3];     /* length of buffers 1-3 */
+               } upper;
+               __le64 reserved;
+       } wb; /* writeback */
+};
+
+/* Transmit Descriptor */
+struct e1000_tx_desc {
+       __le64 buffer_addr;   /* Address of the descriptor's data buffer */
+       union {
+               __le32 data;
+               struct {
+                       __le16 length;    /* Data buffer length */
+                       u8 cso;           /* Checksum offset */
+                       u8 cmd;           /* Descriptor control */
+               } flags;
+       } lower;
+       union {
+               __le32 data;
+               struct {
+                       u8 status;        /* Descriptor status */
+                       u8 css;           /* Checksum start */
+                       __le16 special;
+               } fields;
+       } upper;
+};
+
+/* Offload Context Descriptor */
+struct e1000_context_desc {
+       union {
+               __le32 ip_config;
+               struct {
+                       u8 ipcss;         /* IP checksum start */
+                       u8 ipcso;         /* IP checksum offset */
+                       __le16 ipcse;     /* IP checksum end */
+               } ip_fields;
+       } lower_setup;
+       union {
+               __le32 tcp_config;
+               struct {
+                       u8 tucss;         /* TCP checksum start */
+                       u8 tucso;         /* TCP checksum offset */
+                       __le16 tucse;     /* TCP checksum end */
+               } tcp_fields;
+       } upper_setup;
+       __le32 cmd_and_length;
+       union {
+               __le32 data;
+               struct {
+                       u8 status;        /* Descriptor status */
+                       u8 hdr_len;       /* Header length */
+                       __le16 mss;       /* Maximum segment size */
+               } fields;
+       } tcp_seg_setup;
+};
+
+/* Offload data descriptor */
+struct e1000_data_desc {
+       __le64 buffer_addr;   /* Address of the descriptor's buffer address */
+       union {
+               __le32 data;
+               struct {
+                       __le16 length;    /* Data buffer length */
+                       u8 typ_len_ext;
+                       u8 cmd;
+               } flags;
+       } lower;
+       union {
+               __le32 data;
+               struct {
+                       u8 status;        /* Descriptor status */
+                       u8 popts;         /* Packet Options */
+                       __le16 special;
+               } fields;
+       } upper;
+};
+
+/* Statistics counters collected by the MAC */
+struct e1000_hw_stats {
+       u64 crcerrs;
+       u64 algnerrc;
+       u64 symerrs;
+       u64 rxerrc;
+       u64 mpc;
+       u64 scc;
+       u64 ecol;
+       u64 mcc;
+       u64 latecol;
+       u64 colc;
+       u64 dc;
+       u64 tncrs;
+       u64 sec;
+       u64 cexterr;
+       u64 rlec;
+       u64 xonrxc;
+       u64 xontxc;
+       u64 xoffrxc;
+       u64 xofftxc;
+       u64 fcruc;
+       u64 prc64;
+       u64 prc127;
+       u64 prc255;
+       u64 prc511;
+       u64 prc1023;
+       u64 prc1522;
+       u64 gprc;
+       u64 bprc;
+       u64 mprc;
+       u64 gptc;
+       u64 gorc;
+       u64 gotc;
+       u64 rnbc;
+       u64 ruc;
+       u64 rfc;
+       u64 roc;
+       u64 rjc;
+       u64 mgprc;
+       u64 mgpdc;
+       u64 mgptc;
+       u64 tor;
+       u64 tot;
+       u64 tpr;
+       u64 tpt;
+       u64 ptc64;
+       u64 ptc127;
+       u64 ptc255;
+       u64 ptc511;
+       u64 ptc1023;
+       u64 ptc1522;
+       u64 mptc;
+       u64 bptc;
+       u64 tsctc;
+       u64 tsctfc;
+       u64 iac;
+       u64 icrxptc;
+       u64 icrxatc;
+       u64 ictxptc;
+       u64 ictxatc;
+       u64 ictxqec;
+       u64 ictxqmtc;
+       u64 icrxdmtc;
+       u64 icrxoc;
+       u64 doosync;
+};
+
+
+struct e1000_phy_stats {
+       u32 idle_errors;
+       u32 receive_errors;
+};
+
+struct e1000_host_mng_dhcp_cookie {
+       u32 signature;
+       u8  status;
+       u8  reserved0;
+       u16 vlan_id;
+       u32 reserved1;
+       u16 reserved2;
+       u8  reserved3;
+       u8  checksum;
+};
+
+/* Host Interface "Rev 1" */
+struct e1000_host_command_header {
+       u8 command_id;
+       u8 command_length;
+       u8 command_options;
+       u8 checksum;
+};
+
+#define E1000_HI_MAX_DATA_LENGTH     252
+struct e1000_host_command_info {
+       struct e1000_host_command_header command_header;
+       u8 command_data[E1000_HI_MAX_DATA_LENGTH];
+};
+
+/* Host Interface "Rev 2" */
+struct e1000_host_mng_command_header {
+       u8  command_id;
+       u8  checksum;
+       u16 reserved1;
+       u16 reserved2;
+       u16 command_length;
+};
+
+#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
+struct e1000_host_mng_command_info {
+       struct e1000_host_mng_command_header command_header;
+       u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
+};
+
+#include "e1000e_mac.h"
+#include "e1000e_phy.h"
+#include "e1000e_nvm.h"
+#include "e1000e_manage.h"
+
+struct e1000_mac_operations {
+       /* Function pointers for the MAC. */
+       s32  (*init_params)(struct e1000_hw *);
+       s32  (*id_led_init)(struct e1000_hw *);
+       s32  (*blink_led)(struct e1000_hw *);
+       s32  (*check_for_link)(struct e1000_hw *);
+       bool (*check_mng_mode)(struct e1000_hw *hw);
+       s32  (*cleanup_led)(struct e1000_hw *);
+       void (*clear_hw_cntrs)(struct e1000_hw *);
+       void (*clear_vfta)(struct e1000_hw *);
+       s32  (*get_bus_info)(struct e1000_hw *);
+       void (*set_lan_id)(struct e1000_hw *);
+       s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
+       s32  (*led_on)(struct e1000_hw *);
+       s32  (*led_off)(struct e1000_hw *);
+       void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
+       s32  (*reset_hw)(struct e1000_hw *);
+       s32  (*init_hw)(struct e1000_hw *);
+       s32  (*setup_link)(struct e1000_hw *);
+       s32  (*setup_physical_interface)(struct e1000_hw *);
+       s32  (*setup_led)(struct e1000_hw *);
+       void (*write_vfta)(struct e1000_hw *, u32, u32);
+       void (*mta_set)(struct e1000_hw *, u32);
+       void (*config_collision_dist)(struct e1000_hw *);
+       void (*rar_set)(struct e1000_hw *, u8*, u32);
+       s32  (*read_mac_addr)(struct e1000_hw *);
+       s32  (*validate_mdi_setting)(struct e1000_hw *);
+       s32  (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*);
+       s32  (*mng_write_cmd_header)(struct e1000_hw *hw,
+                      struct e1000_host_mng_command_header*);
+       s32  (*mng_enable_host_if)(struct e1000_hw *);
+       s32  (*wait_autoneg)(struct e1000_hw *);
+};
+
+struct e1000_phy_operations {
+       s32  (*init_params)(struct e1000_hw *);
+       s32  (*acquire)(struct e1000_hw *);
+       s32  (*cfg_on_link_up)(struct e1000_hw *);
+       s32  (*check_polarity)(struct e1000_hw *);
+       s32  (*check_reset_block)(struct e1000_hw *);
+       s32  (*commit)(struct e1000_hw *);
+#if 0
+       s32  (*force_speed_duplex)(struct e1000_hw *);
+#endif
+       s32  (*get_cfg_done)(struct e1000_hw *hw);
+#if 0
+       s32  (*get_cable_length)(struct e1000_hw *);
+#endif
+       s32  (*get_info)(struct e1000_hw *);
+       s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
+       s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
+       void (*release)(struct e1000_hw *);
+       s32  (*reset)(struct e1000_hw *);
+       s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
+       s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
+       s32  (*write_reg)(struct e1000_hw *, u32, u16);
+       s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
+       void (*power_up)(struct e1000_hw *);
+       void (*power_down)(struct e1000_hw *);
+};
+
+struct e1000_nvm_operations {
+       s32  (*init_params)(struct e1000_hw *);
+       s32  (*acquire)(struct e1000_hw *);
+       s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
+       void (*release)(struct e1000_hw *);
+       void (*reload)(struct e1000_hw *);
+       s32  (*update)(struct e1000_hw *);
+       s32  (*valid_led_default)(struct e1000_hw *, u16 *);
+       s32  (*validate)(struct e1000_hw *);
+       s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
+};
+
+struct e1000_mac_info {
+       struct e1000_mac_operations ops;
+       u8 addr[6];
+       u8 perm_addr[6];
+
+       enum e1000_mac_type type;
+
+       u32 collision_delta;
+       u32 ledctl_default;
+       u32 ledctl_mode1;
+       u32 ledctl_mode2;
+       u32 mc_filter_type;
+       u32 tx_packet_delta;
+       u32 txcw;
+
+       u16 current_ifs_val;
+       u16 ifs_max_val;
+       u16 ifs_min_val;
+       u16 ifs_ratio;
+       u16 ifs_step_size;
+       u16 mta_reg_count;
+
+       /* Maximum size of the MTA register table in all supported adapters */
+       #define MAX_MTA_REG 128
+       u32 mta_shadow[MAX_MTA_REG];
+       u16 rar_entry_count;
+
+       u8  forced_speed_duplex;
+
+       bool adaptive_ifs;
+       bool arc_subsystem_valid;
+       bool asf_firmware_present;
+       bool autoneg;
+       bool autoneg_failed;
+       bool get_link_status;
+       bool in_ifs_mode;
+       enum e1000_serdes_link_state serdes_link_state;
+       bool serdes_has_link;
+       bool tx_pkt_filtering;
+};
+
+struct e1000_phy_info {
+       struct e1000_phy_operations ops;
+       enum e1000_phy_type type;
+
+       enum e1000_1000t_rx_status local_rx;
+       enum e1000_1000t_rx_status remote_rx;
+       enum e1000_ms_type ms_type;
+       enum e1000_ms_type original_ms_type;
+       enum e1000_rev_polarity cable_polarity;
+       enum e1000_smart_speed smart_speed;
+
+       u32 addr;
+       u32 id;
+       u32 reset_delay_us; /* in usec */
+       u32 revision;
+
+       enum e1000_media_type media_type;
+
+       u16 autoneg_advertised;
+       u16 autoneg_mask;
+       u16 cable_length;
+       u16 max_cable_length;
+       u16 min_cable_length;
+
+       u8 mdix;
+
+       bool disable_polarity_correction;
+       bool is_mdix;
+       bool polarity_correction;
+       bool reset_disable;
+       bool speed_downgraded;
+       bool autoneg_wait_to_complete;
+};
+
+struct e1000_nvm_info {
+       struct e1000_nvm_operations ops;
+       enum e1000_nvm_type type;
+       enum e1000_nvm_override override;
+
+       u32 flash_bank_size;
+       u32 flash_base_addr;
+
+       u16 word_size;
+       u16 delay_usec;
+       u16 address_bits;
+       u16 opcode_bits;
+       u16 page_size;
+};
+
+struct e1000_bus_info {
+       enum e1000_bus_type type;
+       enum e1000_bus_speed speed;
+       enum e1000_bus_width width;
+
+       u16 func;
+       u16 pci_cmd_word;
+};
+
+struct e1000_fc_info {
+       u32 high_water;          /* Flow control high-water mark */
+       u32 low_water;           /* Flow control low-water mark */
+       u16 pause_time;          /* Flow control pause timer */
+       bool send_xon;           /* Flow control send XON */
+       bool strict_ieee;        /* Strict IEEE mode */
+       enum e1000_fc_mode current_mode; /* FC mode in effect */
+       enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
+};
+
+struct e1000_dev_spec_82571 {
+       bool laa_is_present;
+       u32 smb_counter;
+};
+
+struct e1000_dev_spec_80003es2lan {
+       bool  mdic_wa_enable;
+};
+
+struct e1000_shadow_ram {
+       u16  value;
+       bool modified;
+};
+
+#define E1000_ICH8_SHADOW_RAM_WORDS            2048
+
+struct e1000_dev_spec_ich8lan {
+       bool kmrn_lock_loss_workaround_enabled;
+       struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS];
+       bool nvm_k1_enabled;
+};
+
+struct e1000_hw {
+       struct e1000_adapter *adapter;
+
+       u8 __iomem *hw_addr;
+       u8 __iomem *flash_address;
+
+       void *back;
+       unsigned long io_base;
+
+       struct e1000_mac_info  mac;
+       struct e1000_fc_info   fc;
+       struct e1000_phy_info  phy;
+       struct e1000_nvm_info  nvm;
+       struct e1000_bus_info  bus;
+       struct e1000_host_mng_dhcp_cookie mng_cookie;
+
+       union {
+               struct e1000_dev_spec_82571     _82571;
+               struct e1000_dev_spec_80003es2lan _80003es2lan;
+               struct e1000_dev_spec_ich8lan   ich8lan;
+       } dev_spec;
+
+       u16 device_id;
+       u16 subsystem_vendor_id;
+       u16 subsystem_device_id;
+       u16 vendor_id;
+
+       u8  revision_id;
+};
+
+#include "e1000e_82571.h"
+#include "e1000e_80003es2lan.h"
+#include "e1000e_ich8lan.h"
+
+/* These functions must be implemented by drivers */
+s32  e1000e_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
+
+#endif
diff --git a/src/drivers/net/e1000e/e1000e_ich8lan.c b/src/drivers/net/e1000e/e1000e_ich8lan.c
new file mode 100644 (file)
index 0000000..1f9b3c4
--- /dev/null
@@ -0,0 +1,3444 @@
+/*******************************************************************************
+
+  Intel PRO/1000 Linux driver
+  Copyright(c) 1999 - 2009 Intel Corporation.
+
+  This program is free software; you can redistribute it and/or modify it
+  under the terms and conditions of the GNU General Public License,
+  version 2, as published by the Free Software Foundation.
+
+  This program is distributed in the hope it will be useful, but WITHOUT
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+  more details.
+
+  You should have received a copy of the GNU General Public License along with
+  this program; if not, write to the Free Software Foundation, Inc.,
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+
+  The full GNU General Public License is included in this distribution in
+  the file called "COPYING".
+
+  Contact Information:
+  Linux NICS <linux.nics@intel.com>
+  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+
+*******************************************************************************/
+
+FILE_LICENCE ( GPL2_OR_LATER );
+
+/*
+ * 82562G 10/100 Network Connection
+ * 82562G-2 10/100 Network Connection
+ * 82562GT 10/100 Network Connection
+ * 82562GT-2 10/100 Network Connection
+ * 82562V 10/100 Network Connection
+ * 82562V-2 10/100 Network Connection
+ * 82566DC-2 Gigabit Network Connection
+ * 82566DC Gigabit Network Connection
+ * 82566DM-2 Gigabit Network Connection
+ * 82566DM Gigabit Network Connection
+ * 82566MC Gigabit Network Connection
+ * 82566MM Gigabit Network Connection
+ * 82567LM Gigabit Network Connection
+ * 82567LF Gigabit Network Connection
+ * 82567V Gigabit Network Connection
+ * 82567LM-2 Gigabit Network Connection
+ * 82567LF-2 Gigabit Network Connection
+ * 82567V-2 Gigabit Network Connection
+ * 82567LF-3 Gigabit Network Connection
+ * 82567LM-3 Gigabit Network Connection
+ * 82567LM-4 Gigabit Network Connection
+ * 82577LM Gigabit Network Connection
+ * 82577LC Gigabit Network Connection
+ * 82578DM Gigabit Network Connection
+ * 82578DC Gigabit Network Connection
+ */
+
+#include "e1000e.h"
+
+static s32  e1000e_init_phy_params_ich8lan(struct e1000_hw *hw);
+static s32  e1000e_init_phy_params_pchlan(struct e1000_hw *hw);
+static s32  e1000e_init_nvm_params_ich8lan(struct e1000_hw *hw);
+static s32  e1000e_init_mac_params_ich8lan(struct e1000_hw *hw);
+static s32  e1000e_acquire_swflag_ich8lan(struct e1000_hw *hw);
+static void e1000e_release_swflag_ich8lan(struct e1000_hw *hw);
+static s32  e1000e_acquire_nvm_ich8lan(struct e1000_hw *hw);
+static void e1000e_release_nvm_ich8lan(struct e1000_hw *hw);
+static bool e1000e_check_mng_mode_ich8lan(struct e1000_hw *hw);
+static s32  e1000e_check_reset_block_ich8lan(struct e1000_hw *hw);
+static s32  e1000e_phy_hw_reset_ich8lan(struct e1000_hw *hw);
+static s32  e1000e_get_phy_info_ich8lan(struct e1000_hw *hw);
+static s32  e1000e_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
+static s32  e1000e_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
+                                            bool active);
+static s32  e1000e_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
+                                            bool active);
+static s32  e1000e_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
+                                   u16 words, u16 *data);
+static s32  e1000e_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
+                                    u16 words, u16 *data);
+static s32  e1000e_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
+static s32  e1000e_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
+static s32  e1000e_valid_led_default_ich8lan(struct e1000_hw *hw,
+                                            u16 *data);
+static s32  e1000e_id_led_init_pchlan(struct e1000_hw *hw);
+static s32  e1000e_get_bus_info_ich8lan(struct e1000_hw *hw);
+static s32  e1000e_reset_hw_ich8lan(struct e1000_hw *hw);
+static s32  e1000e_init_hw_ich8lan(struct e1000_hw *hw);
+static s32  e1000e_setup_link_ich8lan(struct e1000_hw *hw);
+static s32  e1000e_setup_copper_link_ich8lan(struct e1000_hw *hw);
+static s32  e1000e_get_link_up_info_ich8lan(struct e1000_hw *hw,
+                                           u16 *speed, u16 *duplex);
+static s32  e1000e_cleanup_led_ich8lan(struct e1000_hw *hw);
+static s32  e1000e_led_on_ich8lan(struct e1000_hw *hw);
+static s32  e1000e_led_off_ich8lan(struct e1000_hw *hw);
+static s32  e1000e_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
+static s32  e1000e_setup_led_pchlan(struct e1000_hw *hw);
+static s32  e1000e_cleanup_led_pchlan(struct e1000_hw *hw);
+static s32  e1000e_led_on_pchlan(struct e1000_hw *hw);
+static s32  e1000e_led_off_pchlan(struct e1000_hw *hw);
+static void e1000e_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
+static s32  e1000e_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
+static s32  e1000e_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout);
+static s32  e1000e_flash_cycle_init_ich8lan(struct e1000_hw *hw);
+static s32  e1000e_get_phy_info_ife_ich8lan(struct e1000_hw *hw);
+static void e1000e_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
+static s32  e1000e_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
+static s32  e1000e_read_flash_byte_ich8lan(struct e1000_hw *hw,
+                                          u32 offset, u8 *data);
+static s32  e1000e_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
+                                          u8 size, u16 *data);
+static s32  e1000e_read_flash_word_ich8lan(struct e1000_hw *hw,
+                                          u32 offset, u16 *data);
+static s32  e1000e_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
+                                                 u32 offset, u8 byte);
+static s32  e1000e_write_flash_byte_ich8lan(struct e1000_hw *hw,
+                                           u32 offset, u8 data);
+static s32  e1000e_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
+                                           u8 size, u16 data);
+static s32  e1000e_get_cfg_done_ich8lan(struct e1000_hw *hw);
+static void e1000e_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
+static s32  e1000e_check_for_copper_link_ich8lan(struct e1000_hw *hw);
+static void e1000e_lan_init_done_ich8lan(struct e1000_hw *hw);
+static s32  e1000e_sw_lcd_config_ich8lan(struct e1000_hw *hw);
+
+/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
+/* Offset 04h HSFSTS */
+union ich8_hws_flash_status {
+       struct ich8_hsfsts {
+               u16 flcdone    :1; /* bit 0 Flash Cycle Done */
+               u16 flcerr     :1; /* bit 1 Flash Cycle Error */
+               u16 dael       :1; /* bit 2 Direct Access error Log */
+               u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
+               u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
+               u16 reserved1  :2; /* bit 13:6 Reserved */
+               u16 reserved2  :6; /* bit 13:6 Reserved */
+               u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
+               u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
+       } hsf_status;
+       u16 regval;
+};
+
+/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
+/* Offset 06h FLCTL */
+union ich8_hws_flash_ctrl {
+       struct ich8_hsflctl {
+               u16 flcgo      :1;   /* 0 Flash Cycle Go */
+               u16 flcycle    :2;   /* 2:1 Flash Cycle */
+               u16 reserved   :5;   /* 7:3 Reserved  */
+               u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
+               u16 flockdn    :6;   /* 15:10 Reserved */
+       } hsf_ctrl;
+       u16 regval;
+};
+
+/* ICH Flash Region Access Permissions */
+union ich8_hws_flash_regacc {
+       struct ich8_flracc {
+               u32 grra      :8; /* 0:7 GbE region Read Access */
+               u32 grwa      :8; /* 8:15 GbE region Write Access */
+               u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
+               u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
+       } hsf_flregacc;
+       u16 regval;
+};
+
+/**
+ *  e1000e_init_phy_params_pchlan - Initialize PHY function pointers
+ *  @hw: pointer to the HW structure
+ *
+ *  Initialize family-specific PHY parameters and function pointers.
+ **/
+static s32 e1000e_init_phy_params_pchlan(struct e1000_hw *hw)
+{
+       struct e1000_phy_info *phy = &hw->phy;
+       s32 ret_val = E1000_SUCCESS;
+
+       phy->addr                     = 1;
+       phy->reset_delay_us           = 100;
+
+       phy->ops.acquire              = e1000e_acquire_swflag_ich8lan;
+       phy->ops.check_polarity       = e1000e_check_polarity_ife;
+       phy->ops.check_reset_block    = e1000e_check_reset_block_ich8lan;
+#if 0
+       phy->ops.force_speed_duplex   = e1000e_phy_force_speed_duplex_ife;
+#endif
+#if 0
+       phy->ops.get_cable_length     = e1000e_get_cable_length_igp_2;
+#endif
+       phy->ops.get_cfg_done         = e1000e_get_cfg_done_ich8lan;
+       phy->ops.get_info             = e1000e_get_phy_info_ich8lan;
+       phy->ops.read_reg             = e1000e_read_phy_reg_hv;
+       phy->ops.read_reg_locked      = e1000e_read_phy_reg_hv_locked;
+       phy->ops.release              = e1000e_release_swflag_ich8lan;
+       phy->ops.reset                = e1000e_phy_hw_reset_ich8lan;
+       phy->ops.set_d0_lplu_state    = e1000e_set_lplu_state_pchlan;
+       phy->ops.set_d3_lplu_state    = e1000e_set_lplu_state_pchlan;
+       phy->ops.write_reg            = e1000e_write_phy_reg_hv;
+       phy->ops.write_reg_locked     = e1000e_write_phy_reg_hv_locked;
+       phy->ops.power_up             = e1000e_power_up_phy_copper;
+       phy->ops.power_down           = e1000e_power_down_phy_copper_ich8lan;
+       phy->autoneg_mask             = AUTONEG_ADVERTISE_SPEED_DEFAULT;
+
+       phy->id = e1000_phy_unknown;
+       e1000e_get_phy_id(hw);
+       phy->type = e1000e_get_phy_type_from_id(phy->id);
+
+       if (phy->type == e1000_phy_82577) {
+               phy->ops.check_polarity = e1000e_check_polarity_82577;
+#if 0
+               phy->ops.force_speed_duplex =
+                       e1000e_phy_force_speed_duplex_82577;
+#endif
+#if 0
+               phy->ops.get_cable_length   = e1000e_get_cable_length_82577;
+#endif
+               phy->ops.get_info = e1000e_get_phy_info_82577;
+               phy->ops.commit = e1000e_phy_sw_reset;
+       }
+
+       return ret_val;
+}
+
+/**
+ *  e1000e_init_phy_params_ich8lan - Initialize PHY function pointers
+ *  @hw: pointer to the HW structure
+ *
+ *  Initialize family-specific PHY parameters and function pointers.
+ **/
+static s32 e1000e_init_phy_params_ich8lan(struct e1000_hw *hw)
+{
+       struct e1000_phy_info *phy = &hw->phy;
+       s32 ret_val = E1000_SUCCESS;
+       u16 i = 0;
+
+       phy->addr                     = 1;
+       phy->reset_delay_us           = 100;
+
+       phy->ops.acquire              = e1000e_acquire_swflag_ich8lan;
+       phy->ops.check_polarity       = e1000e_check_polarity_ife;
+       phy->ops.check_reset_block    = e1000e_check_reset_block_ich8lan;
+#if 0
+       phy->ops.force_speed_duplex   = e1000e_phy_force_speed_duplex_ife;
+#endif
+#if 0
+       phy->ops.get_cable_length     = e1000e_get_cable_length_igp_2;
+#endif
+       phy->ops.get_cfg_done         = e1000e_get_cfg_done_ich8lan;
+       phy->ops.get_info             = e1000e_get_phy_info_ich8lan;
+       phy->ops.read_reg             = e1000e_read_phy_reg_igp;
+       phy->ops.release              = e1000e_release_swflag_ich8lan;
+       phy->ops.reset                = e1000e_phy_hw_reset_ich8lan;
+       phy->ops.set_d0_lplu_state    = e1000e_set_d0_lplu_state_ich8lan;
+       phy->ops.set_d3_lplu_state    = e1000e_set_d3_lplu_state_ich8lan;
+       phy->ops.write_reg            = e1000e_write_phy_reg_igp;
+       phy->ops.power_up             = e1000e_power_up_phy_copper;
+       phy->ops.power_down           = e1000e_power_down_phy_copper_ich8lan;
+
+       /*
+        * We may need to do this twice - once for IGP and if that fails,
+        * we'll set BM func pointers and try again
+        */
+       ret_val = e1000e_determine_phy_address(hw);
+       if (ret_val) {
+               phy->ops.write_reg = e1000e_write_phy_reg_bm;
+               phy->ops.read_reg  = e1000e_read_phy_reg_bm;
+               ret_val = e1000e_determine_phy_address(hw);
+               if (ret_val) {
+                       DBG("Cannot determine PHY addr. Erroring out\n");
+                       goto out;
+               }
+       }
+
+       phy->id = 0;
+       while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
+              (i++ < 100)) {
+               msleep(1);
+               ret_val = e1000e_get_phy_id(hw);
+               if (ret_val)
+                       goto out;
+       }
+
+       /* Verify phy id */
+       switch (phy->id) {
+       case IGP03E1000_E_PHY_ID:
+               phy->type = e1000_phy_igp_3;
+               phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
+               phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
+               phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
+               break;
+       case IFE_E_PHY_ID:
+       case IFE_PLUS_E_PHY_ID:
+       case IFE_C_E_PHY_ID:
+               phy->type = e1000_phy_ife;
+               phy->autoneg_mask = E1000_ALL_NOT_GIG;
+               break;
+       case BME1000_E_PHY_ID:
+               phy->type = e1000_phy_bm;
+               phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
+               phy->ops.read_reg = e1000e_read_phy_reg_bm;
+               phy->ops.write_reg = e1000e_write_phy_reg_bm;
+               phy->ops.commit = e1000e_phy_sw_reset;
+               break;
+       default:
+               ret_val = -E1000_ERR_PHY;
+               goto out;
+       }
+
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000e_init_nvm_params_ich8lan - Initialize NVM function pointers
+ *  @hw: pointer to the HW structure
+ *
+ *  Initialize family-specific NVM parameters and function
+ *  pointers.
+ **/
+static s32 e1000e_init_nvm_params_ich8lan(struct e1000_hw *hw)
+{
+       struct e1000_nvm_info *nvm = &hw->nvm;
+       struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
+       u32 gfpreg, sector_base_addr, sector_end_addr;
+       s32 ret_val = E1000_SUCCESS;
+       u16 i;
+
+       /* Can't read flash registers if the register set isn't mapped. */
+       if (!hw->flash_address) {
+               e_dbg("ERROR: Flash registers not mapped\n");
+               ret_val = -E1000_ERR_CONFIG;
+               goto out;
+       }
+
+       nvm->type = e1000_nvm_flash_sw;
+
+       gfpreg = er32flash(ICH_FLASH_GFPREG);
+
+       /*
+        * sector_X_addr is a "sector"-aligned address (4096 bytes)
+        * Add 1 to sector_end_addr since this sector is included in
+        * the overall size.
+        */
+       sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
+       sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
+
+       /* flash_base_addr is byte-aligned */
+       nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
+
+       /*
+        * find total size of the NVM, then cut in half since the total
+        * size represents two separate NVM banks.
+        */
+       nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
+                                 << FLASH_SECTOR_ADDR_SHIFT;
+       nvm->flash_bank_size /= 2;
+       /* Adjust to word count */
+       nvm->flash_bank_size /= sizeof(u16);
+
+       nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
+
+       /* Clear shadow ram */
+       for (i = 0; i < nvm->word_size; i++) {
+               dev_spec->shadow_ram[i].modified = false;
+               dev_spec->shadow_ram[i].value    = 0xFFFF;
+       }
+
+       /* Function Pointers */
+       nvm->ops.acquire       = e1000e_acquire_nvm_ich8lan;
+       nvm->ops.release       = e1000e_release_nvm_ich8lan;
+       nvm->ops.read          = e1000e_read_nvm_ich8lan;
+       nvm->ops.update        = e1000e_update_nvm_checksum_ich8lan;
+       nvm->ops.valid_led_default = e1000e_valid_led_default_ich8lan;
+       nvm->ops.validate      = e1000e_validate_nvm_checksum_ich8lan;
+       nvm->ops.write         = e1000e_write_nvm_ich8lan;
+
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000e_init_mac_params_ich8lan - Initialize MAC function pointers
+ *  @hw: pointer to the HW structure
+ *
+ *  Initialize family-specific MAC parameters and function
+ *  pointers.
+ **/
+static s32 e1000e_init_mac_params_ich8lan(struct e1000_hw *hw)
+{
+       struct e1000_mac_info *mac = &hw->mac;
+
+       /* Set media type function pointer */
+       hw->phy.media_type = e1000_media_type_copper;
+
+       /* Set mta register count */
+       mac->mta_reg_count = 32;
+       /* Set rar entry count */
+       mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
+       if (mac->type == e1000_ich8lan)
+               mac->rar_entry_count--;
+       /* Set if part includes ASF firmware */
+       mac->asf_firmware_present = true;
+       /* Set if manageability features are enabled. */
+       mac->arc_subsystem_valid = true;
+
+       /* Function pointers */
+
+       /* bus type/speed/width */
+       mac->ops.get_bus_info = e1000e_get_bus_info_ich8lan;
+       /* function id */
+       mac->ops.set_lan_id = e1000e_set_lan_id_single_port;
+       /* reset */
+       mac->ops.reset_hw = e1000e_reset_hw_ich8lan;
+       /* hw initialization */
+       mac->ops.init_hw = e1000e_init_hw_ich8lan;
+       /* link setup */
+       mac->ops.setup_link = e1000e_setup_link_ich8lan;
+       /* physical interface setup */
+       mac->ops.setup_physical_interface = e1000e_setup_copper_link_ich8lan;
+       /* check for link */
+       mac->ops.check_for_link = e1000e_check_for_copper_link_ich8lan;
+       /* check management mode */
+       mac->ops.check_mng_mode = e1000e_check_mng_mode_ich8lan;
+       /* link info */
+       mac->ops.get_link_up_info = e1000e_get_link_up_info_ich8lan;
+       /* multicast address update */
+       mac->ops.update_mc_addr_list = e1000e_update_mc_addr_list_generic;
+       /* setting MTA */
+       mac->ops.mta_set = e1000e_mta_set_generic;
+       /* clear hardware counters */
+       mac->ops.clear_hw_cntrs = e1000e_clear_hw_cntrs_ich8lan;
+
+       /* LED operations */
+       switch (mac->type) {
+       case e1000_ich8lan:
+       case e1000_ich9lan:
+       case e1000_ich10lan:
+               /* ID LED init */
+               mac->ops.id_led_init = e1000e_id_led_init;
+               /* blink LED */
+               mac->ops.blink_led = e1000e_blink_led;
+               /* setup LED */
+               mac->ops.setup_led = e1000e_setup_led_generic;
+               /* cleanup LED */
+               mac->ops.cleanup_led = e1000e_cleanup_led_ich8lan;
+               /* turn on/off LED */
+               mac->ops.led_on = e1000e_led_on_ich8lan;
+               mac->ops.led_off = e1000e_led_off_ich8lan;
+               break;
+       case e1000_pchlan:
+               /* ID LED init */
+               mac->ops.id_led_init = e1000e_id_led_init_pchlan;
+               /* setup LED */
+               mac->ops.setup_led = e1000e_setup_led_pchlan;
+               /* cleanup LED */
+               mac->ops.cleanup_led = e1000e_cleanup_led_pchlan;
+               /* turn on/off LED */
+               mac->ops.led_on = e1000e_led_on_pchlan;
+               mac->ops.led_off = e1000e_led_off_pchlan;
+               break;
+       default:
+               break;
+       }
+
+       /* Enable PCS Lock-loss workaround for ICH8 */
+       if (mac->type == e1000_ich8lan)
+               e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
+
+
+       return E1000_SUCCESS;
+}
+
+/**
+ *  e1000e_check_for_copper_link_ich8lan - Check for link (Copper)
+ *  @hw: pointer to the HW structure
+ *
+ *  Checks to see of the link status of the hardware has changed.  If a
+ *  change in link status has been detected, then we read the PHY registers
+ *  to get the current speed/duplex if link exists.
+ **/
+static s32 e1000e_check_for_copper_link_ich8lan(struct e1000_hw *hw)
+{
+       struct e1000_mac_info *mac = &hw->mac;
+       s32 ret_val;
+       bool link;
+
+       /*
+        * We only want to go out to the PHY registers to see if Auto-Neg
+        * has completed and/or if our link status has changed.  The
+        * get_link_status flag is set upon receiving a Link Status
+        * Change or Rx Sequence Error interrupt.
+        */
+       if (!mac->get_link_status) {
+               ret_val = E1000_SUCCESS;
+               goto out;
+       }
+
+       /*
+        * First we want to see if the MII Status Register reports
+        * link.  If so, then we want to get the current speed/duplex
+        * of the PHY.
+        */
+       ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
+       if (ret_val)
+               goto out;
+
+       if (hw->mac.type == e1000_pchlan) {
+               ret_val = e1000e_k1_gig_workaround_hv(hw, link);
+               if (ret_val)
+                       goto out;
+       }
+
+       if (!link)
+               goto out; /* No link detected */
+
+       mac->get_link_status = false;
+
+       if (hw->phy.type == e1000_phy_82578) {
+               ret_val = e1000e_link_stall_workaround_hv(hw);
+               if (ret_val)
+                       goto out;
+       }
+
+       /*
+        * Check if there was DownShift, must be checked
+        * immediately after link-up
+        */
+       e1000e_check_downshift(hw);
+
+       /*
+        * If we are forcing speed/duplex, then we simply return since
+        * we have already determined whether we have link or not.
+        */
+       if (!mac->autoneg) {
+               ret_val = -E1000_ERR_CONFIG;
+               goto out;
+       }
+
+       /*
+        * Auto-Neg is enabled.  Auto Speed Detection takes care
+        * of MAC speed/duplex configuration.  So we only need to
+        * configure Collision Distance in the MAC.
+        */
+       e1000e_config_collision_dist(hw);
+
+       /*
+        * Configure Flow Control now that Auto-Neg has completed.
+        * First, we need to restore the desired flow control
+        * settings because we may have had to re-autoneg with a
+        * different link partner.
+        */
+       ret_val = e1000e_config_fc_after_link_up(hw);
+       if (ret_val)
+               e_dbg("Error configuring flow control\n");
+
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000e_init_function_pointers_ich8lan - Initialize ICH8 function pointers
+ *  @hw: pointer to the HW structure
+ *
+ *  Initialize family-specific function pointers for PHY, MAC, and NVM.
+ **/
+void e1000e_init_function_pointers_ich8lan(struct e1000_hw *hw)
+{
+       e1000e_init_mac_ops_generic(hw);
+       e1000e_init_nvm_ops_generic(hw);
+       hw->mac.ops.init_params = e1000e_init_mac_params_ich8lan;
+       hw->nvm.ops.init_params = e1000e_init_nvm_params_ich8lan;
+       switch (hw->mac.type) {
+       case e1000_ich8lan:
+       case e1000_ich9lan:
+       case e1000_ich10lan:
+               hw->phy.ops.init_params = e1000e_init_phy_params_ich8lan;
+               break;
+       case e1000_pchlan:
+               hw->phy.ops.init_params = e1000e_init_phy_params_pchlan;
+               break;
+       default:
+               break;
+       }
+}
+
+#if 0
+static DEFINE_MUTEX(nvm_mutex);
+#endif
+
+/**
+ *  e1000e_acquire_nvm_ich8lan - Acquire NVM mutex
+ *  @hw: pointer to the HW structure
+ *
+ *  Acquires the mutex for performing NVM operations.
+ **/
+static s32 e1000e_acquire_nvm_ich8lan(struct e1000_hw *hw __unused)
+{
+#if 0
+       mutex_lock(&nvm_mutex);
+#endif
+       return E1000_SUCCESS;
+}
+
+/**
+ *  e1000e_release_nvm_ich8lan - Release NVM mutex
+ *  @hw: pointer to the HW structure
+ *
+ *  Releases the mutex used while performing NVM operations.
+ **/
+static void e1000e_release_nvm_ich8lan(struct e1000_hw *hw __unused)
+{
+#if 0
+       mutex_unlock(&nvm_mutex);
+#endif
+       return;
+}
+
+#if 0
+static DEFINE_MUTEX(swflag_mutex);
+#endif
+
+/**
+ *  e1000e_acquire_swflag_ich8lan - Acquire software control flag
+ *  @hw: pointer to the HW structure
+ *
+ *  Acquires the software control flag for performing PHY and select
+ *  MAC CSR accesses.
+ **/
+static s32 e1000e_acquire_swflag_ich8lan(struct e1000_hw *hw)
+{
+       u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
+       s32 ret_val = E1000_SUCCESS;
+
+#if 0
+       mutex_lock(&swflag_mutex);
+#endif
+
+       while (timeout) {
+               extcnf_ctrl = er32(EXTCNF_CTRL);
+               if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
+                       break;
+
+               mdelay(1);
+               timeout--;
+       }
+
+       if (!timeout) {
+               e_dbg("SW/FW/HW has locked the resource for too long.\n");
+               ret_val = -E1000_ERR_CONFIG;
+               goto out;
+       }
+
+       timeout = SW_FLAG_TIMEOUT;
+
+       extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
+       ew32(EXTCNF_CTRL, extcnf_ctrl);
+
+       while (timeout) {
+               extcnf_ctrl = er32(EXTCNF_CTRL);
+               if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
+                       break;
+
+               mdelay(1);
+               timeout--;
+       }
+
+       if (!timeout) {
+               e_dbg("Failed to acquire the semaphore.\n");
+               extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
+               ew32(EXTCNF_CTRL, extcnf_ctrl);
+               ret_val = -E1000_ERR_CONFIG;
+               goto out;
+       }
+
+out:
+#if 0
+       if (ret_val)
+               mutex_unlock(&swflag_mutex);
+#endif
+       return ret_val;
+}
+
+/**
+ *  e1000e_release_swflag_ich8lan - Release software control flag
+ *  @hw: pointer to the HW structure
+ *
+ *  Releases the software control flag for performing PHY and select
+ *  MAC CSR accesses.
+ **/
+static void e1000e_release_swflag_ich8lan(struct e1000_hw *hw)
+{
+       u32 extcnf_ctrl;
+
+       extcnf_ctrl = er32(EXTCNF_CTRL);
+       extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
+       ew32(EXTCNF_CTRL, extcnf_ctrl);
+
+#if 0
+       mutex_unlock(&swflag_mutex);
+#endif
+       return;
+}
+
+/**
+ *  e1000e_check_mng_mode_ich8lan - Checks management mode
+ *  @hw: pointer to the HW structure
+ *
+ *  This checks if the adapter has manageability enabled.
+ *  This is a function pointer entry point only called by read/write
+ *  routines for the PHY and NVM parts.
+ **/
+static bool e1000e_check_mng_mode_ich8lan(struct e1000_hw *hw)
+{
+       u32 fwsm;
+
+       fwsm = er32(FWSM);
+       return (fwsm & E1000_FWSM_MODE_MASK) ==
+               (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
+}
+/**
+ *  e1000e_check_reset_block_ich8lan - Check if PHY reset is blocked
+ *  @hw: pointer to the HW structure
+ *
+ *  Checks if firmware is blocking the reset of the PHY.
+ *  This is a function pointer entry point only called by
+ *  reset routines.
+ **/
+static s32 e1000e_check_reset_block_ich8lan(struct e1000_hw *hw)
+{
+       u32 fwsm;
+
+       fwsm = er32(FWSM);
+       return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? E1000_SUCCESS
+                                               : E1000_BLK_PHY_RESET;
+}
+
+/**
+ *  e1000e_sw_lcd_config_ich8lan - SW-based LCD Configuration
+ *  @hw:   pointer to the HW structure
+ *
+ *  SW should configure the LCD from the NVM extended configuration region
+ *  as a workaround for certain parts.
+ **/
+static s32 e1000e_sw_lcd_config_ich8lan(struct e1000_hw *hw)
+{
+       struct e1000_phy_info *phy = &hw->phy;
+       u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
+       s32 ret_val;
+       u16 word_addr, reg_data, reg_addr, phy_page = 0;
+
+       ret_val = hw->phy.ops.acquire(hw);
+       if (ret_val)
+               return ret_val;
+
+       /*
+        * Initialize the PHY from the NVM on ICH platforms.  This
+        * is needed due to an issue where the NVM configuration is
+        * not properly autoloaded after power transitions.
+        * Therefore, after each PHY reset, we will load the
+        * configuration data out of the NVM manually.
+        */
+       if ((hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) ||
+               (hw->mac.type == e1000_pchlan)) {
+               /* Check if SW needs to configure the PHY */
+               if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
+                   (hw->device_id == E1000_DEV_ID_ICH8_IGP_M) ||
+                   (hw->mac.type == e1000_pchlan))
+                       sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
+               else
+                       sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
+
+               data = er32(FEXTNVM);
+               if (!(data & sw_cfg_mask))
+                       goto out;
+
+               /* Wait for basic configuration completes before proceeding */
+               e1000e_lan_init_done_ich8lan(hw);
+
+               /*
+                * Make sure HW does not configure LCD from PHY
+                * extended configuration before SW configuration
+                */
+               data = er32(EXTCNF_CTRL);
+               if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
+                       goto out;
+
+               cnf_size = er32(EXTCNF_SIZE);
+               cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
+               cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
+               if (!cnf_size)
+                       goto out;
+
+               cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
+               cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
+
+               if (!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
+                   (hw->mac.type == e1000_pchlan)) {
+                       /*
+                        * HW configures the SMBus address and LEDs when the
+                        * OEM and LCD Write Enable bits are set in the NVM.
+                        * When both NVM bits are cleared, SW will configure
+                        * them instead.
+                        */
+                       data = er32(STRAP);
+                       data &= E1000_STRAP_SMBUS_ADDRESS_MASK;
+                       reg_data = data >> E1000_STRAP_SMBUS_ADDRESS_SHIFT;
+                       reg_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
+                       ret_val = e1000e_write_phy_reg_hv_locked(hw, HV_SMB_ADDR,
+                                                               reg_data);
+                       if (ret_val)
+                               goto out;
+
+                       data = er32(LEDCTL);
+                       ret_val = e1000e_write_phy_reg_hv_locked(hw,
+                                                               HV_LED_CONFIG,
+                                                               (u16)data);
+                       if (ret_val)
+                               goto out;
+               }
+
+               /* Configure LCD from extended configuration region. */
+
+               /* cnf_base_addr is in DWORD */
+               word_addr = (u16)(cnf_base_addr << 1);
+
+               for (i = 0; i < cnf_size; i++) {
+                       ret_val = e1000e_read_nvm(hw, (word_addr + i * 2), 1,
+                                                  &reg_data);
+                       if (ret_val)
+                               goto out;
+
+                       ret_val = e1000e_read_nvm(hw, (word_addr + i * 2 + 1),
+                                                  1, &reg_addr);
+                       if (ret_val)
+                               goto out;
+
+                       /* Save off the PHY page for future writes. */
+                       if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
+                               phy_page = reg_data;
+                               continue;
+                       }
+
+                       reg_addr &= PHY_REG_MASK;
+                       reg_addr |= phy_page;
+
+                       ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
+                                                           reg_data);
+                       if (ret_val)
+                               goto out;
+               }
+       }
+
+out:
+       hw->phy.ops.release(hw);
+       return ret_val;
+}
+
+/**
+ *  e1000e_k1_gig_workaround_hv - K1 Si workaround
+ *  @hw:   pointer to the HW structure
+ *  @link: link up bool flag
+ *
+ *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
+ *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
+ *  If link is down, the function will restore the default K1 setting located
+ *  in the NVM.
+ **/
+static s32 e1000e_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
+{
+       s32 ret_val = E1000_SUCCESS;
+       u16 status_reg = 0;
+       bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
+
+       if (hw->mac.type != e1000_pchlan)
+               goto out;
+
+       /* Wrap the whole flow with the sw flag */
+       ret_val = hw->phy.ops.acquire(hw);
+       if (ret_val)
+               goto out;
+
+       /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
+       if (link) {
+               if (hw->phy.type == e1000_phy_82578) {
+                       ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
+                                                             &status_reg);
+                       if (ret_val)
+                               goto release;
+
+                       status_reg &= BM_CS_STATUS_LINK_UP |
+                                     BM_CS_STATUS_RESOLVED |
+                                     BM_CS_STATUS_SPEED_MASK;
+
+                       if (status_reg == (BM_CS_STATUS_LINK_UP |
+                                          BM_CS_STATUS_RESOLVED |
+                                          BM_CS_STATUS_SPEED_1000))
+                               k1_enable = false;
+               }
+
+               if (hw->phy.type == e1000_phy_82577) {
+                       ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
+                                                             &status_reg);
+                       if (ret_val)
+                               goto release;
+
+                       status_reg &= HV_M_STATUS_LINK_UP |
+                                     HV_M_STATUS_AUTONEG_COMPLETE |
+                                     HV_M_STATUS_SPEED_MASK;
+
+                       if (status_reg == (HV_M_STATUS_LINK_UP |
+                                          HV_M_STATUS_AUTONEG_COMPLETE |
+                                          HV_M_STATUS_SPEED_1000))
+                               k1_enable = false;
+               }
+
+               /* Link stall fix for link up */
+               ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
+                                                      0x0100);
+               if (ret_val)
+                       goto release;
+
+       } else {
+               /* Link stall fix for link down */
+               ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
+                                                      0x4100);
+               if (ret_val)
+                       goto release;
+       }
+
+       ret_val = e1000e_configure_k1_ich8lan(hw, k1_enable);
+
+release:
+       hw->phy.ops.release(hw);
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000e_configure_k1_ich8lan - Configure K1 power state
+ *  @hw: pointer to the HW structure
+ *  @enable: K1 state to configure
+ *
+ *  Configure the K1 power state based on the provided parameter.
+ *  Assumes semaphore already acquired.
+ *
+ *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
+ **/
+s32 e1000e_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
+{
+       s32 ret_val = E1000_SUCCESS;
+       u32 ctrl_reg = 0;
+       u32 ctrl_ext = 0;
+       u32 reg = 0;
+       u16 kmrn_reg = 0;
+
+       ret_val = e1000e_read_kmrn_reg_locked(hw,
+                                            E1000_KMRNCTRLSTA_K1_CONFIG,
+                                            &kmrn_reg);
+       if (ret_val)
+               goto out;
+
+       if (k1_enable)
+               kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
+       else
+               kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
+
+       ret_val = e1000e_write_kmrn_reg_locked(hw,
+                                             E1000_KMRNCTRLSTA_K1_CONFIG,
+                                             kmrn_reg);
+       if (ret_val)
+               goto out;
+
+       udelay(20);
+       ctrl_ext = er32(CTRL_EXT);
+       ctrl_reg = er32(CTRL);
+
+       reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
+       reg |= E1000_CTRL_FRCSPD;
+       ew32(CTRL, reg);
+
+       E1000_WRITE_REG(hw,
+                       E1000_CTRL_EXT,
+                       ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
+       udelay(20);
+       ew32(CTRL, ctrl_reg);
+       ew32(CTRL_EXT, ctrl_ext);
+       udelay(20);
+
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000e_oem_bits_config_ich8lan - SW-based LCD Configuration
+ *  @hw:       pointer to the HW structure
+ *  @d0_state: boolean if entering d0 or d3 device state
+ *
+ *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
+ *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
+ *  in NVM determines whether HW should configure LPLU and Gbe Disable.
+ **/
+s32 e1000e_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
+{
+       s32 ret_val = 0;
+       u32 mac_reg;
+       u16 oem_reg;
+
+       if (hw->mac.type != e1000_pchlan)
+               return ret_val;
+
+       ret_val = hw->phy.ops.acquire(hw);
+       if (ret_val)
+               return ret_val;
+
+       mac_reg = er32(EXTCNF_CTRL);
+       if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
+               goto out;
+
+       mac_reg = er32(FEXTNVM);
+       if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
+               goto out;
+
+       mac_reg = er32(PHY_CTRL);
+
+       ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
+       if (ret_val)
+               goto out;
+
+       oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
+
+       if (d0_state) {
+               if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
+                       oem_reg |= HV_OEM_BITS_GBE_DIS;
+
+               if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
+                       oem_reg |= HV_OEM_BITS_LPLU;
+       } else {
+               if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE)
+                       oem_reg |= HV_OEM_BITS_GBE_DIS;
+
+               if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU)
+                       oem_reg |= HV_OEM_BITS_LPLU;
+       }
+       /* Restart auto-neg to activate the bits */
+       if (!e1000e_check_reset_block(hw))
+               oem_reg |= HV_OEM_BITS_RESTART_AN;
+       ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
+
+out:
+       hw->phy.ops.release(hw);
+
+       return ret_val;
+}
+
+/**
+ *  e1000e_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
+ *  done after every PHY reset.
+ **/
+static s32 e1000e_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
+{
+       s32 ret_val = E1000_SUCCESS;
+
+       if (hw->mac.type != e1000_pchlan)
+               goto out;
+
+       if (((hw->phy.type == e1000_phy_82577) &&
+            ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
+           ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
+               /* Disable generation of early preamble */
+               ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
+               if (ret_val)
+                       goto out;
+
+               /* Preamble tuning for SSC */
+               ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
+               if (ret_val)
+                       goto out;
+       }
+
+       if (hw->phy.type == e1000_phy_82578) {
+               /*
+                * Return registers to default by doing a soft reset then
+                * writing 0x3140 to the control register.
+                */
+               if (hw->phy.revision < 2) {
+                       e1000e_phy_sw_reset(hw);
+                       ret_val = e1e_wphy(hw, PHY_CONTROL,
+                                                       0x3140);
+               }
+       }
+
+       /* Select page 0 */
+       ret_val = hw->phy.ops.acquire(hw);
+       if (ret_val)
+               goto out;
+
+       hw->phy.addr = 1;
+       ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
+       if (ret_val)
+               goto out;
+       hw->phy.ops.release(hw);
+
+       /*
+        * Configure the K1 Si workaround during phy reset assuming there is
+        * link so that it disables K1 if link is in 1Gbps.
+        */
+       ret_val = e1000e_k1_gig_workaround_hv(hw, true);
+
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000e_lan_init_done_ich8lan - Check for PHY config completion
+ *  @hw: pointer to the HW structure
+ *
+ *  Check the appropriate indication the MAC has finished configuring the
+ *  PHY after a software reset.
+ **/
+static void e1000e_lan_init_done_ich8lan(struct e1000_hw *hw)
+{
+       u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
+
+       /* Wait for basic configuration completes before proceeding */
+       do {
+               data = er32(STATUS);
+               data &= E1000_STATUS_LAN_INIT_DONE;
+               udelay(100);
+       } while ((!data) && --loop);
+
+       /*
+        * If basic configuration is incomplete before the above loop
+        * count reaches 0, loading the configuration from NVM will
+        * leave the PHY in a bad state possibly resulting in no link.
+        */
+       if (loop == 0)
+               e_dbg("LAN_INIT_DONE not set, increase timeout\n");
+
+       /* Clear the Init Done bit for the next init event */
+       data = er32(STATUS);
+       data &= ~E1000_STATUS_LAN_INIT_DONE;
+       ew32(STATUS, data);
+}
+
+/**
+ *  e1000e_phy_hw_reset_ich8lan - Performs a PHY reset
+ *  @hw: pointer to the HW structure
+ *
+ *  Resets the PHY
+ *  This is a function pointer entry point called by drivers
+ *  or other shared routines.
+ **/
+static s32 e1000e_phy_hw_reset_ich8lan(struct e1000_hw *hw)
+{
+       s32 ret_val = E1000_SUCCESS;
+       u16 reg;
+
+       ret_val = e1000e_phy_hw_reset_generic(hw);
+       if (ret_val)
+               goto out;
+
+       /* Allow time for h/w to get to a quiescent state after reset */
+       msleep(10);
+
+       if (hw->mac.type == e1000_pchlan) {
+               ret_val = e1000e_hv_phy_workarounds_ich8lan(hw);
+               if (ret_val)
+                       goto out;
+       }
+
+       /* Dummy read to clear the phy wakeup bit after lcd reset */
+       if (hw->mac.type == e1000_pchlan)
+               e1e_rphy(hw, BM_WUC, &reg);
+
+       /* Configure the LCD with the extended configuration region in NVM */
+       ret_val = e1000e_sw_lcd_config_ich8lan(hw);
+       if (ret_val)
+               goto out;
+
+       /* Configure the LCD with the OEM bits in NVM */
+       if (hw->mac.type == e1000_pchlan)
+               ret_val = e1000e_oem_bits_config_ich8lan(hw, true);
+
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000e_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
+ *  @hw: pointer to the HW structure
+ *
+ *  Wrapper for calling the get_phy_info routines for the appropriate phy type.
+ **/
+static s32 e1000e_get_phy_info_ich8lan(struct e1000_hw *hw)
+{
+       s32 ret_val = -E1000_ERR_PHY_TYPE;
+
+       switch (hw->phy.type) {
+       case e1000_phy_ife:
+               ret_val = e1000e_get_phy_info_ife_ich8lan(hw);
+               break;
+       case e1000_phy_igp_3:
+       case e1000_phy_bm:
+       case e1000_phy_82578:
+       case e1000_phy_82577:
+               ret_val = e1000e_get_phy_info_igp(hw);
+               break;
+       default:
+               break;
+       }
+
+       return ret_val;
+}
+
+/**
+ *  e1000e_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states
+ *  @hw: pointer to the HW structure
+ *
+ *  Populates "phy" structure with various feature states.
+ *  This function is only called by other family-specific
+ *  routines.
+ **/
+static s32 e1000e_get_phy_info_ife_ich8lan(struct e1000_hw *hw)
+{
+       struct e1000_phy_info *phy = &hw->phy;
+       s32 ret_val;
+       u16 data;
+       bool link;
+
+       ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
+       if (ret_val)
+               goto out;
+
+       if (!link) {
+               e_dbg("Phy info is only valid if link is up\n");
+               ret_val = -E1000_ERR_CONFIG;
+               goto out;
+       }
+
+       ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
+       if (ret_val)
+               goto out;
+       phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE)
+                                  ? false : true;
+
+       if (phy->polarity_correction) {
+               ret_val = e1000e_check_polarity_ife(hw);
+               if (ret_val)
+                       goto out;
+       } else {
+               /* Polarity is forced */
+               phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
+                                     ? e1000_rev_polarity_reversed
+                                     : e1000_rev_polarity_normal;
+       }
+
+       ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
+       if (ret_val)
+               goto out;
+
+       phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? true : false;
+
+       /* The following parameters are undefined for 10/100 operation. */
+       phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
+       phy->local_rx = e1000_1000t_rx_status_undefined;
+       phy->remote_rx = e1000_1000t_rx_status_undefined;
+
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000e_set_lplu_state_pchlan - Set Low Power Link Up state
+ *  @hw: pointer to the HW structure
+ *  @active: true to enable LPLU, false to disable
+ *
+ *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
+ *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
+ *  the phy speed. This function will manually set the LPLU bit and restart
+ *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
+ *  since it configures the same bit.
+ **/
+static s32 e1000e_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
+{
+       s32 ret_val = E1000_SUCCESS;
+       u16 oem_reg;
+
+       ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
+       if (ret_val)
+               goto out;
+
+       if (active)
+               oem_reg |= HV_OEM_BITS_LPLU;
+       else
+               oem_reg &= ~HV_OEM_BITS_LPLU;
+
+       oem_reg |= HV_OEM_BITS_RESTART_AN;
+       ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
+
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000e_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
+ *  @hw: pointer to the HW structure
+ *  @active: true to enable LPLU, false to disable
+ *
+ *  Sets the LPLU D0 state according to the active flag.  When
+ *  activating LPLU this function also disables smart speed
+ *  and vice versa.  LPLU will not be activated unless the
+ *  device autonegotiation advertisement meets standards of
+ *  either 10 or 10/100 or 10/100/1000 at all duplexes.
+ *  This is a function pointer entry point only called by
+ *  PHY setup routines.
+ **/
+static s32 e1000e_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
+{
+       struct e1000_phy_info *phy = &hw->phy;
+       u32 phy_ctrl;
+       s32 ret_val = E1000_SUCCESS;
+       u16 data;
+
+       if (phy->type == e1000_phy_ife)
+               goto out;
+
+       phy_ctrl = er32(PHY_CTRL);
+
+       if (active) {
+               phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
+               ew32(PHY_CTRL, phy_ctrl);
+
+               if (phy->type != e1000_phy_igp_3)
+                       goto out;
+
+               /*
+                * Call gig speed drop workaround on LPLU before accessing
+                * any PHY registers
+                */
+               if (hw->mac.type == e1000_ich8lan)
+                       e1000e_gig_downshift_workaround_ich8lan(hw);
+
+               /* When LPLU is enabled, we should disable SmartSpeed */
+               ret_val = e1e_rphy(hw,
+                                           IGP01E1000_PHY_PORT_CONFIG,
+                                           &data);
+               data &= ~IGP01E1000_PSCFR_SMART_SPEED;
+               ret_val = e1e_wphy(hw,
+                                            IGP01E1000_PHY_PORT_CONFIG,
+                                            data);
+               if (ret_val)
+                       goto out;
+       } else {
+               phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
+               ew32(PHY_CTRL, phy_ctrl);
+
+               if (phy->type != e1000_phy_igp_3)
+                       goto out;
+
+               /*
+                * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
+                * during Dx states where the power conservation is most
+                * important.  During driver activity we should enable
+                * SmartSpeed, so performance is maintained.
+                */
+               if (phy->smart_speed == e1000_smart_speed_on) {
+                       ret_val = e1e_rphy(hw,
+                                                   IGP01E1000_PHY_PORT_CONFIG,
+                                                   &data);
+                       if (ret_val)
+                               goto out;
+
+                       data |= IGP01E1000_PSCFR_SMART_SPEED;
+                       ret_val = e1e_wphy(hw,
+                                                    IGP01E1000_PHY_PORT_CONFIG,
+                                                    data);
+                       if (ret_val)
+                               goto out;
+               } else if (phy->smart_speed == e1000_smart_speed_off) {
+                       ret_val = e1e_rphy(hw,
+                                                   IGP01E1000_PHY_PORT_CONFIG,
+                                                   &data);
+                       if (ret_val)
+                               goto out;
+
+                       data &= ~IGP01E1000_PSCFR_SMART_SPEED;
+                       ret_val = e1e_wphy(hw,
+                                                    IGP01E1000_PHY_PORT_CONFIG,
+                                                    data);
+                       if (ret_val)
+                               goto out;
+               }
+       }
+
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000e_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
+ *  @hw: pointer to the HW structure
+ *  @active: true to enable LPLU, false to disable
+ *
+ *  Sets the LPLU D3 state according to the active flag.  When
+ *  activating LPLU this function also disables smart speed
+ *  and vice versa.  LPLU will not be activated unless the
+ *  device autonegotiation advertisement meets standards of
+ *  either 10 or 10/100 or 10/100/1000 at all duplexes.
+ *  This is a function pointer entry point only called by
+ *  PHY setup routines.
+ **/
+static s32 e1000e_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
+{
+       struct e1000_phy_info *phy = &hw->phy;
+       u32 phy_ctrl;
+       s32 ret_val = E1000_SUCCESS;
+       u16 data;
+
+       phy_ctrl = er32(PHY_CTRL);
+
+       if (!active) {
+               phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
+               ew32(PHY_CTRL, phy_ctrl);
+
+               if (phy->type != e1000_phy_igp_3)
+                       goto out;
+
+               /*
+                * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
+                * during Dx states where the power conservation is most
+                * important.  During driver activity we should enable
+                * SmartSpeed, so performance is maintained.
+                */
+               if (phy->smart_speed == e1000_smart_speed_on) {
+                       ret_val = e1e_rphy(hw,
+                                                   IGP01E1000_PHY_PORT_CONFIG,
+                                                   &data);
+                       if (ret_val)
+                               goto out;
+
+                       data |= IGP01E1000_PSCFR_SMART_SPEED;
+                       ret_val = e1e_wphy(hw,
+                                                    IGP01E1000_PHY_PORT_CONFIG,
+                                                    data);
+                       if (ret_val)
+                               goto out;
+               } else if (phy->smart_speed == e1000_smart_speed_off) {
+                       ret_val = e1e_rphy(hw,
+                                                   IGP01E1000_PHY_PORT_CONFIG,
+                                                   &data);
+                       if (ret_val)
+                               goto out;
+
+                       data &= ~IGP01E1000_PSCFR_SMART_SPEED;
+                       ret_val = e1e_wphy(hw,
+                                                    IGP01E1000_PHY_PORT_CONFIG,
+                                                    data);
+                       if (ret_val)
+                               goto out;
+               }
+       } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
+                  (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
+                  (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
+               phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
+               ew32(PHY_CTRL, phy_ctrl);
+
+               if (phy->type != e1000_phy_igp_3)
+                       goto out;
+
+               /*
+                * Call gig speed drop workaround on LPLU before accessing
+                * any PHY registers
+                */
+               if (hw->mac.type == e1000_ich8lan)
+                       e1000e_gig_downshift_workaround_ich8lan(hw);
+
+               /* When LPLU is enabled, we should disable SmartSpeed */
+               ret_val = e1e_rphy(hw,
+                                           IGP01E1000_PHY_PORT_CONFIG,
+                                           &data);
+               if (ret_val)
+                       goto out;
+
+               data &= ~IGP01E1000_PSCFR_SMART_SPEED;
+               ret_val = e1e_wphy(hw,
+                                            IGP01E1000_PHY_PORT_CONFIG,
+                                            data);
+       }
+
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000e_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
+ *  @hw: pointer to the HW structure
+ *  @bank:  pointer to the variable that returns the active bank
+ *
+ *  Reads signature byte from the NVM using the flash access registers.
+ *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
+ **/
+static s32 e1000e_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
+{
+       u32 eecd;
+       struct e1000_nvm_info *nvm = &hw->nvm;
+       u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
+       u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
+       u8 sig_byte = 0;
+       s32 ret_val = E1000_SUCCESS;
+
+       switch (hw->mac.type) {
+       case e1000_ich8lan:
+       case e1000_ich9lan:
+               eecd = er32(EECD);
+               if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
+                   E1000_EECD_SEC1VAL_VALID_MASK) {
+                       if (eecd & E1000_EECD_SEC1VAL)
+                               *bank = 1;
+                       else
+                               *bank = 0;
+
+                       goto out;
+               }
+               e_dbg("Unable to determine valid NVM bank via EEC - "
+                        "reading flash signature\n");
+               /* fall-thru */
+       default:
+               /* set bank to 0 in case flash read fails */
+               *bank = 0;
+
+               /* Check bank 0 */
+               ret_val = e1000e_read_flash_byte_ich8lan(hw, act_offset,
+                                                       &sig_byte);
+               if (ret_val)
+                       goto out;
+               if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
+                   E1000_ICH_NVM_SIG_VALUE) {
+                       *bank = 0;
+                       goto out;
+               }
+
+               /* Check bank 1 */
+               ret_val = e1000e_read_flash_byte_ich8lan(hw, act_offset +
+                                                       bank1_offset,
+                                                       &sig_byte);
+               if (ret_val)
+                       goto out;
+               if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
+                   E1000_ICH_NVM_SIG_VALUE) {
+                       *bank = 1;
+                       goto out;
+               }
+
+               e_dbg("ERROR: No valid NVM bank present\n");
+               ret_val = -E1000_ERR_NVM;
+               break;
+       }
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000e_read_nvm_ich8lan - Read word(s) from the NVM
+ *  @hw: pointer to the HW structure
+ *  @offset: The offset (in bytes) of the word(s) to read.
+ *  @words: Size of data to read in words
+ *  @data: Pointer to the word(s) to read at offset.
+ *
+ *  Reads a word(s) from the NVM using the flash access registers.
+ **/
+static s32 e1000e_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
+                                  u16 *data)
+{
+       struct e1000_nvm_info *nvm = &hw->nvm;
+       struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
+       u32 act_offset;
+       s32 ret_val = E1000_SUCCESS;
+       u32 bank = 0;
+       u16 i, word;
+
+       if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
+           (words == 0)) {
+               e_dbg("nvm parameter(s) out of bounds\n");
+               ret_val = -E1000_ERR_NVM;
+               goto out;
+       }
+
+       nvm->ops.acquire(hw);
+
+       ret_val = e1000e_valid_nvm_bank_detect_ich8lan(hw, &bank);
+       if (ret_val != E1000_SUCCESS) {
+               e_dbg("Could not detect valid bank, assuming bank 0\n");
+               bank = 0;
+       }
+
+       act_offset = (bank) ? nvm->flash_bank_size : 0;
+       act_offset += offset;
+
+       ret_val = E1000_SUCCESS;
+       for (i = 0; i < words; i++) {
+               if ((dev_spec->shadow_ram) &&
+                   (dev_spec->shadow_ram[offset+i].modified)) {
+                       data[i] = dev_spec->shadow_ram[offset+i].value;
+               } else {
+                       ret_val = e1000e_read_flash_word_ich8lan(hw,
+                                                               act_offset + i,
+                                                               &word);
+                       if (ret_val)
+                               break;
+                       data[i] = word;
+               }
+       }
+
+       nvm->ops.release(hw);
+
+out:
+       if (ret_val)
+               e_dbg("NVM read error: %d\n", ret_val);
+
+       return ret_val;
+}
+
+/**
+ *  e1000e_flash_cycle_init_ich8lan - Initialize flash
+ *  @hw: pointer to the HW structure
+ *
+ *  This function does initial flash setup so that a new read/write/erase cycle
+ *  can be started.
+ **/
+static s32 e1000e_flash_cycle_init_ich8lan(struct e1000_hw *hw)
+{
+       union ich8_hws_flash_status hsfsts;
+       s32 ret_val = -E1000_ERR_NVM;
+       s32 i = 0;
+
+       hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
+
+       /* Check if the flash descriptor is valid */
+       if (hsfsts.hsf_status.fldesvalid == 0) {
+               e_dbg("Flash descriptor invalid.  "
+                        "SW Sequencing must be used.");
+               goto out;
+       }
+
+       /* Clear FCERR and DAEL in hw status by writing 1 */
+       hsfsts.hsf_status.flcerr = 1;
+       hsfsts.hsf_status.dael = 1;
+
+       ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
+
+       /*
+        * Either we should have a hardware SPI cycle in progress
+        * bit to check against, in order to start a new cycle or
+        * FDONE bit should be changed in the hardware so that it
+        * is 1 after hardware reset, which can then be used as an
+        * indication whether a cycle is in progress or has been
+        * completed.
+        */
+
+       if (hsfsts.hsf_status.flcinprog == 0) {
+               /*
+                * There is no cycle running at present,
+                * so we can start a cycle.
+                * Begin by setting Flash Cycle Done.
+                */
+               hsfsts.hsf_status.flcdone = 1;
+               ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
+               ret_val = E1000_SUCCESS;
+       } else {
+               /*
+                * Otherwise poll for sometime so the current
+                * cycle has a chance to end before giving up.
+                */
+               for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
+                       hsfsts.regval = er16flash(
+                                                             ICH_FLASH_HSFSTS);
+                       if (hsfsts.hsf_status.flcinprog == 0) {
+                               ret_val = E1000_SUCCESS;
+                               break;
+                       }
+                       udelay(1);
+               }
+               if (ret_val == E1000_SUCCESS) {
+                       /*
+                        * Successful in waiting for previous cycle to timeout,
+                        * now set the Flash Cycle Done.
+                        */
+                       hsfsts.hsf_status.flcdone = 1;
+                       ew16flash(ICH_FLASH_HSFSTS,
+                                               hsfsts.regval);
+               } else {
+                       e_dbg("Flash controller busy, cannot get access");
+               }
+       }
+
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000e_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
+ *  @hw: pointer to the HW structure
+ *  @timeout: maximum time to wait for completion
+ *
+ *  This function starts a flash cycle and waits for its completion.
+ **/
+static s32 e1000e_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
+{
+       union ich8_hws_flash_ctrl hsflctl;
+       union ich8_hws_flash_status hsfsts;
+       s32 ret_val = -E1000_ERR_NVM;
+       u32 i = 0;
+
+       /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
+       hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
+       hsflctl.hsf_ctrl.flcgo = 1;
+       ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
+
+       /* wait till FDONE bit is set to 1 */
+       do {
+               hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
+               if (hsfsts.hsf_status.flcdone == 1)
+                       break;
+               udelay(1);
+       } while (i++ < timeout);
+
+       if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
+               ret_val = E1000_SUCCESS;
+
+       return ret_val;
+}
+
+/**
+ *  e1000e_read_flash_word_ich8lan - Read word from flash
+ *  @hw: pointer to the HW structure
+ *  @offset: offset to data location
+ *  @data: pointer to the location for storing the data
+ *
+ *  Reads the flash word at offset into data.  Offset is converted
+ *  to bytes before read.
+ **/
+static s32 e1000e_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
+                                         u16 *data)
+{
+       s32 ret_val;
+
+       if (!data) {
+               ret_val = -E1000_ERR_NVM;
+               goto out;
+       }
+
+       /* Must convert offset into bytes. */
+       offset <<= 1;
+
+       ret_val = e1000e_read_flash_data_ich8lan(hw, offset, 2, data);
+
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000e_read_flash_byte_ich8lan - Read byte from flash
+ *  @hw: pointer to the HW structure
+ *  @offset: The offset of the byte to read.
+ *  @data: Pointer to a byte to store the value read.
+ *
+ *  Reads a single byte from the NVM using the flash access registers.
+ **/
+static s32 e1000e_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
+                                         u8 *data)
+{
+       s32 ret_val = E1000_SUCCESS;
+       u16 word = 0;
+
+       ret_val = e1000e_read_flash_data_ich8lan(hw, offset, 1, &word);
+       if (ret_val)
+               goto out;
+
+       *data = (u8)word;
+
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000e_read_flash_data_ich8lan - Read byte or word from NVM
+ *  @hw: pointer to the HW structure
+ *  @offset: The offset (in bytes) of the byte or word to read.
+ *  @size: Size of data to read, 1=byte 2=word
+ *  @data: Pointer to the word to store the value read.
+ *
+ *  Reads a byte or word from the NVM using the flash access registers.
+ **/
+static s32 e1000e_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
+                                         u8 size, u16 *data)
+{
+       union ich8_hws_flash_status hsfsts;
+       union ich8_hws_flash_ctrl hsflctl;
+       u32 flash_linear_addr;
+       u32 flash_data = 0;
+       s32 ret_val = -E1000_ERR_NVM;
+       u8 count = 0;
+
+       if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
+               goto out;
+       flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
+                           hw->nvm.flash_base_addr;
+
+       do {
+               udelay(1);
+               /* Steps */
+               ret_val = e1000e_flash_cycle_init_ich8lan(hw);
+               if (ret_val != E1000_SUCCESS)
+                       break;
+
+               hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
+               /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
+               hsflctl.hsf_ctrl.fldbcount = size - 1;
+               hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
+               ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
+
+               ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
+
+               ret_val = e1000e_flash_cycle_ich8lan(hw,
+                                               ICH_FLASH_READ_COMMAND_TIMEOUT);
+
+               /*
+                * Check if FCERR is set to 1, if set to 1, clear it
+                * and try the whole sequence a few more times, else
+                * read in (shift in) the Flash Data0, the order is
+                * least significant byte first msb to lsb
+                */
+               if (ret_val == E1000_SUCCESS) {
+                       flash_data = er32flash(ICH_FLASH_FDATA0);
+                       if (size == 1)
+                               *data = (u8)(flash_data & 0x000000FF);
+                       else if (size == 2)
+                               *data = (u16)(flash_data & 0x0000FFFF);
+                       break;
+               } else {
+                       /*
+                        * If we've gotten here, then things are probably
+                        * completely hosed, but if the error condition is
+                        * detected, it won't hurt to give it another try...
+                        * ICH_FLASH_CYCLE_REPEAT_COUNT times.
+                        */
+                       hsfsts.regval = er16flash(
+                                                             ICH_FLASH_HSFSTS);
+                       if (hsfsts.hsf_status.flcerr == 1) {
+                               /* Repeat for some time before giving up. */
+                               continue;
+                       } else if (hsfsts.hsf_status.flcdone == 0) {
+                               e_dbg("Timeout error - flash cycle "
+                                        "did not complete.");
+                               break;
+                       }
+               }
+       } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
+
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000e_write_nvm_ich8lan - Write word(s) to the NVM
+ *  @hw: pointer to the HW structure
+ *  @offset: The offset (in bytes) of the word(s) to write.
+ *  @words: Size of data to write in words
+ *  @data: Pointer to the word(s) to write at offset.
+ *
+ *  Writes a byte or word to the NVM using the flash access registers.
+ **/
+static s32 e1000e_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
+                                   u16 *data)
+{
+       struct e1000_nvm_info *nvm = &hw->nvm;
+       struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
+       s32 ret_val = E1000_SUCCESS;
+       u16 i;
+
+       if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
+           (words == 0)) {
+               e_dbg("nvm parameter(s) out of bounds\n");
+               ret_val = -E1000_ERR_NVM;
+               goto out;
+       }
+
+       nvm->ops.acquire(hw);
+
+       for (i = 0; i < words; i++) {
+               dev_spec->shadow_ram[offset+i].modified = true;
+               dev_spec->shadow_ram[offset+i].value = data[i];
+       }
+
+       nvm->ops.release(hw);
+
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000e_update_nvm_checksum_ich8lan - Update the checksum for NVM
+ *  @hw: pointer to the HW structure
+ *
+ *  The NVM checksum is updated by calling the generic update_nvm_checksum,
+ *  which writes the checksum to the shadow ram.  The changes in the shadow
+ *  ram are then committed to the EEPROM by processing each bank at a time
+ *  checking for the modified bit and writing only the pending changes.
+ *  After a successful commit, the shadow ram is cleared and is ready for
+ *  future writes.
+ **/
+static s32 e1000e_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
+{
+       struct e1000_nvm_info *nvm = &hw->nvm;
+       struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
+       u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
+       s32 ret_val;
+       u16 data;
+
+       ret_val = e1000e_update_nvm_checksum_generic(hw);
+       if (ret_val)
+               goto out;
+
+       if (nvm->type != e1000_nvm_flash_sw)
+               goto out;
+
+       nvm->ops.acquire(hw);
+
+       /*
+        * We're writing to the opposite bank so if we're on bank 1,
+        * write to bank 0 etc.  We also need to erase the segment that
+        * is going to be written
+        */
+       ret_val =  e1000e_valid_nvm_bank_detect_ich8lan(hw, &bank);
+       if (ret_val != E1000_SUCCESS) {
+               e_dbg("Could not detect valid bank, assuming bank 0\n");
+               bank = 0;
+       }
+
+       if (bank == 0) {
+               new_bank_offset = nvm->flash_bank_size;
+               old_bank_offset = 0;
+               ret_val = e1000e_erase_flash_bank_ich8lan(hw, 1);
+               if (ret_val) {
+                       nvm->ops.release(hw);
+                       goto out;
+               }
+       } else {
+               old_bank_offset = nvm->flash_bank_size;
+               new_bank_offset = 0;
+               ret_val = e1000e_erase_flash_bank_ich8lan(hw, 0);
+               if (ret_val) {
+                       nvm->ops.release(hw);
+                       goto out;
+               }
+       }
+
+       for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
+               /*
+                * Determine whether to write the value stored
+                * in the other NVM bank or a modified value stored
+                * in the shadow RAM
+                */
+               if (dev_spec->shadow_ram[i].modified) {
+                       data = dev_spec->shadow_ram[i].value;
+               } else {
+                       ret_val = e1000e_read_flash_word_ich8lan(hw, i +
+                                                               old_bank_offset,
+                                                               &data);
+                       if (ret_val)
+                               break;
+               }
+
+               /*
+                * If the word is 0x13, then make sure the signature bits
+                * (15:14) are 11b until the commit has completed.
+                * This will allow us to write 10b which indicates the
+                * signature is valid.  We want to do this after the write
+                * has completed so that we don't mark the segment valid
+                * while the write is still in progress
+                */
+               if (i == E1000_ICH_NVM_SIG_WORD)
+                       data |= E1000_ICH_NVM_SIG_MASK;
+
+               /* Convert offset to bytes. */
+               act_offset = (i + new_bank_offset) << 1;
+
+               udelay(100);
+               /* Write the bytes to the new bank. */
+               ret_val = e1000e_retry_write_flash_byte_ich8lan(hw,
+                                                              act_offset,
+                                                              (u8)data);
+               if (ret_val)
+                       break;
+
+               udelay(100);
+               ret_val = e1000e_retry_write_flash_byte_ich8lan(hw,
+                                                         act_offset + 1,
+                                                         (u8)(data >> 8));
+               if (ret_val)
+                       break;
+       }
+
+       /*
+        * Don't bother writing the segment valid bits if sector
+        * programming failed.
+        */
+       if (ret_val) {
+               e_dbg("Flash commit failed.\n");
+               nvm->ops.release(hw);
+               goto out;
+       }
+
+       /*
+        * Finally validate the new segment by setting bit 15:14
+        * to 10b in word 0x13 , this can be done without an
+        * erase as well since these bits are 11 to start with
+        * and we need to change bit 14 to 0b
+        */
+       act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
+       ret_val = e1000e_read_flash_word_ich8lan(hw, act_offset, &data);
+       if (ret_val) {
+               nvm->ops.release(hw);
+               goto out;
+       }
+
+       data &= 0xBFFF;
+       ret_val = e1000e_retry_write_flash_byte_ich8lan(hw,
+                                                      act_offset * 2 + 1,
+                                                      (u8)(data >> 8));
+       if (ret_val) {
+               nvm->ops.release(hw);
+               goto out;
+       }
+
+       /*
+        * And invalidate the previously valid segment by setting
+        * its signature word (0x13) high_byte to 0b. This can be
+        * done without an erase because flash erase sets all bits
+        * to 1's. We can write 1's to 0's without an erase
+        */
+       act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
+       ret_val = e1000e_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
+       if (ret_val) {
+               nvm->ops.release(hw);
+               goto out;
+       }
+
+       /* Great!  Everything worked, we can now clear the cached entries. */
+       for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
+               dev_spec->shadow_ram[i].modified = false;
+               dev_spec->shadow_ram[i].value = 0xFFFF;
+       }
+
+       nvm->ops.release(hw);
+
+       /*
+        * Reload the EEPROM, or else modifications will not appear
+        * until after the next adapter reset.
+        */
+       nvm->ops.reload(hw);
+       msleep(10);
+
+out:
+       if (ret_val)
+               e_dbg("NVM update error: %d\n", ret_val);
+
+       return ret_val;
+}
+
+/**
+ *  e1000e_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
+ *  @hw: pointer to the HW structure
+ *
+ *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
+ *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
+ *  calculated, in which case we need to calculate the checksum and set bit 6.
+ **/
+static s32 e1000e_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
+{
+       s32 ret_val = E1000_SUCCESS;
+       u16 data;
+
+       /*
+        * Read 0x19 and check bit 6.  If this bit is 0, the checksum
+        * needs to be fixed.  This bit is an indication that the NVM
+        * was prepared by OEM software and did not calculate the
+        * checksum...a likely scenario.
+        */
+       ret_val = e1000e_read_nvm(hw, 0x19, 1, &data);
+       if (ret_val)
+               goto out;
+
+       if ((data & 0x40) == 0) {
+               data |= 0x40;
+               ret_val = e1000e_write_nvm(hw, 0x19, 1, &data);
+               if (ret_val)
+                       goto out;
+               ret_val = e1000e_update_nvm_checksum(hw);
+               if (ret_val)
+                       goto out;
+       }
+
+       ret_val = e1000e_validate_nvm_checksum_generic(hw);
+
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000e_write_flash_data_ich8lan - Writes bytes to the NVM
+ *  @hw: pointer to the HW structure
+ *  @offset: The offset (in bytes) of the byte/word to read.
+ *  @size: Size of data to read, 1=byte 2=word
+ *  @data: The byte(s) to write to the NVM.
+ *
+ *  Writes one/two bytes to the NVM using the flash access registers.
+ **/
+static s32 e1000e_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
+                                          u8 size, u16 data)
+{
+       union ich8_hws_flash_status hsfsts;
+       union ich8_hws_flash_ctrl hsflctl;
+       u32 flash_linear_addr;
+       u32 flash_data = 0;
+       s32 ret_val = -E1000_ERR_NVM;
+       u8 count = 0;
+
+       if (size < 1 || size > 2 || data > size * 0xff ||
+           offset > ICH_FLASH_LINEAR_ADDR_MASK)
+               goto out;
+
+       flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
+                           hw->nvm.flash_base_addr;
+
+       do {
+               udelay(1);
+               /* Steps */
+               ret_val = e1000e_flash_cycle_init_ich8lan(hw);
+               if (ret_val != E1000_SUCCESS)
+                       break;
+
+               hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
+               /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
+               hsflctl.hsf_ctrl.fldbcount = size - 1;
+               hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
+               ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
+
+               ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
+
+               if (size == 1)
+                       flash_data = (u32)data & 0x00FF;
+               else
+                       flash_data = (u32)data;
+
+               ew32flash(ICH_FLASH_FDATA0, flash_data);
+
+               /*
+                * check if FCERR is set to 1 , if set to 1, clear it
+                * and try the whole sequence a few more times else done
+                */
+               ret_val = e1000e_flash_cycle_ich8lan(hw,
+                                              ICH_FLASH_WRITE_COMMAND_TIMEOUT);
+               if (ret_val == E1000_SUCCESS)
+                       break;
+
+               /*
+                * If we're here, then things are most likely
+                * completely hosed, but if the error condition
+                * is detected, it won't hurt to give it another
+                * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
+                */
+               hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
+               if (hsfsts.hsf_status.flcerr == 1) {
+                       /* Repeat for some time before giving up. */
+                       continue;
+               } else if (hsfsts.hsf_status.flcdone == 0) {
+                       e_dbg("Timeout error - flash cycle "
+                                "did not complete.");
+                       break;
+               }
+       } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
+
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000e_write_flash_byte_ich8lan - Write a single byte to NVM
+ *  @hw: pointer to the HW structure
+ *  @offset: The index of the byte to read.
+ *  @data: The byte to write to the NVM.
+ *
+ *  Writes a single byte to the NVM using the flash access registers.
+ **/
+static s32 e1000e_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
+                                          u8 data)
+{
+       u16 word = (u16)data;
+
+       return e1000e_write_flash_data_ich8lan(hw, offset, 1, word);
+}
+
+/**
+ *  e1000e_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
+ *  @hw: pointer to the HW structure
+ *  @offset: The offset of the byte to write.
+ *  @byte: The byte to write to the NVM.
+ *
+ *  Writes a single byte to the NVM using the flash access registers.
+ *  Goes through a retry algorithm before giving up.
+ **/
+static s32 e1000e_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
+                                                u32 offset, u8 byte)
+{
+       s32 ret_val;
+       u16 program_retries;
+
+       ret_val = e1000e_write_flash_byte_ich8lan(hw, offset, byte);
+       if (ret_val == E1000_SUCCESS)
+               goto out;
+
+       for (program_retries = 0; program_retries < 100; program_retries++) {
+               e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
+               udelay(100);
+               ret_val = e1000e_write_flash_byte_ich8lan(hw, offset, byte);
+               if (ret_val == E1000_SUCCESS)
+                       break;
+       }
+       if (program_retries == 100) {
+               ret_val = -E1000_ERR_NVM;
+               goto out;
+       }
+
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000e_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
+ *  @hw: pointer to the HW structure
+ *  @bank: 0 for first bank, 1 for second bank, etc.
+ *
+ *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
+ *  bank N is 4096 * N + flash_reg_addr.
+ **/
+static s32 e1000e_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
+{
+       struct e1000_nvm_info *nvm = &hw->nvm;
+       union ich8_hws_flash_status hsfsts;
+       union ich8_hws_flash_ctrl hsflctl;
+       u32 flash_linear_addr;
+       /* bank size is in 16bit words - adjust to bytes */
+       u32 flash_bank_size = nvm->flash_bank_size * 2;
+       s32 ret_val = E1000_SUCCESS;
+       s32 count = 0;
+       s32 j, iteration, sector_size;
+
+       hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
+
+       /*
+        * Determine HW Sector size: Read BERASE bits of hw flash status
+        * register
+        * 00: The Hw sector is 256 bytes, hence we need to erase 16
+        *     consecutive sectors.  The start index for the nth Hw sector
+        *     can be calculated as = bank * 4096 + n * 256
+        * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
+        *     The start index for the nth Hw sector can be calculated
+        *     as = bank * 4096
+&n