[jme] Add JMicron Ethernet driver
[people/cooldavid/gpxe.git] / src / drivers / net / jme.h
1 /*
2  * JMicron JMC2x0 series PCIe Ethernet gPXE Device Driver
3  *
4  * Copyright 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18  *
19  */
20 FILE_LICENCE ( GPL2_OR_LATER );
21
22 #ifndef __JME_H_INCLUDED__
23 #define __JME_H_INCLUDED__
24
25 #define PCI_VENDOR_ID_JMICRON           0x197b
26 #define PCI_DEVICE_ID_JMICRON_JMC250    0x0250
27 #define PCI_DEVICE_ID_JMICRON_JMC260    0x0260
28
29 /*
30  * Extra PCI Configuration space interface
31  */
32 #define PCI_DCSR_MRRS           0x59
33 #define PCI_DCSR_MRRS_MASK      0x70
34
35 enum pci_dcsr_mrrs_vals {
36         MRRS_128B       = 0x00,
37         MRRS_256B       = 0x10,
38         MRRS_512B       = 0x20,
39         MRRS_1024B      = 0x30,
40         MRRS_2048B      = 0x40,
41         MRRS_4096B      = 0x50,
42 };
43
44 /*
45  * TX/RX Descriptors
46  *
47  * TX/RX Ring DESC Count Must be multiple of 16 and <= 1024
48  */
49 #define RING_DESC_ALIGN         16      /* Descriptor alignment */
50 #define TX_DESC_SIZE            16
51
52 struct txdesc {
53         union {
54                 uint8_t         all[16];
55                 uint32_t        dw[4];
56                 struct {
57                         /* DW0 */
58                         uint16_t        vlan;
59                         uint8_t         rsv1;
60                         uint8_t         flags;
61
62                         /* DW1 */
63                         uint16_t        datalen;
64                         uint16_t        mss;
65
66                         /* DW2 */
67                         uint16_t        pktsize;
68                         uint16_t        rsv2;
69
70                         /* DW3 */
71                         uint32_t        bufaddr;
72                 } desc1;
73                 struct {
74                         /* DW0 */
75                         uint16_t        rsv1;
76                         uint8_t         rsv2;
77                         uint8_t         flags;
78
79                         /* DW1 */
80                         uint16_t        datalen;
81                         uint16_t        rsv3;
82
83                         /* DW2 */
84                         uint32_t        bufaddrh;
85
86                         /* DW3 */
87                         uint32_t        bufaddrl;
88                 } desc2;
89                 struct {
90                         /* DW0 */
91                         uint8_t         ehdrsz;
92                         uint8_t         rsv1;
93                         uint8_t         rsv2;
94                         uint8_t         flags;
95
96                         /* DW1 */
97                         uint16_t        trycnt;
98                         uint16_t        segcnt;
99
100                         /* DW2 */
101                         uint16_t        pktsz;
102                         uint16_t        rsv3;
103
104                         /* DW3 */
105                         uint32_t        bufaddrl;
106                 } descwb;
107         };
108 };
109
110 enum jme_txdesc_flags_bits {
111         TXFLAG_OWN      = 0x80,
112         TXFLAG_INT      = 0x40,
113         TXFLAG_64BIT    = 0x20,
114         TXFLAG_TCPCS    = 0x10,
115         TXFLAG_UDPCS    = 0x08,
116         TXFLAG_IPCS     = 0x04,
117         TXFLAG_LSEN     = 0x02,
118         TXFLAG_TAGON    = 0x01,
119 };
120
121 #define TXDESC_MSS_SHIFT        2
122 enum jme_txwbdesc_flags_bits {
123         TXWBFLAG_OWN    = 0x80,
124         TXWBFLAG_INT    = 0x40,
125         TXWBFLAG_TMOUT  = 0x20,
126         TXWBFLAG_TRYOUT = 0x10,
127         TXWBFLAG_COL    = 0x08,
128
129         TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
130                           TXWBFLAG_TRYOUT |
131                           TXWBFLAG_COL,
132 };
133
134 #define RX_DESC_SIZE            16
135 #define RX_BUF_DMA_ALIGN        8
136 #define RX_PREPAD_SIZE          10
137 #define ETH_CRC_LEN             2
138 #define RX_VLANHDR_LEN          2
139 #define RX_EXTRA_LEN            (ETH_HLEN + \
140                                 ETH_CRC_LEN + \
141                                 RX_VLANHDR_LEN + \
142                                 RX_BUF_DMA_ALIGN)
143 #define FIXED_MTU               1500
144 #define RX_ALLOC_LEN            (FIXED_MTU + RX_EXTRA_LEN)
145
146 struct rxdesc {
147         union {
148                 uint8_t         all[16];
149                 uint32_t        dw[4];
150                 struct {
151                         /* DW0 */
152                         uint16_t        rsv2;
153                         uint8_t         rsv1;
154                         uint8_t         flags;
155
156                         /* DW1 */
157                         uint16_t        datalen;
158                         uint16_t        wbcpl;
159
160                         /* DW2 */
161                         uint32_t        bufaddrh;
162
163                         /* DW3 */
164                         uint32_t        bufaddrl;
165                 } desc1;
166                 struct {
167                         /* DW0 */
168                         uint16_t        vlan;
169                         uint16_t        flags;
170
171                         /* DW1 */
172                         uint16_t        framesize;
173                         uint8_t         errstat;
174                         uint8_t         desccnt;
175
176                         /* DW2 */
177                         uint32_t        rsshash;
178
179                         /* DW3 */
180                         uint8_t         hashfun;
181                         uint8_t         hashtype;
182                         uint16_t        resrv;
183                 } descwb;
184         };
185 };
186
187 enum jme_rxdesc_flags_bits {
188         RXFLAG_OWN      = 0x80,
189         RXFLAG_INT      = 0x40,
190         RXFLAG_64BIT    = 0x20,
191 };
192
193 enum jme_rxwbdesc_flags_bits {
194         RXWBFLAG_OWN            = 0x8000,
195         RXWBFLAG_INT            = 0x4000,
196         RXWBFLAG_MF             = 0x2000,
197         RXWBFLAG_64BIT          = 0x2000,
198         RXWBFLAG_TCPON          = 0x1000,
199         RXWBFLAG_UDPON          = 0x0800,
200         RXWBFLAG_IPCS           = 0x0400,
201         RXWBFLAG_TCPCS          = 0x0200,
202         RXWBFLAG_UDPCS          = 0x0100,
203         RXWBFLAG_TAGON          = 0x0080,
204         RXWBFLAG_IPV4           = 0x0040,
205         RXWBFLAG_IPV6           = 0x0020,
206         RXWBFLAG_PAUSE          = 0x0010,
207         RXWBFLAG_MAGIC          = 0x0008,
208         RXWBFLAG_WAKEUP         = 0x0004,
209         RXWBFLAG_DEST           = 0x0003,
210         RXWBFLAG_DEST_UNI       = 0x0001,
211         RXWBFLAG_DEST_MUL       = 0x0002,
212         RXWBFLAG_DEST_BRO       = 0x0003,
213 };
214
215 enum jme_rxwbdesc_desccnt_mask {
216         RXWBDCNT_WBCPL  = 0x80,
217         RXWBDCNT_DCNT   = 0x7F,
218 };
219
220 enum jme_rxwbdesc_errstat_bits {
221         RXWBERR_LIMIT   = 0x80,
222         RXWBERR_MIIER   = 0x40,
223         RXWBERR_NIBON   = 0x20,
224         RXWBERR_COLON   = 0x10,
225         RXWBERR_ABORT   = 0x08,
226         RXWBERR_SHORT   = 0x04,
227         RXWBERR_OVERUN  = 0x02,
228         RXWBERR_CRCERR  = 0x01,
229         RXWBERR_ALLERR  = 0xFF,
230 };
231
232 /*
233  * The structure holding buffer information and ring descriptors all together.
234  */
235 struct jme_ring {
236         void *desc;             /* pointer to ring memory  */
237         unsigned long dma;      /* phys address for ring dma */
238
239         /* Buffer information corresponding to each descriptor */
240         struct io_buffer **bufinf;
241
242         int next_to_clean;
243         int next_to_fill;
244         int next_to_use;
245         int nr_free;
246 };
247
248 /*
249  * Jmac Adapter Private data
250  */
251 struct jme_adapter {
252         void                    *regs;
253         struct mii_if_info      mii_if;
254         struct pci_device       *pdev;
255         unsigned int            fpgaver;
256         unsigned int            chiprev;
257         uint32_t                reg_ghc;
258         uint32_t                reg_txcs;
259         uint32_t                reg_rxcs;
260         uint32_t                reg_rxmcs;
261         uint32_t                phylink;
262         struct jme_ring         rxring;
263         uint32_t                rx_ring_size;
264         uint32_t                rx_ring_mask;
265         struct jme_ring         txring;
266         uint32_t                tx_ring_size;
267         uint32_t                tx_ring_mask;
268 };
269
270 /*
271  * I/O Resters
272  */
273 enum jme_iomap_regs_value {
274         JME_REGS_SIZE   = 0x1000,
275 };
276
277 enum jme_iomap_offsets {
278         JME_MAC         = 0x0000,
279         JME_PHY         = 0x0400,
280         JME_MISC        = 0x0800,
281         JME_RSS         = 0x0C00,
282 };
283
284 enum jme_iomap_lens {
285         JME_MAC_LEN     = 0x80,
286         JME_PHY_LEN     = 0x58,
287         JME_MISC_LEN    = 0x98,
288         JME_RSS_LEN     = 0xFF,
289 };
290
291 enum jme_iomap_regs {
292         JME_TXCS        = JME_MAC | 0x00, /* Transmit Control and Status */
293         JME_TXDBA_LO    = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
294         JME_TXDBA_HI    = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
295         JME_TXQDC       = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
296         JME_TXNDA       = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
297         JME_TXMCS       = JME_MAC | 0x14, /* Transmit MAC Control Status */
298         JME_TXPFC       = JME_MAC | 0x18, /* Transmit Pause Frame Control */
299         JME_TXTRHD      = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
300
301         JME_RXCS        = JME_MAC | 0x20, /* Receive Control and Status */
302         JME_RXDBA_LO    = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
303         JME_RXDBA_HI    = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
304         JME_RXQDC       = JME_MAC | 0x2C, /* Receive Queue Desc Count */
305         JME_RXNDA       = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
306         JME_RXMCS       = JME_MAC | 0x34, /* Receive MAC Control Status */
307         JME_RXUMA_LO    = JME_MAC | 0x38, /* Receive Unicast MAC Address */
308         JME_RXUMA_HI    = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
309         JME_RXMCHT_LO   = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
310         JME_RXMCHT_HI   = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
311         JME_WFODP       = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
312         JME_WFOI        = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
313
314         JME_SMI         = JME_MAC | 0x50, /* Station Management Interface */
315         JME_GHC         = JME_MAC | 0x54, /* Global Host Control */
316         JME_PMCS        = JME_MAC | 0x60, /* Power Management Control/Stat */
317
318
319         JME_PHY_CS      = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
320         JME_PHY_LINK    = JME_PHY | 0x30, /* PHY Link Status Register */
321         JME_SMBCSR      = JME_PHY | 0x40, /* SMB Control and Status */
322         JME_SMBINTF     = JME_PHY | 0x44, /* SMB Interface */
323
324
325         JME_TMCSR       = JME_MISC | 0x00, /* Timer Control/Status Register */
326         JME_GPREG0      = JME_MISC | 0x08, /* General purpose REG-0 */
327         JME_GPREG1      = JME_MISC | 0x0C, /* General purpose REG-1 */
328         JME_IEVE        = JME_MISC | 0x20, /* Interrupt Event Status */
329         JME_IREQ        = JME_MISC | 0x24, /* Intr Req Status(For Debug) */
330         JME_IENS        = JME_MISC | 0x28, /* Intr Enable - Setting Port */
331         JME_IENC        = JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */
332         JME_PCCRX0      = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */
333         JME_PCCTX       = JME_MISC | 0x40, /* PCC Control for TX Queues */
334         JME_CHIPMODE    = JME_MISC | 0x44, /* Identify FPGA Version */
335         JME_SHBA_HI     = JME_MISC | 0x48, /* Shadow Register Base HI */
336         JME_SHBA_LO     = JME_MISC | 0x4C, /* Shadow Register Base LO */
337         JME_TIMER1      = JME_MISC | 0x70, /* Timer1 */
338         JME_TIMER2      = JME_MISC | 0x74, /* Timer2 */
339         JME_APMC        = JME_MISC | 0x7C, /* Aggressive Power Mode Control */
340         JME_PCCSRX0     = JME_MISC | 0x80, /* PCC Status of RX0 */
341 };
342
343 /*
344  * TX Control/Status Bits
345  */
346 enum jme_txcs_bits {
347         TXCS_QUEUE7S    = 0x00008000,
348         TXCS_QUEUE6S    = 0x00004000,
349         TXCS_QUEUE5S    = 0x00002000,
350         TXCS_QUEUE4S    = 0x00001000,
351         TXCS_QUEUE3S    = 0x00000800,
352         TXCS_QUEUE2S    = 0x00000400,
353         TXCS_QUEUE1S    = 0x00000200,
354         TXCS_QUEUE0S    = 0x00000100,
355         TXCS_FIFOTH     = 0x000000C0,
356         TXCS_DMASIZE    = 0x00000030,
357         TXCS_BURST      = 0x00000004,
358         TXCS_ENABLE     = 0x00000001,
359 };
360
361 enum jme_txcs_value {
362         TXCS_FIFOTH_16QW        = 0x000000C0,
363         TXCS_FIFOTH_12QW        = 0x00000080,
364         TXCS_FIFOTH_8QW         = 0x00000040,
365         TXCS_FIFOTH_4QW         = 0x00000000,
366
367         TXCS_DMASIZE_64B        = 0x00000000,
368         TXCS_DMASIZE_128B       = 0x00000010,
369         TXCS_DMASIZE_256B       = 0x00000020,
370         TXCS_DMASIZE_512B       = 0x00000030,
371
372         TXCS_SELECT_QUEUE0      = 0x00000000,
373         TXCS_SELECT_QUEUE1      = 0x00010000,
374         TXCS_SELECT_QUEUE2      = 0x00020000,
375         TXCS_SELECT_QUEUE3      = 0x00030000,
376         TXCS_SELECT_QUEUE4      = 0x00040000,
377         TXCS_SELECT_QUEUE5      = 0x00050000,
378         TXCS_SELECT_QUEUE6      = 0x00060000,
379         TXCS_SELECT_QUEUE7      = 0x00070000,
380
381         TXCS_DEFAULT            = TXCS_FIFOTH_4QW |
382                                   TXCS_BURST,
383 };
384
385 #define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
386
387 /*
388  * TX MAC Control/Status Bits
389  */
390 enum jme_txmcs_bit_masks {
391         TXMCS_IFG2              = 0xC0000000,
392         TXMCS_IFG1              = 0x30000000,
393         TXMCS_TTHOLD            = 0x00000300,
394         TXMCS_FBURST            = 0x00000080,
395         TXMCS_CARRIEREXT        = 0x00000040,
396         TXMCS_DEFER             = 0x00000020,
397         TXMCS_BACKOFF           = 0x00000010,
398         TXMCS_CARRIERSENSE      = 0x00000008,
399         TXMCS_COLLISION         = 0x00000004,
400         TXMCS_CRC               = 0x00000002,
401         TXMCS_PADDING           = 0x00000001,
402 };
403
404 enum jme_txmcs_values {
405         TXMCS_IFG2_6_4          = 0x00000000,
406         TXMCS_IFG2_8_5          = 0x40000000,
407         TXMCS_IFG2_10_6         = 0x80000000,
408         TXMCS_IFG2_12_7         = 0xC0000000,
409
410         TXMCS_IFG1_8_4          = 0x00000000,
411         TXMCS_IFG1_12_6         = 0x10000000,
412         TXMCS_IFG1_16_8         = 0x20000000,
413         TXMCS_IFG1_20_10        = 0x30000000,
414
415         TXMCS_TTHOLD_1_8        = 0x00000000,
416         TXMCS_TTHOLD_1_4        = 0x00000100,
417         TXMCS_TTHOLD_1_2        = 0x00000200,
418         TXMCS_TTHOLD_FULL       = 0x00000300,
419
420         TXMCS_DEFAULT           = TXMCS_IFG2_8_5 |
421                                   TXMCS_IFG1_16_8 |
422                                   TXMCS_TTHOLD_FULL |
423                                   TXMCS_DEFER |
424                                   TXMCS_CRC |
425                                   TXMCS_PADDING,
426 };
427
428 enum jme_txpfc_bits_masks {
429         TXPFC_VLAN_TAG          = 0xFFFF0000,
430         TXPFC_VLAN_EN           = 0x00008000,
431         TXPFC_PF_EN             = 0x00000001,
432 };
433
434 enum jme_txtrhd_bits_masks {
435         TXTRHD_TXPEN            = 0x80000000,
436         TXTRHD_TXP              = 0x7FFFFF00,
437         TXTRHD_TXREN            = 0x00000080,
438         TXTRHD_TXRL             = 0x0000007F,
439 };
440
441 enum jme_txtrhd_shifts {
442         TXTRHD_TXP_SHIFT        = 8,
443         TXTRHD_TXRL_SHIFT       = 0,
444 };
445
446 /*
447  * RX Control/Status Bits
448  */
449 enum jme_rxcs_bit_masks {
450         /* FIFO full threshold for transmitting Tx Pause Packet */
451         RXCS_FIFOTHTP   = 0x30000000,
452         /* FIFO threshold for processing next packet */
453         RXCS_FIFOTHNP   = 0x0C000000,
454         RXCS_DMAREQSZ   = 0x03000000, /* DMA Request Size */
455         RXCS_QUEUESEL   = 0x00030000, /* Queue selection */
456         RXCS_RETRYGAP   = 0x0000F000, /* RX Desc full retry gap */
457         RXCS_RETRYCNT   = 0x00000F00, /* RX Desc full retry counter */
458         RXCS_WAKEUP     = 0x00000040, /* Enable receive wakeup packet */
459         RXCS_MAGIC      = 0x00000020, /* Enable receive magic packet */
460         RXCS_SHORT      = 0x00000010, /* Enable receive short packet */
461         RXCS_ABORT      = 0x00000008, /* Enable receive errorr packet */
462         RXCS_QST        = 0x00000004, /* Receive queue start */
463         RXCS_SUSPEND    = 0x00000002,
464         RXCS_ENABLE     = 0x00000001,
465 };
466
467 enum jme_rxcs_values {
468         RXCS_FIFOTHTP_16T       = 0x00000000,
469         RXCS_FIFOTHTP_32T       = 0x10000000,
470         RXCS_FIFOTHTP_64T       = 0x20000000,
471         RXCS_FIFOTHTP_128T      = 0x30000000,
472
473         RXCS_FIFOTHNP_16QW      = 0x00000000,
474         RXCS_FIFOTHNP_32QW      = 0x04000000,
475         RXCS_FIFOTHNP_64QW      = 0x08000000,
476         RXCS_FIFOTHNP_128QW     = 0x0C000000,
477
478         RXCS_DMAREQSZ_16B       = 0x00000000,
479         RXCS_DMAREQSZ_32B       = 0x01000000,
480         RXCS_DMAREQSZ_64B       = 0x02000000,
481         RXCS_DMAREQSZ_128B      = 0x03000000,
482
483         RXCS_QUEUESEL_Q0        = 0x00000000,
484         RXCS_QUEUESEL_Q1        = 0x00010000,
485         RXCS_QUEUESEL_Q2        = 0x00020000,
486         RXCS_QUEUESEL_Q3        = 0x00030000,
487
488         RXCS_RETRYGAP_256ns     = 0x00000000,
489         RXCS_RETRYGAP_512ns     = 0x00001000,
490         RXCS_RETRYGAP_1024ns    = 0x00002000,
491         RXCS_RETRYGAP_2048ns    = 0x00003000,
492         RXCS_RETRYGAP_4096ns    = 0x00004000,
493         RXCS_RETRYGAP_8192ns    = 0x00005000,
494         RXCS_RETRYGAP_16384ns   = 0x00006000,
495         RXCS_RETRYGAP_32768ns   = 0x00007000,
496
497         RXCS_RETRYCNT_0         = 0x00000000,
498         RXCS_RETRYCNT_4         = 0x00000100,
499         RXCS_RETRYCNT_8         = 0x00000200,
500         RXCS_RETRYCNT_12        = 0x00000300,
501         RXCS_RETRYCNT_16        = 0x00000400,
502         RXCS_RETRYCNT_20        = 0x00000500,
503         RXCS_RETRYCNT_24        = 0x00000600,
504         RXCS_RETRYCNT_28        = 0x00000700,
505         RXCS_RETRYCNT_32        = 0x00000800,
506         RXCS_RETRYCNT_36        = 0x00000900,
507         RXCS_RETRYCNT_40        = 0x00000A00,
508         RXCS_RETRYCNT_44        = 0x00000B00,
509         RXCS_RETRYCNT_48        = 0x00000C00,
510         RXCS_RETRYCNT_52        = 0x00000D00,
511         RXCS_RETRYCNT_56        = 0x00000E00,
512         RXCS_RETRYCNT_60        = 0x00000F00,
513
514         RXCS_DEFAULT            = RXCS_FIFOTHTP_128T |
515                                   RXCS_FIFOTHNP_128QW |
516                                   RXCS_DMAREQSZ_128B |
517                                   RXCS_RETRYGAP_256ns |
518                                   RXCS_RETRYCNT_32,
519 };
520
521 #define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
522
523 /*
524  * RX MAC Control/Status Bits
525  */
526 enum jme_rxmcs_bits {
527         RXMCS_ALLFRAME          = 0x00000800,
528         RXMCS_BRDFRAME          = 0x00000400,
529         RXMCS_MULFRAME          = 0x00000200,
530         RXMCS_UNIFRAME          = 0x00000100,
531         RXMCS_ALLMULFRAME       = 0x00000080,
532         RXMCS_MULFILTERED       = 0x00000040,
533         RXMCS_RXCOLLDEC         = 0x00000020,
534         RXMCS_FLOWCTRL          = 0x00000008,
535         RXMCS_VTAGRM            = 0x00000004,
536         RXMCS_PREPAD            = 0x00000002,
537         RXMCS_CHECKSUM          = 0x00000001,
538
539         RXMCS_DEFAULT           = RXMCS_VTAGRM |
540                                   RXMCS_FLOWCTRL |
541                                   RXMCS_CHECKSUM,
542 };
543
544 /*
545  * Wakeup Frame setup interface registers
546  */
547 #define WAKEUP_FRAME_NR 8
548 #define WAKEUP_FRAME_MASK_DWNR  4
549
550 enum jme_wfoi_bit_masks {
551         WFOI_MASK_SEL           = 0x00000070,
552         WFOI_CRC_SEL            = 0x00000008,
553         WFOI_FRAME_SEL          = 0x00000007,
554 };
555
556 enum jme_wfoi_shifts {
557         WFOI_MASK_SHIFT         = 4,
558 };
559
560 /*
561  * SMI Related definitions
562  */
563 enum jme_smi_bit_mask {
564         SMI_DATA_MASK           = 0xFFFF0000,
565         SMI_REG_ADDR_MASK       = 0x0000F800,
566         SMI_PHY_ADDR_MASK       = 0x000007C0,
567         SMI_OP_WRITE            = 0x00000020,
568         /* Set to 1, after req done it'll be cleared to 0 */
569         SMI_OP_REQ              = 0x00000010,
570         SMI_OP_MDIO             = 0x00000008, /* Software assess In/Out */
571         SMI_OP_MDOE             = 0x00000004, /* Software Output Enable */
572         SMI_OP_MDC              = 0x00000002, /* Software CLK Control */
573         SMI_OP_MDEN             = 0x00000001, /* Software access Enable */
574 };
575
576 enum jme_smi_bit_shift {
577         SMI_DATA_SHIFT          = 16,
578         SMI_REG_ADDR_SHIFT      = 11,
579         SMI_PHY_ADDR_SHIFT      = 6,
580 };
581
582 static inline uint32_t smi_reg_addr(int x)
583 {
584         return (x << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK;
585 }
586
587 static inline uint32_t smi_phy_addr(int x)
588 {
589         return (x << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK;
590 }
591
592 #define JME_PHY_TIMEOUT 100 /* 100 msec */
593 #define JME_PHY_REG_NR 32
594
595 /*
596  * Global Host Control
597  */
598 enum jme_ghc_bit_mask {
599         GHC_SWRST               = 0x40000000,
600         GHC_DPX                 = 0x00000040,
601         GHC_SPEED               = 0x00000030,
602         GHC_LINK_POLL           = 0x00000001,
603 };
604
605 enum jme_ghc_speed_val {
606         GHC_SPEED_10M           = 0x00000010,
607         GHC_SPEED_100M          = 0x00000020,
608         GHC_SPEED_1000M         = 0x00000030,
609 };
610
611 enum jme_ghc_to_clk {
612         GHC_TO_CLK_OFF          = 0x00000000,
613         GHC_TO_CLK_GPHY         = 0x00400000,
614         GHC_TO_CLK_PCIE         = 0x00800000,
615         GHC_TO_CLK_INVALID      = 0x00C00000,
616 };
617
618 enum jme_ghc_txmac_clk {
619         GHC_TXMAC_CLK_OFF       = 0x00000000,
620         GHC_TXMAC_CLK_GPHY      = 0x00100000,
621         GHC_TXMAC_CLK_PCIE      = 0x00200000,
622         GHC_TXMAC_CLK_INVALID   = 0x00300000,
623 };
624
625 /*
626  * Power management control and status register
627  */
628 enum jme_pmcs_bit_masks {
629         PMCS_WF7DET     = 0x80000000,
630         PMCS_WF6DET     = 0x40000000,
631         PMCS_WF5DET     = 0x20000000,
632         PMCS_WF4DET     = 0x10000000,
633         PMCS_WF3DET     = 0x08000000,
634         PMCS_WF2DET     = 0x04000000,
635         PMCS_WF1DET     = 0x02000000,
636         PMCS_WF0DET     = 0x01000000,
637         PMCS_LFDET      = 0x00040000,
638         PMCS_LRDET      = 0x00020000,
639         PMCS_MFDET      = 0x00010000,
640         PMCS_WF7EN      = 0x00008000,
641         PMCS_WF6EN      = 0x00004000,
642         PMCS_WF5EN      = 0x00002000,
643         PMCS_WF4EN      = 0x00001000,
644         PMCS_WF3EN      = 0x00000800,
645         PMCS_WF2EN      = 0x00000400,
646         PMCS_WF1EN      = 0x00000200,
647         PMCS_WF0EN      = 0x00000100,
648         PMCS_LFEN       = 0x00000004,
649         PMCS_LREN       = 0x00000002,
650         PMCS_MFEN       = 0x00000001,
651 };
652
653 /*
654  * Giga PHY Status Registers
655  */
656 enum jme_phy_link_bit_mask {
657         PHY_LINK_SPEED_MASK             = 0x0000C000,
658         PHY_LINK_DUPLEX                 = 0x00002000,
659         PHY_LINK_SPEEDDPU_RESOLVED      = 0x00000800,
660         PHY_LINK_UP                     = 0x00000400,
661         PHY_LINK_AUTONEG_COMPLETE       = 0x00000200,
662         PHY_LINK_MDI_STAT               = 0x00000040,
663 };
664
665 enum jme_phy_link_speed_val {
666         PHY_LINK_SPEED_10M              = 0x00000000,
667         PHY_LINK_SPEED_100M             = 0x00004000,
668         PHY_LINK_SPEED_1000M            = 0x00008000,
669 };
670
671 #define JME_SPDRSV_TIMEOUT      500     /* 500 us */
672
673 /*
674  * SMB Control and Status
675  */
676 enum jme_smbcsr_bit_mask {
677         SMBCSR_CNACK    = 0x00020000,
678         SMBCSR_RELOAD   = 0x00010000,
679         SMBCSR_EEPROMD  = 0x00000020,
680         SMBCSR_INITDONE = 0x00000010,
681         SMBCSR_BUSY     = 0x0000000F,
682 };
683
684 enum jme_smbintf_bit_mask {
685         SMBINTF_HWDATR  = 0xFF000000,
686         SMBINTF_HWDATW  = 0x00FF0000,
687         SMBINTF_HWADDR  = 0x0000FF00,
688         SMBINTF_HWRWN   = 0x00000020,
689         SMBINTF_HWCMD   = 0x00000010,
690         SMBINTF_FASTM   = 0x00000008,
691         SMBINTF_GPIOSCL = 0x00000004,
692         SMBINTF_GPIOSDA = 0x00000002,
693         SMBINTF_GPIOEN  = 0x00000001,
694 };
695
696 enum jme_smbintf_vals {
697         SMBINTF_HWRWN_READ      = 0x00000020,
698         SMBINTF_HWRWN_WRITE     = 0x00000000,
699 };
700
701 enum jme_smbintf_shifts {
702         SMBINTF_HWDATR_SHIFT    = 24,
703         SMBINTF_HWDATW_SHIFT    = 16,
704         SMBINTF_HWADDR_SHIFT    = 8,
705 };
706
707 #define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */
708 #define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */
709 #define JME_SMB_LEN 256
710 #define JME_EEPROM_MAGIC 0x250
711
712 /*
713  * Timer Control/Status Register
714  */
715 enum jme_tmcsr_bit_masks {
716         TMCSR_SWIT      = 0x80000000,
717         TMCSR_EN        = 0x01000000,
718         TMCSR_CNT       = 0x00FFFFFF,
719 };
720
721 /*
722  * General Purpose REG-0
723  */
724 enum jme_gpreg0_masks {
725         GPREG0_DISSH            = 0xFF000000,
726         GPREG0_PCIRLMT          = 0x00300000,
727         GPREG0_PCCNOMUTCLR      = 0x00040000,
728         GPREG0_LNKINTPOLL       = 0x00001000,
729         GPREG0_PCCTMR           = 0x00000300,
730         GPREG0_PHYADDR          = 0x0000001F,
731 };
732
733 enum jme_gpreg0_vals {
734         GPREG0_DISSH_DW7        = 0x80000000,
735         GPREG0_DISSH_DW6        = 0x40000000,
736         GPREG0_DISSH_DW5        = 0x20000000,
737         GPREG0_DISSH_DW4        = 0x10000000,
738         GPREG0_DISSH_DW3        = 0x08000000,
739         GPREG0_DISSH_DW2        = 0x04000000,
740         GPREG0_DISSH_DW1        = 0x02000000,
741         GPREG0_DISSH_DW0        = 0x01000000,
742         GPREG0_DISSH_ALL        = 0xFF000000,
743
744         GPREG0_PCIRLMT_8        = 0x00000000,
745         GPREG0_PCIRLMT_6        = 0x00100000,
746         GPREG0_PCIRLMT_5        = 0x00200000,
747         GPREG0_PCIRLMT_4        = 0x00300000,
748
749         GPREG0_PCCTMR_16ns      = 0x00000000,
750         GPREG0_PCCTMR_256ns     = 0x00000100,
751         GPREG0_PCCTMR_1us       = 0x00000200,
752         GPREG0_PCCTMR_1ms       = 0x00000300,
753
754         GPREG0_PHYADDR_1        = 0x00000001,
755
756         GPREG0_DEFAULT          = GPREG0_DISSH_ALL |
757                                   GPREG0_PCIRLMT_4 |
758                                   GPREG0_PCCTMR_1us |
759                                   GPREG0_PHYADDR_1,
760 };
761
762 /*
763  * General Purpose REG-1
764  * Note: All theses bits defined here are for
765  *       Chip mode revision 0x11 only
766  */
767 enum jme_gpreg1_masks {
768         GPREG1_INTRDELAYUNIT    = 0x00000018,
769         GPREG1_INTRDELAYENABLE  = 0x00000007,
770 };
771
772 enum jme_gpreg1_vals {
773         GPREG1_RSSPATCH         = 0x00000040,
774         GPREG1_HALFMODEPATCH    = 0x00000020,
775
776         GPREG1_INTDLYUNIT_16NS  = 0x00000000,
777         GPREG1_INTDLYUNIT_256NS = 0x00000008,
778         GPREG1_INTDLYUNIT_1US   = 0x00000010,
779         GPREG1_INTDLYUNIT_16US  = 0x00000018,
780
781         GPREG1_INTDLYEN_1U      = 0x00000001,
782         GPREG1_INTDLYEN_2U      = 0x00000002,
783         GPREG1_INTDLYEN_3U      = 0x00000003,
784         GPREG1_INTDLYEN_4U      = 0x00000004,
785         GPREG1_INTDLYEN_5U      = 0x00000005,
786         GPREG1_INTDLYEN_6U      = 0x00000006,
787         GPREG1_INTDLYEN_7U      = 0x00000007,
788
789         GPREG1_DEFAULT          = 0x00000000,
790 };
791
792 /*
793  * Interrupt Status Bits
794  */
795 enum jme_interrupt_bits {
796         INTR_SWINTR     = 0x80000000,
797         INTR_TMINTR     = 0x40000000,
798         INTR_LINKCH     = 0x20000000,
799         INTR_PAUSERCV   = 0x10000000,
800         INTR_MAGICRCV   = 0x08000000,
801         INTR_WAKERCV    = 0x04000000,
802         INTR_PCCRX0TO   = 0x02000000,
803         INTR_PCCRX1TO   = 0x01000000,
804         INTR_PCCRX2TO   = 0x00800000,
805         INTR_PCCRX3TO   = 0x00400000,
806         INTR_PCCTXTO    = 0x00200000,
807         INTR_PCCRX0     = 0x00100000,
808         INTR_PCCRX1     = 0x00080000,
809         INTR_PCCRX2     = 0x00040000,
810         INTR_PCCRX3     = 0x00020000,
811         INTR_PCCTX      = 0x00010000,
812         INTR_RX3EMP     = 0x00008000,
813         INTR_RX2EMP     = 0x00004000,
814         INTR_RX1EMP     = 0x00002000,
815         INTR_RX0EMP     = 0x00001000,
816         INTR_RX3        = 0x00000800,
817         INTR_RX2        = 0x00000400,
818         INTR_RX1        = 0x00000200,
819         INTR_RX0        = 0x00000100,
820         INTR_TX7        = 0x00000080,
821         INTR_TX6        = 0x00000040,
822         INTR_TX5        = 0x00000020,
823         INTR_TX4        = 0x00000010,
824         INTR_TX3        = 0x00000008,
825         INTR_TX2        = 0x00000004,
826         INTR_TX1        = 0x00000002,
827         INTR_TX0        = 0x00000001,
828 };
829
830 static const uint32_t INTR_ENABLE = INTR_LINKCH |
831                                     INTR_RX0EMP |
832                                     INTR_RX0 |
833                                     INTR_TX0;
834
835 /*
836  * PCC Control Registers
837  */
838 enum jme_pccrx_masks {
839         PCCRXTO_MASK    = 0xFFFF0000,
840         PCCRX_MASK      = 0x0000FF00,
841 };
842
843 enum jme_pcctx_masks {
844         PCCTXTO_MASK    = 0xFFFF0000,
845         PCCTX_MASK      = 0x0000FF00,
846         PCCTX_QS_MASK   = 0x000000FF,
847 };
848
849 enum jme_pccrx_shifts {
850         PCCRXTO_SHIFT   = 16,
851         PCCRX_SHIFT     = 8,
852 };
853
854 enum jme_pcctx_shifts {
855         PCCTXTO_SHIFT   = 16,
856         PCCTX_SHIFT     = 8,
857 };
858
859 enum jme_pcctx_bits {
860         PCCTXQ0_EN      = 0x00000001,
861         PCCTXQ1_EN      = 0x00000002,
862         PCCTXQ2_EN      = 0x00000004,
863         PCCTXQ3_EN      = 0x00000008,
864         PCCTXQ4_EN      = 0x00000010,
865         PCCTXQ5_EN      = 0x00000020,
866         PCCTXQ6_EN      = 0x00000040,
867         PCCTXQ7_EN      = 0x00000080,
868 };
869
870 /*
871  * Chip Mode Register
872  */
873 enum jme_chipmode_bit_masks {
874         CM_FPGAVER_MASK         = 0xFFFF0000,
875         CM_CHIPREV_MASK         = 0x0000FF00,
876         CM_CHIPMODE_MASK        = 0x0000000F,
877 };
878
879 enum jme_chipmode_shifts {
880         CM_FPGAVER_SHIFT        = 16,
881         CM_CHIPREV_SHIFT        = 8,
882 };
883
884 /*
885  * Workaround
886  */
887 static inline int is_buggy250(unsigned short device, unsigned int chiprev)
888 {
889         return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11;
890 }
891
892 /*
893  * Read/Write I/O Registers
894  */
895 static inline uint32_t jread32(struct jme_adapter *jme, uint32_t reg)
896 {
897         return readl(jme->regs + reg);
898 }
899
900 static inline void jwrite32(struct jme_adapter *jme, uint32_t reg, uint32_t val)
901 {
902         writel(val, jme->regs + reg);
903 }
904
905 static void jwrite32f(struct jme_adapter *jme, uint32_t reg, uint32_t val)
906 {
907         /*
908          * Read after write should cause flush
909          */
910         writel(val, jme->regs + reg);
911         readl(jme->regs + reg);
912 }
913
914 #endif