ab9a30f881558e202f03d455be0c9fde1b584d56
[people/balajirrao/gpxe.git] / src / drivers / net / r8169.c
1 /**************************************************************************
2 *    r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit
3 *    Written 2003 by Timothy Legge <tlegge@rogers.com>
4 *
5 *    This program is free software; you can redistribute it and/or modify
6 *    it under the terms of the GNU General Public License as published by
7 *    the Free Software Foundation; either version 2 of the License, or
8 *    (at your option) any later version.
9 *
10 *    This program is distributed in the hope that it will be useful,
11 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
12 *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13 *    GNU General Public License for more details.
14 *
15 *    You should have received a copy of the GNU General Public License
16 *    along with this program; if not, write to the Free Software
17 *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 *
19 *    Portions of this code based on:
20 *       r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver 
21 *               for Linux kernel 2.4.x.
22 *
23 *    Written 2002 ShuChen <shuchen@realtek.com.tw>
24 *         See Linux Driver for full information
25 *       
26 *    Linux Driver Versions: 
27 *       1.27a, 10.02.2002
28 *       RTL8169_VERSION "2.2"   <2004/08/09>
29
30 *    Thanks to:
31 *       Jean Chen of RealTek Semiconductor Corp. for
32 *       providing the evaluation NIC used to develop 
33 *       this driver.  RealTek's support for Etherboot 
34 *       is appreciated.
35 *       
36 *    REVISION HISTORY:
37 *    ================
38 *
39 *    v1.0       11-26-2003      timlegge        Initial port of Linux driver
40 *    v1.5       01-17-2004      timlegge        Initial driver output cleanup
41 *    v1.6       03-27-2004      timlegge        Additional Cleanup
42 *    v1.7       11-22-2005      timlegge        Update to RealTek Driver Version 2.2
43 *    
44 *    Indent Options: indent -kr -i8
45 ***************************************************************************/
46
47 #include "etherboot.h"
48 #include "nic.h"
49 #include <gpxe/pci.h>
50 #include <gpxe/ethernet.h>
51 #include <gpxe/malloc.h>
52
53 #define drv_version "v1.6"
54 #define drv_date "03-27-2004"
55
56 #define HZ 1000
57
58 static u32 ioaddr;
59
60 /* Condensed operations for readability. */
61 #define virt_to_le32desc(addr)  cpu_to_le32(virt_to_bus(addr))
62 #define le32desc_to_virt(addr)  bus_to_virt(le32_to_cpu(addr))
63
64 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
65
66 #undef RTL8169_DEBUG
67 #undef RTL8169_JUMBO_FRAME_SUPPORT
68 #undef RTL8169_HW_FLOW_CONTROL_SUPPORT
69
70
71 #undef RTL8169_IOCTL_SUPPORT
72 #undef RTL8169_DYNAMIC_CONTROL
73 #define RTL8169_USE_IO
74
75
76 /* media options 
77         _10_Half = 0x01,
78         _10_Full = 0x02,
79         _100_Half = 0x04,
80         _100_Full = 0x08,
81         _1000_Full = 0x10,
82 */
83 static int media = -1;
84
85 #if 0
86 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
87 static int max_interrupt_work = 20;
88 #endif
89
90 #if 0
91 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
92    The RTL chips use a 64 element hash table based on the Ethernet CRC.  */
93 static int multicast_filter_limit = 32;
94 #endif
95
96 /* MAC address length*/
97 #define MAC_ADDR_LEN    6
98
99 /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/
100 #define MAX_ETH_FRAME_SIZE      1536
101
102 #define TX_FIFO_THRESH 256      /* In bytes */
103
104 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer.  */
105 #define RX_DMA_BURST    7       /* Maximum PCI burst, '6' is 1024 */
106 #define TX_DMA_BURST    7       /* Maximum PCI burst, '6' is 1024 */
107 #define ETTh                0x3F        /* 0x3F means NO threshold */
108
109 #define EarlyTxThld     0x3F    /* 0x3F means NO early transmit */
110 #define RxPacketMaxSize 0x0800  /* Maximum size supported is 16K-1 */
111 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
112
113 #define NUM_TX_DESC     1       /* Number of Tx descriptor registers */
114 #define NUM_RX_DESC     4       /* Number of Rx descriptor registers */
115 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
116
117 #define RTL_MIN_IO_SIZE 0x80
118 #define TX_TIMEOUT  (6*HZ)
119
120 #define RTL8169_TIMER_EXPIRE_TIME 100   //100
121
122 #define ETH_HDR_LEN         14
123 #define DEFAULT_MTU         1500
124 #define DEFAULT_RX_BUF_LEN  1536
125
126
127 #ifdef RTL8169_JUMBO_FRAME_SUPPORT
128 #define MAX_JUMBO_FRAME_MTU    ( 10000 )
129 #define MAX_RX_SKBDATA_SIZE    ( MAX_JUMBO_FRAME_MTU + ETH_HDR_LEN )
130 #else
131 #define MAX_RX_SKBDATA_SIZE 1600
132 #endif                          //end #ifdef RTL8169_JUMBO_FRAME_SUPPORT
133
134 #ifdef RTL8169_USE_IO
135 #define RTL_W8(reg, val8)   outb ((val8), ioaddr + (reg))
136 #define RTL_W16(reg, val16) outw ((val16), ioaddr + (reg))
137 #define RTL_W32(reg, val32) outl ((val32), ioaddr + (reg))
138 #define RTL_R8(reg)         inb (ioaddr + (reg))
139 #define RTL_R16(reg)        inw (ioaddr + (reg))
140 #define RTL_R32(reg)        ((unsigned long) inl (ioaddr + (reg)))
141 #else
142 /* write/read MMIO register */
143 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
144 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
145 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
146 #define RTL_R8(reg)             readb (ioaddr + (reg))
147 #define RTL_R16(reg)            readw (ioaddr + (reg))
148 #define RTL_R32(reg)            ((unsigned long) readl (ioaddr + (reg)))
149 #endif
150
151 #define MCFG_METHOD_1           0x01
152 #define MCFG_METHOD_2           0x02
153 #define MCFG_METHOD_3           0x03
154 #define MCFG_METHOD_4           0x04
155
156 #define PCFG_METHOD_1           0x01    //PHY Reg 0x03 bit0-3 == 0x0000
157 #define PCFG_METHOD_2           0x02    //PHY Reg 0x03 bit0-3 == 0x0001
158 #define PCFG_METHOD_3           0x03    //PHY Reg 0x03 bit0-3 == 0x0002
159
160 static struct {
161         const char *name;
162         u8 mcfg;                /* depend on RTL8169 docs */
163         u32 RxConfigMask;       /* should clear the bits supported by this chip */
164 } rtl_chip_info[] = {
165         {
166         "RTL-8169", MCFG_METHOD_1, 0xff7e1880,}, {
167         "RTL8169s/8110s", MCFG_METHOD_2, 0xff7e1880}, {
168 "RTL8169s/8110s", MCFG_METHOD_3, 0xff7e1880},};
169
170 enum RTL8169_registers {
171         MAC0 = 0x0,             /* Ethernet hardware address. */
172         MAR0 = 0x8,             /* Multicast filter. */
173         TxDescStartAddr = 0x20,
174         TxHDescStartAddr = 0x28,
175         FLASH = 0x30,
176         ERSR = 0x36,
177         ChipCmd = 0x37,
178         TxPoll = 0x38,
179         IntrMask = 0x3C,
180         IntrStatus = 0x3E,
181         TxConfig = 0x40,
182         RxConfig = 0x44,
183         RxMissed = 0x4C,
184         Cfg9346 = 0x50,
185         Config0 = 0x51,
186         Config1 = 0x52,
187         Config2 = 0x53,
188         Config3 = 0x54,
189         Config4 = 0x55,
190         Config5 = 0x56,
191         MultiIntr = 0x5C,
192         PHYAR = 0x60,
193         TBICSR = 0x64,
194         TBI_ANAR = 0x68,
195         TBI_LPAR = 0x6A,
196         PHYstatus = 0x6C,
197         RxMaxSize = 0xDA,
198         CPlusCmd = 0xE0,
199         RxDescStartAddr = 0xE4,
200         ETThReg = 0xEC,
201         FuncEvent = 0xF0,
202         FuncEventMask = 0xF4,
203         FuncPresetState = 0xF8,
204         FuncForceEvent = 0xFC,
205 };
206
207 enum RTL8169_register_content {
208         /*InterruptStatusBits */
209         SYSErr = 0x8000,
210         PCSTimeout = 0x4000,
211         SWInt = 0x0100,
212         TxDescUnavail = 0x80,
213         RxFIFOOver = 0x40,
214         LinkChg = 0x20,
215         RxOverflow = 0x10,
216         TxErr = 0x08,
217         TxOK = 0x04,
218         RxErr = 0x02,
219         RxOK = 0x01,
220
221         /*RxStatusDesc */
222         RxRES = 0x00200000,
223         RxCRC = 0x00080000,
224         RxRUNT = 0x00100000,
225         RxRWT = 0x00400000,
226
227         /*ChipCmdBits */
228         CmdReset = 0x10,
229         CmdRxEnb = 0x08,
230         CmdTxEnb = 0x04,
231         RxBufEmpty = 0x01,
232
233         /*Cfg9346Bits */
234         Cfg9346_Lock = 0x00,
235         Cfg9346_Unlock = 0xC0,
236
237         /*rx_mode_bits */
238         AcceptErr = 0x20,
239         AcceptRunt = 0x10,
240         AcceptBroadcast = 0x08,
241         AcceptMulticast = 0x04,
242         AcceptMyPhys = 0x02,
243         AcceptAllPhys = 0x01,
244
245         /*RxConfigBits */
246         RxCfgFIFOShift = 13,
247         RxCfgDMAShift = 8,
248
249         /*TxConfigBits */
250         TxInterFrameGapShift = 24,
251         TxDMAShift = 8,         /* DMA burst value (0-7) is shift this many bits */
252
253         /*rtl8169_PHYstatus */
254         TBI_Enable = 0x80,
255         TxFlowCtrl = 0x40,
256         RxFlowCtrl = 0x20,
257         _1000bpsF = 0x10,
258         _100bps = 0x08,
259         _10bps = 0x04,
260         LinkStatus = 0x02,
261         FullDup = 0x01,
262
263         /*GIGABIT_PHY_registers */
264         PHY_CTRL_REG = 0,
265         PHY_STAT_REG = 1,
266         PHY_AUTO_NEGO_REG = 4,
267         PHY_1000_CTRL_REG = 9,
268
269         /*GIGABIT_PHY_REG_BIT */
270         PHY_Restart_Auto_Nego = 0x0200,
271         PHY_Enable_Auto_Nego = 0x1000,
272
273         /* PHY_STAT_REG = 1; */
274         PHY_Auto_Neco_Comp = 0x0020,
275
276         /* PHY_AUTO_NEGO_REG = 4; */
277         PHY_Cap_10_Half = 0x0020,
278         PHY_Cap_10_Full = 0x0040,
279         PHY_Cap_100_Half = 0x0080,
280         PHY_Cap_100_Full = 0x0100,
281
282         /* PHY_1000_CTRL_REG = 9; */
283         PHY_Cap_1000_Full = 0x0200,
284         PHY_Cap_1000_Half = 0x0100,
285
286         PHY_Cap_PAUSE = 0x0400,
287         PHY_Cap_ASYM_PAUSE = 0x0800,
288
289         PHY_Cap_Null = 0x0,
290
291         /*_MediaType*/
292         _10_Half = 0x01,
293         _10_Full = 0x02,
294         _100_Half = 0x04,
295         _100_Full = 0x08,
296         _1000_Full = 0x10,
297
298         /*_TBICSRBit*/
299         TBILinkOK = 0x02000000,
300 };
301
302 enum _DescStatusBit {
303         OWNbit = 0x80000000,
304         EORbit = 0x40000000,
305         FSbit = 0x20000000,
306         LSbit = 0x10000000,
307 };
308
309 struct TxDesc {
310         u32 status;
311         u32 vlan_tag;
312         u32 buf_addr;
313         u32 buf_Haddr;
314 };
315
316 struct RxDesc {
317         u32 status;
318         u32 vlan_tag;
319         u32 buf_addr;
320         u32 buf_Haddr;
321 };
322
323 /* The descriptors for this card are required to be aligned on 256
324  * byte boundaries.  As the align attribute does not do more than 16
325  * bytes of alignment it requires some extra steps.  Add 256 to the
326  * size of the array and the init_ring adjusts the alignment.
327  *
328  * UPDATE: This is no longer true; we can request arbitrary alignment.
329  */
330
331 /* Define the TX and RX Descriptors and Buffers */
332 #define __align_256 __attribute__ (( aligned ( 256 ) ))
333 struct {
334         struct TxDesc tx_ring[NUM_TX_DESC] __align_256;
335         unsigned char txb[NUM_TX_DESC * RX_BUF_SIZE];
336         struct RxDesc rx_ring[NUM_RX_DESC] __align_256;
337         unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE];
338 } *r8169_bufs;
339 #define tx_ring r8169_bufs->tx_ring
340 #define rx_ring r8169_bufs->rx_ring
341 #define txb r8169_bufs->txb
342 #define rxb r8169_bufs->rxb
343
344 static struct rtl8169_private {
345         void *mmio_addr;        /* memory map physical address */
346         int chipset;
347         int pcfg;
348         int mcfg;
349         unsigned long cur_rx;   /* Index into the Rx descriptor buffer of next Rx pkt. */
350         unsigned long cur_tx;   /* Index into the Tx descriptor buffer of next Rx pkt. */
351         struct TxDesc *TxDescArray;     /* Index of 256-alignment Tx Descriptor buffer */
352         struct RxDesc *RxDescArray;     /* Index of 256-alignment Rx Descriptor buffer */
353         unsigned char *RxBufferRing[NUM_RX_DESC];       /* Index of Rx Buffer array */
354         unsigned char *Tx_skbuff[NUM_TX_DESC];
355 } tpx;
356
357 static struct rtl8169_private *tpc;
358
359 static const u16 rtl8169_intr_mask =
360     LinkChg | RxOverflow | RxFIFOOver | TxErr | TxOK | RxErr | RxOK;
361 static const unsigned int rtl8169_rx_config =
362     (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift) |
363     0x0000000E;
364
365 static void rtl8169_hw_PHY_config(struct nic *nic __unused);
366 //static void rtl8169_hw_PHY_reset(struct net_device *dev);
367
368 #define RTL8169_WRITE_GMII_REG_BIT( ioaddr, reg, bitnum, bitval )\
369 { \
370        int val; \
371        if( bitval == 1 ){ val = ( RTL8169_READ_GMII_REG( ioaddr, reg ) | (bitval<<bitnum) ) & 0xffff ; } \
372        else{ val = ( RTL8169_READ_GMII_REG( ioaddr, reg ) & (~(0x0001<<bitnum)) ) & 0xffff ; } \
373        RTL8169_WRITE_GMII_REG( ioaddr, reg, val ); \
374  }
375
376 //=================================================================
377 //      PHYAR
378 //      bit             Symbol
379 //      31              Flag
380 //      30-21   reserved
381 //      20-16   5-bit GMII/MII register address
382 //      15-0    16-bit GMII/MII register data
383 //=================================================================
384 static void RTL8169_WRITE_GMII_REG(unsigned long ioaddr, int RegAddr, int value)
385 {
386         int i;
387
388         RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
389         udelay(1000);
390
391         for (i = 2000; i > 0; i--) {
392                 // Check if the RTL8169 has completed writing to the specified MII register
393                 if (!(RTL_R32(PHYAR) & 0x80000000)) {
394                         break;
395                 } else {
396                         udelay(100);
397                 }               // end of if( ! (RTL_R32(PHYAR)&0x80000000) )
398         }                       // end of for() loop
399 }
400
401 //=================================================================
402 static int RTL8169_READ_GMII_REG(unsigned long ioaddr, int RegAddr)
403 {
404         int i, value = -1;
405
406         RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
407         udelay(1000);
408
409         for (i = 2000; i > 0; i--) {
410                 // Check if the RTL8169 has completed retrieving data from the specified MII register
411                 if (RTL_R32(PHYAR) & 0x80000000) {
412                         value = (int) (RTL_R32(PHYAR) & 0xFFFF);
413                         break;
414                 } else {
415                         udelay(100);
416                 }               // end of if( RTL_R32(PHYAR) & 0x80000000 )
417         }                       // end of for() loop
418         return value;
419 }
420
421
422 #if 0
423 static void mdio_write(int RegAddr, int value)
424 {
425         int i;
426
427         RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
428         udelay(1000);
429
430         for (i = 2000; i > 0; i--) {
431                 /* Check if the RTL8169 has completed writing to the specified MII register */
432                 if (!(RTL_R32(PHYAR) & 0x80000000)) {
433                         break;
434                 } else {
435                         udelay(100);
436                 }
437         }
438 }
439
440 static int mdio_read(int RegAddr)
441 {
442         int i, value = -1;
443
444         RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
445         udelay(1000);
446
447         for (i = 2000; i > 0; i--) {
448                 /* Check if the RTL8169 has completed retrieving data from the specified MII register */
449                 if (RTL_R32(PHYAR) & 0x80000000) {
450                         value = (int) (RTL_R32(PHYAR) & 0xFFFF);
451                         break;
452                 } else {
453                         udelay(100);
454                 }
455         }
456         return value;
457 }
458 #endif
459
460 #define IORESOURCE_MEM 0x00000200
461
462 static int rtl8169_init_board(struct pci_device *pdev)
463 {
464         int i;
465 //      unsigned long mmio_end, mmio_flags
466         unsigned long mmio_start, mmio_len;
467
468         adjust_pci_device(pdev);
469
470         mmio_start = pci_bar_start(pdev, PCI_BASE_ADDRESS_1);
471 //       mmio_end = pci_resource_end (pdev, 1);
472 //       mmio_flags = pci_resource_flags (pdev, PCI_BASE_ADDRESS_1);
473         mmio_len = pci_bar_size(pdev, PCI_BASE_ADDRESS_1);
474
475         // make sure PCI base addr 1 is MMIO
476 //     if (!(mmio_flags & IORESOURCE_MEM)) {
477 //             printf ("region #1 not an MMIO resource, aborting\n");
478 //             return 0;
479 //     }
480
481         // check for weird/broken PCI region reporting
482         if (mmio_len < RTL_MIN_IO_SIZE) {
483                 printf("Invalid PCI region size(s), aborting\n");
484                 return 0;
485         }
486 #ifdef RTL8169_USE_IO
487         ioaddr = pci_bar_start(pdev, PCI_BASE_ADDRESS_0);
488 #else
489         // ioremap MMIO region
490         ioaddr = (unsigned long) ioremap(mmio_start, mmio_len);
491         if (ioaddr == 0) {
492                 printk("cannot remap MMIO, aborting\n");
493                 return 0;
494         }
495 #endif
496
497         tpc->mmio_addr = &ioaddr;
498         /* Soft reset the chip. */
499         RTL_W8(ChipCmd, CmdReset);
500
501         /* Check that the chip has finished the reset. */
502         for (i = 1000; i > 0; i--)
503                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
504                         break;
505                 else
506                         udelay(10);
507         // identify config method
508         {
509                 unsigned long val32 = (RTL_R32(TxConfig) & 0x7c800000);
510                 if (val32 == (0x1 << 28)) {
511                         tpc->mcfg = MCFG_METHOD_4;
512                 } else if (val32 == (0x1 << 26)) {
513                         tpc->mcfg = MCFG_METHOD_3;
514                 } else if (val32 == (0x1 << 23)) {
515                         tpc->mcfg = MCFG_METHOD_2;
516                 } else if (val32 == 0x00000000) {
517                         tpc->mcfg = MCFG_METHOD_1;
518                 } else {
519                         tpc->mcfg = MCFG_METHOD_1;
520                 }
521         }
522         {
523                 unsigned char val8 =
524                     (unsigned char) (RTL8169_READ_GMII_REG(ioaddr, 3) &
525                                      0x000f);
526                 if (val8 == 0x00) {
527                         tpc->pcfg = PCFG_METHOD_1;
528                 } else if (val8 == 0x01) {
529                         tpc->pcfg = PCFG_METHOD_2;
530                 } else if (val8 == 0x02) {
531                         tpc->pcfg = PCFG_METHOD_3;
532                 } else {
533                         tpc->pcfg = PCFG_METHOD_3;
534                 }
535         }
536
537         /* identify chip attached to board */
538
539         for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--)
540                 if (tpc->mcfg == rtl_chip_info[i].mcfg) {
541                         tpc->chipset = i;
542                         goto match;
543                 }
544         /* if unknown chip, assume array element #0, original RTL-8169 in this case */
545         DBG ( "PCI device: unknown chip version, assuming RTL-8169\n" );
546         DBG ( "PCI device: TxConfig = %#lX\n", ( unsigned long ) RTL_R32 ( TxConfig ) );
547
548         tpc->chipset = 0;
549         return 1;
550
551       match:
552         return 0;
553
554 }
555
556 /**************************************************************************
557 IRQ - Wait for a frame
558 ***************************************************************************/
559 static void r8169_irq(struct nic *nic __unused, irq_action_t action)
560 {
561         int intr_status = 0;
562         int interested = RxOverflow | RxFIFOOver | RxErr | RxOK;
563
564         switch (action) {
565         case DISABLE:
566         case ENABLE:
567                 intr_status = RTL_R16(IntrStatus);
568                 /* h/w no longer present (hotplug?) or major error, 
569                    bail */
570                 if (intr_status == 0xFFFF)
571                         break;
572                 
573                 intr_status = intr_status & ~interested;
574                 if (action == ENABLE)
575                         intr_status = intr_status | interested;
576                 RTL_W16(IntrMask, intr_status);
577                 break;
578         case FORCE:
579                 RTL_W8(TxPoll, (RTL_R8(TxPoll) | 0x01));
580                 break;
581         }
582 }
583
584 /**************************************************************************
585 POLL - Wait for a frame
586 ***************************************************************************/
587 static int r8169_poll(struct nic *nic, int retreive)
588 {
589         /* return true if there's an ethernet packet ready to read */
590         /* nic->packet should contain data on return */
591         /* nic->packetlen should contain length of data */
592         int cur_rx;
593         unsigned int intr_status = 0;
594         cur_rx = tpc->cur_rx;
595         if ((tpc->RxDescArray[cur_rx].status & OWNbit) == 0) {
596                 /* There is a packet ready */
597                 if (!retreive)
598                         return 1;
599                 intr_status = RTL_R16(IntrStatus);
600                 /* h/w no longer present (hotplug?) or major error,
601                    bail */
602                 if (intr_status == 0xFFFF)
603                         return 0;
604                 RTL_W16(IntrStatus, intr_status &
605                         ~(RxFIFOOver | RxOverflow | RxOK));
606
607                 if (!(tpc->RxDescArray[cur_rx].status & RxRES)) {
608                         nic->packetlen = (int) (tpc->RxDescArray[cur_rx].
609                                                 status & 0x00001FFF) - 4;
610                         memcpy(nic->packet, tpc->RxBufferRing[cur_rx],
611                                nic->packetlen);
612                         if (cur_rx == NUM_RX_DESC - 1)
613                                 tpc->RxDescArray[cur_rx].status =
614                                     (OWNbit | EORbit) + RX_BUF_SIZE;
615                         else
616                                 tpc->RxDescArray[cur_rx].status =
617                                     OWNbit + RX_BUF_SIZE;
618                         tpc->RxDescArray[cur_rx].buf_addr =
619                             virt_to_bus(tpc->RxBufferRing[cur_rx]);
620                 } else
621                         printf("Error Rx");
622                 /* FIXME: shouldn't I reset the status on an error */
623                 cur_rx = (cur_rx + 1) % NUM_RX_DESC;
624                 tpc->cur_rx = cur_rx;
625                 RTL_W16(IntrStatus, intr_status &
626                         (RxFIFOOver | RxOverflow | RxOK));
627
628                 return 1;
629
630         }
631         tpc->cur_rx = cur_rx;
632         /* FIXME: There is no reason to do this as cur_rx did not change */
633
634         return (0);             /* initially as this is called to flush the input */
635
636 }
637
638 /**************************************************************************
639 TRANSMIT - Transmit a frame
640 ***************************************************************************/
641 static void r8169_transmit(struct nic *nic, const char *d,      /* Destination */
642                            unsigned int t,      /* Type */
643                            unsigned int s,      /* size */
644                            const char *p)
645 {                               /* Packet */
646         /* send the packet to destination */
647
648         u16 nstype;
649         u32 to;
650         u8 *ptxb;
651         int entry = tpc->cur_tx % NUM_TX_DESC;
652
653         /* point to the current txb incase multiple tx_rings are used */
654         ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE];
655         memcpy(ptxb, d, ETH_ALEN);
656         memcpy(ptxb + ETH_ALEN, nic->node_addr, ETH_ALEN);
657         nstype = htons((u16) t);
658         memcpy(ptxb + 2 * ETH_ALEN, (u8 *) & nstype, 2);
659         memcpy(ptxb + ETH_HLEN, p, s);
660         s += ETH_HLEN;
661         s &= 0x0FFF;
662         while (s < ETH_ZLEN)
663                 ptxb[s++] = '\0';
664
665         tpc->TxDescArray[entry].buf_addr = virt_to_bus(ptxb);
666         if (entry != (NUM_TX_DESC - 1))
667                 tpc->TxDescArray[entry].status =
668                     (OWNbit | FSbit | LSbit) | ((s > ETH_ZLEN) ? s :
669                                                 ETH_ZLEN);
670         else
671                 tpc->TxDescArray[entry].status =
672                     (OWNbit | EORbit | FSbit | LSbit) | ((s > ETH_ZLEN) ? s
673                                                          : ETH_ZLEN);
674         RTL_W8(TxPoll, 0x40);   /* set polling bit */
675
676         tpc->cur_tx++;
677         to = currticks() + TX_TIMEOUT;
678         while ((tpc->TxDescArray[entry].status & OWNbit) && (currticks() < to));        /* wait */
679
680         if (currticks() >= to) {
681                 printf("TX Time Out");
682         }
683 }
684
685 static void rtl8169_set_rx_mode(struct nic *nic __unused)
686 {
687         u32 mc_filter[2];       /* Multicast hash filter */
688         int rx_mode;
689         u32 tmp = 0;
690
691         /* IFF_ALLMULTI */
692         /* Too many to filter perfectly -- accept all multicasts. */
693         rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
694         mc_filter[1] = mc_filter[0] = 0xffffffff;
695
696         tmp =
697             rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) &
698                                            rtl_chip_info[tpc->chipset].
699                                            RxConfigMask);
700
701         RTL_W32(RxConfig, tmp);
702         RTL_W32(MAR0 + 0, mc_filter[0]);
703         RTL_W32(MAR0 + 4, mc_filter[1]);
704 }
705 static void rtl8169_hw_start(struct nic *nic)
706 {
707         u32 i;
708
709         /* Soft reset the chip. */
710         RTL_W8(ChipCmd, CmdReset);
711
712         /* Check that the chip has finished the reset. */
713         for (i = 1000; i > 0; i--) {
714                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
715                         break;
716                 else
717                         udelay(10);
718         }
719
720         RTL_W8(Cfg9346, Cfg9346_Unlock);
721         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
722         RTL_W8(ETThReg, ETTh);
723
724         /* For gigabit rtl8169 */
725         RTL_W16(RxMaxSize, RxPacketMaxSize);
726
727         /* Set Rx Config register */
728         i = rtl8169_rx_config | (RTL_R32(RxConfig) &
729                                  rtl_chip_info[tpc->chipset].RxConfigMask);
730         RTL_W32(RxConfig, i);
731
732         /* Set DMA burst size and Interframe Gap Time */
733         RTL_W32(TxConfig,
734                 (TX_DMA_BURST << TxDMAShift) | (InterFrameGap <<
735                                                 TxInterFrameGapShift));
736
737
738         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd));
739
740         if (tpc->mcfg == MCFG_METHOD_2 || tpc->mcfg == MCFG_METHOD_3) {
741                 RTL_W16(CPlusCmd,
742                         (RTL_R16(CPlusCmd) | (1 << 14) | (1 << 3)));
743                 DBG
744                     ("Set MAC Reg C+CR Offset 0xE0: bit-3 and bit-14\n");
745         } else {
746                 RTL_W16(CPlusCmd, (RTL_R16(CPlusCmd) | (1 << 3)));
747                 DBG("Set MAC Reg C+CR Offset 0xE0: bit-3.\n");
748         }
749
750         {
751                 //RTL_W16(0xE2, 0x1517);
752                 //RTL_W16(0xE2, 0x152a);
753                 //RTL_W16(0xE2, 0x282a);
754                 RTL_W16(0xE2, 0x0000);
755         }
756
757
758
759         tpc->cur_rx = 0;
760
761         RTL_W32(TxDescStartAddr, virt_to_le32desc(tpc->TxDescArray));
762         RTL_W32(RxDescStartAddr, virt_to_le32desc(tpc->RxDescArray));
763         RTL_W8(Cfg9346, Cfg9346_Lock);
764         udelay(10);
765
766         RTL_W32(RxMissed, 0);
767
768         rtl8169_set_rx_mode(nic);
769
770         /* no early-rx interrupts */
771         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
772
773         RTL_W16(IntrMask, rtl8169_intr_mask);
774
775 }
776
777 static void rtl8169_init_ring(struct nic *nic __unused)
778 {
779         int i;
780
781         tpc->cur_rx = 0;
782         tpc->cur_tx = 0;
783         memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc));
784         memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc));
785
786         for (i = 0; i < NUM_TX_DESC; i++) {
787                 tpc->Tx_skbuff[i] = &txb[i];
788         }
789
790         for (i = 0; i < NUM_RX_DESC; i++) {
791                 if (i == (NUM_RX_DESC - 1))
792                         tpc->RxDescArray[i].status =
793                             (OWNbit | EORbit) | RX_BUF_SIZE;
794                 else
795                         tpc->RxDescArray[i].status = OWNbit | RX_BUF_SIZE;
796
797                 tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE];
798                 tpc->RxDescArray[i].buf_addr =
799                     virt_to_bus(tpc->RxBufferRing[i]);
800         }
801 }
802
803 /**************************************************************************
804 RESET - Finish setting up the ethernet interface
805 ***************************************************************************/
806 static void r8169_reset(struct nic *nic)
807 {
808         int i;
809
810         tpc->TxDescArray = tx_ring;
811         tpc->RxDescArray = rx_ring;
812
813         rtl8169_init_ring(nic);
814         rtl8169_hw_start(nic);
815         /* Construct a perfect filter frame with the mac address as first match
816          * and broadcast for all others */
817         for (i = 0; i < 192; i++)
818                 txb[i] = 0xFF;
819
820         txb[0] = nic->node_addr[0];
821         txb[1] = nic->node_addr[1];
822         txb[2] = nic->node_addr[2];
823         txb[3] = nic->node_addr[3];
824         txb[4] = nic->node_addr[4];
825         txb[5] = nic->node_addr[5];
826 }
827
828 /**************************************************************************
829 DISABLE - Turn off ethernet interface
830 ***************************************************************************/
831 static void r8169_disable ( struct nic *nic __unused ) {
832         int i;
833         /* Stop the chip's Tx and Rx DMA processes. */
834         RTL_W8(ChipCmd, 0x00);
835
836         /* Disable interrupts by clearing the interrupt mask. */
837         RTL_W16(IntrMask, 0x0000);
838
839         RTL_W32(RxMissed, 0);
840
841         tpc->TxDescArray = NULL;
842         tpc->RxDescArray = NULL;
843         for (i = 0; i < NUM_RX_DESC; i++) {
844                 tpc->RxBufferRing[i] = NULL;
845         }
846 }
847
848 static struct nic_operations r8169_operations = {
849         .connect        = dummy_connect,
850         .poll           = r8169_poll,
851         .transmit       = r8169_transmit,
852         .irq            = r8169_irq,
853
854 };
855
856 static struct pci_device_id r8169_nics[] = {
857         PCI_ROM(0x10ec, 0x8169, "r8169", "RealTek RTL8169 Gigabit Ethernet"),
858         PCI_ROM(0x16ec, 0x0116, "usr-r8169", "US Robotics RTL8169 Gigabit Ethernet"),
859         PCI_ROM(0x1186, 0x4300, "dlink-r8169", "D-Link RTL8169 Gigabit Ethernet"),
860         PCI_ROM(0x1737, 0x1032, "linksys-r8169", "Linksys RTL8169 Gigabit Ethernet"),
861 };
862
863 PCI_DRIVER ( r8169_driver, r8169_nics, PCI_NO_CLASS );
864
865 /**************************************************************************
866 PROBE - Look for an adapter, this routine's visible to the outside
867 ***************************************************************************/
868
869 #define board_found 1
870 #define valid_link 0
871 static int r8169_probe ( struct nic *nic, struct pci_device *pci ) {
872
873         static int board_idx = -1;
874         static int printed_version = 0;
875         int i, rc;
876         int option = -1, Cap10_100 = 0, Cap1000 = 0;
877
878         printf ( "r8169.c: Found %s, Vendor=%hX Device=%hX\n",
879                pci->driver_name, pci->vendor, pci->device );
880
881         board_idx++;
882
883         printed_version = 1;
884
885         /* Quick and very dirty hack to get r8169 driver working
886          * again, pre-rewrite
887          */
888         if ( ! r8169_bufs )
889                 r8169_bufs = malloc_dma ( sizeof ( *r8169_bufs ), 256 );
890         if ( ! r8169_bufs )
891                 return 0;
892         memset ( r8169_bufs, 0, sizeof ( *r8169_bufs ) );
893
894         /* point to private storage */
895         tpc = &tpx;
896
897         rc = rtl8169_init_board(pci);   /* Return code is meaningless */
898
899         /* Get MAC address.  FIXME: read EEPROM */
900         for (i = 0; i < MAC_ADDR_LEN; i++)
901                 nic->node_addr[i] = RTL_R8(MAC0 + i);
902
903         DBG ( "%s: Identified chip type is '%s'.\n", pci->driver_name,
904                  rtl_chip_info[tpc->chipset].name );
905
906         /* Print out some hardware info */
907         DBG ( "%s: %s at IOAddr %#hX, ", pci->driver_name, eth_ntoa ( nic->node_addr ),
908               (unsigned int) ioaddr );
909
910         /* Config PHY */
911         rtl8169_hw_PHY_config(nic);
912
913         DBG("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
914         RTL_W8(0x82, 0x01);
915
916         if (tpc->mcfg < MCFG_METHOD_3) {
917                 DBG("Set PCI Latency=0x40\n");
918                 pci_write_config_byte(pci, PCI_LATENCY_TIMER, 0x40);
919         }
920
921         if (tpc->mcfg == MCFG_METHOD_2) {
922                 DBG("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
923                 RTL_W8(0x82, 0x01);
924                 DBG("Set PHY Reg 0x0bh = 0x00h\n");
925                 RTL8169_WRITE_GMII_REG(ioaddr, 0x0b, 0x0000);   //w 0x0b 15 0 0
926         }
927
928         /* if TBI is not endbled */
929         if (!(RTL_R8(PHYstatus) & TBI_Enable)) {
930                 int val = RTL8169_READ_GMII_REG(ioaddr, PHY_AUTO_NEGO_REG);
931
932 #ifdef RTL8169_HW_FLOW_CONTROL_SUPPORT
933                 val |= PHY_Cap_PAUSE | PHY_Cap_ASYM_PAUSE;
934 #endif                          //end #define RTL8169_HW_FLOW_CONTROL_SUPPORT
935
936                 option = media;
937                 /* Force RTL8169 in 10/100/1000 Full/Half mode. */
938                 if (option > 0) {
939                         printf(" Force-mode Enabled.\n");
940                         Cap10_100 = 0, Cap1000 = 0;
941                         switch (option) {
942                         case _10_Half:
943                                 Cap10_100 = PHY_Cap_10_Half;
944                                 Cap1000 = PHY_Cap_Null;
945                                 break;
946                         case _10_Full:
947                                 Cap10_100 = PHY_Cap_10_Full;
948                                 Cap1000 = PHY_Cap_Null;
949                                 break;
950                         case _100_Half:
951                                 Cap10_100 = PHY_Cap_100_Half;
952                                 Cap1000 = PHY_Cap_Null;
953                                 break;
954                         case _100_Full:
955                                 Cap10_100 = PHY_Cap_100_Full;
956                                 Cap1000 = PHY_Cap_Null;
957                                 break;
958                         case _1000_Full:
959                                 Cap10_100 = PHY_Cap_Null;
960                                 Cap1000 = PHY_Cap_1000_Full;
961                                 break;
962                         default:
963                                 break;
964                         }
965                         RTL8169_WRITE_GMII_REG(ioaddr, PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0xC1F));   //leave PHY_AUTO_NEGO_REG bit4:0 unchanged
966                         RTL8169_WRITE_GMII_REG(ioaddr, PHY_1000_CTRL_REG,
967                                                Cap1000);
968                 } else {
969                         DBG ( "%s: Auto-negotiation Enabled.\n",  pci->driver_name );
970
971                         // enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged
972                         RTL8169_WRITE_GMII_REG(ioaddr, PHY_AUTO_NEGO_REG,
973                                                PHY_Cap_10_Half |
974                                                PHY_Cap_10_Full |
975                                                PHY_Cap_100_Half |
976                                                PHY_Cap_100_Full | (val &
977                                                                    0xC1F));
978
979                         // enable 1000 Full Mode
980 //                     RTL8169_WRITE_GMII_REG( ioaddr, PHY_1000_CTRL_REG, PHY_Cap_1000_Full );
981                         RTL8169_WRITE_GMII_REG(ioaddr, PHY_1000_CTRL_REG, PHY_Cap_1000_Full | PHY_Cap_1000_Half);       //rtl8168
982
983                 }               // end of if( option > 0 )
984
985                 // Enable auto-negotiation and restart auto-nigotiation
986                 RTL8169_WRITE_GMII_REG(ioaddr, PHY_CTRL_REG,
987                                        PHY_Enable_Auto_Nego |
988                                        PHY_Restart_Auto_Nego);
989                 udelay(100);
990
991                 // wait for auto-negotiation process
992                 for (i = 10000; i > 0; i--) {
993                         //check if auto-negotiation complete
994                         if (RTL8169_READ_GMII_REG(ioaddr, PHY_STAT_REG) &
995                             PHY_Auto_Neco_Comp) {
996                                 udelay(100);
997                                 option = RTL_R8(PHYstatus);
998                                 if (option & _1000bpsF) {
999                                         printf
1000                                             ("1000Mbps Full-duplex operation.\n");
1001                                 } else {
1002                                         printf
1003                                             ("%sMbps %s-duplex operation.\n",
1004                                              (option & _100bps) ? "100" :
1005                                              "10",
1006                                              (option & FullDup) ? "Full" :
1007                                              "Half");
1008                                 }
1009                                 break;
1010                         } else {
1011                                 udelay(100);
1012                         }       // end of if( RTL8169_READ_GMII_REG(ioaddr, 1) & 0x20 )
1013                 }               // end for-loop to wait for auto-negotiation process
1014
1015
1016         } else {
1017                 udelay(100);
1018                 printf
1019                     ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n",
1020                      pci->driver_name,
1021                      (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed");
1022
1023         }
1024
1025         r8169_reset(nic);
1026
1027         /* point to NIC specific routines */
1028         nic->nic_op = &r8169_operations;
1029
1030         nic->irqno  = pci->irq;
1031         nic->ioaddr = ioaddr;
1032
1033         return 1;
1034 }
1035
1036 //======================================================================================================
1037 /*
1038 static void rtl8169_hw_PHY_reset(struct nic *nic __unused)
1039 {
1040         int val, phy_reset_expiretime = 50;
1041         struct rtl8169_private *priv = dev->priv;
1042         unsigned long ioaddr = priv->ioaddr;
1043
1044         DBG("%s: Reset RTL8169s PHY\n", dev->name);
1045
1046         val = ( RTL8169_READ_GMII_REG( ioaddr, 0 ) | 0x8000 ) & 0xffff;
1047         RTL8169_WRITE_GMII_REG( ioaddr, 0, val );
1048
1049         do //waiting for phy reset
1050         {
1051                 if( RTL8169_READ_GMII_REG( ioaddr, 0 ) & 0x8000 ){
1052                         phy_reset_expiretime --;
1053                         udelay(100);
1054                 }
1055                 else{
1056                         break;
1057                 }
1058         }while( phy_reset_expiretime >= 0 );
1059
1060         assert( phy_reset_expiretime > 0 );
1061 }
1062
1063 */
1064
1065 //======================================================================================================
1066 static void rtl8169_hw_PHY_config(struct nic *nic __unused)
1067 {
1068
1069         DBG("priv->mcfg=%d, priv->pcfg=%d\n", tpc->mcfg, tpc->pcfg);
1070
1071         if (tpc->mcfg == MCFG_METHOD_4) {
1072 /*
1073                 RTL8169_WRITE_GMII_REG( (unsigned long)ioaddr, 0x1F, 0x0001 );
1074                 RTL8169_WRITE_GMII_REG( (unsigned long)ioaddr, 0x1b, 0x841e );
1075                 RTL8169_WRITE_GMII_REG( (unsigned long)ioaddr, 0x0e, 0x7bfb );
1076                 RTL8169_WRITE_GMII_REG( (unsigned long)ioaddr, 0x09, 0x273a );
1077 */
1078
1079                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x1F,
1080                                        0x0002);
1081                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x01,
1082                                        0x90D0);
1083                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x1F,
1084                                        0x0000);
1085         } else if ((tpc->mcfg == MCFG_METHOD_2)
1086                    || (tpc->mcfg == MCFG_METHOD_3)) {
1087                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x1F,
1088                                        0x0001);
1089                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x15,
1090                                        0x1000);
1091                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x18,
1092                                        0x65C7);
1093                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1094                                        0x0000);
1095                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x03,
1096                                        0x00A1);
1097                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x02,
1098                                        0x0008);
1099                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x01,
1100                                        0x1020);
1101                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x00,
1102                                        0x1000);
1103                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1104                                        0x0800);
1105                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1106                                        0x0000);
1107                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1108                                        0x7000);
1109                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x03,
1110                                        0xFF41);
1111                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x02,
1112                                        0xDE60);
1113                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x01,
1114                                        0x0140);
1115                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x00,
1116                                        0x0077);
1117                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1118                                        0x7800);
1119                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1120                                        0x7000);
1121                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1122                                        0xA000);
1123                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x03,
1124                                        0xDF01);
1125                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x02,
1126                                        0xDF20);
1127                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x01,
1128                                        0xFF95);
1129                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x00,
1130                                        0xFA00);
1131                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1132                                        0xA800);
1133                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1134                                        0xA000);
1135                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1136                                        0xB000);
1137                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x03,
1138                                        0xFF41);
1139                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x02,
1140                                        0xDE20);
1141                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x01,
1142                                        0x0140);
1143                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x00,
1144                                        0x00BB);
1145                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1146                                        0xB800);
1147                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1148                                        0xB000);
1149                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1150                                        0xF000);
1151                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x03,
1152                                        0xDF01);
1153                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x02,
1154                                        0xDF20);
1155                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x01,
1156                                        0xFF95);
1157                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x00,
1158                                        0xBF00);
1159                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1160                                        0xF800);
1161                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1162                                        0xF000);
1163                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1164                                        0x0000);
1165                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x1F,
1166                                        0x0000);
1167                 RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x0B,
1168                                        0x0000);
1169         } else {
1170                 DBG("tpc->mcfg=%d. Discard hw PHY config.\n",
1171                           tpc->mcfg);
1172         }
1173 }
1174
1175 DRIVER ( "r8169/PCI", nic_driver, pci_driver, r8169_driver,
1176          r8169_probe, r8169_disable );
1177
1178 /*
1179  * Local variables:
1180  *  c-basic-offset: 8
1181  *  c-indent-level: 8
1182  *  tab-width: 8
1183  * End:
1184  */