[USB] Kind of works..
[people/balajirrao/gpxe.git] / src / drivers / bus / usb / ohci_hcd.c
1 #include <errno.h>
2 #include <stdlib.h>
3 #include <unistd.h>
4 #include <gpxe/usb.h>
5 #include <gpxe/pci.h>
6 #include <gpxe/malloc.h>
7
8 #include <io.h>
9
10 #include "ohci.h"
11
12 int once = 0;
13
14 #define OHCI_INTR_INIT \
15                 (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \
16                 | OHCI_INTR_RD | OHCI_INTR_WDH)
17
18 static void ohci_usb_reset (struct ohci_hcd *ohci)
19 {
20         ohci->hc_control = readl (&ohci->regs->control);
21         ohci->hc_control &= OHCI_CTRL_RWC;
22         writel (ohci->hc_control, &ohci->regs->control);
23 }
24
25 static int ohci_init(struct ohci_hcd *ohci)
26 {
27         if (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
28                 u32 temp;
29
30                 DBG("USB HC TakeOver from BIOS/SMM\n");
31                 /* this timeout is arbitrary.  we make it long, so systems
32                  * depending on usb keyboards may be usable even if the
33                  * BIOS/SMM code seems pretty broken.
34                  */
35                 temp = 500;     /* arbitrary: five seconds */
36
37                 writel (OHCI_INTR_OC, &ohci->regs->intrenable);
38                 writel (OHCI_OCR, &ohci->regs->cmdstatus);
39                 while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
40                         mdelay (10);
41                         if (--temp == 0) {
42                                 DBG ("USB HC takeover failed!"
43                                         "  (BIOS/SMM bug)\n");
44                                 return -EBUSY;
45                         }
46                 }
47         }
48         
49         //mdelay(5000); 
50         ohci_usb_reset (ohci);
51
52         /* Disable HC interrupts */
53         writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
54
55         /* flush the writes, and save key bits like RWC */
56         if (readl (&ohci->regs->control) & OHCI_CTRL_RWC)
57                 ohci->hc_control |= OHCI_CTRL_RWC;
58
59         ohci->num_ports = roothub_a(ohci) & RH_A_NDP;
60         DBG("Num ports = %d\n", ohci->num_ports);
61
62         ohci->hcca = malloc_dma(sizeof(*ohci->hcca), 256);
63         writel(virt_to_bus(ohci->hcca), &ohci->regs->hcca);
64         return 0;
65 }
66
67 /*-------------------------------------------------------------------------*/
68
69 /*
70  * OHCI Root Hub ... the nonsharable stuff
71  */
72
73 #define dbg_port(hc,label,num,temp) \
74         DBG(    "%s roothub.portstatus [%d] " \
75                 "= 0x%08lx%s%s%s%s%s%s%s%s%s%s%s%s\n", \
76                 label, num, temp, \
77                 (temp & RH_PS_PRSC) ? " PRSC" : "", \
78                 (temp & RH_PS_OCIC) ? " OCIC" : "", \
79                 (temp & RH_PS_PSSC) ? " PSSC" : "", \
80                 (temp & RH_PS_PESC) ? " PESC" : "", \
81                 (temp & RH_PS_CSC) ? " CSC" : "", \
82                 \
83                 (temp & RH_PS_LSDA) ? " LSDA" : "", \
84                 (temp & RH_PS_PPS) ? " PPS" : "", \
85                 (temp & RH_PS_PRS) ? " PRS" : "", \
86                 (temp & RH_PS_POCI) ? " POCI" : "", \
87                 (temp & RH_PS_PSS) ? " PSS" : "", \
88                 \
89                 (temp & RH_PS_PES) ? " PES" : "", \
90                 (temp & RH_PS_CCS) ? " CCS" : "" \
91                 );
92
93 /*-------------------------------------------------------------------------*/
94
95 #if 0
96 /* See usb 7.1.7.5:  root hubs must issue at least 50 msec reset signaling,
97  * not necessarily continuous ... to guard against resume signaling.
98  * The short timeout is safe for non-root hubs, and is backward-compatible
99  * with earlier Linux hosts.
100  */
101 #define PORT_RESET_MSEC         50
102
103 static int reset_port (struct ohci_hcd *ohci, int port)
104 {
105         __hc32  *portstat = &ohci->regs->roothub.portstatus [port];
106         uint32_t        temp = 0;
107         int             timeout = 500;
108         
109         temp = readl (portstat);
110         DBG("Resetting port %d\n",port + 1);
111         if (!(temp & RH_PS_CCS))
112                 return -1;
113         if (temp & RH_PS_PRSC)
114                 writel (RH_PS_PRSC, portstat);
115
116         writel(RH_PS_PRS, portstat);
117
118         /* Wait until reset finishes */
119         temp = readl (portstat);
120         while ((temp & RH_PS_PRS) && (timeout > 0)) {
121                 mdelay(10);
122                 timeout -= 10;
123         }
124         mdelay(1);
125         
126         writel(RH_PS_PRSC | RH_PS_CSC, portstat);
127         ///* Now enable the port */
128         dbg_port(ohci, "PORT", port, roothub_portstatus(ohci, port));
129         mdelay(2000);
130 //      writel(roothub_portstatus(ohci, port) | RH_PS_PES, portstat);
131 //      mdelay(1);
132
133         return 0;
134
135 }
136
137 #endif
138
139 #define PORT_RESET_MSEC         50
140
141 /* this timer value might be vendor-specific ... */
142 #define PORT_RESET_HW_MSEC      10
143
144 /* wrap-aware logic morphed from <linux/jiffies.h> */
145 #define tick_before(t1,t2) ((int16_t)(((int16_t)(t1))-((int16_t)(t2))) < 0)
146
147 /* called from some task, normally khubd */
148 static inline int reset_port (struct ohci_hcd *ohci, unsigned port)
149 {
150         __hc32 *portstat = &ohci->regs->roothub.portstatus [port];
151         uint32_t        temp = 0;
152         uint16_t        now = readl(&ohci->regs->fmnumber);
153         uint16_t        reset_done = now + PORT_RESET_MSEC;
154         int             limit_1 = PORT_RESET_MSEC / PORT_RESET_HW_MSEC;
155
156         /* build a "continuous enough" reset signal, with up to
157          * 3msec gap between pulses.  scheduler HZ==100 must work;
158          * this might need to be deadline-scheduled.
159          */
160         do {
161                 int limit_2;
162
163                 /* spin until any current reset finishes */
164                 limit_2 = PORT_RESET_HW_MSEC * 2;
165                 while (--limit_2 >= 0) {
166                         temp = readl(portstat);
167                         /* handle e.g. CardBus eject */
168                         if (temp == ~(uint32_t)0)
169                                 return -1;
170                         if (!(temp & RH_PS_PRS))
171                                 break;
172                         udelay (500);
173                 }
174
175                 /* timeout (a hardware error) has been observed when
176                  * EHCI sets CF while this driver is resetting a port;
177                  * presumably other disconnect paths might do it too.
178                  */
179                 if (limit_2 < 0) {
180                         DBG("port[%d] reset timeout, stat %08lx\n",
181                                 port, temp);
182                         break;
183                 }
184
185                 if (!(temp & RH_PS_CCS))
186                         break;
187                 if (temp & RH_PS_PRSC)
188                         writel(RH_PS_PRSC, portstat);
189
190                 /* start the next reset, sleep till it's probably done */
191                 writel(RH_PS_PRS, portstat);
192                 mdelay(PORT_RESET_HW_MSEC);
193                 now = readl(&ohci->regs->fmnumber);
194         } while (tick_before(now, reset_done) && --limit_1 >= 0);
195
196         /* caller synchronizes using PRSC ... and handles PRS
197          * still being set when this returns.
198          */
199         mdelay(1);
200         return 0;
201 }
202
203 static inline int ohci_reset_port(struct usb_hcd *hcd, int port)
204 {
205         struct ohci_hcd *ohci = hcd_to_ohci(hcd);
206
207         return reset_port(ohci, port);
208         
209 }
210
211 static struct ohci_td * ohci_alloc_td (struct ohci_hcd *hc, struct ohci_ed *ed)
212 {
213         unsigned long   dma;
214         struct ohci_td  *td;
215
216         td = malloc_dma(sizeof(*td), 16);
217         dma = virt_to_bus(td);
218         if (td) {
219                 /* in case hc fetches it, make it look dead */
220                 memset (td, 0, sizeof(*td));
221                 td->hwNextTD = cpu_to_hc32 (hc, dma);
222                 td->dma = dma;
223                 td->ed = ed;
224         }
225         
226
227         return td;
228 }
229
230 static inline void ohci_fill_td (struct ohci_hcd *ohci, struct ohci_td *td,
231                                 uint32_t info, unsigned long data, unsigned int len)
232 {
233         info |= TD_DI_SET(6);
234
235         td->hwINFO = cpu_to_hc32(ohci, info);
236         td->hwCBP = cpu_to_hc32(ohci, data);
237
238         if(data)
239                 td->hwBE = cpu_to_hc32(ohci, data + len - 1);
240         else 
241                 td->hwBE = 0;
242
243         td->len = len;
244
245         td->ed->hwTailP = cpu_to_hc32(ohci, td->dma);
246         wmb();
247
248 }
249
250 static void ohci_free_td(struct ohci_td *td)
251 {
252         free_dma(td, sizeof(*td));
253 }
254
255 static void ohci_free_ed(struct ohci_ed *ed)
256 {
257         free_dma(ed, sizeof(*ed));
258 }
259
260 static struct ohci_ed * ohci_alloc_ed(struct urb *urb, struct ohci_hcd *ohci)
261 {
262         struct ohci_ed *ed;
263         struct ohci_td *td;
264         struct usb_host_endpoint *ep = urb->ep;
265         uint32_t info;
266         int     is_out;
267
268         ed = malloc_dma(sizeof(*ed), 16);
269         ed->dma = virt_to_bus(ed);
270         
271         if (!ed)
272                 goto err_malloc_ed;
273
274         td = ohci_alloc_td(ohci, ed);
275         if (!td)
276                 goto err_malloc_td;
277
278         is_out = (usb_ep_dir(ep) == USB_DIR_OUT);
279         info = urb->udev->devnum;
280
281         ed->dummy_td = td;
282         ed->hwTailP = cpu_to_hc32 (ohci, td->dma);
283         ed->hwHeadP = ed->hwTailP;      /* ED_C, ED_H zeroed */
284
285         info |= (usb_ep_num(ep)) << 7;
286         info |= le16_to_cpu(ep->desc.wMaxPacketSize) << 16;
287         
288 //      if (usb_ep_xfertype(ep) == USB_ENDPOINT_XFER_CONTROL)
289 //              info |= is_out ? ED_OUT : ED_IN;
290
291         ed->hwINFO = cpu_to_hc32(ohci, info);
292
293         INIT_LIST_HEAD(&ed->urbp_list);
294         return ed;
295
296         ohci_free_td(td);
297 err_malloc_td:
298         ohci_free_ed(ed);
299 err_malloc_ed:
300         return NULL;    
301 }
302
303 static void ohci_add_urbp_to_ed(struct ohci_urb_priv *urbp, struct ohci_ed *ed)
304 {
305         list_add_tail(&urbp->list, &ed->urbp_list);
306 }
307
308 static void ohci_del_urbp_from_ed(struct ohci_urb_priv *urbp)
309 {
310         list_del(&urbp->list);
311 }
312
313 static void ohci_add_td_to_urbp(struct ohci_td *td, struct ohci_urb_priv *urbp)
314 {
315         list_add_tail(&td->list, &urbp->td_list);
316 }
317
318 static void ohci_del_td_from_urbp(struct ohci_td *td)
319 {
320         list_del(&td->list);
321 }
322
323 static int ohci_submit_bulk(struct urb *urb, struct ohci_ed *ed)
324 {
325         struct ohci_hcd *ohci = hcd_to_ohci(urb->udev->hcd);
326         struct ohci_td *td;
327         unsigned int len = urb->transfer_buffer_length;
328         unsigned long data = urb->transfer_dma;
329         uint32_t *plink;
330         uint32_t info;
331         struct ohci_urb_priv *urbp = urb->hcpriv;
332         int is_out;
333
334         is_out = (usb_ep_dir(urb->ep) == USB_DIR_OUT);
335
336         info = is_out ?
337                 TD_CC | TD_T_TOGGLE | TD_DP_OUT | TD_R:
338                 TD_CC | TD_T_TOGGLE | TD_DP_IN | TD_R;
339
340         urbp->first_td = td = ed->dummy_td;
341         plink = NULL;
342
343         /*
344          * Build the DATA TDs
345          */
346         do {
347                 unsigned int pktsze = 4096;
348                 
349                 if (len <= pktsze) {            /* The last data packet */
350                         pktsze = len;
351                 }
352
353                 if (plink) {
354                         td = ohci_alloc_td(ohci, ed);
355                         if (!td)
356                                 goto err_td_malloc;
357                         *plink = cpu_to_hc32(ohci, td->dma);
358                 }
359
360                 ohci_fill_td(ohci, td, info, data, pktsze);
361                 ohci_add_td_to_urbp(td, urbp);
362                 plink = &td->hwNextTD;
363
364                 data += pktsze;
365                 len -= pktsze;
366         } while (len > 0);
367
368         urbp->last_td = td;
369         /*
370          * Build the new dummy TD and activate the old one
371          */
372         td = ohci_alloc_td(ohci, ed);
373         if (!td)
374                 goto err_dummytd_malloc;
375
376         *plink = cpu_to_hc32(ohci, td->dma);
377         ed->dummy_td = td;
378         ed->hwTailP = cpu_to_hc32(ohci, td->dma);
379         wmb();
380
381         writel(OHCI_BLF, &ohci->regs->cmdstatus); 
382         return 0;
383
384         ohci_free_td(ed->dummy_td);
385 err_dummytd_malloc:
386         list_for_each_entry(td, &urbp->td_list, list)
387                 ohci_del_td_from_urbp(td);
388 err_td_malloc:
389         list_for_each_entry(td, &urbp->td_list, list)
390                 ohci_del_td_from_urbp(td);
391
392         return -ENOMEM;
393 }
394
395 static int ohci_submit_control(struct urb *urb, struct ohci_ed *ed)
396 {
397         struct ohci_hcd *ohci = hcd_to_ohci(urb->udev->hcd);
398         struct ohci_td *td;
399         unsigned int len = urb->transfer_buffer_length;
400         unsigned long data = urb->transfer_dma;
401         uint32_t *plink;
402         uint32_t info;
403         struct ohci_urb_priv *urbp = urb->hcpriv;
404         int is_out;
405
406         is_out = (usb_ep_dir(urb->ep) == USB_DIR_OUT);
407
408         info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
409         urbp->first_td = td = ed->dummy_td;
410
411         ohci_fill_td(ohci, td, info, urb->setup_dma, 8);
412
413         ohci_add_td_to_urbp(td, urbp);
414         plink = &td->hwNextTD;
415
416         /*
417          * Build the DATA TDs
418          */
419 //      while (len > 0) {
420                 unsigned int pktsze = 4096;
421                 
422                 if (len <= pktsze) {            /* The last data packet */
423                         pktsze = len;
424                 }
425
426                 td = ohci_alloc_td(ohci, ed);
427                 if (!td)
428                         goto err_td_malloc;
429
430                 *plink = cpu_to_hc32(ohci, td->dma);
431
432                 info = TD_CC | TD_R | TD_T_DATA1;
433                 info |= is_out ? TD_DP_OUT : TD_DP_IN;
434                 ohci_fill_td(ohci, td, info, data, pktsze);
435                 ohci_add_td_to_urbp(td, urbp);
436                 plink = &td->hwNextTD;
437
438 //              data += pktsze;
439 //              len -= pktsze;
440 //      }
441
442         /*
443          * Build the final TD for control status 
444          */
445         urbp->last_td = td = ohci_alloc_td(ohci, ed);
446         if (!td) 
447                 goto err_td_malloc;
448
449         *plink = cpu_to_hc32(ohci, td->dma);
450
451         /* Change direction for the status transaction */
452         info = (is_out || (urb->transfer_buffer_length == 0)) ?
453                 TD_CC | TD_DP_IN | TD_T_DATA1:
454                 TD_CC | TD_DP_OUT | TD_T_DATA1;
455
456         ohci_add_td_to_urbp(td, urbp);
457         ohci_fill_td(ohci, td, info, 0, 0);
458         plink = &td->hwNextTD;
459
460         /*
461          * Build the new dummy TD and activate the old one
462          */
463         td = ohci_alloc_td(ohci, ed);
464         if (!td)
465                 goto err_dummytd_malloc;
466
467         *plink = cpu_to_hc32(ohci, td->dma);
468
469         wmb();
470
471         ed->dummy_td = td;
472         ed->hwTailP = cpu_to_hc32(ohci, td->dma);
473         writel(OHCI_CLF, &ohci->regs->cmdstatus); 
474
475         wmb();
476
477         return 0;
478
479         ohci_free_td(ed->dummy_td);
480 err_dummytd_malloc:
481         list_for_each_entry(td, &urbp->td_list, list)
482                 ohci_del_td_from_urbp(td);
483 err_td_malloc:
484         list_for_each_entry(td, &urbp->td_list, list)
485                 ohci_del_td_from_urbp(td);
486
487         return -ENOMEM;
488 }
489
490
491 static int ohci_enqueue_urb(struct usb_hcd *hcd, struct urb *urb)
492 {
493         struct ohci_hcd *ohci;
494         struct ohci_urb_priv *urbp;
495         struct ohci_ed *ed;
496         int ret = -ENOMEM;
497         uint32_t info;
498
499         ohci = hcd_to_ohci(hcd);                
500         urbp = malloc(sizeof(*urbp));
501         
502         if (!urbp)
503                 goto err_urb_malloc;
504
505         INIT_LIST_HEAD(&urbp->td_list);
506         urb->hcpriv = urbp;
507
508         if (!urb->ep->hcpriv) {
509                 /* Create a new ED for this endpoint */
510                 ed = urb->ep->hcpriv = ohci_alloc_ed(urb, ohci);
511                 if (!urb->ep->hcpriv)
512                         goto err_hcpriv_malloc; 
513                 if (usb_ep_xfertype(urb->ep) == USB_ENDPOINT_XFER_CONTROL) {
514                         
515                         /* Check to see if this is the first control ed */
516                         if (!readl(&ohci->regs->ed_controlhead)) {
517                                 writel(0, &ohci->regs->ed_controlcurrent);
518                                 writel(cpu_to_hc32(ohci, ed->dma), &ohci->regs->ed_controlhead);
519                                 ohci->hc_control |= OHCI_CTRL_CLE;
520                                 writel(ohci->hc_control, &ohci->regs->control);
521                                 wmb();
522                         } else {
523                                 ohci->last_control_ed->hwNextED = cpu_to_hc32(ohci, ed->dma);
524                         }
525                         ohci->last_control_ed = ed;
526                 } else {
527                         /* Check to see if this is the first ed */
528                         if (!readl(&ohci->regs->ed_bulkhead)) {
529                                 writel(0, &ohci->regs->ed_bulkcurrent);
530                                 writel(cpu_to_hc32(ohci, ed->dma), &ohci->regs->ed_bulkhead);
531                                 ohci->hc_control |= OHCI_CTRL_BLE;
532                                 writel(ohci->hc_control, &ohci->regs->control);
533                                 wmb();
534                         } else {
535                                 ohci->last_bulk_ed->hwNextED = cpu_to_hc32(ohci, ed->dma);
536                         }
537                         ohci->last_bulk_ed = ed;
538                 }
539         }
540         
541         /* Update the ed's fa */
542         ed = (struct ohci_ed *)urb->ep->hcpriv;
543         info = hc32_to_cpu(ohci, ed->hwINFO);
544         info &= ~((1 << 7) - 1);
545         info |= (urb->udev->devnum);
546         ed->hwINFO = cpu_to_hc32(ohci, info);
547         wmb();
548
549         /* Add the urbp to the ED's list */
550         ohci_add_urbp_to_ed(urbp, ed);
551         
552         if (usb_ep_xfertype(urb->ep) == USB_ENDPOINT_XFER_CONTROL) {
553                 if ((ret = ohci_submit_control(urb, ed)) < 0)
554                         goto err_submit_urb;
555         } else {
556                 if ((ret = ohci_submit_bulk(urb, ed)) < 0)
557                         goto err_submit_urb;    
558         }
559
560         return 0;
561
562         return ret;
563 err_submit_urb:
564         ohci_free_ed(urb->ep->hcpriv);
565 err_hcpriv_malloc:
566         free(urbp);
567 err_urb_malloc:
568         return ret;
569 }
570 static void ohci_unlink_urb(struct urb *urb)
571 {
572         struct ohci_td *td;
573         struct ohci_urb_priv *urbp;
574         struct ohci_hcd *ohci;
575
576         ohci = hcd_to_ohci(urb->udev->hcd);
577         urbp = urb->hcpriv;
578         list_for_each_entry(td, &urbp->td_list, list) {
579                 list_del(&td->list);
580                 mdelay(2);
581                 ohci_free_td(td);
582         }
583         ohci_del_urbp_from_ed(urbp);
584         free(urbp);
585
586 }
587
588 static int ohci_urb_status(struct urb *urb)
589 {
590         int ret = USB_URB_STATUS_COMPLETE;
591         struct ohci_urb_priv *urbp = urb->hcpriv;
592         struct ohci_td *td;
593         struct list_head *p;
594         struct ohci_hcd *ohci = hcd_to_ohci(urb->udev->hcd);
595         uint32_t info;
596         uint32_t be, cbp;
597
598         /* Check for the status of the first td *///
599         info = hc32_to_cpu(ohci, urbp->first_td->hwINFO);
600 //              DBG("%lx  %p %lx\n", urbp->first_td->hwINFO, urb, TD_CC_GET(info));
601 //                      mdelay(1000);                   
602         if (TD_CC_GET(info) != 0) {
603                 if (TD_CC_GET(info) == 0xf) {
604                         ret = USB_URB_STATUS_INPROGRESS;
605                         goto out;
606                 } else {
607                         ret = USB_URB_STATUS_ERROR;
608                         goto out;
609                 }
610         }
611
612         /* Check if URB is complete. Update urb->actual_length */
613         /* Optimie by looking at last_td directly. */
614         td = urbp->last_td;
615         info = hc32_to_cpu(ohci, urbp->last_td->hwINFO);
616 //      DBG("last td = %lx %lx\n", TD_CC_GET(info), urbp->last_td->hwINFO);     
617         if (TD_CC_GET(info) == 0) {
618                 be = hc32_to_cpu(ohci, td->hwBE);
619                 cbp = hc32_to_cpu(ohci, td->hwCBP);
620                 if (cbp == 0) {
621                                 urb->actual_length = urb->transfer_buffer_length;
622                                 return USB_URB_STATUS_COMPLETE;
623                 }
624         }
625
626         urb->actual_length = 0; 
627         list_for_each(p, &urbp->td_list) {
628                 unsigned long cbp, be;
629
630                 td = list_entry(p, struct ohci_td, list);
631                 info = hc32_to_cpu(ohci, td->hwINFO);
632                 cbp = hc32_to_cpu(ohci, td->hwCBP);
633                 be = hc32_to_cpu(ohci, td->hwBE);
634
635                 if (TD_CC_GET(info) != 0) {
636                         ret = USB_URB_STATUS_INPROGRESS;
637                         goto out;
638                 }
639
640                 if (cbp != 0)
641                         urb->actual_length += td->len - (be - cbp);
642                 else
643                         urb->actual_length += td->len;
644         }
645
646 out:
647         return ret;
648 }
649
650 static struct hc_driver ohci_driver = {
651         .urb_status = ohci_urb_status,
652         .enqueue_urb = ohci_enqueue_urb,
653         .reset_port = ohci_reset_port,
654         .unlink_urb = ohci_unlink_urb,
655 };
656
657 static int ohci_start(struct ohci_hcd *ohci)
658 {
659         uint32_t temp, mask;
660
661         temp = readl(&ohci->regs->fminterval);
662         ohci->fminterval = temp & 0x3fff;
663
664         if (ohci->fminterval != FI)
665                 DBG("fminterval delta %lx\n",ohci->fminterval - FI);
666         ohci->fminterval |= FSMP (ohci->fminterval) << 16;
667
668         switch (ohci->hc_control & OHCI_CTRL_HCFS) {
669         case OHCI_USB_OPER:
670                 temp = 0;
671                 break;
672         case OHCI_USB_SUSPEND:
673         case OHCI_USB_RESUME:
674                 ohci->hc_control &= OHCI_CTRL_RWC;
675                 ohci->hc_control |= OHCI_USB_RESUME;
676                 temp = 10 /* msec wait */;
677                 break;
678         // case OHCI_USB_RESET:
679         default:
680                 ohci->hc_control &= OHCI_CTRL_RWC;
681                 ohci->hc_control |= OHCI_USB_RESET;
682                 temp = 50 /* msec wait */;
683                 break;
684         }
685         writel(ohci->hc_control, &ohci->regs->control);
686         // flush the writes
687         (void) readl(&ohci->regs->control);
688         mdelay(temp);
689         
690         /* HC Reset requires max 10 us delay */
691         writel (OHCI_HCR,  &ohci->regs->cmdstatus);
692         temp = 30;      /* ... allow extra time */
693         while ((readl(&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
694                 if (--temp == 0) {
695                         DBG("USB HC reset timed out!\n");
696                         return -1;
697                 }
698                 udelay (1);
699         }
700
701         /* now we're in the SUSPEND state ... must go OPERATIONAL
702          * within 2msec else HC enters RESUME
703          * Tell the controller where the control and bulk lists are
704          * The lists are empty now. 
705          */
706
707         writel(0, &ohci->regs->ed_controlhead);
708         writel(0, &ohci->regs->ed_bulkhead);
709
710         periodic_reinit(ohci);
711
712         ohci->hc_control &= OHCI_CTRL_RWC;
713         ohci->hc_control |= OHCI_CTRL_CBSR | OHCI_USB_OPER;
714         writel(ohci->hc_control, &ohci->regs->control);
715
716         /* wake on ConnectStatusChange, matching external hubs */
717         writel (RH_HS_DRWE, &ohci->regs->roothub.status);
718
719         /* Choose the interrupts we care about now, others later on demand */
720         mask = OHCI_INTR_INIT;
721         writel (~0, &ohci->regs->intrstatus);
722         writel (mask, &ohci->regs->intrenable);
723
724         temp = roothub_a (ohci);
725         writel(RH_HS_LPSC, &ohci->regs->roothub.status);
726         writel((temp & RH_A_NPS) ? 0 : RH_B_PPCM, &ohci->regs->roothub.b);
727
728         // flush those writes
729         (void) readl(&ohci->regs->control);
730
731         return 0;
732 }
733 static int ohci_hcd_pci_probe(struct pci_device *pci,
734                                         const struct pci_device_id *id __unused)
735 {
736         struct usb_hcd *hcd;
737         struct ohci_hcd *ohci;
738         struct usb_device *udev;
739
740         int retval = -ENOMEM;
741         unsigned int port;
742
743         if (pci->class != PCI_CLASS_SERIAL_USB_OHCI)
744                 return -ENOTTY;
745
746         if (once == 1)
747                 return -1;
748
749         once = 1;
750
751         hcd = (struct usb_hcd *) malloc(sizeof(struct usb_hcd));
752         if (!hcd) {
753                 DBG("Failed allocating memory for usb_hcd\n");
754                 goto err_hcd_malloc;
755         }
756
757         ohci = hcd->hcpriv = malloc(sizeof(struct ohci_hcd));
758         if (!hcd->hcpriv) {
759                 DBG("Failed allocating memory for ohci_hcd\n");
760                 goto err_ohci_hcd_malloc;
761         }
762
763         pci_set_drvdata(pci, hcd);
764         hcd->driver = &ohci_driver;
765
766         hcd->res_addr = pci_bar_start(pci, PCI_BASE_ADDRESS_0);
767         hcd->res_size = pci_bar_size(pci, PCI_BASE_ADDRESS_0);
768
769         ohci->regs = ioremap(hcd->res_addr, hcd->res_size);
770         if (ohci->regs == NULL) {
771                 DBG("error mapping memory\n");
772                 retval = -EFAULT;
773                 goto err_ioremap;
774         }
775
776         DBG("OHCI Adapter Found at 0x%lx\n", hcd->res_addr);
777
778         ohci_init(ohci);
779
780         ohci_start(ohci);
781         /* Look for devices at ports */
782 mdelay(100);    
783         for (port = 0; port < ohci->num_ports; port++) {
784                 uint32_t status = roothub_portstatus (ohci, port);
785                 if (!(status & RH_PS_CCS)) {
786                         DBG("No device on port %d\n", port + 1);
787                         continue;
788                 }
789                 udev = usb_alloc_dev();
790                 if(!udev)
791                         goto err_usb_alloc_dev;
792                 udev->hcd = hcd;
793                 /* Tell the usb core about the new device */
794                 usb_dev_init(udev, port);
795         }
796
797         return 0;
798
799         usb_free_dev(udev);
800 err_usb_alloc_dev:
801         iounmap(ohci->regs);
802 err_ioremap:
803         free(hcd->hcpriv);
804 err_ohci_hcd_malloc:
805         free(hcd);
806 err_hcd_malloc:
807
808         return retval;
809 }
810
811 void ohci_hcd_pci_remove(struct pci_device *pci __unused)
812 {
813
814 }
815
816 static struct pci_device_id ohci_hcd_pci_ids[] = {
817         PCI_ROM(0xffff, 0xffff, "OHCI HCD", "OHCI USB Controller"),
818 };
819
820 struct pci_driver ohci_hcd_pci_driver __pci_driver = {
821         .ids = ohci_hcd_pci_ids,
822         .id_count = (sizeof(ohci_hcd_pci_ids) / sizeof(ohci_hcd_pci_ids[0])),
823         .probe = ohci_hcd_pci_probe,
824         .remove = ohci_hcd_pci_remove,
825 };
826