[tg3] Added support for tg3-5754.
[people/balajirrao/gpxe.git] / src / drivers / net / tg3.h
1 /* $Id$
2  * tg3.h: Definitions for Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001 Jeff Garzik (jgarzik@mandrakesoft.com)
6  */
7
8 #ifndef _T3_H
9 #define _T3_H
10
11 #include "stdint.h"
12
13 typedef unsigned long dma_addr_t;
14
15 /* From mii.h */
16
17 /* Indicates what features are advertised by the interface. */
18 #define ADVERTISED_10baseT_Half         (1 << 0)
19 #define ADVERTISED_10baseT_Full         (1 << 1)
20 #define ADVERTISED_100baseT_Half        (1 << 2)
21 #define ADVERTISED_100baseT_Full        (1 << 3)
22 #define ADVERTISED_1000baseT_Half       (1 << 4)
23 #define ADVERTISED_1000baseT_Full       (1 << 5)
24 #define ADVERTISED_Autoneg              (1 << 6)
25 #define ADVERTISED_TP                   (1 << 7)
26 #define ADVERTISED_AUI                  (1 << 8)
27 #define ADVERTISED_MII                  (1 << 9)
28 #define ADVERTISED_FIBRE                (1 << 10)
29 #define ADVERTISED_BNC                  (1 << 11)
30
31 /* The following are all involved in forcing a particular link
32  * mode for the device for setting things.  When getting the
33  * devices settings, these indicate the current mode and whether
34  * it was foced up into this mode or autonegotiated.
35  */
36
37 /* The forced speed, 10Mb, 100Mb, gigabit. */
38 #define SPEED_10                0
39 #define SPEED_100               1
40 #define SPEED_1000              2
41 #define SPEED_INVALID           3
42
43
44 /* Duplex, half or full. */
45 #define DUPLEX_HALF             0x00
46 #define DUPLEX_FULL             0x01
47 #define DUPLEX_INVALID          0x02
48
49 /* Which connector port. */
50 #define PORT_TP                 0x00
51 #define PORT_AUI                0x01
52 #define PORT_MII                0x02
53 #define PORT_FIBRE              0x03
54 #define PORT_BNC                0x04
55
56 /* Which tranceiver to use. */
57 #define XCVR_INTERNAL           0x00
58 #define XCVR_EXTERNAL           0x01
59 #define XCVR_DUMMY1             0x02
60 #define XCVR_DUMMY2             0x03
61 #define XCVR_DUMMY3             0x04
62
63 /* Enable or disable autonegotiation.  If this is set to enable,
64  * the forced link modes above are completely ignored.
65  */
66 #define AUTONEG_DISABLE         0x00
67 #define AUTONEG_ENABLE          0x01
68
69 /* Wake-On-Lan options. */
70 #define WAKE_PHY                (1 << 0)
71 #define WAKE_UCAST              (1 << 1)
72 #define WAKE_MCAST              (1 << 2)
73 #define WAKE_BCAST              (1 << 3)
74 #define WAKE_ARP                (1 << 4)
75 #define WAKE_MAGIC              (1 << 5)
76 #define WAKE_MAGICSECURE        (1 << 6) /* only meaningful if WAKE_MAGIC */
77
78 /* Generic MII registers. */
79
80 #define MII_BMCR            0x00        /* Basic mode control register */
81 #define MII_BMSR            0x01        /* Basic mode status register  */
82 #define MII_PHYSID1         0x02        /* PHYS ID 1                   */
83 #define MII_PHYSID2         0x03        /* PHYS ID 2                   */
84 #define MII_ADVERTISE       0x04        /* Advertisement control reg   */
85 #define MII_LPA             0x05        /* Link partner ability reg    */
86 #define MII_EXPANSION       0x06        /* Expansion register          */
87 #define MII_DCOUNTER        0x12        /* Disconnect counter          */
88 #define MII_FCSCOUNTER      0x13        /* False carrier counter       */
89 #define MII_NWAYTEST        0x14        /* N-way auto-neg test reg     */
90 #define MII_RERRCOUNTER     0x15        /* Receive error counter       */
91 #define MII_SREVISION       0x16        /* Silicon revision            */
92 #define MII_RESV1           0x17        /* Reserved...                 */
93 #define MII_LBRERROR        0x18        /* Lpback, rx, bypass error    */
94 #define MII_PHYADDR         0x19        /* PHY address                 */
95 #define MII_RESV2           0x1a        /* Reserved...                 */
96 #define MII_TPISTATUS       0x1b        /* TPI status for 10mbps       */
97 #define MII_NCONFIG         0x1c        /* Network interface config    */
98
99 /* Basic mode control register. */
100 #define BMCR_RESV               0x007f  /* Unused...                   */
101 #define BMCR_CTST               0x0080  /* Collision test              */
102 #define BMCR_FULLDPLX           0x0100  /* Full duplex                 */
103 #define BMCR_ANRESTART          0x0200  /* Auto negotiation restart    */
104 #define BMCR_ISOLATE            0x0400  /* Disconnect DP83840 from MII */
105 #define BMCR_PDOWN              0x0800  /* Powerdown the DP83840       */
106 #define BMCR_ANENABLE           0x1000  /* Enable auto negotiation     */
107 #define BMCR_SPEED100           0x2000  /* Select 100Mbps              */
108 #define BMCR_LOOPBACK           0x4000  /* TXD loopback bits           */
109 #define BMCR_RESET              0x8000  /* Reset the DP83840           */
110
111 /* Basic mode status register. */
112 #define BMSR_ERCAP              0x0001  /* Ext-reg capability          */
113 #define BMSR_JCD                0x0002  /* Jabber detected             */
114 #define BMSR_LSTATUS            0x0004  /* Link status                 */
115 #define BMSR_ANEGCAPABLE        0x0008  /* Able to do auto-negotiation */
116 #define BMSR_RFAULT             0x0010  /* Remote fault detected       */
117 #define BMSR_ANEGCOMPLETE       0x0020  /* Auto-negotiation complete   */
118 #define BMSR_RESV               0x07c0  /* Unused...                   */
119 #define BMSR_10HALF             0x0800  /* Can do 10mbps, half-duplex  */
120 #define BMSR_10FULL             0x1000  /* Can do 10mbps, full-duplex  */
121 #define BMSR_100HALF            0x2000  /* Can do 100mbps, half-duplex */
122 #define BMSR_100FULL            0x4000  /* Can do 100mbps, full-duplex */
123 #define BMSR_100BASE4           0x8000  /* Can do 100mbps, 4k packets  */
124
125 /* Advertisement control register. */
126 #define ADVERTISE_SLCT          0x001f  /* Selector bits               */
127 #define ADVERTISE_CSMA          0x0001  /* Only selector supported     */
128 #define ADVERTISE_10HALF        0x0020  /* Try for 10mbps half-duplex  */
129 #define ADVERTISE_10FULL        0x0040  /* Try for 10mbps full-duplex  */
130 #define ADVERTISE_100HALF       0x0080  /* Try for 100mbps half-duplex */
131 #define ADVERTISE_100FULL       0x0100  /* Try for 100mbps full-duplex */
132 #define ADVERTISE_100BASE4      0x0200  /* Try for 100mbps 4k packets  */
133 #define ADVERTISE_RESV          0x1c00  /* Unused...                   */
134 #define ADVERTISE_RFAULT        0x2000  /* Say we can detect faults    */
135 #define ADVERTISE_LPACK         0x4000  /* Ack link partners response  */
136 #define ADVERTISE_NPAGE         0x8000  /* Next page bit               */
137
138 #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
139                         ADVERTISE_CSMA)
140 #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
141                        ADVERTISE_100HALF | ADVERTISE_100FULL)
142
143 /* Link partner ability register. */
144 #define LPA_SLCT                0x001f  /* Same as advertise selector  */
145 #define LPA_10HALF              0x0020  /* Can do 10mbps half-duplex   */
146 #define LPA_10FULL              0x0040  /* Can do 10mbps full-duplex   */
147 #define LPA_100HALF             0x0080  /* Can do 100mbps half-duplex  */
148 #define LPA_100FULL             0x0100  /* Can do 100mbps full-duplex  */
149 #define LPA_100BASE4            0x0200  /* Can do 100mbps 4k packets   */
150 #define LPA_RESV                0x1c00  /* Unused...                   */
151 #define LPA_RFAULT              0x2000  /* Link partner faulted        */
152 #define LPA_LPACK               0x4000  /* Link partner acked us       */
153 #define LPA_NPAGE               0x8000  /* Next page bit               */
154
155 #define LPA_DUPLEX              (LPA_10FULL | LPA_100FULL)
156 #define LPA_100                 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
157
158 /* Expansion register for auto-negotiation. */
159 #define EXPANSION_NWAY          0x0001  /* Can do N-way auto-nego      */
160 #define EXPANSION_LCWP          0x0002  /* Got new RX page code word   */
161 #define EXPANSION_ENABLENPAGE   0x0004  /* This enables npage words    */
162 #define EXPANSION_NPCAPABLE     0x0008  /* Link partner supports npage */
163 #define EXPANSION_MFAULTS       0x0010  /* Multiple faults detected    */
164 #define EXPANSION_RESV          0xffe0  /* Unused...                   */
165
166 /* N-way test register. */
167 #define NWAYTEST_RESV1          0x00ff  /* Unused...                   */
168 #define NWAYTEST_LOOPBACK       0x0100  /* Enable loopback for N-way   */
169 #define NWAYTEST_RESV2          0xfe00  /* Unused...                   */
170
171
172 /* From tg3.h */
173
174 #define TG3_64BIT_REG_HIGH              0x00UL
175 #define TG3_64BIT_REG_LOW               0x04UL
176
177 /* Descriptor block info. */
178 #define TG3_BDINFO_HOST_ADDR            0x0UL /* 64-bit */
179 #define TG3_BDINFO_MAXLEN_FLAGS         0x8UL /* 32-bit */
180 #define  BDINFO_FLAGS_USE_EXT_RECV       0x00000001 /* ext rx_buffer_desc */
181 #define  BDINFO_FLAGS_DISABLED           0x00000002
182 #define  BDINFO_FLAGS_MAXLEN_MASK        0xffff0000
183 #define  BDINFO_FLAGS_MAXLEN_SHIFT       16
184 #define TG3_BDINFO_NIC_ADDR             0xcUL /* 32-bit */
185 #define TG3_BDINFO_SIZE                 0x10UL
186
187 #define RX_COPY_THRESHOLD               256
188
189 #define RX_STD_MAX_SIZE                 1536
190 #define RX_STD_MAX_SIZE_5705            512
191 #define RX_JUMBO_MAX_SIZE               0xdeadbeef /* XXX */
192
193 /* First 256 bytes are a mirror of PCI config space. */
194 #define TG3PCI_VENDOR                   0x00000000
195 #define  TG3PCI_VENDOR_BROADCOM          0x14e4
196 #define TG3PCI_DEVICE                   0x00000002
197 #define  TG3PCI_DEVICE_TIGON3_1          0x1644 /* BCM5700 */
198 #define  TG3PCI_DEVICE_TIGON3_2          0x1645 /* BCM5701 */
199 #define  TG3PCI_DEVICE_TIGON3_3          0x1646 /* BCM5702 */
200 #define  TG3PCI_DEVICE_TIGON3_4          0x1647 /* BCM5703 */
201 #define TG3PCI_COMMAND                  0x00000004
202 #define TG3PCI_STATUS                   0x00000006
203 #define TG3PCI_CCREVID                  0x00000008
204 #define TG3PCI_CACHELINESZ              0x0000000c
205 #define TG3PCI_LATTIMER                 0x0000000d
206 #define TG3PCI_HEADERTYPE               0x0000000e
207 #define TG3PCI_BIST                     0x0000000f
208 #define TG3PCI_BASE0_LOW                0x00000010
209 #define TG3PCI_BASE0_HIGH               0x00000014
210 /* 0x18 --> 0x2c unused */
211 #define TG3PCI_SUBSYSVENID              0x0000002c
212 #define TG3PCI_SUBSYSID                 0x0000002e
213 #define TG3PCI_ROMADDR                  0x00000030
214 #define TG3PCI_CAPLIST                  0x00000034
215 /* 0x35 --> 0x3c unused */
216 #define TG3PCI_IRQ_LINE                 0x0000003c
217 #define TG3PCI_IRQ_PIN                  0x0000003d
218 #define TG3PCI_MIN_GNT                  0x0000003e
219 #define TG3PCI_MAX_LAT                  0x0000003f
220 #define TG3PCI_X_CAPS                   0x00000040
221 #define  PCIX_CAPS_RELAXED_ORDERING      0x00020000
222 #define  PCIX_CAPS_SPLIT_MASK            0x00700000
223 #define  PCIX_CAPS_SPLIT_SHIFT           20
224 #define  PCIX_CAPS_BURST_MASK            0x000c0000
225 #define  PCIX_CAPS_BURST_SHIFT           18
226 #define  PCIX_CAPS_MAX_BURST_CPIOB       2
227 #define TG3PCI_PM_CAP_PTR               0x00000041
228 #define TG3PCI_X_COMMAND                0x00000042
229 #define TG3PCI_X_STATUS                 0x00000044
230 #define TG3PCI_PM_CAP_ID                0x00000048
231 #define TG3PCI_VPD_CAP_PTR              0x00000049
232 #define TG3PCI_PM_CAPS                  0x0000004a
233 #define TG3PCI_PM_CTRL_STAT             0x0000004c
234 #define TG3PCI_BR_SUPP_EXT              0x0000004e
235 #define TG3PCI_PM_DATA                  0x0000004f
236 #define TG3PCI_VPD_CAP_ID               0x00000050
237 #define TG3PCI_MSI_CAP_PTR              0x00000051
238 #define TG3PCI_VPD_ADDR_FLAG            0x00000052
239 #define  VPD_ADDR_FLAG_WRITE            0x00008000
240 #define TG3PCI_VPD_DATA                 0x00000054
241 #define TG3PCI_MSI_CAP_ID               0x00000058
242 #define TG3PCI_NXT_CAP_PTR              0x00000059
243 #define TG3PCI_MSI_CTRL                 0x0000005a
244 #define TG3PCI_MSI_ADDR_LOW             0x0000005c
245 #define TG3PCI_MSI_ADDR_HIGH            0x00000060
246 #define TG3PCI_MSI_DATA                 0x00000064
247 /* 0x66 --> 0x68 unused */
248 #define TG3PCI_MISC_HOST_CTRL           0x00000068
249 #define  MISC_HOST_CTRL_CLEAR_INT        0x00000001
250 #define  MISC_HOST_CTRL_MASK_PCI_INT     0x00000002
251 #define  MISC_HOST_CTRL_BYTE_SWAP        0x00000004
252 #define  MISC_HOST_CTRL_WORD_SWAP        0x00000008
253 #define  MISC_HOST_CTRL_PCISTATE_RW      0x00000010
254 #define  MISC_HOST_CTRL_CLKREG_RW        0x00000020
255 #define  MISC_HOST_CTRL_REGWORD_SWAP     0x00000040
256 #define  MISC_HOST_CTRL_INDIR_ACCESS     0x00000080
257 #define  MISC_HOST_CTRL_IRQ_MASK_MODE    0x00000100
258 #define  MISC_HOST_CTRL_TAGGED_STATUS    0x00000200
259 #define  MISC_HOST_CTRL_CHIPREV          0xffff0000
260 #define  MISC_HOST_CTRL_CHIPREV_SHIFT    16
261 #define  GET_CHIP_REV_ID(MISC_HOST_CTRL) \
262          (((MISC_HOST_CTRL) & MISC_HOST_CTRL_CHIPREV) >> \
263           MISC_HOST_CTRL_CHIPREV_SHIFT)
264 #define  CHIPREV_ID_5700_A0              0x7000
265 #define  CHIPREV_ID_5700_A1              0x7001
266 #define  CHIPREV_ID_5700_B0              0x7100
267 #define  CHIPREV_ID_5700_B1              0x7101
268 #define  CHIPREV_ID_5700_B3              0x7102
269 #define  CHIPREV_ID_5700_ALTIMA          0x7104
270 #define  CHIPREV_ID_5700_C0              0x7200
271 #define  CHIPREV_ID_5701_A0              0x0000
272 #define  CHIPREV_ID_5701_B0              0x0100
273 #define  CHIPREV_ID_5701_B2              0x0102
274 #define  CHIPREV_ID_5701_B5              0x0105
275 #define  CHIPREV_ID_5703_A0              0x1000
276 #define  CHIPREV_ID_5703_A1              0x1001
277 #define  CHIPREV_ID_5703_A2              0x1002
278 #define  CHIPREV_ID_5703_A3              0x1003
279 #define  CHIPREV_ID_5704_A0              0x2000
280 #define  CHIPREV_ID_5704_A1              0x2001
281 #define  CHIPREV_ID_5704_A2              0x2002
282 #define  CHIPREV_ID_5705_A0              0x3000
283 #define  CHIPREV_ID_5705_A1              0x3001
284 #define  CHIPREV_ID_5705_A2              0x3002
285 #define  CHIPREV_ID_5705_A3              0x3003
286 #define  CHIPREV_ID_5721                 0x4101
287 #define  CHIPREV_ID_5750_A0              0x4000
288 #define  CHIPREV_ID_5750_A1              0x4001
289 #define  CHIPREV_ID_5750_A3              0x4003
290 #define  GET_ASIC_REV(CHIP_REV_ID)      ((CHIP_REV_ID) >> 12)
291 #define   ASIC_REV_5700                  0x07
292 #define   ASIC_REV_5701                  0x00
293 #define   ASIC_REV_5703                  0x01
294 #define   ASIC_REV_5704                  0x02
295 #define   ASIC_REV_5705                  0x03
296 #define   ASIC_REV_5750                  0x04
297 #define   ASIC_REV_5787                  0x0b
298 #define  GET_CHIP_REV(CHIP_REV_ID)      ((CHIP_REV_ID) >> 8)
299 #define   CHIPREV_5700_AX                0x70
300 #define   CHIPREV_5700_BX                0x71
301 #define   CHIPREV_5700_CX                0x72
302 #define   CHIPREV_5701_AX                0x00
303 #define  GET_METAL_REV(CHIP_REV_ID)     ((CHIP_REV_ID) & 0xff)
304 #define   METAL_REV_A0                   0x00
305 #define   METAL_REV_A1                   0x01
306 #define   METAL_REV_B0                   0x00
307 #define   METAL_REV_B1                   0x01
308 #define   METAL_REV_B2                   0x02
309 #define TG3PCI_DMA_RW_CTRL              0x0000006c
310 #define  DMA_RWCTRL_MIN_DMA              0x000000ff
311 #define  DMA_RWCTRL_MIN_DMA_SHIFT        0
312 #define  DMA_RWCTRL_READ_BNDRY_MASK      0x00000700
313 #define  DMA_RWCTRL_READ_BNDRY_DISAB     0x00000000
314 #define  DMA_RWCTRL_READ_BNDRY_16        0x00000100
315 #define  DMA_RWCTRL_READ_BNDRY_32        0x00000200
316 #define  DMA_RWCTRL_READ_BNDRY_64        0x00000300
317 #define  DMA_RWCTRL_READ_BNDRY_128       0x00000400
318 #define  DMA_RWCTRL_READ_BNDRY_256       0x00000500
319 #define  DMA_RWCTRL_READ_BNDRY_512       0x00000600
320 #define  DMA_RWCTRL_READ_BNDRY_1024      0x00000700
321 #define  DMA_RWCTRL_WRITE_BNDRY_MASK     0x00003800
322 #define  DMA_RWCTRL_WRITE_BNDRY_DISAB    0x00000000
323 #define  DMA_RWCTRL_WRITE_BNDRY_16       0x00000800
324 #define  DMA_RWCTRL_WRITE_BNDRY_32       0x00001000
325 #define  DMA_RWCTRL_WRITE_BNDRY_64       0x00001800
326 #define  DMA_RWCTRL_WRITE_BNDRY_128      0x00002000
327 #define  DMA_RWCTRL_WRITE_BNDRY_256      0x00002800
328 #define  DMA_RWCTRL_WRITE_BNDRY_512      0x00003000
329 #define  DMA_RWCTRL_WRITE_BNDRY_1024     0x00003800
330 #define  DMA_RWCTRL_ONE_DMA              0x00004000
331 #define  DMA_RWCTRL_READ_WATER           0x00070000
332 #define  DMA_RWCTRL_READ_WATER_SHIFT     16
333 #define  DMA_RWCTRL_WRITE_WATER          0x00380000
334 #define  DMA_RWCTRL_WRITE_WATER_SHIFT    19
335 #define  DMA_RWCTRL_USE_MEM_READ_MULT    0x00400000
336 #define  DMA_RWCTRL_ASSERT_ALL_BE        0x00800000
337 #define  DMA_RWCTRL_PCI_READ_CMD         0x0f000000
338 #define  DMA_RWCTRL_PCI_READ_CMD_SHIFT   24
339 #define  DMA_RWCTRL_PCI_WRITE_CMD        0xf0000000
340 #define  DMA_RWCTRL_PCI_WRITE_CMD_SHIFT  28
341 #define TG3PCI_PCISTATE                 0x00000070
342 #define  PCISTATE_FORCE_RESET            0x00000001
343 #define  PCISTATE_INT_NOT_ACTIVE         0x00000002
344 #define  PCISTATE_CONV_PCI_MODE          0x00000004
345 #define  PCISTATE_BUS_SPEED_HIGH         0x00000008
346 #define  PCISTATE_BUS_32BIT              0x00000010
347 #define  PCISTATE_ROM_ENABLE             0x00000020
348 #define  PCISTATE_ROM_RETRY_ENABLE       0x00000040
349 #define  PCISTATE_FLAT_VIEW              0x00000100
350 #define  PCISTATE_RETRY_SAME_DMA         0x00002000
351 #define TG3PCI_CLOCK_CTRL               0x00000074
352 #define  CLOCK_CTRL_CORECLK_DISABLE      0x00000200
353 #define  CLOCK_CTRL_RXCLK_DISABLE        0x00000400
354 #define  CLOCK_CTRL_TXCLK_DISABLE        0x00000800
355 #define  CLOCK_CTRL_ALTCLK               0x00001000
356 #define  CLOCK_CTRL_PWRDOWN_PLL133       0x00008000
357 #define  CLOCK_CTRL_44MHZ_CORE           0x00040000
358 #define  CLOCK_CTRL_625_CORE             0x00100000
359 #define  CLOCK_CTRL_FORCE_CLKRUN         0x00200000
360 #define  CLOCK_CTRL_CLKRUN_OENABLE       0x00400000
361 #define  CLOCK_CTRL_DELAY_PCI_GRANT      0x80000000
362 #define TG3PCI_REG_BASE_ADDR            0x00000078
363 #define TG3PCI_MEM_WIN_BASE_ADDR        0x0000007c
364 #define TG3PCI_REG_DATA                 0x00000080
365 #define TG3PCI_MEM_WIN_DATA             0x00000084
366 #define TG3PCI_MODE_CTRL                0x00000088
367 #define TG3PCI_MISC_CFG                 0x0000008c
368 #define TG3PCI_MISC_LOCAL_CTRL          0x00000090
369 /* 0x94 --> 0x98 unused */
370 #define TG3PCI_STD_RING_PROD_IDX        0x00000098 /* 64-bit */
371 #define TG3PCI_RCV_RET_RING_CON_IDX     0x000000a0 /* 64-bit */
372 #define TG3PCI_SND_PROD_IDX             0x000000a8 /* 64-bit */
373 /* 0xb0 --> 0x100 unused */
374
375 /* 0x100 --> 0x200 unused */
376
377 /* Mailbox registers */
378 #define MAILBOX_INTERRUPT_0             0x00000200 /* 64-bit */
379 #define MAILBOX_INTERRUPT_1             0x00000208 /* 64-bit */
380 #define MAILBOX_INTERRUPT_2             0x00000210 /* 64-bit */
381 #define MAILBOX_INTERRUPT_3             0x00000218 /* 64-bit */
382 #define MAILBOX_GENERAL_0               0x00000220 /* 64-bit */
383 #define MAILBOX_GENERAL_1               0x00000228 /* 64-bit */
384 #define MAILBOX_GENERAL_2               0x00000230 /* 64-bit */
385 #define MAILBOX_GENERAL_3               0x00000238 /* 64-bit */
386 #define MAILBOX_GENERAL_4               0x00000240 /* 64-bit */
387 #define MAILBOX_GENERAL_5               0x00000248 /* 64-bit */
388 #define MAILBOX_GENERAL_6               0x00000250 /* 64-bit */
389 #define MAILBOX_GENERAL_7               0x00000258 /* 64-bit */
390 #define MAILBOX_RELOAD_STAT             0x00000260 /* 64-bit */
391 #define MAILBOX_RCV_STD_PROD_IDX        0x00000268 /* 64-bit */
392 #define MAILBOX_RCV_JUMBO_PROD_IDX      0x00000270 /* 64-bit */
393 #define MAILBOX_RCV_MINI_PROD_IDX       0x00000278 /* 64-bit */
394 #define MAILBOX_RCVRET_CON_IDX_0        0x00000280 /* 64-bit */
395 #define MAILBOX_RCVRET_CON_IDX_1        0x00000288 /* 64-bit */
396 #define MAILBOX_RCVRET_CON_IDX_2        0x00000290 /* 64-bit */
397 #define MAILBOX_RCVRET_CON_IDX_3        0x00000298 /* 64-bit */
398 #define MAILBOX_RCVRET_CON_IDX_4        0x000002a0 /* 64-bit */
399 #define MAILBOX_RCVRET_CON_IDX_5        0x000002a8 /* 64-bit */
400 #define MAILBOX_RCVRET_CON_IDX_6        0x000002b0 /* 64-bit */
401 #define MAILBOX_RCVRET_CON_IDX_7        0x000002b8 /* 64-bit */
402 #define MAILBOX_RCVRET_CON_IDX_8        0x000002c0 /* 64-bit */
403 #define MAILBOX_RCVRET_CON_IDX_9        0x000002c8 /* 64-bit */
404 #define MAILBOX_RCVRET_CON_IDX_10       0x000002d0 /* 64-bit */
405 #define MAILBOX_RCVRET_CON_IDX_11       0x000002d8 /* 64-bit */
406 #define MAILBOX_RCVRET_CON_IDX_12       0x000002e0 /* 64-bit */
407 #define MAILBOX_RCVRET_CON_IDX_13       0x000002e8 /* 64-bit */
408 #define MAILBOX_RCVRET_CON_IDX_14       0x000002f0 /* 64-bit */
409 #define MAILBOX_RCVRET_CON_IDX_15       0x000002f8 /* 64-bit */
410 #define MAILBOX_SNDHOST_PROD_IDX_0      0x00000300 /* 64-bit */
411 #define MAILBOX_SNDHOST_PROD_IDX_1      0x00000308 /* 64-bit */
412 #define MAILBOX_SNDHOST_PROD_IDX_2      0x00000310 /* 64-bit */
413 #define MAILBOX_SNDHOST_PROD_IDX_3      0x00000318 /* 64-bit */
414 #define MAILBOX_SNDHOST_PROD_IDX_4      0x00000320 /* 64-bit */
415 #define MAILBOX_SNDHOST_PROD_IDX_5      0x00000328 /* 64-bit */
416 #define MAILBOX_SNDHOST_PROD_IDX_6      0x00000330 /* 64-bit */
417 #define MAILBOX_SNDHOST_PROD_IDX_7      0x00000338 /* 64-bit */
418 #define MAILBOX_SNDHOST_PROD_IDX_8      0x00000340 /* 64-bit */
419 #define MAILBOX_SNDHOST_PROD_IDX_9      0x00000348 /* 64-bit */
420 #define MAILBOX_SNDHOST_PROD_IDX_10     0x00000350 /* 64-bit */
421 #define MAILBOX_SNDHOST_PROD_IDX_11     0x00000358 /* 64-bit */
422 #define MAILBOX_SNDHOST_PROD_IDX_12     0x00000360 /* 64-bit */
423 #define MAILBOX_SNDHOST_PROD_IDX_13     0x00000368 /* 64-bit */
424 #define MAILBOX_SNDHOST_PROD_IDX_14     0x00000370 /* 64-bit */
425 #define MAILBOX_SNDHOST_PROD_IDX_15     0x00000378 /* 64-bit */
426 #define MAILBOX_SNDNIC_PROD_IDX_0       0x00000380 /* 64-bit */
427 #define MAILBOX_SNDNIC_PROD_IDX_1       0x00000388 /* 64-bit */
428 #define MAILBOX_SNDNIC_PROD_IDX_2       0x00000390 /* 64-bit */
429 #define MAILBOX_SNDNIC_PROD_IDX_3       0x00000398 /* 64-bit */
430 #define MAILBOX_SNDNIC_PROD_IDX_4       0x000003a0 /* 64-bit */
431 #define MAILBOX_SNDNIC_PROD_IDX_5       0x000003a8 /* 64-bit */
432 #define MAILBOX_SNDNIC_PROD_IDX_6       0x000003b0 /* 64-bit */
433 #define MAILBOX_SNDNIC_PROD_IDX_7       0x000003b8 /* 64-bit */
434 #define MAILBOX_SNDNIC_PROD_IDX_8       0x000003c0 /* 64-bit */
435 #define MAILBOX_SNDNIC_PROD_IDX_9       0x000003c8 /* 64-bit */
436 #define MAILBOX_SNDNIC_PROD_IDX_10      0x000003d0 /* 64-bit */
437 #define MAILBOX_SNDNIC_PROD_IDX_11      0x000003d8 /* 64-bit */
438 #define MAILBOX_SNDNIC_PROD_IDX_12      0x000003e0 /* 64-bit */
439 #define MAILBOX_SNDNIC_PROD_IDX_13      0x000003e8 /* 64-bit */
440 #define MAILBOX_SNDNIC_PROD_IDX_14      0x000003f0 /* 64-bit */
441 #define MAILBOX_SNDNIC_PROD_IDX_15      0x000003f8 /* 64-bit */
442
443 /* MAC control registers */
444 #define MAC_MODE                        0x00000400
445 #define  MAC_MODE_RESET                  0x00000001
446 #define  MAC_MODE_HALF_DUPLEX            0x00000002
447 #define  MAC_MODE_PORT_MODE_MASK         0x0000000c
448 #define  MAC_MODE_PORT_MODE_TBI          0x0000000c
449 #define  MAC_MODE_PORT_MODE_GMII         0x00000008
450 #define  MAC_MODE_PORT_MODE_MII          0x00000004
451 #define  MAC_MODE_PORT_MODE_NONE         0x00000000
452 #define  MAC_MODE_PORT_INT_LPBACK        0x00000010
453 #define  MAC_MODE_TAGGED_MAC_CTRL        0x00000080
454 #define  MAC_MODE_TX_BURSTING            0x00000100
455 #define  MAC_MODE_MAX_DEFER              0x00000200
456 #define  MAC_MODE_LINK_POLARITY          0x00000400
457 #define  MAC_MODE_RXSTAT_ENABLE          0x00000800
458 #define  MAC_MODE_RXSTAT_CLEAR           0x00001000
459 #define  MAC_MODE_RXSTAT_FLUSH           0x00002000
460 #define  MAC_MODE_TXSTAT_ENABLE          0x00004000
461 #define  MAC_MODE_TXSTAT_CLEAR           0x00008000
462 #define  MAC_MODE_TXSTAT_FLUSH           0x00010000
463 #define  MAC_MODE_SEND_CONFIGS           0x00020000
464 #define  MAC_MODE_MAGIC_PKT_ENABLE       0x00040000
465 #define  MAC_MODE_ACPI_ENABLE            0x00080000
466 #define  MAC_MODE_MIP_ENABLE             0x00100000
467 #define  MAC_MODE_TDE_ENABLE             0x00200000
468 #define  MAC_MODE_RDE_ENABLE             0x00400000
469 #define  MAC_MODE_FHDE_ENABLE            0x00800000
470 #define MAC_STATUS                      0x00000404
471 #define  MAC_STATUS_PCS_SYNCED           0x00000001
472 #define  MAC_STATUS_SIGNAL_DET           0x00000002
473 #define  MAC_STATUS_RCVD_CFG             0x00000004
474 #define  MAC_STATUS_CFG_CHANGED          0x00000008
475 #define  MAC_STATUS_SYNC_CHANGED         0x00000010
476 #define  MAC_STATUS_PORT_DEC_ERR         0x00000400
477 #define  MAC_STATUS_LNKSTATE_CHANGED     0x00001000
478 #define  MAC_STATUS_MI_COMPLETION        0x00400000
479 #define  MAC_STATUS_MI_INTERRUPT         0x00800000
480 #define  MAC_STATUS_AP_ERROR             0x01000000
481 #define  MAC_STATUS_ODI_ERROR            0x02000000
482 #define  MAC_STATUS_RXSTAT_OVERRUN       0x04000000
483 #define  MAC_STATUS_TXSTAT_OVERRUN       0x08000000
484 #define MAC_EVENT                       0x00000408
485 #define  MAC_EVENT_PORT_DECODE_ERR       0x00000400
486 #define  MAC_EVENT_LNKSTATE_CHANGED      0x00001000
487 #define  MAC_EVENT_MI_COMPLETION         0x00400000
488 #define  MAC_EVENT_MI_INTERRUPT          0x00800000
489 #define  MAC_EVENT_AP_ERROR              0x01000000
490 #define  MAC_EVENT_ODI_ERROR             0x02000000
491 #define  MAC_EVENT_RXSTAT_OVERRUN        0x04000000
492 #define  MAC_EVENT_TXSTAT_OVERRUN        0x08000000
493 #define MAC_LED_CTRL                    0x0000040c
494 #define  LED_CTRL_LNKLED_OVERRIDE        0x00000001
495 #define  LED_CTRL_1000MBPS_ON            0x00000002
496 #define  LED_CTRL_100MBPS_ON             0x00000004
497 #define  LED_CTRL_10MBPS_ON              0x00000008
498 #define  LED_CTRL_TRAFFIC_OVERRIDE       0x00000010
499 #define  LED_CTRL_TRAFFIC_BLINK          0x00000020
500 #define  LED_CTRL_TRAFFIC_LED            0x00000040
501 #define  LED_CTRL_1000MBPS_STATUS        0x00000080
502 #define  LED_CTRL_100MBPS_STATUS         0x00000100
503 #define  LED_CTRL_10MBPS_STATUS          0x00000200
504 #define  LED_CTRL_TRAFFIC_STATUS         0x00000400
505 #define  LED_CTRL_MAC_MODE               0x00000000
506 #define  LED_CTRL_PHY_MODE_1             0x00000800
507 #define  LED_CTRL_PHY_MODE_2             0x00001000
508 #define  LED_CTRL_BLINK_RATE_MASK        0x7ff80000
509 #define  LED_CTRL_BLINK_RATE_SHIFT       19
510 #define  LED_CTRL_BLINK_PER_OVERRIDE     0x00080000
511 #define  LED_CTRL_BLINK_RATE_OVERRIDE    0x80000000
512 #define MAC_ADDR_0_HIGH                 0x00000410 /* upper 2 bytes */
513 #define MAC_ADDR_0_LOW                  0x00000414 /* lower 4 bytes */
514 #define MAC_ADDR_1_HIGH                 0x00000418 /* upper 2 bytes */
515 #define MAC_ADDR_1_LOW                  0x0000041c /* lower 4 bytes */
516 #define MAC_ADDR_2_HIGH                 0x00000420 /* upper 2 bytes */
517 #define MAC_ADDR_2_LOW                  0x00000424 /* lower 4 bytes */
518 #define MAC_ADDR_3_HIGH                 0x00000428 /* upper 2 bytes */
519 #define MAC_ADDR_3_LOW                  0x0000042c /* lower 4 bytes */
520 #define MAC_ACPI_MBUF_PTR               0x00000430
521 #define MAC_ACPI_LEN_OFFSET             0x00000434
522 #define  ACPI_LENOFF_LEN_MASK            0x0000ffff
523 #define  ACPI_LENOFF_LEN_SHIFT           0
524 #define  ACPI_LENOFF_OFF_MASK            0x0fff0000
525 #define  ACPI_LENOFF_OFF_SHIFT           16
526 #define MAC_TX_BACKOFF_SEED             0x00000438
527 #define  TX_BACKOFF_SEED_MASK            0x000003ff
528 #define MAC_RX_MTU_SIZE                 0x0000043c
529 #define  RX_MTU_SIZE_MASK                0x0000ffff
530 #define MAC_PCS_TEST                    0x00000440
531 #define  PCS_TEST_PATTERN_MASK           0x000fffff
532 #define  PCS_TEST_PATTERN_SHIFT          0
533 #define  PCS_TEST_ENABLE                 0x00100000
534 #define MAC_TX_AUTO_NEG                 0x00000444
535 #define  TX_AUTO_NEG_MASK                0x0000ffff
536 #define  TX_AUTO_NEG_SHIFT               0
537 #define MAC_RX_AUTO_NEG                 0x00000448
538 #define  RX_AUTO_NEG_MASK                0x0000ffff
539 #define  RX_AUTO_NEG_SHIFT               0
540 #define MAC_MI_COM                      0x0000044c
541 #define  MI_COM_CMD_MASK                 0x0c000000
542 #define  MI_COM_CMD_WRITE                0x04000000
543 #define  MI_COM_CMD_READ                 0x08000000
544 #define  MI_COM_READ_FAILED              0x10000000
545 #define  MI_COM_START                    0x20000000
546 #define  MI_COM_BUSY                     0x20000000
547 #define  MI_COM_PHY_ADDR_MASK            0x03e00000
548 #define  MI_COM_PHY_ADDR_SHIFT           21
549 #define  MI_COM_REG_ADDR_MASK            0x001f0000
550 #define  MI_COM_REG_ADDR_SHIFT           16
551 #define  MI_COM_DATA_MASK                0x0000ffff
552 #define MAC_MI_STAT                     0x00000450
553 #define  MAC_MI_STAT_LNKSTAT_ATTN_ENAB   0x00000001
554 #define MAC_MI_MODE                     0x00000454
555 #define  MAC_MI_MODE_CLK_10MHZ           0x00000001
556 #define  MAC_MI_MODE_SHORT_PREAMBLE      0x00000002
557 #define  MAC_MI_MODE_AUTO_POLL           0x00000010
558 #define  MAC_MI_MODE_CORE_CLK_62MHZ      0x00008000
559 #define  MAC_MI_MODE_BASE                0x000c0000 /* XXX magic values XXX */
560 #define MAC_AUTO_POLL_STATUS            0x00000458
561 #define  MAC_AUTO_POLL_ERROR             0x00000001
562 #define MAC_TX_MODE                     0x0000045c
563 #define  TX_MODE_RESET                   0x00000001
564 #define  TX_MODE_ENABLE                  0x00000002
565 #define  TX_MODE_FLOW_CTRL_ENABLE        0x00000010
566 #define  TX_MODE_BIG_BCKOFF_ENABLE       0x00000020
567 #define  TX_MODE_LONG_PAUSE_ENABLE       0x00000040
568 #define MAC_TX_STATUS                   0x00000460
569 #define  TX_STATUS_XOFFED                0x00000001
570 #define  TX_STATUS_SENT_XOFF             0x00000002
571 #define  TX_STATUS_SENT_XON              0x00000004
572 #define  TX_STATUS_LINK_UP               0x00000008
573 #define  TX_STATUS_ODI_UNDERRUN          0x00000010
574 #define  TX_STATUS_ODI_OVERRUN           0x00000020
575 #define MAC_TX_LENGTHS                  0x00000464
576 #define  TX_LENGTHS_SLOT_TIME_MASK       0x000000ff
577 #define  TX_LENGTHS_SLOT_TIME_SHIFT      0
578 #define  TX_LENGTHS_IPG_MASK             0x00000f00
579 #define  TX_LENGTHS_IPG_SHIFT            8
580 #define  TX_LENGTHS_IPG_CRS_MASK         0x00003000
581 #define  TX_LENGTHS_IPG_CRS_SHIFT        12
582 #define MAC_RX_MODE                     0x00000468
583 #define  RX_MODE_RESET                   0x00000001
584 #define  RX_MODE_ENABLE                  0x00000002
585 #define  RX_MODE_FLOW_CTRL_ENABLE        0x00000004
586 #define  RX_MODE_KEEP_MAC_CTRL           0x00000008
587 #define  RX_MODE_KEEP_PAUSE              0x00000010
588 #define  RX_MODE_ACCEPT_OVERSIZED        0x00000020
589 #define  RX_MODE_ACCEPT_RUNTS            0x00000040
590 #define  RX_MODE_LEN_CHECK               0x00000080
591 #define  RX_MODE_PROMISC                 0x00000100
592 #define  RX_MODE_NO_CRC_CHECK            0x00000200
593 #define  RX_MODE_KEEP_VLAN_TAG           0x00000400
594 #define MAC_RX_STATUS                   0x0000046c
595 #define  RX_STATUS_REMOTE_TX_XOFFED      0x00000001
596 #define  RX_STATUS_XOFF_RCVD             0x00000002
597 #define  RX_STATUS_XON_RCVD              0x00000004
598 #define MAC_HASH_REG_0                  0x00000470
599 #define MAC_HASH_REG_1                  0x00000474
600 #define MAC_HASH_REG_2                  0x00000478
601 #define MAC_HASH_REG_3                  0x0000047c
602 #define MAC_RCV_RULE_0                  0x00000480
603 #define MAC_RCV_VALUE_0                 0x00000484
604 #define MAC_RCV_RULE_1                  0x00000488
605 #define MAC_RCV_VALUE_1                 0x0000048c
606 #define MAC_RCV_RULE_2                  0x00000490
607 #define MAC_RCV_VALUE_2                 0x00000494
608 #define MAC_RCV_RULE_3                  0x00000498
609 #define MAC_RCV_VALUE_3                 0x0000049c
610 #define MAC_RCV_RULE_4                  0x000004a0
611 #define MAC_RCV_VALUE_4                 0x000004a4
612 #define MAC_RCV_RULE_5                  0x000004a8
613 #define MAC_RCV_VALUE_5                 0x000004ac
614 #define MAC_RCV_RULE_6                  0x000004b0
615 #define MAC_RCV_VALUE_6                 0x000004b4
616 #define MAC_RCV_RULE_7                  0x000004b8
617 #define MAC_RCV_VALUE_7                 0x000004bc
618 #define MAC_RCV_RULE_8                  0x000004c0
619 #define MAC_RCV_VALUE_8                 0x000004c4
620 #define MAC_RCV_RULE_9                  0x000004c8
621 #define MAC_RCV_VALUE_9                 0x000004cc
622 #define MAC_RCV_RULE_10                 0x000004d0
623 #define MAC_RCV_VALUE_10                0x000004d4
624 #define MAC_RCV_RULE_11                 0x000004d8
625 #define MAC_RCV_VALUE_11                0x000004dc
626 #define MAC_RCV_RULE_12                 0x000004e0
627 #define MAC_RCV_VALUE_12                0x000004e4
628 #define MAC_RCV_RULE_13                 0x000004e8
629 #define MAC_RCV_VALUE_13                0x000004ec
630 #define MAC_RCV_RULE_14                 0x000004f0
631 #define MAC_RCV_VALUE_14                0x000004f4
632 #define MAC_RCV_RULE_15                 0x000004f8
633 #define MAC_RCV_VALUE_15                0x000004fc
634 #define  RCV_RULE_DISABLE_MASK           0x7fffffff
635 #define MAC_RCV_RULE_CFG                0x00000500
636 #define  RCV_RULE_CFG_DEFAULT_CLASS     0x00000008
637 #define MAC_LOW_WMARK_MAX_RX_FRAME      0x00000504
638 /* 0x508 --> 0x520 unused */
639 #define MAC_HASHREGU_0                  0x00000520
640 #define MAC_HASHREGU_1                  0x00000524
641 #define MAC_HASHREGU_2                  0x00000528
642 #define MAC_HASHREGU_3                  0x0000052c
643 #define MAC_EXTADDR_0_HIGH              0x00000530
644 #define MAC_EXTADDR_0_LOW               0x00000534
645 #define MAC_EXTADDR_1_HIGH              0x00000538
646 #define MAC_EXTADDR_1_LOW               0x0000053c
647 #define MAC_EXTADDR_2_HIGH              0x00000540
648 #define MAC_EXTADDR_2_LOW               0x00000544
649 #define MAC_EXTADDR_3_HIGH              0x00000548
650 #define MAC_EXTADDR_3_LOW               0x0000054c
651 #define MAC_EXTADDR_4_HIGH              0x00000550
652 #define MAC_EXTADDR_4_LOW               0x00000554
653 #define MAC_EXTADDR_5_HIGH              0x00000558
654 #define MAC_EXTADDR_5_LOW               0x0000055c
655 #define MAC_EXTADDR_6_HIGH              0x00000560
656 #define MAC_EXTADDR_6_LOW               0x00000564
657 #define MAC_EXTADDR_7_HIGH              0x00000568
658 #define MAC_EXTADDR_7_LOW               0x0000056c
659 #define MAC_EXTADDR_8_HIGH              0x00000570
660 #define MAC_EXTADDR_8_LOW               0x00000574
661 #define MAC_EXTADDR_9_HIGH              0x00000578
662 #define MAC_EXTADDR_9_LOW               0x0000057c
663 #define MAC_EXTADDR_10_HIGH             0x00000580
664 #define MAC_EXTADDR_10_LOW              0x00000584
665 #define MAC_EXTADDR_11_HIGH             0x00000588
666 #define MAC_EXTADDR_11_LOW              0x0000058c
667 #define MAC_SERDES_CFG                  0x00000590
668 #define MAC_SERDES_STAT                 0x00000594
669 /* 0x598 --> 0x600 unused */
670 #define MAC_TX_MAC_STATE_BASE           0x00000600 /* 16 bytes */
671 #define MAC_RX_MAC_STATE_BASE           0x00000610 /* 20 bytes */
672 /* 0x624 --> 0x800 unused */
673 #define MAC_TX_STATS_OCTETS             0x00000800
674 #define MAC_TX_STATS_RESV1              0x00000804
675 #define MAC_TX_STATS_COLLISIONS         0x00000808
676 #define MAC_TX_STATS_XON_SENT           0x0000080c
677 #define MAC_TX_STATS_XOFF_SENT          0x00000810
678 #define MAC_TX_STATS_RESV2              0x00000814
679 #define MAC_TX_STATS_MAC_ERRORS         0x00000818
680 #define MAC_TX_STATS_SINGLE_COLLISIONS  0x0000081c
681 #define MAC_TX_STATS_MULT_COLLISIONS    0x00000820
682 #define MAC_TX_STATS_DEFERRED           0x00000824
683 #define MAC_TX_STATS_RESV3              0x00000828
684 #define MAC_TX_STATS_EXCESSIVE_COL      0x0000082c
685 #define MAC_TX_STATS_LATE_COL           0x00000830
686 #define MAC_TX_STATS_RESV4_1            0x00000834
687 #define MAC_TX_STATS_RESV4_2            0x00000838
688 #define MAC_TX_STATS_RESV4_3            0x0000083c
689 #define MAC_TX_STATS_RESV4_4            0x00000840
690 #define MAC_TX_STATS_RESV4_5            0x00000844
691 #define MAC_TX_STATS_RESV4_6            0x00000848
692 #define MAC_TX_STATS_RESV4_7            0x0000084c
693 #define MAC_TX_STATS_RESV4_8            0x00000850
694 #define MAC_TX_STATS_RESV4_9            0x00000854
695 #define MAC_TX_STATS_RESV4_10           0x00000858
696 #define MAC_TX_STATS_RESV4_11           0x0000085c
697 #define MAC_TX_STATS_RESV4_12           0x00000860
698 #define MAC_TX_STATS_RESV4_13           0x00000864
699 #define MAC_TX_STATS_RESV4_14           0x00000868
700 #define MAC_TX_STATS_UCAST              0x0000086c
701 #define MAC_TX_STATS_MCAST              0x00000870
702 #define MAC_TX_STATS_BCAST              0x00000874
703 #define MAC_TX_STATS_RESV5_1            0x00000878
704 #define MAC_TX_STATS_RESV5_2            0x0000087c
705 #define MAC_RX_STATS_OCTETS             0x00000880
706 #define MAC_RX_STATS_RESV1              0x00000884
707 #define MAC_RX_STATS_FRAGMENTS          0x00000888
708 #define MAC_RX_STATS_UCAST              0x0000088c
709 #define MAC_RX_STATS_MCAST              0x00000890
710 #define MAC_RX_STATS_BCAST              0x00000894
711 #define MAC_RX_STATS_FCS_ERRORS         0x00000898
712 #define MAC_RX_STATS_ALIGN_ERRORS       0x0000089c
713 #define MAC_RX_STATS_XON_PAUSE_RECVD    0x000008a0
714 #define MAC_RX_STATS_XOFF_PAUSE_RECVD   0x000008a4
715 #define MAC_RX_STATS_MAC_CTRL_RECVD     0x000008a8
716 #define MAC_RX_STATS_XOFF_ENTERED       0x000008ac
717 #define MAC_RX_STATS_FRAME_TOO_LONG     0x000008b0
718 #define MAC_RX_STATS_JABBERS            0x000008b4
719 #define MAC_RX_STATS_UNDERSIZE          0x000008b8
720 /* 0x8bc --> 0xc00 unused */
721
722 /* Send data initiator control registers */
723 #define SNDDATAI_MODE                   0x00000c00
724 #define  SNDDATAI_MODE_RESET             0x00000001
725 #define  SNDDATAI_MODE_ENABLE            0x00000002
726 #define  SNDDATAI_MODE_STAT_OFLOW_ENAB   0x00000004
727 #define SNDDATAI_STATUS                 0x00000c04
728 #define  SNDDATAI_STATUS_STAT_OFLOW      0x00000004
729 #define SNDDATAI_STATSCTRL              0x00000c08
730 #define  SNDDATAI_SCTRL_ENABLE           0x00000001
731 #define  SNDDATAI_SCTRL_FASTUPD          0x00000002
732 #define  SNDDATAI_SCTRL_CLEAR            0x00000004
733 #define  SNDDATAI_SCTRL_FLUSH            0x00000008
734 #define  SNDDATAI_SCTRL_FORCE_ZERO       0x00000010
735 #define SNDDATAI_STATSENAB              0x00000c0c
736 #define SNDDATAI_STATSINCMASK           0x00000c10
737 /* 0xc14 --> 0xc80 unused */
738 #define SNDDATAI_COS_CNT_0              0x00000c80
739 #define SNDDATAI_COS_CNT_1              0x00000c84
740 #define SNDDATAI_COS_CNT_2              0x00000c88
741 #define SNDDATAI_COS_CNT_3              0x00000c8c
742 #define SNDDATAI_COS_CNT_4              0x00000c90
743 #define SNDDATAI_COS_CNT_5              0x00000c94
744 #define SNDDATAI_COS_CNT_6              0x00000c98
745 #define SNDDATAI_COS_CNT_7              0x00000c9c
746 #define SNDDATAI_COS_CNT_8              0x00000ca0
747 #define SNDDATAI_COS_CNT_9              0x00000ca4
748 #define SNDDATAI_COS_CNT_10             0x00000ca8
749 #define SNDDATAI_COS_CNT_11             0x00000cac
750 #define SNDDATAI_COS_CNT_12             0x00000cb0
751 #define SNDDATAI_COS_CNT_13             0x00000cb4
752 #define SNDDATAI_COS_CNT_14             0x00000cb8
753 #define SNDDATAI_COS_CNT_15             0x00000cbc
754 #define SNDDATAI_DMA_RDQ_FULL_CNT       0x00000cc0
755 #define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT  0x00000cc4
756 #define SNDDATAI_SDCQ_FULL_CNT          0x00000cc8
757 #define SNDDATAI_NICRNG_SSND_PIDX_CNT   0x00000ccc
758 #define SNDDATAI_STATS_UPDATED_CNT      0x00000cd0
759 #define SNDDATAI_INTERRUPTS_CNT         0x00000cd4
760 #define SNDDATAI_AVOID_INTERRUPTS_CNT   0x00000cd8
761 #define SNDDATAI_SND_THRESH_HIT_CNT     0x00000cdc
762 /* 0xce0 --> 0x1000 unused */
763
764 /* Send data completion control registers */
765 #define SNDDATAC_MODE                   0x00001000
766 #define  SNDDATAC_MODE_RESET             0x00000001
767 #define  SNDDATAC_MODE_ENABLE            0x00000002
768 /* 0x1004 --> 0x1400 unused */
769
770 /* Send BD ring selector */
771 #define SNDBDS_MODE                     0x00001400
772 #define  SNDBDS_MODE_RESET               0x00000001
773 #define  SNDBDS_MODE_ENABLE              0x00000002
774 #define  SNDBDS_MODE_ATTN_ENABLE         0x00000004
775 #define SNDBDS_STATUS                   0x00001404
776 #define  SNDBDS_STATUS_ERROR_ATTN        0x00000004
777 #define SNDBDS_HWDIAG                   0x00001408
778 /* 0x140c --> 0x1440 */
779 #define SNDBDS_SEL_CON_IDX_0            0x00001440
780 #define SNDBDS_SEL_CON_IDX_1            0x00001444
781 #define SNDBDS_SEL_CON_IDX_2            0x00001448
782 #define SNDBDS_SEL_CON_IDX_3            0x0000144c
783 #define SNDBDS_SEL_CON_IDX_4            0x00001450
784 #define SNDBDS_SEL_CON_IDX_5            0x00001454
785 #define SNDBDS_SEL_CON_IDX_6            0x00001458
786 #define SNDBDS_SEL_CON_IDX_7            0x0000145c
787 #define SNDBDS_SEL_CON_IDX_8            0x00001460
788 #define SNDBDS_SEL_CON_IDX_9            0x00001464
789 #define SNDBDS_SEL_CON_IDX_10           0x00001468
790 #define SNDBDS_SEL_CON_IDX_11           0x0000146c
791 #define SNDBDS_SEL_CON_IDX_12           0x00001470
792 #define SNDBDS_SEL_CON_IDX_13           0x00001474
793 #define SNDBDS_SEL_CON_IDX_14           0x00001478
794 #define SNDBDS_SEL_CON_IDX_15           0x0000147c
795 /* 0x1480 --> 0x1800 unused */
796
797 /* Send BD initiator control registers */
798 #define SNDBDI_MODE                     0x00001800
799 #define  SNDBDI_MODE_RESET               0x00000001
800 #define  SNDBDI_MODE_ENABLE              0x00000002
801 #define  SNDBDI_MODE_ATTN_ENABLE         0x00000004
802 #define SNDBDI_STATUS                   0x00001804
803 #define  SNDBDI_STATUS_ERROR_ATTN        0x00000004
804 #define SNDBDI_IN_PROD_IDX_0            0x00001808
805 #define SNDBDI_IN_PROD_IDX_1            0x0000180c
806 #define SNDBDI_IN_PROD_IDX_2            0x00001810
807 #define SNDBDI_IN_PROD_IDX_3            0x00001814
808 #define SNDBDI_IN_PROD_IDX_4            0x00001818
809 #define SNDBDI_IN_PROD_IDX_5            0x0000181c
810 #define SNDBDI_IN_PROD_IDX_6            0x00001820
811 #define SNDBDI_IN_PROD_IDX_7            0x00001824
812 #define SNDBDI_IN_PROD_IDX_8            0x00001828
813 #define SNDBDI_IN_PROD_IDX_9            0x0000182c
814 #define SNDBDI_IN_PROD_IDX_10           0x00001830
815 #define SNDBDI_IN_PROD_IDX_11           0x00001834
816 #define SNDBDI_IN_PROD_IDX_12           0x00001838
817 #define SNDBDI_IN_PROD_IDX_13           0x0000183c
818 #define SNDBDI_IN_PROD_IDX_14           0x00001840
819 #define SNDBDI_IN_PROD_IDX_15           0x00001844
820 /* 0x1848 --> 0x1c00 unused */
821
822 /* Send BD completion control registers */
823 #define SNDBDC_MODE                     0x00001c00
824 #define SNDBDC_MODE_RESET                0x00000001
825 #define SNDBDC_MODE_ENABLE               0x00000002
826 #define SNDBDC_MODE_ATTN_ENABLE          0x00000004
827 /* 0x1c04 --> 0x2000 unused */
828
829 /* Receive list placement control registers */
830 #define RCVLPC_MODE                     0x00002000
831 #define  RCVLPC_MODE_RESET               0x00000001
832 #define  RCVLPC_MODE_ENABLE              0x00000002
833 #define  RCVLPC_MODE_CLASS0_ATTN_ENAB    0x00000004
834 #define  RCVLPC_MODE_MAPOOR_AATTN_ENAB   0x00000008
835 #define  RCVLPC_MODE_STAT_OFLOW_ENAB     0x00000010
836 #define RCVLPC_STATUS                   0x00002004
837 #define  RCVLPC_STATUS_CLASS0            0x00000004
838 #define  RCVLPC_STATUS_MAPOOR            0x00000008
839 #define  RCVLPC_STATUS_STAT_OFLOW        0x00000010
840 #define RCVLPC_LOCK                     0x00002008
841 #define  RCVLPC_LOCK_REQ_MASK            0x0000ffff
842 #define  RCVLPC_LOCK_REQ_SHIFT           0
843 #define  RCVLPC_LOCK_GRANT_MASK          0xffff0000
844 #define  RCVLPC_LOCK_GRANT_SHIFT         16
845 #define RCVLPC_NON_EMPTY_BITS           0x0000200c
846 #define  RCVLPC_NON_EMPTY_BITS_MASK      0x0000ffff
847 #define RCVLPC_CONFIG                   0x00002010
848 #define RCVLPC_STATSCTRL                0x00002014
849 #define  RCVLPC_STATSCTRL_ENABLE         0x00000001
850 #define  RCVLPC_STATSCTRL_FASTUPD        0x00000002
851 #define RCVLPC_STATS_ENABLE             0x00002018
852 #define  RCVLPC_STATSENAB_LNGBRST_RFIX   0x00400000
853 #define RCVLPC_STATS_INCMASK            0x0000201c
854 /* 0x2020 --> 0x2100 unused */
855 #define RCVLPC_SELLST_BASE              0x00002100 /* 16 16-byte entries */
856 #define  SELLST_TAIL                    0x00000004
857 #define  SELLST_CONT                    0x00000008
858 #define  SELLST_UNUSED                  0x0000000c
859 #define RCVLPC_COS_CNTL_BASE            0x00002200 /* 16 4-byte entries */
860 #define RCVLPC_DROP_FILTER_CNT          0x00002240
861 #define RCVLPC_DMA_WQ_FULL_CNT          0x00002244
862 #define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT   0x00002248
863 #define RCVLPC_NO_RCV_BD_CNT            0x0000224c
864 #define RCVLPC_IN_DISCARDS_CNT          0x00002250
865 #define RCVLPC_IN_ERRORS_CNT            0x00002254
866 #define RCVLPC_RCV_THRESH_HIT_CNT       0x00002258
867 /* 0x225c --> 0x2400 unused */
868
869 /* Receive Data and Receive BD Initiator Control */
870 #define RCVDBDI_MODE                    0x00002400
871 #define  RCVDBDI_MODE_RESET              0x00000001
872 #define  RCVDBDI_MODE_ENABLE             0x00000002
873 #define  RCVDBDI_MODE_JUMBOBD_NEEDED     0x00000004
874 #define  RCVDBDI_MODE_FRM_TOO_BIG        0x00000008
875 #define  RCVDBDI_MODE_INV_RING_SZ        0x00000010
876 #define RCVDBDI_STATUS                  0x00002404
877 #define  RCVDBDI_STATUS_JUMBOBD_NEEDED   0x00000004
878 #define  RCVDBDI_STATUS_FRM_TOO_BIG      0x00000008
879 #define  RCVDBDI_STATUS_INV_RING_SZ      0x00000010
880 #define RCVDBDI_SPLIT_FRAME_MINSZ       0x00002408
881 /* 0x240c --> 0x2440 unused */
882 #define RCVDBDI_JUMBO_BD                0x00002440 /* TG3_BDINFO_... */
883 #define RCVDBDI_STD_BD                  0x00002450 /* TG3_BDINFO_... */
884 #define RCVDBDI_MINI_BD                 0x00002460 /* TG3_BDINFO_... */
885 #define RCVDBDI_JUMBO_CON_IDX           0x00002470
886 #define RCVDBDI_STD_CON_IDX             0x00002474
887 #define RCVDBDI_MINI_CON_IDX            0x00002478
888 /* 0x247c --> 0x2480 unused */
889 #define RCVDBDI_BD_PROD_IDX_0           0x00002480
890 #define RCVDBDI_BD_PROD_IDX_1           0x00002484
891 #define RCVDBDI_BD_PROD_IDX_2           0x00002488
892 #define RCVDBDI_BD_PROD_IDX_3           0x0000248c
893 #define RCVDBDI_BD_PROD_IDX_4           0x00002490
894 #define RCVDBDI_BD_PROD_IDX_5           0x00002494
895 #define RCVDBDI_BD_PROD_IDX_6           0x00002498
896 #define RCVDBDI_BD_PROD_IDX_7           0x0000249c
897 #define RCVDBDI_BD_PROD_IDX_8           0x000024a0
898 #define RCVDBDI_BD_PROD_IDX_9           0x000024a4
899 #define RCVDBDI_BD_PROD_IDX_10          0x000024a8
900 #define RCVDBDI_BD_PROD_IDX_11          0x000024ac
901 #define RCVDBDI_BD_PROD_IDX_12          0x000024b0
902 #define RCVDBDI_BD_PROD_IDX_13          0x000024b4
903 #define RCVDBDI_BD_PROD_IDX_14          0x000024b8
904 #define RCVDBDI_BD_PROD_IDX_15          0x000024bc
905 #define RCVDBDI_HWDIAG                  0x000024c0
906 /* 0x24c4 --> 0x2800 unused */
907
908 /* Receive Data Completion Control */
909 #define RCVDCC_MODE                     0x00002800
910 #define  RCVDCC_MODE_RESET               0x00000001
911 #define  RCVDCC_MODE_ENABLE              0x00000002
912 #define  RCVDCC_MODE_ATTN_ENABLE         0x00000004
913 /* 0x2804 --> 0x2c00 unused */
914
915 /* Receive BD Initiator Control Registers */
916 #define RCVBDI_MODE                     0x00002c00
917 #define  RCVBDI_MODE_RESET               0x00000001
918 #define  RCVBDI_MODE_ENABLE              0x00000002
919 #define  RCVBDI_MODE_RCB_ATTN_ENAB       0x00000004
920 #define RCVBDI_STATUS                   0x00002c04
921 #define  RCVBDI_STATUS_RCB_ATTN          0x00000004
922 #define RCVBDI_JUMBO_PROD_IDX           0x00002c08
923 #define RCVBDI_STD_PROD_IDX             0x00002c0c
924 #define RCVBDI_MINI_PROD_IDX            0x00002c10
925 #define RCVBDI_MINI_THRESH              0x00002c14
926 #define RCVBDI_STD_THRESH               0x00002c18
927 #define RCVBDI_JUMBO_THRESH             0x00002c1c
928 /* 0x2c20 --> 0x3000 unused */
929
930 /* Receive BD Completion Control Registers */
931 #define RCVCC_MODE                      0x00003000
932 #define  RCVCC_MODE_RESET                0x00000001
933 #define  RCVCC_MODE_ENABLE               0x00000002
934 #define  RCVCC_MODE_ATTN_ENABLE          0x00000004
935 #define RCVCC_STATUS                    0x00003004
936 #define  RCVCC_STATUS_ERROR_ATTN         0x00000004
937 #define RCVCC_JUMP_PROD_IDX             0x00003008
938 #define RCVCC_STD_PROD_IDX              0x0000300c
939 #define RCVCC_MINI_PROD_IDX             0x00003010
940 /* 0x3014 --> 0x3400 unused */
941
942 /* Receive list selector control registers */
943 #define RCVLSC_MODE                     0x00003400
944 #define  RCVLSC_MODE_RESET               0x00000001
945 #define  RCVLSC_MODE_ENABLE              0x00000002
946 #define  RCVLSC_MODE_ATTN_ENABLE         0x00000004
947 #define RCVLSC_STATUS                   0x00003404
948 #define  RCVLSC_STATUS_ERROR_ATTN        0x00000004
949 /* 0x3408 --> 0x3800 unused */
950
951 /* Mbuf cluster free registers */
952 #define MBFREE_MODE                     0x00003800
953 #define  MBFREE_MODE_RESET               0x00000001
954 #define  MBFREE_MODE_ENABLE              0x00000002
955 #define MBFREE_STATUS                   0x00003804
956 /* 0x3808 --> 0x3c00 unused */
957
958 /* Host coalescing control registers */
959 #define HOSTCC_MODE                     0x00003c00
960 #define  HOSTCC_MODE_RESET               0x00000001
961 #define  HOSTCC_MODE_ENABLE              0x00000002
962 #define  HOSTCC_MODE_ATTN                0x00000004
963 #define  HOSTCC_MODE_NOW                 0x00000008
964 #define  HOSTCC_MODE_FULL_STATUS         0x00000000
965 #define  HOSTCC_MODE_64BYTE              0x00000080
966 #define  HOSTCC_MODE_32BYTE              0x00000100
967 #define  HOSTCC_MODE_CLRTICK_RXBD        0x00000200
968 #define  HOSTCC_MODE_CLRTICK_TXBD        0x00000400
969 #define  HOSTCC_MODE_NOINT_ON_NOW        0x00000800
970 #define  HOSTCC_MODE_NOINT_ON_FORCE      0x00001000
971 #define HOSTCC_STATUS                   0x00003c04
972 #define  HOSTCC_STATUS_ERROR_ATTN        0x00000004
973 #define HOSTCC_RXCOL_TICKS              0x00003c08
974 #define  LOW_RXCOL_TICKS                 0x00000032
975 #define  DEFAULT_RXCOL_TICKS             0x00000048
976 #define  HIGH_RXCOL_TICKS                0x00000096
977 #define HOSTCC_TXCOL_TICKS              0x00003c0c
978 #define  LOW_TXCOL_TICKS                 0x00000096
979 #define  DEFAULT_TXCOL_TICKS             0x0000012c
980 #define  HIGH_TXCOL_TICKS                0x00000145
981 #define HOSTCC_RXMAX_FRAMES             0x00003c10
982 #define  LOW_RXMAX_FRAMES                0x00000005
983 #define  DEFAULT_RXMAX_FRAMES            0x00000008
984 #define  HIGH_RXMAX_FRAMES               0x00000012
985 #define HOSTCC_TXMAX_FRAMES             0x00003c14
986 #define  LOW_TXMAX_FRAMES                0x00000035
987 #define  DEFAULT_TXMAX_FRAMES            0x0000004b
988 #define  HIGH_TXMAX_FRAMES               0x00000052
989 #define HOSTCC_RXCOAL_TICK_INT          0x00003c18
990 #define  DEFAULT_RXCOAL_TICK_INT         0x00000019
991 #define HOSTCC_TXCOAL_TICK_INT          0x00003c1c
992 #define  DEFAULT_TXCOAL_TICK_INT         0x00000019
993 #define HOSTCC_RXCOAL_MAXF_INT          0x00003c20
994 #define  DEFAULT_RXCOAL_MAXF_INT         0x00000005
995 #define HOSTCC_TXCOAL_MAXF_INT          0x00003c24
996 #define  DEFAULT_TXCOAL_MAXF_INT         0x00000005
997 #define HOSTCC_STAT_COAL_TICKS          0x00003c28
998 #define  DEFAULT_STAT_COAL_TICKS         0x000f4240
999 /* 0x3c2c --> 0x3c30 unused */
1000 #define HOSTCC_STATS_BLK_HOST_ADDR      0x00003c30 /* 64-bit */
1001 #define HOSTCC_STATUS_BLK_HOST_ADDR     0x00003c38 /* 64-bit */
1002 #define HOSTCC_STATS_BLK_NIC_ADDR       0x00003c40
1003 #define HOSTCC_STATUS_BLK_NIC_ADDR      0x00003c44
1004 #define HOSTCC_FLOW_ATTN                0x00003c48
1005 /* 0x3c4c --> 0x3c50 unused */
1006 #define HOSTCC_JUMBO_CON_IDX            0x00003c50
1007 #define HOSTCC_STD_CON_IDX              0x00003c54
1008 #define HOSTCC_MINI_CON_IDX             0x00003c58
1009 /* 0x3c5c --> 0x3c80 unused */
1010 #define HOSTCC_RET_PROD_IDX_0           0x00003c80
1011 #define HOSTCC_RET_PROD_IDX_1           0x00003c84
1012 #define HOSTCC_RET_PROD_IDX_2           0x00003c88
1013 #define HOSTCC_RET_PROD_IDX_3           0x00003c8c
1014 #define HOSTCC_RET_PROD_IDX_4           0x00003c90
1015 #define HOSTCC_RET_PROD_IDX_5           0x00003c94
1016 #define HOSTCC_RET_PROD_IDX_6           0x00003c98
1017 #define HOSTCC_RET_PROD_IDX_7           0x00003c9c
1018 #define HOSTCC_RET_PROD_IDX_8           0x00003ca0
1019 #define HOSTCC_RET_PROD_IDX_9           0x00003ca4
1020 #define HOSTCC_RET_PROD_IDX_10          0x00003ca8
1021 #define HOSTCC_RET_PROD_IDX_11          0x00003cac
1022 #define HOSTCC_RET_PROD_IDX_12          0x00003cb0
1023 #define HOSTCC_RET_PROD_IDX_13          0x00003cb4
1024 #define HOSTCC_RET_PROD_IDX_14          0x00003cb8
1025 #define HOSTCC_RET_PROD_IDX_15          0x00003cbc
1026 #define HOSTCC_SND_CON_IDX_0            0x00003cc0
1027 #define HOSTCC_SND_CON_IDX_1            0x00003cc4
1028 #define HOSTCC_SND_CON_IDX_2            0x00003cc8
1029 #define HOSTCC_SND_CON_IDX_3            0x00003ccc
1030 #define HOSTCC_SND_CON_IDX_4            0x00003cd0
1031 #define HOSTCC_SND_CON_IDX_5            0x00003cd4
1032 #define HOSTCC_SND_CON_IDX_6            0x00003cd8
1033 #define HOSTCC_SND_CON_IDX_7            0x00003cdc
1034 #define HOSTCC_SND_CON_IDX_8            0x00003ce0
1035 #define HOSTCC_SND_CON_IDX_9            0x00003ce4
1036 #define HOSTCC_SND_CON_IDX_10           0x00003ce8
1037 #define HOSTCC_SND_CON_IDX_11           0x00003cec
1038 #define HOSTCC_SND_CON_IDX_12           0x00003cf0
1039 #define HOSTCC_SND_CON_IDX_13           0x00003cf4
1040 #define HOSTCC_SND_CON_IDX_14           0x00003cf8
1041 #define HOSTCC_SND_CON_IDX_15           0x00003cfc
1042 /* 0x3d00 --> 0x4000 unused */
1043
1044 /* Memory arbiter control registers */
1045 #define MEMARB_MODE                     0x00004000
1046 #define  MEMARB_MODE_RESET               0x00000001
1047 #define  MEMARB_MODE_ENABLE              0x00000002
1048 #define MEMARB_STATUS                   0x00004004
1049 #define MEMARB_TRAP_ADDR_LOW            0x00004008
1050 #define MEMARB_TRAP_ADDR_HIGH           0x0000400c
1051 /* 0x4010 --> 0x4400 unused */
1052
1053 /* Buffer manager control registers */
1054 #define BUFMGR_MODE                     0x00004400
1055 #define  BUFMGR_MODE_RESET               0x00000001
1056 #define  BUFMGR_MODE_ENABLE              0x00000002
1057 #define  BUFMGR_MODE_ATTN_ENABLE         0x00000004
1058 #define  BUFMGR_MODE_BM_TEST             0x00000008
1059 #define  BUFMGR_MODE_MBLOW_ATTN_ENAB     0x00000010
1060 #define BUFMGR_STATUS                   0x00004404
1061 #define  BUFMGR_STATUS_ERROR             0x00000004
1062 #define  BUFMGR_STATUS_MBLOW             0x00000010
1063 #define BUFMGR_MB_POOL_ADDR             0x00004408
1064 #define BUFMGR_MB_POOL_SIZE             0x0000440c
1065 #define BUFMGR_MB_RDMA_LOW_WATER        0x00004410
1066 #define  DEFAULT_MB_RDMA_LOW_WATER       0x00000050
1067 #define  DEFAULT_MB_RDMA_LOW_WATER_5705  0x00000000
1068 #define  DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130
1069 #define BUFMGR_MB_MACRX_LOW_WATER       0x00004414
1070 #define  DEFAULT_MB_MACRX_LOW_WATER       0x00000020
1071 #define  DEFAULT_MB_MACRX_LOW_WATER_5705  0x00000010
1072 #define  DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098
1073 #define BUFMGR_MB_HIGH_WATER            0x00004418
1074 #define  DEFAULT_MB_HIGH_WATER           0x00000060
1075 #define  DEFAULT_MB_HIGH_WATER_5705      0x00000060
1076 #define  DEFAULT_MB_HIGH_WATER_JUMBO     0x0000017c
1077 #define BUFMGR_RX_MB_ALLOC_REQ          0x0000441c
1078 #define  BUFMGR_MB_ALLOC_BIT             0x10000000
1079 #define BUFMGR_RX_MB_ALLOC_RESP         0x00004420
1080 #define BUFMGR_TX_MB_ALLOC_REQ          0x00004424
1081 #define BUFMGR_TX_MB_ALLOC_RESP         0x00004428
1082 #define BUFMGR_DMA_DESC_POOL_ADDR       0x0000442c
1083 #define BUFMGR_DMA_DESC_POOL_SIZE       0x00004430
1084 #define BUFMGR_DMA_LOW_WATER            0x00004434
1085 #define  DEFAULT_DMA_LOW_WATER           0x00000005
1086 #define BUFMGR_DMA_HIGH_WATER           0x00004438
1087 #define  DEFAULT_DMA_HIGH_WATER          0x0000000a
1088 #define BUFMGR_RX_DMA_ALLOC_REQ         0x0000443c
1089 #define BUFMGR_RX_DMA_ALLOC_RESP        0x00004440
1090 #define BUFMGR_TX_DMA_ALLOC_REQ         0x00004444
1091 #define BUFMGR_TX_DMA_ALLOC_RESP        0x00004448
1092 #define BUFMGR_HWDIAG_0                 0x0000444c
1093 #define BUFMGR_HWDIAG_1                 0x00004450
1094 #define BUFMGR_HWDIAG_2                 0x00004454
1095 /* 0x4458 --> 0x4800 unused */
1096
1097 /* Read DMA control registers */
1098 #define RDMAC_MODE                      0x00004800
1099 #define  RDMAC_MODE_RESET                0x00000001
1100 #define  RDMAC_MODE_ENABLE               0x00000002
1101 #define  RDMAC_MODE_TGTABORT_ENAB        0x00000004
1102 #define  RDMAC_MODE_MSTABORT_ENAB        0x00000008
1103 #define  RDMAC_MODE_PARITYERR_ENAB       0x00000010
1104 #define  RDMAC_MODE_ADDROFLOW_ENAB       0x00000020
1105 #define  RDMAC_MODE_FIFOOFLOW_ENAB       0x00000040
1106 #define  RDMAC_MODE_FIFOURUN_ENAB        0x00000080
1107 #define  RDMAC_MODE_FIFOOREAD_ENAB       0x00000100
1108 #define  RDMAC_MODE_LNGREAD_ENAB         0x00000200
1109 #define  RDMAC_MODE_SPLIT_ENABLE         0x00000800
1110 #define  RDMAC_MODE_SPLIT_RESET          0x00001000
1111 #define  RDMAC_MODE_FIFO_SIZE_128        0x00020000
1112 #define  RDMAC_MODE_FIFO_LONG_BURST      0x00030000
1113 #define RDMAC_STATUS                    0x00004804
1114 #define  RDMAC_STATUS_TGTABORT           0x00000004
1115 #define  RDMAC_STATUS_MSTABORT           0x00000008
1116 #define  RDMAC_STATUS_PARITYERR          0x00000010
1117 #define  RDMAC_STATUS_ADDROFLOW          0x00000020
1118 #define  RDMAC_STATUS_FIFOOFLOW          0x00000040
1119 #define  RDMAC_STATUS_FIFOURUN           0x00000080
1120 #define  RDMAC_STATUS_FIFOOREAD          0x00000100
1121 #define  RDMAC_STATUS_LNGREAD            0x00000200
1122 /* 0x4808 --> 0x4c00 unused */
1123
1124 /* Write DMA control registers */
1125 #define WDMAC_MODE                      0x00004c00
1126 #define  WDMAC_MODE_RESET                0x00000001
1127 #define  WDMAC_MODE_ENABLE               0x00000002
1128 #define  WDMAC_MODE_TGTABORT_ENAB        0x00000004
1129 #define  WDMAC_MODE_MSTABORT_ENAB        0x00000008
1130 #define  WDMAC_MODE_PARITYERR_ENAB       0x00000010
1131 #define  WDMAC_MODE_ADDROFLOW_ENAB       0x00000020
1132 #define  WDMAC_MODE_FIFOOFLOW_ENAB       0x00000040
1133 #define  WDMAC_MODE_FIFOURUN_ENAB        0x00000080
1134 #define  WDMAC_MODE_FIFOOREAD_ENAB       0x00000100
1135 #define  WDMAC_MODE_LNGREAD_ENAB         0x00000200
1136 #define  WDMAC_MODE_RX_ACCEL             0x00000400
1137 #define WDMAC_STATUS                    0x00004c04
1138 #define  WDMAC_STATUS_TGTABORT           0x00000004
1139 #define  WDMAC_STATUS_MSTABORT           0x00000008
1140 #define  WDMAC_STATUS_PARITYERR          0x00000010
1141 #define  WDMAC_STATUS_ADDROFLOW          0x00000020
1142 #define  WDMAC_STATUS_FIFOOFLOW          0x00000040
1143 #define  WDMAC_STATUS_FIFOURUN           0x00000080
1144 #define  WDMAC_STATUS_FIFOOREAD          0x00000100
1145 #define  WDMAC_STATUS_LNGREAD            0x00000200
1146 /* 0x4c08 --> 0x5000 unused */
1147
1148 /* Per-cpu register offsets (arm9) */
1149 #define CPU_MODE                        0x00000000
1150 #define  CPU_MODE_RESET                  0x00000001
1151 #define  CPU_MODE_HALT                   0x00000400
1152 #define CPU_STATE                       0x00000004
1153 #define CPU_EVTMASK                     0x00000008
1154 /* 0xc --> 0x1c reserved */
1155 #define CPU_PC                          0x0000001c
1156 #define CPU_INSN                        0x00000020
1157 #define CPU_SPAD_UFLOW                  0x00000024
1158 #define CPU_WDOG_CLEAR                  0x00000028
1159 #define CPU_WDOG_VECTOR                 0x0000002c
1160 #define CPU_WDOG_PC                     0x00000030
1161 #define CPU_HW_BP                       0x00000034
1162 /* 0x38 --> 0x44 unused */
1163 #define CPU_WDOG_SAVED_STATE            0x00000044
1164 #define CPU_LAST_BRANCH_ADDR            0x00000048
1165 #define CPU_SPAD_UFLOW_SET              0x0000004c
1166 /* 0x50 --> 0x200 unused */
1167 #define CPU_R0                          0x00000200
1168 #define CPU_R1                          0x00000204
1169 #define CPU_R2                          0x00000208
1170 #define CPU_R3                          0x0000020c
1171 #define CPU_R4                          0x00000210
1172 #define CPU_R5                          0x00000214
1173 #define CPU_R6                          0x00000218
1174 #define CPU_R7                          0x0000021c
1175 #define CPU_R8                          0x00000220
1176 #define CPU_R9                          0x00000224
1177 #define CPU_R10                         0x00000228
1178 #define CPU_R11                         0x0000022c
1179 #define CPU_R12                         0x00000230
1180 #define CPU_R13                         0x00000234
1181 #define CPU_R14                         0x00000238
1182 #define CPU_R15                         0x0000023c
1183 #define CPU_R16                         0x00000240
1184 #define CPU_R17                         0x00000244
1185 #define CPU_R18                         0x00000248
1186 #define CPU_R19                         0x0000024c
1187 #define CPU_R20                         0x00000250
1188 #define CPU_R21                         0x00000254
1189 #define CPU_R22                         0x00000258
1190 #define CPU_R23                         0x0000025c
1191 #define CPU_R24                         0x00000260
1192 #define CPU_R25                         0x00000264
1193 #define CPU_R26                         0x00000268
1194 #define CPU_R27                         0x0000026c
1195 #define CPU_R28                         0x00000270
1196 #define CPU_R29                         0x00000274
1197 #define CPU_R30                         0x00000278
1198 #define CPU_R31                         0x0000027c
1199 /* 0x280 --> 0x400 unused */
1200
1201 #define RX_CPU_BASE                     0x00005000
1202 #define TX_CPU_BASE                     0x00005400
1203
1204 /* Mailboxes */
1205 #define GRCMBOX_INTERRUPT_0             0x00005800 /* 64-bit */
1206 #define GRCMBOX_INTERRUPT_1             0x00005808 /* 64-bit */
1207 #define GRCMBOX_INTERRUPT_2             0x00005810 /* 64-bit */
1208 #define GRCMBOX_INTERRUPT_3             0x00005818 /* 64-bit */
1209 #define GRCMBOX_GENERAL_0               0x00005820 /* 64-bit */
1210 #define GRCMBOX_GENERAL_1               0x00005828 /* 64-bit */
1211 #define GRCMBOX_GENERAL_2               0x00005830 /* 64-bit */
1212 #define GRCMBOX_GENERAL_3               0x00005838 /* 64-bit */
1213 #define GRCMBOX_GENERAL_4               0x00005840 /* 64-bit */
1214 #define GRCMBOX_GENERAL_5               0x00005848 /* 64-bit */
1215 #define GRCMBOX_GENERAL_6               0x00005850 /* 64-bit */
1216 #define GRCMBOX_GENERAL_7               0x00005858 /* 64-bit */
1217 #define GRCMBOX_RELOAD_STAT             0x00005860 /* 64-bit */
1218 #define GRCMBOX_RCVSTD_PROD_IDX         0x00005868 /* 64-bit */
1219 #define GRCMBOX_RCVJUMBO_PROD_IDX       0x00005870 /* 64-bit */
1220 #define GRCMBOX_RCVMINI_PROD_IDX        0x00005878 /* 64-bit */
1221 #define GRCMBOX_RCVRET_CON_IDX_0        0x00005880 /* 64-bit */
1222 #define GRCMBOX_RCVRET_CON_IDX_1        0x00005888 /* 64-bit */
1223 #define GRCMBOX_RCVRET_CON_IDX_2        0x00005890 /* 64-bit */
1224 #define GRCMBOX_RCVRET_CON_IDX_3        0x00005898 /* 64-bit */
1225 #define GRCMBOX_RCVRET_CON_IDX_4        0x000058a0 /* 64-bit */
1226 #define GRCMBOX_RCVRET_CON_IDX_5        0x000058a8 /* 64-bit */
1227 #define GRCMBOX_RCVRET_CON_IDX_6        0x000058b0 /* 64-bit */
1228 #define GRCMBOX_RCVRET_CON_IDX_7        0x000058b8 /* 64-bit */
1229 #define GRCMBOX_RCVRET_CON_IDX_8        0x000058c0 /* 64-bit */
1230 #define GRCMBOX_RCVRET_CON_IDX_9        0x000058c8 /* 64-bit */
1231 #define GRCMBOX_RCVRET_CON_IDX_10       0x000058d0 /* 64-bit */
1232 #define GRCMBOX_RCVRET_CON_IDX_11       0x000058d8 /* 64-bit */
1233 #define GRCMBOX_RCVRET_CON_IDX_12       0x000058e0 /* 64-bit */
1234 #define GRCMBOX_RCVRET_CON_IDX_13       0x000058e8 /* 64-bit */
1235 #define GRCMBOX_RCVRET_CON_IDX_14       0x000058f0 /* 64-bit */
1236 #define GRCMBOX_RCVRET_CON_IDX_15       0x000058f8 /* 64-bit */
1237 #define GRCMBOX_SNDHOST_PROD_IDX_0      0x00005900 /* 64-bit */
1238 #define GRCMBOX_SNDHOST_PROD_IDX_1      0x00005908 /* 64-bit */
1239 #define GRCMBOX_SNDHOST_PROD_IDX_2      0x00005910 /* 64-bit */
1240 #define GRCMBOX_SNDHOST_PROD_IDX_3      0x00005918 /* 64-bit */
1241 #define GRCMBOX_SNDHOST_PROD_IDX_4      0x00005920 /* 64-bit */
1242 #define GRCMBOX_SNDHOST_PROD_IDX_5      0x00005928 /* 64-bit */
1243 #define GRCMBOX_SNDHOST_PROD_IDX_6      0x00005930 /* 64-bit */
1244 #define GRCMBOX_SNDHOST_PROD_IDX_7      0x00005938 /* 64-bit */
1245 #define GRCMBOX_SNDHOST_PROD_IDX_8      0x00005940 /* 64-bit */
1246 #define GRCMBOX_SNDHOST_PROD_IDX_9      0x00005948 /* 64-bit */
1247 #define GRCMBOX_SNDHOST_PROD_IDX_10     0x00005950 /* 64-bit */
1248 #define GRCMBOX_SNDHOST_PROD_IDX_11     0x00005958 /* 64-bit */
1249 #define GRCMBOX_SNDHOST_PROD_IDX_12     0x00005960 /* 64-bit */
1250 #define GRCMBOX_SNDHOST_PROD_IDX_13     0x00005968 /* 64-bit */
1251 #define GRCMBOX_SNDHOST_PROD_IDX_14     0x00005970 /* 64-bit */
1252 #define GRCMBOX_SNDHOST_PROD_IDX_15     0x00005978 /* 64-bit */
1253 #define GRCMBOX_SNDNIC_PROD_IDX_0       0x00005980 /* 64-bit */
1254 #define GRCMBOX_SNDNIC_PROD_IDX_1       0x00005988 /* 64-bit */
1255 #define GRCMBOX_SNDNIC_PROD_IDX_2       0x00005990 /* 64-bit */
1256 #define GRCMBOX_SNDNIC_PROD_IDX_3       0x00005998 /* 64-bit */
1257 #define GRCMBOX_SNDNIC_PROD_IDX_4       0x000059a0 /* 64-bit */
1258 #define GRCMBOX_SNDNIC_PROD_IDX_5       0x000059a8 /* 64-bit */
1259 #define GRCMBOX_SNDNIC_PROD_IDX_6       0x000059b0 /* 64-bit */
1260 #define GRCMBOX_SNDNIC_PROD_IDX_7       0x000059b8 /* 64-bit */
1261 #define GRCMBOX_SNDNIC_PROD_IDX_8       0x000059c0 /* 64-bit */
1262 #define GRCMBOX_SNDNIC_PROD_IDX_9       0x000059c8 /* 64-bit */
1263 #define GRCMBOX_SNDNIC_PROD_IDX_10      0x000059d0 /* 64-bit */
1264 #define GRCMBOX_SNDNIC_PROD_IDX_11      0x000059d8 /* 64-bit */
1265 #define GRCMBOX_SNDNIC_PROD_IDX_12      0x000059e0 /* 64-bit */
1266 #define GRCMBOX_SNDNIC_PROD_IDX_13      0x000059e8 /* 64-bit */
1267 #define GRCMBOX_SNDNIC_PROD_IDX_14      0x000059f0 /* 64-bit */
1268 #define GRCMBOX_SNDNIC_PROD_IDX_15      0x000059f8 /* 64-bit */
1269 #define GRCMBOX_HIGH_PRIO_EV_VECTOR     0x00005a00
1270 #define GRCMBOX_HIGH_PRIO_EV_MASK       0x00005a04
1271 #define GRCMBOX_LOW_PRIO_EV_VEC         0x00005a08
1272 #define GRCMBOX_LOW_PRIO_EV_MASK        0x00005a0c
1273 /* 0x5a10 --> 0x5c00 */
1274
1275 /* Flow Through queues */
1276 #define FTQ_RESET                       0x00005c00
1277 #define FTQ_RESET_DMA_READ_QUEUE        (1 << 1)
1278 #define FTQ_RESET_DMA_HIGH_PRI_READ     (1 << 2)
1279 #define FTQ_RESET_SEND_BD_COMPLETION    (1 << 4)
1280 #define FTQ_RESET_DMA_WRITE             (1 << 6)
1281 #define FTQ_RESET_DMA_HIGH_PRI_WRITE    (1 << 7)
1282 #define FTQ_RESET_SEND_DATA_COMPLETION  (1 << 9)
1283 #define FTQ_RESET_HOST_COALESCING       (1 << 10)
1284 #define FTQ_RESET_MAC_TX                (1 << 11)
1285 #define FTQ_RESET_RX_BD_COMPLETE        (1 << 13)
1286 #define FTQ_RESET_RX_LIST_PLCMT         (1 << 14)
1287 #define FTQ_RESET_RX_DATA_COMPLETION    (1 << 16)
1288 /* 0x5c04 --> 0x5c10 unused */
1289 #define FTQ_DMA_NORM_READ_CTL           0x00005c10
1290 #define FTQ_DMA_NORM_READ_FULL_CNT      0x00005c14
1291 #define FTQ_DMA_NORM_READ_FIFO_ENQDEQ   0x00005c18
1292 #define FTQ_DMA_NORM_READ_WRITE_PEEK    0x00005c1c
1293 #define FTQ_DMA_HIGH_READ_CTL           0x00005c20
1294 #define FTQ_DMA_HIGH_READ_FULL_CNT      0x00005c24
1295 #define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ   0x00005c28
1296 #define FTQ_DMA_HIGH_READ_WRITE_PEEK    0x00005c2c
1297 #define FTQ_DMA_COMP_DISC_CTL           0x00005c30
1298 #define FTQ_DMA_COMP_DISC_FULL_CNT      0x00005c34
1299 #define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ   0x00005c38
1300 #define FTQ_DMA_COMP_DISC_WRITE_PEEK    0x00005c3c
1301 #define FTQ_SEND_BD_COMP_CTL            0x00005c40
1302 #define FTQ_SEND_BD_COMP_FULL_CNT       0x00005c44
1303 #define FTQ_SEND_BD_COMP_FIFO_ENQDEQ    0x00005c48
1304 #define FTQ_SEND_BD_COMP_WRITE_PEEK     0x00005c4c
1305 #define FTQ_SEND_DATA_INIT_CTL          0x00005c50
1306 #define FTQ_SEND_DATA_INIT_FULL_CNT     0x00005c54
1307 #define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ  0x00005c58
1308 #define FTQ_SEND_DATA_INIT_WRITE_PEEK   0x00005c5c
1309 #define FTQ_DMA_NORM_WRITE_CTL          0x00005c60
1310 #define FTQ_DMA_NORM_WRITE_FULL_CNT     0x00005c64
1311 #define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ  0x00005c68
1312 #define FTQ_DMA_NORM_WRITE_WRITE_PEEK   0x00005c6c
1313 #define FTQ_DMA_HIGH_WRITE_CTL          0x00005c70
1314 #define FTQ_DMA_HIGH_WRITE_FULL_CNT     0x00005c74
1315 #define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ  0x00005c78
1316 #define FTQ_DMA_HIGH_WRITE_WRITE_PEEK   0x00005c7c
1317 #define FTQ_SWTYPE1_CTL                 0x00005c80
1318 #define FTQ_SWTYPE1_FULL_CNT            0x00005c84
1319 #define FTQ_SWTYPE1_FIFO_ENQDEQ         0x00005c88
1320 #define FTQ_SWTYPE1_WRITE_PEEK          0x00005c8c
1321 #define FTQ_SEND_DATA_COMP_CTL          0x00005c90
1322 #define FTQ_SEND_DATA_COMP_FULL_CNT     0x00005c94
1323 #define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ  0x00005c98
1324 #define FTQ_SEND_DATA_COMP_WRITE_PEEK   0x00005c9c
1325 #define FTQ_HOST_COAL_CTL               0x00005ca0
1326 #define FTQ_HOST_COAL_FULL_CNT          0x00005ca4
1327 #define FTQ_HOST_COAL_FIFO_ENQDEQ       0x00005ca8
1328 #define FTQ_HOST_COAL_WRITE_PEEK        0x00005cac
1329 #define FTQ_MAC_TX_CTL                  0x00005cb0
1330 #define FTQ_MAC_TX_FULL_CNT             0x00005cb4
1331 #define FTQ_MAC_TX_FIFO_ENQDEQ          0x00005cb8
1332 #define FTQ_MAC_TX_WRITE_PEEK           0x00005cbc
1333 #define FTQ_MB_FREE_CTL                 0x00005cc0
1334 #define FTQ_MB_FREE_FULL_CNT            0x00005cc4
1335 #define FTQ_MB_FREE_FIFO_ENQDEQ         0x00005cc8
1336 #define FTQ_MB_FREE_WRITE_PEEK          0x00005ccc
1337 #define FTQ_RCVBD_COMP_CTL              0x00005cd0
1338 #define FTQ_RCVBD_COMP_FULL_CNT         0x00005cd4
1339 #define FTQ_RCVBD_COMP_FIFO_ENQDEQ      0x00005cd8
1340 #define FTQ_RCVBD_COMP_WRITE_PEEK       0x00005cdc
1341 #define FTQ_RCVLST_PLMT_CTL             0x00005ce0
1342 #define FTQ_RCVLST_PLMT_FULL_CNT        0x00005ce4
1343 #define FTQ_RCVLST_PLMT_FIFO_ENQDEQ     0x00005ce8
1344 #define FTQ_RCVLST_PLMT_WRITE_PEEK      0x00005cec
1345 #define FTQ_RCVDATA_INI_CTL             0x00005cf0
1346 #define FTQ_RCVDATA_INI_FULL_CNT        0x00005cf4
1347 #define FTQ_RCVDATA_INI_FIFO_ENQDEQ     0x00005cf8
1348 #define FTQ_RCVDATA_INI_WRITE_PEEK      0x00005cfc
1349 #define FTQ_RCVDATA_COMP_CTL            0x00005d00
1350 #define FTQ_RCVDATA_COMP_FULL_CNT       0x00005d04
1351 #define FTQ_RCVDATA_COMP_FIFO_ENQDEQ    0x00005d08
1352 #define FTQ_RCVDATA_COMP_WRITE_PEEK     0x00005d0c
1353 #define FTQ_SWTYPE2_CTL                 0x00005d10
1354 #define FTQ_SWTYPE2_FULL_CNT            0x00005d14
1355 #define FTQ_SWTYPE2_FIFO_ENQDEQ         0x00005d18
1356 #define FTQ_SWTYPE2_WRITE_PEEK          0x00005d1c
1357 /* 0x5d20 --> 0x6000 unused */
1358
1359 /* Message signaled interrupt registers */
1360 #define MSGINT_MODE                     0x00006000
1361 #define  MSGINT_MODE_RESET               0x00000001
1362 #define  MSGINT_MODE_ENABLE              0x00000002
1363 #define MSGINT_STATUS                   0x00006004
1364 #define MSGINT_FIFO                     0x00006008
1365 /* 0x600c --> 0x6400 unused */
1366
1367 /* DMA completion registers */
1368 #define DMAC_MODE                       0x00006400
1369 #define  DMAC_MODE_RESET                 0x00000001
1370 #define  DMAC_MODE_ENABLE                0x00000002
1371 /* 0x6404 --> 0x6800 unused */
1372
1373 /* GRC registers */
1374 #define GRC_MODE                        0x00006800
1375 #define  GRC_MODE_UPD_ON_COAL           0x00000001
1376 #define  GRC_MODE_BSWAP_NONFRM_DATA     0x00000002
1377 #define  GRC_MODE_WSWAP_NONFRM_DATA     0x00000004
1378 #define  GRC_MODE_BSWAP_DATA            0x00000010
1379 #define  GRC_MODE_WSWAP_DATA            0x00000020
1380 #define  GRC_MODE_SPLITHDR              0x00000100
1381 #define  GRC_MODE_NOFRM_CRACKING        0x00000200
1382 #define  GRC_MODE_INCL_CRC              0x00000400
1383 #define  GRC_MODE_ALLOW_BAD_FRMS        0x00000800
1384 #define  GRC_MODE_NOIRQ_ON_SENDS        0x00002000
1385 #define  GRC_MODE_NOIRQ_ON_RCV          0x00004000
1386 #define  GRC_MODE_FORCE_PCI32BIT        0x00008000
1387 #define  GRC_MODE_HOST_STACKUP          0x00010000
1388 #define  GRC_MODE_HOST_SENDBDS          0x00020000
1389 #define  GRC_MODE_NO_TX_PHDR_CSUM       0x00100000
1390 #define  GRC_MODE_NO_RX_PHDR_CSUM       0x00800000
1391 #define  GRC_MODE_IRQ_ON_TX_CPU_ATTN    0x01000000
1392 #define  GRC_MODE_IRQ_ON_RX_CPU_ATTN    0x02000000
1393 #define  GRC_MODE_IRQ_ON_MAC_ATTN       0x04000000
1394 #define  GRC_MODE_IRQ_ON_DMA_ATTN       0x08000000
1395 #define  GRC_MODE_IRQ_ON_FLOW_ATTN      0x10000000
1396 #define  GRC_MODE_4X_NIC_SEND_RINGS     0x20000000
1397 #define  GRC_MODE_MCAST_FRM_ENABLE      0x40000000
1398 #define GRC_MISC_CFG                    0x00006804
1399 #define  GRC_MISC_CFG_CORECLK_RESET     0x00000001
1400 #define  GRC_MISC_CFG_PRESCALAR_MASK    0x000000fe
1401 #define  GRC_MISC_CFG_PRESCALAR_SHIFT   1
1402 #define  GRC_MISC_CFG_BOARD_ID_MASK     0x0001e000
1403 #define  GRC_MISC_CFG_BOARD_ID_5700     0x0001e000
1404 #define  GRC_MISC_CFG_BOARD_ID_5701     0x00000000
1405 #define  GRC_MISC_CFG_BOARD_ID_5702FE   0x00004000
1406 #define  GRC_MISC_CFG_BOARD_ID_5703     0x00000000
1407 #define  GRC_MISC_CFG_BOARD_ID_5703S    0x00002000
1408 #define  GRC_MISC_CFG_BOARD_ID_5704     0x00000000
1409 #define  GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000
1410 #define  GRC_MISC_CFG_BOARD_ID_5704_A2  0x00008000
1411 #define  GRC_MISC_CFG_BOARD_ID_5788     0x00010000
1412 #define  GRC_MISC_CFG_BOARD_ID_5788M    0x00018000
1413 #define  GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000
1414 #define  GRC_MISC_CFG_KEEP_GPHY_POWER   0x04000000
1415 #define GRC_LOCAL_CTRL                  0x00006808
1416 #define  GRC_LCLCTRL_INT_ACTIVE         0x00000001
1417 #define  GRC_LCLCTRL_CLEARINT           0x00000002
1418 #define  GRC_LCLCTRL_SETINT             0x00000004
1419 #define  GRC_LCLCTRL_INT_ON_ATTN        0x00000008
1420 #define  GRC_LCLCTRL_GPIO_INPUT0        0x00000100
1421 #define  GRC_LCLCTRL_GPIO_INPUT1        0x00000200
1422 #define  GRC_LCLCTRL_GPIO_INPUT2        0x00000400
1423 #define  GRC_LCLCTRL_GPIO_OE0           0x00000800
1424 #define  GRC_LCLCTRL_GPIO_OE1           0x00001000
1425 #define  GRC_LCLCTRL_GPIO_OE2           0x00002000
1426 #define  GRC_LCLCTRL_GPIO_OUTPUT0       0x00004000
1427 #define  GRC_LCLCTRL_GPIO_OUTPUT1       0x00008000
1428 #define  GRC_LCLCTRL_GPIO_OUTPUT2       0x00010000
1429 #define  GRC_LCLCTRL_EXTMEM_ENABLE      0x00020000
1430 #define  GRC_LCLCTRL_MEMSZ_MASK         0x001c0000
1431 #define  GRC_LCLCTRL_MEMSZ_256K         0x00000000
1432 #define  GRC_LCLCTRL_MEMSZ_512K         0x00040000
1433 #define  GRC_LCLCTRL_MEMSZ_1M           0x00080000
1434 #define  GRC_LCLCTRL_MEMSZ_2M           0x000c0000
1435 #define  GRC_LCLCTRL_MEMSZ_4M           0x00100000
1436 #define  GRC_LCLCTRL_MEMSZ_8M           0x00140000
1437 #define  GRC_LCLCTRL_MEMSZ_16M          0x00180000
1438 #define  GRC_LCLCTRL_BANK_SELECT        0x00200000
1439 #define  GRC_LCLCTRL_SSRAM_TYPE         0x00400000
1440 #define  GRC_LCLCTRL_AUTO_SEEPROM       0x01000000
1441 #define GRC_TIMER                       0x0000680c
1442 #define GRC_RX_CPU_EVENT                0x00006810
1443 #define GRC_RX_TIMER_REF                0x00006814
1444 #define GRC_RX_CPU_SEM                  0x00006818
1445 #define GRC_REMOTE_RX_CPU_ATTN          0x0000681c
1446 #define GRC_TX_CPU_EVENT                0x00006820
1447 #define GRC_TX_TIMER_REF                0x00006824
1448 #define GRC_TX_CPU_SEM                  0x00006828
1449 #define GRC_REMOTE_TX_CPU_ATTN          0x0000682c
1450 #define GRC_MEM_POWER_UP                0x00006830 /* 64-bit */
1451 #define GRC_EEPROM_ADDR                 0x00006838
1452 #define  EEPROM_ADDR_WRITE              0x00000000
1453 #define  EEPROM_ADDR_READ               0x80000000
1454 #define  EEPROM_ADDR_COMPLETE           0x40000000
1455 #define  EEPROM_ADDR_FSM_RESET          0x20000000
1456 #define  EEPROM_ADDR_DEVID_MASK         0x1c000000
1457 #define  EEPROM_ADDR_DEVID_SHIFT        26
1458 #define  EEPROM_ADDR_START              0x02000000
1459 #define  EEPROM_ADDR_CLKPERD_SHIFT      16
1460 #define  EEPROM_ADDR_ADDR_MASK          0x0000ffff
1461 #define  EEPROM_ADDR_ADDR_SHIFT         0
1462 #define  EEPROM_DEFAULT_CLOCK_PERIOD    0x60
1463 #define  EEPROM_CHIP_SIZE               (64 * 1024)
1464 #define GRC_EEPROM_DATA                 0x0000683c
1465 #define GRC_EEPROM_CTRL                 0x00006840
1466 #define GRC_MDI_CTRL                    0x00006844
1467 #define GRC_SEEPROM_DELAY               0x00006848
1468 /* 0x684c --> 0x6c00 unused */
1469
1470 /* 0x6c00 --> 0x7000 unused */
1471
1472 /* NVRAM Control registers */
1473 #define NVRAM_CMD                       0x00007000
1474 #define  NVRAM_CMD_RESET                 0x00000001
1475 #define  NVRAM_CMD_DONE                  0x00000008
1476 #define  NVRAM_CMD_GO                    0x00000010
1477 #define  NVRAM_CMD_WR                    0x00000020
1478 #define  NVRAM_CMD_RD                    0x00000000
1479 #define  NVRAM_CMD_ERASE                 0x00000040
1480 #define  NVRAM_CMD_FIRST                 0x00000080
1481 #define  NVRAM_CMD_LAST                  0x00000100
1482 #define NVRAM_STAT                      0x00007004
1483 #define NVRAM_WRDATA                    0x00007008
1484 #define NVRAM_ADDR                      0x0000700c
1485 #define  NVRAM_ADDR_MSK                 0x00ffffff
1486 #define NVRAM_RDDATA                    0x00007010
1487 #define NVRAM_CFG1                      0x00007014
1488 #define  NVRAM_CFG1_FLASHIF_ENAB         0x00000001
1489 #define  NVRAM_CFG1_BUFFERED_MODE        0x00000002
1490 #define  NVRAM_CFG1_PASS_THRU            0x00000004
1491 #define  NVRAM_CFG1_BIT_BANG             0x00000008
1492 #define  NVRAM_CFG1_COMPAT_BYPASS        0x80000000
1493 #define NVRAM_CFG2                      0x00007018
1494 #define NVRAM_CFG3                      0x0000701c
1495 #define NVRAM_SWARB                     0x00007020
1496 #define  SWARB_REQ_SET0                  0x00000001
1497 #define  SWARB_REQ_SET1                  0x00000002
1498 #define  SWARB_REQ_SET2                  0x00000004
1499 #define  SWARB_REQ_SET3                  0x00000008
1500 #define  SWARB_REQ_CLR0                  0x00000010
1501 #define  SWARB_REQ_CLR1                  0x00000020
1502 #define  SWARB_REQ_CLR2                  0x00000040
1503 #define  SWARB_REQ_CLR3                  0x00000080
1504 #define  SWARB_GNT0                      0x00000100
1505 #define  SWARB_GNT1                      0x00000200
1506 #define  SWARB_GNT2                      0x00000400
1507 #define  SWARB_GNT3                      0x00000800
1508 #define  SWARB_REQ0                      0x00001000
1509 #define  SWARB_REQ1                      0x00002000
1510 #define  SWARB_REQ2                      0x00004000
1511 #define  SWARB_REQ3                      0x00008000
1512 #define    NVRAM_BUFFERED_PAGE_SIZE        264
1513 #define    NVRAM_BUFFERED_PAGE_POS         9
1514 /* 0x7024 --> 0x7400 unused */
1515
1516 /* 0x7400 --> 0x8000 unused */
1517
1518 /* 32K Window into NIC internal memory */
1519 #define NIC_SRAM_WIN_BASE               0x00008000
1520
1521 /* Offsets into first 32k of NIC internal memory. */
1522 #define NIC_SRAM_PAGE_ZERO              0x00000000
1523 #define NIC_SRAM_SEND_RCB               0x00000100 /* 16 * TG3_BDINFO_... */
1524 #define NIC_SRAM_RCV_RET_RCB            0x00000200 /* 16 * TG3_BDINFO_... */
1525 #define NIC_SRAM_STATS_BLK              0x00000300
1526 #define NIC_SRAM_STATUS_BLK             0x00000b00
1527
1528 #define NIC_SRAM_FIRMWARE_MBOX          0x00000b50
1529 #define  NIC_SRAM_FIRMWARE_MBOX_MAGIC1   0x4B657654
1530 #define  NIC_SRAM_FIRMWARE_MBOX_MAGIC2   0x4861764b /* !dma on linkchg */
1531
1532 #define NIC_SRAM_DATA_SIG               0x00000b54
1533 #define  NIC_SRAM_DATA_SIG_MAGIC         0x4b657654 /* ascii for 'KevT' */
1534
1535 #define NIC_SRAM_DATA_CFG                       0x00000b58
1536 #define  NIC_SRAM_DATA_CFG_LED_MODE_MASK         0x0000000c
1537 #define  NIC_SRAM_DATA_CFG_LED_MODE_UNKNOWN      0x00000000
1538 #define  NIC_SRAM_DATA_CFG_LED_TRIPLE_SPD        0x00000004
1539 #define  NIC_SRAM_DATA_CFG_LED_OPEN_DRAIN        0x00000004
1540 #define  NIC_SRAM_DATA_CFG_LED_LINK_SPD          0x00000008
1541 #define  NIC_SRAM_DATA_CFG_LED_OUTPUT            0x00000008
1542 #define  NIC_SRAM_DATA_CFG_PHY_TYPE_MASK         0x00000030
1543 #define  NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN      0x00000000
1544 #define  NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER       0x00000010
1545 #define  NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER        0x00000020
1546 #define  NIC_SRAM_DATA_CFG_WOL_ENABLE            0x00000040
1547 #define  NIC_SRAM_DATA_CFG_ASF_ENABLE            0x00000080
1548 #define  NIC_SRAM_DATA_CFG_EEPROM_WP             0x00000100
1549 #define  NIC_SRAM_DATA_CFG_MINI_PCI              0x00001000
1550 #define  NIC_SRAM_DATA_CFG_FIBER_WOL             0x00004000
1551
1552 #define NIC_SRAM_DATA_PHY_ID            0x00000b74
1553 #define  NIC_SRAM_DATA_PHY_ID1_MASK      0xffff0000
1554 #define  NIC_SRAM_DATA_PHY_ID2_MASK      0x0000ffff
1555
1556 #define NIC_SRAM_FW_CMD_MBOX            0x00000b78
1557 #define  FWCMD_NICDRV_ALIVE              0x00000001
1558 #define  FWCMD_NICDRV_PAUSE_FW           0x00000002
1559 #define  FWCMD_NICDRV_IPV4ADDR_CHG       0x00000003
1560 #define  FWCMD_NICDRV_IPV6ADDR_CHG       0x00000004
1561 #define  FWCMD_NICDRV_FIX_DMAR           0x00000005
1562 #define  FWCMD_NICDRV_FIX_DMAW           0x00000006
1563 #define NIC_SRAM_FW_CMD_LEN_MBOX        0x00000b7c
1564 #define NIC_SRAM_FW_CMD_DATA_MBOX       0x00000b80
1565 #define NIC_SRAM_FW_ASF_STATUS_MBOX     0x00000c00
1566 #define NIC_SRAM_FW_DRV_STATE_MBOX      0x00000c04
1567 #define  DRV_STATE_START                 0x00000001
1568 #define  DRV_STATE_UNLOAD                0x00000002
1569 #define  DRV_STATE_WOL                   0x00000003
1570 #define  DRV_STATE_SUSPEND               0x00000004
1571
1572 #define NIC_SRAM_FW_RESET_TYPE_MBOX     0x00000c08
1573
1574 #define NIC_SRAM_MAC_ADDR_HIGH_MBOX     0x00000c14
1575 #define NIC_SRAM_MAC_ADDR_LOW_MBOX      0x00000c18
1576
1577 #define NIC_SRAM_RX_MINI_BUFFER_DESC    0x00001000
1578
1579 #define NIC_SRAM_DMA_DESC_POOL_BASE     0x00002000
1580 #define  NIC_SRAM_DMA_DESC_POOL_SIZE     0x00002000
1581 #define NIC_SRAM_TX_BUFFER_DESC         0x00004000 /* 512 entries */
1582 #define NIC_SRAM_RX_BUFFER_DESC         0x00006000 /* 256 entries */
1583 #define NIC_SRAM_RX_JUMBO_BUFFER_DESC   0x00007000 /* 256 entries */
1584 #define NIC_SRAM_MBUF_POOL_BASE         0x00008000
1585 #define  NIC_SRAM_MBUF_POOL_SIZE96       0x00018000
1586 #define  NIC_SRAM_MBUF_POOL_SIZE64       0x00010000
1587 #define  NIC_SRAM_MBUF_POOL_BASE5705    0x00010000
1588 #define  NIC_SRAM_MBUF_POOL_SIZE5705    0x0000e000
1589
1590 /* Currently this is fixed. */
1591 #define PHY_ADDR                0x01
1592
1593 /* Tigon3 specific PHY MII registers. */
1594 #define  TG3_BMCR_SPEED1000             0x0040
1595
1596 #define MII_TG3_CTRL                    0x09 /* 1000-baseT control register */
1597 #define  MII_TG3_CTRL_ADV_1000_HALF     0x0100
1598 #define  MII_TG3_CTRL_ADV_1000_FULL     0x0200
1599 #define  MII_TG3_CTRL_AS_MASTER         0x0800
1600 #define  MII_TG3_CTRL_ENABLE_AS_MASTER  0x1000
1601
1602 #define MII_TG3_EXT_CTRL                0x10 /* Extended control register */
1603 #define  MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002
1604 #define  MII_TG3_EXT_CTRL_TBI           0x8000
1605
1606 #define MII_TG3_EXT_STAT                0x11 /* Extended status register */
1607 #define  MII_TG3_EXT_STAT_LPASS         0x0100
1608
1609 #define MII_TG3_DSP_RW_PORT             0x15 /* DSP coefficient read/write port */
1610
1611 #define MII_TG3_DSP_ADDRESS             0x17 /* DSP address register */
1612
1613 #define MII_TG3_AUX_CTRL                0x18 /* auxilliary control register */
1614
1615 #define MII_TG3_AUX_STAT                0x19 /* auxilliary status register */
1616 #define MII_TG3_AUX_STAT_LPASS          0x0004
1617 #define MII_TG3_AUX_STAT_SPDMASK        0x0700
1618 #define MII_TG3_AUX_STAT_10HALF         0x0100
1619 #define MII_TG3_AUX_STAT_10FULL         0x0200
1620 #define MII_TG3_AUX_STAT_100HALF        0x0300
1621 #define MII_TG3_AUX_STAT_100_4          0x0400
1622 #define MII_TG3_AUX_STAT_100FULL        0x0500
1623 #define MII_TG3_AUX_STAT_1000HALF       0x0600
1624 #define MII_TG3_AUX_STAT_1000FULL       0x0700
1625
1626 #define MII_TG3_ISTAT                   0x1a /* IRQ status register */
1627 #define MII_TG3_IMASK                   0x1b /* IRQ mask register */
1628
1629 /* ISTAT/IMASK event bits */
1630 #define MII_TG3_INT_LINKCHG             0x0002
1631 #define MII_TG3_INT_SPEEDCHG            0x0004
1632 #define MII_TG3_INT_DUPLEXCHG           0x0008
1633 #define MII_TG3_INT_ANEG_PAGE_RX        0x0400
1634
1635 /* XXX Add this to mii.h */
1636 #ifndef ADVERTISE_PAUSE
1637 #define ADVERTISE_PAUSE_CAP             0x0400
1638 #endif
1639 #ifndef ADVERTISE_PAUSE_ASYM
1640 #define ADVERTISE_PAUSE_ASYM            0x0800
1641 #endif
1642 #ifndef LPA_PAUSE
1643 #define LPA_PAUSE_CAP                   0x0400
1644 #endif
1645 #ifndef LPA_PAUSE_ASYM
1646 #define LPA_PAUSE_ASYM                  0x0800
1647 #endif
1648
1649 /* There are two ways to manage the TX descriptors on the tigon3.
1650  * Either the descriptors are in host DMA'able memory, or they
1651  * exist only in the cards on-chip SRAM.  All 16 send bds are under
1652  * the same mode, they may not be configured individually.
1653  *
1654  * The mode we use is controlled by TG3_FLAG_HOST_TXDS in tp->tg3_flags.
1655  *
1656  * To use host memory TX descriptors:
1657  *      1) Set GRC_MODE_HOST_SENDBDS in GRC_MODE register.
1658  *         Make sure GRC_MODE_4X_NIC_SEND_RINGS is clear.
1659  *      2) Allocate DMA'able memory.
1660  *      3) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
1661  *         a) Set TG3_BDINFO_HOST_ADDR to DMA address of memory
1662  *            obtained in step 2
1663  *         b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC.
1664  *         c) Set len field of TG3_BDINFO_MAXLEN_FLAGS to number
1665  *            of TX descriptors.  Leave flags field clear.
1666  *      4) Access TX descriptors via host memory.  The chip
1667  *         will refetch into local SRAM as needed when producer
1668  *         index mailboxes are updated.
1669  *
1670  * To use on-chip TX descriptors:
1671  *      1) Set GRC_MODE_4X_NIC_SEND_RINGS in GRC_MODE register.
1672  *         Make sure GRC_MODE_HOST_SENDBDS is clear.
1673  *      2) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
1674  *         a) Set TG3_BDINFO_HOST_ADDR to zero.
1675  *         b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC
1676  *         c) TG3_BDINFO_MAXLEN_FLAGS is don't care.
1677  *      3) Access TX descriptors directly in on-chip SRAM
1678  *         using normal {read,write}l().  (and not using
1679  *         pointer dereferencing of ioremap()'d memory like
1680  *         the broken Broadcom driver does)
1681  *
1682  * Note that BDINFO_FLAGS_DISABLED should be set in the flags field of
1683  * TG3_BDINFO_MAXLEN_FLAGS of all unused SEND_RCB indices.
1684  */
1685 struct tg3_tx_buffer_desc {
1686         uint32_t                        addr_hi;
1687         uint32_t                        addr_lo;
1688
1689         uint32_t                        len_flags;
1690 #define TXD_FLAG_TCPUDP_CSUM            0x0001
1691 #define TXD_FLAG_IP_CSUM                0x0002
1692 #define TXD_FLAG_END                    0x0004
1693 #define TXD_FLAG_IP_FRAG                0x0008
1694 #define TXD_FLAG_IP_FRAG_END            0x0010
1695 #define TXD_FLAG_VLAN                   0x0040
1696 #define TXD_FLAG_COAL_NOW               0x0080
1697 #define TXD_FLAG_CPU_PRE_DMA            0x0100
1698 #define TXD_FLAG_CPU_POST_DMA           0x0200
1699 #define TXD_FLAG_ADD_SRC_ADDR           0x1000
1700 #define TXD_FLAG_CHOOSE_SRC_ADDR        0x6000
1701 #define TXD_FLAG_NO_CRC                 0x8000
1702 #define TXD_LEN_SHIFT                   16
1703
1704         uint32_t                        vlan_tag;
1705 #define TXD_VLAN_TAG_SHIFT              0
1706 #define TXD_MSS_SHIFT                   16
1707 };
1708
1709 #define TXD_ADDR                        0x00UL /* 64-bit */
1710 #define TXD_LEN_FLAGS                   0x08UL /* 32-bit (upper 16-bits are len) */
1711 #define TXD_VLAN_TAG                    0x0cUL /* 32-bit (upper 16-bits are tag) */
1712 #define TXD_SIZE                        0x10UL
1713
1714 struct tg3_rx_buffer_desc {
1715         uint32_t                        addr_hi;
1716         uint32_t                        addr_lo;
1717
1718         uint32_t                        idx_len;
1719 #define RXD_IDX_MASK    0xffff0000
1720 #define RXD_IDX_SHIFT   16
1721 #define RXD_LEN_MASK    0x0000ffff
1722 #define RXD_LEN_SHIFT   0
1723
1724         uint32_t                        type_flags;
1725 #define RXD_TYPE_SHIFT  16
1726 #define RXD_FLAGS_SHIFT 0
1727
1728 #define RXD_FLAG_END                    0x0004
1729 #define RXD_FLAG_MINI                   0x0800
1730 #define RXD_FLAG_JUMBO                  0x0020
1731 #define RXD_FLAG_VLAN                   0x0040
1732 #define RXD_FLAG_ERROR                  0x0400
1733 #define RXD_FLAG_IP_CSUM                0x1000
1734 #define RXD_FLAG_TCPUDP_CSUM            0x2000
1735 #define RXD_FLAG_IS_TCP                 0x4000
1736
1737         uint32_t                        ip_tcp_csum;
1738 #define RXD_IPCSUM_MASK         0xffff0000
1739 #define RXD_IPCSUM_SHIFT        16
1740 #define RXD_TCPCSUM_MASK        0x0000ffff
1741 #define RXD_TCPCSUM_SHIFT       0
1742
1743         uint32_t                        err_vlan;
1744
1745 #define RXD_VLAN_MASK                   0x0000ffff
1746
1747 #define RXD_ERR_BAD_CRC                 0x00010000
1748 #define RXD_ERR_COLLISION               0x00020000
1749 #define RXD_ERR_LINK_LOST               0x00040000
1750 #define RXD_ERR_PHY_DECODE              0x00080000
1751 #define RXD_ERR_ODD_NIBBLE_RCVD_MII     0x00100000
1752 #define RXD_ERR_MAC_ABRT                0x00200000
1753 #define RXD_ERR_TOO_SMALL               0x00400000
1754 #define RXD_ERR_NO_RESOURCES            0x00800000
1755 #define RXD_ERR_HUGE_FRAME              0x01000000
1756 #define RXD_ERR_MASK                    0xffff0000
1757
1758         uint32_t                        reserved;
1759         uint32_t                        opaque;
1760 #define RXD_OPAQUE_INDEX_MASK           0x0000ffff
1761 #define RXD_OPAQUE_INDEX_SHIFT          0
1762 #define RXD_OPAQUE_RING_STD             0x00010000
1763 #define RXD_OPAQUE_RING_JUMBO           0x00020000
1764 #define RXD_OPAQUE_RING_MINI            0x00040000
1765 #define RXD_OPAQUE_RING_MASK            0x00070000
1766 };
1767
1768 struct tg3_ext_rx_buffer_desc {
1769         struct {
1770                 uint32_t                addr_hi;
1771                 uint32_t                addr_lo;
1772         }                               addrlist[3];
1773         uint32_t                        len2_len1;
1774         uint32_t                        resv_len3;
1775         struct tg3_rx_buffer_desc       std;
1776 };
1777
1778 /* We only use this when testing out the DMA engine
1779  * at probe time.  This is the internal format of buffer
1780  * descriptors used by the chip at NIC_SRAM_DMA_DESCS.
1781  */
1782 struct tg3_internal_buffer_desc {
1783         uint32_t                        addr_hi;
1784         uint32_t                        addr_lo;
1785         uint32_t                        nic_mbuf;
1786         /* XXX FIX THIS */
1787 #if __BYTE_ORDER == __BIG_ENDIAN
1788         uint16_t                        cqid_sqid;
1789         uint16_t                        len;
1790 #else
1791         uint16_t                        len;
1792         uint16_t                        cqid_sqid;
1793 #endif
1794         uint32_t                        flags;
1795         uint32_t                        __cookie1;
1796         uint32_t                        __cookie2;
1797         uint32_t                        __cookie3;
1798 };
1799
1800 #define TG3_HW_STATUS_SIZE              0x50
1801 struct tg3_hw_status {
1802         uint32_t                        status;
1803 #define SD_STATUS_UPDATED               0x00000001
1804 #define SD_STATUS_LINK_CHG              0x00000002
1805 #define SD_STATUS_ERROR                 0x00000004
1806
1807         uint32_t                        status_tag;
1808
1809 #if __BYTE_ORDER == __BIG_ENDIAN
1810         uint16_t                        rx_consumer;
1811         uint16_t                        rx_jumbo_consumer;
1812 #else
1813         uint16_t                        rx_jumbo_consumer;
1814         uint16_t                        rx_consumer;
1815 #endif
1816
1817 #if __BYTE_ORDER ==  __BIG_ENDIAN
1818         uint16_t                        reserved;
1819         uint16_t                        rx_mini_consumer;
1820 #else
1821         uint16_t                        rx_mini_consumer;
1822         uint16_t                        reserved;
1823 #endif
1824         struct {
1825 #if __BYTE_ORDER ==  __BIG_ENDIAN
1826                 uint16_t                tx_consumer;
1827                 uint16_t                rx_producer;
1828 #else
1829                 uint16_t                rx_producer;
1830                 uint16_t                tx_consumer;
1831 #endif
1832         }                               idx[16];
1833 };
1834
1835 typedef struct {
1836         uint32_t high, low;
1837 } tg3_stat64_t;
1838
1839 struct tg3_hw_stats {
1840         uint8_t                         __reserved0[0x400-0x300];
1841
1842         /* Statistics maintained by Receive MAC. */
1843         tg3_stat64_t                    rx_octets;
1844         uint64_t                        __reserved1;
1845         tg3_stat64_t                    rx_fragments;
1846         tg3_stat64_t                    rx_ucast_packets;
1847         tg3_stat64_t                    rx_mcast_packets;
1848         tg3_stat64_t                    rx_bcast_packets;
1849         tg3_stat64_t                    rx_fcs_errors;
1850         tg3_stat64_t                    rx_align_errors;
1851         tg3_stat64_t                    rx_xon_pause_rcvd;
1852         tg3_stat64_t                    rx_xoff_pause_rcvd;
1853         tg3_stat64_t                    rx_mac_ctrl_rcvd;
1854         tg3_stat64_t                    rx_xoff_entered;
1855         tg3_stat64_t                    rx_frame_too_long_errors;
1856         tg3_stat64_t                    rx_jabbers;
1857         tg3_stat64_t                    rx_undersize_packets;
1858         tg3_stat64_t                    rx_in_length_errors;
1859         tg3_stat64_t                    rx_out_length_errors;
1860         tg3_stat64_t                    rx_64_or_less_octet_packets;
1861         tg3_stat64_t                    rx_65_to_127_octet_packets;
1862         tg3_stat64_t                    rx_128_to_255_octet_packets;
1863         tg3_stat64_t                    rx_256_to_511_octet_packets;
1864         tg3_stat64_t                    rx_512_to_1023_octet_packets;
1865         tg3_stat64_t                    rx_1024_to_1522_octet_packets;
1866         tg3_stat64_t                    rx_1523_to_2047_octet_packets;
1867         tg3_stat64_t                    rx_2048_to_4095_octet_packets;
1868         tg3_stat64_t                    rx_4096_to_8191_octet_packets;
1869         tg3_stat64_t                    rx_8192_to_9022_octet_packets;
1870
1871         uint64_t                        __unused0[37];
1872
1873         /* Statistics maintained by Transmit MAC. */
1874         tg3_stat64_t                    tx_octets;
1875         uint64_t                        __reserved2;
1876         tg3_stat64_t                    tx_collisions;
1877         tg3_stat64_t                    tx_xon_sent;
1878         tg3_stat64_t                    tx_xoff_sent;
1879         tg3_stat64_t                    tx_flow_control;
1880         tg3_stat64_t                    tx_mac_errors;
1881         tg3_stat64_t                    tx_single_collisions;
1882         tg3_stat64_t                    tx_mult_collisions;
1883         tg3_stat64_t                    tx_deferred;
1884         uint64_t                        __reserved3;
1885         tg3_stat64_t                    tx_excessive_collisions;
1886         tg3_stat64_t                    tx_late_collisions;
1887         tg3_stat64_t                    tx_collide_2times;
1888         tg3_stat64_t                    tx_collide_3times;
1889         tg3_stat64_t                    tx_collide_4times;
1890         tg3_stat64_t                    tx_collide_5times;
1891         tg3_stat64_t                    tx_collide_6times;
1892         tg3_stat64_t                    tx_collide_7times;
1893         tg3_stat64_t                    tx_collide_8times;
1894         tg3_stat64_t                    tx_collide_9times;
1895         tg3_stat64_t                    tx_collide_10times;
1896         tg3_stat64_t                    tx_collide_11times;
1897         tg3_stat64_t                    tx_collide_12times;
1898         tg3_stat64_t                    tx_collide_13times;
1899         tg3_stat64_t                    tx_collide_14times;
1900         tg3_stat64_t                    tx_collide_15times;
1901         tg3_stat64_t                    tx_ucast_packets;
1902         tg3_stat64_t                    tx_mcast_packets;
1903         tg3_stat64_t                    tx_bcast_packets;
1904         tg3_stat64_t                    tx_carrier_sense_errors;
1905         tg3_stat64_t                    tx_discards;
1906         tg3_stat64_t                    tx_errors;
1907
1908         uint64_t                        __unused1[31];
1909
1910         /* Statistics maintained by Receive List Placement. */
1911         tg3_stat64_t                    COS_rx_packets[16];
1912         tg3_stat64_t                    COS_rx_filter_dropped;
1913         tg3_stat64_t                    dma_writeq_full;
1914         tg3_stat64_t                    dma_write_prioq_full;
1915         tg3_stat64_t                    rxbds_empty;
1916         tg3_stat64_t                    rx_discards;
1917         tg3_stat64_t                    rx_errors;
1918         tg3_stat64_t                    rx_threshold_hit;
1919
1920         uint64_t                        __unused2[9];
1921
1922         /* Statistics maintained by Send Data Initiator. */
1923         tg3_stat64_t                    COS_out_packets[16];
1924         tg3_stat64_t                    dma_readq_full;
1925         tg3_stat64_t                    dma_read_prioq_full;
1926         tg3_stat64_t                    tx_comp_queue_full;
1927
1928         /* Statistics maintained by Host Coalescing. */
1929         tg3_stat64_t                    ring_set_send_prod_index;
1930         tg3_stat64_t                    ring_status_update;
1931         tg3_stat64_t                    nic_irqs;
1932         tg3_stat64_t                    nic_avoided_irqs;
1933         tg3_stat64_t                    nic_tx_threshold_hit;
1934
1935         uint8_t                         __reserved4[0xb00-0x9c0];
1936 };
1937
1938 enum phy_led_mode {
1939         led_mode_auto,
1940         led_mode_three_link,
1941         led_mode_link10
1942 };
1943
1944 #if 0
1945 /* 'mapping' is superfluous as the chip does not write into
1946  * the tx/rx post rings so we could just fetch it from there.
1947  * But the cache behavior is better how we are doing it now.
1948  */
1949 struct ring_info {
1950         struct sk_buff                  *skb;
1951         DECLARE_PCI_UNMAP_ADDR(mapping)
1952 };
1953
1954 struct tx_ring_info {
1955         struct sk_buff                  *skb;
1956         DECLARE_PCI_UNMAP_ADDR(mapping)
1957         uint32_t                        prev_vlan_tag;
1958 };
1959 #endif
1960
1961 struct tg3_config_info {
1962         uint32_t                        flags;
1963 };
1964
1965 struct tg3_link_config {
1966         /* Describes what we're trying to get. */
1967         uint32_t                        advertising;
1968 #if 0
1969         uint16_t                        speed;
1970         uint8_t                         duplex;
1971         uint8_t                         autoneg;
1972 #define SPEED_INVALID           0xffff
1973 #define DUPLEX_INVALID          0xff
1974 #define AUTONEG_INVALID         0xff
1975 #endif
1976
1977         /* Describes what we actually have. */
1978         uint8_t                         active_speed;
1979         uint8_t                         active_duplex;
1980
1981         /* When we go in and out of low power mode we need
1982          * to swap with this state.
1983          */
1984 #if 0
1985         int                             phy_is_low_power;
1986         uint16_t                        orig_speed;
1987         uint8_t                         orig_duplex;
1988         uint8_t                         orig_autoneg;
1989 #endif
1990 };
1991
1992 struct tg3_bufmgr_config {
1993         uint32_t                mbuf_read_dma_low_water;
1994         uint32_t                mbuf_mac_rx_low_water;
1995         uint32_t                mbuf_high_water;
1996
1997         uint32_t                mbuf_read_dma_low_water_jumbo;
1998         uint32_t                mbuf_mac_rx_low_water_jumbo;
1999         uint32_t                mbuf_high_water_jumbo;
2000
2001         uint32_t                dma_low_water;
2002         uint32_t                dma_high_water;
2003 };
2004
2005 struct tg3 {
2006 #if 0
2007         /* SMP locking strategy:
2008          *
2009          * lock: Held during all operations except TX packet
2010          *       processing.
2011          *
2012          * tx_lock: Held during tg3_start_xmit{,_4gbug} and tg3_tx
2013          *
2014          * If you want to shut up all asynchronous processing you must
2015          * acquire both locks, 'lock' taken before 'tx_lock'.  IRQs must
2016          * be disabled to take 'lock' but only softirq disabling is
2017          * necessary for acquisition of 'tx_lock'.
2018          */
2019         spinlock_t                      lock;
2020         spinlock_t                      tx_lock;
2021 #endif
2022
2023         uint32_t                        tx_prod;
2024 #if 0
2025         uint32_t                        tx_cons;
2026 #endif
2027         uint32_t                        rx_rcb_ptr;
2028         uint32_t                        rx_std_ptr;
2029 #if 0
2030         uint32_t                        rx_jumbo_ptr;
2031         spinlock_t                      indirect_lock;
2032
2033         struct net_device_stats         net_stats;
2034         struct net_device_stats         net_stats_prev;
2035 #endif
2036         unsigned long                   phy_crc_errors;
2037
2038 #if 0
2039         uint32_t                        rx_offset;
2040 #endif
2041         uint32_t                        tg3_flags;
2042 #if 0
2043 #define TG3_FLAG_HOST_TXDS              0x00000001
2044 #endif
2045 #define TG3_FLAG_TXD_MBOX_HWBUG         0x00000002
2046 #define TG3_FLAG_RX_CHECKSUMS           0x00000004
2047 #define TG3_FLAG_USE_LINKCHG_REG        0x00000008
2048 #define TG3_FLAG_USE_MI_INTERRUPT       0x00000010
2049 #define TG3_FLAG_ENABLE_ASF             0x00000020
2050 #define TG3_FLAG_5701_REG_WRITE_BUG     0x00000040
2051 #define TG3_FLAG_POLL_SERDES            0x00000080
2052 #define TG3_FLAG_MBOX_WRITE_REORDER     0x00000100
2053 #define TG3_FLAG_PCIX_TARGET_HWBUG      0x00000200
2054 #define TG3_FLAG_WOL_SPEED_100MB        0x00000400
2055 #define TG3_FLAG_WOL_ENABLE             0x00000800
2056 #define TG3_FLAG_EEPROM_WRITE_PROT      0x00001000
2057 #define TG3_FLAG_NVRAM                  0x00002000
2058 #define TG3_FLAG_NVRAM_BUFFERED         0x00004000
2059 #define TG3_FLAG_RX_PAUSE               0x00008000
2060 #define TG3_FLAG_TX_PAUSE               0x00010000
2061 #define TG3_FLAG_PCIX_MODE              0x00020000
2062 #define TG3_FLAG_PCI_HIGH_SPEED         0x00040000
2063 #define TG3_FLAG_PCI_32BIT              0x00080000
2064 #define TG3_FLAG_NO_TX_PSEUDO_CSUM      0x00100000
2065 #define TG3_FLAG_NO_RX_PSEUDO_CSUM      0x00200000
2066 #define TG3_FLAG_SERDES_WOL_CAP         0x00400000
2067 #define TG3_FLAG_JUMBO_ENABLE           0x00800000
2068 #define TG3_FLAG_10_100_ONLY            0x01000000
2069 #define TG3_FLAG_PAUSE_AUTONEG          0x02000000
2070 #define TG3_FLAG_PAUSE_RX               0x04000000
2071 #define TG3_FLAG_PAUSE_TX               0x08000000
2072 #define TG3_FLAG_BROKEN_CHECKSUMS       0x10000000
2073 #define TG3_FLAG_GOT_SERDES_FLOWCTL     0x20000000
2074 #define TG3_FLAG_SPLIT_MODE             0x40000000
2075 #define TG3_FLAG_INIT_COMPLETE          0x80000000
2076
2077         uint32_t                        tg3_flags2;
2078 #define TG3_FLG2_RESTART_TIMER          0x00000001
2079 #define TG3_FLG2_SUN_5704               0x00000002
2080 #define TG3_FLG2_NO_ETH_WIRE_SPEED      0x00000004
2081 #define TG3_FLG2_IS_5788                0x00000008
2082 #define TG3_FLG2_MAX_RXPEND_64          0x00000010
2083 #define TG3_FLG2_TSO_CAPABLE            0x00000020
2084   // Alf: Hope I'm not breaking anything here !
2085 #define TG3_FLG2_PCI_EXPRESS            0x00000040
2086
2087
2088
2089         uint32_t                        split_mode_max_reqs;
2090 #define SPLIT_MODE_5704_MAX_REQ         3
2091
2092 #if 0
2093         struct timer_list               timer;
2094         uint16_t                        timer_counter;
2095         uint16_t                        timer_multiplier;
2096         uint32_t                        timer_offset;
2097         uint16_t                        asf_counter;
2098         uint16_t                        asf_multiplier;
2099 #endif
2100
2101         struct tg3_link_config          link_config;
2102         struct tg3_bufmgr_config        bufmgr_config;
2103
2104 #if 0
2105         uint32_t                        rx_pending;
2106         uint32_t                        rx_jumbo_pending;
2107         uint32_t                        tx_pending;
2108 #endif
2109
2110         /* cache h/w values, often passed straight to h/w */
2111         uint32_t                        rx_mode;
2112         uint32_t                        tx_mode;
2113         uint32_t                        mac_mode;
2114         uint32_t                        mi_mode;
2115         uint32_t                        misc_host_ctrl;
2116         uint32_t                        grc_mode;
2117         uint32_t                        grc_local_ctrl;
2118         uint32_t                        dma_rwctrl;
2119 #if 0
2120         uint32_t                        coalesce_mode;
2121 #endif
2122
2123         /* PCI block */
2124         uint16_t                        pci_chip_rev_id;
2125 #if 0
2126         uint8_t                         pci_cacheline_sz;
2127         uint8_t                         pci_lat_timer;
2128         uint8_t                         pci_hdr_type;
2129         uint8_t                         pci_bist;
2130 #endif
2131         uint32_t                        pci_cfg_state[64 / sizeof(uint32_t)];
2132
2133         int                             pm_cap;
2134
2135         /* PHY info */
2136         uint32_t                        phy_id;
2137 #define PHY_ID_MASK                     0xfffffff0
2138 #define PHY_ID_BCM5400                  0x60008040
2139 #define PHY_ID_BCM5401                  0x60008050
2140 #define PHY_ID_BCM5411                  0x60008070
2141 #define PHY_ID_BCM5701                  0x60008110
2142 #define PHY_ID_BCM5703                  0x60008160
2143 #define PHY_ID_BCM5704                  0x60008190
2144 #define PHY_ID_BCM5705                  0x600081a0
2145 #define PHY_ID_BCM5750                  0x60008180
2146 #define PHY_ID_BCM5787                  0xbc050ce0
2147 #define PHY_ID_BCM8002                  0x60010140
2148 #define PHY_ID_BCM5751                  0x00206180
2149 #define PHY_ID_SERDES                   0xfeedbee0
2150 #define PHY_ID_INVALID                  0xffffffff
2151 #define PHY_ID_REV_MASK                 0x0000000f
2152 #define PHY_REV_BCM5401_B0              0x1
2153 #define PHY_REV_BCM5401_B2              0x3
2154 #define PHY_REV_BCM5401_C0              0x6
2155 #define PHY_REV_BCM5411_X0              0x1 /* Found on Netgear GA302T */
2156
2157         enum phy_led_mode               led_mode;
2158
2159         char                            board_part_number[24];
2160         uint32_t                        nic_sram_data_cfg;
2161         uint32_t                        pci_clock_ctrl;
2162 #if 0
2163         struct pci_device               *pdev_peer;
2164 #endif
2165
2166         /* This macro assumes the passed PHY ID is already masked
2167          * with PHY_ID_MASK.
2168          */
2169 #define KNOWN_PHY_ID(X)         \
2170         ((X) == PHY_ID_BCM5400 || (X) == PHY_ID_BCM5401 || \
2171          (X) == PHY_ID_BCM5411 || (X) == PHY_ID_BCM5701 || \
2172          (X) == PHY_ID_BCM5703 || (X) == PHY_ID_BCM5704 || \
2173          (X) == PHY_ID_BCM5705 || (X) == PHY_ID_BCM5750 || \
2174          (X) == PHY_ID_BCM5751 || (X) == PHY_ID_BCM5787 || \
2175          (X) == PHY_ID_BCM8002 || (X) == PHY_ID_SERDES)
2176
2177         unsigned long                   regs;
2178         struct pci_device               *pdev;
2179         struct nic                      *nic;
2180 #if 0
2181         struct net_device               *dev;
2182 #endif
2183 #if TG3_VLAN_TAG_USED
2184         struct vlan_group               *vlgrp;
2185 #endif
2186
2187         struct tg3_rx_buffer_desc       *rx_std;
2188 #if 0
2189         struct ring_info                *rx_std_buffers;
2190         dma_addr_t                      rx_std_mapping;
2191         struct tg3_rx_buffer_desc       *rx_jumbo;
2192         struct ring_info                *rx_jumbo_buffers;
2193         dma_addr_t                      rx_jumbo_mapping;
2194 #endif
2195
2196         struct tg3_rx_buffer_desc       *rx_rcb;
2197 #if 0
2198         dma_addr_t                      rx_rcb_mapping;
2199 #endif
2200
2201         /* TX descs are only used if TG3_FLAG_HOST_TXDS is set. */
2202         struct tg3_tx_buffer_desc       *tx_ring;
2203 #if 0
2204         struct tx_ring_info             *tx_buffers;
2205         dma_addr_t                      tx_desc_mapping;
2206 #endif
2207
2208         struct tg3_hw_status            *hw_status;
2209 #if 0
2210         dma_addr_t                      status_mapping;
2211 #endif
2212 #if 0
2213         uint32_t                        msg_enable;
2214 #endif
2215
2216         struct tg3_hw_stats             *hw_stats;
2217 #if 0
2218         dma_addr_t                      stats_mapping;
2219 #endif
2220
2221         int                             carrier_ok;
2222         uint16_t                        subsystem_vendor;
2223         uint16_t                        subsystem_device;
2224 };
2225
2226 #endif /* !(_T3_H) */