0d542b710e0df48c59092c3cd4a27f0b4f4fe879
[people/balajirrao/gpxe.git] / src / drivers / bus / usb / ohci_hcd.c
1 #include <errno.h>
2 #include <stdlib.h>
3 #include <unistd.h>
4 #include <gpxe/usb.h>
5 #include <gpxe/pci.h>
6 #include <gpxe/malloc.h>
7
8 #include <io.h>
9
10 #include "ohci.h"
11
12 int once = 0;
13
14 #define OHCI_INTR_INIT \
15                 (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \
16                 | OHCI_INTR_RD | OHCI_INTR_WDH)
17
18 static void ohci_usb_reset (struct ohci_hcd *ohci)
19 {
20         ohci->hc_control = readl (&ohci->regs->control);
21         ohci->hc_control &= OHCI_CTRL_RWC;
22         writel (ohci->hc_control, &ohci->regs->control);
23 }
24
25 static int ohci_init(struct ohci_hcd *ohci)
26 {
27         mdelay(5000);   
28         if (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
29                 u32 temp;
30
31                 DBG("USB HC TakeOver from BIOS/SMM\n");
32                 /* this timeout is arbitrary.  we make it long, so systems
33                  * depending on usb keyboards may be usable even if the
34                  * BIOS/SMM code seems pretty broken.
35                  */
36                 temp = 500;     /* arbitrary: five seconds */
37
38                 writel (OHCI_INTR_OC, &ohci->regs->intrenable);
39                 writel (OHCI_OCR, &ohci->regs->cmdstatus);
40                 while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
41                         mdelay (10);
42                         if (--temp == 0) {
43                                 DBG ("USB HC takeover failed!"
44                                         "  (BIOS/SMM bug)\n");
45                                 return -EBUSY;
46                         }
47                 }
48         }
49         
50         //mdelay(5000); 
51         ohci_usb_reset (ohci);
52
53         /* Disable HC interrupts */
54         writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
55
56         /* flush the writes, and save key bits like RWC */
57         if (readl (&ohci->regs->control) & OHCI_CTRL_RWC)
58                 ohci->hc_control |= OHCI_CTRL_RWC;
59
60         ohci->num_ports = roothub_a(ohci) & RH_A_NDP;
61         DBG("Num ports = %d\n", ohci->num_ports);
62
63         ohci->hcca = malloc_dma(sizeof(*ohci->hcca), 256);
64         writel(virt_to_bus(ohci->hcca), &ohci->regs->hcca);
65         return 0;
66 }
67
68 /*-------------------------------------------------------------------------*/
69
70 /*
71  * OHCI Root Hub ... the nonsharable stuff
72  */
73
74 #define dbg_port(hc,label,num,temp) \
75         DBG(    "%s roothub.portstatus [%d] " \
76                 "= 0x%08lx%s%s%s%s%s%s%s%s%s%s%s%s\n", \
77                 label, num, temp, \
78                 (temp & RH_PS_PRSC) ? " PRSC" : "", \
79                 (temp & RH_PS_OCIC) ? " OCIC" : "", \
80                 (temp & RH_PS_PSSC) ? " PSSC" : "", \
81                 (temp & RH_PS_PESC) ? " PESC" : "", \
82                 (temp & RH_PS_CSC) ? " CSC" : "", \
83                 \
84                 (temp & RH_PS_LSDA) ? " LSDA" : "", \
85                 (temp & RH_PS_PPS) ? " PPS" : "", \
86                 (temp & RH_PS_PRS) ? " PRS" : "", \
87                 (temp & RH_PS_POCI) ? " POCI" : "", \
88                 (temp & RH_PS_PSS) ? " PSS" : "", \
89                 \
90                 (temp & RH_PS_PES) ? " PES" : "", \
91                 (temp & RH_PS_CCS) ? " CCS" : "" \
92                 );
93
94 /*-------------------------------------------------------------------------*/
95
96 #if 0
97 /* See usb 7.1.7.5:  root hubs must issue at least 50 msec reset signaling,
98  * not necessarily continuous ... to guard against resume signaling.
99  * The short timeout is safe for non-root hubs, and is backward-compatible
100  * with earlier Linux hosts.
101  */
102 #define PORT_RESET_MSEC         50
103
104 static int reset_port (struct ohci_hcd *ohci, int port)
105 {
106         __hc32  *portstat = &ohci->regs->roothub.portstatus [port];
107         uint32_t        temp = 0;
108         int             timeout = 500;
109         
110         temp = readl (portstat);
111         DBG("Resetting port %d\n",port + 1);
112         if (!(temp & RH_PS_CCS))
113                 return -1;
114         if (temp & RH_PS_PRSC)
115                 writel (RH_PS_PRSC, portstat);
116
117         writel(RH_PS_PRS, portstat);
118
119         /* Wait until reset finishes */
120         temp = readl (portstat);
121         while ((temp & RH_PS_PRS) && (timeout > 0)) {
122                 mdelay(10);
123                 timeout -= 10;
124         }
125         mdelay(1);
126         
127         writel(RH_PS_PRSC | RH_PS_CSC, portstat);
128         ///* Now enable the port */
129         dbg_port(ohci, "PORT", port, roothub_portstatus(ohci, port));
130         mdelay(2000);
131 //      writel(roothub_portstatus(ohci, port) | RH_PS_PES, portstat);
132 //      mdelay(1);
133
134         return 0;
135
136 }
137
138 #endif
139
140 #define PORT_RESET_MSEC         50
141
142 /* this timer value might be vendor-specific ... */
143 #define PORT_RESET_HW_MSEC      10
144
145 /* wrap-aware logic morphed from <linux/jiffies.h> */
146 #define tick_before(t1,t2) ((int16_t)(((int16_t)(t1))-((int16_t)(t2))) < 0)
147
148 /* called from some task, normally khubd */
149 static inline int reset_port (struct ohci_hcd *ohci, unsigned port)
150 {
151         __hc32 *portstat = &ohci->regs->roothub.portstatus [port];
152         uint32_t        temp = 0;
153         uint16_t        now = readl(&ohci->regs->fmnumber);
154         uint16_t        reset_done = now + PORT_RESET_MSEC;
155         int             limit_1 = PORT_RESET_MSEC / PORT_RESET_HW_MSEC;
156
157         /* build a "continuous enough" reset signal, with up to
158          * 3msec gap between pulses.  scheduler HZ==100 must work;
159          * this might need to be deadline-scheduled.
160          */
161         do {
162                 int limit_2;
163
164                 /* spin until any current reset finishes */
165                 limit_2 = PORT_RESET_HW_MSEC * 2;
166                 while (--limit_2 >= 0) {
167                         temp = readl(portstat);
168                         /* handle e.g. CardBus eject */
169                         if (temp == ~(uint32_t)0)
170                                 return -1;
171                         if (!(temp & RH_PS_PRS))
172                                 break;
173                         udelay (500);
174                 }
175
176                 /* timeout (a hardware error) has been observed when
177                  * EHCI sets CF while this driver is resetting a port;
178                  * presumably other disconnect paths might do it too.
179                  */
180                 if (limit_2 < 0) {
181                         DBG("port[%d] reset timeout, stat %08lx\n",
182                                 port, temp);
183                         break;
184                 }
185
186                 if (!(temp & RH_PS_CCS))
187                         break;
188                 if (temp & RH_PS_PRSC)
189                         writel(RH_PS_PRSC, portstat);
190
191                 /* start the next reset, sleep till it's probably done */
192                 writel(RH_PS_PRS, portstat);
193                 mdelay(PORT_RESET_HW_MSEC);
194                 now = readl(&ohci->regs->fmnumber);
195         } while (tick_before(now, reset_done) && --limit_1 >= 0);
196
197         /* caller synchronizes using PRSC ... and handles PRS
198          * still being set when this returns.
199          */
200         mdelay(1);
201         dbg_port(ohci, "PORT ", port, roothub_portstatus(ohci, port));
202         return 0;
203 }
204
205 static inline int ohci_reset_port(struct usb_hcd *hcd, int port)
206 {
207         struct ohci_hcd *ohci = hcd_to_ohci(hcd);
208
209         return reset_port(ohci, port);
210         
211 }
212
213 static struct ohci_td * ohci_alloc_td (struct ohci_hcd *hc, struct ohci_ed *ed)
214 {
215         unsigned long   dma;
216         struct ohci_td  *td;
217
218         td = malloc_dma(sizeof(*td), 16);
219         dma = virt_to_bus(td);
220         if (td) {
221                 /* in case hc fetches it, make it look dead */
222                 memset (td, 0, sizeof(*td));
223                 td->hwNextTD = cpu_to_hc32 (hc, dma);
224                 td->dma = dma;
225                 td->ed = ed;
226         }
227         
228
229         return td;
230 }
231
232 static inline void ohci_fill_td (struct ohci_hcd *ohci, struct ohci_td *td,
233                                 uint32_t info, unsigned long data, unsigned int len)
234 {
235         info |= TD_DI_SET(7);
236
237         td->hwINFO = cpu_to_hc32(ohci, info);
238         td->hwCBP = cpu_to_hc32(ohci, data);
239
240         if(data)
241                 td->hwBE = cpu_to_hc32(ohci, data + len - 1);
242         else 
243                 td->hwBE = 0;
244
245         td->len = len;
246
247         td->ed->hwTailP = cpu_to_hc32(ohci, td->dma);
248         wmb();
249
250 }
251
252 static void ohci_free_td(struct ohci_td *td)
253 {
254         free_dma(td, sizeof(*td));
255 }
256
257 static void ohci_free_ed(struct ohci_ed *ed)
258 {
259         free_dma(ed, sizeof(*ed));
260 }
261
262 static struct ohci_ed * ohci_alloc_ed(struct urb *urb, struct ohci_hcd *ohci)
263 {
264         struct ohci_ed *ed;
265         struct ohci_td *td;
266         struct usb_host_endpoint *ep = urb->ep;
267         uint32_t info;
268         int     is_out;
269
270         ed = malloc_dma(sizeof(*ed), 16);
271         ed->dma = virt_to_bus(ed);
272         
273         if (!ed)
274                 goto err_malloc_ed;
275
276         td = ohci_alloc_td(ohci, ed);
277         if (!td)
278                 goto err_malloc_td;
279
280         is_out = (usb_ep_dir(ep) == USB_DIR_OUT);
281         info = urb->udev->devnum;
282
283         ed->dummy_td = td;
284         ed->hwTailP = cpu_to_hc32 (ohci, td->dma);
285         ed->hwHeadP = ed->hwTailP;      /* ED_C, ED_H zeroed */
286
287         info |= (usb_ep_num(ep)) << 7;
288         info |= le16_to_cpu(ep->desc.wMaxPacketSize) << 16;
289         
290 //      if (usb_ep_xfertype(ep) == USB_ENDPOINT_XFER_CONTROL)
291 //              info |= is_out ? ED_OUT : ED_IN;
292
293         ed->hwINFO = cpu_to_hc32(ohci, info);
294
295         INIT_LIST_HEAD(&ed->urbp_list);
296         return ed;
297
298         ohci_free_td(td);
299 err_malloc_td:
300         ohci_free_ed(ed);
301 err_malloc_ed:
302         return NULL;    
303 }
304
305 static void ohci_add_urbp_to_ed(struct ohci_urb_priv *urbp, struct ohci_ed *ed)
306 {
307         list_add_tail(&urbp->list, &ed->urbp_list);
308 }
309
310 //static void ohci_del_urbp_from_ed(struct ohci_urb_priv *urbp)
311 //{
312 //      list_del(&urbp->list);
313 //}
314
315 static void ohci_add_td_to_urbp(struct ohci_td *td, struct ohci_urb_priv *urbp)
316 {
317         list_add_tail(&td->list, &urbp->td_list);
318 }
319
320 static void ohci_del_td_from_urbp(struct ohci_td *td)
321 {
322         list_del(&td->list);
323 }
324
325 static int ohci_submit_bulk(struct urb *urb, struct ohci_ed *ed)
326 {
327         struct ohci_hcd *ohci = hcd_to_ohci(urb->udev->hcd);
328         struct ohci_td *td;
329         unsigned int len = urb->transfer_buffer_length;
330         unsigned long data = urb->transfer_dma;
331         uint32_t *plink;
332         uint32_t info;
333         struct ohci_urb_priv *urbp = urb->hcpriv;
334         int is_out;
335
336         is_out = (usb_ep_dir(urb->ep) == USB_DIR_OUT);
337
338         info = is_out ?
339                 TD_CC | TD_T_TOGGLE | TD_DP_OUT | TD_R:
340                 TD_CC | TD_T_TOGGLE | TD_DP_IN | TD_R;
341
342         urbp->first_td = td = ed->dummy_td;
343         plink = NULL;
344
345         /*
346          * Build the DATA TDs
347          */
348         do {
349                 unsigned int pktsze = 4096;
350                 
351                 if (len <= pktsze) {            /* The last data packet */
352                         pktsze = len;
353                 }
354
355                 if (plink) {
356                         td = ohci_alloc_td(ohci, ed);
357                         if (!td)
358                                 goto err_td_malloc;
359                         *plink = cpu_to_hc32(ohci, td->dma);
360                 }
361
362                 ohci_fill_td(ohci, td, info, data, pktsze);
363                 plink = &td->hwNextTD;
364
365                 data += pktsze;
366                 len -= pktsze;
367         } while (len > 0);
368
369         /*
370          * Build the new dummy TD and activate the old one
371          */
372         td = ohci_alloc_td(ohci, ed);
373         if (!td)
374                 goto err_dummytd_malloc;
375
376         *plink = cpu_to_hc32(ohci, td->dma);
377
378         wmb();
379
380         ed->dummy_td = td;
381         ed->hwTailP = cpu_to_hc32(ohci, td->dma);
382         writel(OHCI_BLF, &ohci->regs->cmdstatus); 
383
384         wmb();
385         
386         return 0;
387
388         ohci_free_td(ed->dummy_td);
389 err_dummytd_malloc:
390         list_for_each_entry(td, &urbp->td_list, list)
391                 ohci_del_td_from_urbp(td);
392 err_td_malloc:
393         list_for_each_entry(td, &urbp->td_list, list)
394                 ohci_del_td_from_urbp(td);
395
396         return -ENOMEM;
397 }
398
399 static int ohci_submit_control(struct urb *urb, struct ohci_ed *ed)
400 {
401         struct ohci_hcd *ohci = hcd_to_ohci(urb->udev->hcd);
402         struct ohci_td *td;
403         unsigned int len = urb->transfer_buffer_length;
404         unsigned long data = urb->transfer_dma;
405         uint32_t *plink;
406         uint32_t info;
407         struct ohci_urb_priv *urbp = urb->hcpriv;
408         int is_out;
409
410         is_out = (usb_ep_dir(urb->ep) == USB_DIR_OUT);
411
412         info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
413         urbp->first_td = td = ed->dummy_td;
414
415         ohci_fill_td(ohci, td, info, urb->setup_dma, 8);
416
417         ohci_add_td_to_urbp(td, urbp);
418         plink = &td->hwNextTD;
419
420         /*
421          * Build the DATA TDs
422          */
423 //      while (len > 0) {
424                 unsigned int pktsze = 4096;
425                 
426                 if (len <= pktsze) {            /* The last data packet */
427                         pktsze = len;
428                 }
429
430                 td = ohci_alloc_td(ohci, ed);
431                 if (!td)
432                         goto err_td_malloc;
433
434                 *plink = cpu_to_hc32(ohci, td->dma);
435
436                 info = TD_CC | TD_R | TD_T_DATA1;
437                 info |= is_out ? TD_DP_OUT : TD_DP_IN;
438                 ohci_fill_td(ohci, td, info, data, pktsze);
439                 plink = &td->hwNextTD;
440
441 //              data += pktsze;
442 //              len -= pktsze;
443 //      }
444
445         /*
446          * Build the final TD for control status 
447          */
448         urbp->last_td = td = ohci_alloc_td(ohci, ed);
449         if (!td) 
450                 goto err_td_malloc;
451
452         *plink = cpu_to_hc32(ohci, td->dma);
453
454         /* Change direction for the status transaction */
455         info = (is_out || (urb->transfer_buffer_length == 0)) ?
456                 TD_CC | TD_DP_IN | TD_T_DATA1:
457                 TD_CC | TD_DP_OUT | TD_T_DATA1;
458
459         ohci_add_td_to_urbp(td, urbp);
460         ohci_fill_td(ohci, td, info, 0, 0);
461         plink = &td->hwNextTD;
462
463         /*
464          * Build the new dummy TD and activate the old one
465          */
466         td = ohci_alloc_td(ohci, ed);
467         if (!td)
468                 goto err_dummytd_malloc;
469
470         *plink = cpu_to_hc32(ohci, td->dma);
471
472         wmb();
473
474         ed->dummy_td = td;
475         ed->hwTailP = cpu_to_hc32(ohci, td->dma);
476         writel(OHCI_CLF, &ohci->regs->cmdstatus); 
477
478         wmb();
479
480         return 0;
481
482         ohci_free_td(ed->dummy_td);
483 err_dummytd_malloc:
484         list_for_each_entry(td, &urbp->td_list, list)
485                 ohci_del_td_from_urbp(td);
486 err_td_malloc:
487         list_for_each_entry(td, &urbp->td_list, list)
488                 ohci_del_td_from_urbp(td);
489
490         return -ENOMEM;
491 }
492
493
494 static int ohci_enqueue_urb(struct usb_hcd *hcd, struct urb *urb)
495 {
496         struct ohci_hcd *ohci;
497         struct ohci_urb_priv *urbp;
498         struct ohci_ed *ed;
499         int ret = -ENOMEM;
500         uint32_t info;
501
502         ohci = hcd_to_ohci(hcd);                
503         urbp = malloc(sizeof(*urbp));
504         
505         if (!urbp)
506                 goto err_urb_malloc;
507
508         INIT_LIST_HEAD(&urbp->td_list);
509         urb->hcpriv = urbp;
510
511         if (!urb->ep->hcpriv) {
512                 /* Create a new ED for this endpoint */
513                 ed = urb->ep->hcpriv = ohci_alloc_ed(urb, ohci);
514                 if (!urb->ep->hcpriv)
515                         goto err_hcpriv_malloc; 
516                 if (usb_ep_xfertype(urb->ep) == USB_ENDPOINT_XFER_CONTROL) {
517                         
518                         /* Check to see if this is the first control ed */
519                         if (!readl(&ohci->regs->ed_controlhead)) {
520                                 writel(0, &ohci->regs->ed_controlcurrent);
521                                 writel(cpu_to_hc32(ohci, ed->dma), &ohci->regs->ed_controlhead);
522                                 ohci->hc_control |= OHCI_CTRL_CLE;
523                                 writel(ohci->hc_control, &ohci->regs->control);
524                         } else {
525                                 ohci->last_control_ed->hwNextED = cpu_to_hc32(ohci, ed->dma);
526                         }
527                         ohci->last_control_ed = ed;
528                 } else {
529                         /* Check to see if this is the first ed */
530                         if (!readl(&ohci->regs->ed_bulkhead)) {
531                                 writel(cpu_to_hc32(ohci, ed->dma), &ohci->regs->ed_bulkhead);
532                                 ohci->hc_control |= OHCI_CTRL_BLE;
533                                 writel(ohci->hc_control, &ohci->regs->control);
534                                 writel(0, &ohci->regs->ed_bulkcurrent);
535                         } else {
536                                 ohci->last_bulk_ed->hwNextED = cpu_to_hc32(ohci, ed->dma);
537                         }
538                         ohci->last_bulk_ed = ed;
539                 }
540
541                                 writel(ohci->hc_control, &ohci->regs->control);
542         }
543         
544         /* Update the ed's fa */
545         ed = (struct ohci_ed *)urb->ep->hcpriv;
546         info = hc32_to_cpu(ohci, ed->hwINFO);
547         info &= ~((1 << 7) - 1);
548         info |= (urb->udev->devnum);
549         ed->hwINFO = cpu_to_hc32(ohci, info);
550
551         /* Add the urbp to the ED's list */
552         ohci_add_urbp_to_ed(urbp, ed);
553         
554         if (usb_ep_xfertype(urb->ep) == USB_ENDPOINT_XFER_CONTROL) {
555                 if ((ret = ohci_submit_control(urb, ed)) < 0)
556                         goto err_submit_urb;
557         } else {
558                 if ((ret = ohci_submit_bulk(urb, ed)) < 0)
559                         goto err_submit_urb;    
560         }
561
562         return 0;
563
564         return ret;
565 err_submit_urb:
566         ohci_free_ed(urb->ep->hcpriv);
567 err_hcpriv_malloc:
568         free(urbp);
569 err_urb_malloc:
570         return ret;
571 }
572 static void ohci_unlink_urb(struct urb *urb __unused)
573 {
574 }
575
576 static int ohci_urb_status(struct urb *urb)
577 {
578         int ret = USB_URB_STATUS_COMPLETE;
579         struct ohci_urb_priv *urbp = urb->hcpriv;
580         struct ohci_td *td;
581         struct list_head *p;
582         struct ohci_hcd *ohci = hcd_to_ohci(urb->udev->hcd);
583         uint32_t info;
584
585         /* Check for the status of the first td *///
586         info = hc32_to_cpu(ohci, urbp->first_td->hwINFO);
587
588         if (TD_CC_GET(info) != 0) {
589                 if (TD_CC_GET(info) == 0xf) {
590                         ret = USB_URB_STATUS_INPROGRESS;
591                         goto out;
592                 } else {
593                         ret = USB_URB_STATUS_ERROR;
594                         goto out;
595                 }
596         }
597
598         /* Check if URB is complete. Update urb->actual_length */
599         /* Optimie by looking at last_td directly. */
600         td = urbp->last_td;
601         info = hc32_to_cpu(ohci, urbp->last_td->hwINFO);
602         
603         if (TD_CC_GET(info) == 0) {
604                 unsigned long be, cbp;
605                 be = hc32_to_cpu(ohci, td->hwBE);
606                 cbp = hc32_to_cpu(ohci, td->hwCBP);
607                 if (cbp == 0) {
608                                 urb->actual_length = urb->transfer_buffer_length;
609                                 return USB_URB_STATUS_COMPLETE;
610                 }
611         }
612
613         urb->actual_length = 0; 
614         list_for_each(p, &urbp->td_list) {
615                 unsigned long cbp, be;
616
617                 td = list_entry(p, struct ohci_td, list);
618                 info = hc32_to_cpu(ohci, td->hwINFO);
619                 cbp = hc32_to_cpu(ohci, td->hwCBP);
620                 be = hc32_to_cpu(ohci, td->hwBE);
621
622                 if (TD_CC_GET(info) != 0) {
623                         ret = USB_URB_STATUS_INPROGRESS;
624                         goto out;
625                 }
626
627                 if (cbp != 0)
628                         urb->actual_length += td->len - (be - cbp);
629                 else
630                         urb->actual_length += td->len;
631         }
632
633 out:
634         return ret;
635 }
636
637 static struct hc_driver ohci_driver = {
638         .urb_status = ohci_urb_status,
639         .enqueue_urb = ohci_enqueue_urb,
640         .reset_port = ohci_reset_port,
641         .unlink_urb = ohci_unlink_urb,
642 };
643
644 static int ohci_start(struct ohci_hcd *ohci)
645 {
646         uint32_t temp, mask;
647
648         temp = readl(&ohci->regs->fminterval);
649         ohci->fminterval = temp & 0x3fff;
650
651         if (ohci->fminterval != FI)
652                 DBG("fminterval delta %lx\n",ohci->fminterval - FI);
653         ohci->fminterval |= FSMP (ohci->fminterval) << 16;
654
655         switch (ohci->hc_control & OHCI_CTRL_HCFS) {
656         case OHCI_USB_OPER:
657                 temp = 0;
658                 break;
659         case OHCI_USB_SUSPEND:
660         case OHCI_USB_RESUME:
661                 ohci->hc_control &= OHCI_CTRL_RWC;
662                 ohci->hc_control |= OHCI_USB_RESUME;
663                 temp = 10 /* msec wait */;
664                 break;
665         // case OHCI_USB_RESET:
666         default:
667                 ohci->hc_control &= OHCI_CTRL_RWC;
668                 ohci->hc_control |= OHCI_USB_RESET;
669                 temp = 50 /* msec wait */;
670                 break;
671         }
672         writel(ohci->hc_control, &ohci->regs->control);
673         // flush the writes
674         (void) readl(&ohci->regs->control);
675         mdelay(temp);
676         
677         /* HC Reset requires max 10 us delay */
678         writel (OHCI_HCR,  &ohci->regs->cmdstatus);
679         temp = 30;      /* ... allow extra time */
680         while ((readl(&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
681                 if (--temp == 0) {
682                         DBG("USB HC reset timed out!\n");
683                         return -1;
684                 }
685                 udelay (1);
686         }
687
688         /* now we're in the SUSPEND state ... must go OPERATIONAL
689          * within 2msec else HC enters RESUME
690          * Tell the controller where the control and bulk lists are
691          * The lists are empty now. 
692          */
693
694         writel(0, &ohci->regs->ed_controlhead);
695         writel(0, &ohci->regs->ed_bulkhead);
696
697         periodic_reinit(ohci);
698
699         ohci->hc_control &= OHCI_CTRL_RWC;
700         ohci->hc_control |= OHCI_CTRL_CBSR | OHCI_USB_OPER;
701         writel(ohci->hc_control, &ohci->regs->control);
702
703         /* wake on ConnectStatusChange, matching external hubs */
704         writel (RH_HS_DRWE, &ohci->regs->roothub.status);
705
706         /* Choose the interrupts we care about now, others later on demand */
707         mask = OHCI_INTR_INIT;
708         writel (~0, &ohci->regs->intrstatus);
709         writel (mask, &ohci->regs->intrenable);
710
711         temp = roothub_a (ohci);
712         writel(RH_HS_LPSC, &ohci->regs->roothub.status);
713         writel((temp & RH_A_NPS) ? 0 : RH_B_PPCM, &ohci->regs->roothub.b);
714
715         // flush those writes
716         (void) readl(&ohci->regs->control);
717
718         return 0;
719 }
720 static int ohci_hcd_pci_probe(struct pci_device *pci,
721                                         const struct pci_device_id *id __unused)
722 {
723         struct usb_hcd *hcd;
724         struct ohci_hcd *ohci;
725         struct usb_device *udev;
726
727         int retval = -ENOMEM;
728         unsigned int port;
729
730         if (pci->class != PCI_CLASS_SERIAL_USB_OHCI)
731                 return -ENOTTY;
732
733 //      if (once == 1)
734 //              return -1;
735
736         once = 1;
737
738         hcd = (struct usb_hcd *) malloc(sizeof(struct usb_hcd));
739         if (!hcd) {
740                 DBG("Failed allocating memory for usb_hcd\n");
741                 goto err_hcd_malloc;
742         }
743
744         ohci = hcd->hcpriv = malloc(sizeof(struct ohci_hcd));
745         if (!hcd->hcpriv) {
746                 DBG("Failed allocating memory for ohci_hcd\n");
747                 goto err_ohci_hcd_malloc;
748         }
749
750         pci_set_drvdata(pci, hcd);
751         hcd->driver = &ohci_driver;
752
753         hcd->res_addr = pci_bar_start(pci, PCI_BASE_ADDRESS_0);
754         hcd->res_size = pci_bar_size(pci, PCI_BASE_ADDRESS_0);
755
756         ohci->regs = ioremap(hcd->res_addr, hcd->res_size);
757         if (ohci->regs == NULL) {
758                 DBG("error mapping memory\n");
759                 retval = -EFAULT;
760                 goto err_ioremap;
761         }
762
763         DBG("OHCI Adapter Found at 0x%lx\n", hcd->res_addr);
764
765         ohci_init(ohci);
766
767         ohci_start(ohci);
768         /* Look for devices at ports */
769 mdelay(100);    
770         for (port = 0; port < ohci->num_ports; port++) {
771                                 dbg_port(ohci, "PORT", port, roothub_portstatus(ohci,  port));
772                 uint32_t status = roothub_portstatus (ohci, port);
773                 if (!(status & RH_PS_CCS)) {
774                         DBG("No device on port %d\n", port + 1);
775                         continue;
776                 }
777                 udev = usb_alloc_dev();
778                 if(!udev)
779                         goto err_usb_alloc_dev;
780                 udev->hcd = hcd;
781                 /* Tell the usb core about the new device */
782                 usb_dev_init(udev, port);
783         }
784
785         return 0;
786
787         usb_free_dev(udev);
788 err_usb_alloc_dev:
789         iounmap(ohci->regs);
790 err_ioremap:
791         free(hcd->hcpriv);
792 err_ohci_hcd_malloc:
793         free(hcd);
794 err_hcd_malloc:
795
796         return retval;
797 }
798
799 void ohci_hcd_pci_remove(struct pci_device *pci __unused)
800 {
801
802 }
803
804 static struct pci_device_id ohci_hcd_pci_ids[] = {
805         PCI_ROM(0xffff, 0xffff, "OHCI HCD", "OHCI USB Controller"),
806 };
807
808 struct pci_driver ohci_hcd_pci_driver __pci_driver = {
809         .ids = ohci_hcd_pci_ids,
810         .id_count = (sizeof(ohci_hcd_pci_ids) / sizeof(ohci_hcd_pci_ids[0])),
811         .probe = ohci_hcd_pci_probe,
812         .remove = ohci_hcd_pci_remove,
813 };
814