[MTHCA]bug fixes:
[mirror/winof/.git] / hw / mthca / kernel / mthca_cq.c
1 /*
2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
3  * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4  * Copyright (c) 2005 Cisco Systems, Inc. All rights reserved.
5  * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
6  * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
7  *
8  * This software is available to you under a choice of one of two
9  * licenses.  You may choose to be licensed under the terms of the GNU
10  * General Public License (GPL) Version 2, available from the file
11  * COPYING in the main directory of this source tree, or the
12  * OpenIB.org BSD license below:
13  *
14  *     Redistribution and use in source and binary forms, with or
15  *     without modification, are permitted provided that the following
16  *     conditions are met:
17  *
18  *      - Redistributions of source code must retain the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer.
21  *
22  *      - Redistributions in binary form must reproduce the above
23  *        copyright notice, this list of conditions and the following
24  *        disclaimer in the documentation and/or other materials
25  *        provided with the distribution.
26  *
27  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34  * SOFTWARE.
35  *
36  * $Id$
37  */
38
39 #include <ib_pack.h>
40
41 #include "mthca_dev.h"
42 #if defined(EVENT_TRACING)
43 #ifdef offsetof
44 #undef offsetof
45 #endif
46 #include "mthca_cq.tmh"
47 #endif
48 #include "mthca_cmd.h"
49 #include "mthca_memfree.h"
50 #include "mthca_wqe.h"
51
52
53 #ifdef ALLOC_PRAGMA
54 #pragma alloc_text (PAGE, mthca_init_cq_table)
55 #pragma alloc_text (PAGE, mthca_cleanup_cq_table)
56 #endif
57
58 enum {
59         MTHCA_MAX_DIRECT_CQ_SIZE = 4 * PAGE_SIZE
60 };
61
62 /*
63  * Must be packed because start is 64 bits but only aligned to 32 bits.
64  */
65 #pragma pack(push,1)
66 struct mthca_cq_context {
67         __be32 flags;
68         __be64 start;
69         __be32 logsize_usrpage;
70         __be32 error_eqn;       /* Tavor only */
71         __be32 comp_eqn;
72         __be32 pd;
73         __be32 lkey;
74         __be32 last_notified_index;
75         __be32 solicit_producer_index;
76         __be32 consumer_index;
77         __be32 producer_index;
78         __be32 cqn;
79         __be32 ci_db;           /* Arbel only */
80         __be32 state_db;        /* Arbel only */
81         u32    reserved;
82 };
83 #pragma pack(pop)
84
85 #define MTHCA_CQ_STATUS_OK          ( 0 << 28)
86 #define MTHCA_CQ_STATUS_OVERFLOW    ( 9 << 28)
87 #define MTHCA_CQ_STATUS_WRITE_FAIL  (10 << 28)
88 #define MTHCA_CQ_FLAG_TR            ( 1 << 18)
89 #define MTHCA_CQ_FLAG_OI            ( 1 << 17)
90 #define MTHCA_CQ_STATE_DISARMED     ( 0 <<  8)
91 #define MTHCA_CQ_STATE_ARMED        ( 1 <<  8)
92 #define MTHCA_CQ_STATE_ARMED_SOL    ( 4 <<  8)
93 #define MTHCA_EQ_STATE_FIRED        (10 <<  8)
94
95 enum {
96         MTHCA_ERROR_CQE_OPCODE_MASK = 0xfe
97 };
98
99 enum {
100         SYNDROME_LOCAL_LENGTH_ERR        = 0x01,
101         SYNDROME_LOCAL_QP_OP_ERR         = 0x02,
102         SYNDROME_LOCAL_EEC_OP_ERR        = 0x03,
103         SYNDROME_LOCAL_PROT_ERR          = 0x04,
104         SYNDROME_WR_FLUSH_ERR            = 0x05,
105         SYNDROME_MW_BIND_ERR             = 0x06,
106         SYNDROME_BAD_RESP_ERR            = 0x10,
107         SYNDROME_LOCAL_ACCESS_ERR        = 0x11,
108         SYNDROME_REMOTE_INVAL_REQ_ERR    = 0x12,
109         SYNDROME_REMOTE_ACCESS_ERR       = 0x13,
110         SYNDROME_REMOTE_OP_ERR           = 0x14,
111         SYNDROME_RETRY_EXC_ERR           = 0x15,
112         SYNDROME_RNR_RETRY_EXC_ERR       = 0x16,
113         SYNDROME_LOCAL_RDD_VIOL_ERR      = 0x20,
114         SYNDROME_REMOTE_INVAL_RD_REQ_ERR = 0x21,
115         SYNDROME_REMOTE_ABORTED_ERR      = 0x22,
116         SYNDROME_INVAL_EECN_ERR          = 0x23,
117         SYNDROME_INVAL_EEC_STATE_ERR     = 0x24
118 };
119
120 struct mthca_cqe {
121         __be32 my_qpn;
122         __be32 my_ee;
123         __be32 rqpn;
124         __be16 sl_g_mlpath;
125         __be16 rlid;
126         __be32 imm_etype_pkey_eec;
127         __be32 byte_cnt;
128         __be32 wqe;
129         u8     opcode;
130         u8     is_send;
131         u8     reserved;
132         u8     owner;
133 };
134
135 struct mthca_err_cqe {
136         __be32 my_qpn;
137         u32    reserved1[3];
138         u8     syndrome;
139         u8     vendor_err;
140         __be16 db_cnt;
141         u32    reserved2;
142         __be32 wqe;
143         u8     opcode;
144         u8     reserved3[2];
145         u8     owner;
146 };
147
148 #define MTHCA_CQ_ENTRY_OWNER_SW      (0 << 7)
149 #define MTHCA_CQ_ENTRY_OWNER_HW      (1 << 7)
150
151 #define MTHCA_TAVOR_CQ_DB_INC_CI       (1 << 24)
152 #define MTHCA_TAVOR_CQ_DB_REQ_NOT      (2 << 24)
153 #define MTHCA_TAVOR_CQ_DB_REQ_NOT_SOL  (3 << 24)
154 #define MTHCA_TAVOR_CQ_DB_SET_CI       (4 << 24)
155 #define MTHCA_TAVOR_CQ_DB_REQ_NOT_MULT (5 << 24)
156
157 #define MTHCA_ARBEL_CQ_DB_REQ_NOT_SOL  (1 << 24)
158 #define MTHCA_ARBEL_CQ_DB_REQ_NOT      (2 << 24)
159 #define MTHCA_ARBEL_CQ_DB_REQ_NOT_MULT (3 << 24)
160
161 static inline struct mthca_cqe *get_cqe(struct mthca_cq *cq, int entry)
162 {
163         if (cq->is_direct)
164                 return (struct mthca_cqe *)((u8*)cq->queue.direct.page + (entry * MTHCA_CQ_ENTRY_SIZE));
165         else
166                 return (struct mthca_cqe *)((u8*)cq->queue.page_list[entry * MTHCA_CQ_ENTRY_SIZE / PAGE_SIZE].page
167                         + (entry * MTHCA_CQ_ENTRY_SIZE) % PAGE_SIZE);
168 }
169
170 static inline struct mthca_cqe *cqe_sw(struct mthca_cq *cq, int i)
171 {
172         struct mthca_cqe *cqe = get_cqe(cq, i);
173         return MTHCA_CQ_ENTRY_OWNER_HW & cqe->owner ? NULL : cqe;
174 }
175
176 static inline struct mthca_cqe *next_cqe_sw(struct mthca_cq *cq)
177 {
178         return cqe_sw(cq, cq->cons_index & cq->ibcq.cqe);
179 }
180
181 static inline void set_cqe_hw(struct mthca_cqe *cqe)
182 {
183         cqe->owner = MTHCA_CQ_ENTRY_OWNER_HW;
184 }
185
186 static void dump_cqe(u32 print_lvl, struct mthca_dev *dev, void *cqe_ptr)
187 {
188         __be32 *cqe = cqe_ptr;
189         UNREFERENCED_PARAMETER(dev);
190     UNUSED_PARAM_WOWPP(print_lvl);
191
192         (void) cqe;     /* avoid warning if mthca_dbg compiled away... */
193         HCA_PRINT(print_lvl,HCA_DBG_CQ,("CQE contents \n"));
194         HCA_PRINT(print_lvl,HCA_DBG_CQ,("\t[%2x] %08x %08x %08x %08x\n",0,
195                 cl_ntoh32(cqe[0]), cl_ntoh32(cqe[1]), cl_ntoh32(cqe[2]), cl_ntoh32(cqe[3])));
196         HCA_PRINT(print_lvl,HCA_DBG_CQ,("\t[%2x] %08x %08x %08x %08x \n",16,
197                 cl_ntoh32(cqe[4]), cl_ntoh32(cqe[5]), cl_ntoh32(cqe[6]), cl_ntoh32(cqe[7])));
198 }
199
200 /*
201  * incr is ignored in native Arbel (mem-free) mode, so cq->cons_index
202  * should be correct before calling update_cons_index().
203  */
204 static inline void update_cons_index(struct mthca_dev *dev, struct mthca_cq *cq,
205                                      int incr)
206 {
207         __be32 doorbell[2];
208
209         if (mthca_is_memfree(dev)) {
210                 *cq->set_ci_db = cl_hton32(cq->cons_index);
211                 wmb();
212         } else {
213                 doorbell[0] = cl_hton32(MTHCA_TAVOR_CQ_DB_INC_CI | cq->cqn);
214                 doorbell[1] = cl_hton32(incr - 1);
215
216                 mthca_write64(doorbell,
217                               dev->kar + MTHCA_CQ_DOORBELL,
218                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
219         }
220 }
221
222 void mthca_cq_completion(struct mthca_dev *dev, u32 cqn)
223 {
224         struct mthca_cq *cq;
225
226         cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1));
227
228         if (!cq) {
229                 HCA_PRINT(TRACE_LEVEL_WARNING  ,HCA_DBG_LOW  ,("Completion event for bogus CQ %08x\n", cqn));
230                 return;
231         }
232
233         if (mthca_is_memfree(dev)) {
234                 if (cq->ibcq.ucontext)
235                         ++*cq->p_u_arm_sn;
236                 else
237                         ++cq->arm_sn;
238         }
239
240         cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context);
241 }
242
243 void mthca_cq_event(struct mthca_dev *dev, u32 cqn,
244                     enum ib_event_type event_type)
245 {
246         struct mthca_cq *cq;
247         struct ib_event event;
248         SPIN_LOCK_PREP(lh);
249
250         spin_lock(&dev->cq_table.lock, &lh);
251
252         cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1));
253
254         if (cq)
255                 atomic_inc(&cq->refcount);
256         spin_unlock(&lh);
257
258         if (!cq) {
259                 HCA_PRINT(TRACE_LEVEL_WARNING  ,HCA_DBG_LOW  ,("Async event for bogus CQ %08x\n", cqn));
260                 return;
261         }
262
263         event.device      = &dev->ib_dev;
264         event.event       = event_type;
265         event.element.cq  = &cq->ibcq;
266         if (cq->ibcq.event_handler)
267                 cq->ibcq.event_handler(&event, cq->ibcq.cq_context);
268
269         if (atomic_dec_and_test(&cq->refcount))
270                 wake_up(&cq->wait);
271 }
272
273 void mthca_cq_clean(struct mthca_dev *dev, u32 cqn, u32 qpn,
274                     struct mthca_srq *srq)
275 {
276         struct mthca_cq *cq;
277         struct mthca_cqe *cqe;
278         u32 prod_index;
279         int nfreed = 0;
280         SPIN_LOCK_PREP(lht);
281         SPIN_LOCK_PREP(lh);
282
283         spin_lock_irq(&dev->cq_table.lock, &lht);
284         cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1));
285         if (cq)
286                 atomic_inc(&cq->refcount);
287         spin_unlock_irq(&lht);
288
289         if (!cq)
290                 return;
291
292         spin_lock_irq(&cq->lock, &lh);
293
294         /*
295          * First we need to find the current producer index, so we
296          * know where to start cleaning from.  It doesn't matter if HW
297          * adds new entries after this loop -- the QP we're worried
298          * about is already in RESET, so the new entries won't come
299          * from our QP and therefore don't need to be checked.
300          */
301         for (prod_index = cq->cons_index;
302              cqe_sw(cq, prod_index & cq->ibcq.cqe);
303              ++prod_index) {
304                 if (prod_index == cq->cons_index + cq->ibcq.cqe)
305                         break;
306         }
307
308         HCA_PRINT(TRACE_LEVEL_VERBOSE,HCA_DBG_LOW,("Cleaning QPN %06x from CQN %06x; ci %d, pi %d\n",
309                   qpn, cqn, cq->cons_index, prod_index));
310
311         /*
312          * Now sweep backwards through the CQ, removing CQ entries
313          * that match our QP by copying older entries on top of them.
314          */
315         while ((int) --prod_index - (int) cq->cons_index >= 0) {
316                 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe);
317                 if (cqe->my_qpn == cl_hton32(qpn)) {
318                         if (srq)
319                                 mthca_free_srq_wqe(srq, cl_ntoh32(cqe->wqe));
320                         ++nfreed;
321                 } 
322                 else 
323                 if (nfreed) {
324                         memcpy(get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe),
325                                 cqe, MTHCA_CQ_ENTRY_SIZE);
326                 }
327         }
328
329         if (nfreed) {
330                 wmb();
331                 cq->cons_index += nfreed;
332                 update_cons_index(dev, cq, nfreed);
333         }
334
335         spin_unlock_irq(&lh);
336         if (atomic_dec_and_test(&cq->refcount))
337                 wake_up(&cq->wait);
338 }
339
340 static void handle_error_cqe(struct mthca_dev *dev, struct mthca_cq *cq,
341                             struct mthca_qp *qp, int wqe_index, int is_send,
342                             struct mthca_err_cqe *cqe,
343                             struct _ib_wc *entry, int *free_cqe)
344 {
345         int dbd;
346         __be32 new_wqe;
347
348         UNREFERENCED_PARAMETER(cq);
349         
350         if (cqe->syndrome != SYNDROME_WR_FLUSH_ERR) {
351                 HCA_PRINT(TRACE_LEVEL_INFORMATION ,HCA_DBG_CQ ,("Completion with errro "
352                           "(QPN %06x, WQE @ %08x, CQN %06x, index %d)\n",
353                           cl_ntoh32(cqe->my_qpn), cl_ntoh32(cqe->wqe),
354                           cq->cqn, cq->cons_index));
355                 dump_cqe(TRACE_LEVEL_INFORMATION, dev, cqe);
356         }
357
358
359         /*
360          * For completions in error, only work request ID, status, vendor error
361          * (and freed resource count for RD) have to be set.
362          */
363         switch (cqe->syndrome) {
364         case SYNDROME_LOCAL_LENGTH_ERR:
365                 entry->status = IB_WCS_LOCAL_LEN_ERR;
366                 break;
367         case SYNDROME_LOCAL_QP_OP_ERR:
368                 entry->status = IB_WCS_LOCAL_OP_ERR;
369                 break;
370         case SYNDROME_LOCAL_PROT_ERR:
371                 entry->status = IB_WCS_LOCAL_PROTECTION_ERR;
372                 break;
373         case SYNDROME_WR_FLUSH_ERR:
374                 entry->status = IB_WCS_WR_FLUSHED_ERR;
375                 break;
376         case SYNDROME_MW_BIND_ERR:
377                 entry->status = IB_WCS_MEM_WINDOW_BIND_ERR;
378                 break;
379         case SYNDROME_BAD_RESP_ERR:
380                 entry->status = IB_WCS_BAD_RESP_ERR;
381                 break;
382         case SYNDROME_LOCAL_ACCESS_ERR:
383                 entry->status = IB_WCS_LOCAL_ACCESS_ERR;
384                 break;
385         case SYNDROME_REMOTE_INVAL_REQ_ERR:
386                 entry->status = IB_WCS_REM_INVALID_REQ_ERR;
387                 break;
388         case SYNDROME_REMOTE_ACCESS_ERR:
389                 entry->status = IB_WCS_REM_ACCESS_ERR;
390                 break;
391         case SYNDROME_REMOTE_OP_ERR:
392                 entry->status = IB_WCS_REM_OP_ERR;
393                 break;
394         case SYNDROME_RETRY_EXC_ERR:
395                 entry->status = IB_WCS_TIMEOUT_RETRY_ERR;
396                 break;
397         case SYNDROME_RNR_RETRY_EXC_ERR:
398                 entry->status = IB_WCS_RNR_RETRY_ERR;
399                 break;
400         case SYNDROME_REMOTE_INVAL_RD_REQ_ERR:
401                 entry->status = IB_WCS_REM_INVALID_REQ_ERR;
402                 break;
403         case SYNDROME_REMOTE_ABORTED_ERR:
404         case SYNDROME_LOCAL_EEC_OP_ERR:
405         case SYNDROME_LOCAL_RDD_VIOL_ERR:
406         case SYNDROME_INVAL_EECN_ERR:
407         case SYNDROME_INVAL_EEC_STATE_ERR:
408         default:
409                 entry->status = IB_WCS_GENERAL_ERR;
410                 break;
411         }
412
413         entry->vendor_specific = cqe->vendor_err;
414         
415         /*
416          * Mem-free HCAs always generate one CQE per WQE, even in the
417          * error case, so we don't have to check the doorbell count, etc.
418          */
419         if (mthca_is_memfree(dev))
420                 return;
421
422         mthca_free_err_wqe(dev, qp, is_send, wqe_index, &dbd, &new_wqe);
423
424         /*
425          * If we're at the end of the WQE chain, or we've used up our
426          * doorbell count, free the CQE.  Otherwise just update it for
427          * the next poll operation.
428          */
429         if (!(new_wqe & cl_hton32(0x3f)) || (!cqe->db_cnt && dbd))
430                 return;
431
432         cqe->db_cnt   = cl_hton16(cl_ntoh16(cqe->db_cnt) - (u16)dbd);
433         cqe->wqe      = new_wqe;
434         cqe->syndrome = SYNDROME_WR_FLUSH_ERR;
435
436         *free_cqe = 0;
437 }
438
439 static inline int mthca_poll_one(struct mthca_dev *dev,
440                                  struct mthca_cq *cq,
441                                  struct mthca_qp **cur_qp,
442                                  int *freed,
443                                  struct _ib_wc *entry)
444 {
445         struct mthca_wq *wq;
446         struct mthca_cqe *cqe;
447         unsigned  wqe_index;
448         int is_error;
449         int is_send;
450         int free_cqe = 1;
451         int err = 0;
452
453         HCA_ENTER(HCA_DBG_CQ);
454         cqe = next_cqe_sw(cq);
455         if (!cqe)
456                 return -EAGAIN;
457
458         /*
459          * Make sure we read CQ entry contents after we've checked the
460          * ownership bit.
461          */
462         rmb();
463
464         { // debug print
465                 HCA_PRINT(TRACE_LEVEL_VERBOSE,HCA_DBG_CQ,("CQ: 0x%06x/%d: CQE -> QPN 0x%06x, WQE @ 0x%08x\n",
466                           cq->cqn, cq->cons_index, cl_ntoh32(cqe->my_qpn),
467                           cl_ntoh32(cqe->wqe)));
468                 dump_cqe(TRACE_LEVEL_VERBOSE, dev, cqe);
469         }
470
471         is_error = (cqe->opcode & MTHCA_ERROR_CQE_OPCODE_MASK) ==
472                 MTHCA_ERROR_CQE_OPCODE_MASK;
473         is_send  = is_error ? cqe->opcode & 0x01 : cqe->is_send & 0x80;
474
475         if (!*cur_qp || cl_ntoh32(cqe->my_qpn) != (*cur_qp)->qpn) {
476                 /*
477                  * We do not have to take the QP table lock here,
478                  * because CQs will be locked while QPs are removed
479                  * from the table.
480                  */
481                 *cur_qp = mthca_array_get(&dev->qp_table.qp,
482                                           cl_ntoh32(cqe->my_qpn) &
483                                           (dev->limits.num_qps - 1));
484                 if (!*cur_qp) {
485                         HCA_PRINT(TRACE_LEVEL_WARNING,HCA_DBG_CQ, ("CQ entry for unknown QP %06x\n",
486                                    cl_ntoh32(cqe->my_qpn) & 0xffffff));
487                         err = -EINVAL;
488                         goto out;
489                 }
490         }
491
492         if (is_send) {
493                 wq = &(*cur_qp)->sq;
494                 wqe_index = ((cl_ntoh32(cqe->wqe) - (*cur_qp)->send_wqe_offset)
495                              >> wq->wqe_shift);
496                 entry->wr_id = (*cur_qp)->wrid[wqe_index +
497                                                (*cur_qp)->rq.max];
498         } else if ((*cur_qp)->ibqp.srq) {
499                 struct mthca_srq *srq = to_msrq((*cur_qp)->ibqp.srq);
500                 u32 wqe = cl_ntoh32(cqe->wqe);
501                 wq = NULL;
502                 wqe_index = wqe >> srq->wqe_shift;
503                 entry->wr_id = srq->wrid[wqe_index];
504                 mthca_free_srq_wqe(srq, wqe);
505         } else {
506                 wq = &(*cur_qp)->rq;
507                 wqe_index = cl_ntoh32(cqe->wqe) >> wq->wqe_shift;
508                 entry->wr_id = (*cur_qp)->wrid[wqe_index];
509         }
510
511         if (wq) {
512                 if (wq->last_comp < wqe_index)
513                         wq->tail += wqe_index - wq->last_comp;
514                 else
515                         wq->tail += wqe_index + wq->max - wq->last_comp;
516
517                 wq->last_comp = wqe_index;
518         }
519
520         if (is_send) {
521                 entry->recv.ud.recv_opt = 0;
522                 switch (cqe->opcode) {
523                 case MTHCA_OPCODE_RDMA_WRITE:
524                         entry->wc_type    = IB_WC_RDMA_WRITE;
525                         break;
526                 case MTHCA_OPCODE_RDMA_WRITE_IMM:
527                         entry->wc_type    = IB_WC_RDMA_WRITE;
528                         entry->recv.ud.recv_opt |= IB_RECV_OPT_IMMEDIATE;
529                         break;
530                 case MTHCA_OPCODE_SEND:
531                         entry->wc_type    = IB_WC_SEND;
532                         break;
533                 case MTHCA_OPCODE_SEND_IMM:
534                         entry->wc_type    = IB_WC_SEND;
535                         entry->recv.ud.recv_opt |= IB_RECV_OPT_IMMEDIATE;
536                         break;
537                 case MTHCA_OPCODE_RDMA_READ:
538                         entry->wc_type    = IB_WC_RDMA_READ;
539                         entry->length  = cl_ntoh32(cqe->byte_cnt);
540                         break;
541                 case MTHCA_OPCODE_ATOMIC_CS:
542                         entry->wc_type    = IB_WC_COMPARE_SWAP;
543                         entry->length = MTHCA_BYTES_PER_ATOMIC_COMPL;
544                         break;
545                 case MTHCA_OPCODE_ATOMIC_FA:
546                         entry->wc_type    = IB_WC_FETCH_ADD;
547                         entry->length = MTHCA_BYTES_PER_ATOMIC_COMPL;
548                         break;
549                 case MTHCA_OPCODE_BIND_MW:
550                         entry->wc_type    = IB_WC_MW_BIND;
551                         break;
552                 default:
553                         entry->wc_type    = IB_WC_SEND;
554                         break;
555                 }
556         } else {
557                 entry->length = cl_ntoh32(cqe->byte_cnt);
558                 switch (cqe->opcode & 0x1f) {
559                 case IB_OPCODE_SEND_LAST_WITH_IMMEDIATE:
560                 case IB_OPCODE_SEND_ONLY_WITH_IMMEDIATE:
561                         entry->recv.ud.recv_opt = IB_RECV_OPT_IMMEDIATE;
562                         entry->recv.ud.immediate_data = cqe->imm_etype_pkey_eec;
563                         entry->wc_type = IB_WC_RECV;
564                         break;
565                 case IB_OPCODE_RDMA_WRITE_LAST_WITH_IMMEDIATE:
566                 case IB_OPCODE_RDMA_WRITE_ONLY_WITH_IMMEDIATE:
567                         entry->recv.ud.recv_opt = IB_RECV_OPT_IMMEDIATE;
568                         entry->recv.ud.immediate_data = cqe->imm_etype_pkey_eec;
569                         entry->wc_type = IB_WC_RECV_RDMA_WRITE;
570                         break;
571                 default:
572                         entry->recv.ud.recv_opt = 0;
573                         entry->wc_type = IB_WC_RECV;
574                         break;
575                 }
576                 entry->recv.ud.remote_lid          = cqe->rlid;
577                 entry->recv.ud.remote_qp           = cqe->rqpn & 0xffffff00;
578                 entry->recv.ud.pkey_index  = (u16)(cl_ntoh32(cqe->imm_etype_pkey_eec) >> 16);
579                 entry->recv.ud.remote_sl           = (uint8_t)(cl_ntoh16(cqe->sl_g_mlpath) >> 12);
580                 entry->recv.ud.path_bits = (uint8_t)(cl_ntoh16(cqe->sl_g_mlpath) & 0x7f);
581                 entry->recv.ud.recv_opt   |= cl_ntoh16(cqe->sl_g_mlpath) & 0x80 ?
582                                         IB_RECV_OPT_GRH_VALID : 0;
583         }
584         if (!is_send && cqe->rlid == 0){
585                 HCA_PRINT(TRACE_LEVEL_INFORMATION,HCA_DBG_CQ,("found rlid == 0 \n "));
586                 entry->recv.ud.recv_opt   |= IB_RECV_OPT_FORWARD;
587
588         }
589         if (is_error) {
590                 handle_error_cqe(dev, cq, *cur_qp, wqe_index, is_send,
591                         (struct mthca_err_cqe *) cqe, entry, &free_cqe);
592         }
593         else
594                 entry->status = IB_WCS_SUCCESS;
595
596  out:
597         if (likely(free_cqe)) {
598                 set_cqe_hw(cqe);
599                 ++(*freed);
600                 ++cq->cons_index;
601         }
602         HCA_EXIT(HCA_DBG_CQ);
603         return err;
604 }
605
606 int mthca_poll_cq(struct ib_cq *ibcq, int num_entries,
607                   struct _ib_wc *entry)
608 {
609         struct mthca_dev *dev = to_mdev(ibcq->device);
610         struct mthca_cq *cq = to_mcq(ibcq);
611         struct mthca_qp *qp = NULL;
612         int err = 0;
613         int freed = 0;
614         int npolled;
615         SPIN_LOCK_PREP(lh);
616
617         spin_lock_irqsave(&cq->lock, &lh);
618
619         for (npolled = 0; npolled < num_entries; ++npolled) {
620                 err = mthca_poll_one(dev, cq, &qp,
621                                      &freed, entry + npolled);
622                 if (err)
623                         break;
624         }
625
626         if (freed) {
627                 wmb();
628                 update_cons_index(dev, cq, freed);
629         }
630
631         spin_unlock_irqrestore(&lh);
632
633         return (err == 0 || err == -EAGAIN) ? npolled : err;
634 }
635
636 int mthca_poll_cq_list(
637         IN              struct ib_cq *ibcq, 
638         IN      OUT                     ib_wc_t** const                         pp_free_wclist,
639                 OUT                     ib_wc_t** const                         pp_done_wclist )
640 {
641         struct mthca_dev *dev = to_mdev(ibcq->device);
642         struct mthca_cq *cq = to_mcq(ibcq);
643         struct mthca_qp *qp = NULL;
644         int err = 0;
645         int freed = 0;
646         ib_wc_t         *wc_p, **next_pp;
647         SPIN_LOCK_PREP(lh);
648
649         HCA_ENTER(HCA_DBG_CQ);
650
651         spin_lock_irqsave(&cq->lock, &lh);
652
653         // loop through CQ
654         next_pp = pp_done_wclist;
655         wc_p = *pp_free_wclist;
656         while( wc_p ) {
657                 // poll one CQE
658                 err = mthca_poll_one(dev, cq, &qp, &freed, wc_p);
659                 if (err)
660                         break;
661
662                 // prepare for the next loop
663                 *next_pp = wc_p;
664                 next_pp = &wc_p->p_next;
665                 wc_p = wc_p->p_next;
666         }
667
668         // prepare the results
669         *pp_free_wclist = wc_p;         /* Set the head of the free list. */
670         *next_pp = NULL;                                                /* Clear the tail of the done list. */
671
672         // update consumer index
673         if (freed) {
674                 wmb();
675                 update_cons_index(dev, cq, freed);
676         }
677
678         spin_unlock_irqrestore(&lh);
679         HCA_EXIT(HCA_DBG_CQ);
680         return (err == 0 || err == -EAGAIN)? 0 : err;
681 }
682
683
684 int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify)
685 {
686         __be32 doorbell[2];
687
688         doorbell[0] = cl_hton32((notify == IB_CQ_SOLICITED ?
689                                    MTHCA_TAVOR_CQ_DB_REQ_NOT_SOL :
690                                    MTHCA_TAVOR_CQ_DB_REQ_NOT)      |
691                                   to_mcq(cq)->cqn);
692         doorbell[1] = (__be32) 0xffffffff;
693
694         mthca_write64(doorbell,
695                       to_mdev(cq->device)->kar + MTHCA_CQ_DOORBELL,
696                       MTHCA_GET_DOORBELL_LOCK(&to_mdev(cq->device)->doorbell_lock));
697
698         return 0;
699 }
700
701 int mthca_arbel_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify notify)
702 {
703         struct mthca_cq *cq = to_mcq(ibcq);
704         __be32 doorbell[2];
705         u32 sn;
706         __be32 ci;
707
708         sn = cq->arm_sn & 3;
709         ci = cl_hton32(cq->cons_index);
710
711         doorbell[0] = ci;
712         doorbell[1] = cl_hton32((cq->cqn << 8) | (2 << 5) | (sn << 3) |
713                                   (notify == IB_CQ_SOLICITED ? 1 : 2));
714
715         mthca_write_db_rec(doorbell, cq->arm_db);
716
717         /*
718          * Make sure that the doorbell record in host memory is
719          * written before ringing the doorbell via PCI MMIO.
720          */
721         wmb();
722
723         doorbell[0] = cl_hton32((sn << 28)                       |
724                                   (notify == IB_CQ_SOLICITED ?
725                                    MTHCA_ARBEL_CQ_DB_REQ_NOT_SOL :
726                                    MTHCA_ARBEL_CQ_DB_REQ_NOT)      |
727                                   cq->cqn);
728         doorbell[1] = ci;
729
730         mthca_write64(doorbell,
731                       to_mdev(ibcq->device)->kar + MTHCA_CQ_DOORBELL,
732                       MTHCA_GET_DOORBELL_LOCK(&to_mdev(ibcq->device)->doorbell_lock));
733
734         return 0;
735 }
736
737 static void mthca_free_cq_buf(struct mthca_dev *dev, struct mthca_cq *cq)
738 {
739         mthca_buf_free(dev, (cq->ibcq.cqe + 1) * MTHCA_CQ_ENTRY_SIZE,
740                        &cq->queue, cq->is_direct, &cq->mr);
741 }
742
743 int mthca_init_cq(struct mthca_dev *dev, int nent,
744                   struct mthca_ucontext *ctx, u32 pdn,
745                   struct mthca_cq *cq)
746 {
747         int size = NEXT_PAGE_ALIGN(nent * MTHCA_CQ_ENTRY_SIZE );
748         struct mthca_mailbox *mailbox;
749         struct mthca_cq_context *cq_context;
750         int err = -ENOMEM;
751         u8 status;
752         int i;
753         SPIN_LOCK_PREP(lh);
754
755         cq->ibcq.cqe  = nent - 1;
756         cq->is_kernel = !ctx;
757
758         cq->cqn = mthca_alloc(&dev->cq_table.alloc);
759         if (cq->cqn == -1)
760                 return -ENOMEM;
761
762         if (mthca_is_memfree(dev)) {
763                 err = mthca_table_get(dev, dev->cq_table.table, cq->cqn);
764                 if (err)
765                         goto err_out;
766
767                 if (cq->is_kernel) {
768                         cq->arm_sn = 1;
769
770                         err = -ENOMEM;
771
772                         cq->set_ci_db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_CQ_SET_CI,
773                                                              cq->cqn, &cq->set_ci_db);
774                         if (cq->set_ci_db_index < 0)
775                                 goto err_out_icm;
776
777                         cq->arm_db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_CQ_ARM,
778                                                           cq->cqn, &cq->arm_db);
779                         if (cq->arm_db_index < 0)
780                                 goto err_out_ci;
781                 }
782         }
783
784         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
785         if (IS_ERR(mailbox))
786                 goto err_out_arm;
787
788         cq_context = mailbox->buf;
789
790         if (cq->is_kernel) {
791                 err = mthca_buf_alloc(dev, size, MTHCA_MAX_DIRECT_CQ_SIZE,
792                                       &cq->queue, &cq->is_direct,
793                                       &dev->driver_pd, 1, &cq->mr);
794                 if (err)
795                         goto err_out_mailbox;
796
797                 for (i = 0; i < nent; ++i)
798                         set_cqe_hw(get_cqe(cq, i));
799         }
800
801         spin_lock_init(&cq->lock);
802         atomic_set(&cq->refcount, 1);
803         init_waitqueue_head(&cq->wait);
804         KeInitializeMutex(&cq->mutex, 0);
805
806         RtlZeroMemory(cq_context, sizeof *cq_context);
807         cq_context->flags           = cl_hton32(MTHCA_CQ_STATUS_OK      |
808                                                   MTHCA_CQ_STATE_DISARMED |
809                                                   MTHCA_CQ_FLAG_TR);
810         cq_context->logsize_usrpage = cl_hton32((ffs(nent) - 1) << 24);
811         if (ctx)
812                 cq_context->logsize_usrpage |= cl_hton32(ctx->uar.index);
813         else
814                 cq_context->logsize_usrpage |= cl_hton32(dev->driver_uar.index);
815         cq_context->error_eqn       = cl_hton32(dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn);
816         cq_context->comp_eqn        = cl_hton32(dev->eq_table.eq[MTHCA_EQ_COMP].eqn);
817         cq_context->pd              = cl_hton32(pdn);
818         cq_context->lkey            = cl_hton32(cq->mr.ibmr.lkey);
819         cq_context->cqn             = cl_hton32(cq->cqn);
820
821         if (mthca_is_memfree(dev)) {
822                 cq_context->ci_db    = cl_hton32(cq->set_ci_db_index);
823                 cq_context->state_db = cl_hton32(cq->arm_db_index);
824         }
825
826         err = mthca_SW2HW_CQ(dev, mailbox, cq->cqn, &status);
827         if (err) {
828                 HCA_PRINT(TRACE_LEVEL_WARNING  ,HCA_DBG_LOW  ,("SW2HW_CQ failed (%d)\n", err));
829                 goto err_out_free_mr;
830         }
831
832         if (status) {
833                 HCA_PRINT(TRACE_LEVEL_WARNING,HCA_DBG_LOW,("SW2HW_CQ returned status 0x%02x\n",
834                            status));
835                 err = -EINVAL;
836                 goto err_out_free_mr;
837         }
838
839         spin_lock_irq(&dev->cq_table.lock, &lh);
840         if (mthca_array_set(&dev->cq_table.cq,
841                             cq->cqn & (dev->limits.num_cqs - 1),
842                             cq)) {
843                 spin_unlock_irq(&lh);
844                 goto err_out_free_mr;
845         }
846         spin_unlock_irq(&lh);
847
848         cq->cons_index = 0;
849
850         mthca_free_mailbox(dev, mailbox);
851
852         return 0;
853
854 err_out_free_mr:
855         if (cq->is_kernel)
856                 mthca_free_cq_buf(dev, cq);
857
858 err_out_mailbox:
859         mthca_free_mailbox(dev, mailbox);
860
861 err_out_arm:
862         if (cq->is_kernel && mthca_is_memfree(dev))
863                 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_ARM, cq->arm_db_index);
864
865 err_out_ci:
866         if (cq->is_kernel && mthca_is_memfree(dev))
867                 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_SET_CI, cq->set_ci_db_index);
868
869 err_out_icm:
870         mthca_table_put(dev, dev->cq_table.table, cq->cqn);
871
872 err_out:
873         mthca_free(&dev->cq_table.alloc, cq->cqn);
874
875         return err;
876 }
877
878 void mthca_free_cq(struct mthca_dev *dev,
879                    struct mthca_cq *cq)
880 {
881         struct mthca_mailbox *mailbox;
882         int err;
883         u8 status;
884         SPIN_LOCK_PREP(lh);
885
886         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
887         if (IS_ERR(mailbox)) {
888                 HCA_PRINT(TRACE_LEVEL_WARNING  ,HCA_DBG_LOW  ,("No memory for mailbox to free CQ.\n"));
889                 return;
890         }
891
892         err = mthca_HW2SW_CQ(dev, mailbox, cq->cqn, &status);
893         if (err){
894                 HCA_PRINT(TRACE_LEVEL_WARNING  ,HCA_DBG_LOW  ,("HW2SW_CQ failed (%d)\n", err));
895         }
896         else if (status){
897                 HCA_PRINT(TRACE_LEVEL_WARNING  ,HCA_DBG_LOW  ,("HW2SW_CQ returned status 0x%02x\n", status));
898         }
899         { // debug print
900                 __be32 *ctx = mailbox->buf;
901                 int j;
902                 UNUSED_PARAM_WOWPP(ctx);
903                 UNUSED_PARAM_WOWPP(j);
904
905                 HCA_PRINT(TRACE_LEVEL_VERBOSE ,HCA_DBG_LOW ,("context for CQN %x (cons index %x, next sw %d)\n",
906                        cq->cqn, cq->cons_index,
907                        cq->is_kernel ? !!next_cqe_sw(cq) : 0));
908                 for (j = 0; j < 16; ++j)
909                         HCA_PRINT(TRACE_LEVEL_VERBOSE   ,HCA_DBG_LOW   ,("[%2x] %08x\n", j * 4, cl_ntoh32(ctx[j])));
910         }
911         spin_lock_irq(&dev->cq_table.lock, &lh);
912         mthca_array_clear(&dev->cq_table.cq,
913                           cq->cqn & (dev->limits.num_cqs - 1));
914         spin_unlock_irq(&lh);
915
916         /* wait for all RUNNING DPCs on that EQ to complete */
917         ASSERT(KeGetCurrentIrql() == PASSIVE_LEVEL);
918         KeFlushQueuedDpcs();
919
920         atomic_dec(&cq->refcount);
921         wait_event(&cq->wait, !atomic_read(&cq->refcount));
922
923         if (cq->is_kernel) {
924                 mthca_free_cq_buf(dev, cq);
925                 if (mthca_is_memfree(dev)) {
926                         mthca_free_db(dev, MTHCA_DB_TYPE_CQ_ARM,    cq->arm_db_index);
927                         mthca_free_db(dev, MTHCA_DB_TYPE_CQ_SET_CI, cq->set_ci_db_index);
928                 }
929         }
930
931         mthca_table_put(dev, dev->cq_table.table, cq->cqn);
932         mthca_free(&dev->cq_table.alloc, cq->cqn);
933         mthca_free_mailbox(dev, mailbox);
934 }
935
936 int mthca_init_cq_table(struct mthca_dev *dev)
937 {
938         int err;
939
940         spin_lock_init(&dev->cq_table.lock);
941
942         err = mthca_alloc_init(&dev->cq_table.alloc,
943                                dev->limits.num_cqs,
944                                (1 << 24) - 1,
945                                dev->limits.reserved_cqs);
946         if (err)
947                 return err;
948
949         err = mthca_array_init(&dev->cq_table.cq,
950                                dev->limits.num_cqs);
951         if (err)
952                 mthca_alloc_cleanup(&dev->cq_table.alloc);
953
954         return err;
955 }
956
957 void mthca_cleanup_cq_table(struct mthca_dev *dev)
958 {
959         mthca_array_cleanup(&dev->cq_table.cq, dev->limits.num_cqs);
960         mthca_alloc_cleanup(&dev->cq_table.alloc);
961 }
962
963