2 * Copyright (c) 2005 SilverStorm Technologies. All rights reserved.
3 * Copyright (c) 2004-2005 Mellanox Technologies, Inc. All rights reserved.
5 * This software is available to you under the OpenIB.org BSD license
8 * Redistribution and use in source and binary forms, with or
9 * without modification, are permitted provided that the following
12 * - Redistributions of source code must retain the above
13 * copyright notice, this list of conditions and the following
16 * - Redistributions in binary form must reproduce the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer in the documentation and/or other materials
19 * provided with the distribution.
21 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
24 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
25 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
26 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
27 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #define PTR_ALIGN(size) (((size) + sizeof(void*) - 1) & ~(sizeof(void*) - 1))
40 unsigned __int64 va; /* address of CRSPACE, mapped to user space */
41 unsigned long size; /* size of CRSPACE, mapped to user space */
42 unsigned long reserved; /* to align on quadword boundary */
45 /* Definitions for hca_driver commands*/
48 #define FW_READ_CMD 0x08
49 #define FW_WRITE_CMD 0x09
50 #define FW_MAP_CRSPACE 0x0A
51 #define FW_UNMAP_CRSPACE 0x0B
52 #define FW_REREGISTER_HCA 0x0c
53 #define FW_OPEN_IF 0xe7
54 #define FW_CLOSE_IF 0x7e
58 uint8_t bus_type; /* 1 - PCI, 2 - PCI-X, 3 - PCI_E */
59 #define UPLINK_BUS_PCI 1
60 #define UPLINK_BUS_PCIX 2
61 #define UPLINK_BUS_PCIE 3
65 #define UPLINK_BUS_PCIX_133 2 /* 133 MHz capable */
66 uint16_t frequency; /* in MHz */
70 uint8_t link_speed; /* 1X link speed */
71 #define UPLINK_BUS_PCIE_SDR 1 /* 2.5 Gbps */
72 #define UPLINK_BUS_PCIE_DDR 2 /* 5 Gbps */
73 uint8_t link_width; /* x1, x2, x4, x8, x12, x16, x32 */
78 /* Defines for get data for vendor specific */
79 #define MTHCA_BRD_ID_LEN 64
81 inline char* mthca_get_board_id(ib_ca_attr_t *ca_attr)
83 return (char*)(ca_attr) + (ca_attr->size - PTR_ALIGN(MTHCA_BRD_ID_LEN) - PTR_ALIGN(sizeof(uplink_info_t)));
86 inline void* mthca_get_uplink_info(ib_ca_attr_t *ca_attr)
88 return (char*)(ca_attr) + (ca_attr->size - PTR_ALIGN(sizeof(uplink_info_t)));