hw/mthca/kernel/mthca_cmd.c

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  *
  33  * $Id: mthca_cmd.c 3047 2005-08-10 03:59:35Z roland $
  34  */
  35
  36 #include <ib_mad.h>
  37
  38 #include "mthca_dev.h"
  39 #if defined(EVENT_TRACING)
  40 #ifdef offsetof
  41 #undef offsetof
  42 #endif
  43 #include "mthca_cmd.tmh"
  44 #endif
  45 #include "mthca_config_reg.h"
  46 #include "mthca_cmd.h"
  47 #include "mthca_memfree.h"
  48
  49 #define CMD_POLL_TOKEN 0xffff
  50
  51 enum {
  52         HCR_IN_PARAM_OFFSET    = 0x00,
  53         HCR_IN_MODIFIER_OFFSET = 0x08,
  54         HCR_OUT_PARAM_OFFSET   = 0x0c,
  55         HCR_TOKEN_OFFSET       = 0x14,
  56         HCR_STATUS_OFFSET      = 0x18,
  57
  58         HCR_OPMOD_SHIFT        = 12,
  59         HCA_E_BIT              = 22,
  60         HCR_GO_BIT             = 23
  61 };
  62
  63 enum {
  64         /* initialization and general commands */
  65         CMD_SYS_EN          = 0x1,
  66         CMD_SYS_DIS         = 0x2,
  67         CMD_MAP_FA          = 0xfff,
  68         CMD_UNMAP_FA        = 0xffe,
  69         CMD_RUN_FW          = 0xff6,
  70         CMD_MOD_STAT_CFG    = 0x34,
  71         CMD_QUERY_DEV_LIM   = 0x3,
  72         CMD_QUERY_FW        = 0x4,
  73         CMD_ENABLE_LAM      = 0xff8,
  74         CMD_DISABLE_LAM     = 0xff7,
  75         CMD_QUERY_DDR       = 0x5,
  76         CMD_QUERY_ADAPTER   = 0x6,
  77         CMD_INIT_HCA        = 0x7,
  78         CMD_CLOSE_HCA       = 0x8,
  79         CMD_INIT_IB         = 0x9,
  80         CMD_CLOSE_IB        = 0xa,
  81         CMD_QUERY_HCA       = 0xb,
  82         CMD_SET_IB          = 0xc,
  83         CMD_ACCESS_DDR      = 0x2e,
  84         CMD_MAP_ICM         = 0xffa,
  85         CMD_UNMAP_ICM       = 0xff9,
  86         CMD_MAP_ICM_AUX     = 0xffc,
  87         CMD_UNMAP_ICM_AUX   = 0xffb,
  88         CMD_SET_ICM_SIZE    = 0xffd,
  89
  90         /* TPT commands */
  91         CMD_SW2HW_MPT       = 0xd,
  92         CMD_QUERY_MPT       = 0xe,
  93         CMD_HW2SW_MPT       = 0xf,
  94         CMD_READ_MTT        = 0x10,
  95         CMD_WRITE_MTT       = 0x11,
  96         CMD_SYNC_TPT        = 0x2f,
  97
  98         /* EQ commands */
  99         CMD_MAP_EQ          = 0x12,
 100         CMD_SW2HW_EQ        = 0x13,
 101         CMD_HW2SW_EQ        = 0x14,
 102         CMD_QUERY_EQ        = 0x15,
 103
 104         /* CQ commands */
 105         CMD_SW2HW_CQ        = 0x16,
 106         CMD_HW2SW_CQ        = 0x17,
 107         CMD_QUERY_CQ        = 0x18,
 108         CMD_RESIZE_CQ       = 0x2c,
 109
 110         /* SRQ commands */
 111         CMD_SW2HW_SRQ       = 0x35,
 112         CMD_HW2SW_SRQ       = 0x36,
 113         CMD_QUERY_SRQ       = 0x37,
 114         CMD_ARM_SRQ         = 0x40,
 115
 116         /* QP/EE commands */
 117         CMD_RST2INIT_QPEE   = 0x19,
 118         CMD_INIT2RTR_QPEE   = 0x1a,
 119         CMD_RTR2RTS_QPEE    = 0x1b,
 120         CMD_RTS2RTS_QPEE    = 0x1c,
 121         CMD_SQERR2RTS_QPEE  = 0x1d,
 122         CMD_2ERR_QPEE       = 0x1e,
 123         CMD_RTS2SQD_QPEE    = 0x1f,
 124         CMD_SQD2SQD_QPEE    = 0x38,
 125         CMD_SQD2RTS_QPEE    = 0x20,
 126         CMD_ERR2RST_QPEE    = 0x21,
 127         CMD_QUERY_QPEE      = 0x22,
 128         CMD_INIT2INIT_QPEE  = 0x2d,
 129         CMD_SUSPEND_QPEE    = 0x32,
 130         CMD_UNSUSPEND_QPEE  = 0x33,
 131         /* special QPs and management commands */
 132         CMD_CONF_SPECIAL_QP = 0x23,
 133         CMD_MAD_IFC         = 0x24,
 134
 135         /* multicast commands */
 136         CMD_READ_MGM        = 0x25,
 137         CMD_WRITE_MGM       = 0x26,
 138         CMD_MGID_HASH       = 0x27,
 139
 140         /* miscellaneous commands */
 141         CMD_DIAG_RPRT       = 0x30,
 142         CMD_NOP             = 0x31,
 143
 144         /* debug commands */
 145         CMD_QUERY_DEBUG_MSG = 0x2a,
 146         CMD_SET_DEBUG_MSG   = 0x2b,
 147 };
 148
 149 /*
 150  * According to Mellanox code, FW may be starved and never complete
 151  * commands.  So we can't use strict timeouts described in PRM -- we
 152  * just arbitrarily select 60 seconds for now.
 153  */
 154 #define CMD_POLL_N_TRIES                60
 155
 156 enum {
 157         CMD_TIME_CLASS_A = 60 * HZ,
 158         CMD_TIME_CLASS_B = 60 * HZ,
 159         CMD_TIME_CLASS_C = 60 * HZ
 160 };
 161
 162 enum {
 163         GO_BIT_TIMEOUT = 10 * HZ
 164 };
 165
 166 #define GO_BIT_N_TRIES          5
 167 #define GO_BIT_STALL_TIMEOUT            ((GO_BIT_TIMEOUT/HZ)/GO_BIT_N_TRIES)            /* usecs */
 168
 169 struct mthca_cmd_context {
 170         KEVENT  event;
 171         int               result;
 172         int               next;
 173         u64               out_param;
 174         u16               token;
 175         u8                status;
 176 };
 177
 178 static inline int go_bit(struct mthca_dev *dev)
 179 {
 180         return readl(dev->hcr + HCR_STATUS_OFFSET) &
 181                 _byteswap_ulong(1 << HCR_GO_BIT);
 182 }
 183
 184 /*
 185 *       Function: performs busy-wait loop, while polling GO bit
 186 *       Return: 0 when GO bit was extinguished in time
 187 */
 188 static int poll_go_bit(struct mthca_dev *dev)
 189 {
 190         int i=0; /* init must be here !*/
 191
 192         if (!go_bit(dev))
 193                 return 0;
 194
 195         for (; i<GO_BIT_N_TRIES; i++) {
 196                 /* Nope, stall for a little bit and try again. */
 197                 KeStallExecutionProcessor( GO_BIT_STALL_TIMEOUT );
 198                 if (!go_bit(dev))
 199                         return 0;
 200         }
 201
 202         return 1;
 203 }
 204
 205 /*
 206 * Function: put thread on hold, while polling GO bit
 207 * Return: 0 when GO bit was extinguished in time
 208 * Note: the functions make c. CMD_POLL_N_TRIES polls
 209 */
 210 static int wait_go_bit(struct mthca_dev *dev, unsigned long timeout_usecs)
 211 {
 212         u64 start, end;
 213         LARGE_INTEGER  interval;
 214
 215         if (!go_bit(dev))       return 0;
 216
 217         interval.QuadPart = -(__int64)(((u64)(timeout_usecs) * 10) /    CMD_POLL_N_TRIES);
 218         start = cl_get_time_stamp();
 219         end = start + timeout_usecs;
 220         while (go_bit(dev) && (cl_get_time_stamp() < end)) {
 221                 KeDelayExecutionThread( KernelMode, FALSE, &interval );
 222         }
 223
 224         if (!go_bit(dev))       return 0;
 225         return 1;
 226 }
 227
 228
 229 static int mthca_cmd_post(struct mthca_dev *dev,
 230                           u64 in_param,
 231                           u64 out_param,
 232                           u32 in_modifier,
 233                           u8 op_modifier,
 234                           u16 op,
 235                           u16 token,
 236                           int event)
 237 {
 238         int err = 0;
 239
 240         down(&dev->cmd.hcr_mutex);
 241
 242         if (event && wait_go_bit(dev,GO_BIT_TIMEOUT)) {
 243                 err = -EAGAIN;
 244                 goto out;
 245         }
 246
 247         /*
 248          * We use writel (instead of something like memcpy_toio)
 249          * because writes of less than 32 bits to the HCR don't work
 250          * (and some architectures such as ia64 implement memcpy_toio
 251          * in terms of writeb).
 252          */
 253         __raw_writel((u32) cl_hton32((u32)(in_param >> 32)),           (u8 *)dev->hcr + 0 * 4);
 254         __raw_writel((u32) cl_hton32((u32)(in_param & 0xfffffffful)), (u8 *) dev->hcr + 1 * 4);
 255         __raw_writel((u32) cl_hton32(in_modifier),              (u8 *)dev->hcr + 2 * 4);
 256         __raw_writel((u32) cl_hton32((u32)(out_param >> 32)),          (u8 *)dev->hcr + 3 * 4);
 257         __raw_writel((u32) cl_hton32((u32)(out_param & 0xfffffffful)), (u8 *)dev->hcr + 4 * 4);
 258         __raw_writel((u32) cl_hton32(token << 16),              (u8 *)dev->hcr + 5 * 4);
 259
 260         /* __raw_writel may not order writes. */
 261         wmb();
 262
 263         __raw_writel((u32) cl_hton32((1 << HCR_GO_BIT)                |
 264                                                (event ? (1 << HCA_E_BIT) : 0)   |
 265                                                (op_modifier << HCR_OPMOD_SHIFT) |
 266                                                op),                       (u8 *)dev->hcr + 6 * 4);
 267
 268 out:
 269         up(&dev->cmd.hcr_mutex);
 270         return err;
 271 }
 272
 273
 274 static int mthca_cmd_poll(struct mthca_dev *dev,
 275                           u64 in_param,
 276                           u64 *out_param,
 277                           int out_is_imm,
 278                           u32 in_modifier,
 279                           u8 op_modifier,
 280                           u16 op,
 281                           unsigned long timeout,
 282                           u8 *status)
 283 {
 284         int err = 0;
 285
 286         sem_down(&dev->cmd.poll_sem);
 287
 288         err = mthca_cmd_post(dev, in_param,
 289                              out_param ? *out_param : 0,
 290                              in_modifier, op_modifier,
 291                              op, CMD_POLL_TOKEN, 0);
 292         if (err)
 293                 goto out;
 294
 295         if (wait_go_bit(dev,timeout)) {
 296                 err = -EBUSY;
 297                 goto out;
 298         }
 299
 300         if (out_is_imm)
 301                 *out_param =
 302                         (u64) cl_ntoh32((__be32)
 303                                           __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
 304                         (u64) cl_ntoh32((__be32)
 305                                           __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET + 4));
 306
 307         *status = (u8)(cl_ntoh32((__be32) __raw_readl(dev->hcr + HCR_STATUS_OFFSET)) >> 24);
 308         if (*status)
 309                 HCA_PRINT(TRACE_LEVEL_VERBOSE,HCA_DBG_LOW,("mthca_cmd_wait: Command %02x completed with status %02x\n",
 310                           op, *status));
 311
 312 out:
 313         sem_up(&dev->cmd.poll_sem);
 314         return err;
 315 }
 316
 317 void mthca_cmd_event(struct mthca_dev *dev,
 318                      u16 token,
 319                      u8  status,
 320                      u64 out_param)
 321 {
 322         struct mthca_cmd_context *context =
 323                 &dev->cmd.context[token & dev->cmd.token_mask];
 324
 325         /* previously timed out command completing at long last */
 326         if (token != context->token)
 327                 return;
 328
 329         context->result    = 0;
 330         context->status    = status;
 331         context->out_param = out_param;
 332
 333         context->token += dev->cmd.token_mask + 1;
 334
 335         ASSERT(KeGetCurrentIrql() <= DISPATCH_LEVEL);
 336         KeSetEvent( &context->event, 0, FALSE );
 337 }
 338
 339 static int mthca_cmd_wait(struct mthca_dev *dev,
 340                           u64 in_param,
 341                           u64 *out_param,
 342                           int out_is_imm,
 343                           u32 in_modifier,
 344                           u8 op_modifier,
 345                           u16 op,
 346                           unsigned long timeout,
 347                           u8 *status)
 348 {
 349         int err = 0;
 350         struct mthca_cmd_context *context;
 351         SPIN_LOCK_PREP(lh);
 352
 353         sem_down(&dev->cmd.event_sem);
 354
 355         spin_lock( &dev->cmd.context_lock, &lh );
 356         BUG_ON(dev->cmd.free_head < 0);
 357         context = &dev->cmd.context[dev->cmd.free_head];
 358         dev->cmd.free_head = context->next;
 359         spin_unlock( &lh );
 360
 361         KeClearEvent(   &context->event );
 362         err = mthca_cmd_post(dev, in_param,
 363                              out_param ? *out_param : 0,
 364                              in_modifier, op_modifier,
 365                              op, context->token, 1);
 366         if (err)
 367                 goto out;
 368
 369         {
 370                 //TODO: Questions:
 371                 // Can it once be on behalf of user request, which would require UserRequest and UserMode
 372                 // Can it be alertable ?
 373                 NTSTATUS res;
 374                 LARGE_INTEGER  interval;
 375                 interval.QuadPart = (-10)* (__int64)timeout;
 376                 res = KeWaitForSingleObject( &context->event, Executive, KernelMode, FALSE,  &interval );
 377                 if (res != STATUS_SUCCESS) {
 378                         err = -EBUSY;
 379                         goto out;
 380                 }
 381         }
 382
 383         *status = context->status;
 384         if (*status)
 385                 HCA_PRINT(TRACE_LEVEL_VERBOSE,HCA_DBG_LOW,("mthca_cmd_wait: Command %02x completed with status %02x\n",
 386                           op, *status));
 387
 388         if (out_is_imm)
 389                 *out_param = context->out_param;
 390
 391 out:
 392         spin_lock(&dev->cmd.context_lock, &lh);
 393         context->next = dev->cmd.free_head;
 394         dev->cmd.free_head = (int)(context - dev->cmd.context);
 395         spin_unlock(&lh);
 396
 397         sem_up( &dev->cmd.event_sem );
 398
 399         return err;
 400 }
 401
 402 /* Invoke a command with an output mailbox */
 403 static int mthca_cmd_box(struct mthca_dev *dev,
 404                          u64 in_param,
 405                          u64 out_param,
 406                          u32 in_modifier,
 407                          u8 op_modifier,
 408                          u16 op,
 409                          unsigned long timeout,
 410                          u8 *status)
 411 {
 412         if (dev->cmd.use_events)
 413                 return mthca_cmd_wait(dev, in_param, &out_param, 0,
 414                                       in_modifier, op_modifier, op,
 415                                       timeout, status);
 416         else
 417                 return mthca_cmd_poll(dev, in_param, &out_param, 0,
 418                                       in_modifier, op_modifier, op,
 419                                       timeout, status);
 420 }
 421
 422 /* Invoke a command with no output parameter */
 423 static int mthca_cmd(struct mthca_dev *dev,
 424                      u64 in_param,
 425                      u32 in_modifier,
 426                      u8 op_modifier,
 427                      u16 op,
 428                      unsigned long timeout,
 429                      u8 *status)
 430 {
 431         return mthca_cmd_box(dev, in_param, 0, in_modifier,
 432                              op_modifier, op, timeout, status);
 433 }
 434
 435 /*
 436  * Invoke a command with an immediate output parameter (and copy the
 437  * output into the caller's out_param pointer after the command
 438  * executes).
 439  */
 440 static int mthca_cmd_imm(struct mthca_dev *dev,
 441                          u64 in_param,
 442                          u64 *out_param,
 443                          u32 in_modifier,
 444                          u8 op_modifier,
 445                          u16 op,
 446                          unsigned long timeout,
 447                          u8 *status)
 448 {
 449         if (dev->cmd.use_events)
 450                 return mthca_cmd_wait(dev, in_param, out_param, 1,
 451                                       in_modifier, op_modifier, op,
 452                                       timeout, status);
 453         else
 454                 return mthca_cmd_poll(dev, in_param, out_param, 1,
 455                                       in_modifier, op_modifier, op,
 456                                       timeout, status);
 457 }
 458
 459 int mthca_cmd_init(struct mthca_dev *dev)
 460 {
 461         KeInitializeMutex(&dev->cmd.hcr_mutex, 0);
 462         sem_init(&dev->cmd.poll_sem, 1, 1);
 463         dev->cmd.use_events = 0;
 464
 465         dev->hcr = ioremap(pci_resource_start(dev, HCA_BAR_TYPE_HCR) + MTHCA_HCR_BASE,
 466                            MTHCA_HCR_SIZE, &dev->hcr_size);
 467         if (!dev->hcr) {
 468                 HCA_PRINT(TRACE_LEVEL_ERROR  ,HCA_DBG_LOW  ,("Couldn't map command register."));
 469                 return -ENOMEM;
 470         }
 471
 472         dev->cmd.pool = pci_pool_create("mthca_cmd", dev,
 473                                         MTHCA_MAILBOX_SIZE,
 474                                         MTHCA_MAILBOX_SIZE, 0);
 475         if (!dev->cmd.pool) {
 476                 iounmap(dev->hcr, dev->hcr_size);
 477                 return -ENOMEM;
 478         }
 479
 480         return 0;
 481 }
 482
 483 void mthca_cmd_cleanup(struct mthca_dev *dev)
 484 {
 485         pci_pool_destroy(dev->cmd.pool);
 486         iounmap(dev->hcr, dev->hcr_size);
 487 }
 488
 489 /*
 490  * Switch to using events to issue FW commands (should be called after
 491  * event queue to command events has been initialized).
 492  */
 493 int mthca_cmd_use_events(struct mthca_dev *dev)
 494 {
 495         int i;
 496
 497         dev->cmd.context = kmalloc(dev->cmd.max_cmds *
 498                                    sizeof (struct mthca_cmd_context),
 499                                    GFP_KERNEL);
 500         if (!dev->cmd.context)
 501                 return -ENOMEM;
 502
 503         for (i = 0; i < dev->cmd.max_cmds; ++i) {
 504                 dev->cmd.context[i].token = (u16)i;
 505                 dev->cmd.context[i].next = i + 1;
 506         KeInitializeEvent(      &dev->cmd.context[i].event, NotificationEvent , FALSE );
 507         }
 508
 509         dev->cmd.context[dev->cmd.max_cmds - 1].next = -1;
 510         dev->cmd.free_head = 0;
 511
 512         sem_init(&dev->cmd.event_sem, dev->cmd.max_cmds, LONG_MAX);
 513         spin_lock_init(&dev->cmd.context_lock);
 514
 515         for (dev->cmd.token_mask = 1;
 516              dev->cmd.token_mask < dev->cmd.max_cmds;
 517              dev->cmd.token_mask <<= 1)
 518                 ; /* nothing */
 519         --dev->cmd.token_mask;
 520
 521         dev->cmd.use_events = 1;
 522         sem_down(&dev->cmd.poll_sem);
 523
 524         return 0;
 525 }
 526
 527 /*
 528  * Switch back to polling (used when shutting down the device)
 529  */
 530 void mthca_cmd_use_polling(struct mthca_dev *dev)
 531 {
 532         int i;
 533
 534         dev->cmd.use_events = 0;
 535
 536         for (i = 0; i < dev->cmd.max_cmds; ++i)
 537                 sem_down(&dev->cmd.event_sem);
 538
 539         kfree(dev->cmd.context);
 540
 541         sem_up(&dev->cmd.poll_sem);
 542 }
 543
 544 struct mthca_mailbox *mthca_alloc_mailbox(struct mthca_dev *dev,
 545                                           unsigned int gfp_mask)
 546 {
 547         struct mthca_mailbox *mailbox;
 548
 549         mailbox = kmalloc(sizeof *mailbox, gfp_mask);
 550         if (!mailbox)
 551                 return ERR_PTR(-ENOMEM);
 552
 553         mailbox->buf = pci_pool_alloc(dev->cmd.pool, gfp_mask, &mailbox->dma);
 554         if (!mailbox->buf) {
 555                 kfree(mailbox);
 556                 return ERR_PTR(-ENOMEM);
 557         }
 558
 559         return mailbox;
 560 }
 561
 562 void mthca_free_mailbox(struct mthca_dev *dev, struct mthca_mailbox *mailbox)
 563 {
 564         if (!mailbox)
 565                 return;
 566
 567         pci_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
 568         kfree(mailbox);
 569 }
 570
 571 int mthca_SYS_EN(struct mthca_dev *dev, u8 *status)
 572 {
 573         u64 out;
 574         int ret;
 575
 576         ret = mthca_cmd_imm(dev, 0, &out, 0, 0, CMD_SYS_EN, HZ, status);
 577
 578         if (*status == MTHCA_CMD_STAT_DDR_MEM_ERR)
 579                 HCA_PRINT(TRACE_LEVEL_WARNING,HCA_DBG_LOW,("SYS_EN DDR error: syn=%x, sock=%d, "
 580                            "sladdr=%d, SPD source=%s\n",
 581                            (int) (out >> 6) & 0xf, (int) (out >> 4) & 3,
 582                            (int) (out >> 1) & 7, (int) out & 1 ? "NVMEM" : "DIMM"));
 583
 584         return ret;
 585 }
 586
 587 int mthca_SYS_DIS(struct mthca_dev *dev, u8 *status)
 588 {
 589         return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, HZ, status);
 590 }
 591
 592 static int mthca_map_cmd(struct mthca_dev *dev, u16 op, struct mthca_icm *icm,
 593                          u64 virt, u8 *status)
 594 {
 595         struct mthca_mailbox *mailbox;
 596         struct mthca_icm_iter iter;
 597         __be64 *pages;
 598         int lg;
 599         int nent = 0;
 600         unsigned long i;
 601         int err = 0;
 602         int ts = 0, tc = 0;
 603         CPU_2_BE64_PREP;
 604
 605         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 606         if (IS_ERR(mailbox))
 607                 return PTR_ERR(mailbox);
 608         RtlZeroMemory(mailbox->buf, MTHCA_MAILBOX_SIZE);
 609         pages = mailbox->buf;
 610
 611         for (mthca_icm_first(icm, &iter);
 612              !mthca_icm_last(&iter);
 613              mthca_icm_next(&iter)) {
 614                 /*
 615                  * We have to pass pages that are aligned to their
 616                  * size, so find the least significant 1 in the
 617                  * address or size and use that as our log2 size.
 618                  */
 619                 i = (u32)mthca_icm_addr(&iter) | mthca_icm_size(&iter);
 620                 lg = ffs(i) - 1;
 621                 if (lg < 12) {
 622                         HCA_PRINT(TRACE_LEVEL_WARNING ,HCA_DBG_LOW ,("Got FW area not aligned to 4K (%I64x/%lx).\n",
 623                                    (unsigned long long) mthca_icm_addr(&iter),
 624                                    mthca_icm_size(&iter)));
 625                         err = -EINVAL;
 626                         goto out;
 627                 }
 628                 for (i = 0; i < mthca_icm_size(&iter) >> lg; ++i) {
 629                         if (virt != -1) {
 630                                 pages[nent * 2] = cl_hton64(virt);
 631                                 virt += 1ULL << lg;
 632                         }
 633                         pages[nent * 2 + 1] = CPU_2_BE64((mthca_icm_addr(&iter) +
 634                                                            (i << lg)) | (lg - 12));
 635                         ts += 1 << (lg - 10);
 636                         ++tc;
 637
 638                         if (++nent == MTHCA_MAILBOX_SIZE / 16) {
 639                                 err = mthca_cmd(dev, mailbox->dma, nent, 0, op,
 640                                                 CMD_TIME_CLASS_B, status);
 641                                 if (err || *status)
 642                                         goto out;
 643                                 nent = 0;
 644                         }
 645                 }
 646         }
 647
 648         if (nent)
 649                 err = mthca_cmd(dev, mailbox->dma, nent, 0, op,
 650                                 CMD_TIME_CLASS_B, status);
 651
 652         switch (op) {
 653         case CMD_MAP_FA:
 654                 HCA_PRINT(TRACE_LEVEL_VERBOSE  ,HCA_DBG_LOW  ,("Mapped %d chunks/%d KB for FW.\n", tc, ts));
 655                 break;
 656         case CMD_MAP_ICM_AUX:
 657                 HCA_PRINT(TRACE_LEVEL_VERBOSE  ,HCA_DBG_LOW  ,("Mapped %d chunks/%d KB for ICM aux.\n", tc, ts));
 658                 break;
 659         case CMD_MAP_ICM:
 660                 HCA_PRINT(TRACE_LEVEL_VERBOSE,HCA_DBG_LOW,("Mapped %d chunks/%d KB at %I64x for ICM.\n",
 661                           tc, ts, (unsigned long long) virt - (ts << 10)));
 662                 break;
 663         }
 664
 665 out:
 666         mthca_free_mailbox(dev, mailbox);
 667         return err;
 668 }
 669
 670 int mthca_MAP_FA(struct mthca_dev *dev, struct mthca_icm *icm, u8 *status)
 671 {
 672         return mthca_map_cmd(dev, CMD_MAP_FA, icm, (u64)-1, status);
 673 }
 674
 675 int mthca_UNMAP_FA(struct mthca_dev *dev, u8 *status)
 676 {
 677         return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_FA, CMD_TIME_CLASS_B, status);
 678 }
 679
 680 int mthca_RUN_FW(struct mthca_dev *dev, u8 *status)
 681 {
 682         return mthca_cmd(dev, 0, 0, 0, CMD_RUN_FW, CMD_TIME_CLASS_A, status);
 683 }
 684
 685 int mthca_QUERY_FW(struct mthca_dev *dev, u8 *status)
 686 {
 687         struct mthca_mailbox *mailbox;
 688         u32 *outbox;
 689         int err = 0;
 690         u8 lg;
 691
 692 #define QUERY_FW_OUT_SIZE             0x100
 693 #define QUERY_FW_VER_OFFSET            0x00
 694 #define QUERY_FW_MAX_CMD_OFFSET        0x0f
 695 #define QUERY_FW_ERR_START_OFFSET      0x30
 696 #define QUERY_FW_ERR_SIZE_OFFSET       0x38
 697
 698 #define QUERY_FW_START_OFFSET          0x20
 699 #define QUERY_FW_END_OFFSET            0x28
 700
 701 #define QUERY_FW_SIZE_OFFSET           0x00
 702 #define QUERY_FW_CLR_INT_BASE_OFFSET   0x20
 703 #define QUERY_FW_EQ_ARM_BASE_OFFSET    0x40
 704 #define QUERY_FW_EQ_SET_CI_BASE_OFFSET 0x48
 705
 706         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 707         if (IS_ERR(mailbox))
 708                 return PTR_ERR(mailbox);
 709         outbox = mailbox->buf;
 710
 711         err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_FW,
 712                             CMD_TIME_CLASS_A, status);
 713
 714         if (err)
 715                 goto out;
 716
 717         MTHCA_GET(dev->fw_ver,   outbox, QUERY_FW_VER_OFFSET);
 718         /*
 719          * FW subSIZE_Tor version is at more signifant bits than minor
 720          * version, so swap here.
 721          */
 722         dev->fw_ver = (dev->fw_ver & 0xffff00000000ull) |
 723                 ((dev->fw_ver & 0xffff0000ull) >> 16) |
 724                 ((dev->fw_ver & 0x0000ffffull) << 16);
 725
 726         MTHCA_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
 727         dev->cmd.max_cmds = 1 << lg;
 728         MTHCA_GET(dev->catas_err.addr, outbox, QUERY_FW_ERR_START_OFFSET);
 729         MTHCA_GET(dev->catas_err.size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
 730
 731         HCA_PRINT(TRACE_LEVEL_VERBOSE,HCA_DBG_LOW,("FW version %012I64x, max commands %d\n",
 732                   (unsigned long long) dev->fw_ver, dev->cmd.max_cmds));
 733         HCA_PRINT(TRACE_LEVEL_VERBOSE,HCA_DBG_LOW,("Catastrophic error buffer at 0x%I64x, size 0x%x\n",
 734                 (unsigned long long) dev->catas_err.addr, dev->catas_err.size));
 735
 736
 737         if (mthca_is_memfree(dev)) {
 738                 MTHCA_GET(dev->fw.arbel.fw_pages,       outbox, QUERY_FW_SIZE_OFFSET);
 739                 MTHCA_GET(dev->fw.arbel.clr_int_base,   outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
 740                 MTHCA_GET(dev->fw.arbel.eq_arm_base,    outbox, QUERY_FW_EQ_ARM_BASE_OFFSET);
 741                 MTHCA_GET(dev->fw.arbel.eq_set_ci_base, outbox, QUERY_FW_EQ_SET_CI_BASE_OFFSET);
 742                 HCA_PRINT(TRACE_LEVEL_VERBOSE  ,HCA_DBG_LOW  ,("FW size %d KB\n", dev->fw.arbel.fw_pages << 2));
 743
 744                 /*
 745                  * Arbel page size is always 4 KB; round up number of
 746                  * system pages needed.
 747                  */
 748                 dev->fw.arbel.fw_pages =
 749                         ALIGN(dev->fw.arbel.fw_pages, PAGE_SIZE >> 12) >>
 750                                 (PAGE_SHIFT - 12);
 751
 752                 HCA_PRINT(TRACE_LEVEL_VERBOSE,HCA_DBG_LOW,("Clear int @ %I64x, EQ arm @ %I64x, EQ set CI @ %I64x\n",
 753                           (unsigned long long) dev->fw.arbel.clr_int_base,
 754                           (unsigned long long) dev->fw.arbel.eq_arm_base,
 755                           (unsigned long long) dev->fw.arbel.eq_set_ci_base));
 756         } else {
 757                 MTHCA_GET(dev->fw.tavor.fw_start, outbox, QUERY_FW_START_OFFSET);
 758                 MTHCA_GET(dev->fw.tavor.fw_end,   outbox, QUERY_FW_END_OFFSET);
 759
 760                 HCA_PRINT(TRACE_LEVEL_VERBOSE,HCA_DBG_LOW,("FW size %d KB (start %I64x, end %I64x)\n",
 761                           (int) ((dev->fw.tavor.fw_end - dev->fw.tavor.fw_start) >> 10),
 762                           (unsigned long long) dev->fw.tavor.fw_start,
 763                           (unsigned long long) dev->fw.tavor.fw_end));
 764         }
 765
 766 out:
 767         mthca_free_mailbox(dev, mailbox);
 768         return err;
 769 }
 770
 771 int mthca_ENABLE_LAM(struct mthca_dev *dev, u8 *status)
 772 {
 773         struct mthca_mailbox *mailbox;
 774         u8 info;
 775         u32 *outbox;
 776         int err = 0;
 777
 778 #define ENABLE_LAM_OUT_SIZE         0x100
 779 #define ENABLE_LAM_START_OFFSET     0x00
 780 #define ENABLE_LAM_END_OFFSET       0x08
 781 #define ENABLE_LAM_INFO_OFFSET      0x13
 782
 783 #define ENABLE_LAM_INFO_HIDDEN_FLAG (1 << 4)
 784 #define ENABLE_LAM_INFO_ECC_MASK    0x3
 785
 786         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 787         if (IS_ERR(mailbox))
 788                 return PTR_ERR(mailbox);
 789         outbox = mailbox->buf;
 790
 791         err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_ENABLE_LAM,
 792                             CMD_TIME_CLASS_C, status);
 793
 794         if (err)
 795                 goto out;
 796
 797         if (*status == MTHCA_CMD_STAT_LAM_NOT_PRE)
 798                 goto out;
 799
 800         MTHCA_GET(dev->ddr_start, outbox, ENABLE_LAM_START_OFFSET);
 801         MTHCA_GET(dev->ddr_end,   outbox, ENABLE_LAM_END_OFFSET);
 802         MTHCA_GET(info,           outbox, ENABLE_LAM_INFO_OFFSET);
 803
 804         if (!!(info & ENABLE_LAM_INFO_HIDDEN_FLAG) !=
 805             !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) {
 806                 HCA_PRINT(TRACE_LEVEL_INFORMATION ,HCA_DBG_LOW ,("FW reports that HCA-attached memory "
 807                            "is %s hidden; does not match PCI config\n",
 808                            (info & ENABLE_LAM_INFO_HIDDEN_FLAG)?
 809                            "" : "not"));
 810         }
 811         if (info & ENABLE_LAM_INFO_HIDDEN_FLAG)
 812                 HCA_PRINT(TRACE_LEVEL_VERBOSE  ,HCA_DBG_LOW  ,("HCA-attached memory is hidden.\n"));
 813
 814         HCA_PRINT(TRACE_LEVEL_VERBOSE,HCA_DBG_LOW,("HCA memory size %d KB (start %I64x, end %I64x)\n",
 815                   (int) ((dev->ddr_end - dev->ddr_start) >> 10),
 816                   (unsigned long long) dev->ddr_start,
 817                   (unsigned long long) dev->ddr_end));
 818
 819 out:
 820         mthca_free_mailbox(dev, mailbox);
 821         return err;
 822 }
 823
 824 int mthca_DISABLE_LAM(struct mthca_dev *dev, u8 *status)
 825 {
 826         return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, CMD_TIME_CLASS_C, status);
 827 }
 828
 829 int mthca_QUERY_DDR(struct mthca_dev *dev, u8 *status)
 830 {
 831         struct mthca_mailbox *mailbox;
 832         u8 info;
 833         u32 *outbox;
 834         int err = 0;
 835
 836 #define QUERY_DDR_OUT_SIZE         0x100
 837 #define QUERY_DDR_START_OFFSET     0x00
 838 #define QUERY_DDR_END_OFFSET       0x08
 839 #define QUERY_DDR_INFO_OFFSET      0x13
 840
 841 #define QUERY_DDR_INFO_HIDDEN_FLAG (1 << 4)
 842 #define QUERY_DDR_INFO_ECC_MASK    0x3
 843
 844         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 845         if (IS_ERR(mailbox))
 846                 return PTR_ERR(mailbox);
 847         outbox = mailbox->buf;
 848
 849         err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DDR,
 850                             CMD_TIME_CLASS_A, status);
 851
 852         if (err)
 853                 goto out;
 854
 855         MTHCA_GET(dev->ddr_start, outbox, QUERY_DDR_START_OFFSET);
 856         MTHCA_GET(dev->ddr_end,   outbox, QUERY_DDR_END_OFFSET);
 857         MTHCA_GET(info,           outbox, QUERY_DDR_INFO_OFFSET);
 858
 859         if (!!(info & QUERY_DDR_INFO_HIDDEN_FLAG) !=
 860             !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) {
 861
 862                 HCA_PRINT(TRACE_LEVEL_INFORMATION ,HCA_DBG_LOW ,("FW reports that HCA-attached memory "
 863                            "is %s hidden; does not match PCI config\n",
 864                            (info & QUERY_DDR_INFO_HIDDEN_FLAG) ?
 865                            "" : "not"));
 866         }
 867         if (info & QUERY_DDR_INFO_HIDDEN_FLAG)
 868                 HCA_PRINT(TRACE_LEVEL_VERBOSE  ,HCA_DBG_LOW  ,("HCA-attached memory is hidden.\n"));
 869
 870         HCA_PRINT(TRACE_LEVEL_VERBOSE,HCA_DBG_LOW,("HCA memory size %d KB (start %I64x, end %I64x)\n",
 871                   (int) ((dev->ddr_end - dev->ddr_start) >> 10),
 872                   (unsigned long long) dev->ddr_start,
 873                   (unsigned long long) dev->ddr_end));
 874
 875 out:
 876         mthca_free_mailbox(dev, mailbox);
 877         return err;
 878 }
 879
 880 int mthca_QUERY_DEV_LIM(struct mthca_dev *dev,
 881                         struct mthca_dev_lim *dev_lim, u8 *status)
 882 {
 883         struct mthca_mailbox *mailbox;
 884         u32 *outbox;
 885         u8 field;
 886         u16 size;
 887         int err;
 888
 889 #define QUERY_DEV_LIM_OUT_SIZE             0x100
 890 #define QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET     0x10
 891 #define QUERY_DEV_LIM_MAX_QP_SZ_OFFSET      0x11
 892 #define QUERY_DEV_LIM_RSVD_QP_OFFSET        0x12
 893 #define QUERY_DEV_LIM_MAX_QP_OFFSET         0x13
 894 #define QUERY_DEV_LIM_RSVD_SRQ_OFFSET       0x14
 895 #define QUERY_DEV_LIM_MAX_SRQ_OFFSET        0x15
 896 #define QUERY_DEV_LIM_RSVD_EEC_OFFSET       0x16
 897 #define QUERY_DEV_LIM_MAX_EEC_OFFSET        0x17
 898 #define QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET      0x19
 899 #define QUERY_DEV_LIM_RSVD_CQ_OFFSET        0x1a
 900 #define QUERY_DEV_LIM_MAX_CQ_OFFSET         0x1b
 901 #define QUERY_DEV_LIM_MAX_MPT_OFFSET        0x1d
 902 #define QUERY_DEV_LIM_RSVD_EQ_OFFSET        0x1e
 903 #define QUERY_DEV_LIM_MAX_EQ_OFFSET         0x1f
 904 #define QUERY_DEV_LIM_RSVD_MTT_OFFSET       0x20
 905 #define QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET     0x21
 906 #define QUERY_DEV_LIM_RSVD_MRW_OFFSET       0x22
 907 #define QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET    0x23
 908 #define QUERY_DEV_LIM_MAX_AV_OFFSET         0x27
 909 #define QUERY_DEV_LIM_MAX_REQ_QP_OFFSET     0x29
 910 #define QUERY_DEV_LIM_MAX_RES_QP_OFFSET     0x2b
 911 #define QUERY_DEV_LIM_MAX_RDMA_OFFSET       0x2f
 912 #define QUERY_DEV_LIM_RSZ_SRQ_OFFSET        0x33
 913 #define QUERY_DEV_LIM_ACK_DELAY_OFFSET      0x35
 914 #define QUERY_DEV_LIM_MTU_WIDTH_OFFSET      0x36
 915 #define QUERY_DEV_LIM_VL_PORT_OFFSET        0x37
 916 #define QUERY_DEV_LIM_MAX_GID_OFFSET        0x3b
 917 #define QUERY_DEV_LIM_MAX_PKEY_OFFSET       0x3f
 918 #define QUERY_DEV_LIM_FLAGS_OFFSET          0x44
 919 #define QUERY_DEV_LIM_RSVD_UAR_OFFSET       0x48
 920 #define QUERY_DEV_LIM_UAR_SZ_OFFSET         0x49
 921 #define QUERY_DEV_LIM_PAGE_SZ_OFFSET        0x4b
 922 #define QUERY_DEV_LIM_MAX_SG_OFFSET         0x51
 923 #define QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET    0x52
 924 #define QUERY_DEV_LIM_MAX_SG_RQ_OFFSET      0x55
 925 #define QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET 0x56
 926 #define QUERY_DEV_LIM_MAX_QP_MCG_OFFSET     0x61
 927 #define QUERY_DEV_LIM_RSVD_MCG_OFFSET       0x62
 928 #define QUERY_DEV_LIM_MAX_MCG_OFFSET        0x63
 929 #define QUERY_DEV_LIM_RSVD_PD_OFFSET        0x64
 930 #define QUERY_DEV_LIM_MAX_PD_OFFSET         0x65
 931 #define QUERY_DEV_LIM_RSVD_RDD_OFFSET       0x66
 932 #define QUERY_DEV_LIM_MAX_RDD_OFFSET        0x67
 933 #define QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET   0x80
 934 #define QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET   0x82
 935 #define QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET  0x84
 936 #define QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET  0x86
 937 #define QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET   0x88
 938 #define QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET   0x8a
 939 #define QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET   0x8c
 940 #define QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET   0x8e
 941 #define QUERY_DEV_LIM_MTT_ENTRY_SZ_OFFSET   0x90
 942 #define QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET   0x92
 943 #define QUERY_DEV_LIM_PBL_SZ_OFFSET         0x96
 944 #define QUERY_DEV_LIM_BMME_FLAGS_OFFSET     0x97
 945 #define QUERY_DEV_LIM_RSVD_LKEY_OFFSET      0x98
 946 #define QUERY_DEV_LIM_LAMR_OFFSET           0x9f
 947 #define QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET     0xa0
 948
 949         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 950         if (IS_ERR(mailbox))
 951                 return PTR_ERR(mailbox);
 952         outbox = mailbox->buf;
 953
 954         err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DEV_LIM,
 955                             CMD_TIME_CLASS_A, status);
 956
 957         if (err)
 958                 goto out;
 959
 960         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_QP_OFFSET);
 961         dev_lim->reserved_qps = 1 << (field & 0xf);
 962         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_OFFSET);
 963         dev_lim->max_qps = 1 << (field & 0x1f);
 964         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_SRQ_OFFSET);
 965         dev_lim->reserved_srqs = 1 << (field >> 4);
 966         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_OFFSET);
 967         dev_lim->max_srqs = 1 << (field & 0x1f);
 968         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EEC_OFFSET);
 969         dev_lim->reserved_eecs = 1 << (field & 0xf);
 970         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EEC_OFFSET);
 971         dev_lim->max_eecs = 1 << (field & 0x1f);
 972         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET);
 973         dev_lim->max_cq_sz = 1 << field;
 974         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_CQ_OFFSET);
 975         dev_lim->reserved_cqs = 1 << (field & 0xf);
 976         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_OFFSET);
 977         dev_lim->max_cqs = 1 << (field & 0x1f);
 978         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MPT_OFFSET);
 979         dev_lim->max_mpts = 1 << (field & 0x3f);
 980         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EQ_OFFSET);
 981         dev_lim->reserved_eqs = 1 << (field & 0xf);
 982         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EQ_OFFSET);
 983         dev_lim->max_eqs = 1 << (field & 0x7);
 984         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MTT_OFFSET);
 985         dev_lim->reserved_mtts = 1 << (field >> 4);
 986         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET);
 987         dev_lim->max_mrw_sz = 1 << field;
 988         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MRW_OFFSET);
 989         dev_lim->reserved_mrws = 1 << (field & 0xf);
 990         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET);
 991         dev_lim->max_mtt_seg = 1 << (field & 0x3f);
 992         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_REQ_QP_OFFSET);
 993         dev_lim->max_requester_per_qp = 1 << (field & 0x3f);
 994         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RES_QP_OFFSET);
 995         dev_lim->max_responder_per_qp = 1 << (field & 0x3f);
 996         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDMA_OFFSET);
 997         dev_lim->max_rdma_global = 1 << (field & 0x3f);
 998         MTHCA_GET(field, outbox, QUERY_DEV_LIM_ACK_DELAY_OFFSET);
 999         dev_lim->local_ca_ack_delay = field & 0x1f;
1000         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MTU_WIDTH_OFFSET);
1001         dev_lim->max_mtu        = field >> 4;
1002         dev_lim->max_port_width = field & 0xf;
1003         MTHCA_GET(field, outbox, QUERY_DEV_LIM_VL_PORT_OFFSET);
1004         dev_lim->max_vl    = field >> 4;
1005         dev_lim->num_ports = field & 0xf;
1006         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_GID_OFFSET);
1007         dev_lim->max_gids = 1 << (field & 0xf);
1008         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PKEY_OFFSET);
1009         dev_lim->max_pkeys = 1 << (field & 0xf);
1010         MTHCA_GET(dev_lim->flags, outbox, QUERY_DEV_LIM_FLAGS_OFFSET);
1011         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_UAR_OFFSET);
1012         dev_lim->reserved_uars = field >> 4;
1013         MTHCA_GET(field, outbox, QUERY_DEV_LIM_UAR_SZ_OFFSET);
1014         dev_lim->uar_size = 1 << ((field & 0x3f) + 20);
1015         MTHCA_GET(field, outbox, QUERY_DEV_LIM_PAGE_SZ_OFFSET);
1016         dev_lim->min_page_sz = 1 << field;
1017         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_OFFSET);
1018         dev_lim->max_sg = field;
1019
1020         MTHCA_GET(size, outbox, QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET);
1021         dev_lim->max_desc_sz = size;
1022
1023         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_MCG_OFFSET);
1024         dev_lim->max_qp_per_mcg = 1 << field;
1025         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MCG_OFFSET);
1026         dev_lim->reserved_mgms = field & 0xf;
1027         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MCG_OFFSET);
1028         dev_lim->max_mcgs = 1 << field;
1029         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_PD_OFFSET);
1030         dev_lim->reserved_pds = field >> 4;
1031         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PD_OFFSET);
1032         dev_lim->max_pds = 1 << (field & 0x3f);
1033         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_RDD_OFFSET);
1034         dev_lim->reserved_rdds = field >> 4;
1035         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDD_OFFSET);
1036         dev_lim->max_rdds = 1 << (field & 0x3f);
1037
1038         MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET);
1039         dev_lim->eec_entry_sz = size;
1040         MTHCA_GET(size, outbox, QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET);
1041         dev_lim->qpc_entry_sz = size;
1042         MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET);
1043         dev_lim->eeec_entry_sz = size;
1044         MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET);
1045         dev_lim->eqpc_entry_sz = size;
1046         MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET);
1047         dev_lim->eqc_entry_sz = size;
1048         MTHCA_GET(size, outbox, QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET);
1049         dev_lim->cqc_entry_sz = size;
1050         MTHCA_GET(size, outbox, QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET);
1051         dev_lim->srq_entry_sz = size;
1052         MTHCA_GET(size, outbox, QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET);
1053         dev_lim->uar_scratch_entry_sz = size;
1054
1055         if (mthca_is_memfree(dev)) {
1056                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET);
1057                 dev_lim->max_srq_sz = 1 << field;
1058                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET);
1059                 dev_lim->max_qp_sz = 1 << field;
1060                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSZ_SRQ_OFFSET);
1061                 dev_lim->hca.arbel.resize_srq = field & 1;
1062                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_RQ_OFFSET);
1063                 dev_lim->max_sg = min(field, dev_lim->max_sg);
1064                 MTHCA_GET(size, outbox, QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET);
1065                 dev_lim->max_desc_sz = min((int)size, dev_lim->max_desc_sz);
1066                 MTHCA_GET(size, outbox, QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET);
1067                 dev_lim->mpt_entry_sz = size;
1068                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_PBL_SZ_OFFSET);
1069                 dev_lim->hca.arbel.max_pbl_sz = 1 << (field & 0x3f);
1070                 MTHCA_GET(dev_lim->hca.arbel.bmme_flags, outbox,
1071                           QUERY_DEV_LIM_BMME_FLAGS_OFFSET);
1072                 MTHCA_GET(dev_lim->hca.arbel.reserved_lkey, outbox,
1073                           QUERY_DEV_LIM_RSVD_LKEY_OFFSET);
1074                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_LAMR_OFFSET);
1075                 dev_lim->hca.arbel.lam_required = field & 1;
1076                 MTHCA_GET(dev_lim->hca.arbel.max_icm_sz, outbox,
1077                           QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET);
1078
1079                 if (dev_lim->hca.arbel.bmme_flags & 1){
1080                         HCA_PRINT(TRACE_LEVEL_VERBOSE,HCA_DBG_LOW,("Base MM extensions: yes "
1081                                   "(flags %d, max PBL %d, rsvd L_Key %08x)\n",
1082                                   dev_lim->hca.arbel.bmme_flags,
1083                                   dev_lim->hca.arbel.max_pbl_sz,
1084                                   dev_lim->hca.arbel.reserved_lkey));
1085                 }else{
1086                         HCA_PRINT(TRACE_LEVEL_VERBOSE  ,HCA_DBG_LOW  ,("Base MM extensions: no\n"));
1087                 }
1088
1089                 HCA_PRINT(TRACE_LEVEL_VERBOSE,HCA_DBG_LOW,("Max ICM size %I64d MB\n",
1090                           (unsigned long long) dev_lim->hca.arbel.max_icm_sz >> 20));
1091         }
1092         else {
1093                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET);
1094                 dev_lim->max_srq_sz = (1 << field) - 1;
1095                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET);
1096                 dev_lim->max_qp_sz = (1 << field) - 1;
1097                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_AV_OFFSET);
1098                 dev_lim->hca.tavor.max_avs = 1 << (field & 0x3f);
1099                 dev_lim->mpt_entry_sz = MTHCA_MPT_ENTRY_SIZE;
1100         }
1101
1102         HCA_PRINT(TRACE_LEVEL_VERBOSE,HCA_DBG_LOW,("Max QPs: %d, reserved QPs: %d, entry size: %d\n",
1103                   dev_lim->max_qps, dev_lim->reserved_qps, dev_lim->qpc_entry_sz));
1104         HCA_PRINT(TRACE_LEVEL_VERBOSE,HCA_DBG_LOW,("Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
1105                   dev_lim->max_srqs, dev_lim->reserved_srqs, dev_lim->srq_entry_sz));
1106         HCA_PRINT(TRACE_LEVEL_VERBOSE,HCA_DBG_LOW,("Max CQs: %d, reserved CQs: %d, entry size: %d\n",
1107                   dev_lim->max_cqs, dev_lim->reserved_cqs, dev_lim->cqc_entry_sz));
1108         HCA_PRINT(TRACE_LEVEL_VERBOSE,HCA_DBG_LOW,("Max EQs: %d, reserved EQs: %d, entry size: %d\n",
1109                   dev_lim->max_eqs, dev_lim->reserved_eqs, dev_lim->eqc_entry_sz));
1110         HCA_PRINT(TRACE_LEVEL_VERBOSE,HCA_DBG_LOW,("reserved MPTs: %d, reserved MTTs: %d\n",
1111                   dev_lim->reserved_mrws, dev_lim->reserved_mtts));
1112         HCA_PRINT(TRACE_LEVEL_VERBOSE,HCA_DBG_LOW,("Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
1113                   dev_lim->max_pds, dev_lim->reserved_pds, dev_lim->reserved_uars));
1114         HCA_PRINT(TRACE_LEVEL_VERBOSE,HCA_DBG_LOW,("Max QP/MCG: %d, reserved MGMs: %d\n",
1115                   dev_lim->max_pds, dev_lim->reserved_mgms));
1116         HCA_PRINT(TRACE_LEVEL_VERBOSE,HCA_DBG_LOW,("Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
1117                   dev_lim->max_cq_sz, dev_lim->max_qp_sz, dev_lim->max_srq_sz));
1118
1119         HCA_PRINT(TRACE_LEVEL_VERBOSE  ,HCA_DBG_LOW  ,("Flags: %08x\n", dev_lim->flags));
1120
1121 out:
1122         mthca_free_mailbox(dev, mailbox);
1123         return err;
1124 }
1125
1126 static void get_board_id(u8 *vsd, char *board_id)
1127 {
1128         int i;
1129
1130 #define VSD_OFFSET_SIG1         0x00
1131 #define VSD_OFFSET_SIG2         0xde
1132 #define VSD_OFFSET_MLX_BOARD_ID 0xd0
1133 #define VSD_OFFSET_TS_BOARD_ID  0x20
1134
1135 #define VSD_SIGNATURE_TOPSPIN   0x5ad
1136
1137         RtlZeroMemory(board_id, MTHCA_BOARD_ID_LEN);
1138
1139         if (cl_ntoh16(*(u16*)(vsd + VSD_OFFSET_SIG1)) == VSD_SIGNATURE_TOPSPIN &&
1140             cl_ntoh16(*(u16*)(vsd + VSD_OFFSET_SIG2)) == VSD_SIGNATURE_TOPSPIN) {
1141                 strlcpy(board_id, (const char *)(vsd + VSD_OFFSET_TS_BOARD_ID), MTHCA_BOARD_ID_LEN);
1142         } else {
1143                 /*
1144                  * The board ID is a string but the firmware byte
1145                  * swaps each 4-byte word before passing it back to
1146                  * us.  Therefore we need to swab it before printing.
1147                  */
1148                 for (i = 0; i < 4; ++i)
1149                         ((u32 *) board_id)[i] =
1150                                 _byteswap_ulong(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
1151         }
1152 }
1153
1154 int mthca_QUERY_ADAPTER(struct mthca_dev *dev,
1155                         struct mthca_adapter *adapter, u8 *status)
1156 {
1157         struct mthca_mailbox *mailbox;
1158         u32 *outbox;
1159         int err;
1160
1161 #define QUERY_ADAPTER_OUT_SIZE             0x100
1162 #define QUERY_ADAPTER_VENDOR_ID_OFFSET     0x00
1163 #define QUERY_ADAPTER_DEVICE_ID_OFFSET     0x04
1164 #define QUERY_ADAPTER_REVISION_ID_OFFSET   0x08
1165 #define QUERY_ADAPTER_INTA_PIN_OFFSET      0x10
1166 #define QUERY_ADAPTER_VSD_OFFSET           0x20
1167
1168         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1169         if (IS_ERR(mailbox))
1170                 return PTR_ERR(mailbox);
1171         outbox = mailbox->buf;
1172
1173         err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_ADAPTER,
1174                             CMD_TIME_CLASS_A, status);
1175
1176         if (err)
1177                 goto out;
1178
1179         MTHCA_GET(adapter->vendor_id, outbox,   QUERY_ADAPTER_VENDOR_ID_OFFSET);
1180         MTHCA_GET(adapter->device_id, outbox,   QUERY_ADAPTER_DEVICE_ID_OFFSET);
1181         MTHCA_GET(adapter->revision_id, outbox, QUERY_ADAPTER_REVISION_ID_OFFSET);
1182         MTHCA_GET(adapter->inta_pin, outbox,    QUERY_ADAPTER_INTA_PIN_OFFSET);
1183
1184         get_board_id((u8*)outbox + QUERY_ADAPTER_VSD_OFFSET,
1185                      adapter->board_id);
1186
1187 out:
1188         mthca_free_mailbox(dev, mailbox);
1189         return err;
1190 }
1191
1192 int mthca_INIT_HCA(struct mthca_dev *dev,
1193                    struct mthca_init_hca_param *param,
1194                    u8 *status)
1195 {
1196         struct mthca_mailbox *mailbox;
1197         __be32 *inbox;
1198         int err;
1199
1200 #define INIT_HCA_IN_SIZE                 0x200
1201 #define INIT_HCA_FLAGS_OFFSET            0x014
1202 #define INIT_HCA_QPC_OFFSET              0x020
1203 #define  INIT_HCA_QPC_BASE_OFFSET        (INIT_HCA_QPC_OFFSET + 0x10)
1204 #define  INIT_HCA_LOG_QP_OFFSET          (INIT_HCA_QPC_OFFSET + 0x17)
1205 #define  INIT_HCA_EEC_BASE_OFFSET        (INIT_HCA_QPC_OFFSET + 0x20)
1206 #define  INIT_HCA_LOG_EEC_OFFSET         (INIT_HCA_QPC_OFFSET + 0x27)
1207 #define  INIT_HCA_SRQC_BASE_OFFSET       (INIT_HCA_QPC_OFFSET + 0x28)
1208 #define  INIT_HCA_LOG_SRQ_OFFSET         (INIT_HCA_QPC_OFFSET + 0x2f)
1209 #define  INIT_HCA_CQC_BASE_OFFSET        (INIT_HCA_QPC_OFFSET + 0x30)
1210 #define  INIT_HCA_LOG_CQ_OFFSET          (INIT_HCA_QPC_OFFSET + 0x37)
1211 #define  INIT_HCA_EQPC_BASE_OFFSET       (INIT_HCA_QPC_OFFSET + 0x40)
1212 #define  INIT_HCA_EEEC_BASE_OFFSET       (INIT_HCA_QPC_OFFSET + 0x50)
1213 #define  INIT_HCA_EQC_BASE_OFFSET        (INIT_HCA_QPC_OFFSET + 0x60)
1214 #define  INIT_HCA_LOG_EQ_OFFSET          (INIT_HCA_QPC_OFFSET + 0x67)
1215 #define  INIT_HCA_RDB_BASE_OFFSET        (INIT_HCA_QPC_OFFSET + 0x70)
1216 #define INIT_HCA_UDAV_OFFSET             0x0b0
1217 #define  INIT_HCA_UDAV_LKEY_OFFSET       (INIT_HCA_UDAV_OFFSET + 0x0)
1218 #define  INIT_HCA_UDAV_PD_OFFSET         (INIT_HCA_UDAV_OFFSET + 0x4)
1219 #define INIT_HCA_MCAST_OFFSET            0x0c0
1220 #define  INIT_HCA_MC_BASE_OFFSET         (INIT_HCA_MCAST_OFFSET + 0x00)
1221 #define  INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1222 #define  INIT_HCA_MC_HASH_SZ_OFFSET      (INIT_HCA_MCAST_OFFSET + 0x16)
1223 #define  INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
1224 #define INIT_HCA_TPT_OFFSET              0x0f0
1225 #define  INIT_HCA_MPT_BASE_OFFSET        (INIT_HCA_TPT_OFFSET + 0x00)
1226 #define  INIT_HCA_MTT_SEG_SZ_OFFSET      (INIT_HCA_TPT_OFFSET + 0x09)
1227 #define  INIT_HCA_LOG_MPT_SZ_OFFSET      (INIT_HCA_TPT_OFFSET + 0x0b)
1228 #define  INIT_HCA_MTT_BASE_OFFSET        (INIT_HCA_TPT_OFFSET + 0x10)
1229 #define INIT_HCA_UAR_OFFSET              0x120
1230 #define  INIT_HCA_UAR_BASE_OFFSET        (INIT_HCA_UAR_OFFSET + 0x00)
1231 #define  INIT_HCA_UARC_SZ_OFFSET         (INIT_HCA_UAR_OFFSET + 0x09)
1232 #define  INIT_HCA_LOG_UAR_SZ_OFFSET      (INIT_HCA_UAR_OFFSET + 0x0a)
1233 #define  INIT_HCA_UAR_PAGE_SZ_OFFSET     (INIT_HCA_UAR_OFFSET + 0x0b)
1234 #define  INIT_HCA_UAR_SCATCH_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x10)
1235 #define  INIT_HCA_UAR_CTX_BASE_OFFSET    (INIT_HCA_UAR_OFFSET + 0x18)
1236
1237         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1238         if (IS_ERR(mailbox))
1239                 return PTR_ERR(mailbox);
1240         inbox = mailbox->buf;
1241
1242         RtlZeroMemory(inbox, INIT_HCA_IN_SIZE);
1243
1244 #if defined(__LITTLE_ENDIAN)
1245         *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cl_hton32(1 << 1);
1246 #elif defined(__BIG_ENDIAN)
1247         *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cl_hton32(1 << 1);
1248 #else
1249 #error Host endianness not defined
1250 #endif
1251         /* Check port for UD address vector: */
1252         *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cl_hton32(1);
1253
1254         /* We leave wqe_quota, responder_exu, etc as 0 (default) */
1255
1256         /* QPC/EEC/CQC/EQC/RDB attributes */
1257
1258         MTHCA_PUT(inbox, param->qpc_base,     INIT_HCA_QPC_BASE_OFFSET);
1259         MTHCA_PUT(inbox, param->log_num_qps,  INIT_HCA_LOG_QP_OFFSET);
1260         MTHCA_PUT(inbox, param->eec_base,     INIT_HCA_EEC_BASE_OFFSET);
1261         MTHCA_PUT(inbox, param->log_num_eecs, INIT_HCA_LOG_EEC_OFFSET);
1262         MTHCA_PUT(inbox, param->srqc_base,    INIT_HCA_SRQC_BASE_OFFSET);
1263         MTHCA_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1264         MTHCA_PUT(inbox, param->cqc_base,     INIT_HCA_CQC_BASE_OFFSET);
1265         MTHCA_PUT(inbox, param->log_num_cqs,  INIT_HCA_LOG_CQ_OFFSET);
1266         MTHCA_PUT(inbox, param->eqpc_base,    INIT_HCA_EQPC_BASE_OFFSET);
1267         MTHCA_PUT(inbox, param->eeec_base,    INIT_HCA_EEEC_BASE_OFFSET);
1268         MTHCA_PUT(inbox, param->eqc_base,     INIT_HCA_EQC_BASE_OFFSET);
1269         MTHCA_PUT(inbox, param->log_num_eqs,  INIT_HCA_LOG_EQ_OFFSET);
1270         MTHCA_PUT(inbox, param->rdb_base,     INIT_HCA_RDB_BASE_OFFSET);
1271
1272         /* UD AV attributes */
1273
1274         /* multicast attributes */
1275
1276         MTHCA_PUT(inbox, param->mc_base,         INIT_HCA_MC_BASE_OFFSET);
1277         MTHCA_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1278         MTHCA_PUT(inbox, param->mc_hash_sz,      INIT_HCA_MC_HASH_SZ_OFFSET);
1279         MTHCA_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1280
1281         /* TPT attributes */
1282
1283         MTHCA_PUT(inbox, param->mpt_base,   INIT_HCA_MPT_BASE_OFFSET);
1284         if (!mthca_is_memfree(dev))
1285                 MTHCA_PUT(inbox, param->mtt_seg_sz, INIT_HCA_MTT_SEG_SZ_OFFSET);
1286         MTHCA_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1287         MTHCA_PUT(inbox, param->mtt_base,   INIT_HCA_MTT_BASE_OFFSET);
1288
1289         /* UAR attributes */
1290         {
1291                 u8 uar_page_sz = PAGE_SHIFT - 12;
1292                 MTHCA_PUT(inbox, uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1293         }
1294
1295         MTHCA_PUT(inbox, param->uar_scratch_base, INIT_HCA_UAR_SCATCH_BASE_OFFSET);
1296
1297         if (mthca_is_memfree(dev)) {
1298                 MTHCA_PUT(inbox, param->log_uarc_sz, INIT_HCA_UARC_SZ_OFFSET);
1299                 MTHCA_PUT(inbox, param->log_uar_sz,  INIT_HCA_LOG_UAR_SZ_OFFSET);
1300                 MTHCA_PUT(inbox, param->uarc_base,   INIT_HCA_UAR_CTX_BASE_OFFSET);
1301         }
1302
1303         err = mthca_cmd(dev, mailbox->dma, 0, 0, CMD_INIT_HCA, HZ, status);
1304
1305         mthca_free_mailbox(dev, mailbox);
1306         return err;
1307 }
1308
1309 int mthca_INIT_IB(struct mthca_dev *dev,
1310                   struct mthca_init_ib_param *param,
1311                   int port, u8 *status)
1312 {
1313         struct mthca_mailbox *mailbox;
1314         u32 *inbox;
1315         int err;
1316         u32 flags;
1317
1318 #define INIT_IB_IN_SIZE                                         56
1319 #define INIT_IB_FLAGS_OFFSET                    0x00
1320 #define INIT_IB_FLAG_SIG                                        (1 << 18)
1321 #define INIT_IB_FLAG_NG                                         (1 << 17)
1322 #define INIT_IB_FLAG_G0                                         (1 << 16)
1323 #define INIT_IB_VL_SHIFT                                        4
1324 #define INIT_IB_PORT_WIDTH_SHIFT        8
1325 #define INIT_IB_MTU_SHIFT                               12
1326 #define INIT_IB_MAX_GID_OFFSET                  0x06
1327 #define INIT_IB_MAX_PKEY_OFFSET         0x0a
1328 #define INIT_IB_GUID0_OFFSET                    0x10
1329 #define INIT_IB_NODE_GUID_OFFSET        0x18
1330 #define INIT_IB_SI_GUID_OFFSET                  0x20
1331
1332         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1333         if (IS_ERR(mailbox))
1334                 return PTR_ERR(mailbox);
1335         inbox = mailbox->buf;
1336
1337         RtlZeroMemory(inbox, INIT_IB_IN_SIZE);
1338
1339         flags = 0;
1340         flags |= param->set_guid0     ? INIT_IB_FLAG_G0  : 0;
1341         flags |= param->set_node_guid ? INIT_IB_FLAG_NG  : 0;
1342         flags |= param->set_si_guid   ? INIT_IB_FLAG_SIG : 0;
1343         flags |= param->vl_cap << INIT_IB_VL_SHIFT;
1344         flags |= param->port_width << INIT_IB_PORT_WIDTH_SHIFT;
1345         flags |= param->mtu_cap << INIT_IB_MTU_SHIFT;
1346         MTHCA_PUT(inbox, flags, INIT_IB_FLAGS_OFFSET);
1347
1348         MTHCA_PUT(inbox, param->gid_cap,   INIT_IB_MAX_GID_OFFSET);
1349         MTHCA_PUT(inbox, param->pkey_cap,  INIT_IB_MAX_PKEY_OFFSET);
1350         MTHCA_PUT(inbox, param->guid0,     INIT_IB_GUID0_OFFSET);
1351         MTHCA_PUT(inbox, param->node_guid, INIT_IB_NODE_GUID_OFFSET);
1352         MTHCA_PUT(inbox, param->si_guid,   INIT_IB_SI_GUID_OFFSET);
1353
1354         err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_INIT_IB,
1355                         CMD_TIME_CLASS_A, status);
1356
1357         mthca_free_mailbox(dev, mailbox);
1358         return err;
1359 }
1360
1361 int mthca_CLOSE_IB(struct mthca_dev *dev, int port, u8 *status)
1362 {
1363         return mthca_cmd(dev, 0, port, 0, CMD_CLOSE_IB, HZ, status);
1364 }
1365
1366 int mthca_CLOSE_HCA(struct mthca_dev *dev, int panic, u8 *status)
1367 {
1368         return mthca_cmd(dev, 0, 0, (u8)panic, CMD_CLOSE_HCA, HZ, status);
1369 }
1370
1371 int mthca_SET_IB(struct mthca_dev *dev, struct mthca_set_ib_param *param,
1372                  int port, u8 *status)
1373 {
1374         struct mthca_mailbox *mailbox;
1375         u32 *inbox;
1376         int err;
1377         u32 flags = 0;
1378
1379 #define SET_IB_IN_SIZE         0x40
1380 #define SET_IB_FLAGS_OFFSET    0x00
1381 #define SET_IB_FLAG_SIG        (1 << 18)
1382 #define SET_IB_FLAG_RQK        (1 <<  0)
1383 #define SET_IB_CAP_MASK_OFFSET 0x04
1384 #define SET_IB_SI_GUID_OFFSET  0x08
1385
1386         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1387         if (IS_ERR(mailbox))
1388                 return PTR_ERR(mailbox);
1389         inbox = mailbox->buf;
1390
1391         RtlZeroMemory(inbox, SET_IB_IN_SIZE);
1392
1393         flags |= param->set_si_guid     ? SET_IB_FLAG_SIG : 0;
1394         flags |= param->reset_qkey_viol ? SET_IB_FLAG_RQK : 0;
1395         MTHCA_PUT(inbox, flags, SET_IB_FLAGS_OFFSET);
1396
1397         MTHCA_PUT(inbox, param->cap_mask, SET_IB_CAP_MASK_OFFSET);
1398         MTHCA_PUT(inbox, param->si_guid,  SET_IB_SI_GUID_OFFSET);
1399
1400         err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_SET_IB,
1401                         CMD_TIME_CLASS_B, status);
1402
1403         mthca_free_mailbox(dev, mailbox);
1404         return err;
1405 }
1406
1407 int mthca_MAP_ICM(struct mthca_dev *dev, struct mthca_icm *icm, u64 virt, u8 *status)
1408 {
1409         return mthca_map_cmd(dev, CMD_MAP_ICM, icm, virt, status);
1410 }
1411
1412 int mthca_MAP_ICM_page(struct mthca_dev *dev, u64 dma_addr, u64 virt, u8 *status)
1413 {
1414         struct mthca_mailbox *mailbox;
1415         __be64 *inbox;
1416         int err;
1417
1418         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1419         if (IS_ERR(mailbox))
1420                 return PTR_ERR(mailbox);
1421         inbox = mailbox->buf;
1422
1423         inbox[0] = cl_hton64(virt);
1424         inbox[1] = cl_hton64(dma_addr);
1425
1426         err = mthca_cmd(dev, mailbox->dma, 1, 0, CMD_MAP_ICM,
1427                         CMD_TIME_CLASS_B, status);
1428
1429         mthca_free_mailbox(dev, mailbox);
1430
1431         if (!err)
1432                 HCA_PRINT(TRACE_LEVEL_VERBOSE,HCA_DBG_LOW,("Mapped page at %I64x to %I64x for ICM.\n",
1433                           (unsigned long long) dma_addr, (unsigned long long) virt));
1434
1435         return err;
1436 }
1437
1438 int mthca_UNMAP_ICM(struct mthca_dev *dev, u64 virt, u32 page_count, u8 *status)
1439 {
1440         HCA_PRINT(TRACE_LEVEL_VERBOSE,HCA_DBG_LOW,("Unmapping %d pages at %I64x from ICM.\n",
1441                   page_count, (unsigned long long) virt));
1442
1443         return mthca_cmd(dev, virt, page_count, 0, CMD_UNMAP_ICM, CMD_TIME_CLASS_B, status);
1444 }
1445
1446 int mthca_MAP_ICM_AUX(struct mthca_dev *dev, struct mthca_icm *icm, u8 *status)
1447 {
1448         return mthca_map_cmd(dev, CMD_MAP_ICM_AUX, icm, (u64)-1, status);
1449 }
1450
1451 int mthca_UNMAP_ICM_AUX(struct mthca_dev *dev, u8 *status)
1452 {
1453         return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_ICM_AUX, CMD_TIME_CLASS_B, status);
1454 }
1455
1456 int mthca_SET_ICM_SIZE(struct mthca_dev *dev, u64 icm_size, u64 *aux_pages,
1457                        u8 *status)
1458 {
1459         int ret = mthca_cmd_imm(dev, icm_size, aux_pages, 0, 0, CMD_SET_ICM_SIZE,
1460                                 CMD_TIME_CLASS_A, status);
1461
1462         if (ret || status)
1463                 return ret;
1464
1465         /*
1466          * Arbel page size is always 4 KB; round up number of system
1467          * pages needed.
1468          */
1469         *aux_pages = (*aux_pages + (1 << (PAGE_SHIFT - 12)) - 1) >> (PAGE_SHIFT - 12);
1470         *aux_pages = ALIGN(*aux_pages, PAGE_SIZE >> 12) >> (PAGE_SHIFT - 12);
1471
1472         return 0;
1473 }
1474
1475 int mthca_SW2HW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1476                     int mpt_index, u8 *status)
1477 {
1478         return mthca_cmd(dev, mailbox->dma, mpt_index, 0, CMD_SW2HW_MPT,
1479                          CMD_TIME_CLASS_B, status);
1480 }
1481
1482 int mthca_HW2SW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1483                     int mpt_index, u8 *status)
1484 {
1485         return mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, mpt_index,
1486                              (u8)!mailbox, CMD_HW2SW_MPT,
1487                              CMD_TIME_CLASS_B, status);
1488 }
1489
1490 int mthca_WRITE_MTT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1491                     int num_mtt, u8 *status)
1492 {
1493         return mthca_cmd(dev, mailbox->dma, num_mtt, 0, CMD_WRITE_MTT,
1494                          CMD_TIME_CLASS_B, status);
1495 }
1496
1497 int mthca_SYNC_TPT(struct mthca_dev *dev, u8 *status)
1498 {
1499         return mthca_cmd(dev, 0, 0, 0, CMD_SYNC_TPT, CMD_TIME_CLASS_B, status);
1500 }
1501
1502 int mthca_MAP_EQ(struct mthca_dev *dev, u64 event_mask, int unmap,
1503                  int eq_num, u8 *status)
1504 {
1505         HCA_PRINT(TRACE_LEVEL_VERBOSE,HCA_DBG_LOW,("%s mask %016I64x for eqn %d\n",
1506                   unmap ? "Clearing" : "Setting",
1507                   (unsigned long long) event_mask, eq_num));
1508         return mthca_cmd(dev, event_mask, (unmap << 31) | eq_num,
1509                          0, CMD_MAP_EQ, CMD_TIME_CLASS_B, status);
1510 }
1511
1512 int mthca_SW2HW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1513                    int eq_num, u8 *status)
1514 {
1515         return mthca_cmd(dev, mailbox->dma, eq_num, 0, CMD_SW2HW_EQ,
1516                          CMD_TIME_CLASS_A, status);
1517 }
1518
1519 int mthca_HW2SW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1520                    int eq_num, u8 *status)
1521 {
1522         return mthca_cmd_box(dev, 0, mailbox->dma, eq_num, 0,
1523                              CMD_HW2SW_EQ,
1524                              CMD_TIME_CLASS_A, status);
1525 }
1526
1527 int mthca_SW2HW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1528                    int cq_num, u8 *status)
1529 {
1530         return mthca_cmd(dev, mailbox->dma, cq_num, 0, CMD_SW2HW_CQ,
1531                         CMD_TIME_CLASS_A, status);
1532 }
1533
1534 int mthca_HW2SW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1535                    int cq_num, u8 *status)
1536 {
1537         return mthca_cmd_box(dev, 0, mailbox->dma, cq_num, 0,
1538                              CMD_HW2SW_CQ,
1539                              CMD_TIME_CLASS_A, status);
1540 }
1541
1542 int mthca_SW2HW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1543                     int srq_num, u8 *status)
1544 {
1545         return mthca_cmd(dev, mailbox->dma, srq_num, 0, CMD_SW2HW_SRQ,
1546                         CMD_TIME_CLASS_A, status);
1547 }
1548
1549 int mthca_HW2SW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1550                     int srq_num, u8 *status)
1551 {
1552         return mthca_cmd_box(dev, 0, mailbox->dma, srq_num, 0,
1553                              CMD_HW2SW_SRQ,
1554                              CMD_TIME_CLASS_A, status);
1555 }
1556
1557 int mthca_ARM_SRQ(struct mthca_dev *dev, int srq_num, int limit, u8 *status)
1558 {
1559         return mthca_cmd(dev, limit, srq_num, 0, CMD_ARM_SRQ,
1560                          CMD_TIME_CLASS_B, status);
1561 }
1562
1563 int mthca_MODIFY_QP(struct mthca_dev *dev, int trans, u32 num,
1564                     int is_ee, struct mthca_mailbox *mailbox, u32 optmask,
1565                     u8 *status)
1566 {
1567         enum {
1568                 MTHCA_TRANS_INVALID = 0,
1569                 MTHCA_TRANS_RST2INIT,
1570                 MTHCA_TRANS_INIT2INIT,
1571                 MTHCA_TRANS_INIT2RTR,
1572                 MTHCA_TRANS_RTR2RTS,
1573                 MTHCA_TRANS_RTS2RTS,
1574                 MTHCA_TRANS_SQERR2RTS,
1575                 MTHCA_TRANS_ANY2ERR,
1576                 MTHCA_TRANS_RTS2SQD,
1577                 MTHCA_TRANS_SQD2SQD,
1578                 MTHCA_TRANS_SQD2RTS,
1579                 MTHCA_TRANS_ANY2RST,
1580         };
1581         static const u16 op[] = {
1582                 0,                                                                                      /* MTHCA_TRANS_INVALID */
1583                 CMD_RST2INIT_QPEE,              /* MTHCA_TRANS_RST2INIT */
1584                 CMD_INIT2INIT_QPEE,             /* MTHCA_TRANS_INIT2INIT */
1585                 CMD_INIT2RTR_QPEE,              /* MTHCA_TRANS_INIT2RTR */
1586                 CMD_RTR2RTS_QPEE,               /* MTHCA_TRANS_RTR2RTS */
1587                 CMD_RTS2RTS_QPEE,               /* MTHCA_TRANS_RTS2RTS */
1588                 CMD_SQERR2RTS_QPEE,     /* MTHCA_TRANS_SQERR2RTS */
1589                 CMD_2ERR_QPEE,                          /* MTHCA_TRANS_ANY2ERR */
1590                 CMD_RTS2SQD_QPEE,               /* MTHCA_TRANS_RTS2SQD */
1591                 CMD_SQD2SQD_QPEE,               /* MTHCA_TRANS_SQD2SQD */
1592                 CMD_SQD2RTS_QPEE,               /* MTHCA_TRANS_SQD2RTS */
1593                 CMD_ERR2RST_QPEE                        /* MTHCA_TRANS_ANY2RST */
1594         };
1595         u8 op_mod = 0;
1596         int my_mailbox = 0;
1597         int err;
1598
1599         UNREFERENCED_PARAMETER(optmask);
1600
1601         if (trans < 0 || trans >= ARRAY_SIZE(op))
1602                 return -EINVAL;
1603
1604         if (trans == MTHCA_TRANS_ANY2RST) {
1605                 op_mod = 3;     /* don't write outbox, any->reset */
1606
1607                 /* For debugging */
1608                 if (!mailbox) {
1609                         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1610                         if (!IS_ERR(mailbox)) {
1611                                 my_mailbox = 1;
1612                                 op_mod     = 2; /* write outbox, any->reset */
1613                         } else
1614                                 mailbox = NULL;
1615                 }
1616         } else {
1617                 { // debug print
1618                         int i;
1619                         HCA_PRINT(TRACE_LEVEL_VERBOSE ,HCA_DBG_QP ,("Dumping QP context:\n"));
1620                         HCA_PRINT(TRACE_LEVEL_VERBOSE ,HCA_DBG_QP ,("  opt param mask: %08x\n", cl_ntoh32(*(__be32 *)mailbox->buf)));
1621                         for (i = 2; i < 0x100 / 4; i=i+4) {
1622                                 HCA_PRINT(TRACE_LEVEL_VERBOSE ,HCA_DBG_QP ,("  [%02x] %08x %08x %08x %08x\n",i-2,
1623                                                         cl_ntoh32(((__be32 *) mailbox->buf)[i ]),
1624                                                         cl_ntoh32(((__be32 *) mailbox->buf)[i + 1]),
1625                                                         cl_ntoh32(((__be32 *) mailbox->buf)[i + 2]),
1626                                                         cl_ntoh32(((__be32 *) mailbox->buf)[i + 3])));
1627                         }
1628                 }
1629         }
1630
1631         if (trans == MTHCA_TRANS_ANY2RST) {
1632                 err = mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0,
1633                                     (!!is_ee << 24) | num, op_mod,
1634                                     op[trans], CMD_TIME_CLASS_C, status);
1635
1636                 if (mailbox) { // debug print
1637                         int i;
1638                         HCA_PRINT(TRACE_LEVEL_VERBOSE ,HCA_DBG_QP ,("Dumping QP context:\n"));
1639                         for (i = 2; i < 0x100 / 4; i=i+4) {
1640                                 HCA_PRINT(TRACE_LEVEL_VERBOSE ,HCA_DBG_QP ,("  [%02x] %08x %08x %08x %08x\n",i-2,
1641                                                         cl_ntoh32(((__be32 *) mailbox->buf)[i ]),
1642                                                         cl_ntoh32(((__be32 *) mailbox->buf)[i + 1]),
1643                                                         cl_ntoh32(((__be32 *) mailbox->buf)[i + 2]),
1644                                                         cl_ntoh32(((__be32 *) mailbox->buf)[i + 3])));
1645                         }
1646                 }
1647         } else
1648                 err = mthca_cmd(dev, mailbox->dma, optmask | (!!is_ee << 24) | num,
1649                                 op_mod, op[trans], CMD_TIME_CLASS_C, status);
1650
1651         if (my_mailbox)
1652                 mthca_free_mailbox(dev, mailbox);
1653
1654         return err;
1655 }
1656
1657 int mthca_QUERY_QP(struct mthca_dev *dev, u32 num, int is_ee,
1658                    struct mthca_mailbox *mailbox, u8 *status)
1659 {
1660         return mthca_cmd_box(dev, 0, mailbox->dma, (!!is_ee << 24) | num, 0,
1661                              CMD_QUERY_QPEE, CMD_TIME_CLASS_A, status);
1662 }
1663
1664 int mthca_CONF_SPECIAL_QP(struct mthca_dev *dev, int type, u32 qpn,
1665                           u8 *status)
1666 {
1667         u8 op_mod;
1668
1669         switch (type) {
1670         case IB_QPT_QP0:
1671                 op_mod = 0;
1672                 break;
1673         case IB_QPT_QP1:
1674                 op_mod = 1;
1675                 break;
1676         case IB_QPT_RAW_IPV6:
1677                 op_mod = 2;
1678                 break;
1679         case IB_QPT_RAW_ETHER:
1680                 op_mod = 3;
1681                 break;
1682         default:
1683                 return -EINVAL;
1684         }
1685
1686         return mthca_cmd(dev, 0, qpn, op_mod, CMD_CONF_SPECIAL_QP,
1687                          CMD_TIME_CLASS_B, status);
1688 }
1689
1690 int mthca_MAD_IFC(struct mthca_dev *dev, int ignore_mkey, int ignore_bkey,
1691                   int port, struct _ib_wc *in_wc, struct ib_grh *in_grh,
1692                   void *in_mad, void *response_mad, u8 *status)
1693 {
1694         struct mthca_mailbox *inmailbox, *outmailbox;
1695         u8 *inbox;
1696         int err;
1697         u32 in_modifier = port;
1698         u8 op_modifier = 0;
1699
1700         ASSERT( !in_wc );
1701         UNREFERENCED_PARAMETER( in_grh );
1702
1703 #define MAD_IFC_BOX_SIZE      0x400
1704 #define MAD_IFC_MY_QPN_OFFSET 0x100
1705 #define MAD_IFC_RQPN_OFFSET   0x104
1706 #define MAD_IFC_SL_OFFSET     0x108
1707 #define MAD_IFC_G_PATH_OFFSET 0x109
1708 #define MAD_IFC_RLID_OFFSET   0x10a
1709 #define MAD_IFC_PKEY_OFFSET   0x10e
1710 #define MAD_IFC_GRH_OFFSET    0x140
1711
1712         inmailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1713         if (IS_ERR(inmailbox))
1714                 return PTR_ERR(inmailbox);
1715         inbox = inmailbox->buf;
1716
1717         outmailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1718         if (IS_ERR(outmailbox)) {
1719                 mthca_free_mailbox(dev, inmailbox);
1720                 return PTR_ERR(outmailbox);
1721         }
1722
1723         memcpy(inbox, in_mad, 256);
1724
1725         /*
1726          * Key check traps can't be generated unless we have in_wc to
1727          * tell us where to send the trap.
1728          */
1729         if (ignore_mkey || !in_wc)
1730                 op_modifier |= 0x1;
1731         if (ignore_bkey || !in_wc)
1732                 op_modifier |= 0x2;
1733
1734         err = mthca_cmd_box(dev, inmailbox->dma, outmailbox->dma,
1735                             in_modifier, op_modifier,
1736                             CMD_MAD_IFC, CMD_TIME_CLASS_C, status);
1737
1738         if (!err && !*status)
1739                 memcpy(response_mad, outmailbox->buf, 256);
1740
1741         mthca_free_mailbox(dev, inmailbox);
1742         mthca_free_mailbox(dev, outmailbox);
1743         return err;
1744 }
1745
1746 int mthca_READ_MGM(struct mthca_dev *dev, int index,
1747                    struct mthca_mailbox *mailbox, u8 *status)
1748 {
1749         return mthca_cmd_box(dev, 0, mailbox->dma, index, 0,
1750                              CMD_READ_MGM, CMD_TIME_CLASS_A, status);
1751 }
1752
1753 int mthca_WRITE_MGM(struct mthca_dev *dev, int index,
1754                     struct mthca_mailbox *mailbox, u8 *status)
1755 {
1756         return mthca_cmd(dev, mailbox->dma, index, 0, CMD_WRITE_MGM,
1757                          CMD_TIME_CLASS_A, status);
1758 }
1759
1760 int mthca_MGID_HASH(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1761                     u16 *hash, u8 *status)
1762 {
1763         u64 imm;
1764         int err;
1765
1766         err = mthca_cmd_imm(dev, mailbox->dma, &imm, 0, 0, CMD_MGID_HASH,
1767                             CMD_TIME_CLASS_A, status);
1768
1769         *hash = (u16)imm;
1770         return err;
1771 }
1772
1773 int mthca_NOP(struct mthca_dev *dev, u8 *status)
1774 {
1775         return mthca_cmd(dev, 0, 0x1f, 0, CMD_NOP, 100000, status);     /* 100 msecs */
1776 }