hw/mlx4/kernel/bus/net/cmd.c

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
   4  * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc.  All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #include "mlx4.h"
  36 #include "cmd.h"
  37
  38 #define CMD_POLL_TOKEN 0xffff
  39
  40 enum {
  41         /* command completed successfully: */
  42         CMD_STAT_OK             = 0x00,
  43         /* Internal error (such as a bus error) occurred while processing command: */
  44         CMD_STAT_INTERNAL_ERR   = 0x01,
  45         /* Operation/command not supported or opcode modifier not supported: */
  46         CMD_STAT_BAD_OP         = 0x02,
  47         /* Parameter not supported or parameter out of range: */
  48         CMD_STAT_BAD_PARAM      = 0x03,
  49         /* System not enabled or bad system state: */
  50         CMD_STAT_BAD_SYS_STATE  = 0x04,
  51         /* Attempt to access reserved or unallocaterd resource: */
  52         CMD_STAT_BAD_RESOURCE   = 0x05,
  53         /* Requested resource is currently executing a command, or is otherwise busy: */
  54         CMD_STAT_RESOURCE_BUSY  = 0x06,
  55         /* Required capability exceeds device limits: */
  56         CMD_STAT_EXCEED_LIM     = 0x08,
  57         /* Resource is not in the appropriate state or ownership: */
  58         CMD_STAT_BAD_RES_STATE  = 0x09,
  59         /* Index out of range: */
  60         CMD_STAT_BAD_INDEX      = 0x0a,
  61         /* FW image corrupted: */
  62         CMD_STAT_BAD_NVMEM      = 0x0b,
  63         /* Attempt to modify a QP/EE which is not in the presumed state: */
  64         CMD_STAT_BAD_QP_STATE   = 0x10,
  65         /* Bad segment parameters (Address/Size): */
  66         CMD_STAT_BAD_SEG_PARAM  = 0x20,
  67         /* Memory Region has Memory Windows bound to: */
  68         CMD_STAT_REG_BOUND      = 0x21,
  69         /* HCA local attached memory not present: */
  70         CMD_STAT_LAM_NOT_PRE    = 0x22,
  71         /* Bad management packet (silently discarded): */
  72         CMD_STAT_BAD_PKT        = 0x30,
  73         /* More outstanding CQEs in CQ than new CQ size: */
  74         CMD_STAT_BAD_SIZE       = 0x40,
  75         /* must be the last and have max value */
  76         CMD_STAT_SIZE           = CMD_STAT_BAD_SIZE + 1
  77 };
  78
  79 enum {
  80         HCR_IN_PARAM_OFFSET     = 0x00,
  81         HCR_IN_MODIFIER_OFFSET  = 0x08,
  82         HCR_OUT_PARAM_OFFSET    = 0x0c,
  83         HCR_TOKEN_OFFSET        = 0x14,
  84         HCR_STATUS_OFFSET       = 0x18,
  85
  86         HCR_OPMOD_SHIFT         = 12,
  87         HCR_T_BIT               = 21,
  88         HCR_E_BIT               = 22,
  89         HCR_GO_BIT              = 23
  90 };
  91
  92 enum {
  93         GO_BIT_TIMEOUT_MSECS    = 10000
  94 };
  95
  96 struct mlx4_cmd_context {
  97         struct completion       done;
  98         int                     result;
  99         int                     next;
 100         u64                     out_param;
 101         u16                     token;
 102 };
 103
 104 static int mlx4_status_to_errno(u8 status) {
 105         static int trans_table[CMD_STAT_SIZE];
 106         static int filled = 0;
 107
 108         if ( !filled ) {
 109                 memset( (char*)trans_table, 0, sizeof(trans_table) );
 110                 trans_table[CMD_STAT_INTERNAL_ERR]        = -EIO;
 111                 trans_table[CMD_STAT_BAD_OP]      = -EPERM;
 112                 trans_table[CMD_STAT_BAD_PARAM]   = -EINVAL;
 113                 trans_table[CMD_STAT_BAD_SYS_STATE]  = -ENXIO;
 114                 trans_table[CMD_STAT_BAD_RESOURCE]        = -EBADF;
 115                 trans_table[CMD_STAT_RESOURCE_BUSY]  = -EBUSY;
 116                 trans_table[CMD_STAT_EXCEED_LIM]          = -ENOMEM;
 117                 trans_table[CMD_STAT_BAD_RES_STATE]  = -EBADF;
 118                 trans_table[CMD_STAT_BAD_INDEX]   = -EBADF;
 119                 trans_table[CMD_STAT_BAD_NVMEM]   = -EFAULT;
 120                 trans_table[CMD_STAT_BAD_QP_STATE]   = -EINVAL;
 121                 trans_table[CMD_STAT_BAD_SEG_PARAM]  = -EFAULT;
 122                 trans_table[CMD_STAT_REG_BOUND]   = -EBUSY;
 123                 trans_table[CMD_STAT_LAM_NOT_PRE]         = -EAGAIN;
 124                 trans_table[CMD_STAT_BAD_PKT]     = -EINVAL;
 125                 trans_table[CMD_STAT_BAD_SIZE]    = -ENOMEM;
 126                 filled = 1;
 127         }
 128
 129         if (status >= ARRAY_SIZE(trans_table) ||
 130                 (status != CMD_STAT_OK && trans_table[status] == 0))
 131                 return -EIO;
 132
 133         return trans_table[status];
 134 }
 135
 136 static int cmd_pending(struct mlx4_dev *dev)
 137 {
 138         u32 status = readl(mlx4_priv(dev)->cmd.hcr + HCR_STATUS_OFFSET);
 139
 140         return (status & swab32(1 << HCR_GO_BIT)) ||
 141                 (mlx4_priv(dev)->cmd.toggle ==
 142                  !!(status & swab32(1 << HCR_T_BIT)));
 143 }
 144
 145 static int mlx4_cmd_post(struct mlx4_dev *dev, u64 in_param, u64 out_param,
 146                          u32 in_modifier, u8 op_modifier, u16 op, u16 token,
 147                          int event)
 148 {
 149         struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
 150         u32 __iomem *hcr = (u32 __iomem *)cmd->hcr;
 151         int ret = -EAGAIN;
 152         u64 end;
 153
 154         mutex_lock(&cmd->hcr_mutex);
 155
 156         end = jiffies;
 157         if (event)
 158                 end += msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS);
 159
 160         while (cmd_pending(dev)) {
 161                 if (time_after_eq(jiffies, end))
 162                         goto out;
 163                 cond_resched();
 164         }
 165
 166         /*
 167          * We use writel (instead of something like memcpy_toio)
 168          * because writes of less than 32 bits to the HCR don't work
 169          * (and some architectures such as ia64 implement memcpy_toio
 170          * in terms of writeb).
 171          */
 172         __raw_writel((__force u32) cpu_to_be32(in_param >> 32),           hcr + 0);
 173         __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful),  hcr + 1);
 174         __raw_writel((__force u32) cpu_to_be32(in_modifier),              hcr + 2);
 175         __raw_writel((__force u32) cpu_to_be32(out_param >> 32),          hcr + 3);
 176         __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), hcr + 4);
 177         __raw_writel((__force u32) cpu_to_be32(token << 16),              hcr + 5);
 178
 179         /* __raw_writel may not order writes. */
 180         wmb();
 181
 182         __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT)                |
 183                                                (cmd->toggle << HCR_T_BIT)       |
 184                                                (event ? (1 << HCR_E_BIT) : 0)   |
 185                                                (op_modifier << HCR_OPMOD_SHIFT) |
 186                                                op),                       hcr + 6);
 187
 188         /*
 189          * Make sure that our HCR writes don't get mixed in with
 190          * writes from another CPU starting a FW command.
 191          */
 192         mmiowb();
 193
 194         cmd->toggle = cmd->toggle ^ 1;
 195
 196         ret = 0;
 197
 198 out:
 199         mutex_unlock(&cmd->hcr_mutex);
 200         return ret;
 201 }
 202
 203 static int mlx4_cmd_poll(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
 204                          int out_is_imm, u32 in_modifier, u8 op_modifier,
 205                          u16 op, unsigned long timeout)
 206 {
 207         struct mlx4_priv *priv = mlx4_priv(dev);
 208         u8 __iomem *hcr = priv->cmd.hcr;
 209         int err = 0;
 210         u64 end;
 211
 212         down(&priv->cmd.poll_sem);
 213
 214         err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
 215                             in_modifier, op_modifier, op, CMD_POLL_TOKEN, 0);
 216         if (err)
 217                 goto out;
 218
 219         end = msecs_to_jiffies(timeout) + jiffies;
 220         while (cmd_pending(dev) && time_before(jiffies, end))
 221                 cond_resched();
 222
 223         if (cmd_pending(dev)) {
 224                 err = -ETIMEDOUT;
 225                 goto out;
 226         }
 227
 228         if (out_is_imm)
 229                 *out_param =
 230                         (u64) be32_to_cpu((__force __be32)
 231                                           __raw_readl(hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
 232                         (u64) be32_to_cpu((__force __be32)
 233                                           __raw_readl(hcr + HCR_OUT_PARAM_OFFSET + 4));
 234
 235         err = mlx4_status_to_errno((u8)(be32_to_cpu((__force __be32)
 236                                                __raw_readl(hcr + HCR_STATUS_OFFSET)) >> 24));
 237
 238 out:
 239         up(&priv->cmd.poll_sem);
 240         return err;
 241 }
 242
 243 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param)
 244 {
 245         struct mlx4_priv *priv = mlx4_priv(dev);
 246         struct mlx4_cmd_context *context =
 247                 &priv->cmd.context[token & priv->cmd.token_mask];
 248
 249         /* previously timed out command completing at long last */
 250         if (token != context->token)
 251                 return;
 252
 253         context->result    = mlx4_status_to_errno(status);
 254         context->out_param = out_param;
 255
 256         complete(&context->done);
 257 }
 258
 259 static int mlx4_cmd_wait(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
 260                          int out_is_imm, u32 in_modifier, u8 op_modifier,
 261                          u16 op, unsigned long timeout)
 262 {
 263         struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
 264         struct mlx4_cmd_context *context;
 265         int err = 0;
 266
 267         down(&cmd->event_sem);
 268
 269         spin_lock(&cmd->context_lock);
 270         BUG_ON(cmd->free_head < 0);
 271         context = &cmd->context[cmd->free_head];
 272         context->token += cmd->token_mask + 1;
 273         cmd->free_head = context->next;
 274         spin_unlock(&cmd->context_lock);
 275
 276         init_completion(&context->done);
 277
 278         mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
 279                       in_modifier, op_modifier, op, context->token, 1);
 280
 281         if (wait_for_completion_timeout(&context->done, msecs_to_jiffies(timeout))) {
 282                 if (!context->done.done) {
 283                         static int spam_limit = 10;
 284                         err = -EBUSY;
 285                         if (spam_limit-- > 0)
 286                                 mlx4_err(dev, "mlx4_cmd_wait: Command %02x completed with timeout after %d secs \n",
 287                                   op, timeout/1000);
 288                         goto out;
 289                 }
 290         }
 291
 292         err = context->result;
 293         if (err)
 294                 goto out;
 295
 296         if (out_is_imm)
 297                 *out_param = context->out_param;
 298
 299 out:
 300         spin_lock(&cmd->context_lock);
 301         context->next = cmd->free_head;
 302         cmd->free_head = (int)(context - cmd->context);
 303         spin_unlock(&cmd->context_lock);
 304
 305         up(&cmd->event_sem);
 306         return err;
 307 }
 308
 309 static char *__print_opcode(int opcode)
 310 {
 311         char *str = NULL;
 312         switch (opcode) {
 313                 case MLX4_CMD_SYS_EN    : str = "MLX4_CMD_SYS_EN        "; break;
 314                 case MLX4_CMD_SYS_DIS: str = "MLX4_CMD_SYS_DIS"; break;
 315                 case MLX4_CMD_MAP_FA    : str = "MLX4_CMD_MAP_FA        "; break;
 316                 case MLX4_CMD_UNMAP_FA: str = "MLX4_CMD_UNMAP_FA"; break;
 317                 case MLX4_CMD_RUN_FW    : str = "MLX4_CMD_RUN_FW        "; break;
 318                 case MLX4_CMD_MOD_STAT_CFG: str = "MLX4_CMD_MOD_STAT_CFG"; break;
 319                 case MLX4_CMD_QUERY_DEV_CAP: str = "MLX4_CMD_QUERY_DEV_CAP"; break;
 320                 case MLX4_CMD_QUERY_FW: str = "MLX4_CMD_QUERY_FW"; break;
 321                 case MLX4_CMD_ENABLE_LAM: str = "MLX4_CMD_ENABLE_LAM"; break;
 322                 case MLX4_CMD_DISABLE_LAM: str = "MLX4_CMD_DISABLE_LAM"; break;
 323                 case MLX4_CMD_QUERY_DDR: str = "MLX4_CMD_QUERY_DDR"; break;
 324                 case MLX4_CMD_QUERY_ADAPTER: str = "MLX4_CMD_QUERY_ADAPTER"; break;
 325                 case MLX4_CMD_INIT_HCA: str = "MLX4_CMD_INIT_HCA"; break;
 326                 case MLX4_CMD_CLOSE_HCA: str = "MLX4_CMD_CLOSE_HCA"; break;
 327                 case MLX4_CMD_INIT_PORT: str = "MLX4_CMD_INIT_PORT"; break;
 328                 case MLX4_CMD_CLOSE_PORT: str = "MLX4_CMD_CLOSE_PORT"; break;
 329                 case MLX4_CMD_QUERY_HCA: str = "MLX4_CMD_QUERY_HCA"; break;
 330                 case MLX4_CMD_QUERY_PORT: str = "MLX4_CMD_QUERY_PORT"; break;
 331                 case MLX4_CMD_SET_PORT: str = "MLX4_CMD_SET_PORT"; break;
 332                 case MLX4_CMD_ACCESS_DDR: str = "MLX4_CMD_ACCESS_DDR"; break;
 333                 case MLX4_CMD_MAP_ICM: str = "MLX4_CMD_MAP_ICM"; break;
 334                 case MLX4_CMD_UNMAP_ICM: str = "MLX4_CMD_UNMAP_ICM"; break;
 335                 case MLX4_CMD_MAP_ICM_AUX: str = "MLX4_CMD_MAP_ICM_AUX"; break;
 336                 case MLX4_CMD_UNMAP_ICM_AUX: str = "MLX4_CMD_UNMAP_ICM_AUX"; break;
 337                 case MLX4_CMD_SET_ICM_SIZE: str = "MLX4_CMD_SET_ICM_SIZE"; break;
 338                 case MLX4_CMD_SW2HW_MPT: str = "MLX4_CMD_SW2HW_MPT"; break;
 339                 case MLX4_CMD_QUERY_MPT: str = "MLX4_CMD_QUERY_MPT"; break;
 340                 case MLX4_CMD_HW2SW_MPT: str = "MLX4_CMD_HW2SW_MPT"; break;
 341                 case MLX4_CMD_READ_MTT: str = "MLX4_CMD_READ_MTT"; break;
 342                 case MLX4_CMD_WRITE_MTT: str = "MLX4_CMD_WRITE_MTT"; break;
 343                 case MLX4_CMD_SYNC_TPT: str = "MLX4_CMD_SYNC_TPT"; break;
 344                 case MLX4_CMD_MAP_EQ    : str = "MLX4_CMD_MAP_EQ        "; break;
 345                 case MLX4_CMD_SW2HW_EQ: str = "MLX4_CMD_SW2HW_EQ"; break;
 346                 case MLX4_CMD_HW2SW_EQ: str = "MLX4_CMD_HW2SW_EQ"; break;
 347                 case MLX4_CMD_QUERY_EQ: str = "MLX4_CMD_QUERY_EQ"; break;
 348                 case MLX4_CMD_SW2HW_CQ: str = "MLX4_CMD_SW2HW_CQ"; break;
 349                 case MLX4_CMD_HW2SW_CQ: str = "MLX4_CMD_HW2SW_CQ"; break;
 350                 case MLX4_CMD_QUERY_CQ: str = "MLX4_CMD_QUERY_CQ"; break;
 351                 case MLX4_CMD_MODIFY_CQ: str = "MLX4_CMD_MODIFY_CQ"; break;
 352                 case MLX4_CMD_SW2HW_SRQ: str = "MLX4_CMD_SW2HW_SRQ"; break;
 353                 case MLX4_CMD_HW2SW_SRQ: str = "MLX4_CMD_HW2SW_SRQ"; break;
 354                 case MLX4_CMD_QUERY_SRQ: str = "MLX4_CMD_QUERY_SRQ"; break;
 355                 case MLX4_CMD_ARM_SRQ: str = "MLX4_CMD_ARM_SRQ"; break;
 356                 case MLX4_CMD_RST2INIT_QP: str = "MLX4_CMD_RST2INIT_QP"; break;
 357                 case MLX4_CMD_INIT2RTR_QP: str = "MLX4_CMD_INIT2RTR_QP"; break;
 358                 case MLX4_CMD_RTR2RTS_QP: str = "MLX4_CMD_RTR2RTS_QP"; break;
 359                 case MLX4_CMD_RTS2RTS_QP: str = "MLX4_CMD_RTS2RTS_QP"; break;
 360                 case MLX4_CMD_SQERR2RTS_QP: str = "MLX4_CMD_SQERR2RTS_QP"; break;
 361                 case MLX4_CMD_2ERR_QP: str = "MLX4_CMD_2ERR_QP"; break;
 362                 case MLX4_CMD_RTS2SQD_QP: str = "MLX4_CMD_RTS2SQD_QP"; break;
 363                 case MLX4_CMD_SQD2SQD_QP: str = "MLX4_CMD_SQD2SQD_QP"; break;
 364                 case MLX4_CMD_SQD2RTS_QP: str = "MLX4_CMD_SQD2RTS_QP"; break;
 365                 case MLX4_CMD_2RST_QP: str = "MLX4_CMD_2RST_QP"; break;
 366                 case MLX4_CMD_QUERY_QP: str = "MLX4_CMD_QUERY_QP"; break;
 367                 case MLX4_CMD_INIT2INIT_QP: str = "MLX4_CMD_INIT2INIT_QP"; break;
 368                 case MLX4_CMD_SUSPEND_QP: str = "MLX4_CMD_SUSPEND_QP"; break;
 369                 case MLX4_CMD_UNSUSPEND_QP: str = "MLX4_CMD_UNSUSPEND_QP"; break;
 370                 case MLX4_CMD_CONF_SPECIAL_QP: str = "MLX4_CMD_CONF_SPECIAL_QP"; break;
 371                 case MLX4_CMD_MAD_IFC: str = "MLX4_CMD_MAD_IFC"; break;
 372                 case MLX4_CMD_READ_MCG: str = "MLX4_CMD_READ_MCG"; break;
 373                 case MLX4_CMD_WRITE_MCG: str = "MLX4_CMD_WRITE_MCG"; break;
 374                 case MLX4_CMD_MGID_HASH: str = "MLX4_CMD_MGID_HASH"; break;
 375                 case MLX4_CMD_DIAG_RPRT: str = "MLX4_CMD_DIAG_RPRT"; break;
 376                 case MLX4_CMD_NOP       : str = "MLX4_CMD_NOP   "; break;
 377                 case MLX4_CMD_QUERY_DEBUG_MSG: str = "MLX4_CMD_QUERY_DEBUG_MSG"; break;
 378                 case MLX4_CMD_SET_DEBUG_MSG: str = "MLX4_CMD_SET_DEBUG_MSG"; break;
 379         }
 380         return str;
 381 }
 382
 383 int __mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
 384                int out_is_imm, u32 in_modifier, u8 op_modifier,
 385                u16 op, unsigned long timeout)
 386 {
 387 #if 0
 388         mlx4_err(dev, "op %s, ev %d, in_param %#I64x, in_param %#I64x, out_is_imm %d, in_modifier %#x, op_modifier %d\n",
 389                 __print_opcode(op), mlx4_priv(dev)->cmd.use_events, in_param, out_param,
 390                 out_is_imm, in_modifier, (int)op_modifier);
 391 #endif
 392
 393         if ( mlx4_is_barred(dev) )
 394                 return -EFAULT;
 395
 396         if (mlx4_priv(dev)->cmd.use_events)
 397                 return mlx4_cmd_wait(dev, in_param, out_param, out_is_imm,
 398                                      in_modifier, op_modifier, op, timeout);
 399         else
 400                 return mlx4_cmd_poll(dev, in_param, out_param, out_is_imm,
 401                                      in_modifier, op_modifier, op, timeout);
 402 }
 403 EXPORT_SYMBOL_GPL(__mlx4_cmd);
 404
 405 int mlx4_cmd_init(struct mlx4_dev *dev)
 406 {
 407         struct mlx4_priv *priv = mlx4_priv(dev);
 408
 409         mutex_init(&priv->cmd.hcr_mutex);
 410         sema_init(&priv->cmd.poll_sem, 1);
 411         priv->cmd.use_events = 0;
 412         priv->cmd.toggle     = 1;
 413
 414         priv->cmd.hcr = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_HCR_BASE,
 415                 MLX4_HCR_SIZE);
 416         if (!priv->cmd.hcr) {
 417                 mlx4_err(dev, "Couldn't map command register.");
 418                 return -ENOMEM;
 419         }
 420
 421         priv->cmd.pool = pci_pool_create("mlx4_cmd", dev->pdev,
 422                                          MLX4_MAILBOX_SIZE,
 423                                          MLX4_MAILBOX_SIZE, 0);
 424         if (!priv->cmd.pool) {
 425                 iounmap(priv->cmd.hcr, MLX4_HCR_SIZE);
 426                 return -ENOMEM;
 427         }
 428
 429         return 0;
 430 }
 431
 432 void mlx4_cmd_cleanup(struct mlx4_dev *dev)
 433 {
 434         struct mlx4_priv *priv = mlx4_priv(dev);
 435
 436         pci_pool_destroy(priv->cmd.pool);
 437         iounmap(priv->cmd.hcr, MLX4_HCR_SIZE);
 438 }
 439
 440 /*
 441  * Switch to using events to issue FW commands (can only be called
 442  * after event queue for command events has been initialized).
 443  */
 444 int mlx4_cmd_use_events(struct mlx4_dev *dev)
 445 {
 446         struct mlx4_priv *priv = mlx4_priv(dev);
 447         int i;
 448
 449         priv->cmd.context = kmalloc(priv->cmd.max_cmds *
 450                                    sizeof (struct mlx4_cmd_context),
 451                                    GFP_KERNEL);
 452         if (!priv->cmd.context)
 453                 return -ENOMEM;
 454
 455         for (i = 0; i < priv->cmd.max_cmds; ++i) {
 456                 priv->cmd.context[i].token = (u16)i;
 457                 priv->cmd.context[i].next  = i + 1;
 458         }
 459
 460         priv->cmd.context[priv->cmd.max_cmds - 1].next = -1;
 461         priv->cmd.free_head = 0;
 462
 463         sema_init(&priv->cmd.event_sem, priv->cmd.max_cmds);
 464         spin_lock_init(&priv->cmd.context_lock);
 465
 466         for (priv->cmd.token_mask = 1;
 467              priv->cmd.token_mask < priv->cmd.max_cmds;
 468              priv->cmd.token_mask <<= 1)
 469                 ; /* nothing */
 470         --priv->cmd.token_mask;
 471
 472         priv->cmd.use_events = 1;
 473
 474         down(&priv->cmd.poll_sem);
 475
 476         return 0;
 477 }
 478
 479 /*
 480  * Switch back to polling (used when shutting down the device)
 481  */
 482 void mlx4_cmd_use_polling(struct mlx4_dev *dev)
 483 {
 484         struct mlx4_priv *priv = mlx4_priv(dev);
 485         int i;
 486
 487         priv->cmd.use_events = 0;
 488
 489         for (i = 0; i < priv->cmd.max_cmds; ++i)
 490                 down(&priv->cmd.event_sem);
 491
 492         kfree(priv->cmd.context);
 493
 494         up(&priv->cmd.poll_sem);
 495 }
 496
 497 struct mlx4_cmd_mailbox *mlx4_alloc_cmd_mailbox(struct mlx4_dev *dev)
 498 {
 499         struct mlx4_cmd_mailbox *mailbox;
 500
 501         if ( mlx4_is_barred(dev) )
 502                 return ERR_PTR(-EFAULT);
 503
 504         mailbox = kmalloc(sizeof *mailbox, GFP_KERNEL);
 505         if (!mailbox)
 506                 return ERR_PTR(-ENOMEM);
 507
 508         mailbox->buf = pci_pool_alloc(mlx4_priv(dev)->cmd.pool, GFP_KERNEL,
 509                                       &mailbox->dma);
 510         if (!mailbox->buf) {
 511                 kfree(mailbox);
 512                 return ERR_PTR(-ENOMEM);
 513         }
 514
 515         return mailbox;
 516 }
 517 EXPORT_SYMBOL_GPL(mlx4_alloc_cmd_mailbox);
 518
 519 void mlx4_free_cmd_mailbox(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox)
 520 {
 521         if (!mailbox)
 522                 return;
 523
 524         pci_pool_free(mlx4_priv(dev)->cmd.pool, mailbox->buf, mailbox->dma);
 525         kfree(mailbox);
 526 }
 527 EXPORT_SYMBOL_GPL(mlx4_free_cmd_mailbox);
 528
 529 // This is the interface version of this function
 530 int imlx4_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param, int out_is_imm,
 531                 u32 in_modifier, u8 op_modifier, u16 op, unsigned long timeout)
 532 {
 533         return __mlx4_cmd(dev, in_param, out_param, out_is_imm, in_modifier,
 534                           op_modifier, op, timeout);
 535 }
 536