7cb324428a183a60341ae40491afff7c7ace415c
[mirror/winof/.git] / hw / mlx4 / kernel / bus / ib / qp.c
1 /*
2  * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32
33 #include "mlx4_ib.h"
34 #include "ib_cache.h"
35 #include "ib_pack.h"
36 #include "qp.h"
37 #include "user.h"
38
39 enum {
40         MLX4_IB_ACK_REQ_FREQ    = 8,
41 };
42
43 enum {
44         MLX4_IB_DEFAULT_SCHED_QUEUE     = 0x83,
45         MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f
46 };
47
48 enum {
49         /*
50          * Largest possible UD header: send with GRH and immediate data.
51          */
52         MLX4_IB_UD_HEADER_SIZE          = 72
53 };
54
55 struct mlx4_ib_sqp {
56         struct mlx4_ib_qp       qp;
57         int                     pkey_index;
58         u32                     qkey;
59         u32                     send_psn;
60         struct ib_ud_header     ud_header;
61         u8                      header_buf[MLX4_IB_UD_HEADER_SIZE];
62 };
63
64 enum {
65         MLX4_IB_MIN_SQ_STRIDE = 6
66 };
67
68 static const __be32 mlx4_ib_opcode[] = {
69         __constant_cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),         /*      [IB_WR_RDMA_WRITE]                      */
70         __constant_cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),     /*      [IB_WR_RDMA_WRITE_WITH_IMM] */
71         __constant_cpu_to_be32(MLX4_OPCODE_SEND),                       /*      [IB_WR_SEND]                            */
72         __constant_cpu_to_be32(MLX4_OPCODE_SEND_IMM),           /*      [IB_WR_SEND_WITH_IMM]           */
73         __constant_cpu_to_be32(MLX4_OPCODE_RDMA_READ),          /*      [IB_WR_RDMA_READ]                       */
74         __constant_cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),          /*      [IB_WR_ATOMIC_CMP_AND_SWP]      */
75         __constant_cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),          /*      [IB_WR_ATOMIC_FETCH_AND_ADD]*/
76 };
77
78 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
79 {
80         return container_of(mqp, struct mlx4_ib_sqp, qp);
81 }
82
83 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
84 {
85         return qp->mqp.qpn >= dev->dev->caps.sqp_start &&
86                 qp->mqp.qpn <= dev->dev->caps.sqp_start + 3;
87 }
88
89 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
90 {
91         return qp->mqp.qpn >= dev->dev->caps.sqp_start &&
92                 qp->mqp.qpn <= dev->dev->caps.sqp_start + 1;
93 }
94
95 static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
96 {
97         if (qp->buf.nbufs == 1)
98                 return qp->buf.u.direct.buf + offset;
99         else
100                 return qp->buf.u.page_list[offset >> PAGE_SHIFT].buf +
101                         (offset & (PAGE_SIZE - 1));
102 }
103
104 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
105 {
106         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
107 }
108
109 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
110 {
111         return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
112 }
113
114 /*
115  * Stamp a SQ WQE so that it is invalid if prefetched by marking the
116  * first four bytes of every 64 byte chunk with 0xffffffff, except for
117  * the very first chunk of the WQE.
118  */
119 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n)
120 {
121         u32 *wqe = get_send_wqe(qp, n);
122         int i;
123
124         for (i = 16; i < 1 << (qp->sq.wqe_shift - 2); i += 16)
125                 wqe[i] = 0xffffffff;
126 }
127
128 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
129 {
130         struct ib_event event;
131         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
132
133         if (type == MLX4_EVENT_TYPE_PATH_MIG)
134                 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
135
136         if (ibqp->event_handler) {
137                 event.device     = ibqp->device;
138                 event.element.qp = ibqp;
139                 switch (type) {
140                 case MLX4_EVENT_TYPE_PATH_MIG:
141                         event.event = IB_EVENT_PATH_MIG;
142                         break;
143                 case MLX4_EVENT_TYPE_COMM_EST:
144                         event.event = IB_EVENT_COMM_EST;
145                         break;
146                 case MLX4_EVENT_TYPE_SQ_DRAINED:
147                         event.event = IB_EVENT_SQ_DRAINED;
148                         break;
149                 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
150                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
151                         break;
152                 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
153                         event.event = IB_EVENT_QP_FATAL;
154                         break;
155                 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
156                         event.event = IB_EVENT_PATH_MIG_ERR;
157                         break;
158                 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
159                         event.event = IB_EVENT_QP_REQ_ERR;
160                         break;
161                 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
162                         event.event = IB_EVENT_QP_ACCESS_ERR;
163                         break;
164                 default:
165                         printk(KERN_WARNING "mlx4_ib: Unexpected event type %d "
166                                "on QP %06x\n", type, qp->qpn);
167                         return;
168                 }
169
170                 ibqp->event_handler(&event, ibqp->qp_context);
171         }
172 }
173
174 static int send_wqe_overhead(enum ib_qp_type type)
175 {
176         /*
177          * UD WQEs must have a datagram segment.
178          * RC and UC WQEs might have a remote address segment.
179          * MLX WQEs need two extra inline data segments (for the UD
180          * header and space for the ICRC).
181          */
182         switch (type) {
183         case IB_QPT_UD:
184                 return sizeof (struct mlx4_wqe_ctrl_seg) +
185                         sizeof (struct mlx4_wqe_datagram_seg);
186         case IB_QPT_UC:
187                 return sizeof (struct mlx4_wqe_ctrl_seg) +
188                         sizeof (struct mlx4_wqe_raddr_seg);
189         case IB_QPT_RC:
190                 return sizeof (struct mlx4_wqe_ctrl_seg) +
191                         sizeof (struct mlx4_wqe_atomic_seg) +
192                         sizeof (struct mlx4_wqe_raddr_seg);
193         case IB_QPT_SMI:
194         case IB_QPT_GSI:
195                 return sizeof (struct mlx4_wqe_ctrl_seg) +
196                         ALIGN(MLX4_IB_UD_HEADER_SIZE +
197                               DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
198                                            MLX4_INLINE_ALIGN) *
199                               sizeof (struct mlx4_wqe_inline_seg),
200                               sizeof (struct mlx4_wqe_data_seg)) +
201                         ALIGN(4 +
202                               sizeof (struct mlx4_wqe_inline_seg),
203                               sizeof (struct mlx4_wqe_data_seg));
204         default:
205                 return sizeof (struct mlx4_wqe_ctrl_seg);
206         }
207 }
208
209 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
210                        int is_user, int has_srq, struct mlx4_ib_qp *qp)
211 {
212         /* Sanity check RQ size before proceeding */
213         if ((int)cap->max_recv_wr  > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
214             (int)cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
215                 return -EINVAL;
216
217         if (has_srq) {
218                 /* QPs attached to an SRQ should have no RQ */
219                 if (cap->max_recv_wr)
220                         return -EINVAL;
221
222                 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
223         } else {
224                 /* HW requires >= 1 RQ entry with >= 1 gather entry */
225                 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
226                         return -EINVAL;
227
228                 qp->rq.wqe_cnt   = roundup_pow_of_two(max(1U, cap->max_recv_wr));
229                 qp->rq.max_gs    = roundup_pow_of_two(max(1U, cap->max_recv_sge));
230                 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
231         }
232
233         /* leave userspace return values as they were, so as not to break ABI */
234         if (is_user) {
235                 cap->max_recv_wr  = qp->rq.max_post = qp->rq.wqe_cnt;
236                 cap->max_recv_sge = qp->rq.max_gs;
237         } else {
238                 cap->max_recv_wr  = qp->rq.max_post =
239                         min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
240                 cap->max_recv_sge = min(qp->rq.max_gs,
241                                         min(dev->dev->caps.max_sq_sg,
242                                         dev->dev->caps.max_rq_sg));
243         }
244         /* We don't support inline sends for kernel QPs (yet) */
245
246         return 0;
247 }
248
249 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
250                               enum ib_qp_type type, struct mlx4_ib_qp *qp)
251 {
252         /* Sanity check SQ size before proceeding */
253         if ((int)cap->max_send_wr       > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE  ||
254             (int)cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
255             (int)cap->max_inline_data + send_wqe_overhead(type) +
256             (int)sizeof(struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
257                 return -EINVAL;
258
259         /*
260          * For MLX transport we need 2 extra S/G entries:
261          * one for the header and one for the checksum at the end
262          */
263         if ((type == IB_QPT_SMI || type == IB_QPT_GSI) &&
264             (int)cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
265                 return -EINVAL;
266
267         qp->sq.wqe_shift = ilog2(roundup_pow_of_two(max(cap->max_send_sge *
268                                                         sizeof (struct mlx4_wqe_data_seg),
269                                                         cap->max_inline_data +
270                                                         sizeof (struct mlx4_wqe_inline_seg)) +
271                                                     send_wqe_overhead(type)));
272         qp->sq.wqe_shift = max(MLX4_IB_SQ_MIN_WQE_SHIFT, qp->sq.wqe_shift);
273         qp->sq.max_gs    = ((1 << qp->sq.wqe_shift) - send_wqe_overhead(type)) /
274                 sizeof (struct mlx4_wqe_data_seg);
275
276         /*
277          * We need to leave 2 KB + 1 WQE of headroom in the SQ to
278          * allow HW to prefetch.
279          */
280         qp->sq_spare_wqes = MLX4_IB_SQ_HEADROOM(qp->sq.wqe_shift);
281         qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr + qp->sq_spare_wqes);
282
283         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
284                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
285         if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
286                 qp->rq.offset = 0;
287                 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
288         } else {
289                 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
290                 qp->sq.offset = 0;
291         }
292
293         cap->max_send_wr = qp->sq.max_post =
294                 min(qp->sq.wqe_cnt - qp->sq_spare_wqes,
295                         dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE);
296         cap->max_send_sge = min(qp->sq.max_gs,
297                                 min(dev->dev->caps.max_sq_sg,
298                                         dev->dev->caps.max_rq_sg));
299         /* We don't support inline sends for kernel QPs (yet) */
300         cap->max_inline_data = 0;
301
302         return 0;
303 }
304
305 static int set_user_sq_size(struct mlx4_ib_dev *dev,
306                             struct mlx4_ib_qp *qp,
307                             struct mlx4_ib_create_qp *ucmd)
308 {
309         /* Sanity check SQ size before proceeding */
310         if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes       ||
311             ucmd->log_sq_stride >
312                 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
313             ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
314                 return -EINVAL;
315
316         qp->sq.wqe_cnt   = 1 << ucmd->log_sq_bb_count;
317         qp->sq.wqe_shift = ucmd->log_sq_stride;
318
319         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
320                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
321
322         return 0;
323 }
324
325 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
326                             struct ib_qp_init_attr *init_attr,
327                             struct ib_udata *udata, u32 sqpn, struct mlx4_ib_qp *qp)
328 {
329         int err;
330
331         mutex_init(&qp->mutex);
332         spin_lock_init(&qp->sq.lock);
333         spin_lock_init(&qp->rq.lock);
334
335         qp->state        = XIB_QPS_RESET;
336         qp->atomic_rd_en = 0;
337         qp->resp_depth   = 0;
338
339         qp->rq.head         = 0;
340         qp->rq.tail         = 0;
341         qp->sq.head         = 0;
342         qp->sq.tail         = 0;
343
344         err = set_rq_size(dev, &init_attr->cap, !!pd->p_uctx, !!init_attr->srq, qp);
345         if (err)
346                 goto err;
347
348         if (pd->p_uctx) {
349                 struct mlx4_ib_create_qp ucmd;
350
351                 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
352                         err = -EFAULT;
353                         goto err;
354                 }
355
356                 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
357
358                 err = set_user_sq_size(dev, qp, &ucmd);
359                 if (err)
360                         goto err;
361
362                 qp->umem = ib_umem_get(pd->p_uctx, ucmd.buf_addr,
363                                        qp->buf_size, 0, FALSE);
364                 if (IS_ERR(qp->umem)) {
365                         err = PTR_ERR(qp->umem);
366                         goto err;
367                 }
368
369                 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
370                                     ilog2(qp->umem->page_size), &qp->mtt);
371                 if (err)
372                         goto err_buf;
373
374                 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
375                 if (err)
376                         goto err_mtt;
377
378                 if (!init_attr->srq) {
379                         err = mlx4_ib_db_map_user(to_mucontext(pd->p_uctx),
380                                                   ucmd.db_addr, &qp->db);
381                         if (err)
382                                 goto err_mtt;
383                 }
384         } else {
385                 qp->sq_no_prefetch = 0;
386
387                 err = set_kernel_sq_size(dev, &init_attr->cap, init_attr->qp_type, qp);
388                 if (err)
389                         goto err;
390
391                 if (!init_attr->srq) {
392                         err = mlx4_ib_db_alloc(dev, &qp->db, 0);
393                         if (err)
394                                 goto err;
395
396                         *qp->db.db = 0;
397                 }
398
399                 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf)) {
400                         err = -ENOMEM;
401                         goto err_db;
402                 }
403
404                 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
405                                     &qp->mtt);
406                 if (err)
407                         goto err_buf;
408
409                 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf);
410                 if (err)
411                         goto err_mtt;
412
413                 qp->sq.wrid  = kmalloc(qp->sq.wqe_cnt * sizeof (u64), GFP_KERNEL);
414                 qp->rq.wrid  = kmalloc(qp->rq.wqe_cnt * sizeof (u64), GFP_KERNEL);
415
416                 if (!qp->sq.wrid || !qp->rq.wrid) {
417                         err = -ENOMEM;
418                         goto err_wrid;
419                 }
420         }
421
422         if (!sqpn)
423                 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &sqpn);
424         if (err)
425                 goto err_wrid;
426
427         err = mlx4_qp_alloc(dev->dev, sqpn, &qp->mqp);
428         if (err)
429                 goto err_wrid;
430
431         /*
432          * Hardware wants QPN written in big-endian order (after
433          * shifting) for send doorbell.  Precompute this value to save
434          * a little bit when posting sends.
435          */
436         qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
437
438         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
439                 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
440         else
441                 qp->sq_signal_bits = 0;
442
443         qp->mqp.event = mlx4_ib_qp_event;
444
445         return 0;
446
447 err_wrid:
448         if (pd->p_uctx) {
449                 if (!init_attr->srq)
450                         mlx4_ib_db_unmap_user(to_mucontext(pd->p_uctx),
451                                               &qp->db);
452         } else {
453                 kfree(qp->sq.wrid);
454                 kfree(qp->rq.wrid);
455         }
456
457 err_mtt:
458         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
459
460 err_buf:
461         if (pd->p_uctx)
462                 ib_umem_release(qp->umem);
463         else
464                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
465
466 err_db:
467         if (!pd->p_uctx && !init_attr->srq)
468                 mlx4_ib_db_free(dev, &qp->db);
469
470 err:
471         return err;
472 }
473
474 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
475 {
476         switch (state) {
477         case XIB_QPS_RESET:     return MLX4_QP_STATE_RST;
478         case XIB_QPS_INIT:      return MLX4_QP_STATE_INIT;
479         case XIB_QPS_RTR:       return MLX4_QP_STATE_RTR;
480         case XIB_QPS_RTS:       return MLX4_QP_STATE_RTS;
481         case XIB_QPS_SQD:       return MLX4_QP_STATE_SQD;
482         case XIB_QPS_SQE:       return MLX4_QP_STATE_SQER;
483         case XIB_QPS_ERR:       return MLX4_QP_STATE_ERR;
484         default:                return -1;
485         }
486 }
487
488 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
489 {
490         if (send_cq == recv_cq)
491                 spin_lock_irq(&send_cq->lock);
492         else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
493                 spin_lock_irq(&send_cq->lock);
494                 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
495         } else {
496                 spin_lock_irq(&recv_cq->lock);
497                 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
498         }
499 }
500
501 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
502 {
503         if (send_cq == recv_cq)
504                 spin_unlock_irq(&send_cq->lock);
505         else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
506                 spin_unlock(&recv_cq->lock);
507                 spin_unlock_irq(&send_cq->lock);
508         } else {
509                 spin_unlock(&send_cq->lock);
510                 spin_unlock_irq(&recv_cq->lock);
511         }
512 }
513
514 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
515                               int is_user)
516 {
517         struct mlx4_ib_cq *send_cq, *recv_cq;
518
519         if (qp->state != XIB_QPS_RESET)
520                 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
521                                    MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
522                         printk(KERN_WARNING "mlx4_ib: modify QP %06x to RESET failed.\n",
523                                qp->mqp.qpn);
524
525         send_cq = to_mcq(qp->ibqp.send_cq);
526         recv_cq = to_mcq(qp->ibqp.recv_cq);
527
528         mlx4_ib_lock_cqs(send_cq, recv_cq);
529
530         if (!is_user) {
531                 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
532                                  qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
533                 if (send_cq != recv_cq)
534                         __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
535         }
536
537         mlx4_qp_remove(dev->dev, &qp->mqp);
538
539         mlx4_ib_unlock_cqs(send_cq, recv_cq);
540
541         mlx4_qp_free(dev->dev, &qp->mqp);
542         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
543
544         if (is_user) {
545                 if (!qp->ibqp.srq)
546                         mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.p_uctx),
547                                               &qp->db);
548                 ib_umem_release(qp->umem);
549         } else {
550                 kfree(qp->sq.wrid);
551                 kfree(qp->rq.wrid);
552                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
553                 if (!qp->ibqp.srq)
554                         mlx4_ib_db_free(dev, &qp->db);
555         }
556 }
557
558 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
559                                 struct ib_qp_init_attr *init_attr,
560                                 struct ib_udata *udata)
561 {
562         struct mlx4_ib_dev *dev = to_mdev(pd->device);
563         struct mlx4_ib_sqp *sqp;
564         struct mlx4_ib_qp *qp;
565         int err;
566
567         switch (init_attr->qp_type) {
568         case IB_QPT_RC:
569         case IB_QPT_UC:
570         case IB_QPT_UD:
571         {
572                 qp = kzalloc(sizeof *qp, GFP_KERNEL);
573                 if (!qp)
574                         return ERR_PTR(-ENOMEM);
575
576                 err = create_qp_common(dev, pd, init_attr, udata, 0, qp);
577                 if (err) {
578                         kfree(qp);
579                         return ERR_PTR(err);
580                 }
581
582                 qp->ibqp.qp_num = qp->mqp.qpn;
583
584                 break;
585         }
586         case IB_QPT_SMI:
587         case IB_QPT_GSI:
588         {
589                 /* Userspace is not allowed to create special QPs: */
590                 if (pd->p_uctx)
591                         return ERR_PTR(-EINVAL);
592
593                 sqp = kzalloc(sizeof *sqp, GFP_KERNEL);
594                 if (!sqp)
595                         return ERR_PTR(-ENOMEM);
596
597                 qp = &sqp->qp;
598
599                 err = create_qp_common(dev, pd, init_attr, udata,
600                                        dev->dev->caps.sqp_start +
601                                        (init_attr->qp_type == IB_QPT_SMI ? 0 : 2) +
602                                        init_attr->port_num - 1,
603                                        qp);
604                 if (err) {
605                         kfree(sqp);
606                         return ERR_PTR(err);
607                 }
608
609                 qp->port        = init_attr->port_num;
610                 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1;
611
612                 break;
613         }
614         default:
615                 /* Don't support raw QPs */
616                 return ERR_PTR(-EINVAL);
617         }
618
619         return &qp->ibqp;
620 }
621
622 int mlx4_ib_destroy_qp(struct ib_qp *qp)
623 {
624         struct mlx4_ib_dev *dev = to_mdev(qp->device);
625         struct mlx4_ib_qp *mqp = to_mqp(qp);
626
627         if (is_qp0(dev, mqp))
628                 mlx4_CLOSE_PORT(dev->dev, mqp->port);
629
630         destroy_qp_common(dev, mqp, !!qp->pd->p_uctx);
631
632         if (is_sqp(dev, mqp))
633                 kfree(to_msqp(mqp));
634         else
635                 kfree(mqp);
636
637         return 0;
638 }
639
640 static int to_mlx4_st(enum ib_qp_type type)
641 {
642         switch (type) {
643         case IB_QPT_RC:         return MLX4_QP_ST_RC;
644         case IB_QPT_UC:         return MLX4_QP_ST_UC;
645         case IB_QPT_UD:         return MLX4_QP_ST_UD;
646         case IB_QPT_SMI:
647         case IB_QPT_GSI:        return MLX4_QP_ST_MLX;
648         default:                return -1;
649         }
650 }
651
652 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
653                                    int attr_mask)
654 {
655         u8 dest_rd_atomic;
656         u32 access_flags;
657         u32 hw_access_flags = 0;
658
659         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
660                 dest_rd_atomic = attr->max_dest_rd_atomic;
661         else
662                 dest_rd_atomic = qp->resp_depth;
663
664         if (attr_mask & IB_QP_ACCESS_FLAGS)
665                 access_flags = attr->qp_access_flags;
666         else
667                 access_flags = qp->atomic_rd_en;
668
669         if (!dest_rd_atomic)
670                 access_flags &= IB_ACCESS_REMOTE_WRITE;
671
672         if (access_flags & IB_ACCESS_REMOTE_READ)
673                 hw_access_flags |= MLX4_QP_BIT_RRE;
674         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
675                 hw_access_flags |= MLX4_QP_BIT_RAE;
676         if (access_flags & IB_ACCESS_REMOTE_WRITE)
677                 hw_access_flags |= MLX4_QP_BIT_RWE;
678
679         return cpu_to_be32(hw_access_flags);
680 }
681
682 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
683                             int attr_mask)
684 {
685         if (attr_mask & IB_QP_PKEY_INDEX)
686                 sqp->pkey_index = attr->pkey_index;
687         if (attr_mask & IB_QP_QKEY)
688                 sqp->qkey = attr->qkey;
689         if (attr_mask & IB_QP_SQ_PSN)
690                 sqp->send_psn = attr->sq_psn;
691 }
692
693 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
694 {
695         path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
696 }
697
698 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
699                          struct mlx4_qp_path *path, u8 port)
700 {
701         path->grh_mylmc     = ah->src_path_bits & 0x7f;
702         path->rlid          = cpu_to_be16(ah->dlid);
703         if (ah->static_rate) {
704                 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
705                 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
706                        !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
707                         --path->static_rate;
708         } else
709                 path->static_rate = 0;
710         path->counter_index = 0xff;
711
712         if (ah->ah_flags & IB_AH_GRH) {
713                 if (ah->grh.sgid_index >= dev->dev->caps.gid_table_len[port]) {
714                         printk(KERN_ERR "sgid_index (%u) too large. max is %d\n",
715                                ah->grh.sgid_index, dev->dev->caps.gid_table_len[port] - 1);
716                         return -1;
717                 }
718
719                 path->grh_mylmc |= 1 << 7;
720                 path->mgid_index = ah->grh.sgid_index;
721                 path->hop_limit  = ah->grh.hop_limit;
722                 path->tclass_flowlabel =
723                         cpu_to_be32((ah->grh.traffic_class << 20) |
724                                     (ah->grh.flow_label));
725                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
726         }
727
728         path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
729                 ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
730
731         return 0;
732 }
733
734 static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
735                                const struct ib_qp_attr *attr, int attr_mask,
736                                enum ib_qp_state cur_state, enum ib_qp_state new_state)
737 {
738         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
739         struct mlx4_ib_qp *qp = to_mqp(ibqp);
740         struct mlx4_qp_context *context;
741         enum mlx4_qp_optpar optpar = 0;
742         int sqd_event;
743         int err = -EINVAL;
744
745         context = kzalloc(sizeof *context, GFP_KERNEL);
746         if (!context)
747                 return -ENOMEM;
748
749         context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
750                                      (to_mlx4_st(ibqp->qp_type) << 16));
751         context->flags     |= cpu_to_be32(1 << 8); /* DE? */
752
753         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
754                 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
755         else {
756                 optpar |= MLX4_QP_OPTPAR_PM_STATE;
757                 switch (attr->path_mig_state) {
758                 case IB_MIG_MIGRATED:
759                         context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
760                         break;
761                 case IB_MIG_REARM:
762                         context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
763                         break;
764                 case IB_MIG_ARMED:
765                         context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
766                         break;
767                 }
768         }
769
770         if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
771             ibqp->qp_type == IB_QPT_UD)
772                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
773         else if (attr_mask & IB_QP_PATH_MTU) {
774                 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
775                         printk(KERN_ERR "path MTU (%u) is invalid\n",
776                                attr->path_mtu);
777                         goto out;
778                 }
779                 context->mtu_msgmax = (u8)((attr->path_mtu << 5) |
780                         ilog2(dev->dev->caps.max_msg_sz));
781         }
782
783         if (qp->rq.wqe_cnt)
784                 context->rq_size_stride = (u8)(ilog2(qp->rq.wqe_cnt) << 3);
785         context->rq_size_stride |= qp->rq.wqe_shift - 4;
786
787         if (qp->sq.wqe_cnt)
788                 context->sq_size_stride = (u8)(ilog2(qp->sq.wqe_cnt) << 3);
789         context->sq_size_stride |= qp->sq.wqe_shift - 4;
790
791         if (cur_state == XIB_QPS_RESET && new_state == XIB_QPS_INIT)
792                 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
793
794         if (qp->ibqp.p_uctx)
795                 context->usr_page = cpu_to_be32(to_mucontext(ibqp->p_uctx)->uar.index);
796         else
797                 context->usr_page = cpu_to_be32(dev->priv_uar.index);
798
799         if (attr_mask & IB_QP_DEST_QPN)
800                 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
801
802         if (attr_mask & IB_QP_PORT) {
803                 if (cur_state == XIB_QPS_SQD && new_state == XIB_QPS_SQD &&
804                     !(attr_mask & IB_QP_AV)) {
805                         mlx4_set_sched(&context->pri_path, attr->port_num);
806                         optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
807                 }
808         }
809
810         if (attr_mask & IB_QP_PKEY_INDEX) {
811                 context->pri_path.pkey_index = (u8)attr->pkey_index;
812                 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
813         }
814
815         if (attr_mask & IB_QP_AV) {
816                 if (mlx4_set_path(dev, &attr->ah_attr, &context->pri_path,
817                                   attr_mask & IB_QP_PORT ? attr->port_num : qp->port))
818                         goto out;
819
820                 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
821                            MLX4_QP_OPTPAR_SCHED_QUEUE);
822         }
823
824         if (attr_mask & IB_QP_TIMEOUT) {
825                 context->pri_path.ackto = attr->timeout << 3;
826                 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
827         }
828
829         if (attr_mask & IB_QP_ALT_PATH) {
830                 if (attr->alt_port_num == 0 ||
831                     attr->alt_port_num > dev->dev->caps.num_ports)
832                         goto out;
833
834                 if (attr->alt_pkey_index >=
835                     dev->dev->caps.pkey_table_len[attr->alt_port_num])
836                         goto out;
837
838                 if (mlx4_set_path(dev, &attr->alt_ah_attr, &context->alt_path,
839                                   attr->alt_port_num))
840                         goto out;
841
842                 context->alt_path.pkey_index = (u8)attr->alt_pkey_index;
843                 context->alt_path.ackto = attr->alt_timeout << 3;
844                 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
845         }
846
847         context->pd         = cpu_to_be32(to_mpd(ibqp->pd)->pdn);
848         context->params1    = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
849
850         if (attr_mask & IB_QP_RNR_RETRY) {
851                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
852                 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
853         }
854
855         if (attr_mask & IB_QP_RETRY_CNT) {
856                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
857                 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
858         }
859
860         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
861                 if (attr->max_rd_atomic)
862                         context->params1 |=
863                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
864                 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
865         }
866
867         if (attr_mask & IB_QP_SQ_PSN)
868                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
869
870         context->cqn_send = cpu_to_be32(to_mcq(ibqp->send_cq)->mcq.cqn);
871
872         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
873                 if (attr->max_dest_rd_atomic)
874                         context->params2 |=
875                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
876                 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
877         }
878
879         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
880                 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
881                 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
882         }
883
884         if (ibqp->srq)
885                 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
886
887         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
888                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
889                 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
890         }
891         if (attr_mask & IB_QP_RQ_PSN)
892                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
893
894         context->cqn_recv = cpu_to_be32(to_mcq(ibqp->recv_cq)->mcq.cqn);
895
896         if (attr_mask & IB_QP_QKEY) {
897                 context->qkey = cpu_to_be32(attr->qkey);
898                 optpar |= MLX4_QP_OPTPAR_Q_KEY;
899         }
900
901         if (ibqp->srq)
902                 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
903
904         if (!ibqp->srq && cur_state == XIB_QPS_RESET && new_state == XIB_QPS_INIT)
905                 context->db_rec_addr = cpu_to_be64(qp->db.dma.da);
906
907         if (cur_state == XIB_QPS_INIT &&
908             new_state == XIB_QPS_RTR  &&
909             (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
910              ibqp->qp_type == IB_QPT_UD)) {
911                 context->pri_path.sched_queue = (qp->port - 1) << 6;
912                 if (is_qp0(dev, qp))
913                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
914                 else
915                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
916         }
917
918         if (cur_state == XIB_QPS_RTS && new_state == XIB_QPS_SQD        &&
919             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
920                 sqd_event = 1;
921         else
922                 sqd_event = 0;
923
924         /*
925          * Before passing a kernel QP to the HW, make sure that the
926          * ownership bits of the send queue are set and the SQ
927          * headroom is stamped so that the hardware doesn't start
928          * processing stale work requests.
929          */
930         if (!ibqp->p_uctx && cur_state == XIB_QPS_RESET && new_state == XIB_QPS_INIT) {
931                 struct mlx4_wqe_ctrl_seg *ctrl;
932                 int i;
933
934                 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
935                         ctrl = get_send_wqe(qp, i);
936                         ctrl->owner_opcode = cpu_to_be32(1 << 31);
937
938                         stamp_send_wqe(qp, i);
939                 }
940         }
941
942         err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
943                              to_mlx4_state(new_state), context, optpar,
944                              sqd_event, &qp->mqp);
945         if (err)
946                 goto out;
947
948         qp->state = new_state;
949
950         if (attr_mask & IB_QP_ACCESS_FLAGS)
951                 qp->atomic_rd_en = (u8)attr->qp_access_flags;
952         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
953                 qp->resp_depth = attr->max_dest_rd_atomic;
954         if (attr_mask & IB_QP_PORT)
955                 qp->port = attr->port_num;
956         if (attr_mask & IB_QP_ALT_PATH)
957                 qp->alt_port = attr->alt_port_num;
958
959         if (is_sqp(dev, qp))
960                 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
961
962         /*
963          * If we moved QP0 to RTR, bring the IB link up; if we moved
964          * QP0 to RESET or ERROR, bring the link back down.
965          */
966         if (is_qp0(dev, qp)) {
967                 if (cur_state != XIB_QPS_RTR && new_state == XIB_QPS_RTR)
968                         if (mlx4_INIT_PORT(dev->dev, qp->port))
969                                 printk(KERN_WARNING "INIT_PORT failed for port %d\n",
970                                        qp->port);
971
972                 if (cur_state != XIB_QPS_RESET && cur_state != XIB_QPS_ERR &&
973                     (new_state == XIB_QPS_RESET || new_state == XIB_QPS_ERR))
974                         mlx4_CLOSE_PORT(dev->dev, qp->port);
975         }
976
977         /*
978          * If we moved a kernel QP to RESET, clean up all old CQ
979          * entries and reinitialize the QP.
980          */
981         if (new_state == XIB_QPS_RESET && !ibqp->p_uctx) {
982                 mlx4_ib_cq_clean(to_mcq(ibqp->recv_cq), qp->mqp.qpn,
983                                  ibqp->srq ? to_msrq(ibqp->srq): NULL);
984                 if (ibqp->send_cq != ibqp->recv_cq)
985                         mlx4_ib_cq_clean(to_mcq(ibqp->send_cq), qp->mqp.qpn, NULL);
986
987                 qp->rq.head = 0;
988                 qp->rq.tail = 0;
989                 qp->sq.head = 0;
990                 qp->sq.tail = 0;
991                 if (!ibqp->srq)
992                         *qp->db.db  = 0;
993         }
994
995 out:
996         kfree(context);
997         return err;
998 }
999
1000 static struct ib_qp_attr mlx4_ib_qp_attr;
1001 static int mlx4_ib_qp_attr_mask_table[IB_QPT_UD + 1];
1002
1003 void mlx4_ib_qp_init()
1004 {
1005         memset( &mlx4_ib_qp_attr, 0, sizeof(mlx4_ib_qp_attr) );
1006         mlx4_ib_qp_attr.port_num = 1;
1007
1008         memset( &mlx4_ib_qp_attr_mask_table, 0, sizeof(mlx4_ib_qp_attr_mask_table) );
1009         mlx4_ib_qp_attr_mask_table[IB_QPT_UD]  = (IB_QP_PKEY_INDEX              |
1010                                 IB_QP_PORT                      |
1011                                 IB_QP_QKEY);
1012         mlx4_ib_qp_attr_mask_table[IB_QPT_UC]  = (IB_QP_PKEY_INDEX              |
1013                                 IB_QP_PORT                      |
1014                                 IB_QP_ACCESS_FLAGS);
1015         mlx4_ib_qp_attr_mask_table[IB_QPT_RC]  = (IB_QP_PKEY_INDEX              |
1016                                 IB_QP_PORT                      |
1017                                 IB_QP_ACCESS_FLAGS);
1018         mlx4_ib_qp_attr_mask_table[IB_QPT_SMI] = (IB_QP_PKEY_INDEX              |
1019                                 IB_QP_QKEY);
1020         mlx4_ib_qp_attr_mask_table[IB_QPT_GSI] = (IB_QP_PKEY_INDEX              |
1021                                 IB_QP_QKEY);
1022 }
1023
1024 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1025                       int attr_mask, struct ib_udata *udata)
1026 {
1027         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1028         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1029         enum ib_qp_state cur_state, new_state;
1030         int err = -EINVAL;
1031
1032         UNUSED_PARAM(udata);
1033         
1034         mutex_lock(&qp->mutex);
1035
1036         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
1037         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
1038
1039         if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask))
1040                 goto out;
1041
1042         if ((attr_mask & IB_QP_PORT) &&
1043             (attr->port_num == 0 || attr->port_num > dev->dev->caps.num_ports)) {
1044                 goto out;
1045         }
1046
1047         if (attr_mask & IB_QP_PKEY_INDEX) {
1048                 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1049                 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p])
1050                         goto out;
1051         }
1052
1053         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
1054             attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
1055                 goto out;
1056         }
1057
1058         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
1059             attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
1060                 goto out;
1061         }
1062
1063         if (cur_state == new_state && cur_state == XIB_QPS_RESET) {
1064                 err = 0;
1065                 goto out;
1066         }
1067
1068         if (cur_state == XIB_QPS_RESET && new_state == XIB_QPS_ERR) {
1069                 err = __mlx4_ib_modify_qp(ibqp, &mlx4_ib_qp_attr,
1070                                           mlx4_ib_qp_attr_mask_table[ibqp->qp_type],
1071                                           XIB_QPS_RESET, XIB_QPS_INIT);
1072                 if (err)
1073                         goto out;
1074                 cur_state = XIB_QPS_INIT;
1075         }
1076
1077         err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
1078
1079 out:
1080         mutex_unlock(&qp->mutex);
1081         return err;
1082 }
1083
1084 static enum ib_wr_opcode to_wr_opcode(struct _ib_send_wr *wr)
1085 {
1086
1087         enum ib_wr_opcode opcode = -1; //= wr->wr_type;
1088
1089         switch (wr->wr_type) {
1090                 case WR_SEND: 
1091                         opcode = (wr->send_opt & IB_SEND_OPT_IMMEDIATE) ? IB_WR_SEND_WITH_IMM : IB_WR_SEND;
1092                         break;
1093                 case WR_RDMA_WRITE:     
1094                         opcode = (wr->send_opt & IB_SEND_OPT_IMMEDIATE) ? IB_WR_RDMA_WRITE_WITH_IMM : IB_WR_RDMA_WRITE;
1095                         break;
1096                 case WR_RDMA_READ:              opcode = IB_WR_RDMA_READ; break;
1097                 case WR_COMPARE_SWAP:           opcode = IB_WR_ATOMIC_CMP_AND_SWP; break;
1098                 case WR_FETCH_ADD:                      opcode = IB_WR_ATOMIC_FETCH_AND_ADD; break;
1099         }
1100         return opcode;
1101 }
1102
1103 static int build_mlx_header(struct mlx4_ib_sqp *sqp, ib_send_wr_t *wr,
1104                             void *wqe)
1105 {
1106         enum ib_wr_opcode opcode = to_wr_opcode(wr);
1107         struct ib_device *ib_dev = &to_mdev(sqp->qp.ibqp.device)->ib_dev;
1108         struct mlx4_wqe_mlx_seg *mlx = wqe;
1109         struct mlx4_wqe_inline_seg *inl = (void*)((u8*)wqe + sizeof *mlx);
1110         struct mlx4_ib_ah *ah = to_mah((struct ib_ah *)wr->dgrm.ud.h_av);
1111         __be16 pkey;
1112         int send_size;
1113         int header_size;
1114         int spc;
1115         u32 i;
1116
1117         send_size = 0;
1118         for (i = 0; i < wr->num_ds; ++i)
1119                 send_size += wr->ds_array[i].length;
1120
1121         ib_ud_header_init(send_size, mlx4_ib_ah_grh_present(ah), &sqp->ud_header);
1122
1123         sqp->ud_header.lrh.service_level   =
1124                 (u8)(be32_to_cpu(ah->av.sl_tclass_flowlabel) >> 28);
1125         sqp->ud_header.lrh.destination_lid = ah->av.dlid;
1126         sqp->ud_header.lrh.source_lid      = cpu_to_be16(ah->av.g_slid & 0x7f);
1127         if (mlx4_ib_ah_grh_present(ah)) {
1128                 sqp->ud_header.grh.traffic_class =
1129                         (u8)((be32_to_cpu(ah->av.sl_tclass_flowlabel) >> 20) & 0xff);
1130                 sqp->ud_header.grh.flow_label    =
1131                         ah->av.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
1132                 sqp->ud_header.grh.hop_limit     = ah->av.hop_limit;
1133                 ib_get_cached_gid(ib_dev, (u8)(be32_to_cpu(ah->av.port_pd) >> 24),
1134                                   ah->av.gid_index, &sqp->ud_header.grh.source_gid);
1135                 memcpy(sqp->ud_header.grh.destination_gid.raw,
1136                        ah->av.dgid, 16);
1137         }
1138
1139         mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
1140         mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
1141                                   (sqp->ud_header.lrh.destination_lid ==
1142                                    XIB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
1143                                   (sqp->ud_header.lrh.service_level << 8));
1144         mlx->rlid   = sqp->ud_header.lrh.destination_lid;
1145
1146         switch (opcode) {
1147         case IB_WR_SEND:
1148                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
1149                 sqp->ud_header.immediate_present = 0;
1150                 break;
1151         case IB_WR_SEND_WITH_IMM:
1152                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1153                 sqp->ud_header.immediate_present = 1;
1154                 sqp->ud_header.immediate_data    = wr->immediate_data;
1155                 break;
1156         default:
1157                 return -EINVAL;
1158         }
1159
1160         sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
1161         if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1162                 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1163         sqp->ud_header.bth.solicited_event = (u8)(!!(wr->send_opt & IB_SEND_OPT_SOLICITED));
1164         if (!sqp->qp.ibqp.qp_num)
1165                 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
1166         else
1167                 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->dgrm.ud.pkey_index, &pkey);
1168         sqp->ud_header.bth.pkey = pkey;
1169         sqp->ud_header.bth.destination_qpn = wr->dgrm.ud.remote_qp;
1170         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1171         sqp->ud_header.deth.qkey = wr->dgrm.ud.remote_qkey & 0x00000080 ?
1172                 cpu_to_be32(sqp->qkey) : wr->dgrm.ud.remote_qkey;
1173         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1174
1175         header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
1176
1177 #if 0
1178         {
1179                 printk(KERN_ERR "built UD header of size %d:\n", header_size);
1180                 for (i = 0; i < header_size / 4; ++i) {
1181                         if (i % 8 == 0)
1182                                 printk("  [%02x] ", i * 4);
1183                         printk(" %08x",
1184                                be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
1185                         if ((i + 1) % 8 == 0)
1186                                 printk("\n");
1187                 }
1188                 printk("\n");
1189         }
1190 #endif
1191
1192         /*
1193          * Inline data segments may not cross a 64 byte boundary.  If
1194          * our UD header is bigger than the space available up to the
1195          * next 64 byte boundary in the WQE, use two inline data
1196          * segments to hold the UD header.
1197          */
1198         spc = MLX4_INLINE_ALIGN -
1199                 ((u32)(ULONG_PTR)(inl + 1) & (MLX4_INLINE_ALIGN - 1));
1200         if (header_size <= spc) {
1201                 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
1202                 memcpy(inl + 1, sqp->header_buf, header_size);
1203                 i = 1;
1204         } else {
1205                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
1206                 memcpy(inl + 1, sqp->header_buf, spc);
1207
1208                 inl = (void*)((u8*)(inl + 1) + spc);
1209                 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
1210                 /*
1211                  * Need a barrier here to make sure all the data is
1212                  * visible before the byte_count field is set.
1213                  * Otherwise the HCA prefetcher could grab the 64-byte
1214                  * chunk with this inline segment and get a valid (!=
1215                  * 0xffffffff) byte count but stale data, and end up
1216                  * generating a packet with bad headers.
1217                  *
1218                  * The first inline segment's byte_count field doesn't
1219                  * need a barrier, because it comes after a
1220                  * control/MLX segment and therefore is at an offset
1221                  * of 16 mod 64.
1222                  */
1223                 wmb();
1224                 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
1225                 i = 2;
1226         }
1227
1228         return ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
1229 }
1230
1231 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
1232 {
1233         unsigned cur;
1234         struct mlx4_ib_cq *cq;
1235
1236         cur = wq->head - wq->tail;
1237         if (likely((int)cur + nreq < wq->max_post))
1238                 return 0;
1239
1240         cq = to_mcq(ib_cq);
1241         spin_lock(&cq->lock);
1242         cur = wq->head - wq->tail;
1243         spin_unlock(&cq->lock);
1244
1245         return (int)cur + nreq >= wq->max_post;
1246 }
1247
1248 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
1249                                           u64 remote_addr, __be32 rkey)
1250 {
1251         rseg->raddr    = cpu_to_be64(remote_addr);
1252         rseg->rkey     = rkey;
1253         rseg->reserved = 0;
1254 }
1255
1256 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg, ib_send_wr_t *wr)
1257 {
1258         if (wr->wr_type == WR_COMPARE_SWAP) {
1259                 aseg->swap_add = wr->remote_ops.atomic2;
1260                 aseg->compare  = wr->remote_ops.atomic1;
1261         } else {
1262                 aseg->swap_add = wr->remote_ops.atomic1;
1263                 aseg->compare  = 0;
1264         }
1265
1266 }
1267
1268 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
1269                              ib_send_wr_t *wr)
1270 {
1271         memcpy(dseg->av, &to_mah((struct ib_ah *)wr->dgrm.ud.h_av)->av, sizeof (struct mlx4_av));
1272         dseg->dqpn = wr->dgrm.ud.remote_qp;
1273         dseg->qkey = wr->dgrm.ud.remote_qkey;
1274 }
1275
1276 static void set_mlx_icrc_seg(void *dseg)
1277 {
1278         u32 *t = dseg;
1279         struct mlx4_wqe_inline_seg *iseg = dseg;
1280
1281         t[1] = 0;
1282
1283         /*
1284          * Need a barrier here before writing the byte_count field to
1285          * make sure that all the data is visible before the
1286          * byte_count field is set.  Otherwise, if the segment begins
1287          * a new cacheline, the HCA prefetcher could grab the 64-byte
1288          * chunk and get a valid (!= * 0xffffffff) byte count but
1289          * stale data, and end up sending the wrong data.
1290          */
1291         wmb();
1292
1293         iseg->byte_count = cpu_to_be32((1 << 31) | 4);
1294 }
1295
1296 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, ib_local_ds_t *sg)
1297 {
1298         dseg->lkey       = cpu_to_be32(sg->lkey);
1299         dseg->addr       = cpu_to_be64(sg->vaddr);
1300
1301         /*
1302          * Need a barrier here before writing the byte_count field to
1303          * make sure that all the data is visible before the
1304          * byte_count field is set.  Otherwise, if the segment begins
1305          * a new cacheline, the HCA prefetcher could grab the 64-byte
1306          * chunk and get a valid (!= * 0xffffffff) byte count but
1307          * stale data, and end up sending the wrong data.
1308          */
1309         wmb();
1310
1311         dseg->byte_count = cpu_to_be32(sg->length);
1312 }
1313
1314 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, ib_local_ds_t *sg)
1315 {
1316         dseg->byte_count = cpu_to_be32(sg->length);
1317         dseg->lkey       = cpu_to_be32(sg->lkey);
1318         dseg->addr       = cpu_to_be64(sg->vaddr);
1319 }
1320
1321 int mlx4_ib_post_send(struct ib_qp *ibqp, ib_send_wr_t *wr,
1322                       ib_send_wr_t **bad_wr)
1323 {
1324         enum ib_wr_opcode opcode;
1325         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1326         u8 *wqe;
1327         struct mlx4_wqe_ctrl_seg *ctrl;
1328         struct mlx4_wqe_data_seg *dseg;
1329         unsigned long flags;
1330         int nreq;
1331         int err = 0;
1332         int ind;
1333         int size;
1334         int i;
1335
1336         spin_lock_irqsave(&qp->sq.lock, &flags);
1337
1338         ind = qp->sq.head;
1339
1340         for (nreq = 0; wr; ++nreq, wr = wr->p_next) {
1341                 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1342                         err = -ENOMEM;
1343                         if (bad_wr)
1344                                 *bad_wr = wr;
1345                         goto out;
1346                 }
1347
1348                 if (unlikely(wr->num_ds > (u32)qp->sq.max_gs)) {
1349                         err = -EINVAL;
1350                         if (bad_wr)
1351                                 *bad_wr = wr;
1352                         goto out;
1353                 }
1354
1355                 wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
1356                 ctrl = (void*)wqe;
1357                 qp->sq.wrid[ind & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
1358                 opcode = to_wr_opcode(wr);
1359
1360                 ctrl->srcrb_flags =
1361                         (wr->send_opt & IB_SEND_OPT_SIGNALED ?
1362                          cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
1363                         (wr->send_opt & IB_SEND_OPT_SOLICITED ?
1364                          cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
1365                         qp->sq_signal_bits;
1366
1367                 if (opcode == IB_WR_SEND_WITH_IMM ||
1368                     opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1369                         ctrl->imm = wr->immediate_data;
1370                 else
1371                         ctrl->imm = 0;
1372
1373                 wqe += sizeof *ctrl;
1374                 size = sizeof *ctrl / 16;
1375
1376                 switch (ibqp->qp_type) {
1377                 case IB_QPT_RC:
1378                 case IB_QPT_UC:
1379                         switch (opcode) {
1380                         case IB_WR_ATOMIC_CMP_AND_SWP:
1381                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1382                                 set_raddr_seg((void*)wqe, wr->remote_ops.vaddr,
1383                                               wr->remote_ops.rkey);
1384                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
1385
1386                                 set_atomic_seg((void*)wqe, wr);
1387                                 wqe  += sizeof (struct mlx4_wqe_atomic_seg);
1388
1389                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
1390                                          sizeof (struct mlx4_wqe_atomic_seg)) / 16;
1391
1392                                 break;
1393
1394                         case IB_WR_RDMA_READ:
1395                         case IB_WR_RDMA_WRITE:
1396                         case IB_WR_RDMA_WRITE_WITH_IMM:
1397                                 set_raddr_seg((void*)wqe, wr->remote_ops.vaddr,
1398                                               wr->remote_ops.rkey);
1399                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
1400                                 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
1401                                 break;
1402
1403                         default:
1404                                 /* No extra segments required for sends */
1405                                 break;
1406                         }
1407                         break;
1408
1409                 case IB_QPT_UD:
1410                         set_datagram_seg((void*)wqe, wr);
1411                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
1412                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
1413                         break;
1414
1415                 case IB_QPT_SMI:
1416                 case IB_QPT_GSI:
1417                         err = build_mlx_header(to_msqp(qp), wr, ctrl);
1418                         if (err < 0) {
1419                                 if (bad_wr)
1420                                         *bad_wr = wr;
1421                                 goto out;
1422                         }
1423                         wqe  += err;
1424                         size += err / 16;
1425
1426                         err = 0;
1427                         break;
1428
1429                 default:
1430                         break;
1431                 }
1432
1433                 /*
1434                  * Write data segments in reverse order, so as to
1435                  * overwrite cacheline stamp last within each
1436                  * cacheline.  This avoids issues with WQE
1437                  * prefetching.
1438                  */
1439
1440                 dseg = (void*)wqe;
1441                 dseg += wr->num_ds - 1;
1442                 size += wr->num_ds * (sizeof (struct mlx4_wqe_data_seg) / 16);
1443
1444                 /* Add one more inline data segment for ICRC for MLX sends */
1445                 if (unlikely(qp->ibqp.qp_type == IB_QPT_SMI ||
1446                              qp->ibqp.qp_type == IB_QPT_GSI)) {
1447                         set_mlx_icrc_seg(dseg + 1);
1448                         size += sizeof (struct mlx4_wqe_data_seg) / 16;
1449                 }
1450
1451                 for (i = wr->num_ds - 1; i >= 0; --i, --dseg)
1452                         set_data_seg(dseg, wr->ds_array + i);
1453
1454                 ctrl->fence_size = (u8)((wr->send_opt & IB_SEND_OPT_FENCE ?
1455                                     MLX4_WQE_CTRL_FENCE : 0) | size);
1456
1457                 /*
1458                  * Make sure descriptor is fully written before
1459                  * setting ownership bit (because HW can start
1460                  * executing as soon as we do).
1461                  */
1462                 wmb();
1463
1464                 if (opcode < 0 || opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
1465                         err = -EINVAL;
1466                         goto out;
1467                 }
1468
1469                 ctrl->owner_opcode = mlx4_ib_opcode[opcode] |
1470                         (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
1471
1472                 /*
1473                  * We can improve latency by not stamping the last
1474                  * send queue WQE until after ringing the doorbell, so
1475                  * only stamp here if there are still more WQEs to post.
1476                  */
1477                 if (wr->p_next)
1478                         stamp_send_wqe(qp, (ind + qp->sq_spare_wqes) &
1479                                        (qp->sq.wqe_cnt - 1));
1480
1481                 ++ind;
1482         }
1483
1484 out:
1485         if (likely(nreq)) {
1486                 qp->sq.head += nreq;
1487
1488                 /*
1489                  * Make sure that descriptors are written before
1490                  * doorbell record.
1491                  */
1492                 wmb();
1493
1494                 writel(qp->doorbell_qpn,
1495                        (u8*)to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
1496
1497 #if 0
1498                 if (qp->mqp.qpn == 0x41)
1499                         DbgPrint( "[MLX4_BUS] mlx4_ib_post_send : qtype %d, qpn %#x, nreq %d, sq.head %#x, wqe_ix %d, db %p \n", 
1500                                 ibqp->qp_type, qp->mqp.qpn, nreq, qp->sq.head, ind, 
1501                                 (u8*)to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL );
1502 #endif          
1503                 /*
1504                  * Make sure doorbells don't leak out of SQ spinlock
1505                  * and reach the HCA out of order.
1506                  */
1507                 mmiowb();
1508
1509                 stamp_send_wqe(qp, (ind + qp->sq_spare_wqes - 1) &
1510                                (qp->sq.wqe_cnt - 1));
1511         }
1512
1513         spin_unlock_irqrestore(&qp->sq.lock, flags);
1514
1515         return err;
1516 }
1517
1518 int mlx4_ib_post_recv(struct ib_qp *ibqp, ib_recv_wr_t *wr,
1519                       ib_recv_wr_t **bad_wr)
1520 {
1521         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1522         struct mlx4_wqe_data_seg *scat;
1523         unsigned long flags;
1524         int err = 0;
1525         int nreq;
1526         int ind;
1527         int i;
1528
1529         spin_lock_irqsave(&qp->rq.lock, &flags);
1530
1531         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
1532
1533         for (nreq = 0; wr; ++nreq, wr = wr->p_next) {
1534                 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.send_cq)) {
1535                         err = -ENOMEM;
1536                         if (bad_wr)
1537                                 *bad_wr = wr;
1538                         goto out;
1539                 }
1540
1541                 if (unlikely(wr->num_ds > (u32)qp->rq.max_gs)) {
1542                         err = -EINVAL;
1543                         if (bad_wr)
1544                                 *bad_wr = wr;
1545                         goto out;
1546                 }
1547
1548                 scat = get_recv_wqe(qp, ind);
1549
1550                 for (i = 0; i < (int)wr->num_ds; ++i)
1551                         __set_data_seg(scat + i, wr->ds_array + i);
1552
1553                 if (i < qp->rq.max_gs) {
1554                         scat[i].byte_count = 0;
1555                         scat[i].lkey       = cpu_to_be32(MLX4_INVALID_LKEY);
1556                         scat[i].addr       = 0;
1557                 }
1558
1559                 qp->rq.wrid[ind] = wr->wr_id;
1560
1561                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
1562         }
1563
1564 out:
1565         if (likely(nreq)) {
1566                 qp->rq.head += nreq;
1567
1568                 /*
1569                  * Make sure that descriptors are written before
1570                  * doorbell record.
1571                  */
1572                 wmb();
1573
1574                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
1575
1576 #if 0
1577                 if (qp->mqp.qpn == 0x41)
1578                         DbgPrint( "[MLX4_BUS] mlx4_ib_post_recv : qtype %d, qpn %#x, nreq %d, rq.head %#x, wqe_ix %d, db_obj %p, db %p \n", 
1579                                 ibqp->qp_type, qp->mqp.qpn, nreq, qp->rq.head, ind, &qp->db, qp->db.db );
1580 #endif          
1581         }
1582
1583         spin_unlock_irqrestore(&qp->rq.lock, flags);
1584
1585         return err;
1586 }
1587
1588 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
1589 {
1590         switch (mlx4_state) {
1591         case MLX4_QP_STATE_RST:      return XIB_QPS_RESET;
1592         case MLX4_QP_STATE_INIT:     return XIB_QPS_INIT;
1593         case MLX4_QP_STATE_RTR:      return XIB_QPS_RTR;
1594         case MLX4_QP_STATE_RTS:      return XIB_QPS_RTS;
1595         case MLX4_QP_STATE_SQ_DRAINING:
1596         case MLX4_QP_STATE_SQD:      return XIB_QPS_SQD;
1597         case MLX4_QP_STATE_SQER:     return XIB_QPS_SQE;
1598         case MLX4_QP_STATE_ERR:      return XIB_QPS_ERR;
1599         default:                     return -1;
1600         }
1601 }
1602
1603 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
1604 {
1605         switch (mlx4_mig_state) {
1606         case MLX4_QP_PM_ARMED:          return IB_MIG_ARMED;
1607         case MLX4_QP_PM_REARM:          return IB_MIG_REARM;
1608         case MLX4_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
1609         default: return -1;
1610         }
1611 }
1612
1613 static int to_ib_qp_access_flags(int mlx4_flags)
1614 {
1615         int ib_flags = 0;
1616
1617         if (mlx4_flags & MLX4_QP_BIT_RRE)
1618                 ib_flags |= IB_ACCESS_REMOTE_READ;
1619         if (mlx4_flags & MLX4_QP_BIT_RWE)
1620                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
1621         if (mlx4_flags & MLX4_QP_BIT_RAE)
1622                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
1623
1624         return ib_flags;
1625 }
1626
1627 static void to_ib_ah_attr(struct mlx4_dev *dev, struct ib_ah_attr *ib_ah_attr,
1628                                 struct mlx4_qp_path *path)
1629 {
1630         memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
1631         ib_ah_attr->port_num      = path->sched_queue & 0x40 ? 2 : 1;
1632
1633         if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
1634                 return;
1635
1636         ib_ah_attr->dlid          = be16_to_cpu(path->rlid);
1637         ib_ah_attr->sl            = (path->sched_queue >> 2) & 0xf;
1638         ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f;
1639         ib_ah_attr->static_rate   = path->static_rate ? path->static_rate - 5 : 0;
1640         ib_ah_attr->ah_flags      = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
1641         if (ib_ah_attr->ah_flags) {
1642                 ib_ah_attr->grh.sgid_index = path->mgid_index;
1643                 ib_ah_attr->grh.hop_limit  = path->hop_limit;
1644                 ib_ah_attr->grh.traffic_class =
1645                         (u8)((be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff);
1646                 ib_ah_attr->grh.flow_label =
1647                         be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
1648                 memcpy(ib_ah_attr->grh.dgid.raw,
1649                         path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
1650         }
1651 }
1652
1653 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
1654                      struct ib_qp_init_attr *qp_init_attr)
1655 {
1656         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1657         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1658         struct mlx4_qp_context context;
1659         int mlx4_state;
1660         int err;
1661
1662         UNUSED_PARAM(qp_attr_mask);
1663
1664         if (qp->state == XIB_QPS_RESET) {
1665                 qp_attr->qp_state = XIB_QPS_RESET;
1666                 goto done;
1667         }
1668
1669         err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
1670         if (err)
1671                 return -EINVAL;
1672
1673         mlx4_state = be32_to_cpu(context.flags) >> 28;
1674
1675         qp_attr->qp_state            = to_ib_qp_state(mlx4_state);
1676         qp_attr->path_mtu            = context.mtu_msgmax >> 5;
1677         qp_attr->path_mig_state      =
1678                 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
1679         qp_attr->qkey                = be32_to_cpu(context.qkey);
1680         qp_attr->rq_psn              = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
1681         qp_attr->sq_psn              = be32_to_cpu(context.next_send_psn) & 0xffffff;
1682         qp_attr->dest_qp_num         = be32_to_cpu(context.remote_qpn) & 0xffffff;
1683         qp_attr->qp_access_flags     =
1684                 to_ib_qp_access_flags(be32_to_cpu(context.params2));
1685
1686         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
1687                 to_ib_ah_attr(dev->dev, &qp_attr->ah_attr, &context.pri_path);
1688                 to_ib_ah_attr(dev->dev, &qp_attr->alt_ah_attr, &context.alt_path);
1689                 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
1690                 qp_attr->alt_port_num   = qp_attr->alt_ah_attr.port_num;
1691         }
1692
1693         qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
1694         if (qp_attr->qp_state == XIB_QPS_INIT)
1695                 qp_attr->port_num = qp->port;
1696         else
1697                 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
1698
1699         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
1700         qp_attr->sq_draining = (u8)(mlx4_state == MLX4_QP_STATE_SQ_DRAINING);
1701
1702         qp_attr->max_rd_atomic = (u8)(1 << ((be32_to_cpu(context.params1) >> 21) & 0x7));
1703
1704         qp_attr->max_dest_rd_atomic =
1705                 (u8)(1 << ((be32_to_cpu(context.params2) >> 21) & 0x7));
1706         qp_attr->min_rnr_timer      =
1707                 (u8)((be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f);
1708         qp_attr->timeout            = context.pri_path.ackto >> 3;
1709         qp_attr->retry_cnt          = (u8)((be32_to_cpu(context.params1) >> 16) & 0x7);
1710         qp_attr->rnr_retry          = (u8)((be32_to_cpu(context.params1) >> 13) & 0x7);
1711         qp_attr->alt_timeout        = context.alt_path.ackto >> 3;
1712
1713 done:
1714         qp_attr->cur_qp_state        = qp_attr->qp_state;
1715         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
1716         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
1717
1718         if (!ibqp->p_uctx) {
1719                 qp_attr->cap.max_send_wr  = qp->sq.wqe_cnt;
1720                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
1721         } else {
1722                 qp_attr->cap.max_send_wr  = 0;
1723                 qp_attr->cap.max_send_sge = 0;
1724         }
1725
1726         /*
1727          * We don't support inline sends for kernel QPs (yet), and we
1728          * don't know what userspace's value should be.
1729          */
1730         qp_attr->cap.max_inline_data = 0;
1731
1732         qp_init_attr->cap            = qp_attr->cap;
1733
1734         return 0;
1735 }
1736