6d7d8481a7ecf5f4ec90d3866fcbde4fdc09168e
[mirror/winof/.git] / hw / mlx4 / kernel / bus / net / main.c
1 /*
2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
3  * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4  * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
5  * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
6  *
7  * This software is available to you under a choice of one of two
8  * licenses.  You may choose to be licensed under the terms of the GNU
9  * General Public License (GPL) Version 2, available from the file
10  * COPYING in the main directory of this source tree, or the
11  * OpenIB.org BSD license below:
12  *
13  *     Redistribution and use in source and binary forms, with or
14  *     without modification, are permitted provided that the following
15  *     conditions are met:
16  *
17  *      - Redistributions of source code must retain the above
18  *        copyright notice, this list of conditions and the following
19  *        disclaimer.
20  *
21  *      - Redistributions in binary form must reproduce the above
22  *        copyright notice, this list of conditions and the following
23  *        disclaimer in the documentation and/or other materials
24  *        provided with the distribution.
25  *
26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33  * SOFTWARE.
34  */
35
36
37 #include "mlx4.h"
38 #include "fw.h"
39 #include "icm.h"
40 #include "device.h"
41 #include "doorbell.h"
42 #include "complib\cl_thread.h"
43 #include <mlx4_debug.h>
44
45 #if defined(EVENT_TRACING)
46 #ifdef offsetof
47 #undef offsetof
48 #endif
49 #include "main.tmh"
50 #endif
51
52
53 static struct mlx4_profile default_profile = {
54         1 << 17,        /* num_qp               */
55         1 << 4,         /* rdmarc_per_qp        */
56         1 << 16,        /* num_srq      */
57         1 << 16,        /* num_cq               */
58         1 << 13,        /* num_mcg      */
59         1 << 18,        /* num_mpt      */ 
60         1 << 20         /* num_mtt      */
61 };
62
63 static void process_mod_param_profile(void)
64 {
65         if (g.mod_num_qp)
66                 default_profile.num_qp = 1 << g.mod_num_qp;
67
68         if (g.mod_rdmarc_per_qp)
69                 default_profile.rdmarc_per_qp = 1 << g.mod_rdmarc_per_qp;
70
71         if (g.mod_num_srq)
72                 default_profile.num_srq = 1 << g.mod_num_srq;
73
74         if (g.mod_num_cq)
75                 default_profile.num_cq = 1 << g.mod_num_cq;
76
77         if (g.mod_num_mcg)
78                 default_profile.num_mcg = 1 << g.mod_num_mcg;
79
80         if (g.mod_num_mpt)
81                 default_profile.num_mpt = 1 << g.mod_num_mpt;
82
83         if (g.mod_num_mtt)
84                 default_profile.num_mtt = 1 << g.mod_num_mtt;
85 }
86
87 static struct pci_device_id 
88 mlx4_pci_table[] = {
89         HCA(MELLANOX, SDR,              HERMON),
90         HCA(MELLANOX, DDR,              HERMON),
91         HCA(MELLANOX, ETH,              HERMON),
92         HCA(MELLANOX, ETH_YATIR,                HERMON),
93         HCA(MELLANOX, DDR_G2,           HERMON),
94         HCA(MELLANOX, QDR_G2,           HERMON),
95         HCA(MELLANOX, ETH_G2,           HERMON),
96         HCA(MELLANOX, ETH_YATIR_G2,             HERMON),
97         HCA(MELLANOX, BD,               LIVEFISH),
98 };
99 #define MLX4_PCI_TABLE_SIZE (sizeof(mlx4_pci_table)/sizeof(struct pci_device_id))
100
101
102 static int mlx4_check_port_params(struct mlx4_dev *dev,
103                                   enum mlx4_port_type *port_type)
104 {
105         if (port_type[0] != port_type[1] &&
106             !(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
107                 mlx4_err(dev, "Only same port types supported "
108                               "on this HCA, aborting.\n");
109                 return -EINVAL;
110         }
111         if ((port_type[0] == MLX4_PORT_TYPE_ETH) &&
112             (port_type[1] == MLX4_PORT_TYPE_IB)) {
113                 mlx4_err(dev, "eth-ib configuration is not supported.\n");
114                 return -EINVAL;
115         }
116         return 0;
117 }
118
119 static void mlx4_str2port_type(WCHAR **port_str,
120                                enum mlx4_port_type *port_type)
121 {
122         int i;
123
124         for (i = 0; i < MLX4_MAX_PORTS; i++) {
125                 if (!wcscmp(port_str[i], L"eth"))
126                         port_type[i] = MLX4_PORT_TYPE_ETH;
127                 else
128                         port_type[i] = MLX4_PORT_TYPE_IB;
129         }
130 }
131
132 int mlx4_count_ib_ports(struct mlx4_dev *dev)
133 {
134         int i;
135         int count = 0;
136
137         for (i = 0; i < MLX4_MAX_PORTS; i++) {
138                 if (dev->caps.port_type[i+1] == MLX4_PORT_TYPE_IB) {
139                         count++;
140                 }
141         }
142         return count;
143 }
144
145 BOOLEAN mlx4_is_eth_port(struct mlx4_dev *dev, int port_number)
146 {
147         if (dev->caps.port_type[port_number+1] == MLX4_PORT_TYPE_ETH) {
148                 return TRUE;
149         }
150         return FALSE;
151 }
152
153 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
154 {
155         int err;
156         int i;
157         int num_eth_ports = 0;
158         enum mlx4_port_type port_type[MLX4_MAX_PORTS];
159         struct mlx4_dev *mdev = dev;
160
161         for (i = 0; i < MLX4_MAX_PORTS; i++) 
162                 port_type[i] = g.mod_port_type[i];
163
164         err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
165         if (err) {
166                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
167                 return err;
168         }
169
170         if (dev_cap->min_page_sz > PAGE_SIZE) {
171                 mlx4_err(dev, "HCA minimum page size of %d bigger than "
172                          "kernel PAGE_SIZE of %ld, aborting.\n",
173                          dev_cap->min_page_sz, PAGE_SIZE);
174                 return -ENODEV;
175         }
176         if (dev_cap->num_ports > MLX4_MAX_PORTS) {
177                 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
178                          "aborting.\n",
179                          dev_cap->num_ports, MLX4_MAX_PORTS);
180                 return -ENODEV;
181         }
182
183         if (dev_cap->uar_size > (int)pci_resource_len(dev->pdev, 2)) {
184                 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than "
185                          "PCI resource 2 size of 0x%llx, aborting.\n",
186                          dev_cap->uar_size,
187                          (unsigned long long) pci_resource_len(dev->pdev, 2));
188                 return -ENODEV;
189         }
190
191         dev->caps.num_ports          = dev_cap->num_ports;
192         for (i = 1; i <= dev->caps.num_ports; ++i) {
193                 dev->caps.vl_cap[i]         = dev_cap->max_vl[i];
194                 dev->caps.ib_mtu_cap[i]     = dev_cap->ib_mtu[i];       
195                 dev->caps.gid_table_len[i]  = dev_cap->max_gids[i];
196                 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
197                 dev->caps.port_width_cap[i] = (u8)dev_cap->max_port_width[i];
198                 dev->caps.eth_mtu_cap[i]    = dev_cap->eth_mtu[i];
199                 dev->caps.def_mac[i]        = dev_cap->def_mac[i];        
200         }
201
202         dev->caps.num_uars           = dev_cap->uar_size / PAGE_SIZE;
203         dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
204         dev->caps.bf_reg_size        = dev_cap->bf_reg_size;
205         dev->caps.bf_regs_per_page   = dev_cap->bf_regs_per_page;
206         dev->caps.max_sq_sg          = dev_cap->max_sq_sg;
207         dev->caps.max_rq_sg          = dev_cap->max_rq_sg;
208         dev->caps.max_wqes           = dev_cap->max_qp_sz;
209         dev->caps.max_qp_init_rdma   = dev_cap->max_requester_per_qp;
210         dev->caps.max_srq_wqes       = dev_cap->max_srq_sz;
211         dev->caps.max_srq_sge        = dev_cap->max_rq_sg - 1;
212         dev->caps.reserved_srqs      = dev_cap->reserved_srqs;
213         dev->caps.max_sq_desc_sz     = dev_cap->max_sq_desc_sz;
214         dev->caps.max_rq_desc_sz     = dev_cap->max_rq_desc_sz;
215         dev->caps.num_qp_per_mgm     = MLX4_QP_PER_MGM;
216         /*
217          * Subtract 1 from the limit because we need to allocate a
218          * spare CQE so the HCA HW can tell the difference between an
219          * empty CQ and a full CQ.
220          */
221         dev->caps.max_cqes           = dev_cap->max_cq_sz - 1;
222         dev->caps.reserved_cqs       = dev_cap->reserved_cqs;
223         dev->caps.reserved_eqs       = dev_cap->reserved_eqs;
224         dev->caps.reserved_mtts      = DIV_ROUND_UP(dev_cap->reserved_mtts,
225                                                     MLX4_MTT_ENTRY_PER_SEG);
226         dev->caps.reserved_mrws      = dev_cap->reserved_mrws;
227         dev->caps.reserved_uars      = dev_cap->reserved_uars;
228         dev->caps.reserved_pds       = dev_cap->reserved_pds;
229         dev->caps.mtt_entry_sz       = MLX4_MTT_ENTRY_PER_SEG * dev_cap->mtt_entry_sz;
230         dev->caps.max_msg_sz         = dev_cap->max_msg_sz;
231         dev->caps.page_size_cap      = ~(u32) (dev_cap->min_page_sz - 1);
232         dev->caps.flags              = dev_cap->flags;
233         dev->caps.stat_rate_support  = dev_cap->stat_rate_support;
234         dev->caps.max_gso_sz         = dev_cap->max_gso_sz;
235
236         dev->caps.log_num_macs  = ilog2(roundup_pow_of_two
237                                         (g.mod_num_mac + 1));
238         dev->caps.log_num_vlans = ilog2(roundup_pow_of_two
239                                         (g.mod_num_vlan + 2));
240         dev->caps.log_num_prios = (g.mod_use_prio)? 3: 0;
241
242         err = mlx4_check_port_params(dev, port_type);
243         if (err)
244                 return err;
245
246         for (i = 1; i <= dev->caps.num_ports; ++i) {
247                 if (!dev_cap->supported_port_types[i]) {
248                         mlx4_warn(dev, "FW doesn't support Multi Protocol, "
249                                        "loading IB only\n");
250                         dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
251                         continue;
252                 }
253                 if (port_type[i-1] & dev_cap->supported_port_types[i])
254                         dev->caps.port_type[i] = port_type[i-1];
255                 else {
256                         MLX4_PRINT_EV(TRACE_LEVEL_ERROR ,MLX4_DBG_DRV ,
257                                 ("Requested port type %#x for port %d is "
258                                 "not supported by HW. Supported %#x\n", 
259                                 port_type[i-1], i, (int)dev_cap->supported_port_types[i]));
260                         MLX4_PRINT_EV(TRACE_LEVEL_ERROR ,MLX4_DBG_DRV ,
261                                 ("Ven %x Dev %d Fw %d.%d.%d, IsBurnDevice %s\n", 
262                                 (unsigned)dev->pdev->ven_id, (unsigned)dev->pdev->dev_id,
263                                 (int) (dev->caps.fw_ver >> 32),
264                                 (int) (dev->caps.fw_ver >> 16) & 0xffff, 
265                                 (int) (dev->caps.fw_ver & 0xffff),
266                                 mlx4_is_livefish(dev) ? "Y" : "N"
267                                 ));
268                         
269                         return -ENODEV;
270                 }
271                 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) {
272                         dev->caps.log_num_macs = dev_cap->log_max_macs[i];
273                         mlx4_warn(dev, "Requested number of MACs is too much "
274                                        "for port %d, reducing to %d.\n",
275                                         i, 1 << dev->caps.log_num_macs);
276                 }
277                 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) {
278                         dev->caps.log_num_vlans = dev_cap->log_max_vlans[i];
279                         mlx4_warn(dev, "Requested number of VLANs is too much "
280                                        "for port %d, reducing to %d.\n",
281                                         i, 1 << dev->caps.log_num_vlans);
282                 }
283                 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
284                         ++num_eth_ports;
285         }
286
287         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
288         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
289                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
290                 (1 << dev->caps.log_num_macs)*
291                 (1 << dev->caps.log_num_vlans)*
292                 (1 << dev->caps.log_num_prios)*
293                 num_eth_ports;
294         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
295
296         return 0;
297 }
298
299 static int __devinit mlx4_load_fw(struct mlx4_dev *dev)
300 {
301         struct mlx4_priv *priv = mlx4_priv(dev);
302         int err;
303
304         priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
305                                          GFP_HIGHUSER | __GFP_NOWARN, 0);
306         if (!priv->fw.fw_icm) {
307                 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n");
308                 return -ENOMEM;
309         }
310
311         err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
312         if (err) {
313                 mlx4_err(dev, "MAP_FA command failed, aborting.\n");
314                 goto err_free;
315         }
316
317         err = mlx4_RUN_FW(dev);
318         if (err) {
319                 mlx4_err(dev, "RUN_FW command failed, aborting.\n");
320                 goto err_unmap_fa;
321         }
322
323         return 0;
324
325 err_unmap_fa:
326         mlx4_UNMAP_FA(dev);
327
328 err_free:
329         mlx4_free_icm(dev, priv->fw.fw_icm, 0);
330         return err;
331 }
332
333 static int __devinit mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
334                                           int cmpt_entry_sz)
335 {
336         struct mlx4_priv *priv = mlx4_priv(dev);
337         int err;
338
339         err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
340                                   cmpt_base +
341                                   ((u64) (MLX4_CMPT_TYPE_QP *
342                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
343                                   cmpt_entry_sz, dev->caps.num_qps,
344                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
345                                   0, 0);
346         if (err)
347                 goto err;
348
349         err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
350                                   cmpt_base +
351                                   ((u64) (MLX4_CMPT_TYPE_SRQ *
352                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
353                                   cmpt_entry_sz, dev->caps.num_srqs,
354                                   dev->caps.reserved_srqs, 0, 0);
355         if (err)
356                 goto err_qp;
357
358         err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
359                                   cmpt_base +
360                                   ((u64) (MLX4_CMPT_TYPE_CQ *
361                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
362                                   cmpt_entry_sz, dev->caps.num_cqs,
363                                   dev->caps.reserved_cqs, 0, 0);
364         if (err)
365                 goto err_srq;
366
367         err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
368                                   cmpt_base +
369                                   ((u64) (MLX4_CMPT_TYPE_EQ *
370                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
371                                   cmpt_entry_sz,
372                                   roundup_pow_of_two(MLX4_NUM_EQ +
373                                                      dev->caps.reserved_eqs),
374                                   MLX4_NUM_EQ + dev->caps.reserved_eqs, 0, 0);
375         if (err)
376                 goto err_cq;
377
378         return 0;
379
380 err_cq:
381         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
382
383 err_srq:
384         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
385
386 err_qp:
387         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
388
389 err:
390         return err;
391 }
392
393 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
394                          struct mlx4_init_hca_param *init_hca, u64 icm_size)
395 {
396         struct mlx4_priv *priv = mlx4_priv(dev);
397         u64 aux_pages;
398         int err;
399
400         err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
401         if (err) {
402                 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n");
403                 return err;
404         }
405
406         mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n",
407                  (unsigned long long) icm_size >> 10,
408                  (unsigned long long) aux_pages << 2);
409
410         priv->fw.aux_icm = mlx4_alloc_icm(dev, (int)aux_pages,
411                                           GFP_HIGHUSER | __GFP_NOWARN, 0);
412         if (!priv->fw.aux_icm) {
413                 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n");
414                 return -ENOMEM;
415         }
416
417         err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
418         if (err) {
419                 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n");
420                 goto err_free_aux;
421         }
422
423         err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
424         if (err) {
425                 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n");
426                 goto err_unmap_aux;
427         }
428
429         err = mlx4_map_eq_icm(dev, init_hca->eqc_base);
430         if (err) {
431                 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n");
432                 goto err_unmap_cmpt;
433         }
434
435         /*
436          * Reserved MTT entries must be aligned up to a cacheline
437          * boundary, since the FW will write to them, while the driver
438          * writes to all other MTT entries. (The variable
439          * dev->caps.mtt_entry_sz below is really the MTT segment
440          * size, not the raw entry size)
441          */
442         dev->caps.reserved_mtts =
443                 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
444                       dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
445         if ( dev->pdev->p_self_do->AlignmentRequirement + 1 != dma_get_cache_alignment()) {
446                 mlx4_dbg(dev, "Cache-line size %d, recommended value %d.\n",
447                         dev->pdev->p_self_do->AlignmentRequirement + 1,
448                         dma_get_cache_alignment() );
449         }
450
451         err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
452                                   init_hca->mtt_base,
453                                   dev->caps.mtt_entry_sz,
454                                   dev->caps.num_mtt_segs,
455                                   dev->caps.reserved_mtts, 1, 0);
456         if (err) {
457                 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n");
458                 goto err_unmap_eq;
459         }
460
461         err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
462                                   init_hca->dmpt_base,
463                                   dev_cap->dmpt_entry_sz,
464                                   dev->caps.num_mpts,
465                                   dev->caps.reserved_mrws, 1, 1);
466         if (err) {
467                 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n");
468                 goto err_unmap_mtt;
469         }
470
471         err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
472                                   init_hca->qpc_base,
473                                   dev_cap->qpc_entry_sz,
474                                   dev->caps.num_qps,
475                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
476                                   0, 0);
477         if (err) {
478                 mlx4_err(dev, "Failed to map QP context memory, aborting.\n");
479                 goto err_unmap_dmpt;
480         }
481
482         err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
483                                   init_hca->auxc_base,
484                                   dev_cap->aux_entry_sz,
485                                   dev->caps.num_qps,
486                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
487                                   0, 0);
488         if (err) {
489                 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n");
490                 goto err_unmap_qp;
491         }
492
493         err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
494                                   init_hca->altc_base,
495                                   dev_cap->altc_entry_sz,
496                                   dev->caps.num_qps,
497                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
498                                   0, 0);
499         if (err) {
500                 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n");
501                 goto err_unmap_auxc;
502         }
503
504         err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
505                                   init_hca->rdmarc_base,
506                                   dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
507                                   dev->caps.num_qps,
508                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
509                                   0, 0);
510         if (err) {
511                 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
512                 goto err_unmap_altc;
513         }
514
515         err = mlx4_init_icm_table(dev, &priv->cq_table.table,
516                                   init_hca->cqc_base,
517                                   dev_cap->cqc_entry_sz,
518                                   dev->caps.num_cqs,
519                                   dev->caps.reserved_cqs, 0, 0);
520         if (err) {
521                 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n");
522                 goto err_unmap_rdmarc;
523         }
524
525         err = mlx4_init_icm_table(dev, &priv->srq_table.table,
526                                   init_hca->srqc_base,
527                                   dev_cap->srq_entry_sz,
528                                   dev->caps.num_srqs,
529                                   dev->caps.reserved_srqs, 0, 0);
530         if (err) {
531                 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n");
532                 goto err_unmap_cq;
533         }
534
535         /*
536          * It's not strictly required, but for simplicity just map the
537          * whole multicast group table now.  The table isn't very big
538          * and it's a lot easier than trying to track ref counts.
539          */
540         err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
541                                   init_hca->mc_base, MLX4_MGM_ENTRY_SIZE,
542                                   dev->caps.num_mgms + dev->caps.num_amgms,
543                                   dev->caps.num_mgms + dev->caps.num_amgms,
544                                   0, 0);
545         if (err) {
546                 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n");
547                 goto err_unmap_srq;
548         }
549
550         return 0;
551
552 err_unmap_srq:
553         mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
554
555 err_unmap_cq:
556         mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
557
558 err_unmap_rdmarc:
559         mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
560
561 err_unmap_altc:
562         mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
563
564 err_unmap_auxc:
565         mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
566
567 err_unmap_qp:
568         mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
569
570 err_unmap_dmpt:
571         mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
572
573 err_unmap_mtt:
574         mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
575
576 err_unmap_eq:
577         mlx4_unmap_eq_icm(dev);
578
579 err_unmap_cmpt:
580         mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
581         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
582         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
583         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
584
585 err_unmap_aux:
586         mlx4_UNMAP_ICM_AUX(dev);
587
588 err_free_aux:
589         mlx4_free_icm(dev, priv->fw.aux_icm, 0);
590
591         return err;
592 }
593
594 static void mlx4_free_icms(struct mlx4_dev *dev)
595 {
596         struct mlx4_priv *priv = mlx4_priv(dev);
597
598         mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
599         mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
600         mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
601         mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
602         mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
603         mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
604         mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
605         mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
606         mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
607         mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
608         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
609         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
610         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
611         mlx4_unmap_eq_icm(dev);
612
613         mlx4_UNMAP_ICM_AUX(dev);
614         mlx4_free_icm(dev, priv->fw.aux_icm, 0);
615 }
616
617 static void mlx4_close_hca(struct mlx4_dev *dev)
618 {
619         mlx4_CLOSE_HCA(dev, 0);
620         mlx4_free_icms(dev);
621         mlx4_UNMAP_FA(dev);
622         mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
623 }
624
625 static int mlx4_init_hca(struct mlx4_dev *dev)
626 {
627         struct mlx4_priv          *priv = mlx4_priv(dev);
628         struct mlx4_adapter        adapter;
629         struct mlx4_dev_cap        dev_cap;
630         struct mlx4_profile        profile;
631         struct mlx4_init_hca_param init_hca;
632         u64 icm_size;
633         int err;
634
635         err = mlx4_QUERY_FW(dev);
636         if (err) {
637                 mlx4_err(dev, "QUERY_FW command failed, aborting.\n");
638                 return err;
639         }
640
641         err = mlx4_load_fw(dev);
642         if (err) {
643                 mlx4_err(dev, "Failed to start FW, aborting.\n");
644                 return err;
645         }
646
647         err = mlx4_dev_cap(dev, &dev_cap);
648         if (err) {
649                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
650                 goto err_stop_fw;
651         }
652
653         process_mod_param_profile();
654         profile = default_profile;
655
656         icm_size = mlx4_make_profile(dev, &profile, &dev_cap, &init_hca);
657         if ((long long) icm_size < 0) {
658                 err = (int)icm_size;
659                 goto err_stop_fw;
660         }
661
662         init_hca.log_uar_sz = (u8)ilog2(dev->caps.num_uars);
663
664         err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
665         if (err)
666                 goto err_stop_fw;
667
668         err = mlx4_INIT_HCA(dev, &init_hca);
669         if (err) {
670                 mlx4_err(dev, "INIT_HCA command failed, aborting.\n");
671                 goto err_free_icm;
672         }
673
674         err = mlx4_QUERY_ADAPTER(dev, &adapter);
675         if (err) {
676                 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n");
677                 goto err_close;
678         }
679
680         priv->eq_table.inta_pin = adapter.inta_pin;
681         memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
682
683         return 0;
684
685 err_close:
686         mlx4_close_hca(dev);
687
688 err_free_icm:
689         mlx4_free_icms(dev);
690
691 err_stop_fw:
692         mlx4_UNMAP_FA(dev);
693         mlx4_free_icm(dev, priv->fw.fw_icm, 0);
694
695         return err;
696 }
697
698 static int mlx4_setup_hca(struct mlx4_dev *dev)
699 {
700         struct mlx4_priv *priv = mlx4_priv(dev);
701         int err;
702         u8 port;
703
704         err = mlx4_init_uar_table(dev);
705         if (err) {
706                 mlx4_err(dev, "Failed to initialize "
707                          "user access region table, aborting.\n");
708                 return err;
709         }
710
711         err = mlx4_uar_alloc(dev, &priv->driver_uar);
712         if (err) {
713                 mlx4_err(dev, "Failed to allocate driver access region, "
714                          "aborting.\n");
715                 goto err_uar_table_free;
716         }
717
718         priv->kar = ioremap((u64)priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
719         if (!priv->kar) {
720                 mlx4_err(dev, "Couldn't map kernel access region, "
721                          "aborting.\n");
722                 err = -ENOMEM;
723                 goto err_uar_free;
724         }
725
726         err = mlx4_init_pd_table(dev);
727         if (err) {
728                 mlx4_err(dev, "Failed to initialize "
729                          "protection domain table, aborting.\n");
730                 goto err_kar_unmap;
731         }
732
733         err = mlx4_init_mr_table(dev);
734         if (err) {
735                 mlx4_err(dev, "Failed to initialize "
736                          "memory region table, aborting.\n");
737                 goto err_pd_table_free;
738         }
739
740         
741         err = mlx4_init_eq_table(dev);
742         if (err) {
743                 mlx4_err(dev, "Failed to initialize "
744                          "event queue table, aborting.\n");
745                 goto err_mr_table_free;
746         }
747
748         err = mlx4_cmd_use_events(dev);
749         if (err) {
750                 mlx4_err(dev, "Failed to switch to event-driven "
751                          "firmware commands, aborting.\n");
752                 goto err_eq_table_free;
753         }
754
755         err = mlx4_NOP(dev);
756         if (err) {
757                 if (dev->flags & MLX4_FLAG_MSI_X) {
758                         mlx4_warn(dev, "NOP command failed to generate MSI-X "
759                                   "interrupt IRQ %d).\n",
760                                   priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
761                         mlx4_warn(dev, "Trying again without MSI-X.\n");
762                 } else {
763                         mlx4_err(dev, "NOP command failed to generate interrupt "
764                                  "(IRQ %d), aborting.\n",
765                                  priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
766                         mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
767                 }
768
769                 goto err_cmd_poll;
770         }
771
772         mlx4_dbg(dev, "NOP command IRQ test passed\n");
773
774         err = mlx4_init_cq_table(dev);
775         if (err) {
776                 mlx4_err(dev, "Failed to initialize "
777                          "completion queue table, aborting.\n");
778                 goto err_cmd_poll;
779         }
780
781         err = mlx4_init_srq_table(dev);
782         if (err) {
783                 mlx4_err(dev, "Failed to initialize "
784                          "shared receive queue table, aborting.\n");
785                 goto err_cq_table_free;
786         }
787
788         err = mlx4_init_qp_table(dev);
789         if (err) {
790                 mlx4_err(dev, "Failed to initialize "
791                          "queue pair table, aborting.\n");
792                 goto err_srq_table_free;
793         }
794
795         err = mlx4_init_mcg_table(dev);
796         if (err) {
797                 mlx4_err(dev, "Failed to initialize "
798                          "multicast group table, aborting.\n");
799                 goto err_qp_table_free;
800         }
801         for (port = 1; port <= dev->caps.num_ports; port++) {
802                 err = mlx4_SET_PORT(dev, port,0 ,0);
803                 if (err) {
804                         mlx4_err(dev, "Failed to set port %d, aborting\n",
805                                  port);
806                         goto err_mcg_table_free;
807                 }
808         }
809
810         for (port = 0; port < dev->caps.num_ports; port++) {
811                 mlx4_init_mac_table(dev, port);
812                 mlx4_init_vlan_table(dev, port);
813         }
814
815         return 0;
816 err_mcg_table_free:
817         mlx4_cleanup_mcg_table(dev);
818
819 err_qp_table_free:
820         mlx4_cleanup_qp_table(dev);
821
822 err_srq_table_free:
823         mlx4_cleanup_srq_table(dev);
824
825 err_cq_table_free:
826         mlx4_cleanup_cq_table(dev);
827
828 err_cmd_poll:
829         mlx4_cmd_use_polling(dev);
830
831 err_eq_table_free:
832         mlx4_cleanup_eq_table(dev);
833
834 err_mr_table_free:
835         mlx4_cleanup_mr_table(dev);
836
837 err_pd_table_free:
838         mlx4_cleanup_pd_table(dev);
839
840 err_kar_unmap:
841         iounmap(priv->kar,PAGE_SIZE);
842
843 err_uar_free:
844         mlx4_uar_free(dev, &priv->driver_uar);
845
846 err_uar_table_free:
847         mlx4_cleanup_uar_table(dev);
848         return err;
849 }
850
851 static void __devinit mlx4_enable_msi_x(struct mlx4_dev *dev)
852 {
853 #ifdef CONFIG_PCI_MSI
854         struct mlx4_priv *priv = mlx4_priv(dev);
855         struct msix_entry entries[MLX4_NUM_EQ];
856         int err;
857         int i;
858
859         if (g.mod_msi_num_vector) {
860                 for (i = 0; i < MLX4_NUM_EQ; ++i)
861                         entries[i].entry = i;
862
863                 err = pci_enable_msix(dev->pdev, entries, ARRAY_SIZE(entries));
864                 if (err) {
865                         if (err > 0)
866                                 mlx4_info(dev, "Only %d MSI-X vectors available, "
867                                           "not using MSI-X\n", err);
868                         goto no_msi;
869                 }
870
871                 for (i = 0; i < MLX4_NUM_EQ; ++i)
872                         priv->eq_table.eq[i].irq = entries[i].vector;
873
874                 dev->flags |= MLX4_FLAG_MSI_X;
875                 return;
876         }
877
878 no_msi:
879         for (i = 0; i < MLX4_NUM_EQ; ++i)
880                 priv->eq_table.eq[i].irq = dev->pdev->irq;
881
882 #else
883         UNUSED_PARAM(dev);
884 #endif
885 }
886
887
888 static struct pci_device_id * mlx4_find_pci_dev(USHORT ven_id, USHORT dev_id)
889 {
890         struct pci_device_id *p_id = mlx4_pci_table;
891         int i;
892
893         // find p_id (appropriate line in mlx4_pci_table)
894         for (i = 0; i < MLX4_PCI_TABLE_SIZE; ++i, ++p_id) {
895                 if (p_id->device == dev_id && p_id->vendor ==  ven_id)
896                         return p_id;
897         }
898         return NULL;
899 }
900
901 int mlx4_init_one(struct pci_dev *pdev)
902 {
903         struct pci_device_id *id;
904         struct mlx4_priv *priv;
905         struct mlx4_dev *dev;
906         int err;
907         NTSTATUS status;
908
909 #ifdef FORCE_LIVEFISH
910                 if (pdev)
911                         goto err;
912 #endif
913
914         /* find the type of device */
915         id = mlx4_find_pci_dev(pdev->ven_id, pdev->dev_id);
916         if (id == NULL) {
917                 err = -ENOSYS;
918                 goto err;
919         }
920
921         /*
922          * Check for BARs.  We expect 0: 1MB, 2: 8MB, 4: DDR (may not
923          * be present)
924          */
925         if (pci_resource_len(pdev, 0) != 1 << 20) {
926                 MLX4_PRINT(TRACE_LEVEL_INFORMATION ,MLX4_DBG_LOW ,
927                         ("Missing DCS, aborting.\n"));
928                 err = -ENODEV;
929                 goto err;
930         }
931         if (!pci_resource_len(pdev, 1)) {
932                 MLX4_PRINT(TRACE_LEVEL_INFORMATION ,MLX4_DBG_LOW ,
933                         ("Missing UAR, aborting.\n"));
934                 err = -ENODEV;
935                 goto err;
936         }
937
938 run_as_livefish:
939         /* allocate mlx4_priv structure */
940         priv = kzalloc(sizeof *priv, GFP_KERNEL);
941         if (!priv) {
942                 MLX4_PRINT(TRACE_LEVEL_INFORMATION ,MLX4_DBG_LOW ,
943                         ("Device struct alloc failed, aborting.\n"));
944                 err = -ENOMEM;
945                 goto end;
946         }
947         /* must be here for livefish */
948         INIT_LIST_HEAD(&priv->ctx_list);
949         spin_lock_init(&priv->ctx_lock);
950
951         INIT_LIST_HEAD(&priv->pgdir_list);
952         mutex_init(&priv->pgdir_mutex);
953
954         /* deal with livefish, if any */
955         dev       = &priv->dev;
956         dev->pdev = pdev;
957         pdev->dev = dev;
958         if (id->driver_data == LIVEFISH)
959                 dev->flags |= MLX4_FLAG_LIVEFISH;
960         if (mlx4_is_livefish(dev)) {
961                 err = mlx4_register_device(dev);
962                 if (err)
963                         MLX4_PRINT(TRACE_LEVEL_INFORMATION ,MLX4_DBG_LOW ,
964                                 ("mlx4_register_device for livefish failed, trying to proceed.\n"));
965                 goto end;
966         }
967
968         /*
969          * Now reset the HCA before we touch the PCI capabilities or
970          * attempt a firmware command, since a boot ROM may have left
971          * the HCA in an undefined state.
972          */
973         status = mlx4_reset(dev);
974         if ( !NT_SUCCESS( status ) ) {
975                 mlx4_err(dev, "Failed to reset HCA, aborting.(status %#x)\n", status);
976                 err = -EFAULT;
977                 goto err_free_dev;
978         }
979
980         if (mlx4_cmd_init(dev)) {
981                 mlx4_err(dev, "Failed to init command interface, aborting.\n");
982                 goto err_free_dev;
983         }
984
985         err = mlx4_init_hca(dev);
986         if (err)
987                 goto err_cmd;
988
989         mlx4_enable_msi_x(dev);
990
991         err = mlx4_setup_hca(dev);
992         if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X)) {
993 #ifdef CONFIG_PCI_MSI
994                 dev->flags &= ~MLX4_FLAG_MSI_X;
995                 pci_disable_msix(pdev);
996 #endif          
997                 err = mlx4_setup_hca(dev);
998         }
999
1000         if (err)
1001                 goto err_close;
1002
1003         err = mlx4_register_device(dev);
1004         if (err)
1005                 goto err_cleanup;
1006
1007         mlx4_dbg(dev, "MLX4_BUS: NET device (dev_id=%d) is INITIALIZED ! \n", (int)pdev->dev_id);
1008         return 0;
1009
1010 err_cleanup:
1011         mlx4_cleanup_mcg_table(dev);
1012         mlx4_cleanup_qp_table(dev);
1013         mlx4_cleanup_srq_table(dev);
1014         mlx4_cleanup_cq_table(dev);
1015         mlx4_cmd_use_polling(dev);
1016         mlx4_cleanup_eq_table(dev);
1017         mlx4_cleanup_mr_table(dev);
1018         mlx4_cleanup_pd_table(dev);
1019         mlx4_cleanup_uar_table(dev);
1020
1021 err_close:
1022 #ifdef CONFIG_PCI_MSI
1023         if (dev->flags & MLX4_FLAG_MSI_X)
1024                 pci_disable_msix(pdev);
1025 #endif
1026
1027         mlx4_close_hca(dev);
1028
1029 err_cmd:
1030         mlx4_cmd_cleanup(dev);
1031
1032 err_free_dev:
1033         kfree(priv);
1034
1035 err:
1036         /* we failed device initialization - try to simulate "livefish" device to facilitate using FW burning tools */
1037         id = mlx4_find_pci_dev(pdev->ven_id, DEVID_HERMON_BD);
1038         if (id == NULL) {
1039                 err = -ENOSYS;
1040                 goto end;
1041         }
1042         goto run_as_livefish;
1043
1044 end:    
1045         return err;
1046 }
1047
1048 void mlx4_remove_one(struct pci_dev *pdev)
1049 {
1050         struct mlx4_dev  *dev  = pdev->dev;
1051         struct mlx4_priv *priv = mlx4_priv(dev);
1052         int p;
1053
1054         if (dev) {
1055                 mlx4_unregister_device(dev);
1056                 if (mlx4_is_livefish(dev))
1057                         goto done;
1058
1059                 for (p = 1; p <= dev->caps.num_ports; ++p)
1060                         mlx4_CLOSE_PORT(dev, p);
1061
1062                 mlx4_cleanup_mcg_table(dev);
1063                 mlx4_cleanup_qp_table(dev);
1064                 mlx4_cleanup_srq_table(dev);
1065                 mlx4_cleanup_cq_table(dev);
1066                 mlx4_cmd_use_polling(dev);
1067                 mlx4_cleanup_eq_table(dev);
1068                 mlx4_cleanup_mr_table(dev);
1069                 mlx4_cleanup_pd_table(dev);
1070
1071                 iounmap(priv->kar,PAGE_SIZE);
1072                 mlx4_uar_free(dev, &priv->driver_uar);
1073                 mlx4_cleanup_uar_table(dev);
1074                 mlx4_close_hca(dev);
1075                 mlx4_cmd_cleanup(dev);
1076
1077 #ifdef CONFIG_PCI_MSI
1078                 if (dev->flags & MLX4_FLAG_MSI_X)
1079                         pci_disable_msix(pdev);
1080 #endif
1081
1082                 mlx4_reset(dev);
1083                 mlx4_dbg(dev, "MLX4_BUS: NET device (dev_id=%d) is REMOVED ! \n", (int)pdev->dev_id);
1084                 pdev->dev = NULL;
1085 done:
1086                 kfree(priv);
1087         }
1088 }
1089
1090 int mlx4_restart_one(struct pci_dev *pdev)
1091 {
1092         mlx4_remove_one(pdev);
1093         return mlx4_init_one(pdev);
1094 }
1095
1096 void mlx4_net_init()
1097 {
1098         mlx4_intf_init();
1099 }
1100
1101