[IBAL, HCA] Provide HCA driver with UM CA handle for resource
[mirror/winof/.git] / hw / mt23108 / kernel / hca_data.h
1 /*\r
2  * Copyright (c) 2005 SilverStorm Technologies.  All rights reserved.\r
3  * Copyright (c) 2004-2005 Mellanox Technologies, Inc. All rights reserved. \r
4  *\r
5  * This software is available to you under the OpenIB.org BSD license\r
6  * below:\r
7  *\r
8  *     Redistribution and use in source and binary forms, with or\r
9  *     without modification, are permitted provided that the following\r
10  *     conditions are met:\r
11  *\r
12  *      - Redistributions of source code must retain the above\r
13  *        copyright notice, this list of conditions and the following\r
14  *        disclaimer.\r
15  *\r
16  *      - Redistributions in binary form must reproduce the above\r
17  *        copyright notice, this list of conditions and the following\r
18  *        disclaimer in the documentation and/or other materials\r
19  *        provided with the distribution.\r
20  *\r
21  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
22  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
23  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
24  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
25  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
26  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
27  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
28  * SOFTWARE.\r
29  *\r
30  * $Id$\r
31  */\r
32 \r
33 #ifndef __HCA_DATA_H__\r
34 #define __HCA_DATA_H__\r
35 \r
36 \r
37 #include <iba/ib_ci.h>\r
38 #include <complib/comp_lib.h>\r
39 \r
40 #include <vapi.h>\r
41 #include <evapi.h>\r
42 #include <hh.h>\r
43 #include <thh.h>\r
44 #include <thh_hob.h>\r
45 #include <tavor_dev_defs.h>\r
46 #include <thh_init.h>\r
47 #include <hhul.h>\r
48 #include <thhul_hob.h>\r
49 #include <thhul_pdm.h>\r
50 #include <thhul_cqm.h>\r
51 #include <thhul_qpm.h>\r
52 \r
53 extern u_int32_t                g_mlnx_dbg_lvl;\r
54 extern uint32_t                 g_sqp_max_avs;\r
55 extern char                             mlnx_uvp_lib_name[];\r
56 \r
57 #define MLNX_DBG_INFO    (1<<1)\r
58 #define MLNX_DBG_TRACE   (1<<2)\r
59 #define MLNX_DBG_VERBOSE (1<<3)\r
60 // for data path debugging\r
61 #define MLNX_DBG_DIRECT  (1<<4)\r
62 #define MLNX_DBG_QPN     (1<<5)\r
63 #define MLNX_DBG_MEM     (1<<6)\r
64 \r
65 #define MLNX_MAX_HCA   4\r
66 #define MLNX_NUM_HOBKL MLNX_MAX_HCA\r
67 #define MLNX_NUM_HOBUL MLNX_MAX_HCA\r
68 #define MLNX_NUM_CB_THR     1\r
69 #define MLNX_SIZE_CB_POOL 256\r
70 #define MLNX_UAL_ALLOC_HCA_UL_RES 1\r
71 #define MLNX_UAL_FREE_HCA_UL_RES 2\r
72 \r
73 \r
74 // Defines for QP ops\r
75 #define MLNX_MAX_NUM_SGE 8\r
76 #define MLNX_MAX_WRS_PER_CHAIN 4\r
77 \r
78 #define MLNX_NUM_RESERVED_QPS 16\r
79 \r
80 /*\r
81  * Completion model.\r
82  *      0: No DPC processor assignment\r
83  *      1: DPCs per-CQ, processor affinity set at CQ initialization time.\r
84  *      2: DPCs per-CQ, processor affinity set at runtime.\r
85  *      3: DPCs per-CQ, no processor affinity set.\r
86  */\r
87 #define MLNX_COMP_MODEL         3\r
88 \r
89 #define PD_HCA_FROM_HNDL(hndl) (((pd_info_t *)hndl)->hca_idx)\r
90 #define PD_NUM_FROM_HNDL(hndl) (((pd_info_t *)hndl)->pd_num)\r
91 #define CQ_HCA_FROM_HNDL(hndl) (((cq_info_t *)hndl)->hca_idx)\r
92 #define CQ_NUM_FROM_HNDL(hndl) (((cq_info_t *)hndl)->cq_num)\r
93 #define QP_HCA_FROM_HNDL(hndl) (((qp_info_t *)hndl)->hca_idx)\r
94 #define QP_NUM_FROM_HNDL(hndl) (((qp_info_t *)hndl)->qp_num)\r
95 \r
96 #define PD_HNDL_FROM_PD(pd_num) (&hobul_p->pd_info_tbl[pd_num])\r
97 #define CQ_HNDL_FROM_CQ(cq_num) (&hobul_p->cq_info_tbl[cq_num])\r
98 #define QP_HNDL_FROM_QP(qp_num) (&hobul_p->qp_info_tbl[qp_num])\r
99 \r
100 #ifdef _DEBUG_\r
101 #define VALIDATE_INDEX(index, limit, error, label) \\r
102         {                  \\r
103                 if (index >= limit) \\r
104                 {                   \\r
105                         status = error;   \\r
106                         CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("file %s line %d\n", __FILE__, __LINE__)); \\r
107                         goto label;       \\r
108                 }                   \\r
109         }\r
110 #else\r
111 #define VALIDATE_INDEX(index, limit, error, label)\r
112 #endif\r
113 \r
114 \r
115 \r
116 // Typedefs\r
117 \r
118 typedef enum {\r
119         E_EV_CA=1,\r
120         E_EV_QP,\r
121         E_EV_CQ,\r
122         E_EV_LAST\r
123 } ENUM_EVENT_CLASS;\r
124 \r
125 typedef enum {\r
126         E_MARK_CA=1, // Channel Adaptor\r
127         E_MARK_PD, // Protection Domain\r
128         E_MARK_CQ, // Completion Queue\r
129         E_MARK_QP, // Queue Pair\r
130         E_MARK_AV, // Address Vector (UD)\r
131         E_MARK_MG, // Multicast Group\r
132         E_MARK_MR, // Memory Region\r
133         E_MARK_MW, // Memory Windows\r
134         E_MARK_INVALID,\r
135 } ENUM_MARK;\r
136 \r
137 typedef enum {\r
138         E_MR_PHYS=1,\r
139         E_MR_SHARED,\r
140         E_MR_ANY,\r
141         E_MR_INVALID\r
142 } ENUM_MR_TYPE;\r
143 \r
144 /*\r
145  * Attribute cache for port info saved to expedite local MAD processing.\r
146  * Note that the cache accounts for the worst case GID and PKEY table size\r
147  * but is allocated from paged pool, so it's nothing to worry about.\r
148  */\r
149 \r
150 typedef struct _guid_block\r
151 {\r
152         boolean_t                               valid;\r
153         ib_guid_info_t                  tbl;\r
154 \r
155 }       mlnx_guid_block_t;\r
156 \r
157 typedef struct _port_info_cache\r
158 {\r
159         boolean_t                               valid;\r
160         ib_port_info_t                  info;\r
161 \r
162 }       mlnx_port_info_cache_t;\r
163 \r
164 typedef struct _pkey_block\r
165 {\r
166         boolean_t                               valid;\r
167         ib_pkey_table_info_t    tbl;\r
168 \r
169 }       mlnx_pkey_block_t;\r
170 \r
171 typedef struct _sl_vl_cache\r
172 {\r
173         boolean_t                               valid;\r
174         ib_slvl_table_t                 tbl;\r
175 \r
176 }       mlnx_sl_vl_cache_t;\r
177 \r
178 typedef struct _vl_arb_block\r
179 {\r
180         boolean_t                               valid;\r
181         ib_vl_arb_table_t               tbl;\r
182 \r
183 }       mlnx_vl_arb_block_t;\r
184 \r
185 typedef struct _attr_cache\r
186 {\r
187         mlnx_guid_block_t               guid_block[32];\r
188         mlnx_port_info_cache_t  port_info;\r
189         mlnx_pkey_block_t               pkey_tbl[2048];\r
190         mlnx_sl_vl_cache_t              sl_vl;\r
191         mlnx_vl_arb_block_t             vl_arb[4];\r
192 \r
193 }       mlnx_cache_t;\r
194 \r
195 typedef struct _ib_ca {\r
196         ENUM_MARK           mark;\r
197         HH_hca_hndl_t       hh_hndl;\r
198         ci_completion_cb_t  comp_cb_p;\r
199         ci_async_event_cb_t async_cb_p;\r
200         const void          *ca_context;\r
201         void                *cl_device_h;\r
202         u_int32_t           index;\r
203         cl_async_proc_t     *async_proc_mgr_p;\r
204         mlnx_cache_t            *cache; // Cached port attributes.\r
205         const void * __ptr64    p_dev_obj; // store underlying device object\r
206 } mlnx_hob_t;\r
207 \r
208 typedef struct _ib_um_ca\r
209 {\r
210         MDL                                     *p_mdl;\r
211         void                            *p_mapped_addr;\r
212         HH_hca_hndl_t           hh_hndl;\r
213         mlnx_hob_t                      *hob_p;\r
214         /* The next two fields must be grouped together as the are mapped to UM. */\r
215         HH_hca_dev_t            dev_info;\r
216         uint8_t                         ul_hca_res[1];  // Beginning of UL resource buffer.\r
217 \r
218 }       mlnx_um_ca_t;\r
219 \r
220 typedef struct {\r
221         cl_async_proc_item_t async_item;\r
222         HH_hca_hndl_t        hh_hndl;\r
223         HH_cq_hndl_t         hh_cq; // for completion\r
224         HH_event_record_t    hh_er; // for async events\r
225         void                 *private_data;\r
226 } mlnx_cb_data_t;\r
227 \r
228 typedef struct {\r
229         cl_list_item_t  list_item;\r
230         HH_hca_hndl_t   hh_hndl;\r
231 //      char                    *hca_name_p;\r
232         net64_t                 guid;\r
233         const void* __ptr64     p_dev_obj;              // hca device object\r
234 //      ci_interface_t ifx;\r
235 } mlnx_hca_t;\r
236 \r
237 typedef struct _ib_pd {        /* struct of PD related resources */\r
238         ENUM_MARK         mark;\r
239         cl_mutex_t        mutex;\r
240         u_int32_t         kernel_mode;\r
241         atomic32_t        count;\r
242         u_int32_t         hca_idx;\r
243         // mlnx_hob_t        *hob_p;\r
244         HH_hca_hndl_t     hh_hndl;        /* For HH direct access */\r
245         HH_pd_hndl_t      pd_num;         /* For HH-UL direct access */\r
246         HHUL_pd_hndl_t    hhul_pd_hndl;\r
247         void              *pd_ul_resources_p;\r
248 } pd_info_t;\r
249 \r
250 typedef struct _ib_cq {        /* struct of CQ related resources */\r
251         ENUM_MARK         mark;\r
252         cl_mutex_t        mutex;\r
253         u_int32_t         hca_idx;\r
254         u_int32_t         kernel_mode;\r
255         // mlnx_hob_t        *hob_p;\r
256         HH_hca_hndl_t     hh_hndl;        /* For HH direct access */\r
257         HH_cq_hndl_t      cq_num;         /* For HH-UL direct access */\r
258 //      HH_pd_hndl_t      pd_num;         /* For HH-UL direct access */\r
259         HHUL_cq_hndl_t    hhul_cq_hndl;\r
260         void              *cq_ul_resources_p;\r
261         const void        *cq_context;\r
262         KDPC                            dpc;\r
263         atomic32_t                      spl_qp_cnt;\r
264 \r
265 } cq_info_t;\r
266 \r
267 typedef struct _ib_qp {\r
268         ENUM_MARK         mark;\r
269         cl_mutex_t        mutex;\r
270         u_int32_t         hca_idx;\r
271         u_int32_t         kernel_mode;\r
272         // mlnx_hob_t        *hob_p;\r
273         HH_hca_hndl_t     hh_hndl;      // For HH direct access */\r
274         HHUL_qp_hndl_t    hhul_qp_hndl;\r
275         IB_wqpn_t         qp_num;       // For direct HH-UL access */\r
276         HH_pd_hndl_t      pd_num;       // For HH-UL direct access */\r
277         IB_port_t         port;         // Valid for special QPs only */\r
278         ib_qp_type_t      qp_type;      // Required for qp_query\r
279         u_int32_t         sq_signaled;  // Required for qp_query\r
280         ib_cq_handle_t          h_sq_cq;\r
281         ib_cq_handle_t          h_rq_cq;\r
282         u_int32_t         sq_size;\r
283         u_int32_t         rq_size;\r
284         VAPI_sr_desc_t    *send_desc_p;\r
285         VAPI_rr_desc_t    *recv_desc_p;\r
286         VAPI_sg_lst_entry_t *send_sge_p;\r
287         VAPI_sg_lst_entry_t *recv_sge_p;\r
288         void              *qp_ul_resources_p;\r
289         const void        *qp_context;\r
290 } qp_info_t;\r
291 \r
292 typedef struct HOBUL_t {\r
293         HH_hca_hndl_t     hh_hndl;                /* For HH direct access */\r
294         HHUL_hca_hndl_t   hhul_hndl;              /* user level HCA resources handle for HH */\r
295         u_int32_t         cq_idx_mask;            /*                                                */\r
296         u_int32_t         qp_idx_mask;            /*                                                */\r
297         u_int32_t         vendor_id;              /* \                                              */\r
298         u_int32_t         device_id;              /*  >  3 items needed for initializing user level */\r
299         void              *hca_ul_resources_p;    /* /                                              */\r
300         MT_size_t         cq_ul_resources_sz;     /* Needed for allocating user resources for CQs  */\r
301         MT_size_t         qp_ul_resources_sz;     /* Needed for allocating user resources for QPs  */\r
302         MT_size_t         pd_ul_resources_sz;     /* Needed for allocating user resources for PDs  */\r
303         u_int32_t         max_cq;                 /* Max num. of CQs - size of following table */\r
304         cq_info_t         *cq_info_tbl;\r
305         u_int32_t         max_qp;                 /* Max num. of QPs - size of following table */\r
306         qp_info_t         *qp_info_tbl;\r
307         u_int32_t         max_pd;                 /* Max num. of PDs - size of following table */\r
308         pd_info_t         *pd_info_tbl;\r
309         u_int32_t         log2_mpt_size;\r
310         atomic32_t        count;\r
311 } mlnx_hobul_t, *mlnx_hobul_hndl_t;\r
312 \r
313 typedef struct _ib_mr {\r
314         ENUM_MARK                               mark;\r
315         ENUM_MR_TYPE                    mr_type;\r
316         u_int64_t                               mr_start;       // TBD: IA64\r
317         u_int64_t                               mr_size;                // TBD: IA64\r
318 //      u_int64_t                               mr_first_page_addr; // TBD : IA64\r
319 //      u_int32_t                               mr_num_pages;\r
320         ib_pd_handle_t                  mr_pd_handle;\r
321         MOSAL_iobuf_t                   mr_iobuf;\r
322         VAPI_mrw_acl_t                  mr_acl;\r
323         VAPI_lkey_t                             mr_lkey;\r
324         MOSAL_protection_ctx_t  mr_prot_ctx;\r
325         MOSAL_mem_perm_t                mr_mosal_perm;\r
326 } mlnx_mro_t;\r
327 \r
328 typedef struct _ib_mw {\r
329         ENUM_MARK         mark;\r
330         u_int32_t         hca_idx;\r
331         u_int32_t         pd_idx;\r
332         u_int32_t         mw_rkey;\r
333 } mlnx_mwo_t;\r
334 \r
335 typedef struct _ib_mcast {\r
336         ENUM_MARK         mark;\r
337         IB_gid_t          mcast_gid;\r
338         u_int32_t         hca_idx;\r
339         u_int32_t         qp_num;\r
340         u_int32_t         kernel_mode;\r
341 } mlnx_mcast_t;\r
342 \r
343 typedef struct _ib_av {\r
344         ENUM_MARK         mark;\r
345         u_int32_t         hca_idx;\r
346         u_int32_t         pd_idx;\r
347         u_int32_t         user_mode;\r
348         HHUL_ud_av_hndl_t h_av;\r
349 } mlnx_avo_t;\r
350 \r
351 typedef mlnx_hob_t *mlnx_hca_h;\r
352 \r
353 // Global Variables\r
354 //extern mlnx_hca_t       mlnx_hca_array[];\r
355 //extern uint32_t         mlnx_num_hca;\r
356 \r
357 extern mlnx_hob_t   mlnx_hob_array[];\r
358 extern mlnx_hobul_t *mlnx_hobul_array[];\r
359 \r
360 // Functions\r
361 void\r
362 setup_ci_interface(\r
363         IN              const   ib_net64_t                                      ca_guid,\r
364                 OUT                     ci_interface_t                          *p_interface );\r
365 \r
366 void\r
367 mlnx_hca_insert(\r
368         IN                              mlnx_hca_t                                      *p_hca );\r
369 \r
370 void\r
371 mlnx_hca_remove(\r
372         IN                              mlnx_hca_t                                      *p_hca );\r
373 \r
374 mlnx_hca_t*\r
375 mlnx_hca_from_guid(\r
376         IN                              ib_net64_t                                      guid );\r
377 \r
378 /*\r
379 void\r
380 mlnx_names_from_guid(\r
381         IN                              ib_net64_t                                      guid,\r
382                 OUT                     char                                            **hca_name_p,\r
383                 OUT                     char                                            **dev_name_p);\r
384 */\r
385 \r
386 cl_status_t\r
387 mlnx_hobs_init( void );\r
388 \r
389 ib_api_status_t\r
390 mlnx_hobs_insert(\r
391         IN                              mlnx_hca_t                                      *p_hca,\r
392                 OUT                     mlnx_hob_t                                      **hob_p);\r
393 \r
394 void\r
395 mlnx_hobs_get_handle(\r
396         IN                              mlnx_hob_t                                      *hob_p,\r
397                 OUT                     HH_hca_hndl_t                           *hndl_p);\r
398 \r
399 ib_api_status_t\r
400 mlnx_hobs_set_cb(\r
401         IN                              mlnx_hob_t                                      *hob_p, \r
402         IN                              ci_completion_cb_t                      comp_cb_p,\r
403         IN                              ci_async_event_cb_t                     async_cb_p,\r
404         IN              const   void* const                                     ib_context);\r
405 \r
406 ib_api_status_t\r
407 mlnx_hobs_get_context(\r
408         IN                              mlnx_hob_t                                      *hob_p,\r
409                 OUT                     void                                            **context_p);\r
410 \r
411 ib_api_status_t\r
412 mlnx_hobs_create_device(\r
413         IN                              mlnx_hob_t                                      *hob_p,\r
414                 OUT                     char*                                           dev_name);\r
415 \r
416 void\r
417 mlnx_hobs_remove(\r
418         IN                              mlnx_hob_t                                      *hob_p);\r
419 \r
420 ib_api_status_t\r
421 mlnx_hobs_lookup(\r
422         IN                              HH_hca_hndl_t                           hndl,\r
423                 OUT                     mlnx_hob_t                                      **hca_p);\r
424 \r
425 mlnx_hobul_t *\r
426 mlnx_hobs_get_hobul(\r
427         IN                              mlnx_hob_t                                      *hob_p);\r
428 \r
429 ib_api_status_t\r
430 mlnx_hobul_new(\r
431         IN                              mlnx_hob_t                                      *hob_p,\r
432         IN                              HH_hca_hndl_t                           hh_hndl,\r
433         IN                              void                                            *resources_p);\r
434 \r
435 void\r
436 mlnx_hobul_get(\r
437         IN                              mlnx_hob_t                                      *hob_p,\r
438                 OUT                     void                                            **resources_p );\r
439 \r
440 void\r
441 mlnx_hobul_delete(\r
442         IN                              mlnx_hob_t                                      *hob_p);\r
443 \r
444 // Conversion Functions\r
445 \r
446 VAPI_mrw_acl_t\r
447 map_ibal_acl(\r
448         IN                              ib_access_t                                     ibal_acl);\r
449 \r
450 ib_access_t\r
451 map_vapi_acl(\r
452         IN                              VAPI_mrw_acl_t                          vapi_acl);\r
453 \r
454 ib_api_status_t\r
455 mlnx_lock_region(\r
456         IN                              mlnx_mro_t                                      *mro_p,\r
457         IN                              boolean_t                                       um_call );\r
458 \r
459 ib_api_status_t\r
460 mlnx_conv_ibal_mr_create(\r
461         IN                              u_int32_t                                       pd_idx,\r
462         IN      OUT                     mlnx_mro_t                                      *mro_p,\r
463         IN                              VAPI_mr_change_t                        change_flags,\r
464         IN                              ib_mr_create_t const            *p_mr_create,\r
465         IN                              boolean_t                                       um_call,\r
466                 OUT                     HH_mr_t                                         *mr_props_p );\r
467 \r
468 ib_api_status_t\r
469 mlnx_conv_ibal_pmr_create(\r
470         IN                              u_int32_t                                       pd_idx,\r
471         IN                              mlnx_mro_t                                      *mro_p,\r
472         IN                              ib_phys_create_t const          *p_pmr_create,\r
473                 OUT                     HH_mr_t                                         *mr_props_p );\r
474 \r
475 void\r
476 mlnx_conv_ibal_av(\r
477         IN                              HH_hca_hndl_t                           hh_hndl,\r
478         IN              const   ib_av_attr_t                            *ibal_av_p,\r
479                 OUT                     VAPI_ud_av_t                            *vapi_av_p);\r
480 \r
481 void\r
482 mlnx_conv_vapi_av(\r
483         IN                              HH_hca_hndl_t                           hh_hndl,\r
484         IN              const   VAPI_ud_av_t                            *vapi_av_p,\r
485                 OUT                     ib_av_attr_t                            *ibal_av_p);\r
486 \r
487 int\r
488 mlnx_map_vapi_cqe_status(\r
489         IN                              VAPI_wc_status_t                        vapi_status);\r
490 \r
491 int\r
492 mlnx_map_vapi_cqe_type(\r
493         IN                              VAPI_cqe_opcode_t                       opcode);\r
494 \r
495 int\r
496 mlnx_map_vapi_rna_type(\r
497         IN                              VAPI_remote_node_addr_type_t    rna);\r
498 \r
499 void\r
500 mlnx_conv_vapi_mr_attr(\r
501         IN                              ib_pd_handle_t                          pd_h,\r
502         IN                              HH_mr_info_t                            *mr_info_p,\r
503                 OUT                     ib_mr_attr_t                            *mr_query_p);\r
504 \r
505 void\r
506 mlnx_conv_bind_req(\r
507         IN                              HHUL_qp_hndl_t                          hhul_qp_hndl,\r
508         IN                              ib_bind_wr_t* const                     p_mw_bind,\r
509                 OUT                     HHUL_mw_bind_t                          *bind_prop_p);\r
510 \r
511 int\r
512 mlnx_map_ibal_qp_type(\r
513         IN                              ib_qp_type_t                            ibal_qpt,\r
514                 OUT                     VAPI_special_qp_t                       *vapi_qp_type_p);\r
515 \r
516 void\r
517 mlnx_conv_qp_create_attr(\r
518         IN              const   ib_qp_create_t                          *create_attr_p,\r
519         IN                              HHUL_qp_init_attr_t                     *init_attr_p,\r
520                 OUT                     VAPI_special_qp_t                       *vapi_qp_type_p);\r
521 \r
522 void\r
523 mlnx_conv_vapi_qp_attr(\r
524         IN                              HH_hca_hndl_t                           hh_hndl,\r
525         IN                              VAPI_qp_attr_t                          *hh_qp_attr_p,\r
526                 OUT                     ib_qp_attr_t                            *qp_attr_p);\r
527 \r
528 ib_api_status_t\r
529 mlnx_conv_qp_modify_attr(\r
530         IN                              HH_hca_hndl_t                           hh_hndl,\r
531         IN                              ib_qp_type_t                            qp_type,\r
532         IN              const   ib_qp_mod_t                                     *modify_attr_p,\r
533                 OUT                     VAPI_qp_attr_t                          *qp_attr_p, \r
534                 OUT                     VAPI_qp_attr_mask_t                     *attr_mask_p);\r
535 \r
536 ib_api_status_t\r
537 mlnx_conv_send_desc(\r
538         IN                              IB_ts_t                                         transport,\r
539         IN              const   ib_send_wr_t                            *ibal_send_wqe_p,\r
540                 OUT                     VAPI_sr_desc_t                          *vapi_send_desc_p);\r
541 \r
542 ib_api_status_t\r
543 mlnx_conv_recv_desc(\r
544         IN              const   ib_recv_wr_t                            *ibal_recv_wqe_p,\r
545                 OUT                     VAPI_rr_desc_t                          *vapi_recv_desc_p);\r
546 \r
547 void\r
548 mlnx_conv_vapi_hca_cap(\r
549         IN                              HH_hca_dev_t                            *hca_info_p,\r
550         IN                              VAPI_hca_cap_t                          *vapi_hca_cap_p,\r
551         IN                              VAPI_hca_port_t                         *vapi_hca_ports,\r
552                 OUT                     ib_ca_attr_t                            *ca_attr_p);\r
553 \r
554 ib_api_status_t\r
555 mlnx_get_hca_pkey_tbl(\r
556         IN                              HH_hca_hndl_t                           hh_hndl,\r
557         IN                              u_int8_t                                        port_num,\r
558         IN                              u_int16_t                                       num_entries,\r
559                 OUT                     void*                                           table);\r
560 \r
561 ib_api_status_t\r
562 mlnx_get_hca_gid_tbl(\r
563         IN                              HH_hca_hndl_t                           hh_hndl,\r
564         IN                              u_int8_t                                        port_num,\r
565         IN                              u_int16_t                                       num_entries,\r
566                 OUT                     void*                                           table);\r
567 \r
568 ib_api_status_t\r
569 mlnx_local_mad (\r
570         IN              const   ib_ca_handle_t                          h_ca,\r
571         IN              const   uint8_t                                         port_num,\r
572         IN              const   ib_mad_t                                        *p_mad_in,\r
573                 OUT                     ib_mad_t                                        *p_mad_out );\r
574 \r
575 void\r
576 mlnx_memory_if(\r
577         IN      OUT                     ci_interface_t                          *p_interface );\r
578 \r
579 void\r
580 mlnx_ecc_if(\r
581         IN      OUT                     ci_interface_t                          *p_interface );\r
582 \r
583 void\r
584 mlnx_direct_if(\r
585         IN      OUT                     ci_interface_t                          *p_interface );\r
586 \r
587 void\r
588 mlnx_mcast_if(\r
589         IN      OUT                     ci_interface_t                          *p_interface );\r
590 \r
591 ib_api_status_t\r
592 fw_access_ctrl(\r
593         IN              const   void* __ptr64                           context,\r
594         IN              const   void* __ptr64* const            handle_array    OPTIONAL,\r
595         IN                              uint32_t                                        num_handles,\r
596         IN                              ib_ci_op_t* const                       p_ci_op,\r
597         IN      OUT                     ci_umv_buf_t                            *p_umv_buf              OPTIONAL);\r
598 \r
599 #endif\r