[MLX4] added support to new device. [mlnx: 4473]
[mirror/winof/.git] / hw / mlx4 / kernel / inc / l2w_pci.h
1 #pragma once
2
3 // ===========================================
4 // LITERALS
5 // ===========================================
6
7 #define DEVID_HERMON_SDR                0x6340  /* 25408 */
8 #define DEVID_HERMON_DDR                0x634a  /* 25418 */
9 #define DEVID_HERMON_ETH                0x6368  /* 25448 */
10 #define DEVID_HERMON_ETH_YATIR          0x6372  /* 25458 */
11 #define DEVID_HERMON_DDR_G2             0x6732  /* 26418 */
12 #define DEVID_HERMON_QDR_G2             0x673c  /* 26428 */
13 #define DEVID_HERMON_ETH_G2             0x6750  /* 26448 */
14 #define DEVID_HERMON_ETH_YATIR_G2               0x675A  /* 26458 */
15 #define DEVID_HERMON_ETH_B0_G2          0x6764  /* 26468 */
16 /* livefish */
17 #define DEVID_HERMON_BD         0x0191  /* 401 */
18
19 /* Types of supported HCA */
20 typedef enum __hca_type {
21         HERMON,                 /* fully functional HCA */
22         LIVEFISH                /* a burning device */
23 } hca_type_t;
24
25 /* vendors */
26 #define PCI_VENDOR_ID_MELLANOX                          0x15b3
27 #define PCI_VENDOR_ID_TOPSPIN                           0x1867
28
29 #define HCA(v, d, t) \
30         { PCI_VENDOR_ID_##v,    DEVID_HERMON_##d, t }
31
32 struct pci_device_id {
33         USHORT          vendor;
34         USHORT          device;
35         hca_type_t      driver_data;
36 };
37
38
39 // ===========================================
40 // TYPES
41 // ===========================================
42
43
44 // ===========================================
45 // MACROS/FUNCTIONS
46 // ===========================================
47
48 NTSTATUS pci_hca_reset( struct pci_dev *pdev);
49
50 /* use shim to implement that */
51 #define mlx4_reset(dev)         pci_hca_reset(dev->pdev)
52
53 // get bar boundaries
54 #define pci_resource_start(dev,bar_num) ((dev)->bar[bar_num >> 1].phys)
55 #define pci_resource_len(dev,bar_num)   ((dev)->bar[bar_num >> 1].size)
56
57 // i/o to registers
58
59 static inline u64 readq(const volatile void __iomem *addr)
60 {
61         //TODO: write atomic implementation of _IO_READ_QWORD and change mthca_doorbell.h
62         u64 val;
63         READ_REGISTER_BUFFER_ULONG((PULONG)(addr), (PULONG)&val, 2 );
64         return val;
65 }
66
67 static inline u32 readl(const volatile void __iomem *addr)
68 {
69         return READ_REGISTER_ULONG((PULONG)(addr));
70 }
71
72 static inline u16 reads(const volatile void __iomem *addr)
73 {
74         return READ_REGISTER_USHORT((PUSHORT)(addr));
75 }
76
77 static inline u8 readb(const volatile void __iomem *addr)
78 {
79         return READ_REGISTER_UCHAR((PUCHAR)(addr));
80 }
81
82 #define __raw_readq             readq
83 #define __raw_readl             readl
84 #define __raw_reads             reads
85 #define __raw_readb             readb
86
87 static inline void writeq(unsigned __int64 val, volatile void __iomem *addr)
88 {
89         //TODO: write atomic implementation of _IO_WRITE_QWORD and change mthca_doorbell.h
90         WRITE_REGISTER_BUFFER_ULONG( (PULONG)(addr), (PULONG)&val, 2 );
91 }
92
93 static inline void writel(unsigned int val, volatile void __iomem *addr)
94 {
95         WRITE_REGISTER_ULONG((PULONG)(addr),val);
96 }
97
98 static inline void writes(unsigned short val, volatile void __iomem *addr)
99 {
100         WRITE_REGISTER_USHORT((PUSHORT)(addr),val);
101 }
102
103 static inline void writeb(unsigned char val, volatile void __iomem *addr)
104 {
105         WRITE_REGISTER_UCHAR((PUCHAR)(addr),val);
106 }
107
108 #define __raw_writeq            writeq
109 #define __raw_writel            writel
110 #define __raw_writes            writes
111 #define __raw_writeb            writeb
112
113