2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <complib/cl_thread.h>
39 #define CMD_POLL_TOKEN 0xffff
42 /* command completed successfully: */
44 /* Internal error (such as a bus error) occurred while processing command: */
45 CMD_STAT_INTERNAL_ERR = 0x01,
46 /* Operation/command not supported or opcode modifier not supported: */
47 CMD_STAT_BAD_OP = 0x02,
48 /* Parameter not supported or parameter out of range: */
49 CMD_STAT_BAD_PARAM = 0x03,
50 /* System not enabled or bad system state: */
51 CMD_STAT_BAD_SYS_STATE = 0x04,
52 /* Attempt to access reserved or unallocaterd resource: */
53 CMD_STAT_BAD_RESOURCE = 0x05,
54 /* Requested resource is currently executing a command, or is otherwise busy: */
55 CMD_STAT_RESOURCE_BUSY = 0x06,
56 /* Required capability exceeds device limits: */
57 CMD_STAT_EXCEED_LIM = 0x08,
58 /* Resource is not in the appropriate state or ownership: */
59 CMD_STAT_BAD_RES_STATE = 0x09,
60 /* Index out of range: */
61 CMD_STAT_BAD_INDEX = 0x0a,
62 /* FW image corrupted: */
63 CMD_STAT_BAD_NVMEM = 0x0b,
64 /* Attempt to modify a QP/EE which is not in the presumed state: */
65 CMD_STAT_BAD_QP_STATE = 0x10,
66 /* Bad segment parameters (Address/Size): */
67 CMD_STAT_BAD_SEG_PARAM = 0x20,
68 /* Memory Region has Memory Windows bound to: */
69 CMD_STAT_REG_BOUND = 0x21,
70 /* HCA local attached memory not present: */
71 CMD_STAT_LAM_NOT_PRE = 0x22,
72 /* Bad management packet (silently discarded): */
73 CMD_STAT_BAD_PKT = 0x30,
74 /* More outstanding CQEs in CQ than new CQ size: */
75 CMD_STAT_BAD_SIZE = 0x40,
76 /* Multi Function device support required: */
77 CMD_STAT_MULTI_FUNC_REQ = 0x50,
78 /* must be the last and have max value */
79 CMD_STAT_SIZE = CMD_STAT_MULTI_FUNC_REQ + 1
83 HCR_IN_PARAM_OFFSET = 0x00,
84 HCR_IN_MODIFIER_OFFSET = 0x08,
85 HCR_OUT_PARAM_OFFSET = 0x0c,
86 HCR_TOKEN_OFFSET = 0x14,
87 HCR_STATUS_OFFSET = 0x18,
96 GO_BIT_TIMEOUT_MSECS = 10000
99 struct mlx4_cmd_context {
100 struct completion done;
107 static int mlx4_status_to_errno(u8 status) {
108 static int trans_table[CMD_STAT_SIZE];
109 static int filled = 0;
112 memset( (char*)trans_table, 0, sizeof(trans_table) );
113 trans_table[CMD_STAT_INTERNAL_ERR] = -EIO;
114 trans_table[CMD_STAT_BAD_OP] = -EPERM;
115 trans_table[CMD_STAT_BAD_PARAM] = -EINVAL;
116 trans_table[CMD_STAT_BAD_SYS_STATE] = -ENXIO;
117 trans_table[CMD_STAT_BAD_RESOURCE] = -EBADF;
118 trans_table[CMD_STAT_RESOURCE_BUSY] = -EBUSY;
119 trans_table[CMD_STAT_EXCEED_LIM] = -ENOMEM;
120 trans_table[CMD_STAT_BAD_RES_STATE] = -EBADF;
121 trans_table[CMD_STAT_BAD_INDEX] = -EBADF;
122 trans_table[CMD_STAT_BAD_NVMEM] = -EFAULT;
123 trans_table[CMD_STAT_BAD_QP_STATE] = -EINVAL;
124 trans_table[CMD_STAT_BAD_SEG_PARAM] = -EFAULT;
125 trans_table[CMD_STAT_REG_BOUND] = -EBUSY;
126 trans_table[CMD_STAT_LAM_NOT_PRE] = -EAGAIN;
127 trans_table[CMD_STAT_BAD_PKT] = -EINVAL;
128 trans_table[CMD_STAT_BAD_SIZE] = -ENOMEM;
129 trans_table[CMD_STAT_MULTI_FUNC_REQ] = -EACCES;
133 if (status >= ARRAY_SIZE(trans_table) ||
134 (status != CMD_STAT_OK && trans_table[status] == 0))
137 return trans_table[status];
140 static int cmd_pending(struct mlx4_dev *dev)
142 u32 status = readl(mlx4_priv(dev)->cmd.hcr + HCR_STATUS_OFFSET);
144 return (status & swab32(1 << HCR_GO_BIT)) ||
145 (mlx4_priv(dev)->cmd.toggle ==
146 !!(status & swab32(1 << HCR_T_BIT)));
149 static int mlx4_cmd_post(struct mlx4_dev *dev, u64 in_param, u64 out_param,
150 u32 in_modifier, u8 op_modifier, u16 op, u16 token,
153 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
154 u32 __iomem *hcr = (u32 __iomem *)cmd->hcr;
158 mutex_lock(&cmd->hcr_mutex);
162 end += msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS);
164 while (cmd_pending(dev)) {
165 if (time_after_eq(jiffies, end))
171 * We use writel (instead of something like memcpy_toio)
172 * because writes of less than 32 bits to the HCR don't work
173 * (and some architectures such as ia64 implement memcpy_toio
174 * in terms of writeb).
176 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), hcr + 0);
177 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), hcr + 1);
178 __raw_writel((__force u32) cpu_to_be32(in_modifier), hcr + 2);
179 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), hcr + 3);
180 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), hcr + 4);
181 __raw_writel((__force u32) cpu_to_be32(token << 16), hcr + 5);
183 /* __raw_writel may not order writes. */
186 __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) |
187 (cmd->toggle << HCR_T_BIT) |
188 (event ? (1 << HCR_E_BIT) : 0) |
189 (op_modifier << HCR_OPMOD_SHIFT) |
193 * Make sure that our HCR writes don't get mixed in with
194 * writes from another CPU starting a FW command.
198 cmd->toggle = cmd->toggle ^ 1;
203 mutex_unlock(&cmd->hcr_mutex);
207 static int mlx4_cmd_poll(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
208 int out_is_imm, u32 in_modifier, u8 op_modifier,
209 u16 op, unsigned long timeout)
211 struct mlx4_priv *priv = mlx4_priv(dev);
212 u8 __iomem *hcr = priv->cmd.hcr;
218 down(&priv->cmd.poll_sem);
220 err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
221 in_modifier, op_modifier, op, CMD_POLL_TOKEN, 0);
225 end = msecs_to_jiffies(timeout) + jiffies;
226 while (cmd_pending(dev) && time_before(jiffies, end))
229 if (cmd_pending(dev)) {
232 do_reset = InterlockedCompareExchange(&dev->reset_pending, 1, 0);
235 status1 = mlx4_reset(dev);
236 if ( !NT_SUCCESS( status1 ) ) {
237 mlx4_err(dev, "Failed to reset HCA, aborting.(status %#x)\n", status1);
240 dev->flags |= MLX4_FLAG_RESET_DRIVER; // bar the device
243 if (dev->pdev->ib_dev)
244 mlx4_dispatch_reset_event(dev->pdev->ib_dev, IB_EVENT_RESET_DRIVER);
251 (u64) be32_to_cpu((__force __be32)
252 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
253 (u64) be32_to_cpu((__force __be32)
254 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET + 4));
256 status = (u8)(be32_to_cpu((__force __be32)__raw_readl(hcr + HCR_STATUS_OFFSET)) >> 24);
257 err = mlx4_status_to_errno(status);
258 if (status && status != 0x50)
259 mlx4_err(dev, "Command failed: op %#hx, status %#02x, errno %d.\n",
263 up(&priv->cmd.poll_sem);
267 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param)
269 struct mlx4_priv *priv = mlx4_priv(dev);
270 struct mlx4_cmd_context *context =
271 &priv->cmd.context[token & priv->cmd.token_mask];
273 /* previously timed out command completing at long last */
274 if (token != context->token)
277 context->result = mlx4_status_to_errno(status);
280 mlx4_err(dev, "Command failed: token %#hx, status %#02x, errno %d.\n",
281 token, status, context->result);
282 context->out_param = out_param;
284 complete(&context->done);
287 static int mlx4_cmd_wait(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
288 int out_is_imm, u32 in_modifier, u8 op_modifier,
289 u16 op, unsigned long timeout)
291 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
292 struct mlx4_cmd_context *context;
294 u64 out_prm = out_param ? *out_param : 0;
297 down(&cmd->event_sem);
298 if ( dev->flags & MLX4_FLAG_RESET_DRIVER ) {
300 mlx4_warn(dev, "mlx4_cmd_wait: Command %02x is skipped because the card is stuck \n", op);
303 spin_lock(&cmd->context_lock);
304 BUG_ON(cmd->free_head < 0);
305 context = &cmd->context[cmd->free_head];
306 context->token += cmd->token_mask + 1;
307 cmd->free_head = context->next;
308 spin_unlock(&cmd->context_lock);
310 init_completion(&context->done);
312 mlx4_cmd_post(dev, in_param, out_prm,
313 in_modifier, op_modifier, op, context->token, 1);
315 if (wait_for_completion_timeout(&context->done, msecs_to_jiffies(timeout))) {
316 if (!context->done.done) {
320 mlx4_err(dev, "mlx4_cmd_wait: Command %02x completed with timeout after %d msecs \n",
323 /* for enabling busy-wait loop, add MLX4_FLAG_BUSY_WAIT (0x8000) to dev->flags */
325 u32 wait_ms =2000; /* wait interval in msecs */
326 if (!(dev->flags & MLX4_FLAG_BUSY_WAIT))
328 cl_thread_suspend( wait_ms );
330 do_reset = InterlockedCompareExchange(&dev->reset_pending, 1, 0);
332 NTSTATUS status = mlx4_reset(dev);
333 if ( !NT_SUCCESS( status ) ) {
334 mlx4_err(dev, "Failed to reset HCA, aborting.(status %#x)\n", status);
337 dev->flags |= MLX4_FLAG_RESET_DRIVER; // bar the device
340 /* try to solve the problem */
341 if (dev->pdev->ib_dev)
342 mlx4_dispatch_reset_event(dev->pdev->ib_dev, IB_EVENT_RESET_DRIVER);
346 mlx4_err(dev, "mlx4_cmd_wait: Unexpected end of waiting for a comand \n");
351 err = context->result;
357 *out_param = context->out_param;
360 spin_lock(&cmd->context_lock);
361 context->next = cmd->free_head;
362 cmd->free_head = (int)(context - cmd->context);
363 spin_unlock(&cmd->context_lock);
370 static char *__print_opcode(int opcode)
374 case MLX4_CMD_SYS_EN : str = "MLX4_CMD_SYS_EN "; break;
375 case MLX4_CMD_SYS_DIS: str = "MLX4_CMD_SYS_DIS"; break;
376 case MLX4_CMD_MAP_FA : str = "MLX4_CMD_MAP_FA "; break;
377 case MLX4_CMD_UNMAP_FA: str = "MLX4_CMD_UNMAP_FA"; break;
378 case MLX4_CMD_RUN_FW : str = "MLX4_CMD_RUN_FW "; break;
379 case MLX4_CMD_MOD_STAT_CFG: str = "MLX4_CMD_MOD_STAT_CFG"; break;
380 case MLX4_CMD_QUERY_DEV_CAP: str = "MLX4_CMD_QUERY_DEV_CAP"; break;
381 case MLX4_CMD_QUERY_FW: str = "MLX4_CMD_QUERY_FW"; break;
382 case MLX4_CMD_ENABLE_LAM: str = "MLX4_CMD_ENABLE_LAM"; break;
383 case MLX4_CMD_DISABLE_LAM: str = "MLX4_CMD_DISABLE_LAM"; break;
384 case MLX4_CMD_QUERY_DDR: str = "MLX4_CMD_QUERY_DDR"; break;
385 case MLX4_CMD_QUERY_ADAPTER: str = "MLX4_CMD_QUERY_ADAPTER"; break;
386 case MLX4_CMD_INIT_HCA: str = "MLX4_CMD_INIT_HCA"; break;
387 case MLX4_CMD_CLOSE_HCA: str = "MLX4_CMD_CLOSE_HCA"; break;
388 case MLX4_CMD_INIT_PORT: str = "MLX4_CMD_INIT_PORT"; break;
389 case MLX4_CMD_CLOSE_PORT: str = "MLX4_CMD_CLOSE_PORT"; break;
390 case MLX4_CMD_QUERY_HCA: str = "MLX4_CMD_QUERY_HCA"; break;
391 case MLX4_CMD_QUERY_PORT: str = "MLX4_CMD_QUERY_PORT"; break;
392 case MLX4_CMD_SET_PORT: str = "MLX4_CMD_SET_PORT"; break;
393 case MLX4_CMD_ACCESS_DDR: str = "MLX4_CMD_ACCESS_DDR"; break;
394 case MLX4_CMD_MAP_ICM: str = "MLX4_CMD_MAP_ICM"; break;
395 case MLX4_CMD_UNMAP_ICM: str = "MLX4_CMD_UNMAP_ICM"; break;
396 case MLX4_CMD_MAP_ICM_AUX: str = "MLX4_CMD_MAP_ICM_AUX"; break;
397 case MLX4_CMD_UNMAP_ICM_AUX: str = "MLX4_CMD_UNMAP_ICM_AUX"; break;
398 case MLX4_CMD_SET_ICM_SIZE: str = "MLX4_CMD_SET_ICM_SIZE"; break;
399 case MLX4_CMD_SW2HW_MPT: str = "MLX4_CMD_SW2HW_MPT"; break;
400 case MLX4_CMD_QUERY_MPT: str = "MLX4_CMD_QUERY_MPT"; break;
401 case MLX4_CMD_HW2SW_MPT: str = "MLX4_CMD_HW2SW_MPT"; break;
402 case MLX4_CMD_READ_MTT: str = "MLX4_CMD_READ_MTT"; break;
403 case MLX4_CMD_WRITE_MTT: str = "MLX4_CMD_WRITE_MTT"; break;
404 case MLX4_CMD_SYNC_TPT: str = "MLX4_CMD_SYNC_TPT"; break;
405 case MLX4_CMD_MAP_EQ : str = "MLX4_CMD_MAP_EQ "; break;
406 case MLX4_CMD_SW2HW_EQ: str = "MLX4_CMD_SW2HW_EQ"; break;
407 case MLX4_CMD_HW2SW_EQ: str = "MLX4_CMD_HW2SW_EQ"; break;
408 case MLX4_CMD_QUERY_EQ: str = "MLX4_CMD_QUERY_EQ"; break;
409 case MLX4_CMD_SW2HW_CQ: str = "MLX4_CMD_SW2HW_CQ"; break;
410 case MLX4_CMD_HW2SW_CQ: str = "MLX4_CMD_HW2SW_CQ"; break;
411 case MLX4_CMD_QUERY_CQ: str = "MLX4_CMD_QUERY_CQ"; break;
412 case MLX4_CMD_MODIFY_CQ: str = "MLX4_CMD_MODIFY_CQ"; break;
413 case MLX4_CMD_SW2HW_SRQ: str = "MLX4_CMD_SW2HW_SRQ"; break;
414 case MLX4_CMD_HW2SW_SRQ: str = "MLX4_CMD_HW2SW_SRQ"; break;
415 case MLX4_CMD_QUERY_SRQ: str = "MLX4_CMD_QUERY_SRQ"; break;
416 case MLX4_CMD_ARM_SRQ: str = "MLX4_CMD_ARM_SRQ"; break;
417 case MLX4_CMD_RST2INIT_QP: str = "MLX4_CMD_RST2INIT_QP"; break;
418 case MLX4_CMD_INIT2RTR_QP: str = "MLX4_CMD_INIT2RTR_QP"; break;
419 case MLX4_CMD_RTR2RTS_QP: str = "MLX4_CMD_RTR2RTS_QP"; break;
420 case MLX4_CMD_RTS2RTS_QP: str = "MLX4_CMD_RTS2RTS_QP"; break;
421 case MLX4_CMD_SQERR2RTS_QP: str = "MLX4_CMD_SQERR2RTS_QP"; break;
422 case MLX4_CMD_2ERR_QP: str = "MLX4_CMD_2ERR_QP"; break;
423 case MLX4_CMD_RTS2SQD_QP: str = "MLX4_CMD_RTS2SQD_QP"; break;
424 case MLX4_CMD_SQD2SQD_QP: str = "MLX4_CMD_SQD2SQD_QP"; break;
425 case MLX4_CMD_SQD2RTS_QP: str = "MLX4_CMD_SQD2RTS_QP"; break;
426 case MLX4_CMD_2RST_QP: str = "MLX4_CMD_2RST_QP"; break;
427 case MLX4_CMD_QUERY_QP: str = "MLX4_CMD_QUERY_QP"; break;
428 case MLX4_CMD_INIT2INIT_QP: str = "MLX4_CMD_INIT2INIT_QP"; break;
429 case MLX4_CMD_SUSPEND_QP: str = "MLX4_CMD_SUSPEND_QP"; break;
430 case MLX4_CMD_UNSUSPEND_QP: str = "MLX4_CMD_UNSUSPEND_QP"; break;
431 case MLX4_CMD_CONF_SPECIAL_QP: str = "MLX4_CMD_CONF_SPECIAL_QP"; break;
432 case MLX4_CMD_MAD_IFC: str = "MLX4_CMD_MAD_IFC"; break;
433 case MLX4_CMD_READ_MCG: str = "MLX4_CMD_READ_MCG"; break;
434 case MLX4_CMD_WRITE_MCG: str = "MLX4_CMD_WRITE_MCG"; break;
435 case MLX4_CMD_MGID_HASH: str = "MLX4_CMD_MGID_HASH"; break;
436 case MLX4_CMD_DIAG_RPRT: str = "MLX4_CMD_DIAG_RPRT"; break;
437 case MLX4_CMD_NOP : str = "MLX4_CMD_NOP "; break;
438 case MLX4_CMD_QUERY_DEBUG_MSG: str = "MLX4_CMD_QUERY_DEBUG_MSG"; break;
439 case MLX4_CMD_SET_DEBUG_MSG: str = "MLX4_CMD_SET_DEBUG_MSG"; break;
444 int __mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
445 int out_is_imm, u32 in_modifier, u8 op_modifier,
446 u16 op, unsigned long timeout)
449 mlx4_err(dev, "op %s, ev %d, in_param %#I64x, in_param %#I64x, out_is_imm %d, in_modifier %#x, op_modifier %d\n",
450 __print_opcode(op), mlx4_priv(dev)->cmd.use_events, in_param, out_param,
451 out_is_imm, in_modifier, (int)op_modifier);
454 if ( mlx4_is_barred(dev) )
457 if (mlx4_priv(dev)->cmd.use_events)
458 return mlx4_cmd_wait(dev, in_param, out_param, out_is_imm,
459 in_modifier, op_modifier, op, timeout);
461 return mlx4_cmd_poll(dev, in_param, out_param, out_is_imm,
462 in_modifier, op_modifier, op, timeout);
464 EXPORT_SYMBOL_GPL(__mlx4_cmd);
466 int mlx4_cmd_init(struct mlx4_dev *dev)
468 struct mlx4_priv *priv = mlx4_priv(dev);
470 mutex_init(&priv->cmd.hcr_mutex);
471 sema_init(&priv->cmd.poll_sem, 1);
472 priv->cmd.use_events = 0;
473 priv->cmd.toggle = 1;
475 priv->cmd.hcr = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_HCR_BASE,
477 if (!priv->cmd.hcr) {
478 mlx4_err(dev, "Couldn't map command register.");
482 priv->cmd.pool = pci_pool_create("mlx4_cmd", dev->pdev,
484 MLX4_MAILBOX_SIZE, 0);
485 if (!priv->cmd.pool) {
486 iounmap(priv->cmd.hcr, MLX4_HCR_SIZE);
493 void mlx4_cmd_cleanup(struct mlx4_dev *dev)
495 struct mlx4_priv *priv = mlx4_priv(dev);
497 pci_pool_destroy(priv->cmd.pool);
498 iounmap(priv->cmd.hcr, MLX4_HCR_SIZE);
502 * Switch to using events to issue FW commands (can only be called
503 * after event queue for command events has been initialized).
505 int mlx4_cmd_use_events(struct mlx4_dev *dev)
507 struct mlx4_priv *priv = mlx4_priv(dev);
510 priv->cmd.context = kmalloc(priv->cmd.max_cmds *
511 sizeof (struct mlx4_cmd_context),
513 if (!priv->cmd.context)
516 for (i = 0; i < priv->cmd.max_cmds; ++i) {
517 priv->cmd.context[i].token = (u16)i;
518 priv->cmd.context[i].next = i + 1;
521 priv->cmd.context[priv->cmd.max_cmds - 1].next = -1;
522 priv->cmd.free_head = 0;
524 sema_init(&priv->cmd.event_sem, priv->cmd.max_cmds);
525 spin_lock_init(&priv->cmd.context_lock);
527 for (priv->cmd.token_mask = 1;
528 priv->cmd.token_mask < priv->cmd.max_cmds;
529 priv->cmd.token_mask <<= 1)
531 --priv->cmd.token_mask;
533 priv->cmd.use_events = 1;
535 down(&priv->cmd.poll_sem);
541 * Switch back to polling (used when shutting down the device)
543 void mlx4_cmd_use_polling(struct mlx4_dev *dev)
545 struct mlx4_priv *priv = mlx4_priv(dev);
548 priv->cmd.use_events = 0;
550 for (i = 0; i < priv->cmd.max_cmds; ++i)
551 down(&priv->cmd.event_sem);
553 kfree(priv->cmd.context);
555 up(&priv->cmd.poll_sem);
558 struct mlx4_cmd_mailbox *mlx4_alloc_cmd_mailbox(struct mlx4_dev *dev)
560 struct mlx4_cmd_mailbox *mailbox;
562 if ( mlx4_is_barred(dev) )
563 return ERR_PTR(-EFAULT);
565 mailbox = kmalloc(sizeof *mailbox, GFP_KERNEL);
567 return ERR_PTR(-ENOMEM);
569 mailbox->buf = pci_pool_alloc(mlx4_priv(dev)->cmd.pool, GFP_KERNEL,
573 return ERR_PTR(-ENOMEM);
578 EXPORT_SYMBOL_GPL(mlx4_alloc_cmd_mailbox);
580 void mlx4_free_cmd_mailbox(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox)
585 pci_pool_free(mlx4_priv(dev)->cmd.pool, mailbox->buf, mailbox->dma);
588 EXPORT_SYMBOL_GPL(mlx4_free_cmd_mailbox);
590 // This is the interface version of this function
591 int imlx4_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param, int out_is_imm,
592 u32 in_modifier, u8 op_modifier, u16 op, unsigned long timeout)
594 return __mlx4_cmd(dev, in_param, out_param, out_is_imm, in_modifier,
595 op_modifier, op, timeout);