2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
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11 * without modification, are permitted provided that the following
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15 * copyright notice, this list of conditions and the following
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21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
37 MLX4_FLAG_MSI_X = 1 << 0,
38 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
39 MLX4_FLAG_NOT_PRIME = 1 << 2,
40 MLX4_FLAG_LIVEFISH = 1 << 10,
41 MLX4_FLAG_RESET_CLIENT = 1 << 11,
42 MLX4_FLAG_RESET_DRIVER = 1 << 12,
43 MLX4_FLAG_RESET_STARTED = 1 << 13,
44 MLX4_FLAG_BUSY_WAIT = 1 << 14
52 MLX4_BOARD_ID_LEN = 64
56 MLX4_DEV_CAP_FLAG_RC = 1 << 0,
57 MLX4_DEV_CAP_FLAG_UC = 1 << 1,
58 MLX4_DEV_CAP_FLAG_UD = 1 << 2,
59 MLX4_DEV_CAP_FLAG_SRQ = 1 << 6,
60 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1 << 7,
61 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1 << 8,
62 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1 << 9,
63 MLX4_DEV_CAP_FLAG_DPDP = 1 << 12,
64 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1 << 16,
65 MLX4_DEV_CAP_FLAG_APM = 1 << 17,
66 MLX4_DEV_CAP_FLAG_ATOMIC = 1 << 18,
67 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1 << 19,
68 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1 << 20,
69 MLX4_DEV_CAP_FLAG_UD_MCAST = 1 << 21
73 MLX4_EVENT_TYPE_COMP = 0x00,
74 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
75 MLX4_EVENT_TYPE_COMM_EST = 0x02,
76 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
77 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
78 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
79 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
80 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
81 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
82 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
83 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
84 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
85 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
86 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
87 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
88 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
89 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
90 MLX4_EVENT_TYPE_CMD = 0x0a
94 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
95 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
99 MLX4_PERM_LOCAL_READ = 1 << 10,
100 MLX4_PERM_LOCAL_WRITE = 1 << 11,
101 MLX4_PERM_REMOTE_READ = 1 << 12,
102 MLX4_PERM_REMOTE_WRITE = 1 << 13,
103 MLX4_PERM_ATOMIC = 1 << 14
107 MLX4_OPCODE_NOP = 0x00,
108 MLX4_OPCODE_SEND_INVAL = 0x01,
109 MLX4_OPCODE_RDMA_WRITE = 0x08,
110 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
111 MLX4_OPCODE_SEND = 0x0a,
112 MLX4_OPCODE_SEND_IMM = 0x0b,
113 MLX4_OPCODE_LSO = 0x0e,
114 MLX4_OPCODE_RDMA_READ = 0x10,
115 MLX4_OPCODE_ATOMIC_CS = 0x11,
116 MLX4_OPCODE_ATOMIC_FA = 0x12,
117 MLX4_OPCODE_ATOMIC_MASK_CS = 0x14,
118 MLX4_OPCODE_ATOMIC_MASK_FA = 0x15,
119 MLX4_OPCODE_BIND_MW = 0x18,
120 MLX4_OPCODE_FMR = 0x19,
121 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
122 MLX4_OPCODE_CONFIG_CMD = 0x1f,
124 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
125 MLX4_RECV_OPCODE_SEND = 0x01,
126 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
127 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
129 MLX4_CQE_OPCODE_ERROR = 0x1e,
130 MLX4_CQE_OPCODE_RESIZE = 0x16,
134 MLX4_STAT_RATE_OFFSET = 5
138 MLX4_QP_REGION_FW = 0,
139 MLX4_QP_REGION_ETH_ADDR,
140 MLX4_QP_REGION_FC_ADDR,
141 MLX4_QP_REGION_FC_EXCH,
142 MLX4_QP_REGION_COUNT /* Must be last */
146 MLX4_NUM_FEXCH = 64 * 1024,
153 int vl_cap[MLX4_MAX_PORTS + 1];
154 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
155 u64 def_mac[MLX4_MAX_PORTS + 1];
156 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
157 int gid_table_len[MLX4_MAX_PORTS + 1];
158 int pkey_table_len[MLX4_MAX_PORTS + 1];
159 int local_ca_ack_delay;
162 int bf_regs_per_page;
169 int max_qp_init_rdma;
170 int max_qp_dest_rdma;
183 int fmr_reserved_mtts;
197 u16 stat_rate_support;
198 u8 port_width_cap[MLX4_MAX_PORTS + 1];
200 int reserved_qps_cnt[MLX4_QP_REGION_COUNT];
201 int reserved_qps_base[MLX4_QP_REGION_COUNT];
205 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
206 int reserved_fexch_mpts_base;
209 struct mlx4_buf_list {
214 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
217 struct mlx4_db_pgdir {
218 struct list_head list;
219 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
220 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
221 unsigned long *bits[2];
228 struct mlx4_db_pgdir *pgdir;
242 struct mlx4_buf_list direct;
243 struct mlx4_buf_list *page_list;
250 struct mlx4_hwq_resources {
268 struct mlx4_mpt_entry *mpt;
270 dma_addr_t dma_handle;
283 void (*comp) (struct mlx4_cq *);
284 void (*event) (struct mlx4_cq *, enum mlx4_event);
286 struct mlx4_uar *uar;
298 struct completion free;
306 void (*event) (struct mlx4_qp *, enum mlx4_event);
311 struct completion free;
315 void (*event) (struct mlx4_srq *, enum mlx4_event);
323 struct completion free;
335 __be32 sl_tclass_flowlabel;
339 #define MLX4_DEV_SIGNATURE 0xf1b34a6e
341 struct mlx4_dev_params {
342 enum mlx4_port_type mod_port_type[MLX4_MAX_PORTS];
345 static inline void mlx4_copy_dev_params(
346 struct mlx4_dev_params *dst,
347 struct mlx4_dev_params *src)
354 struct pci_dev *pdev;
357 struct mlx4_caps caps;
358 struct radix_tree_root qp_table_tree;
360 char board_id[MLX4_BOARD_ID_LEN];
361 struct mlx4_dev_params dev_params;
364 struct mlx4_init_port_param {
378 static inline void mlx4_query_steer_cap(struct mlx4_dev *dev, int *log_mac,
379 int *log_vlan, int *log_prio)
381 *log_mac = dev->caps.log_num_macs;
382 *log_vlan = dev->caps.log_num_vlans;
383 *log_prio = dev->caps.log_num_prios;
386 static inline u32 mlx4_get_ports_of_type(struct mlx4_dev *dev,
387 enum mlx4_port_type ptype)
392 for (i = 1; i <= dev->caps.num_ports; ++i) {
393 if (dev->caps.port_type[i] == ptype)
399 #define foreach_port(port, bitmap) \
400 for ((port) = 1; (port) <= MLX4_MAX_PORTS; ++(port)) \
401 if (bitmap & 1 << ((port)-1))
403 static inline int mlx4_get_fexch_mpts_base(struct mlx4_dev *dev)
405 return dev->caps.reserved_fexch_mpts_base;
408 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
409 struct mlx4_buf *buf);
410 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
412 int mlx4_db_alloc(struct mlx4_dev *dev,
413 struct mlx4_db *db, int order);
415 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
417 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
418 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
420 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
421 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
423 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
424 struct mlx4_mtt *mtt);
425 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
426 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
428 int mlx4_mr_alloc_reserved(struct mlx4_dev *dev, u32 mridx, u32 pd,
429 u64 iova, u64 size, u32 access, int npages,
430 int page_shift, struct mlx4_mr *mr);
431 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
432 int npages, int page_shift, struct mlx4_mr *mr);
433 void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
434 void mlx4_mr_free_reserved(struct mlx4_dev *dev, struct mlx4_mr *mr);
435 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
436 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
437 int start_index, int npages, u64 *page_list);
438 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
439 struct mlx4_buf *buf);
443 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
444 int size, int max_direct);
445 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
448 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
449 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
450 unsigned vector, int collapsed);
451 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
453 struct mlx4_cq_context;
454 int mlx4_cq_modify(struct mlx4_dev *dev, struct mlx4_cq *cq,
455 struct mlx4_cq_context *context, int modify);
457 static inline void mlx4_cq_arm(struct mlx4_cq *cq, u32 cmd,
458 void __iomem *uar_page,
459 spinlock_t *doorbell_lock);
463 struct mlx4_qp_context;
465 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, u32 *base);
466 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
467 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp);
468 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
470 int mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
471 enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state,
472 struct mlx4_qp_context *context, enum mlx4_qp_optpar optpar,
473 int sqd_event, struct mlx4_qp *qp);
476 int mlx4_qp_to_ready(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
477 struct mlx4_qp_context *context,
478 struct mlx4_qp *qp, enum mlx4_qp_state *qp_state);
480 void mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp);
483 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcd,
484 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
485 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
487 void mlx4_srq_invalidate(struct mlx4_dev *dev, struct mlx4_srq *srq);
488 void mlx4_srq_remove(struct mlx4_dev *dev, struct mlx4_srq *srq);
490 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
491 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
493 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
494 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
496 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16]);
497 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16]);
499 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *index);
500 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, int index);
501 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
502 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index);
504 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
505 int npages, u64 iova, u32 *lkey, u32 *rkey);
506 int mlx4_map_phys_fmr_fbo(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
507 u64 *page_list, int npages, u64 iova,
508 u32 fbo, u32 len, u32 *lkey, u32 *rkey);
509 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
510 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
511 int mlx4_fmr_alloc_reserved(struct mlx4_dev *dev, u32 mridx, u32 pd,
512 u32 access, int max_pages, int max_maps,
513 u8 page_shift, struct mlx4_fmr *fmr);
514 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
515 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
516 u32 *lkey, u32 *rkey);
517 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
518 int mlx4_fmr_free_reserved(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
519 int mlx4_SYNC_TPT(struct mlx4_dev *dev);
521 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int reset_qkey_viols,
524 #endif /* MLX4_DEVICE_H */