3326cad929389775fd6b27416561e99f777bf2bb
[mirror/winof/.git] / hw / mlx4 / kernel / inc / l2w_pci.h
1 #pragma once
2
3 // ===========================================
4 // LITERALS
5 // ===========================================
6
7 #define DEVID_HERMON_SDR                0x6340  /* 25408 */
8 #define DEVID_HERMON_DDR                0x634a  /* 25418 */
9 #define DEVID_HERMON_ETH                0x6368  /* 25448 */
10 #define DEVID_HERMON_ETH_YATIR          0x6372  /* 25458 */
11 #define DEVID_HERMON_DDR_G2             0x6732  /* 26418 */
12 #define DEVID_HERMON_QDR_G2             0x673c  /* 26428 */
13 #define DEVID_HERMON_ETH_G2             0x6750  /* 26448 */
14 #define DEVID_HERMON_ETH_YATIR_G2               0x675A  /* 26458 */
15 #define DEVID_HERMON_ETH_B0_G2          0x6764  /* 26468 */
16 #define DEVID_HERMON_ETH_B0_40Gb_G2             0x676E  /* 26478 */
17 /* livefish */
18 #define DEVID_HERMON_BD         0x0191  /* 401 */
19
20 /* Types of supported HCA */
21 typedef enum __hca_type {
22         HERMON,                 /* fully functional HCA */
23         LIVEFISH                /* a burning device */
24 } hca_type_t;
25
26 /* vendors */
27 #define PCI_VENDOR_ID_MELLANOX                          0x15b3
28 #define PCI_VENDOR_ID_TOPSPIN                           0x1867
29
30 #define HCA(v, d, t) \
31         { PCI_VENDOR_ID_##v,    DEVID_HERMON_##d, t }
32
33 struct pci_device_id {
34         USHORT          vendor;
35         USHORT          device;
36         hca_type_t      driver_data;
37 };
38
39
40 // ===========================================
41 // TYPES
42 // ===========================================
43
44
45 // ===========================================
46 // MACROS/FUNCTIONS
47 // ===========================================
48
49 NTSTATUS pci_hca_reset( struct pci_dev *pdev);
50
51 /* use shim to implement that */
52 #define mlx4_reset(dev)         pci_hca_reset(dev->pdev)
53
54 // get bar boundaries
55 #define pci_resource_start(dev,bar_num) ((dev)->bar[bar_num >> 1].phys)
56 #define pci_resource_len(dev,bar_num)   ((dev)->bar[bar_num >> 1].size)
57
58 // i/o to registers
59
60 static inline u64 readq(const volatile void __iomem *addr)
61 {
62         //TODO: write atomic implementation of _IO_READ_QWORD and change mthca_doorbell.h
63         u64 val;
64         READ_REGISTER_BUFFER_ULONG((PULONG)(addr), (PULONG)&val, 2 );
65         return val;
66 }
67
68 static inline u32 readl(const volatile void __iomem *addr)
69 {
70         return READ_REGISTER_ULONG((PULONG)(addr));
71 }
72
73 static inline u16 reads(const volatile void __iomem *addr)
74 {
75         return READ_REGISTER_USHORT((PUSHORT)(addr));
76 }
77
78 static inline u8 readb(const volatile void __iomem *addr)
79 {
80         return READ_REGISTER_UCHAR((PUCHAR)(addr));
81 }
82
83 #define __raw_readq             readq
84 #define __raw_readl             readl
85 #define __raw_reads             reads
86 #define __raw_readb             readb
87
88 static inline void writeq(unsigned __int64 val, volatile void __iomem *addr)
89 {
90         //TODO: write atomic implementation of _IO_WRITE_QWORD and change mthca_doorbell.h
91         WRITE_REGISTER_BUFFER_ULONG( (PULONG)(addr), (PULONG)&val, 2 );
92 }
93
94 static inline void writel(unsigned int val, volatile void __iomem *addr)
95 {
96         WRITE_REGISTER_ULONG((PULONG)(addr),val);
97 }
98
99 static inline void writes(unsigned short val, volatile void __iomem *addr)
100 {
101         WRITE_REGISTER_USHORT((PUSHORT)(addr),val);
102 }
103
104 static inline void writeb(unsigned char val, volatile void __iomem *addr)
105 {
106         WRITE_REGISTER_UCHAR((PUCHAR)(addr),val);
107 }
108
109 #define __raw_writeq            writeq
110 #define __raw_writel            writel
111 #define __raw_writes            writes
112 #define __raw_writeb            writeb
113
114